diff --git a/CMakeLists.txt b/CMakeLists.txt index 28fb650d4..54d93fcd8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -572,6 +572,7 @@ if(CAPSTONE_RISCV_SUPPORT) arch/RISCV/RISCVGenRegisterInfo.inc arch/RISCV/RISCVGenSubtargetInfo.inc arch/RISCV/RISCVMappingInsn.inc + arch/RISCV/RISCVMappingInsnOp.inc ) set(TEST_SOURCES ${TEST_SOURCES} test_riscv.c) endif() diff --git a/Mapping.c b/Mapping.c index 6e9ececf0..2f871273d 100644 --- a/Mapping.c +++ b/Mapping.c @@ -338,6 +338,7 @@ DEFINE_get_detail_op(aarch64, AArch64); DEFINE_get_detail_op(alpha, Alpha); DEFINE_get_detail_op(hppa, HPPA); DEFINE_get_detail_op(loongarch, LoongArch); +DEFINE_get_detail_op(riscv, RISCV); /// Returns true if for this architecture the /// alias operands should be filled. diff --git a/Mapping.h b/Mapping.h index 0daa2af4a..3efd3f3ca 100644 --- a/Mapping.h +++ b/Mapping.h @@ -138,6 +138,7 @@ DECL_get_detail_op(aarch64, AArch64); DECL_get_detail_op(alpha, Alpha); DECL_get_detail_op(hppa, HPPA); DECL_get_detail_op(loongarch, LoongArch); +DECL_get_detail_op(riscv, RISCV); /// Increments the detail->arch.op_count by one. #define DEFINE_inc_detail_op_count(arch, ARCH) \ @@ -167,6 +168,8 @@ DEFINE_inc_detail_op_count(hppa, HPPA); DEFINE_dec_detail_op_count(hppa, HPPA); DEFINE_inc_detail_op_count(loongarch, LoongArch); DEFINE_dec_detail_op_count(loongarch, LoongArch); +DEFINE_inc_detail_op_count(riscv, RISCV); +DEFINE_dec_detail_op_count(riscv, RISCV); /// Returns true if a memory operand is currently edited. static inline bool doing_mem(const MCInst *MI) @@ -195,6 +198,7 @@ DEFINE_get_arch_detail(aarch64, AArch64); DEFINE_get_arch_detail(alpha, Alpha); DEFINE_get_arch_detail(hppa, HPPA); DEFINE_get_arch_detail(loongarch, LoongArch); +DEFINE_get_arch_detail(riscv, RISCV); static inline bool detail_is_set(const MCInst *MI) { diff --git a/arch/Alpha/AlphaMapping.c b/arch/Alpha/AlphaMapping.c index 2bc18671c..48c0dc70e 100644 --- a/arch/Alpha/AlphaMapping.c +++ b/arch/Alpha/AlphaMapping.c @@ -23,7 +23,7 @@ static const insn_map insns[] = { #include "AlphaGenCSMappingInsn.inc" }; -const map_insn_ops insn_operands[] = { +static const map_insn_ops insn_operands[] = { #include "AlphaGenCSMappingInsnOp.inc" }; diff --git a/arch/RISCV/RISCVDisassembler.c b/arch/RISCV/RISCVDisassembler.c index bf7e6e01e..4b81da2aa 100644 --- a/arch/RISCV/RISCVDisassembler.c +++ b/arch/RISCV/RISCVDisassembler.c @@ -26,6 +26,7 @@ #include "../../MCRegisterInfo.h" #include "../../MCDisassembler.h" #include "../../MathExtras.h" +#include "../../Mapping.h" #include "RISCVBaseInfo.h" #include "RISCVDisassembler.h" @@ -322,16 +323,36 @@ static void markLSInsn(MCInst *MI, uint32_t in) st 0100011 = 0x23 F/D ld 0000111 = 0x07 st 0100111 = 0x27 + st 0101111 = 0x2f */ #define MASK_LS_INSN 0x0000007f uint32_t opcode = in & MASK_LS_INSN; if (0 == (opcode ^ 0x03) || 0 == (opcode ^ 0x07) || - 0 == (opcode ^ 0x23) || 0 == (opcode ^ 0x27)) + 0 == (opcode ^ 0x23) || 0 == (opcode ^ 0x27) || + 0 == (opcode ^ 0x2f)) MI->flat_insn->detail->riscv.need_effective_addr = true; #undef MASK_LS_INSN return; } +static void markCLSInsn(MCInst *MI, uint32_t in) +{ + // Unfortunately there is no obvious pattern in terms of RISC-V C instructions + // Thus, we compare the instruction IDs to see if it is a load/store instruction + unsigned id = MCInst_getOpcode(MI); + if (id == RISCV_C_FLD || id == RISCV_C_LW || + id == RISCV_C_FLW || id == RISCV_C_LD || + id == RISCV_C_FSD || id == RISCV_C_SW || + id == RISCV_C_FSW || id == RISCV_C_SD || + id == RISCV_C_FLDSP || id == RISCV_C_LWSP || + id == RISCV_C_FLWSP || id == RISCV_C_LDSP || + id == RISCV_C_FSDSP || id == RISCV_C_SWSP || + id == RISCV_C_FSWSP || id == RISCV_C_SDSP) { + RISCV_get_detail(MI)->need_effective_addr = true; + } + return; +} + static DecodeStatus RISCVDisassembler_getInstruction(int mode, MCInst *MI, const uint8_t *code, size_t code_len, uint16_t *Size, uint64_t Address, @@ -382,6 +403,12 @@ static DecodeStatus RISCVDisassembler_getInstruction(int mode, MCInst *MI, init_MI_insn_detail(MI); // Calling the auto-generated decoder function. Result = decodeInstruction(DecoderTable16, MI, Inst, Address, MRI, mode); + // Now we need mark what instruction need fix effective address output. + // Note that we mark it AFTER the instruction is decoded + // This is because there is no obvious pattern in terms of RISC-V C instructions + // So we compare the instruction IDs one by one + if (detail_is_set(MI)) + markCLSInsn(MI, Inst); *Size = 2; } diff --git a/arch/RISCV/RISCVInstPrinter.c b/arch/RISCV/RISCVInstPrinter.c index 028851f55..feb7e3d74 100644 --- a/arch/RISCV/RISCVInstPrinter.c +++ b/arch/RISCV/RISCVInstPrinter.c @@ -24,6 +24,7 @@ #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "../../utils.h" +#include "../../Mapping.h" #include "RISCVMapping.h" //#include "RISCVDisassembler.h" @@ -54,28 +55,180 @@ static const char *getRegisterName(unsigned RegNo, unsigned AltIdx); static void fixDetailOfEffectiveAddr(MCInst *MI) { + // Operands for load and store instructions in RISCV vary widely + unsigned id = MI->flat_insn->id; unsigned reg = 0; int64_t imm = 0; + uint8_t access = 0; + + switch (id) { + case RISCV_INS_C_FLD: + case RISCV_INS_C_LW: + case RISCV_INS_C_FLW: + case RISCV_INS_C_LD: + case RISCV_INS_C_FSD: + case RISCV_INS_C_SW: + case RISCV_INS_C_FSW: + case RISCV_INS_C_SD: + case RISCV_INS_C_FLDSP: + case RISCV_INS_C_LWSP: + case RISCV_INS_C_FLWSP: + case RISCV_INS_C_LDSP: + case RISCV_INS_C_FSDSP: + case RISCV_INS_C_SWSP: + case RISCV_INS_C_FSWSP: + case RISCV_INS_C_SDSP: + case RISCV_INS_FLW: + case RISCV_INS_FSW: + case RISCV_INS_FLD: + case RISCV_INS_FSD: + case RISCV_INS_LB: + case RISCV_INS_LBU: + case RISCV_INS_LD: + case RISCV_INS_LH: + case RISCV_INS_LHU: + case RISCV_INS_LW: + case RISCV_INS_LWU: + case RISCV_INS_SB: + case RISCV_INS_SD: + case RISCV_INS_SH: + case RISCV_INS_SW: { + CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count); + CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -3)->type); + CS_ASSERT(RISCV_OP_IMM == RISCV_get_detail_op(MI, -2)->type); + CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -1)->type); - CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count); - CS_ASSERT(RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[0].type); + imm = RISCV_get_detail_op(MI, -2)->imm; + reg = RISCV_get_detail_op(MI, -1)->reg; + access = RISCV_get_detail_op(MI, -1)->access; - if (RISCV_OP_IMM == MI->flat_insn->detail->riscv.operands[1].type) { - CS_ASSERT(RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[2].type); - imm = MI->flat_insn->detail->riscv.operands[1].imm; - reg = MI->flat_insn->detail->riscv.operands[2].reg; - } else if (RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[1].type) { - CS_ASSERT(RISCV_OP_IMM == MI->flat_insn->detail->riscv.operands[2].type); - reg = MI->flat_insn->detail->riscv.operands[1].reg; - imm = MI->flat_insn->detail->riscv.operands[2].imm; + RISCV_get_detail_op(MI, -2)->type = RISCV_OP_MEM; + RISCV_get_detail_op(MI, -2)->mem.base = reg; + RISCV_get_detail_op(MI, -2)->mem.disp = imm; + RISCV_get_detail_op(MI, -2)->access = access; + + RISCV_dec_op_count(MI); + + break; + } + case RISCV_INS_LR_W: + case RISCV_INS_LR_W_AQ: + case RISCV_INS_LR_W_AQ_RL: + case RISCV_INS_LR_W_RL: + case RISCV_INS_LR_D: + case RISCV_INS_LR_D_AQ: + case RISCV_INS_LR_D_AQ_RL: + case RISCV_INS_LR_D_RL: { + CS_ASSERT(2 == MI->flat_insn->detail->riscv.op_count); + CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -1)->type); + CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -2)->type); + + reg = RISCV_get_detail_op(MI, -1)->reg; + + RISCV_get_detail_op(MI, -1)->type = RISCV_OP_MEM; + RISCV_get_detail_op(MI, -1)->mem.base = reg; + RISCV_get_detail_op(MI, -1)->mem.disp = 0; + + break; + } + case RISCV_INS_SC_W: + case RISCV_INS_SC_W_AQ: + case RISCV_INS_SC_W_AQ_RL: + case RISCV_INS_SC_W_RL: + case RISCV_INS_SC_D: + case RISCV_INS_SC_D_AQ: + case RISCV_INS_SC_D_AQ_RL: + case RISCV_INS_SC_D_RL: + case RISCV_INS_AMOADD_D: + case RISCV_INS_AMOADD_D_AQ: + case RISCV_INS_AMOADD_D_AQ_RL: + case RISCV_INS_AMOADD_D_RL: + case RISCV_INS_AMOADD_W: + case RISCV_INS_AMOADD_W_AQ: + case RISCV_INS_AMOADD_W_AQ_RL: + case RISCV_INS_AMOADD_W_RL: + case RISCV_INS_AMOAND_D: + case RISCV_INS_AMOAND_D_AQ: + case RISCV_INS_AMOAND_D_AQ_RL: + case RISCV_INS_AMOAND_D_RL: + case RISCV_INS_AMOAND_W: + case RISCV_INS_AMOAND_W_AQ: + case RISCV_INS_AMOAND_W_AQ_RL: + case RISCV_INS_AMOAND_W_RL: + case RISCV_INS_AMOMAXU_D: + case RISCV_INS_AMOMAXU_D_AQ: + case RISCV_INS_AMOMAXU_D_AQ_RL: + case RISCV_INS_AMOMAXU_D_RL: + case RISCV_INS_AMOMAXU_W: + case RISCV_INS_AMOMAXU_W_AQ: + case RISCV_INS_AMOMAXU_W_AQ_RL: + case RISCV_INS_AMOMAXU_W_RL: + case RISCV_INS_AMOMAX_D: + case RISCV_INS_AMOMAX_D_AQ: + case RISCV_INS_AMOMAX_D_AQ_RL: + case RISCV_INS_AMOMAX_D_RL: + case RISCV_INS_AMOMAX_W: + case RISCV_INS_AMOMAX_W_AQ: + case RISCV_INS_AMOMAX_W_AQ_RL: + case RISCV_INS_AMOMAX_W_RL: + case RISCV_INS_AMOMINU_D: + case RISCV_INS_AMOMINU_D_AQ: + case RISCV_INS_AMOMINU_D_AQ_RL: + case RISCV_INS_AMOMINU_D_RL: + case RISCV_INS_AMOMINU_W: + case RISCV_INS_AMOMINU_W_AQ: + case RISCV_INS_AMOMINU_W_AQ_RL: + case RISCV_INS_AMOMINU_W_RL: + case RISCV_INS_AMOMIN_D: + case RISCV_INS_AMOMIN_D_AQ: + case RISCV_INS_AMOMIN_D_AQ_RL: + case RISCV_INS_AMOMIN_D_RL: + case RISCV_INS_AMOMIN_W: + case RISCV_INS_AMOMIN_W_AQ: + case RISCV_INS_AMOMIN_W_AQ_RL: + case RISCV_INS_AMOMIN_W_RL: + case RISCV_INS_AMOOR_D: + case RISCV_INS_AMOOR_D_AQ: + case RISCV_INS_AMOOR_D_AQ_RL: + case RISCV_INS_AMOOR_D_RL: + case RISCV_INS_AMOOR_W: + case RISCV_INS_AMOOR_W_AQ: + case RISCV_INS_AMOOR_W_AQ_RL: + case RISCV_INS_AMOOR_W_RL: + case RISCV_INS_AMOSWAP_D: + case RISCV_INS_AMOSWAP_D_AQ: + case RISCV_INS_AMOSWAP_D_AQ_RL: + case RISCV_INS_AMOSWAP_D_RL: + case RISCV_INS_AMOSWAP_W: + case RISCV_INS_AMOSWAP_W_AQ: + case RISCV_INS_AMOSWAP_W_AQ_RL: + case RISCV_INS_AMOSWAP_W_RL: + case RISCV_INS_AMOXOR_D: + case RISCV_INS_AMOXOR_D_AQ: + case RISCV_INS_AMOXOR_D_AQ_RL: + case RISCV_INS_AMOXOR_D_RL: + case RISCV_INS_AMOXOR_W: + case RISCV_INS_AMOXOR_W_AQ: + case RISCV_INS_AMOXOR_W_AQ_RL: + case RISCV_INS_AMOXOR_W_RL: { + CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count); + CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -3)->type); + CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -2)->type); + CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -1)->type); + + reg = RISCV_get_detail_op(MI, -1)->reg; + + RISCV_get_detail_op(MI, -1)->type = RISCV_OP_MEM; + RISCV_get_detail_op(MI, -1)->mem.base = reg; + RISCV_get_detail_op(MI, -1)->mem.disp = 0; + + break; + } + default: { + CS_ASSERT(0 && "id is not a RISC-V memory instruction"); + break; + } } - - // set up effective address. - MI->flat_insn->detail->riscv.operands[1].type = RISCV_OP_MEM; - MI->flat_insn->detail->riscv.op_count--; - MI->flat_insn->detail->riscv.operands[1].mem.base = reg; - MI->flat_insn->detail->riscv.operands[1].mem.disp = imm; - return; } @@ -118,16 +271,13 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) unsigned reg; int64_t Imm = 0; + RISCV_add_cs_detail(MI, OpNo); + MCOperand *MO = MCInst_getOperand(MI, OpNo); if (MCOperand_isReg(MO)) { reg = MCOperand_getReg(MO); printRegName(O, reg); - if (MI->csh->detail_opt) { - MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].type = RISCV_OP_REG; - MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].reg = reg; - MI->flat_insn->detail->riscv.op_count++; - } } else { CS_ASSERT(MCOperand_isImm(MO) && "Unknown operand kind in printOperand"); Imm = MCOperand_getImm(MO); @@ -142,12 +292,6 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) else SStream_concat(O, "-%" PRIu64, -Imm); } - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].type = RISCV_OP_IMM; - MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].imm = Imm; - MI->flat_insn->detail->riscv.op_count++; - } } //CS_ASSERT(MO.isExpr() && "Unknown operand kind in printOperand"); diff --git a/arch/RISCV/RISCVMapping.c b/arch/RISCV/RISCVMapping.c index e1c0c946c..5d4a90e5c 100644 --- a/arch/RISCV/RISCVMapping.c +++ b/arch/RISCV/RISCVMapping.c @@ -6,6 +6,7 @@ #include "../../Mapping.h" #include "../../utils.h" +#include "../../cs_simple_types.h" #include "RISCVMapping.h" #include "RISCVInstPrinter.h" @@ -140,6 +141,37 @@ static const insn_map insns[] = { #include "RISCVMappingInsn.inc" }; +#ifndef CAPSTONE_DIET + +static const map_insn_ops insn_operands[] = { +#include "RISCVMappingInsnOp.inc" +}; + +#endif + +void RISCV_add_cs_detail(MCInst *MI, unsigned OpNum) { + if (!detail_is_set(MI)) + return; + + cs_op_type op_type = map_get_op_type(MI, OpNum); + + if (op_type == CS_OP_IMM) { + RISCV_get_detail_op(MI, 0)->type = RISCV_OP_IMM; + RISCV_get_detail_op(MI, 0)->imm = MCInst_getOpVal(MI, OpNum); + RISCV_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); + RISCV_inc_op_count(MI); + } + else if (op_type == CS_OP_REG) { + RISCV_get_detail_op(MI, 0)->type = RISCV_OP_REG; + RISCV_get_detail_op(MI, 0)->reg = MCInst_getOpVal(MI, OpNum); + RISCV_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); + RISCV_inc_op_count(MI); + } + else { + CS_ASSERT(0 && "Op type not handled."); + } +} + // given internal insn id, return public instruction info void RISCV_get_insn_id(cs_struct * h, cs_insn * insn, unsigned int id) { diff --git a/arch/RISCV/RISCVMapping.h b/arch/RISCV/RISCVMapping.h index c592e7fb5..e2992231d 100644 --- a/arch/RISCV/RISCVMapping.h +++ b/arch/RISCV/RISCVMapping.h @@ -13,6 +13,8 @@ const char *RISCV_group_name(csh handle, unsigned int id); const char *RISCV_reg_name(csh handle, unsigned int reg); +void RISCV_add_cs_detail(MCInst *MI, unsigned OpNum); + // map instruction name to instruction ID riscv_reg RISCV_map_insn(const char *name); diff --git a/arch/RISCV/RISCVMappingInsnOp.inc b/arch/RISCV/RISCVMappingInsnOp.inc new file mode 100644 index 000000000..fc67f0834 --- /dev/null +++ b/arch/RISCV/RISCVMappingInsnOp.inc @@ -0,0 +1,2438 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ + +{{{ /* RISCV_PHI (0) */ + 0 +}}}, +{{{ /* RISCV_INLINEASM (1) */ + 0 +}}}, +{{{ /* RISCV_INLINEASM_BR (2) */ + 0 +}}}, +{{{ /* RISCV_CFI_INSTRUCTION (3) */ + 0 +}}}, +{{{ /* RISCV_EH_LABEL (4) */ + 0 +}}}, +{{{ /* RISCV_GC_LABEL (5) */ + 0 +}}}, +{{{ /* RISCV_ANNOTATION_LABEL (6) */ + 0 +}}}, +{{{ /* RISCV_KILL (7) */ + 0 +}}}, +{{{ /* RISCV_EXTRACT_SUBREG (8) */ + 0 +}}}, +{{{ /* RISCV_INSERT_SUBREG (9) */ + 0 +}}}, +{{{ /* RISCV_IMPLICIT_DEF (10) */ + 0 +}}}, +{{{ /* RISCV_SUBREG_TO_REG (11) */ + 0 +}}}, +{{{ /* RISCV_COPY_TO_REGCLASS (12) */ + 0 +}}}, +{{{ /* RISCV_DBG_VALUE (13) */ + 0 +}}}, +{{{ /* RISCV_DBG_LABEL (14) */ + 0 +}}}, +{{{ /* RISCV_REG_SEQUENCE (15) */ + 0 +}}}, +{{{ /* RISCV_COPY (16) */ + 0 +}}}, +{{{ /* RISCV_BUNDLE (17) */ + 0 +}}}, +{{{ /* RISCV_LIFETIME_START (18) */ + 0 +}}}, +{{{ /* RISCV_LIFETIME_END (19) */ + 0 +}}}, +{{{ /* RISCV_STACKMAP (20) */ + 0 +}}}, +{{{ /* RISCV_FENTRY_CALL (21) */ + 0 +}}}, +{{{ /* RISCV_PATCHPOINT (22) */ + 0 +}}}, +{{{ /* RISCV_LOAD_STACK_GUARD (23) */ + 0 +}}}, +{{{ /* RISCV_STATEPOINT (24) */ + 0 +}}}, +{{{ /* RISCV_LOCAL_ESCAPE (25) */ + 0 +}}}, +{{{ /* RISCV_FAULTING_OP (26) */ + 0 +}}}, +{{{ /* RISCV_PATCHABLE_OP (27) */ + 0 +}}}, +{{{ /* RISCV_PATCHABLE_FUNCTION_ENTER (28) */ + 0 +}}}, +{{{ /* RISCV_PATCHABLE_RET (29) */ + 0 +}}}, +{{{ /* RISCV_PATCHABLE_FUNCTION_EXIT (30) */ + 0 +}}}, +{{{ /* RISCV_PATCHABLE_TAIL_CALL (31) */ + 0 +}}}, +{{{ /* RISCV_PATCHABLE_EVENT_CALL (32) */ + 0 +}}}, +{{{ /* RISCV_PATCHABLE_TYPED_EVENT_CALL (33) */ + 0 +}}}, +{{{ /* RISCV_ICALL_BRANCH_FUNNEL (34) */ + 0 +}}}, +{{{ /* RISCV_G_ADD (35) */ + 0 +}}}, +{{{ /* RISCV_G_SUB (36) */ + 0 +}}}, +{{{ /* RISCV_G_MUL (37) */ + 0 +}}}, +{{{ /* RISCV_G_SDIV (38) */ + 0 +}}}, +{{{ /* RISCV_G_UDIV (39) */ + 0 +}}}, +{{{ /* RISCV_G_SREM (40) */ + 0 +}}}, +{{{ /* RISCV_G_UREM (41) */ + 0 +}}}, +{{{ /* RISCV_G_AND (42) */ + 0 +}}}, +{{{ /* RISCV_G_OR (43) */ + 0 +}}}, +{{{ /* RISCV_G_XOR (44) */ + 0 +}}}, +{{{ /* RISCV_G_IMPLICIT_DEF (45) */ + 0 +}}}, +{{{ /* RISCV_G_PHI (46) */ + 0 +}}}, +{{{ /* RISCV_G_FRAME_INDEX (47) */ + 0 +}}}, +{{{ /* RISCV_G_GLOBAL_VALUE (48) */ + 0 +}}}, +{{{ /* RISCV_G_EXTRACT (49) */ + 0 +}}}, +{{{ /* RISCV_G_UNMERGE_VALUES (50) */ + 0 +}}}, +{{{ /* RISCV_G_INSERT (51) */ + 0 +}}}, +{{{ /* RISCV_G_MERGE_VALUES (52) */ + 0 +}}}, +{{{ /* RISCV_G_BUILD_VECTOR (53) */ + 0 +}}}, +{{{ /* RISCV_G_BUILD_VECTOR_TRUNC (54) */ + 0 +}}}, +{{{ /* RISCV_G_CONCAT_VECTORS (55) */ + 0 +}}}, +{{{ /* RISCV_G_PTRTOINT (56) */ + 0 +}}}, +{{{ /* RISCV_G_INTTOPTR (57) */ + 0 +}}}, +{{{ /* RISCV_G_BITCAST (58) */ + 0 +}}}, +{{{ /* RISCV_G_INTRINSIC_TRUNC (59) */ + 0 +}}}, +{{{ /* RISCV_G_INTRINSIC_ROUND (60) */ + 0 +}}}, +{{{ /* RISCV_G_LOAD (61) */ + 0 +}}}, +{{{ /* RISCV_G_SEXTLOAD (62) */ + 0 +}}}, +{{{ /* RISCV_G_ZEXTLOAD (63) */ + 0 +}}}, +{{{ /* RISCV_G_STORE (64) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMIC_CMPXCHG_WITH_SUCCESS (65) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMIC_CMPXCHG (66) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMICRMW_XCHG (67) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMICRMW_ADD (68) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMICRMW_SUB (69) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMICRMW_AND (70) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMICRMW_NAND (71) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMICRMW_OR (72) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMICRMW_XOR (73) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMICRMW_MAX (74) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMICRMW_MIN (75) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMICRMW_UMAX (76) */ + 0 +}}}, +{{{ /* RISCV_G_ATOMICRMW_UMIN (77) */ + 0 +}}}, +{{{ /* RISCV_G_BRCOND (78) */ + 0 +}}}, +{{{ /* RISCV_G_BRINDIRECT (79) */ + 0 +}}}, +{{{ /* RISCV_G_INTRINSIC (80) */ + 0 +}}}, +{{{ /* RISCV_G_INTRINSIC_W_SIDE_EFFECTS (81) */ + 0 +}}}, +{{{ /* RISCV_G_ANYEXT (82) */ + 0 +}}}, +{{{ /* RISCV_G_TRUNC (83) */ + 0 +}}}, +{{{ /* RISCV_G_CONSTANT (84) */ + 0 +}}}, +{{{ /* RISCV_G_FCONSTANT (85) */ + 0 +}}}, +{{{ /* RISCV_G_VASTART (86) */ + 0 +}}}, +{{{ /* RISCV_G_VAARG (87) */ + 0 +}}}, +{{{ /* RISCV_G_SEXT (88) */ + 0 +}}}, +{{{ /* RISCV_G_ZEXT (89) */ + 0 +}}}, +{{{ /* RISCV_G_SHL (90) */ + 0 +}}}, +{{{ /* RISCV_G_LSHR (91) */ + 0 +}}}, +{{{ /* RISCV_G_ASHR (92) */ + 0 +}}}, +{{{ /* RISCV_G_ICMP (93) */ + 0 +}}}, +{{{ /* RISCV_G_FCMP (94) */ + 0 +}}}, +{{{ /* RISCV_G_SELECT (95) */ + 0 +}}}, +{{{ /* RISCV_G_UADDO (96) */ + 0 +}}}, +{{{ /* RISCV_G_UADDE (97) */ + 0 +}}}, +{{{ /* RISCV_G_USUBO (98) */ + 0 +}}}, +{{{ /* RISCV_G_USUBE (99) */ + 0 +}}}, +{{{ /* RISCV_G_SADDO (100) */ + 0 +}}}, +{{{ /* RISCV_G_SADDE (101) */ + 0 +}}}, +{{{ /* RISCV_G_SSUBO (102) */ + 0 +}}}, +{{{ /* RISCV_G_SSUBE (103) */ + 0 +}}}, +{{{ /* RISCV_G_UMULO (104) */ + 0 +}}}, +{{{ /* RISCV_G_SMULO (105) */ + 0 +}}}, +{{{ /* RISCV_G_UMULH (106) */ + 0 +}}}, +{{{ /* RISCV_G_SMULH (107) */ + 0 +}}}, +{{{ /* RISCV_G_FADD (108) */ + 0 +}}}, +{{{ /* RISCV_G_FSUB (109) */ + 0 +}}}, +{{{ /* RISCV_G_FMUL (110) */ + 0 +}}}, +{{{ /* RISCV_G_FMA (111) */ + 0 +}}}, +{{{ /* RISCV_G_FDIV (112) */ + 0 +}}}, +{{{ /* RISCV_G_FREM (113) */ + 0 +}}}, +{{{ /* RISCV_G_FPOW (114) */ + 0 +}}}, +{{{ /* RISCV_G_FEXP (115) */ + 0 +}}}, +{{{ /* RISCV_G_FEXP2 (116) */ + 0 +}}}, +{{{ /* RISCV_G_FLOG (117) */ + 0 +}}}, +{{{ /* RISCV_G_FLOG2 (118) */ + 0 +}}}, +{{{ /* RISCV_G_FLOG10 (119) */ + 0 +}}}, +{{{ /* RISCV_G_FNEG (120) */ + 0 +}}}, +{{{ /* RISCV_G_FPEXT (121) */ + 0 +}}}, +{{{ /* RISCV_G_FPTRUNC (122) */ + 0 +}}}, +{{{ /* RISCV_G_FPTOSI (123) */ + 0 +}}}, +{{{ /* RISCV_G_FPTOUI (124) */ + 0 +}}}, +{{{ /* RISCV_G_SITOFP (125) */ + 0 +}}}, +{{{ /* RISCV_G_UITOFP (126) */ + 0 +}}}, +{{{ /* RISCV_G_FABS (127) */ + 0 +}}}, +{{{ /* RISCV_G_FCANONICALIZE (128) */ + 0 +}}}, +{{{ /* RISCV_G_GEP (129) */ + 0 +}}}, +{{{ /* RISCV_G_PTR_MASK (130) */ + 0 +}}}, +{{{ /* RISCV_G_BR (131) */ + 0 +}}}, +{{{ /* RISCV_G_INSERT_VECTOR_ELT (132) */ + 0 +}}}, +{{{ /* RISCV_G_EXTRACT_VECTOR_ELT (133) */ + 0 +}}}, +{{{ /* RISCV_G_SHUFFLE_VECTOR (134) */ + 0 +}}}, +{{{ /* RISCV_G_CTTZ (135) */ + 0 +}}}, +{{{ /* RISCV_G_CTTZ_ZERO_UNDEF (136) */ + 0 +}}}, +{{{ /* RISCV_G_CTLZ (137) */ + 0 +}}}, +{{{ /* RISCV_G_CTLZ_ZERO_UNDEF (138) */ + 0 +}}}, +{{{ /* RISCV_G_CTPOP (139) */ + 0 +}}}, +{{{ /* RISCV_G_BSWAP (140) */ + 0 +}}}, +{{{ /* RISCV_G_FCEIL (141) */ + 0 +}}}, +{{{ /* RISCV_G_FCOS (142) */ + 0 +}}}, +{{{ /* RISCV_G_FSIN (143) */ + 0 +}}}, +{{{ /* RISCV_G_FSQRT (144) */ + 0 +}}}, +{{{ /* RISCV_G_FFLOOR (145) */ + 0 +}}}, +{{{ /* RISCV_G_ADDRSPACE_CAST (146) */ + 0 +}}}, +{{{ /* RISCV_G_BLOCK_ADDR (147) */ + 0 +}}}, +{{{ /* RISCV_ADJCALLSTACKDOWN (148) */ + 0 +}}}, +{{{ /* RISCV_ADJCALLSTACKUP (149) */ + 0 +}}}, +{{{ /* RISCV_BuildPairF64Pseudo (150) */ + 0 +}}}, +{{{ /* RISCV_PseudoAtomicLoadNand32 (151) */ + 0 +}}}, +{{{ /* RISCV_PseudoAtomicLoadNand64 (152) */ + 0 +}}}, +{{{ /* RISCV_PseudoBR (153) */ + 0 +}}}, +{{{ /* RISCV_PseudoBRIND (154) */ + 0 +}}}, +{{{ /* RISCV_PseudoCALL (155) */ + 0 +}}}, +{{{ /* RISCV_PseudoCALLIndirect (156) */ + 0 +}}}, +{{{ /* RISCV_PseudoCmpXchg32 (157) */ + 0 +}}}, +{{{ /* RISCV_PseudoCmpXchg64 (158) */ + 0 +}}}, +{{{ /* RISCV_PseudoLA (159) */ + 0 +}}}, +{{{ /* RISCV_PseudoLI (160) */ + 0 +}}}, +{{{ /* RISCV_PseudoLLA (161) */ + 0 +}}}, +{{{ /* RISCV_PseudoMaskedAtomicLoadAdd32 (162) */ + 0 +}}}, +{{{ /* RISCV_PseudoMaskedAtomicLoadMax32 (163) */ + 0 +}}}, +{{{ /* RISCV_PseudoMaskedAtomicLoadMin32 (164) */ + 0 +}}}, +{{{ /* RISCV_PseudoMaskedAtomicLoadNand32 (165) */ + 0 +}}}, +{{{ /* RISCV_PseudoMaskedAtomicLoadSub32 (166) */ + 0 +}}}, +{{{ /* RISCV_PseudoMaskedAtomicLoadUMax32 (167) */ + 0 +}}}, +{{{ /* RISCV_PseudoMaskedAtomicLoadUMin32 (168) */ + 0 +}}}, +{{{ /* RISCV_PseudoMaskedAtomicSwap32 (169) */ + 0 +}}}, +{{{ /* RISCV_PseudoMaskedCmpXchg32 (170) */ + 0 +}}}, +{{{ /* RISCV_PseudoRET (171) */ + 0 +}}}, +{{{ /* RISCV_PseudoTAIL (172) */ + 0 +}}}, +{{{ /* RISCV_PseudoTAILIndirect (173) */ + 0 +}}}, +{{{ /* RISCV_Select_FPR32_Using_CC_GPR (174) */ + 0 +}}}, +{{{ /* RISCV_Select_FPR64_Using_CC_GPR (175) */ + 0 +}}}, +{{{ /* RISCV_Select_GPR_Using_CC_GPR (176) */ + 0 +}}}, +{{{ /* RISCV_SplitF64Pseudo (177) */ + 0 +}}}, +{ /* RISCV_ADD (178) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_ADDI (179) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_ADDIW (180) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_ADDW (181) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOADD_D (182) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOADD_D_AQ (183) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOADD_D_AQ_RL (184) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOADD_D_RL (185) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOADD_W (186) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOADD_W_AQ (187) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOADD_W_AQ_RL (188) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOADD_W_RL (189) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOAND_D (190) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOAND_D_AQ (191) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOAND_D_AQ_RL (192) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOAND_D_RL (193) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOAND_W (194) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOAND_W_AQ (195) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOAND_W_AQ_RL (196) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOAND_W_RL (197) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAXU_D (198) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAXU_D_AQ (199) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAXU_D_AQ_RL (200) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAXU_D_RL (201) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAXU_W (202) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAXU_W_AQ (203) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAXU_W_AQ_RL (204) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAXU_W_RL (205) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAX_D (206) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAX_D_AQ (207) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAX_D_AQ_RL (208) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAX_D_RL (209) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAX_W (210) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAX_W_AQ (211) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAX_W_AQ_RL (212) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMAX_W_RL (213) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMINU_D (214) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMINU_D_AQ (215) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMINU_D_AQ_RL (216) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMINU_D_RL (217) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMINU_W (218) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMINU_W_AQ (219) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMINU_W_AQ_RL (220) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMINU_W_RL (221) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMIN_D (222) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMIN_D_AQ (223) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMIN_D_AQ_RL (224) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMIN_D_RL (225) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMIN_W (226) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMIN_W_AQ (227) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMIN_W_AQ_RL (228) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOMIN_W_RL (229) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOOR_D (230) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOOR_D_AQ (231) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOOR_D_AQ_RL (232) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOOR_D_RL (233) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOOR_W (234) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOOR_W_AQ (235) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOOR_W_AQ_RL (236) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOOR_W_RL (237) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOSWAP_D (238) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOSWAP_D_AQ (239) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOSWAP_D_AQ_RL (240) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOSWAP_D_RL (241) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOSWAP_W (242) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOSWAP_W_AQ (243) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOSWAP_W_AQ_RL (244) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOSWAP_W_RL (245) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOXOR_D (246) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOXOR_D_AQ (247) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOXOR_D_AQ_RL (248) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOXOR_D_RL (249) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOXOR_W (250) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOXOR_W_AQ (251) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOXOR_W_AQ_RL (252) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AMOXOR_W_RL (253) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AND (254) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_ANDI (255) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_AUIPC (256) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_BEQ (257) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_BGE (258) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_BGEU (259) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_BLT (260) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_BLTU (261) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_BNE (262) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_CSRRC (263) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_CSRRCI (264) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_CSRRS (265) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_CSRRSI (266) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_CSRRW (267) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_CSRRWI (268) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_ADD (269) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_ADDI (270) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_ADDI16SP (271) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_ADDI4SPN (272) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_ADDIW (273) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_ADDW (274) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_AND (275) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_ANDI (276) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_BEQZ (277) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_BNEZ (278) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_EBREAK (279) */ +{ + { 0 } +}}, +{ /* RISCV_C_FLD (280) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_FLDSP (281) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_FLW (282) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_FLWSP (283) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_FSD (284) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_FSDSP (285) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_FSW (286) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_FSWSP (287) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_J (288) */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_JAL (289) */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_JALR (290) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_JR (291) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_LD (292) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_LDSP (293) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_LI (294) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_LUI (295) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_LW (296) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_LWSP (297) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_MV (298) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_NOP (299) */ +{ + { 0 } +}}, +{ /* RISCV_C_OR (300) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_SD (301) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_SDSP (302) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_SLLI (303) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_SRAI (304) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_SRLI (305) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_SUB (306) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_SUBW (307) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_SW (308) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_SWSP (309) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_C_UNIMP (310) */ +{ + { 0 } +}}, +{ /* RISCV_C_XOR (311) */ +{ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_DIV (312) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_DIVU (313) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_DIVUW (314) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_DIVW (315) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_EBREAK (316) */ +{ + { 0 } +}}, +{ /* RISCV_ECALL (317) */ +{ + { 0 } +}}, +{ /* RISCV_FADD_D (318) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FADD_S (319) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCLASS_D (320) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCLASS_S (321) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_D_L (322) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_D_LU (323) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_D_S (324) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_D_W (325) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_D_WU (326) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_LU_D (327) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_LU_S (328) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_L_D (329) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_L_S (330) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_S_D (331) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_S_L (332) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_S_LU (333) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_S_W (334) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_S_WU (335) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_WU_D (336) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_WU_S (337) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_W_D (338) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FCVT_W_S (339) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FDIV_D (340) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FDIV_S (341) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FENCE (342) */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FENCE_I (343) */ +{ + { 0 } +}}, +{ /* RISCV_FENCE_TSO (344) */ +{ + { 0 } +}}, +{ /* RISCV_FEQ_D (345) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FEQ_S (346) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FLD (347) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FLE_D (348) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FLE_S (349) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FLT_D (350) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FLT_S (351) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FLW (352) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMADD_D (353) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMADD_S (354) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMAX_D (355) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMAX_S (356) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMIN_D (357) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMIN_S (358) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMSUB_D (359) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMSUB_S (360) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMUL_D (361) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMUL_S (362) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMV_D_X (363) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMV_W_X (364) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMV_X_D (365) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FMV_X_W (366) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FNMADD_D (367) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FNMADD_S (368) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FNMSUB_D (369) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FNMSUB_S (370) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FSD (371) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FSGNJN_D (372) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FSGNJN_S (373) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FSGNJX_D (374) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FSGNJX_S (375) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FSGNJ_D (376) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FSGNJ_S (377) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FSQRT_D (378) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FSQRT_S (379) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FSUB_D (380) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FSUB_S (381) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_FSW (382) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_JAL (383) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_JALR (384) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LB (385) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i8, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LBU (386) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i8, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LD (387) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LH (388) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i16, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LHU (389) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i16, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LR_D (390) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LR_D_AQ (391) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LR_D_AQ_RL (392) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LR_D_RL (393) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LR_W (394) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LR_W_AQ (395) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LR_W_AQ_RL (396) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LR_W_RL (397) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LUI (398) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LW (399) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_LWU (400) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_MRET (401) */ +{ + { 0 } +}}, +{ /* RISCV_MUL (402) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_MULH (403) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_MULHSU (404) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_MULHU (405) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_MULW (406) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_OR (407) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_ORI (408) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_REM (409) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_REMU (410) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_REMUW (411) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_REMW (412) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SB (413) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i8, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SC_D (414) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SC_D_AQ (415) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SC_D_AQ_RL (416) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SC_D_RL (417) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SC_W (418) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SC_W_AQ (419) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SC_W_AQ_RL (420) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SC_W_RL (421) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SD (422) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SFENCE_VMA (423) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SH (424) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i16, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SLL (425) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SLLI (426) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SLLIW (427) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SLLW (428) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SLT (429) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SLTI (430) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SLTIU (431) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SLTU (432) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SRA (433) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SRAI (434) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SRAIW (435) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SRAW (436) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SRET (437) */ +{ + { 0 } +}}, +{ /* RISCV_SRL (438) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SRLI (439) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SRLIW (440) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SRLW (441) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SUB (442) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SUBW (443) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_SW (444) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_UNIMP (445) */ +{ + { 0 } +}}, +{ /* RISCV_URET (446) */ +{ + { 0 } +}}, +{ /* RISCV_WFI (447) */ +{ + { 0 } +}}, +{ /* RISCV_XOR (448) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_XORI (449) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ + { 0 } +}}, +{ /* RISCV_INSTRUCTION_LIST_END (450) */ +{ + { 0 } +}}, diff --git a/bindings/python/capstone/riscv.py b/bindings/python/capstone/riscv.py index ca09db61f..40cd23c5e 100644 --- a/bindings/python/capstone/riscv.py +++ b/bindings/python/capstone/riscv.py @@ -22,6 +22,7 @@ class RISCVOp(ctypes.Structure): _fields_ = ( ('type', ctypes.c_uint), ('value', RISCVOpValue), + ('access', ctypes.c_uint8), ) @property diff --git a/bindings/python/test_riscv.py b/bindings/python/test_riscv.py index 7f7acae25..396ef9228 100755 --- a/bindings/python/test_riscv.py +++ b/bindings/python/test_riscv.py @@ -6,12 +6,14 @@ from capstone import * from capstone.riscv import * from xprint import to_x, to_hex -RISCV_CODE32 = b"\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00" -RISCV_CODE64 = b"\x13\x04\xa8\x7a" +RISCV_CODE32 = b"\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00\x73\x15\x04\xb0\xf3\x56\x00\x10\x33\x05\x7b\x03\xb3\x45\x9c\x03\x33\x66\xbd\x03\x2f\xa4\x02\x10\xaf\x23\x65\x18\x2f\x27\x2f\x01\x43\xf0\x20\x18\xd3\x72\x73\x00\x53\xf4\x04\x58\x53\x85\xc5\x28\x53\x2e\xde\xa1\xd3\x84\x05\xf0\x53\x06\x05\xe0\x53\x75\x00\xc0\xd3\xf0\x05\xd0\xd3\x15\x08\xe0\x87\xaa\x75\x00\x27\x27\x66\x01\x43\xf0\x20\x1a\xd3\x72\x73\x02\x53\xf4\x04\x5a\x53\x85\xc5\x2a\x53\x2e\xde\xa3" +RISCV_CODE64 = b"\x13\x04\xa8\x7a\xbb\x07\x9c\x02\xbb\x40\x5d\x02\x3b\x63\xb7\x03\x2f\xb4\x02\x10\xaf\x33\x65\x18\x2f\x37\x2f\x01\x53\x75\x20\xc0\xd3\xf0\x25\xd0\xd3\x84\x05\xf2\x53\x06\x05\xe2\x53\x75\x00\xc2\xd3\x80\x05\xd2\xd3\x15\x08\xe2\x87\xba\x75\x00\x27\x37\x66\x01" +RISCV_CODEC = b"\xe8\x1f\x7d\x61\x80\x25\x00\x46\x88\xa2\x04\xcb\x55\x13\xf2\x93\x5d\x45\x19\x80\x15\x68\x2a\xa4\x62\x24\xa6\xff\x2a\x65\x76\x86\x65\xdd\x01\x00\xfd\xaf\x82\x82\x11\x20\x82\x94" all_tests = ( (CS_ARCH_RISCV, CS_MODE_RISCV32, RISCV_CODE32, "riscv32"), (CS_ARCH_RISCV, CS_MODE_RISCV64, RISCV_CODE64, "riscv64"), + (CS_ARCH_RISCV, CS_MODE_RISCVC, RISCV_CODEC, "riscvc"), ) @@ -39,6 +41,14 @@ def print_insn_detail(insn): if i.mem.disp != 0: print("\t\t\toperands[%u].mem.disp: 0x%s" \ % (c, to_x(i.mem.disp))) + + if i.access == CS_AC_READ: + print("\t\toperands[%u].access: READ" % (c)) + elif i.access == CS_AC_WRITE: + print("\t\toperands[%u].access: WRITE" % (c)) + elif i.access == CS_AC_READ | CS_AC_WRITE: + print("\t\toperands[%u].access: READ | WRITE" % (c)) + c += 1 if len(insn.groups) > 0: diff --git a/cstool/cstool_riscv.c b/cstool/cstool_riscv.c index fcd60d09a..c5a4d07c7 100644 --- a/cstool/cstool_riscv.c +++ b/cstool/cstool_riscv.c @@ -39,6 +39,20 @@ void print_insn_detail_riscv(csh handle, cs_insn *ins) break; } + + switch(op->access) { + default: + break; + case CS_AC_READ: + printf("\t\toperands[%u].access: READ\n", i); + break; + case CS_AC_WRITE: + printf("\t\toperands[%u].access: WRITE\n", i); + break; + case CS_AC_READ | CS_AC_WRITE: + printf("\t\toperands[%u].access: READ | WRITE\n", i); + break; + } } printf("\n"); diff --git a/include/capstone/riscv.h b/include/capstone/riscv.h index 6c8793474..bd8d563b3 100644 --- a/include/capstone/riscv.h +++ b/include/capstone/riscv.h @@ -46,6 +46,7 @@ typedef struct cs_riscv_op { int64_t imm; // immediate value for IMM operand riscv_op_mem mem; // base/disp value for MEM operand }; + uint8_t access; ///< How is this operand accessed? (READ, WRITE or READ|WRITE) } cs_riscv_op; // Instruction structure diff --git a/suite/cstest/src/riscv_detail.c b/suite/cstest/src/riscv_detail.c index 70cc770e2..ac9ea03d8 100644 --- a/suite/cstest/src/riscv_detail.c +++ b/suite/cstest/src/riscv_detail.c @@ -40,6 +40,20 @@ char *get_detail_riscv(csh *handle, cs_mode mode, cs_insn *ins) add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); break; } + + switch(op->access) { + default: + break; + case CS_AC_READ: + add_str(&result, " ; operands[%u].access: READ", i); + break; + case CS_AC_WRITE: + add_str(&result, " ; operands[%u].access: WRITE", i); + break; + case CS_AC_READ | CS_AC_WRITE: + add_str(&result, " ; operands[%u].access: READ | WRITE", i); + break; + } } return result; diff --git a/tests/cs_details/issue.cs b/tests/cs_details/issue.cs index 1e5a0d989..ee59e4224 100644 --- a/tests/cs_details/issue.cs +++ b/tests/cs_details/issue.cs @@ -204,6 +204,418 @@ !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL 0xef,0xf3,0x11,0x85 == ldrhi pc, [r1, #-0x3ef] ; op_count: 2 ; operands[0].type: REG = r15 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r1 ; operands[1].mem.disp: 0x3ef ; operands[1].access: READ ; Code condition: 8 ; Registers read: cpsr r1 ; Registers modified: r15 ; Groups: IsARM jump +!# issue 0 RISCV operand groups 0x37,0x34,0x00,0x00 == lui s0, 3 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x37,0x34,0x00,0x00 == lui s0, 3 ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x3 ; operands[1].access: READ + +!# issue 0 RISCV operand groups 0x97,0x82,0x00,0x00 == auipc t0, 8 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x97,0x82,0x00,0x00 == auipc t0, 8 ; op_count: 2 ; operands[0].type: REG = t0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x8 ; operands[1].access: READ + +!# issue 0 RISCV operand groups 0xef,0x00,0x80,0x00 == jal 8 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xef,0x00,0x80,0x00 == jal 8 ; op_count: 1 ; operands[0].type: IMM = 0x8 ; operands[0].access: READ ; Groups: call + +!# issue 0 RISCV operand groups 0xef,0xf0,0x1f,0xff == jal -0x10 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xef,0xf0,0x1f,0xff == jal -0x10 ; op_count: 1 ; operands[0].type: IMM = 0xfffffff0 ; operands[0].access: READ ; Groups: call + +!# issue 0 RISCV operand groups 0xe7,0x00,0x45,0x00 == jalr ra, a0, 4 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xe7,0x00,0x45,0x00 == jalr ra, a0, 4 ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = a0 ; operands[1].access: READ ; operands[2].type: IMM = 0x4 ; operands[2].access: READ ; Groups: call + +!# issue 0 RISCV operand groups 0xe7,0x00,0xc0,0xff == jalr ra, zero, -4 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xe7,0x00,0xc0,0xff == jalr ra, zero, -4 ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = zero ; operands[1].access: READ ; operands[2].type: IMM = 0xfffffffc ; operands[2].access: READ ; Groups: call + +!# issue 0 RISCV operand groups 0x63,0x05,0x41,0x00 == beq sp, tp, 0xa +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x63,0x05,0x41,0x00 == beq sp, tp, 0xa ; op_count: 3 ; operands[0].type: REG = sp ; operands[0].access: READ ; operands[1].type: REG = tp ; operands[1].access: READ ; operands[2].type: IMM = 0xa ; operands[2].access: READ ; Groups: branch_relative jump + +!# issue 0 RISCV operand groups 0xe3,0x9d,0x61,0xfe == bne gp, t1, -6 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xe3,0x9d,0x61,0xfe == bne gp, t1, -6 ; op_count: 3 ; operands[0].type: REG = gp ; operands[0].access: READ ; operands[1].type: REG = t1 ; operands[1].access: READ ; operands[2].type: IMM = 0xfffffffa ; operands[2].access: READ ; Groups: branch_relative jump + +!# issue 0 RISCV operand groups 0x63,0xca,0x93,0x00 == blt t2, s1, 0x14 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x63,0xca,0x93,0x00 == blt t2, s1, 0x14 ; op_count: 3 ; operands[0].type: REG = t2 ; operands[0].access: READ ; operands[1].type: REG = s1 ; operands[1].access: READ ; operands[2].type: IMM = 0x14 ; operands[2].access: READ ; Groups: branch_relative jump + +!# issue 0 RISCV operand groups 0x63,0x53,0xb5,0x00 == bge a0, a1, 6 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x63,0x53,0xb5,0x00 == bge a0, a1, 6 ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: READ ; operands[1].type: REG = a1 ; operands[1].access: READ ; operands[2].type: IMM = 0x6 ; operands[2].access: READ ; Groups: branch_relative jump + +!# issue 0 RISCV operand groups 0x63,0x65,0xd6,0x00 == bltu a2, a3, 0xa +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x63,0x65,0xd6,0x00 == bltu a2, a3, 0xa ; op_count: 3 ; operands[0].type: REG = a2 ; operands[0].access: READ ; operands[1].type: REG = a3 ; operands[1].access: READ ; operands[2].type: IMM = 0xa ; operands[2].access: READ ; Groups: branch_relative jump + +!# issue 0 RISCV operand groups 0x63,0x76,0xf7,0x00 == bgeu a4, a5, 0xc +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x63,0x76,0xf7,0x00 == bgeu a4, a5, 0xc ; op_count: 3 ; operands[0].type: REG = a4 ; operands[0].access: READ ; operands[1].type: REG = a5 ; operands[1].access: READ ; operands[2].type: IMM = 0xc ; operands[2].access: READ ; Groups: branch_relative jump + +!# issue 0 RISCV operand groups 0x03,0x88,0x18,0x00 == lb a6, 1(a7) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x03,0x88,0x18,0x00 == lb a6, 1(a7) ; op_count: 2 ; operands[0].type: REG = a6 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a7 ; operands[1].mem.disp: 0x1 ; operands[1].access: READ + +!# issue 0 RISCV operand groups 0x03,0x99,0x49,0x00 == lh s2, 4(s3) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x03,0x99,0x49,0x00 == lh s2, 4(s3) ; op_count: 2 ; operands[0].type: REG = s2 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = s3 ; operands[1].mem.disp: 0x4 ; operands[1].access: READ + +!# issue 0 RISCV operand groups 0x03,0xaa,0x6a,0x00 == lw s4, 6(s5) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x03,0xaa,0x6a,0x00 == lw s4, 6(s5) ; op_count: 2 ; operands[0].type: REG = s4 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = s5 ; operands[1].mem.disp: 0x6 ; operands[1].access: READ + +!# issue 0 RISCV operand groups 0x03,0xcb,0x2b,0x01 == lbu s6, 0x12(s7) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x03,0xcb,0x2b,0x01 == lbu s6, 0x12(s7) ; op_count: 2 ; operands[0].type: REG = s6 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = s7 ; operands[1].mem.disp: 0x12 ; operands[1].access: READ + +!# issue 0 RISCV operand groups 0x03,0xdc,0x8c,0x01 == lhu s8, 0x18(s9) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x03,0xdc,0x8c,0x01 == lhu s8, 0x18(s9) ; op_count: 2 ; operands[0].type: REG = s8 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = s9 ; operands[1].mem.disp: 0x18 ; operands[1].access: READ + +!# issue 0 RISCV operand groups 0x23,0x86,0xad,0x03 == sb s10, 0x2c(s11) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x23,0x86,0xad,0x03 == sb s10, 0x2c(s11) ; op_count: 2 ; operands[0].type: REG = s10 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = s11 ; operands[1].mem.disp: 0x2c ; operands[1].access: WRITE + +!# issue 0 RISCV operand groups 0x23,0x9a,0xce,0x03 == sh t3, 0x34(t4) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x23,0x9a,0xce,0x03 == sh t3, 0x34(t4) ; op_count: 2 ; operands[0].type: REG = t3 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = t4 ; operands[1].mem.disp: 0x34 ; operands[1].access: WRITE + +!# issue 0 RISCV operand groups 0x23,0x8f,0xef,0x01 == sb t5, 0x1e(t6) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x23,0x8f,0xef,0x01 == sb t5, 0x1e(t6) ; op_count: 2 ; operands[0].type: REG = t5 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = t6 ; operands[1].mem.disp: 0x1e ; operands[1].access: WRITE + +!# issue 0 RISCV operand groups 0x93,0x00,0xe0,0x00 == addi ra, zero, 0xe +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x93,0x00,0xe0,0x00 == addi ra, zero, 0xe ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = zero ; operands[1].access: READ ; operands[2].type: IMM = 0xe ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x13,0xa1,0x01,0x01 == slti sp, gp, 0x10 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x13,0xa1,0x01,0x01 == slti sp, gp, 0x10 ; op_count: 3 ; operands[0].type: REG = sp ; operands[0].access: WRITE ; operands[1].type: REG = gp ; operands[1].access: READ ; operands[2].type: IMM = 0x10 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x13,0xb2,0x02,0x7d == sltiu tp, t0, 0x7d0 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x13,0xb2,0x02,0x7d == sltiu tp, t0, 0x7d0 ; op_count: 3 ; operands[0].type: REG = tp ; operands[0].access: WRITE ; operands[1].type: REG = t0 ; operands[1].access: READ ; operands[2].type: IMM = 0x7d0 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x13,0xc3,0x03,0xdd == xori t1, t2, -0x230 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x13,0xc3,0x03,0xdd == xori t1, t2, -0x230 ; op_count: 3 ; operands[0].type: REG = t1 ; operands[0].access: WRITE ; operands[1].type: REG = t2 ; operands[1].access: READ ; operands[2].type: IMM = 0xfffffdd0 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x13,0xe4,0xc4,0x12 == ori s0, s1, 0x12c +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x13,0xe4,0xc4,0x12 == ori s0, s1, 0x12c ; op_count: 3 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: REG = s1 ; operands[1].access: READ ; operands[2].type: IMM = 0x12c ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x13,0xf5,0x85,0x0c == andi a0, a1, 0xc8 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x13,0xf5,0x85,0x0c == andi a0, a1, 0xc8 ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; operands[2].type: IMM = 0xc8 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x13,0x96,0xe6,0x01 == slli a2, a3, 0x1e +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x13,0x96,0xe6,0x01 == slli a2, a3, 0x1e ; op_count: 3 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = a3 ; operands[1].access: READ ; operands[2].type: IMM = 0x1e ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x13,0xd7,0x97,0x01 == srli a4, a5, 0x19 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x13,0xd7,0x97,0x01 == srli a4, a5, 0x19 ; op_count: 3 ; operands[0].type: REG = a4 ; operands[0].access: WRITE ; operands[1].type: REG = a5 ; operands[1].access: READ ; operands[2].type: IMM = 0x19 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x13,0xd8,0xf8,0x40 == srai a6, a7, 0xf +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x13,0xd8,0xf8,0x40 == srai a6, a7, 0xf ; op_count: 3 ; operands[0].type: REG = a6 ; operands[0].access: WRITE ; operands[1].type: REG = a7 ; operands[1].access: READ ; operands[2].type: IMM = 0xf ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x33,0x89,0x49,0x01 == add s2, s3, s4 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x33,0x89,0x49,0x01 == add s2, s3, s4 ; op_count: 3 ; operands[0].type: REG = s2 ; operands[0].access: WRITE ; operands[1].type: REG = s3 ; operands[1].access: READ ; operands[2].type: REG = s4 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0xb3,0x0a,0x7b,0x41 == sub s5, s6, s7 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xb3,0x0a,0x7b,0x41 == sub s5, s6, s7 ; op_count: 3 ; operands[0].type: REG = s5 ; operands[0].access: WRITE ; operands[1].type: REG = s6 ; operands[1].access: READ ; operands[2].type: REG = s7 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x33,0xac,0xac,0x01 == slt s8, s9, s10 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x33,0xac,0xac,0x01 == slt s8, s9, s10 ; op_count: 3 ; operands[0].type: REG = s8 ; operands[0].access: WRITE ; operands[1].type: REG = s9 ; operands[1].access: READ ; operands[2].type: REG = s10 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0xb3,0x3d,0xde,0x01 == sltu s11, t3, t4 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xb3,0x3d,0xde,0x01 == sltu s11, t3, t4 ; op_count: 3 ; operands[0].type: REG = s11 ; operands[0].access: WRITE ; operands[1].type: REG = t3 ; operands[1].access: READ ; operands[2].type: REG = t4 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x33,0xd2,0x62,0x40 == sra tp, t0, t1 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x33,0xd2,0x62,0x40 == sra tp, t0, t1 ; op_count: 3 ; operands[0].type: REG = tp ; operands[0].access: WRITE ; operands[1].type: REG = t0 ; operands[1].access: READ ; operands[2].type: REG = t1 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0xb3,0x43,0x94,0x00 == xor t2, s0, s1 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xb3,0x43,0x94,0x00 == xor t2, s0, s1 ; op_count: 3 ; operands[0].type: REG = t2 ; operands[0].access: WRITE ; operands[1].type: REG = s0 ; operands[1].access: READ ; operands[2].type: REG = s1 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x33,0xe5,0xc5,0x00 == or a0, a1, a2 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x33,0xe5,0xc5,0x00 == or a0, a1, a2 ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; operands[2].type: REG = a2 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0xb3,0x76,0xf7,0x00 == and a3, a4, a5 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xb3,0x76,0xf7,0x00 == and a3, a4, a5 ; op_count: 3 ; operands[0].type: REG = a3 ; operands[0].access: WRITE ; operands[1].type: REG = a4 ; operands[1].access: READ ; operands[2].type: REG = a5 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0xb3,0x54,0x39,0x01 == srl s1, s2, s3 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xb3,0x54,0x39,0x01 == srl s1, s2, s3 ; op_count: 3 ; operands[0].type: REG = s1 ; operands[0].access: WRITE ; operands[1].type: REG = s2 ; operands[1].access: READ ; operands[2].type: REG = s3 ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0xb3,0x50,0x31,0x00 == srl ra, sp, gp +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xb3,0x50,0x31,0x00 == srl ra, sp, gp ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = sp ; operands[1].access: READ ; operands[2].type: REG = gp ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x33,0x9f,0x0f,0x00 == sll t5, t6, zero +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x33,0x9f,0x0f,0x00 == sll t5, t6, zero ; op_count: 3 ; operands[0].type: REG = t5 ; operands[0].access: WRITE ; operands[1].type: REG = t6 ; operands[1].access: READ ; operands[2].type: REG = zero ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0x73,0x15,0x04,0xb0 == csrrw a0, mcycle, s0 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x73,0x15,0x04,0xb0 == csrrw a0, mcycle, s0 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = s0 ; operands[1].access: READ + +!# issue 0 RISCV operand groups 0xf3,0x56,0x00,0x10 == csrrwi a3, sstatus, 0 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xf3,0x56,0x00,0x10 == csrrwi a3, sstatus, 0 ; op_count: 2 ; operands[0].type: REG = a3 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x0 ; operands[1].access: READ + +!# issue 0 RISCV operand groups 0x33,0x05,0x7b,0x03 == mul a0, s6, s7 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x33,0x05,0x7b,0x03 == mul a0, s6, s7 ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = s6 ; operands[1].access: READ ; operands[2].type: REG = s7 ; operands[2].access: READ ; Groups: hasStdExtM + +!# issue 0 RISCV operand groups 0xb3,0x45,0x9c,0x03 == div a1, s8, s9 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xb3,0x45,0x9c,0x03 == div a1, s8, s9 ; op_count: 3 ; operands[0].type: REG = a1 ; operands[0].access: WRITE ; operands[1].type: REG = s8 ; operands[1].access: READ ; operands[2].type: REG = s9 ; operands[2].access: READ ; Groups: hasStdExtM + +!# issue 0 RISCV operand groups 0x33,0x66,0xbd,0x03 == rem a2, s10, s11 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x33,0x66,0xbd,0x03 == rem a2, s10, s11 ; op_count: 3 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = s10 ; operands[1].access: READ ; operands[2].type: REG = s11 ; operands[2].access: READ ; Groups: hasStdExtM + +!# issue 0 RISCV operand groups 0x2f,0xa4,0x02,0x10 == lr.w s0, (t0) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x2f,0xa4,0x02,0x10 == lr.w s0, (t0) ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = t0 ; operands[1].access: READ ; Groups: hasStdExtA + +!# issue 0 RISCV operand groups 0xaf,0x23,0x65,0x18 == sc.w t2, t1, (a0) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xaf,0x23,0x65,0x18 == sc.w t2, t1, (a0) ; op_count: 3 ; operands[0].type: REG = t2 ; operands[0].access: WRITE ; operands[1].type: REG = t1 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = a0 ; operands[2].access: WRITE ; Groups: hasStdExtA + +!# issue 0 RISCV operand groups 0x2f,0x27,0x2f,0x01 == amoadd.w a4, s2, (t5) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x2f,0x27,0x2f,0x01 == amoadd.w a4, s2, (t5) ; op_count: 3 ; operands[0].type: REG = a4 ; operands[0].access: WRITE ; operands[1].type: REG = s2 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = t5 ; operands[2].access: READ | WRITE ; Groups: hasStdExtA + +!# issue 0 RISCV operand groups 0x43,0xf0,0x20,0x18 == fmadd.s ft0, ft1, ft2, ft3 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x43,0xf0,0x20,0x18 == fmadd.s ft0, ft1, ft2, ft3 ; op_count: 4 ; operands[0].type: REG = ft0 ; operands[0].access: WRITE ; operands[1].type: REG = ft1 ; operands[1].access: READ ; operands[2].type: REG = ft2 ; operands[2].access: READ ; operands[3].type: REG = ft3 ; operands[3].access: READ ; Groups: hasStdExtF + +!# issue 0 RISCV operand groups 0xd3,0x72,0x73,0x00 == fadd.s ft5, ft6, ft7 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xd3,0x72,0x73,0x00 == fadd.s ft5, ft6, ft7 ; op_count: 3 ; operands[0].type: REG = ft5 ; operands[0].access: WRITE ; operands[1].type: REG = ft6 ; operands[1].access: READ ; operands[2].type: REG = ft7 ; operands[2].access: READ ; Groups: hasStdExtF + +!# issue 0 RISCV operand groups 0x53,0xf4,0x04,0x58 == fsqrt.s fs0, fs1 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x53,0xf4,0x04,0x58 == fsqrt.s fs0, fs1 ; op_count: 2 ; operands[0].type: REG = fs0 ; operands[0].access: WRITE ; operands[1].type: REG = fs1 ; operands[1].access: READ ; Groups: hasStdExtF + +!# issue 0 RISCV operand groups 0x53,0x85,0xc5,0x28 == fmin.s fa0, fa1, fa2 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x53,0x85,0xc5,0x28 == fmin.s fa0, fa1, fa2 ; op_count: 3 ; operands[0].type: REG = fa0 ; operands[0].access: WRITE ; operands[1].type: REG = fa1 ; operands[1].access: READ ; operands[2].type: REG = fa2 ; operands[2].access: READ ; Groups: hasStdExtF + +!# issue 0 RISCV operand groups 0x53,0x2e,0xde,0xa1 == feq.s t3, ft8, ft9 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x53,0x2e,0xde,0xa1 == feq.s t3, ft8, ft9 ; op_count: 3 ; operands[0].type: REG = t3 ; operands[0].access: WRITE ; operands[1].type: REG = ft8 ; operands[1].access: READ ; operands[2].type: REG = ft9 ; operands[2].access: READ ; Groups: hasStdExtF + +!# issue 0 RISCV operand groups 0xd3,0x84,0x05,0xf0 == fmv.w.x fs1, a1 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xd3,0x84,0x05,0xf0 == fmv.w.x fs1, a1 ; op_count: 2 ; operands[0].type: REG = fs1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtF + +!# issue 0 RISCV operand groups 0x53,0x06,0x05,0xe0 == fmv.x.w a2, fa0 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x53,0x06,0x05,0xe0 == fmv.x.w a2, fa0 ; op_count: 2 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = fa0 ; operands[1].access: READ ; Groups: hasStdExtF + +!# issue 0 RISCV operand groups 0x53,0x75,0x00,0xc0 == fcvt.w.s a0, ft0 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x53,0x75,0x00,0xc0 == fcvt.w.s a0, ft0 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = ft0 ; operands[1].access: READ ; Groups: hasStdExtF + +!# issue 0 RISCV operand groups 0xd3,0xf0,0x05,0xd0 == fcvt.s.w ft1, a1 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xd3,0xf0,0x05,0xd0 == fcvt.s.w ft1, a1 ; op_count: 2 ; operands[0].type: REG = ft1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtF + +!# issue 0 RISCV operand groups 0xd3,0x15,0x08,0xe0 == fclass.s a1, fa6 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xd3,0x15,0x08,0xe0 == fclass.s a1, fa6 ; op_count: 2 ; operands[0].type: REG = a1 ; operands[0].access: WRITE ; operands[1].type: REG = fa6 ; operands[1].access: READ ; Groups: hasStdExtF + +!# issue 0 RISCV operand groups 0x87,0xaa,0x75,0x00 == flw fs5, 7(a1) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x87,0xaa,0x75,0x00 == flw fs5, 7(a1) ; op_count: 2 ; operands[0].type: REG = fs5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a1 ; operands[1].mem.disp: 0x7 ; operands[1].access: READ ; Groups: hasStdExtF + +!# issue 0 RISCV operand groups 0x27,0x27,0x66,0x01 == fsw fs6, 0xe(a2) +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x27,0x27,0x66,0x01 == fsw fs6, 0xe(a2) ; op_count: 2 ; operands[0].type: REG = fs6 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = a2 ; operands[1].mem.disp: 0xe ; operands[1].access: WRITE ; Groups: hasStdExtF + +!# issue 0 RISCV operand groups 0x43,0xf0,0x20,0x1a == fmadd.d ft0, ft1, ft2, ft3 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x43,0xf0,0x20,0x1a == fmadd.d ft0, ft1, ft2, ft3 ; op_count: 4 ; operands[0].type: REG = ft0 ; operands[0].access: WRITE ; operands[1].type: REG = ft1 ; operands[1].access: READ ; operands[2].type: REG = ft2 ; operands[2].access: READ ; operands[3].type: REG = ft3 ; operands[3].access: READ ; Groups: hasStdExtD + +!# issue 0 RISCV operand groups 0xd3,0x72,0x73,0x02 == fadd.d ft5, ft6, ft7 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0xd3,0x72,0x73,0x02 == fadd.d ft5, ft6, ft7 ; op_count: 3 ; operands[0].type: REG = ft5 ; operands[0].access: WRITE ; operands[1].type: REG = ft6 ; operands[1].access: READ ; operands[2].type: REG = ft7 ; operands[2].access: READ ; Groups: hasStdExtD + +!# issue 0 RISCV operand groups 0x53,0xf4,0x04,0x5a == fsqrt.d fs0, fs1 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x53,0xf4,0x04,0x5a == fsqrt.d fs0, fs1 ; op_count: 2 ; operands[0].type: REG = fs0 ; operands[0].access: WRITE ; operands[1].type: REG = fs1 ; operands[1].access: READ ; Groups: hasStdExtD + +!# issue 0 RISCV operand groups 0x53,0x85,0xc5,0x2a == fmin.d fa0, fa1, fa2 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x53,0x85,0xc5,0x2a == fmin.d fa0, fa1, fa2 ; op_count: 3 ; operands[0].type: REG = fa0 ; operands[0].access: WRITE ; operands[1].type: REG = fa1 ; operands[1].access: READ ; operands[2].type: REG = fa2 ; operands[2].access: READ ; Groups: hasStdExtD + +!# issue 0 RISCV operand groups 0x53,0x2e,0xde,0xa3 == feq.d t3, ft8, ft9 +!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL +0x53,0x2e,0xde,0xa3 == feq.d t3, ft8, ft9 ; op_count: 3 ; operands[0].type: REG = t3 ; operands[0].access: WRITE ; operands[1].type: REG = ft8 ; operands[1].access: READ ; operands[2].type: REG = ft9 ; operands[2].access: READ ; Groups: hasStdExtD + +!# issue 0 RISCV operand groups 0x13,0x04,0xa8,0x7a == addi s0, a6, 0x7aa +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0x13,0x04,0xa8,0x7a == addi s0, a6, 0x7aa ; op_count: 3 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: REG = a6 ; operands[1].access: READ ; operands[2].type: IMM = 0x7aa ; operands[2].access: READ + +!# issue 0 RISCV operand groups 0xbb,0x07,0x9c,0x02 == mulw a5, s8, s1 +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0xbb,0x07,0x9c,0x02 == mulw a5, s8, s1 ; op_count: 3 ; operands[0].type: REG = a5 ; operands[0].access: WRITE ; operands[1].type: REG = s8 ; operands[1].access: READ ; operands[2].type: REG = s1 ; operands[2].access: READ ; Groups: hasStdExtM isrv64 + +!# issue 0 RISCV operand groups 0xbb,0x40,0x5d,0x02 == divw ra, s10, t0 +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0xbb,0x40,0x5d,0x02 == divw ra, s10, t0 ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = s10 ; operands[1].access: READ ; operands[2].type: REG = t0 ; operands[2].access: READ ; Groups: hasStdExtM isrv64 + +!# issue 0 RISCV operand groups 0x3b,0x63,0xb7,0x03 == remw t1, a4, s11 +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0x3b,0x63,0xb7,0x03 == remw t1, a4, s11 ; op_count: 3 ; operands[0].type: REG = t1 ; operands[0].access: WRITE ; operands[1].type: REG = a4 ; operands[1].access: READ ; operands[2].type: REG = s11 ; operands[2].access: READ ; Groups: hasStdExtM isrv64 + +!# issue 0 RISCV operand groups 0x2f,0xb4,0x02,0x10 == lr.d s0, (t0) +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0x2f,0xb4,0x02,0x10 == lr.d s0, (t0) ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = t0 ; operands[1].access: READ ; Groups: hasStdExtA isrv64 + +!# issue 0 RISCV operand groups 0xaf,0x33,0x65,0x18 == sc.d t2, t1, (a0) +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0xaf,0x33,0x65,0x18 == sc.d t2, t1, (a0) ; op_count: 3 ; operands[0].type: REG = t2 ; operands[0].access: WRITE ; operands[1].type: REG = t1 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = a0 ; operands[2].access: WRITE ; Groups: hasStdExtA isrv64 + +!# issue 0 RISCV operand groups 0x2f,0x37,0x2f,0x01 == amoadd.d a4, s2, (t5) +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0x2f,0x37,0x2f,0x01 == amoadd.d a4, s2, (t5) ; op_count: 3 ; operands[0].type: REG = a4 ; operands[0].access: WRITE ; operands[1].type: REG = s2 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = t5 ; operands[2].access: READ | WRITE ; Groups: hasStdExtA isrv64 + +!# issue 0 RISCV operand groups 0x53,0x75,0x20,0xc0 == fcvt.l.s a0, ft0 +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0x53,0x75,0x20,0xc0 == fcvt.l.s a0, ft0 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = ft0 ; operands[1].access: READ ; Groups: hasStdExtF isrv64 + +!# issue 0 RISCV operand groups 0xd3,0xf0,0x25,0xd0 == fcvt.s.l ft1, a1 +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0xd3,0xf0,0x25,0xd0 == fcvt.s.l ft1, a1 ; op_count: 2 ; operands[0].type: REG = ft1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtF isrv64 + +!# issue 0 RISCV operand groups 0xd3,0x84,0x05,0xf2 == fmv.d.x fs1, a1 +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0xd3,0x84,0x05,0xf2 == fmv.d.x fs1, a1 ; op_count: 2 ; operands[0].type: REG = fs1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtD isrv64 + +!# issue 0 RISCV operand groups 0x53,0x06,0x05,0xe2 == fmv.x.d a2, fa0 +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0x53,0x06,0x05,0xe2 == fmv.x.d a2, fa0 ; op_count: 2 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = fa0 ; operands[1].access: READ ; Groups: hasStdExtD isrv64 + +!# issue 0 RISCV operand groups 0x53,0x75,0x00,0xc2 == fcvt.w.d a0, ft0 +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0x53,0x75,0x00,0xc2 == fcvt.w.d a0, ft0 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = ft0 ; operands[1].access: READ ; Groups: hasStdExtD + +!# issue 0 RISCV operand groups 0xd3,0x80,0x05,0xd2 == fcvt.d.w ft1, a1 +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0xd3,0x80,0x05,0xd2 == fcvt.d.w ft1, a1 ; op_count: 2 ; operands[0].type: REG = ft1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtD + +!# issue 0 RISCV operand groups 0xd3,0x15,0x08,0xe2 == fclass.d a1, fa6 +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0xd3,0x15,0x08,0xe2 == fclass.d a1, fa6 ; op_count: 2 ; operands[0].type: REG = a1 ; operands[0].access: WRITE ; operands[1].type: REG = fa6 ; operands[1].access: READ ; Groups: hasStdExtD + +!# issue 0 RISCV operand groups 0x87,0xba,0x75,0x00 == fld fs5, 7(a1) +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0x87,0xba,0x75,0x00 == fld fs5, 7(a1) ; op_count: 2 ; operands[0].type: REG = fs5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a1 ; operands[1].mem.disp: 0x7 ; operands[1].access: READ ; Groups: hasStdExtD + +!# issue 0 RISCV operand groups 0x27,0x37,0x66,0x01 == fsd fs6, 0xe(a2) +!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL +0x27,0x37,0x66,0x01 == fsd fs6, 0xe(a2) ; op_count: 2 ; operands[0].type: REG = fs6 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = a2 ; operands[1].mem.disp: 0xe ; operands[1].access: WRITE ; Groups: hasStdExtD + +!# issue 0 RISCV operand groups 0xe8,0x1f == c.addi4spn a0, sp, 0x3fc +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0xe8,0x1f == c.addi4spn a0, sp, 0x3fc ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = sp ; operands[1].access: READ ; operands[2].type: IMM = 0x3fc ; operands[2].access: READ ; Groups: hasStdExtC + +!# issue 0 RISCV operand groups 0x7d,0x61 == c.addi16sp sp, 0x1f0 +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x7d,0x61 == c.addi16sp sp, 0x1f0 ; op_count: 2 ; operands[0].type: REG = sp ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x1f0 ; operands[1].access: READ ; Groups: hasStdExtC + +!# issue 0 RISCV operand groups 0x80,0x25 == c.fld fs0, 8(a1) +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x80,0x25 == c.fld fs0, 8(a1) ; op_count: 2 ; operands[0].type: REG = fs0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a1 ; operands[1].mem.disp: 0x8 ; operands[1].access: READ ; Groups: hasStdExtC hasStdExtD + +!# issue 0 RISCV operand groups 0x00,0x46 == c.lw s0, 8(a2) +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x00,0x46 == c.lw s0, 8(a2) ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a2 ; operands[1].mem.disp: 0x8 ; operands[1].access: READ ; Groups: hasStdExtC + +!# issue 0 RISCV operand groups 0x88,0xa2 == c.fsd fa0, 0(a3) +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x88,0xa2 == c.fsd fa0, 0(a3) ; op_count: 2 ; operands[0].type: REG = fa0 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = a3 ; operands[1].access: WRITE ; Groups: hasStdExtC hasStdExtD + +!# issue 0 RISCV operand groups 0x04,0xcb == c.sw s1, 0x10(a4) +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x04,0xcb == c.sw s1, 0x10(a4) ; op_count: 2 ; operands[0].type: REG = s1 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = a4 ; operands[1].mem.disp: 0x10 ; operands[1].access: WRITE ; Groups: hasStdExtC + +!# issue 0 RISCV operand groups 0x55,0x13 == c.addi t1, -0xb +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x55,0x13 == c.addi t1, -0xb ; op_count: 2 ; operands[0].type: REG = t1 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0xfffffff5 ; operands[1].access: READ ; Groups: hasStdExtC + +!# issue 0 RISCV operand groups 0xf2,0x93 == c.add t2, t3 +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0xf2,0x93 == c.add t2, t3 ; op_count: 2 ; operands[0].type: REG = t2 ; operands[0].access: READ | WRITE ; operands[1].type: REG = t3 ; operands[1].access: READ ; Groups: hasStdExtC + +!# issue 0 RISCV operand groups 0x5d,0x45 == c.li a0, 0x17 +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x5d,0x45 == c.li a0, 0x17 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x17 ; operands[1].access: READ ; Groups: hasStdExtC + +!# issue 0 RISCV operand groups 0x19,0x80 == c.srli s0, 6 +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x19,0x80 == c.srli s0, 6 ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x6 ; operands[1].access: READ ; Groups: hasStdExtC + +!# issue 0 RISCV operand groups 0x15,0x68 == c.lui a6, 5 +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x15,0x68 == c.lui a6, 5 ; op_count: 2 ; operands[0].type: REG = a6 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x5 ; operands[1].access: READ ; Groups: hasStdExtC + +!# issue 0 RISCV operand groups 0x2a,0xa4 == c.fsdsp fa0, 8(sp) +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x2a,0xa4 == c.fsdsp fa0, 8(sp) ; op_count: 2 ; operands[0].type: REG = fa0 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = sp ; operands[1].mem.disp: 0x8 ; operands[1].access: WRITE ; Groups: hasStdExtC hasStdExtD + +!# issue 0 RISCV operand groups 0x62,0x24 == c.fldsp fs0, 0x18(sp) +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x62,0x24 == c.fldsp fs0, 0x18(sp) ; op_count: 2 ; operands[0].type: REG = fs0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = sp ; operands[1].mem.disp: 0x18 ; operands[1].access: READ ; Groups: hasStdExtC hasStdExtD + +!# issue 0 RISCV operand groups 0xa6,0xff == c.fswsp fs1, 0xfc(sp) +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0xa6,0xff == c.fswsp fs1, 0xfc(sp) ; op_count: 3 ; operands[0].type: REG = fs1 ; operands[0].access: READ ; operands[1].type: IMM = 0xfc ; operands[1].access: READ ; operands[2].type: REG = sp ; operands[2].access: WRITE ; Groups: hasStdExtC hasStdExtF isrv32 + +!# issue 0 RISCV operand groups 0x2a,0x65 == c.flwsp fa0, 0x88(sp) +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x2a,0x65 == c.flwsp fa0, 0x88(sp) ; op_count: 3 ; operands[0].type: REG = fa0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x88 ; operands[1].access: READ ; operands[2].type: REG = sp ; operands[2].access: READ ; Groups: hasStdExtC hasStdExtF isrv32 + +!# issue 0 RISCV operand groups 0x76,0x86 == c.mv a2, t4 +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x76,0x86 == c.mv a2, t4 ; op_count: 2 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = t4 ; operands[1].access: READ ; Groups: hasStdExtC + +!# issue 0 RISCV operand groups 0x65,0xdd == c.beqz a0, -8 +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x65,0xdd == c.beqz a0, -8 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: READ ; operands[1].type: IMM = 0xfffffff8 ; operands[1].access: READ ; Groups: hasStdExtC branch_relative jump + +!# issue 0 RISCV operand groups 0x01,0x00 == c.nop +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x01,0x00 == c.nop ; Groups: hasStdExtC + +!# issue 0 RISCV operand groups 0xfd,0xaf == c.j 0x7fe +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0xfd,0xaf == c.j 0x7fe ; op_count: 1 ; operands[0].type: IMM = 0x7fe ; operands[0].access: READ ; Groups: hasStdExtC jump + +!# issue 0 RISCV operand groups 0x82,0x82 == c.jr t0 +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x82,0x82 == c.jr t0 ; op_count: 1 ; operands[0].type: REG = t0 ; operands[0].access: READ ; Groups: hasStdExtC jump + +!# issue 0 RISCV operand groups 0x11,0x20 == c.jal 4 +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x11,0x20 == c.jal 4 ; op_count: 1 ; operands[0].type: IMM = 0x4 ; operands[0].access: READ ; Groups: hasStdExtC isrv32 call + +!# issue 0 RISCV operand groups 0x82,0x94 == c.jalr s1 +!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL +0x82,0x94 == c.jalr s1 ; op_count: 1 ; operands[0].type: REG = s1 ; operands[0].access: READ ; Groups: hasStdExtC call + !# issue 2285 AArch64 operands !# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL 0xc0,0x08,0x9f,0xe0 == ld1w {za0h.s[w12, 0]}, p2/z, [x6] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za0.s ; operands[0].sme.slice_reg: w12 ; operands[0].sme.slice_offset: 0 ; operands[0].sme.is_vertical: false ; operands[0].access: WRITE ; operands[0].vas: 0x20 ; operands[1].type: PREDICATE ; operands[1].pred.reg: p2 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x6 ; operands[2].access: READ ; Registers read: w12 p2 x6 ; Registers modified: za0.s ; Groups: HasSME diff --git a/tests/test_riscv.c b/tests/test_riscv.c index 5b5d67c4b..7da86e36f 100644 --- a/tests/test_riscv.c +++ b/tests/test_riscv.c @@ -65,6 +65,20 @@ static void print_insn_detail(cs_insn *ins) break; } + switch(op->access) { + default: + break; + case CS_AC_READ: + printf("\t\toperands[%u].access: READ\n", i); + break; + case CS_AC_WRITE: + printf("\t\toperands[%u].access: WRITE\n", i); + break; + case CS_AC_READ | CS_AC_WRITE: + printf("\t\toperands[%u].access: READ | WRITE\n", i); + break; + } + } //print the groups this instruction belongs to @@ -81,8 +95,9 @@ static void print_insn_detail(cs_insn *ins) static void test() { -#define RISCV_CODE32 "\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00" -#define RISCV_CODE64 "\x13\x04\xa8\x7a" // aaa80413 +#define RISCV_CODE32 "\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00\x73\x15\x04\xb0\xf3\x56\x00\x10\x33\x05\x7b\x03\xb3\x45\x9c\x03\x33\x66\xbd\x03\x2f\xa4\x02\x10\xaf\x23\x65\x18\x2f\x27\x2f\x01\x43\xf0\x20\x18\xd3\x72\x73\x00\x53\xf4\x04\x58\x53\x85\xc5\x28\x53\x2e\xde\xa1\xd3\x84\x05\xf0\x53\x06\x05\xe0\x53\x75\x00\xc0\xd3\xf0\x05\xd0\xd3\x15\x08\xe0\x87\xaa\x75\x00\x27\x27\x66\x01\x43\xf0\x20\x1a\xd3\x72\x73\x02\x53\xf4\x04\x5a\x53\x85\xc5\x2a\x53\x2e\xde\xa3" +#define RISCV_CODE64 "\x13\x04\xa8\x7a\xbb\x07\x9c\x02\xbb\x40\x5d\x02\x3b\x63\xb7\x03\x2f\xb4\x02\x10\xaf\x33\x65\x18\x2f\x37\x2f\x01\x53\x75\x20\xc0\xd3\xf0\x25\xd0\xd3\x84\x05\xf2\x53\x06\x05\xe2\x53\x75\x00\xc2\xd3\x80\x05\xd2\xd3\x15\x08\xe2\x87\xba\x75\x00\x27\x37\x66\x01" +#define RISCV_CODEC "\xe8\x1f\x7d\x61\x80\x25\x00\x46\x88\xa2\x04\xcb\x55\x13\xf2\x93\x5d\x45\x19\x80\x15\x68\x2a\xa4\x62\x24\xa6\xff\x2a\x65\x76\x86\x65\xdd\x01\x00\xfd\xaf\x82\x82\x11\x20\x82\x94" struct platform platforms[] = { { CS_ARCH_RISCV, @@ -97,6 +112,13 @@ static void test() (unsigned char *)RISCV_CODE64, sizeof(RISCV_CODE64) - 1, "riscv64" + }, + { + CS_ARCH_RISCV, + CS_MODE_RISCVC, + (unsigned char *)RISCV_CODEC, + sizeof(RISCV_CODEC) - 1, + "riscvc" } };