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add some tricore v1.1 inst

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This commit is contained in:
billow 2023-04-01 19:16:45 +08:00
parent 753b6a4ce0
commit 4567335c20
9 changed files with 5955 additions and 5751 deletions
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32
arch/TriCore/TriCore.td
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@ -23,32 +23,28 @@ include "llvm/Target/Target.td"
// Specify whether target support specific TRICORE ISA variants.
def HasGenericOps : SubtargetFeature<"generic", "HasGenericOps", "true",
"Support TriCore generic instructions",
[]>;
def HasV110Ops : SubtargetFeature<"v1.1", "HasV110Ops", "true",
"Support TriCore v1.1 instructions",
[HasGenericOps]>;
[]>;
def HasV120Ops : SubtargetFeature<"v1.2", "HasV120Ops", "true",
"Support TriCore v1.2 instructions",
[HasGenericOps]>;
[]>;
def HasV130Ops : SubtargetFeature<"v1.3", "HasV130Ops", "true",
"Support TriCore v1.3 instructions",
[HasGenericOps]>;
[]>;
def HasV131Ops : SubtargetFeature<"v1.3.1", "HasV131Ops", "true",
"Support TriCore v1.3.1 instructions",
[HasGenericOps]>;
[]>;
def HasV160Ops : SubtargetFeature<"v1.6", "HasV160Ops", "true",
"Support TriCore v1.6 instructions",
[HasGenericOps]>;
[]>;
def HasV161Ops : SubtargetFeature<"v1.6.1", "HasV161Ops", "true",
"Support TriCore v1.6.1 instructions",
[HasGenericOps]>;
[]>;
def HasV162Ops : SubtargetFeature<"v1.6.2", "HasV162Ops", "true",
"Support TriCore v1.6.2 instructions",
[HasGenericOps]>;
[]>;
def HasGeneric : Predicate<"HasGenericOps()">;
def HasV110 : Predicate<"HasV110Ops()">;
def HasV120 : Predicate<"HasV120Ops()">;
def HasV130 : Predicate<"HasV130Ops()">;
@ -57,6 +53,20 @@ def HasV160 : Predicate<"HasV160Ops()">;
def HasV161 : Predicate<"HasV161Ops()">;
def HasV162 : Predicate<"HasV162Ops()">;
def HasV120_UP : Predicate<"HasV120Ops() || HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">;
def HasV130_UP : Predicate<"HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">;
def HasV131_UP : Predicate<"HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">;
def HasV160_UP : Predicate<"HasV160Ops() || HasV161Ops() || HasV162Ops()">;
def HasV161_UP : Predicate<"HasV161Ops() || HasV162Ops()">;
def HasV162_UP : Predicate<"HasV162Ops()">;
def HasV120_DN : Predicate<"HasV120Ops() || HasV110Ops()">;
def HasV130_DN : Predicate<"HasV130Ops() || HasV120Ops() || HasV110Ops()">;
def HasV131_DN : Predicate<"HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">;
def HasV160_DN : Predicate<"HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">;
def HasV161_DN : Predicate<"HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">;
def HasV162_DN : Predicate<"HasV162Ops() || HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">;
class Architecture<string fname, string aname, list<SubtargetFeature> features = []>
: SubtargetFeature<fname, "TriCoreArch", aname,
!strconcat(aname, " architecture"), features>;

2228
arch/TriCore/TriCoreGenAsmWriter.inc
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4358
arch/TriCore/TriCoreGenDisassemblerTables.inc
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3291
arch/TriCore/TriCoreGenInstrInfo.inc
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33
arch/TriCore/TriCoreGenSubtargetInfo.inc Normal file
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@ -0,0 +1,33 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by the LLVM TableGen Disassembler Backend. */
/* Do not edit. */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
TriCore_HasV110Ops = 0,
TriCore_HasV120Ops = 1,
TriCore_HasV130Ops = 2,
TriCore_HasV131Ops = 3,
TriCore_HasV160Ops = 4,
TriCore_HasV161Ops = 5,
TriCore_HasV162Ops = 6,
TriCore_TRICORE_PCP = 7,
TriCore_TRICORE_PCP2 = 8,
TriCore_TRICORE_RIDER_A = 9,
TriCore_TRICORE_V1_1 = 10,
TriCore_TRICORE_V1_2 = 11,
TriCore_TRICORE_V1_3 = 12,
TriCore_TRICORE_V1_3_1 = 13,
TriCore_TRICORE_V1_6 = 14,
TriCore_TRICORE_V1_6_1 = 15,
TriCore_TRICORE_V1_6_2 = 16,
TriCore_NumSubtargetFeatures = 17
};
#endif // GET_SUBTARGETINFO_ENUM

40
arch/TriCore/TriCoreInstrInfo.td
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@ -277,10 +277,14 @@ multiclass mISRC_a15a<bits<8> op1, bits<8> op2, bits<8> op3,
def _src_15a : ISRC_15a<op3, asmstr>;
}
class ISRRS<bits<6> op1, string asmstr>
class ISRRS_AcAbD15N<bits<6> op1, string asmstr>
: SRRS<op1, (outs AddrRegs:$d), (ins AddrRegs:$s2, u2imm:$n),
asmstr # " $d, $s2, %d15, $n", []>;
class ISRRS_AcDbN<bits<6> op1, string asmstr>
: SRRS<op1, (outs AddrRegs:$d), (ins DataRegs:$s2, u2imm:$n),
asmstr # " $d, $s2, $n", []>;
/// 32-Bit Opcode Formats
/// RC
@ -356,6 +360,10 @@ class IRR_AcAbDaN<bits<8> op1, bits<8> op2, string asmstr>
: RR<op1, op2, (outs AddrRegs:$d), (ins DataRegs:$s1, AddrRegs:$s2, i32imm:$n),
asmstr # " $d, $s2, $s1, $n", []>;
class IRR_AcAaDbN<bits<8> op1, bits<8> op2, string asmstr>
: RR<op1, op2, (outs AddrRegs:$d), (ins DataRegs:$s1, AddrRegs:$s2, i32imm:$n),
asmstr # " $d, $s1, $s2, $n", []>;
multiclass mIRR_RC<bits<8> rr1, bits<8> rr2, bits<8> rc1, bits<7> rc2,
string asmstr> {
def _rr : IRR_DcDaDb<rr1, rr2, asmstr>;
@ -461,6 +469,10 @@ let Defs = [PSW] in {
def ABSDIFS_rr : RR<0x0B, 0x0F, (outs DataRegs:$d),
(ins DataRegs:$s1, DataRegs:$s2), "absdifs $d, $s1, $s2",
[(set DataRegs:$d, (TriCoreAbsDif DataRegs:$s1, DataRegs:$s2))]>;
def ABSDIFS_B_rr_v110 : RR<0x0B, 0x4F, (outs DataRegs:$d),
(ins DataRegs:$s1, DataRegs:$s2), "absdifs.b $d, $s1, $s2",
[(set DataRegs:$d, (TriCoreAbsDif DataRegs:$s1, DataRegs:$s2))]>
, Requires<[HasV110]>;
def ABSDIFS_H_rr : RR<0x0B, 0x6F, (outs DataRegs:$d),
(ins DataRegs:$s1, DataRegs:$s2), "absdifs.h $d, $s1, $s2",
[(set DataRegs:$d, (TriCoreAbsDif DataRegs:$s1, DataRegs:$s2))]>;
@ -468,6 +480,10 @@ let Defs = [PSW] in {
def ABSS_rr : RR<0x0B, 0x1D, (outs DataRegs:$d),
(ins DataRegs:$s1, DataRegs:$s2), "abss $d, $s1, $s2",
[(set DataRegs:$d, (TriCoreAbsDif DataRegs:$s1, DataRegs:$s2))]>;
def ABSS_B_rr_v110 : RR<0x0B, 0x5D, (outs DataRegs:$d),
(ins DataRegs:$s1, DataRegs:$s2), "abss.b $d, $s1, $s2",
[(set DataRegs:$d, (TriCoreAbsDif DataRegs:$s1, DataRegs:$s2))]>
, Requires<[HasV110]>;
def ABSS_H_rr : RR<0x0B, 0x7D, (outs DataRegs:$d),
(ins DataRegs:$s1, DataRegs:$s2), "abss.h $d, $s1, $s2",
[(set DataRegs:$d, (TriCoreAbsDif DataRegs:$s1, DataRegs:$s2))]>;
@ -517,9 +533,19 @@ defm ADDS : mIRR_RC<0x0B, 0x02, 0x8B, 0x02, "adds">,
mISRR_s<0x22, "adds">,
mIH_HU_U<0x0B, 0x62, 0x0B, 0x63, 0x0B, 0x03, "adds">;
def ADDS_U_rc : IRC_2<0x8B, 0x03, "adds.u">;
def ADDSC_A_rr : IRR_AcAbDaN<0x01, 0x60, "addsc.a">;
def ADDSC_A_srrs : ISRRS<0x10, "addsc.a">;
def ADDSC_AT_rr : IRR_DcDaDb<0x01, 0x62, "addsc.at">;
def ADDSC_A_srrs_v120u : ISRRS_AcAbD15N<0x10, "addsc.a">, Requires<[HasV120_UP]>;
def ADDSC_A_rr_v120u : IRR_AcAbDaN<0x01, 0x60, "addsc.a">, Requires<[HasV120_UP]>;
def ADDSC_AT_rr_v120u : IRR_2<0x01, 0x62, "addsc.at %d, %s2, %s1", AddrRegs, AddrRegs, DataRegs>
, Requires<[HasV120_UP]>;
let DecoderNamespace = "V110" in {
def ADDS_B_rr_v110 : IRR_DcDaDb<0x0B, 0x42, "adds.b">, Requires<[HasV110]>;
def ADDS_BU_rr_v110 : IRR_DcDaDb<0x0B, 0x43, "adds.bu">, Requires<[HasV110]>;
def ADDSC_A_srrs_v110 : ISRRS_AcDbN<0x10, "addsc.a">, Requires<[HasV110]>;
def ADDSC_A_rr_v110 : IRR_AcAaDbN<0x01, 0x60, "addsc.a">, Requires<[HasV110]>;
def ADDSC_AT_rr_v110 : IRR_2<0x01, 0x62, "addsc.at %d, %s1, %s2", AddrRegs, AddrRegs, DataRegs>
, Requires<[HasV110]>;
}
defm ADDX : mIRR_RC<0x0B, 0x04, 0x8B, 0x04, "addx">;
@ -748,7 +774,7 @@ class IBO_cPbOEa<bits<8> op1, bits<6> op2, string asmstr>
// A[b], off10, E[a] (BO)(Post-increment Addressing Mode)
class IBO_posAbOEa<bits<8> op1, bits<6> op2, string asmstr>
: BO<op1, op2, (outs), (ins ExtRegs:$s1, AddrRegs:$s2, s10imm:$off10),
asmstr # " [$s2+]$off10, $s1", []>;
asmstr # " [${s2}+]$off10, $s1", []>;
// A[b], off10, E[a] (BO)(Pre-increment Addressing Mode)
class IBO_preAbOEa<bits<8> op1, bits<6> op2, string asmstr>
: BO<op1, op2, (outs), (ins ExtRegs:$s1, AddrRegs:$s2, s10imm:$off10),
@ -1117,7 +1143,7 @@ class ISLR<bits<8> op1, string asmstr, RegisterClass dc>
asmstr # " $d, [$s2]", []>;
class ISLR_pos<bits<8> op1, string asmstr, RegisterClass dc>
: SLR<op1, (outs dc:$d), (ins AddrRegs:$s2),
asmstr # " $d, [$s2+]", []>;
asmstr # " $d, [${s2}+]", []>;
class ISLRO<bits<8> op1, string asmstr, RegisterClass dc>
: SLRO<op1, (outs dc:$d), (ins u4imm:$off4),
@ -1666,7 +1692,7 @@ multiclass mISRO_SSR_SSRO_st<bits<8> sro, bits<8> ssr, bits<8> ssrpos, bits<8> s
def _ssr : SSR<ssr, (outs AddrRegs:$d), (ins rc:$s1),
asmstr # " [$d], $s1", []>;
def _ssr_pos : SSR<ssrpos, (outs AddrRegs:$d), (ins rc:$s1),
asmstr # " [$d+], $s1", []>;
asmstr # " [${d}+], $s1", []>;
def _ssro : SSRO<ssro, (outs), (ins rc:$s1, u4imm:$off4),
asmstr # " [%a15]$off4, $s1", []>;
}

1714
arch/TriCore/gen/TriCoreGenCSMappingInsn.inc
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5
arch/TriCore/gen/TriCoreGenCSMappingInsnName.inc
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@ -6,11 +6,13 @@
/* Code generator: https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
"xor.t", // TriCore_INS_XOR.T
"absdifs.b", // TriCore_INS_ABSDIFS.B
"absdifs.h", // TriCore_INS_ABSDIFS.H
"absdifs", // TriCore_INS_ABSDIFS
"absdif.b", // TriCore_INS_ABSDIF.B
"absdif.h", // TriCore_INS_ABSDIF.H
"absdif", // TriCore_INS_ABSDIF
"abss.b", // TriCore_INS_ABSS.B
"abss.h", // TriCore_INS_ABSS.H
"abss", // TriCore_INS_ABSS
"abs.b", // TriCore_INS_ABS.B
@ -22,6 +24,8 @@
"addi", // TriCore_INS_ADDI
"addsc.at", // TriCore_INS_ADDSC.AT
"addsc.a", // TriCore_INS_ADDSC.A
"adds.bu", // TriCore_INS_ADDS.BU
"adds.b", // TriCore_INS_ADDS.B
"adds.h", // TriCore_INS_ADDS.H
"adds.hu", // TriCore_INS_ADDS.HU
"adds.u", // TriCore_INS_ADDS.U
@ -238,6 +242,7 @@
"msub.h", // TriCore_INS_MSUB.H
"msub.q", // TriCore_INS_MSUB.Q
"msub", // TriCore_INS_MSUB
"mtcr", // TriCore_INS_MTCR
"mulm.h", // TriCore_INS_MULM.H
"mulr.h", // TriCore_INS_MULR.H
"mulr.q", // TriCore_INS_MULR.Q

5
include/capstone/inc/TriCoreGenCSInsnEnum.inc
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@ -6,11 +6,13 @@
/* Code generator: https://github_com/capstone-engine/capstone/tree/next/suite/auto-sync */
TriCore_INS_XOR_T,
TriCore_INS_ABSDIFS_B,
TriCore_INS_ABSDIFS_H,
TriCore_INS_ABSDIFS,
TriCore_INS_ABSDIF_B,
TriCore_INS_ABSDIF_H,
TriCore_INS_ABSDIF,
TriCore_INS_ABSS_B,
TriCore_INS_ABSS_H,
TriCore_INS_ABSS,
TriCore_INS_ABS_B,
@ -22,6 +24,8 @@
TriCore_INS_ADDI,
TriCore_INS_ADDSC_AT,
TriCore_INS_ADDSC_A,
TriCore_INS_ADDS_BU,
TriCore_INS_ADDS_B,
TriCore_INS_ADDS_H,
TriCore_INS_ADDS_HU,
TriCore_INS_ADDS_U,
@ -238,6 +242,7 @@
TriCore_INS_MSUB_H,
TriCore_INS_MSUB_Q,
TriCore_INS_MSUB,
TriCore_INS_MTCR,
TriCore_INS_MULM_H,
TriCore_INS_MULR_H,
TriCore_INS_MULR_Q,