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x86: printf64m should print qword ptr by default. TODO: fix related cases in tablegen instead

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This commit is contained in:
naq 2019-06-09 01:58:03 +08:00
parent 886c535a6e
commit 46c6aab052
3 changed files with 18 additions and 4 deletions
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4
MCInst.h
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@ -87,11 +87,11 @@ MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val);
/// MCInst - Instances of this class represent a single low-level machine
/// instruction.
struct MCInst {
unsigned OpcodePub;
unsigned OpcodePub; // public opcode (<arch>_INS_yyy in header files <arch>.h)
uint8_t size; // number of operands
bool has_imm; // indicate this instruction has an X86_OP_IMM operand - used for ATT syntax
uint8_t op1_size; // size of 1st operand - for X86 Intel syntax
unsigned Opcode;
unsigned Opcode; // private opcode
MCOperand Operands[48];
cs_insn *flat_insn; // insn to be exposed to public
uint64_t address; // address of this insn

14
arch/X86/X86IntelInstPrinter.c
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@ -230,8 +230,18 @@ static void printf64mem(MCInst *MI, unsigned OpNo, SStream *O)
{
// TODO: fix COMISD in Tablegen instead (#1456)
if (MI->op1_size == 16) {
SStream_concat0(O, "xmmword ptr ");
MI->x86opsize = 16;
// printf("printf64mem id = %u\n", MCInst_getOpcode(MI));
switch(MCInst_getOpcode(MI)) {
default:
SStream_concat0(O, "qword ptr ");
MI->x86opsize = 8;
break;
case X86_MOVPQI2QImr:
case X86_COMISDrm:
SStream_concat0(O, "xmmword ptr ");
MI->x86opsize = 16;
break;
}
} else {
SStream_concat0(O, "qword ptr ");
MI->x86opsize = 8;

4
suite/cstest/issues.cs
View File

@ -1,3 +1,7 @@
!# issue 1504 movhps qword ptr
!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0f,0x16,0x08 == movhps xmm1, qword ptr [rax] ; Opcode:0x0f 0x16 0x00 0x00
!# issue 1505 opcode 0f
!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0f,0xa5,0xc2 == shld edx, eax, cl ; Opcode:0x0f 0xa5 0x00 0x00