add the missing include/ppc.h

arch/PowerPC/PPCPredicates.h

@@ -19,7 +19,7 @@
 
 #include "../../include/ppc.h"
 
-// NOTE: duplicate of ppc_cc in ppc.h to maitain code compatibility with LLVM
+// NOTE: duplicate of ppc_bc in ppc.h to maitain code compatibility with LLVM
 typedef enum ppc_predicate {
   PPC_PRED_LT       = (0 << 5) | 12,
   PPC_PRED_LE       = (1 << 5) |  4,

bindings/python/test.py

@@ -15,6 +15,7 @@ THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
 MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
 MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00"
 ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
+PPC64_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80"
 
 all_tests = (
         (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0),
@@ -28,6 +29,7 @@ all_tests = (
         (CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
         (CS_ARCH_MIPS, CS_MODE_64+ CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0),
         (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", 0),
+        (CS_ARCH_PPC, CS_MODE_64 + CS_MODE_BIG_ENDIAN, PPC64_CODE, "PPC-64", 0),
         )
 
 

include/ppc.h

@@ -0,0 +1,106 @@
+#ifndef CS_PPC_H
+#define CS_PPC_H
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+
+//> Branch code for some branch instructions
+typedef enum ppc_bc {
+  PPC_BC_LT       = (0 << 5) | 12,
+  PPC_BC_LE       = (1 << 5) |  4,
+  PPC_BC_EQ       = (2 << 5) | 12,
+  PPC_BC_GE       = (0 << 5) |  4,
+  PPC_BC_GT       = (1 << 5) | 12,
+  PPC_BC_NE       = (2 << 5) |  4,
+  PPC_BC_UN       = (3 << 5) | 12,
+  PPC_BC_NU       = (3 << 5) |  4,
+  PPC_BC_LT_MINUS = (0 << 5) | 14,
+  PPC_BC_LE_MINUS = (1 << 5) |  6,
+  PPC_BC_EQ_MINUS = (2 << 5) | 14,
+  PPC_BC_GE_MINUS = (0 << 5) |  6,
+  PPC_BC_GT_MINUS = (1 << 5) | 14,
+  PPC_BC_NE_MINUS = (2 << 5) |  6,
+  PPC_BC_UN_MINUS = (3 << 5) | 14,
+  PPC_BC_NU_MINUS = (3 << 5) |  6,
+  PPC_BC_LT_PLUS  = (0 << 5) | 15,
+  PPC_BC_LE_PLUS  = (1 << 5) |  7,
+  PPC_BC_EQ_PLUS  = (2 << 5) | 15,
+  PPC_BC_GE_PLUS  = (0 << 5) |  7,
+  PPC_BC_GT_PLUS  = (1 << 5) | 15,
+  PPC_BC_NE_PLUS  = (2 << 5) |  7,
+  PPC_BC_UN_PLUS  = (3 << 5) | 15,
+  PPC_BC_NU_PLUS  = (3 << 5) |  7
+} ppc_bc;
+
+//> Operand type for instruction's operands
+typedef enum ppc_op_type {
+	PPC_OP_INVALID = 0,	// Uninitialized.
+	PPC_OP_REG,	// Register operand.
+	PPC_OP_IMM,	// Immediate operand.
+	PPC_OP_MEM,	// Memory operand
+} ppc_op_type;
+
+// Instruction's operand referring to memory
+// This is associated with PPC_OP_MEM operand type above
+typedef struct ppc_op_mem {
+	unsigned int base;	// base register
+	int64_t disp;	// displacement/offset value
+} ppc_op_mem;
+
+// Instruction operand
+typedef struct cs_ppc_op {
+	ppc_op_type type;	// operand type
+	union {
+		unsigned int reg;	// register value for REG operand
+		int64_t imm;		// immediate value for C-IMM or IMM operand
+		ppc_op_mem mem;		// base/index/scale/disp value for MEM operand
+	};
+} cs_ppc_op;
+
+// Instruction structure
+typedef struct cs_ppc {
+	// branch code for branch instructions
+	ppc_bc cc;
+
+	// Number of operands of this instruction, 
+	// or 0 when instruction has no operand.
+	uint8_t op_count;
+	cs_ppc_op operands[8]; // operands for this instruction.
+} cs_ppc;
+
+//> PPC registers
+typedef enum ppc_reg {
+	PPC_REG_INVALID = 0,
+	// General purpose registers
+
+	PPC_REG_MAX,	// <-- mark the end of the list or registers
+} ppc_reg;
+
+//> PPC instruction
+typedef enum ppc_insn {
+	PPC_INS_INVALID = 0,
+	PPC_INS_MAX,
+} ppc_insn;
+
+//> Group of PPC instructions
+typedef enum ppc_insn_group {
+	PPC_GRP_INVALID = 0,
+
+	PPC_GRP_JUMP,	// all jump instructions (conditional+direct+indirect jumps)
+
+	PPC_GRP_MAX,
+} ppc_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif