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Merge pull request #2507 from thestr4ng3r/no-varargs-aarch64
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AArch64: Replace vararg add_cs_detail by multiple concrete functions
This commit is contained in:
Rot127
GitHub
commit
5026c2c4e9
@ -905,8 +905,9 @@ bool printSyspAlias(MCInst *MI, SStream *O)
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void CONCAT(printMatrix, EltSize)(MCInst * MI, unsigned OpNum, \
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SStream *O) \
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{ \
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add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Matrix, EltSize), \
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OpNum, EltSize); \
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AArch64_add_cs_detail_1( \
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MI, CONCAT(AArch64_OP_GROUP_Matrix, EltSize), OpNum, \
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EltSize); \
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MCOperand *RegOp = MCInst_getOperand(MI, (OpNum)); \
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\
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printRegName(O, MCOperand_getReg(RegOp)); \
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@ -941,10 +942,10 @@ DEFINE_printMatrix(0);
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void CONCAT(printMatrixTileVector, \
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IsVertical)(MCInst * MI, unsigned OpNum, SStream *O) \
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{ \
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add_cs_detail(MI, \
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CONCAT(AArch64_OP_GROUP_MatrixTileVector, \
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IsVertical), \
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OpNum, IsVertical); \
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AArch64_add_cs_detail_1( \
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MI, \
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CONCAT(AArch64_OP_GROUP_MatrixTileVector, IsVertical), \
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OpNum, IsVertical); \
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MCOperand *RegOp = MCInst_getOperand(MI, (OpNum)); \
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\
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const char *RegName = getRegisterName(MCOperand_getReg(RegOp), \
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@ -970,7 +971,7 @@ DEFINE_printMatrixTileVector(1);
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void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_MatrixTile, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_MatrixTile, OpNum);
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MCOperand *RegOp = MCInst_getOperand(MI, (OpNum));
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printRegName(O, MCOperand_getReg(RegOp));
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@ -978,7 +979,7 @@ void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O)
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void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_SVCROp, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_SVCROp, OpNum);
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MCOperand *MO = MCInst_getOperand(MI, (OpNum));
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unsigned svcrop = MCOperand_getImm(MO);
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@ -989,7 +990,7 @@ void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O)
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void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_Operand, OpNo);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_Operand, OpNo);
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MCOperand *Op = MCInst_getOperand(MI, (OpNo));
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if (MCOperand_isReg(Op)) {
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unsigned Reg = MCOperand_getReg(Op);
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@ -1006,7 +1007,7 @@ void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
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void printImm(MCInst *MI, unsigned OpNo, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_Imm, OpNo);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_Imm, OpNo);
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MCOperand *Op = MCInst_getOperand(MI, (OpNo));
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SStream_concat(O, "%s", markup("<imm:"));
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printInt64Bang(O, MCOperand_getImm(Op));
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@ -1015,7 +1016,7 @@ void printImm(MCInst *MI, unsigned OpNo, SStream *O)
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void printImmHex(MCInst *MI, unsigned OpNo, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_ImmHex, OpNo);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_ImmHex, OpNo);
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MCOperand *Op = MCInst_getOperand(MI, (OpNo));
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SStream_concat(O, "%s", markup("<imm:"));
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printInt64Bang(O, MCOperand_getImm(Op));
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@ -1025,8 +1026,8 @@ void printImmHex(MCInst *MI, unsigned OpNo, SStream *O)
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#define DEFINE_printSImm(Size) \
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void CONCAT(printSImm, Size)(MCInst * MI, unsigned OpNo, SStream *O) \
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{ \
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add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SImm, Size), OpNo, \
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Size); \
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AArch64_add_cs_detail_1( \
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MI, CONCAT(AArch64_OP_GROUP_SImm, Size), OpNo, Size); \
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MCOperand *Op = MCInst_getOperand(MI, (OpNo)); \
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if (Size == 8) { \
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SStream_concat(O, "%s", markup("<imm:")); \
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@ -1062,7 +1063,7 @@ void printPostIncOperand(MCInst *MI, unsigned OpNo, unsigned Imm, SStream *O)
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void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_VRegOperand, OpNo);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_VRegOperand, OpNo);
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MCOperand *Op = MCInst_getOperand(MI, (OpNo));
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unsigned Reg = MCOperand_getReg(Op);
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@ -1071,7 +1072,7 @@ void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O)
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void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_SysCROperand, OpNo);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_SysCROperand, OpNo);
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MCOperand *Op = MCInst_getOperand(MI, (OpNo));
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SStream_concat(O, "%s", "c");
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@ -1081,7 +1082,7 @@ void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O)
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void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_AddSubImm, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_AddSubImm, OpNum);
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MCOperand *MO = MCInst_getOperand(MI, (OpNum));
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if (MCOperand_isImm(MO)) {
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unsigned Val = (MCOperand_getImm(MO) & 0xfff);
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@ -1103,8 +1104,8 @@ void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O)
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void CONCAT(printLogicalImm, T)(MCInst * MI, unsigned OpNum, \
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SStream *O) \
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{ \
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add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_LogicalImm, T), \
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OpNum, sizeof(T)); \
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AArch64_add_cs_detail_1( \
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MI, CONCAT(AArch64_OP_GROUP_LogicalImm, T), OpNum, sizeof(T)); \
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uint64_t Val = \
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MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \
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SStream_concat(O, "%s", markup("<imm:")); \
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@ -1119,7 +1120,7 @@ DEFINE_printLogicalImm(int16_t);
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void printShifter(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_Shifter, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_Shifter, OpNum);
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unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
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// LSL #0 should not be printed.
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if (AArch64_AM_getShiftType(Val) == AArch64_AM_LSL &&
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@ -1134,21 +1135,21 @@ void printShifter(MCInst *MI, unsigned OpNum, SStream *O)
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void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_ShiftedRegister, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_ShiftedRegister, OpNum);
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printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
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printShifter(MI, OpNum + 1, O);
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}
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void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_ExtendedRegister, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_ExtendedRegister, OpNum);
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printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
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printArithExtend(MI, OpNum + 1, O);
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}
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void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_ArithExtend, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_ArithExtend, OpNum);
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unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
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AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val);
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unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val);
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@ -1219,7 +1220,7 @@ void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
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CONCAT(ExtWidth, CONCAT(SrcRegKind, Suffix))))( \
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MCInst * MI, unsigned OpNum, SStream *O) \
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{ \
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add_cs_detail( \
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AArch64_add_cs_detail_4( \
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MI, \
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CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \
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SignExtend), \
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@ -1278,10 +1279,10 @@ DEFINE_printRegWithShiftExtend(false, 128, x, 0);
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void CONCAT(printPredicateAsCounter, \
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EltSize)(MCInst * MI, unsigned OpNum, SStream *O) \
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{ \
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add_cs_detail(MI, \
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CONCAT(AArch64_OP_GROUP_PredicateAsCounter, \
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EltSize), \
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OpNum, EltSize); \
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AArch64_add_cs_detail_1( \
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MI, \
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CONCAT(AArch64_OP_GROUP_PredicateAsCounter, EltSize), \
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OpNum, EltSize); \
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unsigned Reg = \
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MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \
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if (Reg < AArch64_PN0 || Reg > AArch64_PN15) \
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@ -1316,7 +1317,7 @@ DEFINE_printPredicateAsCounter(0);
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void printCondCode(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_CondCode, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_CondCode, OpNum);
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AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(
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MCInst_getOperand(MI, (OpNum)));
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SStream_concat0(O, AArch64CC_getCondCodeName(CC));
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@ -1324,7 +1325,7 @@ void printCondCode(MCInst *MI, unsigned OpNum, SStream *O)
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void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_InverseCondCode, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_InverseCondCode, OpNum);
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AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(
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MCInst_getOperand(MI, (OpNum)));
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SStream_concat0(O, AArch64CC_getCondCodeName(
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@ -1333,7 +1334,7 @@ void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O)
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void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_AMNoIndex, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_AMNoIndex, OpNum);
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SStream_concat0(O, "[");
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printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
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@ -1344,8 +1345,9 @@ void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O)
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void CONCAT(printImmScale, Scale)(MCInst * MI, unsigned OpNum, \
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SStream *O) \
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{ \
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add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ImmScale, Scale), \
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OpNum, Scale); \
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AArch64_add_cs_detail_1( \
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MI, CONCAT(AArch64_OP_GROUP_ImmScale, Scale), OpNum, \
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Scale); \
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SStream_concat(O, "%s", markup("<imm:")); \
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printInt32Bang(O, Scale *MCOperand_getImm( \
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MCInst_getOperand(MI, (OpNum)))); \
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@ -1362,7 +1364,7 @@ DEFINE_printImmScale(3);
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void CONCAT(printImmRangeScale, CONCAT(Scale, Offset))( \
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MCInst * MI, unsigned OpNum, SStream *O) \
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{ \
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add_cs_detail( \
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AArch64_add_cs_detail_2( \
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MI, \
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CONCAT(CONCAT(AArch64_OP_GROUP_ImmRangeScale, Scale), \
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Offset), \
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@ -1408,7 +1410,7 @@ void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O)
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void printRPRFMOperand(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_RPRFMOperand, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_RPRFMOperand, OpNum);
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unsigned prfop = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
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const AArch64PRFM_PRFM *PRFM =
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AArch64RPRFM_lookupRPRFMByEncoding(prfop);
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@ -1425,10 +1427,10 @@ void printRPRFMOperand(MCInst *MI, unsigned OpNum, SStream *O)
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void CONCAT(printPrefetchOp, \
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IsSVEPrefetch)(MCInst * MI, unsigned OpNum, SStream *O) \
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{ \
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add_cs_detail(MI, \
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CONCAT(AArch64_OP_GROUP_PrefetchOp, \
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IsSVEPrefetch), \
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OpNum, IsSVEPrefetch); \
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AArch64_add_cs_detail_1(MI, \
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CONCAT(AArch64_OP_GROUP_PrefetchOp, \
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IsSVEPrefetch), \
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OpNum, IsSVEPrefetch); \
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unsigned prfop = \
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MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \
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if (IsSVEPrefetch) { \
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@ -1458,7 +1460,7 @@ DEFINE_printPrefetchOp(true);
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void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_PSBHintOp, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_PSBHintOp, OpNum);
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unsigned psbhintop = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
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const AArch64PSBHint_PSB *PSB =
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AArch64PSBHint_lookupPSBByEncoding(psbhintop);
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@ -1474,7 +1476,7 @@ void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O)
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void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_BTIHintOp, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_BTIHintOp, OpNum);
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unsigned btihintop = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))) ^
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32;
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const AArch64BTIHint_BTI *BTI =
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@ -1490,7 +1492,7 @@ void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O)
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static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, AArch64_OP_GROUP_FPImmOperand, OpNum);
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AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_FPImmOperand, OpNum);
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MCOperand *MO = MCInst_getOperand(MI, (OpNum));
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float FPImm = MCOperand_isDFPImm(MO) ?
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BitsToDouble(MCOperand_getImm(MO)) :
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@ -1760,10 +1762,11 @@ static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride /* = 1 */)
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void CONCAT(printGPRSeqPairsClassOperand, \
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size)(MCInst * MI, unsigned OpNum, SStream *O) \
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{ \
|
||||
add_cs_detail(MI, \
|
||||
CONCAT(AArch64_OP_GROUP_GPRSeqPairsClassOperand, \
|
||||
size), \
|
||||
OpNum, size); \
|
||||
AArch64_add_cs_detail_1( \
|
||||
MI, \
|
||||
CONCAT(AArch64_OP_GROUP_GPRSeqPairsClassOperand, \
|
||||
size), \
|
||||
OpNum, size); \
|
||||
CS_ASSERT_RET((size == 64 || size == 32) && \
|
||||
"Template parameter must be either 32 or 64"); \
|
||||
unsigned Reg = \
|
||||
@ -1787,7 +1790,7 @@ DEFINE_printGPRSeqPairsClassOperand(64);
|
||||
void CONCAT(printMatrixIndex, Scale)(MCInst * MI, unsigned OpNum, \
|
||||
SStream *O) \
|
||||
{ \
|
||||
add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_MatrixIndex, Scale), \
|
||||
AArch64_add_cs_detail_1(MI, CONCAT(AArch64_OP_GROUP_MatrixIndex, Scale), \
|
||||
OpNum, Scale); \
|
||||
printInt64(O, Scale *MCOperand_getImm( \
|
||||
MCInst_getOperand(MI, (OpNum)))); \
|
||||
@ -1798,7 +1801,7 @@ DEFINE_printMatrixIndex(1);
|
||||
|
||||
void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_MatrixTileList, OpNum);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_MatrixTileList, OpNum);
|
||||
unsigned MaxRegs = 8;
|
||||
unsigned RegMask = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
|
||||
|
||||
@ -1957,7 +1960,8 @@ void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
|
||||
|
||||
void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_ImplicitlyTypedVectorList, OpNum);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_ImplicitlyTypedVectorList,
|
||||
OpNum);
|
||||
printVectorList(MI, OpNum, O, "");
|
||||
}
|
||||
|
||||
@ -1965,11 +1969,12 @@ void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
void CONCAT(printTypedVectorList, CONCAT(NumLanes, LaneKind))( \
|
||||
MCInst * MI, unsigned OpNum, SStream *O) \
|
||||
{ \
|
||||
add_cs_detail(MI, \
|
||||
CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \
|
||||
NumLanes), \
|
||||
LaneKind), \
|
||||
OpNum, NumLanes, CHAR(LaneKind)); \
|
||||
AArch64_add_cs_detail_2( \
|
||||
MI, \
|
||||
CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \
|
||||
NumLanes), \
|
||||
LaneKind), \
|
||||
OpNum, NumLanes, CHAR(LaneKind)); \
|
||||
if (CHAR(LaneKind) == '0') { \
|
||||
printVectorList(MI, OpNum, O, ""); \
|
||||
return; \
|
||||
@ -2003,8 +2008,9 @@ DEFINE_printTypedVectorList(0, 0);
|
||||
void CONCAT(printVectorIndex, Scale)(MCInst * MI, unsigned OpNum, \
|
||||
SStream *O) \
|
||||
{ \
|
||||
add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_VectorIndex, Scale), \
|
||||
OpNum, Scale); \
|
||||
AArch64_add_cs_detail_1( \
|
||||
MI, CONCAT(AArch64_OP_GROUP_VectorIndex, Scale), \
|
||||
OpNum, Scale); \
|
||||
SStream_concat(O, "%s", "["); \
|
||||
printUInt64(O, Scale *MCOperand_getImm( \
|
||||
MCInst_getOperand(MI, (OpNum)))); \
|
||||
@ -2015,7 +2021,7 @@ DEFINE_printVectorIndex(8);
|
||||
|
||||
void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_AlignedLabel, OpNum);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_AlignedLabel, OpNum);
|
||||
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
|
||||
|
||||
// If the label has already been resolved to an immediate offset (say, when
|
||||
@ -2037,7 +2043,7 @@ void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
|
||||
|
||||
void printAdrLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_AdrLabel, OpNum);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_AdrLabel, OpNum);
|
||||
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
|
||||
|
||||
// If the label has already been resolved to an immediate offset (say, when
|
||||
@ -2059,7 +2065,7 @@ void printAdrLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
|
||||
|
||||
void printAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_AdrpLabel, OpNum);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_AdrpLabel, OpNum);
|
||||
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
|
||||
|
||||
// If the label has already been resolved to an immediate offset (say, when
|
||||
@ -2080,7 +2086,7 @@ void printAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
|
||||
}
|
||||
|
||||
void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) {
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_AdrAdrpLabel, OpNum);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_AdrAdrpLabel, OpNum);
|
||||
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
|
||||
|
||||
// If the label has already been resolved to an immediate offset (say, when
|
||||
@ -2106,7 +2112,7 @@ void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
|
||||
|
||||
void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_BarrierOption, OpNo);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_BarrierOption, OpNo);
|
||||
unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
unsigned Opcode = MCInst_getOpcode(MI);
|
||||
|
||||
@ -2132,7 +2138,7 @@ void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
|
||||
void printBarriernXSOption(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_BarriernXSOption, OpNo);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_BarriernXSOption, OpNo);
|
||||
unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
|
||||
const char *Name;
|
||||
@ -2174,7 +2180,7 @@ static const AArch64SysReg_SysReg *lookupSysReg(unsigned Val, bool Read,
|
||||
|
||||
void printMRSSystemRegister(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_MRSSystemRegister, OpNo);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_MRSSystemRegister, OpNo);
|
||||
unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
|
||||
// Horrible hack for the one register that has identical encodings but
|
||||
@ -2205,7 +2211,7 @@ void printMRSSystemRegister(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
|
||||
void printMSRSystemRegister(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_MSRSystemRegister, OpNo);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_MSRSystemRegister, OpNo);
|
||||
unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
|
||||
// Horrible hack for the one register that has identical encodings but
|
||||
@ -2236,7 +2242,7 @@ void printMSRSystemRegister(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
|
||||
void printSystemPStateField(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_SystemPStateField, OpNo);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_SystemPStateField, OpNo);
|
||||
unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
|
||||
const AArch64PState_PStateImm0_15 *PStateImm15 =
|
||||
@ -2259,7 +2265,7 @@ void printSystemPStateField(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
|
||||
void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_SIMDType10Operand, OpNo);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_SIMDType10Operand, OpNo);
|
||||
unsigned RawVal = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal);
|
||||
SStream_concat(O, "%s#%#016llx", markup("<imm:"), Val);
|
||||
@ -2270,7 +2276,7 @@ void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
static void CONCAT(printComplexRotationOp, CONCAT(Angle, Remainder))( \
|
||||
MCInst * MI, unsigned OpNo, SStream *O) \
|
||||
{ \
|
||||
add_cs_detail( \
|
||||
AArch64_add_cs_detail_2( \
|
||||
MI, \
|
||||
CONCAT(CONCAT(AArch64_OP_GROUP_ComplexRotationOp, \
|
||||
Angle), \
|
||||
@ -2287,7 +2293,7 @@ DEFINE_printComplexRotationOp(90, 0);
|
||||
|
||||
void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_SVEPattern, OpNum);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_SVEPattern, OpNum);
|
||||
unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
|
||||
const AArch64SVEPredPattern_SVEPREDPAT *Pat =
|
||||
AArch64SVEPredPattern_lookupSVEPREDPATByEncoding(Val);
|
||||
@ -2299,7 +2305,7 @@ void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
|
||||
void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_SVEVecLenSpecifier, OpNum);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_SVEVecLenSpecifier, OpNum);
|
||||
unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
|
||||
// Pattern has only 1 bit
|
||||
if (Val > 1)
|
||||
@ -2315,8 +2321,9 @@ void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
void CONCAT(printSVERegOp, suffix)(MCInst * MI, unsigned OpNum, \
|
||||
SStream *O) \
|
||||
{ \
|
||||
add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVERegOp, suffix), \
|
||||
OpNum, CHAR(suffix)); \
|
||||
AArch64_add_cs_detail_1( \
|
||||
MI, CONCAT(AArch64_OP_GROUP_SVERegOp, suffix), OpNum, \
|
||||
CHAR(suffix)); \
|
||||
switch (CHAR(suffix)) { \
|
||||
case '0': \
|
||||
case 'b': \
|
||||
@ -2394,8 +2401,8 @@ DEFINE_isSignedType(uint64_t);
|
||||
void CONCAT(printImm8OptLsl, T)(MCInst * MI, unsigned OpNum, \
|
||||
SStream *O) \
|
||||
{ \
|
||||
add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Imm8OptLsl, T), \
|
||||
OpNum, sizeof(T)); \
|
||||
AArch64_add_cs_detail_1( \
|
||||
MI, CONCAT(AArch64_OP_GROUP_Imm8OptLsl, T), OpNum, sizeof(T)); \
|
||||
unsigned UnscaledVal = \
|
||||
MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \
|
||||
unsigned Shift = \
|
||||
@ -2434,8 +2441,9 @@ DEFINE_printImm8OptLsl(uint32_t);
|
||||
void CONCAT(printSVELogicalImm, T)(MCInst * MI, unsigned OpNum, \
|
||||
SStream *O) \
|
||||
{ \
|
||||
add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVELogicalImm, T), \
|
||||
OpNum, sizeof(T)); \
|
||||
AArch64_add_cs_detail_1( \
|
||||
MI, CONCAT(AArch64_OP_GROUP_SVELogicalImm, T), OpNum, \
|
||||
sizeof(T)); \
|
||||
typedef T SignedT; \
|
||||
typedef CONCATS(u, T) UnsignedT; \
|
||||
\
|
||||
@ -2462,8 +2470,9 @@ DEFINE_printSVELogicalImm(int64_t);
|
||||
void CONCAT(printZPRasFPR, Width)(MCInst * MI, unsigned OpNum, \
|
||||
SStream *O) \
|
||||
{ \
|
||||
add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ZPRasFPR, Width), \
|
||||
OpNum, Width); \
|
||||
AArch64_add_cs_detail_1( \
|
||||
MI, CONCAT(AArch64_OP_GROUP_ZPRasFPR, Width), OpNum, \
|
||||
Width); \
|
||||
unsigned Base; \
|
||||
switch (Width) { \
|
||||
case 8: \
|
||||
@ -2498,7 +2507,7 @@ DEFINE_printZPRasFPR(128);
|
||||
void CONCAT(printExactFPImm, CONCAT(ImmIs0, ImmIs1))( \
|
||||
MCInst * MI, unsigned OpNum, SStream *O) \
|
||||
{ \
|
||||
add_cs_detail( \
|
||||
AArch64_add_cs_detail_2( \
|
||||
MI, \
|
||||
CONCAT(CONCAT(AArch64_OP_GROUP_ExactFPImm, ImmIs0), \
|
||||
ImmIs1), \
|
||||
@ -2519,14 +2528,14 @@ DEFINE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_two);
|
||||
|
||||
void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_GPR64as32, OpNum);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_GPR64as32, OpNum);
|
||||
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));
|
||||
printRegName(O, getWRegFromXReg(Reg));
|
||||
}
|
||||
|
||||
void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_GPR64x8, OpNum);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_GPR64x8, OpNum);
|
||||
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));
|
||||
printRegName(O,
|
||||
MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_x8sub_0));
|
||||
@ -2534,7 +2543,7 @@ void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
|
||||
void printSyspXzrPair(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_SyspXzrPair, OpNum);
|
||||
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_SyspXzrPair, OpNum);
|
||||
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));
|
||||
|
||||
SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_NoRegAltName),
|
||||
|
||||
@ -76,7 +76,7 @@ void printPostIncOperand(MCInst *MI, unsigned OpNo, unsigned Imm, SStream *O);
|
||||
static inline void CONCAT(printPostIncOperand, Amount)( \
|
||||
MCInst * MI, unsigned OpNo, SStream *O) \
|
||||
{ \
|
||||
add_cs_detail(MI, \
|
||||
AArch64_add_cs_detail_1(MI, \
|
||||
CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
|
||||
OpNo, Amount); \
|
||||
printPostIncOperand(MI, OpNo, Amount, O); \
|
||||
@ -118,7 +118,7 @@ void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
|
||||
static inline void CONCAT(printMemExtend, CONCAT(SrcRegKind, Width))( \
|
||||
MCInst * MI, unsigned OpNum, SStream *O) \
|
||||
{ \
|
||||
add_cs_detail( \
|
||||
AArch64_add_cs_detail_2( \
|
||||
MI, \
|
||||
CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
|
||||
Width), \
|
||||
@ -182,7 +182,7 @@ void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
|
||||
static inline void CONCAT(printUImm12Offset, Scale)( \
|
||||
MCInst * MI, unsigned OpNum, SStream *O) \
|
||||
{ \
|
||||
add_cs_detail(MI, \
|
||||
AArch64_add_cs_detail_1(MI, \
|
||||
CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
|
||||
OpNum, Scale); \
|
||||
printUImm12Offset(MI, OpNum, Scale, O); \
|
||||
|
||||
@ -1281,13 +1281,29 @@ void AArch64_set_mem_access(MCInst *MI, bool status)
|
||||
}
|
||||
}
|
||||
|
||||
/// Common prefix for all AArch64_add_cs_detail_* functions
|
||||
static bool add_cs_detail_begin(MCInst *MI, unsigned op_num)
|
||||
{
|
||||
if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
|
||||
return false;
|
||||
|
||||
if (AArch64_get_detail(MI)->is_doing_sme) {
|
||||
// Unset the flag if there is no bound operand anymore.
|
||||
if (!(map_get_op_type(MI, op_num) & CS_OP_BOUND)) {
|
||||
AArch64_get_detail(MI)->is_doing_sme = false;
|
||||
AArch64_inc_op_count(MI);
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
/// Fills cs_detail with the data of the operand.
|
||||
/// This function handles operands which's original printer function has no
|
||||
/// specialities.
|
||||
static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group,
|
||||
void AArch64_add_cs_detail_0(MCInst *MI, aarch64_op_group op_group,
|
||||
unsigned OpNum)
|
||||
{
|
||||
if (!detail_is_set(MI))
|
||||
if (!add_cs_detail_begin(MI, OpNum))
|
||||
return;
|
||||
|
||||
// Fill cs_detail
|
||||
@ -1501,7 +1517,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group,
|
||||
break;
|
||||
case AArch64_OP_GROUP_ImplicitlyTypedVectorList:
|
||||
// The TypedVectorList implements the logic of implicitly typed operand.
|
||||
add_cs_detail(MI, AArch64_OP_GROUP_TypedVectorList_0_b, OpNum,
|
||||
AArch64_add_cs_detail_2(MI, AArch64_OP_GROUP_TypedVectorList_0_b, OpNum,
|
||||
0, 0);
|
||||
break;
|
||||
case AArch64_OP_GROUP_InverseCondCode: {
|
||||
@ -1724,10 +1740,10 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group,
|
||||
/// Fills cs_detail with the data of the operand.
|
||||
/// This function handles operands which original printer function is a template
|
||||
/// with one argument.
|
||||
static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group,
|
||||
void AArch64_add_cs_detail_1(MCInst *MI, aarch64_op_group op_group,
|
||||
unsigned OpNum, uint64_t temp_arg_0)
|
||||
{
|
||||
if (!detail_is_set(MI))
|
||||
if (!add_cs_detail_begin(MI, OpNum))
|
||||
return;
|
||||
switch (op_group) {
|
||||
default:
|
||||
@ -2052,11 +2068,11 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group,
|
||||
/// Fills cs_detail with the data of the operand.
|
||||
/// This function handles operands which original printer function is a template
|
||||
/// with two arguments.
|
||||
static void add_cs_detail_template_2(MCInst *MI, aarch64_op_group op_group,
|
||||
void AArch64_add_cs_detail_2(MCInst *MI, aarch64_op_group op_group,
|
||||
unsigned OpNum, uint64_t temp_arg_0,
|
||||
uint64_t temp_arg_1)
|
||||
{
|
||||
if (!detail_is_set(MI))
|
||||
if (!add_cs_detail_begin(MI, OpNum))
|
||||
return;
|
||||
switch (op_group) {
|
||||
default:
|
||||
@ -2235,12 +2251,12 @@ static void add_cs_detail_template_2(MCInst *MI, aarch64_op_group op_group,
|
||||
/// Fills cs_detail with the data of the operand.
|
||||
/// This function handles operands which original printer function is a template
|
||||
/// with four arguments.
|
||||
static void add_cs_detail_template_4(MCInst *MI, aarch64_op_group op_group,
|
||||
void AArch64_add_cs_detail_4(MCInst *MI, aarch64_op_group op_group,
|
||||
unsigned OpNum, uint64_t temp_arg_0,
|
||||
uint64_t temp_arg_1, uint64_t temp_arg_2,
|
||||
uint64_t temp_arg_3)
|
||||
{
|
||||
if (!detail_is_set(MI))
|
||||
if (!add_cs_detail_begin(MI, OpNum))
|
||||
return;
|
||||
switch (op_group) {
|
||||
default:
|
||||
@ -2302,216 +2318,6 @@ static void add_cs_detail_template_4(MCInst *MI, aarch64_op_group op_group,
|
||||
}
|
||||
}
|
||||
|
||||
void AArch64_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
|
||||
va_list args)
|
||||
{
|
||||
if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
|
||||
return;
|
||||
|
||||
unsigned op_num = va_arg(args, unsigned);
|
||||
if (AArch64_get_detail(MI)->is_doing_sme) {
|
||||
// Unset the flag if there is no bound operand anymore.
|
||||
if (!(map_get_op_type(MI, op_num) & CS_OP_BOUND)) {
|
||||
AArch64_get_detail(MI)->is_doing_sme = false;
|
||||
AArch64_inc_op_count(MI);
|
||||
}
|
||||
}
|
||||
|
||||
switch (op_group) {
|
||||
default:
|
||||
printf("Operand group %d not handled\n", op_group);
|
||||
break;
|
||||
case AArch64_OP_GROUP_AddSubImm:
|
||||
case AArch64_OP_GROUP_AdrLabel:
|
||||
case AArch64_OP_GROUP_AdrpLabel:
|
||||
case AArch64_OP_GROUP_AdrAdrpLabel:
|
||||
case AArch64_OP_GROUP_AlignedLabel:
|
||||
case AArch64_OP_GROUP_AMNoIndex:
|
||||
case AArch64_OP_GROUP_ArithExtend:
|
||||
case AArch64_OP_GROUP_BarriernXSOption:
|
||||
case AArch64_OP_GROUP_BarrierOption:
|
||||
case AArch64_OP_GROUP_BTIHintOp:
|
||||
case AArch64_OP_GROUP_CondCode:
|
||||
case AArch64_OP_GROUP_ExtendedRegister:
|
||||
case AArch64_OP_GROUP_FPImmOperand:
|
||||
case AArch64_OP_GROUP_GPR64as32:
|
||||
case AArch64_OP_GROUP_GPR64x8:
|
||||
case AArch64_OP_GROUP_Imm:
|
||||
case AArch64_OP_GROUP_ImmHex:
|
||||
case AArch64_OP_GROUP_ImplicitlyTypedVectorList:
|
||||
case AArch64_OP_GROUP_InverseCondCode:
|
||||
case AArch64_OP_GROUP_MatrixTile:
|
||||
case AArch64_OP_GROUP_MatrixTileList:
|
||||
case AArch64_OP_GROUP_MRSSystemRegister:
|
||||
case AArch64_OP_GROUP_MSRSystemRegister:
|
||||
case AArch64_OP_GROUP_Operand:
|
||||
case AArch64_OP_GROUP_PSBHintOp:
|
||||
case AArch64_OP_GROUP_RPRFMOperand:
|
||||
case AArch64_OP_GROUP_ShiftedRegister:
|
||||
case AArch64_OP_GROUP_Shifter:
|
||||
case AArch64_OP_GROUP_SIMDType10Operand:
|
||||
case AArch64_OP_GROUP_SVCROp:
|
||||
case AArch64_OP_GROUP_SVEPattern:
|
||||
case AArch64_OP_GROUP_SVEVecLenSpecifier:
|
||||
case AArch64_OP_GROUP_SysCROperand:
|
||||
case AArch64_OP_GROUP_SyspXzrPair:
|
||||
case AArch64_OP_GROUP_SystemPStateField:
|
||||
case AArch64_OP_GROUP_VRegOperand: {
|
||||
add_cs_detail_general(MI, op_group, op_num);
|
||||
break;
|
||||
}
|
||||
case AArch64_OP_GROUP_GPRSeqPairsClassOperand_32:
|
||||
case AArch64_OP_GROUP_GPRSeqPairsClassOperand_64:
|
||||
case AArch64_OP_GROUP_Imm8OptLsl_int16_t:
|
||||
case AArch64_OP_GROUP_Imm8OptLsl_int32_t:
|
||||
case AArch64_OP_GROUP_Imm8OptLsl_int64_t:
|
||||
case AArch64_OP_GROUP_Imm8OptLsl_int8_t:
|
||||
case AArch64_OP_GROUP_Imm8OptLsl_uint16_t:
|
||||
case AArch64_OP_GROUP_Imm8OptLsl_uint32_t:
|
||||
case AArch64_OP_GROUP_Imm8OptLsl_uint64_t:
|
||||
case AArch64_OP_GROUP_Imm8OptLsl_uint8_t:
|
||||
case AArch64_OP_GROUP_ImmScale_16:
|
||||
case AArch64_OP_GROUP_ImmScale_2:
|
||||
case AArch64_OP_GROUP_ImmScale_3:
|
||||
case AArch64_OP_GROUP_ImmScale_32:
|
||||
case AArch64_OP_GROUP_ImmScale_4:
|
||||
case AArch64_OP_GROUP_ImmScale_8:
|
||||
case AArch64_OP_GROUP_LogicalImm_int16_t:
|
||||
case AArch64_OP_GROUP_LogicalImm_int32_t:
|
||||
case AArch64_OP_GROUP_LogicalImm_int64_t:
|
||||
case AArch64_OP_GROUP_LogicalImm_int8_t:
|
||||
case AArch64_OP_GROUP_Matrix_0:
|
||||
case AArch64_OP_GROUP_Matrix_16:
|
||||
case AArch64_OP_GROUP_Matrix_32:
|
||||
case AArch64_OP_GROUP_Matrix_64:
|
||||
case AArch64_OP_GROUP_MatrixIndex_0:
|
||||
case AArch64_OP_GROUP_MatrixIndex_1:
|
||||
case AArch64_OP_GROUP_MatrixIndex_8:
|
||||
case AArch64_OP_GROUP_MatrixTileVector_0:
|
||||
case AArch64_OP_GROUP_MatrixTileVector_1:
|
||||
case AArch64_OP_GROUP_PostIncOperand_1:
|
||||
case AArch64_OP_GROUP_PostIncOperand_12:
|
||||
case AArch64_OP_GROUP_PostIncOperand_16:
|
||||
case AArch64_OP_GROUP_PostIncOperand_2:
|
||||
case AArch64_OP_GROUP_PostIncOperand_24:
|
||||
case AArch64_OP_GROUP_PostIncOperand_3:
|
||||
case AArch64_OP_GROUP_PostIncOperand_32:
|
||||
case AArch64_OP_GROUP_PostIncOperand_4:
|
||||
case AArch64_OP_GROUP_PostIncOperand_48:
|
||||
case AArch64_OP_GROUP_PostIncOperand_6:
|
||||
case AArch64_OP_GROUP_PostIncOperand_64:
|
||||
case AArch64_OP_GROUP_PostIncOperand_8:
|
||||
case AArch64_OP_GROUP_PredicateAsCounter_0:
|
||||
case AArch64_OP_GROUP_PredicateAsCounter_16:
|
||||
case AArch64_OP_GROUP_PredicateAsCounter_32:
|
||||
case AArch64_OP_GROUP_PredicateAsCounter_64:
|
||||
case AArch64_OP_GROUP_PredicateAsCounter_8:
|
||||
case AArch64_OP_GROUP_PrefetchOp_0:
|
||||
case AArch64_OP_GROUP_PrefetchOp_1:
|
||||
case AArch64_OP_GROUP_SImm_16:
|
||||
case AArch64_OP_GROUP_SImm_8:
|
||||
case AArch64_OP_GROUP_SVELogicalImm_int16_t:
|
||||
case AArch64_OP_GROUP_SVELogicalImm_int32_t:
|
||||
case AArch64_OP_GROUP_SVELogicalImm_int64_t:
|
||||
case AArch64_OP_GROUP_SVERegOp_0:
|
||||
case AArch64_OP_GROUP_SVERegOp_b:
|
||||
case AArch64_OP_GROUP_SVERegOp_d:
|
||||
case AArch64_OP_GROUP_SVERegOp_h:
|
||||
case AArch64_OP_GROUP_SVERegOp_q:
|
||||
case AArch64_OP_GROUP_SVERegOp_s:
|
||||
case AArch64_OP_GROUP_UImm12Offset_1:
|
||||
case AArch64_OP_GROUP_UImm12Offset_16:
|
||||
case AArch64_OP_GROUP_UImm12Offset_2:
|
||||
case AArch64_OP_GROUP_UImm12Offset_4:
|
||||
case AArch64_OP_GROUP_UImm12Offset_8:
|
||||
case AArch64_OP_GROUP_VectorIndex_1:
|
||||
case AArch64_OP_GROUP_VectorIndex_8:
|
||||
case AArch64_OP_GROUP_ZPRasFPR_128:
|
||||
case AArch64_OP_GROUP_ZPRasFPR_16:
|
||||
case AArch64_OP_GROUP_ZPRasFPR_32:
|
||||
case AArch64_OP_GROUP_ZPRasFPR_64:
|
||||
case AArch64_OP_GROUP_ZPRasFPR_8: {
|
||||
uint64_t temp_arg_0 = va_arg(args, uint64_t);
|
||||
add_cs_detail_template_1(MI, op_group, op_num, temp_arg_0);
|
||||
break;
|
||||
}
|
||||
case AArch64_OP_GROUP_ComplexRotationOp_180_90:
|
||||
case AArch64_OP_GROUP_ComplexRotationOp_90_0:
|
||||
case AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_one:
|
||||
case AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_two:
|
||||
case AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_zero_AArch64ExactFPImm_one:
|
||||
case AArch64_OP_GROUP_ImmRangeScale_2_1:
|
||||
case AArch64_OP_GROUP_ImmRangeScale_4_3:
|
||||
case AArch64_OP_GROUP_MemExtend_w_128:
|
||||
case AArch64_OP_GROUP_MemExtend_w_16:
|
||||
case AArch64_OP_GROUP_MemExtend_w_32:
|
||||
case AArch64_OP_GROUP_MemExtend_w_64:
|
||||
case AArch64_OP_GROUP_MemExtend_w_8:
|
||||
case AArch64_OP_GROUP_MemExtend_x_128:
|
||||
case AArch64_OP_GROUP_MemExtend_x_16:
|
||||
case AArch64_OP_GROUP_MemExtend_x_32:
|
||||
case AArch64_OP_GROUP_MemExtend_x_64:
|
||||
case AArch64_OP_GROUP_MemExtend_x_8:
|
||||
case AArch64_OP_GROUP_TypedVectorList_0_b:
|
||||
case AArch64_OP_GROUP_TypedVectorList_0_d:
|
||||
case AArch64_OP_GROUP_TypedVectorList_0_h:
|
||||
case AArch64_OP_GROUP_TypedVectorList_0_q:
|
||||
case AArch64_OP_GROUP_TypedVectorList_0_s:
|
||||
case AArch64_OP_GROUP_TypedVectorList_0_0:
|
||||
case AArch64_OP_GROUP_TypedVectorList_16_b:
|
||||
case AArch64_OP_GROUP_TypedVectorList_1_d:
|
||||
case AArch64_OP_GROUP_TypedVectorList_2_d:
|
||||
case AArch64_OP_GROUP_TypedVectorList_2_s:
|
||||
case AArch64_OP_GROUP_TypedVectorList_4_h:
|
||||
case AArch64_OP_GROUP_TypedVectorList_4_s:
|
||||
case AArch64_OP_GROUP_TypedVectorList_8_b:
|
||||
case AArch64_OP_GROUP_TypedVectorList_8_h: {
|
||||
uint64_t temp_arg_0 = va_arg(args, uint64_t);
|
||||
uint64_t temp_arg_1 = va_arg(args, uint64_t);
|
||||
add_cs_detail_template_2(MI, op_group, op_num, temp_arg_0,
|
||||
temp_arg_1);
|
||||
break;
|
||||
}
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_128_x_0:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_d:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_s:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_0:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_d:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_s:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_d:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_s:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_0:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_d:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_s:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_d:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_s:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_0:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_d:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_s:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_d:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_s:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_0:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_d:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_s:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_d:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_s:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_d:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_s:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_d:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_s:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_d:
|
||||
case AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_s: {
|
||||
uint64_t temp_arg_0 = va_arg(args, uint64_t);
|
||||
uint64_t temp_arg_1 = va_arg(args, uint64_t);
|
||||
uint64_t temp_arg_2 = va_arg(args, uint64_t);
|
||||
uint64_t temp_arg_3 = va_arg(args, uint64_t);
|
||||
add_cs_detail_template_4(MI, op_group, op_num, temp_arg_0,
|
||||
temp_arg_1, temp_arg_2, temp_arg_3);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Adds a register AArch64 operand at position OpNum and increases the op_count by
|
||||
/// one.
|
||||
void AArch64_set_detail_op_reg(MCInst *MI, unsigned OpNum, aarch64_reg Reg)
|
||||
|
||||
@ -36,19 +36,17 @@ void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read,
|
||||
uint8_t *regs_read_count, cs_regs regs_write,
|
||||
uint8_t *regs_write_count);
|
||||
|
||||
void AArch64_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
|
||||
va_list args);
|
||||
|
||||
static inline void add_cs_detail(MCInst *MI,
|
||||
int /* aarch64_op_group */ op_group, ...)
|
||||
{
|
||||
if (!MI->flat_insn->detail)
|
||||
return;
|
||||
va_list args;
|
||||
va_start(args, op_group);
|
||||
AArch64_add_cs_detail(MI, op_group, args);
|
||||
va_end(args);
|
||||
}
|
||||
void AArch64_add_cs_detail_0(MCInst *MI, aarch64_op_group op_group,
|
||||
unsigned OpNum);
|
||||
void AArch64_add_cs_detail_1(MCInst *MI, aarch64_op_group op_group,
|
||||
unsigned OpNum, uint64_t temp_arg_0);
|
||||
void AArch64_add_cs_detail_2(MCInst *MI, aarch64_op_group op_group,
|
||||
unsigned OpNum, uint64_t temp_arg_0,
|
||||
uint64_t temp_arg_1);
|
||||
void AArch64_add_cs_detail_4(MCInst *MI, aarch64_op_group op_group,
|
||||
unsigned OpNum, uint64_t temp_arg_0,
|
||||
uint64_t temp_arg_1, uint64_t temp_arg_2,
|
||||
uint64_t temp_arg_3);
|
||||
|
||||
void AArch64_init_mri(MCRegisterInfo *MRI);
|
||||
|
||||
|
||||
@ -117,7 +117,7 @@ class TestPatches(unittest.TestCase):
|
||||
patch,
|
||||
syntax,
|
||||
b"static inline void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNo, SStream *O){ "
|
||||
b"add_cs_detail(MI, ARCH_OP_GROUP_ThumbLdrLabelOperand, OpNo); "
|
||||
b"ARCH_add_cs_detail_0(MI, ARCH_OP_GROUP_ThumbLdrLabelOperand, OpNo); "
|
||||
b"int i = OpNo; "
|
||||
b"}",
|
||||
)
|
||||
|
||||
@ -16,17 +16,17 @@ from autosync.cpptranslator.patches.Patch import Patch
|
||||
|
||||
class AddCSDetail(Patch):
|
||||
"""
|
||||
Adds calls to `add_cs_detail()` for printOperand functions in <ARCH>InstPrinter.c
|
||||
Adds calls to `<ARCH>_add_cs_detail_<n>()` for printOperand functions in <ARCH>InstPrinter.c
|
||||
|
||||
Patch void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNo, SStream *O) {...}
|
||||
to void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNo, SStream *O) {
|
||||
add_cs_detail(MI, ARM_OP_GROUP_ThumbLdrLabelOperand, ...);
|
||||
<ARCH>_add_cs_detail_<n>(MI, ARM_OP_GROUP_ThumbLdrLabelOperand, ...);
|
||||
...
|
||||
}
|
||||
"""
|
||||
|
||||
# TODO Simply checking for the passed types would be so much nicer.
|
||||
# Parameter lists of printOperand() functions we need to add `add_cs_detail()` to.
|
||||
# Parameter lists of printOperand() functions we need to add `<ARCH>_add_cs_detail_<n>()` to.
|
||||
# Spaces are removed, so we only need to check the letters.
|
||||
valid_param_lists = [
|
||||
b"(MCInst*MI,unsignedOpNum,SStream*O)", # Default printOperand parameters.
|
||||
@ -59,7 +59,9 @@ class AddCSDetail(Patch):
|
||||
def get_main_capture_name(self) -> str:
|
||||
return "print_op"
|
||||
|
||||
def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
|
||||
def get_patch(
|
||||
self, captures: list[tuple[Node, str]], src: bytes, **kwargs
|
||||
) -> bytes:
|
||||
fcn_def: Node = captures[0][0]
|
||||
params = captures[2][0]
|
||||
params = get_text(src, params.start_byte, params.end_byte)
|
||||
@ -105,7 +107,7 @@ class AddCSDetail(Patch):
|
||||
# Standard printOperand() parameters
|
||||
mcinst_var = get_MCInst_var_name(src, fcn_def)
|
||||
return (
|
||||
b"add_cs_detail("
|
||||
f"{self.arch}_add_cs_detail_0(".encode()
|
||||
+ mcinst_var
|
||||
+ b", "
|
||||
+ op_group_enum
|
||||
@ -114,7 +116,11 @@ class AddCSDetail(Patch):
|
||||
+ b");"
|
||||
)
|
||||
elif op_group_enum == b"ARM_OP_GROUP_RegImmShift":
|
||||
return b"add_cs_detail(MI, " + op_group_enum + b", ShOpc, ShImm);"
|
||||
return (
|
||||
f"{self.arch}_add_cs_detail_1(MI, ".encode()
|
||||
+ op_group_enum
|
||||
+ b", ShOpc, ShImm);"
|
||||
)
|
||||
elif is_template and op_num_var_name in params:
|
||||
mcinst_var = get_MCInst_var_name(src, fcn_def)
|
||||
templ_p = template_param_list_to_dict(fcn_def.prev_sibling)
|
||||
@ -125,7 +131,7 @@ class AddCSDetail(Patch):
|
||||
)
|
||||
cs_args += b", " + tp["identifier"]
|
||||
return (
|
||||
b"add_cs_detail("
|
||||
f"{self.arch}_add_cs_detail_{len(templ_p)}(".encode()
|
||||
+ mcinst_var
|
||||
+ b", "
|
||||
+ op_group_enum
|
||||
|
||||
@ -5506,3 +5506,28 @@ test_cases:
|
||||
asm_text: "call #0x7fffffcc"
|
||||
-
|
||||
asm_text: "call #0x7fffffe0"
|
||||
-
|
||||
input:
|
||||
name: "issue 2458 -- UB on PPC because vargs are not casted (AArch64)"
|
||||
bytes: [ 0x20, 0x48, 0x62, 0xf8 ]
|
||||
arch: "CS_ARCH_AARCH64"
|
||||
options: [ CS_OPT_DETAIL ]
|
||||
address: 0x0
|
||||
expected:
|
||||
insns:
|
||||
-
|
||||
asm_text: "ldr x0, [x1, w2, uxtw]"
|
||||
details:
|
||||
aarch64:
|
||||
operands:
|
||||
-
|
||||
type: AARCH64_OP_REG
|
||||
reg: x0
|
||||
access: CS_AC_WRITE
|
||||
-
|
||||
type: AARCH64_OP_MEM
|
||||
mem_base: x1
|
||||
mem_index: w2
|
||||
access: CS_AC_READ
|
||||
regs_read: [ x1, w2 ]
|
||||
regs_write: [ x0 ]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user