mirror of
https://github.com/capstone-engine/capstone.git
synced 2024-11-23 13:39:46 +00:00
fix
This commit is contained in:
billow
parent
f3c11e85cd
commit
564f962146
@ -39,7 +39,7 @@ option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" ${BUILD_SHARED_LIBS}
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option(CAPSTONE_BUILD_DIET "Build diet library" OFF)
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option(CAPSTONE_BUILD_TESTS "Build tests" ${PROJECT_IS_TOP_LEVEL})
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option(CAPSTONE_BUILD_CSTOOL "Build cstool" ${PROJECT_IS_TOP_LEVEL})
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option(CAPSTONE_BUILD_CSTEST "Build cstest" ${PROJECT_IS_TOP_LEVEL})
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option(CAPSTONE_BUILD_CSTEST "Build cstest" OFF)
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option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)
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option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by default" ON)
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option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF)
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File diff suppressed because it is too large
Load Diff
@ -215,7 +215,7 @@ static const MCRegisterDesc TriCoreRegDesc[] = { // Descriptors
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// AddrRegs Register Class...
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static const MCPhysReg AddrRegs[] = {
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TriCore_A15, TriCore_A2, TriCore_A3, TriCore_A4, TriCore_A5, TriCore_A6, TriCore_A7, TriCore_A12, TriCore_A13, TriCore_A14, TriCore_A10, TriCore_A11, TriCore_A0, TriCore_A1, TriCore_A8, TriCore_A9,
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TriCore_A0, TriCore_A1, TriCore_A2, TriCore_A3, TriCore_A4, TriCore_A5, TriCore_A6, TriCore_A7, TriCore_A8, TriCore_A9, TriCore_A10, TriCore_A11, TriCore_A12, TriCore_A13, TriCore_A14, TriCore_A15,
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};
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// AddrRegs Bit set.
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@ -225,7 +225,7 @@ static const MCRegisterDesc TriCoreRegDesc[] = { // Descriptors
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// DataRegs Register Class...
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static const MCPhysReg DataRegs[] = {
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TriCore_D15, TriCore_D2, TriCore_D3, TriCore_D4, TriCore_D5, TriCore_D6, TriCore_D7, TriCore_D8, TriCore_D9, TriCore_D10, TriCore_D11, TriCore_D12, TriCore_D13, TriCore_D14, TriCore_D0, TriCore_D1,
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TriCore_D0, TriCore_D1, TriCore_D2, TriCore_D3, TriCore_D4, TriCore_D5, TriCore_D6, TriCore_D7, TriCore_D8, TriCore_D9, TriCore_D10, TriCore_D11, TriCore_D12, TriCore_D13, TriCore_D14, TriCore_D15,
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};
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// DataRegs Bit set.
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@ -245,7 +245,7 @@ static const MCRegisterDesc TriCoreRegDesc[] = { // Descriptors
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// AddrExtRegs Register Class...
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static const MCPhysReg AddrExtRegs[] = {
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TriCore_P2, TriCore_P4, TriCore_P6, TriCore_P8, TriCore_P10, TriCore_P12, TriCore_P14, TriCore_P0,
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TriCore_P0, TriCore_P2, TriCore_P4, TriCore_P6, TriCore_P8, TriCore_P10, TriCore_P12, TriCore_P14,
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};
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// AddrExtRegs Bit set.
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@ -255,7 +255,7 @@ static const MCRegisterDesc TriCoreRegDesc[] = { // Descriptors
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// ExtRegs Register Class...
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static const MCPhysReg ExtRegs[] = {
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TriCore_E2, TriCore_E4, TriCore_E6, TriCore_E8, TriCore_E10, TriCore_E12, TriCore_E14, TriCore_E0,
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TriCore_E0, TriCore_E2, TriCore_E4, TriCore_E6, TriCore_E8, TriCore_E10, TriCore_E12, TriCore_E14,
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};
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// ExtRegs Bit set.
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@ -16,17 +16,17 @@
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#ifdef CAPSTONE_HAS_TRICORE
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#include <platform.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <platform.h>
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#include "TriCoreInstPrinter.h"
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#include "../../MCInst.h"
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#include "../../utils.h"
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#include "../../SStream.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MathExtras.h"
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#include "../../SStream.h"
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#include "../../utils.h"
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#include "TriCoreInstPrinter.h"
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#include "TriCoreMapping.h"
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static const char *getRegisterName(unsigned RegNo);
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@ -35,11 +35,12 @@ static void printInstruction(MCInst *, uint64_t, SStream *);
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static void printOperand(MCInst *MI, int OpNum, SStream *O);
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void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) {
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/*
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if (((cs_struct *)ud)->detail != CS_OPT_ON)
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return;
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*/
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void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
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{
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/*
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if (((cs_struct *)ud)->detail != CS_OPT_ON)
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return;
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*/
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}
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#define GET_INSTRINFO_ENUM
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@ -50,409 +51,519 @@ void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) {
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#include "TriCoreGenRegisterInfo.inc"
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static void printOperand(MCInst *MI, int OpNum, SStream *O) {
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MCOperand *Op;
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if (OpNum >= MI->size)
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return;
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static void printOperand(MCInst *MI, int OpNum, SStream *O)
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{
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MCOperand *Op;
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if (OpNum >= MI->size)
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return;
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Op = MCInst_getOperand(MI, OpNum);
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Op = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isReg(Op)) {
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unsigned reg = MCOperand_getReg(Op);
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SStream_concat(O, "%%%s", getRegisterName(reg));
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if (MCOperand_isReg(Op)) {
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unsigned reg = MCOperand_getReg(Op);
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SStream_concat(O, "%%%s", getRegisterName(reg));
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
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MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
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reg);
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MI->flat_insn->detail->tricore.op_count++;
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}
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} else if (MCOperand_isImm(Op)) {
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int64_t Imm = MCOperand_getImm(Op);
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.type = TRICORE_OP_REG;
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.reg = (uint8_t)TriCore_map_register(reg);
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MI->flat_insn->detail->tricore.op_count++;
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}
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} else if (MCOperand_isImm(Op)) {
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int64_t Imm = MCOperand_getImm(Op);
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if (Imm >= 0) {
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if (Imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%"PRIx64, Imm);
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else
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SStream_concat(O, "%"PRIu64, Imm);
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} else {
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if (Imm < -HEX_THRESHOLD)
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SStream_concat(O, "-0x%"PRIx64, -Imm);
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else
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SStream_concat(O, "-%"PRIu64, -Imm);
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}
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if (Imm >= 0) {
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if (Imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%" PRIx64, Imm);
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else
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SStream_concat(O, "%" PRIu64, Imm);
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} else {
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if (Imm < -HEX_THRESHOLD)
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SStream_concat(O, "-0x%" PRIx64, -Imm);
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else
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SStream_concat(O, "-%" PRIu64, -Imm);
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}
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_IMM;
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MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].imm = Imm;
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MI->flat_insn->detail->tricore.op_count++;
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}
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}
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.type = TRICORE_OP_IMM;
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.imm = Imm;
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MI->flat_insn->detail->tricore.op_count++;
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}
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}
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}
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static void printPairAddrRegsOperand(MCInst *MI, unsigned OpNum, SStream *O,
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MCRegisterInfo *MRI) {
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unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
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SStream_concat0(O, "[");
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SStream_concat(O, "%%%s", getRegisterName(MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_even)));
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
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MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
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MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_even));
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MI->flat_insn->detail->tricore.op_count++;
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}
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SStream_concat0(O, "/");
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SStream_concat(O, "%%%s", getRegisterName(MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_odd)));
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
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MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
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MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_odd));
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MI->flat_insn->detail->tricore.op_count++;
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}
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SStream_concat0(O, "]");
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MCRegisterInfo *MRI)
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{
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unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
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SStream_concat0(O, "[");
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SStream_concat(
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O, "%%%s",
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getRegisterName(MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_even)));
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.type = TRICORE_OP_REG;
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.reg = (uint8_t)TriCore_map_register(
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MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_even));
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MI->flat_insn->detail->tricore.op_count++;
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}
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SStream_concat0(O, "/");
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SStream_concat(
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O, "%%%s",
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getRegisterName(MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_odd)));
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.type = TRICORE_OP_REG;
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.reg = (uint8_t)TriCore_map_register(
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MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_odd));
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MI->flat_insn->detail->tricore.op_count++;
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}
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SStream_concat0(O, "]");
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}
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static void printSExtImm(MCInst *MI, int OpNum, SStream *O) {
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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int64_t imm = MCOperand_getImm(MO);
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if (imm >= 0) {
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if (imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%x", (unsigned short int) imm);
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else
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SStream_concat(O, "%u", (unsigned short int) imm);
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} else {
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if (imm < -HEX_THRESHOLD)
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SStream_concat(O, "-0x%x", (short int) -imm);
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else
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SStream_concat(O, "-%u", (short int) -imm);
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}
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_IMM;
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MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].imm = (unsigned short int) imm;
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MI->flat_insn->detail->tricore.op_count++;
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}
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} else
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printOperand(MI, OpNum, O);
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static void printSExtImm(MCInst *MI, int OpNum, SStream *O)
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{
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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int64_t imm = MCOperand_getImm(MO);
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if (imm >= 0) {
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if (imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%x", (unsigned short int)imm);
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else
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SStream_concat(O, "%u", (unsigned short int)imm);
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} else {
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if (imm < -HEX_THRESHOLD)
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SStream_concat(O, "-0x%x", (short int)-imm);
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else
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SStream_concat(O, "-%u", (short int)-imm);
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}
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.type = TRICORE_OP_IMM;
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.imm = (unsigned short int)imm;
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MI->flat_insn->detail->tricore.op_count++;
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}
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} else
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printOperand(MI, OpNum, O);
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}
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static void printSExtImm_16(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
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static void printSExtImm_10(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
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static void printSExtImm_9(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
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static void printSExtImm_4(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
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static void printZExtImm(MCInst *MI, int OpNum, SStream *O) {
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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unsigned imm = (unsigned) MCOperand_getImm(MO);
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if (imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%x", imm);
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else
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SStream_concat(O, "%u", imm);
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_IMM;
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MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].imm = imm;
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MI->flat_insn->detail->tricore.op_count++;
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}
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} else
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printOperand(MI, OpNum, O);
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static void printSExtImm_16(MCInst *MI, int OpNum, SStream *O)
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{ /*TODO: TriCore*/
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}
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static void printZExtImm_8(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
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static void printSExtImm_10(MCInst *MI, int OpNum, SStream *O)
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{ /*TODO: TriCore*/
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}
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static void printZExtImm_4(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
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static void printSExtImm_9(MCInst *MI, int OpNum, SStream *O)
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{ /*TODO: TriCore*/
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}
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static void printZExtImm_2(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
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static void printSExtImm_4(MCInst *MI, int OpNum, SStream *O)
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{ /*TODO: TriCore*/
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}
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static void printZExtImm(MCInst *MI, int OpNum, SStream *O)
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{
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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unsigned imm = (unsigned)MCOperand_getImm(MO);
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if (imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%x", imm);
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else
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SStream_concat(O, "%u", imm);
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.type = TRICORE_OP_IMM;
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.imm = imm;
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MI->flat_insn->detail->tricore.op_count++;
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}
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} else
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printOperand(MI, OpNum, O);
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}
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static void printPCRelImmOperand(MCInst *MI, int OpNum, SStream *O) {
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MCOperand *Op = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(Op)) {
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unsigned imm = (unsigned) MCOperand_getImm(Op);
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if (imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%x", imm);
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else
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SStream_concat(O, "%u", imm);
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} else
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printOperand(MI, OpNum, O);
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static void printZExtImm_8(MCInst *MI, int OpNum, SStream *O)
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{ /*TODO: TriCore*/
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}
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static void printZExtImm_4(MCInst *MI, int OpNum, SStream *O)
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{ /*TODO: TriCore*/
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}
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static void printZExtImm_2(MCInst *MI, int OpNum, SStream *O)
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{ /*TODO: TriCore*/
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}
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static void printPCRelImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNum);
|
||||
if (MCOperand_isImm(Op)) {
|
||||
unsigned imm = (unsigned)MCOperand_getImm(Op);
|
||||
if (imm > HEX_THRESHOLD)
|
||||
SStream_concat(O, "0x%x", imm);
|
||||
else
|
||||
SStream_concat(O, "%u", imm);
|
||||
} else
|
||||
printOperand(MI, OpNum, O);
|
||||
}
|
||||
|
||||
// Print a 'bo' operand which is an addressing mode
|
||||
// Base+Offset
|
||||
static void printAddrBO(MCInst *MI, int OpNum, SStream *O) {
|
||||
static void printAddrBO(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
|
||||
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
uint64_t Disp = (uint64_t) MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
|
||||
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
|
||||
|
||||
SStream_concat(O, "[");
|
||||
SStream_concat(O, "%%%s", getRegisterName(Base));
|
||||
SStream_concat(O, "] ");
|
||||
SStream_concat(O, "[");
|
||||
SStream_concat(O, "%%%s", getRegisterName(Base));
|
||||
SStream_concat(O, "] ");
|
||||
|
||||
if (Disp > HEX_THRESHOLD)
|
||||
SStream_concat(O, "0x%"PRIx64, Disp);
|
||||
else
|
||||
SStream_concat(O, "%"PRIu64, Disp);
|
||||
if (Disp > HEX_THRESHOLD)
|
||||
SStream_concat(O, "0x%" PRIx64, Disp);
|
||||
else
|
||||
SStream_concat(O, "%" PRIu64, Disp);
|
||||
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_MEM;
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.base = (uint8_t) TriCore_map_register(
|
||||
Base);
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.disp = Disp;
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.type = TRICORE_OP_MEM;
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.mem.base = (uint8_t)TriCore_map_register(Base);
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.mem.disp = Disp;
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
}
|
||||
|
||||
// Print a 'preincbo' operand which is an addressing mode
|
||||
// Pre-increment Base+Offset
|
||||
static void printAddrPreIncBO(MCInst *MI, int OpNum, SStream *O) {
|
||||
static void printAddrPreIncBO(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
|
||||
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
uint64_t Disp = (uint64_t) MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
|
||||
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
|
||||
|
||||
SStream_concat(O, "[+");
|
||||
SStream_concat(O, "%%%s", getRegisterName(Base));
|
||||
SStream_concat(O, "] ");
|
||||
SStream_concat(O, "[+");
|
||||
SStream_concat(O, "%%%s", getRegisterName(Base));
|
||||
SStream_concat(O, "] ");
|
||||
|
||||
if (Disp > HEX_THRESHOLD)
|
||||
SStream_concat(O, "0x%"PRIx64, Disp);
|
||||
else
|
||||
SStream_concat(O, "%"PRIu64, Disp);
|
||||
if (Disp > HEX_THRESHOLD)
|
||||
SStream_concat(O, "0x%" PRIx64, Disp);
|
||||
else
|
||||
SStream_concat(O, "%" PRIu64, Disp);
|
||||
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_MEM;
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.base = (uint8_t) TriCore_map_register(
|
||||
Base);
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.disp = Disp;
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.type = TRICORE_OP_MEM;
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.mem.base = (uint8_t)TriCore_map_register(Base);
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.mem.disp = Disp;
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
}
|
||||
|
||||
// Print a 'postincbo' operand which is an addressing mode
|
||||
// Post-increment Base+Offset
|
||||
static void printAddrPostIncBO(MCInst *MI, int OpNum, SStream *O) {
|
||||
static void printAddrPostIncBO(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
|
||||
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
uint64_t Disp = (uint64_t) MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
|
||||
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
|
||||
|
||||
SStream_concat(O, "[");
|
||||
SStream_concat(O, "%%%s", getRegisterName(Base));
|
||||
SStream_concat(O, "+] ");
|
||||
SStream_concat(O, "[");
|
||||
SStream_concat(O, "%%%s", getRegisterName(Base));
|
||||
SStream_concat(O, "+] ");
|
||||
|
||||
if (Disp > HEX_THRESHOLD)
|
||||
SStream_concat(O, "0x%"PRIx64, Disp);
|
||||
else
|
||||
SStream_concat(O, "%"PRIu64, Disp);
|
||||
if (Disp > HEX_THRESHOLD)
|
||||
SStream_concat(O, "0x%" PRIx64, Disp);
|
||||
else
|
||||
SStream_concat(O, "%" PRIu64, Disp);
|
||||
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_MEM;
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.base = (uint8_t) TriCore_map_register(
|
||||
Base);
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.disp = Disp;
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.type = TRICORE_OP_MEM;
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.mem.base = (uint8_t)TriCore_map_register(Base);
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.mem.disp = Disp;
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
}
|
||||
|
||||
// Print a 'circbo' operand which is an addressing mode
|
||||
// Circular Base+Offset
|
||||
static void printAddrCircBO(MCInst *MI, unsigned OpNum, SStream *O,
|
||||
MCRegisterInfo *MRI) {
|
||||
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
uint64_t Disp = (uint64_t) MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
|
||||
MCRegisterInfo *MRI)
|
||||
{
|
||||
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
|
||||
|
||||
SStream_concat0(O, "[");
|
||||
SStream_concat(O, "%%%s", getRegisterName(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even)));
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
|
||||
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even));
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
SStream_concat0(O, "/");
|
||||
SStream_concat(O, "%%%s", getRegisterName(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd)));
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
|
||||
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd));
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
SStream_concat0(O, "+c] ");
|
||||
SStream_concat0(O, "[");
|
||||
SStream_concat(O, "%%%s",
|
||||
getRegisterName(
|
||||
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even)));
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.type = TRICORE_OP_REG;
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.reg = (uint8_t)TriCore_map_register(
|
||||
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even));
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
SStream_concat0(O, "/");
|
||||
SStream_concat(
|
||||
O, "%%%s",
|
||||
getRegisterName(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd)));
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.type = TRICORE_OP_REG;
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.reg = (uint8_t)TriCore_map_register(
|
||||
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd));
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
SStream_concat0(O, "+c] ");
|
||||
|
||||
if (Disp > HEX_THRESHOLD)
|
||||
SStream_concat(O, "0x%"PRIx64, Disp);
|
||||
else
|
||||
SStream_concat(O, "%"PRIu64, Disp);
|
||||
if (Disp > HEX_THRESHOLD)
|
||||
SStream_concat(O, "0x%" PRIx64, Disp);
|
||||
else
|
||||
SStream_concat(O, "%" PRIu64, Disp);
|
||||
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_MEM;
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.base = (uint8_t) TriCore_map_register(
|
||||
Base);
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.disp = Disp;
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.type = TRICORE_OP_MEM;
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.mem.base = (uint8_t)TriCore_map_register(Base);
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.mem.disp = Disp;
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
}
|
||||
|
||||
// Print a 'bitrevbo' operand which is an addressing mode
|
||||
// Bit-Reverse Base+Offset
|
||||
static void printAddrBitRevBO(MCInst *MI, unsigned OpNum, SStream *O,
|
||||
MCRegisterInfo *MRI) {
|
||||
MCRegisterInfo *MRI)
|
||||
{
|
||||
|
||||
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
|
||||
SStream_concat0(O, "[");
|
||||
SStream_concat(O, "%%%s", getRegisterName(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even)));
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
|
||||
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even));
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
SStream_concat0(O, "/");
|
||||
SStream_concat(O, "%%%s", getRegisterName(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd)));
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
|
||||
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
|
||||
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd));
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
SStream_concat0(O, "+r]");
|
||||
SStream_concat0(O, "[");
|
||||
SStream_concat(O, "%%%s",
|
||||
getRegisterName(
|
||||
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even)));
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.type = TRICORE_OP_REG;
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.reg = (uint8_t)TriCore_map_register(
|
||||
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even));
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
SStream_concat0(O, "/");
|
||||
SStream_concat(
|
||||
O, "%%%s",
|
||||
getRegisterName(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd)));
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.type = TRICORE_OP_REG;
|
||||
MI->flat_insn->detail->tricore
|
||||
.operands[MI->flat_insn->detail->tricore.op_count]
|
||||
.reg = (uint8_t)TriCore_map_register(
|
||||
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd));
|
||||
MI->flat_insn->detail->tricore.op_count++;
|
||||
}
|
||||
SStream_concat0(O, "+r]");
|
||||
}
|
||||
|
||||
/// Returned by getMnemonic() of the AsmPrinters.
|
||||
typedef struct {
|
||||
const char *first; // Menmonic
|
||||
uint64_t second; // Bits
|
||||
const char *first; // Menmonic
|
||||
uint64_t second; // Bits
|
||||
} MnemonicBitsInfo;
|
||||
|
||||
void set_mem_access(MCInst *MI, unsigned int access) {
|
||||
// TODO: TriCore
|
||||
void set_mem_access(MCInst *MI, unsigned int access)
|
||||
{
|
||||
// TODO: TriCore
|
||||
}
|
||||
|
||||
#define PRINT_ALIAS_INSTR
|
||||
|
||||
#include "TriCoreGenAsmWriter.inc"
|
||||
|
||||
void TriCore_printInst(MCInst *MI, SStream *O, void *Info) {
|
||||
MCRegisterInfo *MRI = (MCRegisterInfo *) Info;
|
||||
void TriCore_printInst(MCInst *MI, SStream *O, void *Info)
|
||||
{
|
||||
MCRegisterInfo *MRI = (MCRegisterInfo *)Info;
|
||||
|
||||
unsigned Opcode = MCInst_getOpcode(MI), i;
|
||||
unsigned Opcode = MCInst_getOpcode(MI), i;
|
||||
|
||||
// switch(Opcode) {
|
||||
// // Combine 2 AddrRegs from disassember into a PairAddrRegs to match
|
||||
// // with instr def. load/store require even/odd AddrReg pair. To enforce
|
||||
// // this constraint, a single PairAddrRegs reg operand is used in the .td
|
||||
// // file to replace the two AddrRegs. However, when decoding them, the two
|
||||
// // AddrRegs cannot be automatically expressed as a PairAddrRegs, so we
|
||||
// // have to manually merge them.
|
||||
// // FIXME: We would really like to be able to tablegen'erate this.
|
||||
// case TriCore_LD_DAabs:
|
||||
// case TriCore_LD_DAbo:
|
||||
// case TriCore_LD_DApreincbo:
|
||||
// case TriCore_LD_DApostincbo:
|
||||
// case TriCore_ST_Bcircbo:
|
||||
// case TriCore_ST_Hcircbo:
|
||||
// case TriCore_ST_Wcircbo:
|
||||
// case TriCore_ST_Dcircbo:
|
||||
// case TriCore_ST_Qcircbo:
|
||||
// case TriCore_ST_Acircbo:
|
||||
// case TriCore_ST_Bbitrevbo:
|
||||
// case TriCore_ST_Hbitrevbo:
|
||||
// case TriCore_ST_Wbitrevbo:
|
||||
// case TriCore_ST_Dbitrevbo:
|
||||
// case TriCore_ST_Qbitrevbo:
|
||||
// case TriCore_ST_Abitrevbo: {
|
||||
// const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, TriCore_AddrRegsRegClassID);
|
||||
//
|
||||
// unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
|
||||
// if (MCRegisterClass_contains(MRC, Reg)) {
|
||||
// MCInst NewMI;
|
||||
//
|
||||
// MCInst_Init(&NewMI);
|
||||
// MCInst_setOpcode(&NewMI, Opcode);
|
||||
//
|
||||
// MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, TriCore_subreg_even,
|
||||
// MCRegisterInfo_getRegClass(MRI, TriCore_PairAddrRegsRegClassID)));
|
||||
//
|
||||
// // Copy the rest operands into NewMI.
|
||||
// for(i = 2; i < MCInst_getNumOperands(MI); ++i)
|
||||
// MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
|
||||
//
|
||||
// printInstruction(&NewMI, O, MRI);
|
||||
// return;
|
||||
// }
|
||||
// }
|
||||
// case TriCore_ST_DAabs:
|
||||
// case TriCore_ST_DAbo:
|
||||
// case TriCore_ST_DApreincbo:
|
||||
// case TriCore_ST_DApostincbo:
|
||||
// case TriCore_LD_Bcircbo:
|
||||
// case TriCore_LD_BUcircbo:
|
||||
// case TriCore_LD_Hcircbo:
|
||||
// case TriCore_LD_HUcircbo:
|
||||
// case TriCore_LD_Wcircbo:
|
||||
// case TriCore_LD_Dcircbo:
|
||||
// case TriCore_LD_Acircbo:
|
||||
// case TriCore_LD_Bbitrevbo:
|
||||
// case TriCore_LD_BUbitrevbo:
|
||||
// case TriCore_LD_Hbitrevbo:
|
||||
// case TriCore_LD_HUbitrevbo:
|
||||
// case TriCore_LD_Wbitrevbo:
|
||||
// case TriCore_LD_Dbitrevbo:
|
||||
// case TriCore_LD_Abitrevbo: {
|
||||
// const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, TriCore_AddrRegsRegClassID);
|
||||
//
|
||||
// unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
|
||||
// if (MCRegisterClass_contains(MRC, Reg)) {
|
||||
// MCInst NewMI;
|
||||
//
|
||||
// MCInst_Init(&NewMI);
|
||||
// MCInst_setOpcode(&NewMI, Opcode);
|
||||
//
|
||||
// MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
|
||||
//
|
||||
// MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, TriCore_subreg_even,
|
||||
// MCRegisterInfo_getRegClass(MRI, TriCore_PairAddrRegsRegClassID)));
|
||||
//
|
||||
// // Copy the rest operands into NewMI.
|
||||
// for(i = 3; i < MCInst_getNumOperands(MI); ++i)
|
||||
// MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
|
||||
//
|
||||
// printInstruction(&NewMI, O, MRI);
|
||||
// return;
|
||||
// }
|
||||
// }
|
||||
// case TriCore_LD_DAcircbo:
|
||||
// case TriCore_ST_DAcircbo:
|
||||
// case TriCore_LD_DAbitrevbo:
|
||||
// case TriCore_ST_DAbitrevbo: {
|
||||
// const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, TriCore_AddrRegsRegClassID);
|
||||
//
|
||||
// unsigned Reg1 = MCOperand_getReg(MCInst_getOperand(MI, 0));
|
||||
// unsigned Reg2 = MCOperand_getReg(MCInst_getOperand(MI, 2));
|
||||
// if (MCRegisterClass_contains(MRC, Reg2)) {
|
||||
// MCInst NewMI;
|
||||
//
|
||||
// MCInst_Init(&NewMI);
|
||||
// MCInst_setOpcode(&NewMI, Opcode);
|
||||
//
|
||||
// MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg1, TriCore_subreg_even,
|
||||
// MCRegisterInfo_getRegClass(MRI, TriCore_PairAddrRegsRegClassID)));
|
||||
//
|
||||
// MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg2, TriCore_subreg_even,
|
||||
// MCRegisterInfo_getRegClass(MRI, TriCore_PairAddrRegsRegClassID)));
|
||||
//
|
||||
// // Copy the rest operands into NewMI.
|
||||
// for(i = 4; i < MCInst_getNumOperands(MI); ++i)
|
||||
// MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
|
||||
//
|
||||
// printInstruction(&NewMI, O, MRI);
|
||||
// return;
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
printInstruction(MI, Info, O);
|
||||
// switch(Opcode) {
|
||||
// // Combine 2 AddrRegs from disassember into a PairAddrRegs to
|
||||
//match
|
||||
// // with instr def. load/store require even/odd AddrReg pair. To
|
||||
//enforce
|
||||
// // this constraint, a single PairAddrRegs reg operand is used in the
|
||||
//.td
|
||||
// // file to replace the two AddrRegs. However, when decoding them,
|
||||
//the two
|
||||
// // AddrRegs cannot be automatically expressed as a PairAddrRegs, so
|
||||
//we
|
||||
// // have to manually merge them.
|
||||
// // FIXME: We would really like to be able to tablegen'erate
|
||||
//this. case TriCore_LD_DAabs: case TriCore_LD_DAbo: case
|
||||
//TriCore_LD_DApreincbo: case TriCore_LD_DApostincbo: case TriCore_ST_Bcircbo:
|
||||
// case TriCore_ST_Hcircbo:
|
||||
// case TriCore_ST_Wcircbo:
|
||||
// case TriCore_ST_Dcircbo:
|
||||
// case TriCore_ST_Qcircbo:
|
||||
// case TriCore_ST_Acircbo:
|
||||
// case TriCore_ST_Bbitrevbo:
|
||||
// case TriCore_ST_Hbitrevbo:
|
||||
// case TriCore_ST_Wbitrevbo:
|
||||
// case TriCore_ST_Dbitrevbo:
|
||||
// case TriCore_ST_Qbitrevbo:
|
||||
// case TriCore_ST_Abitrevbo: {
|
||||
// const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI,
|
||||
//TriCore_AddrRegsRegClassID);
|
||||
//
|
||||
// unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI,
|
||||
//0)); if (MCRegisterClass_contains(MRC, Reg)) { MCInst NewMI;
|
||||
//
|
||||
// MCInst_Init(&NewMI);
|
||||
// MCInst_setOpcode(&NewMI, Opcode);
|
||||
//
|
||||
// MCOperand_CreateReg0(&NewMI,
|
||||
//MCRegisterInfo_getMatchingSuperReg(MRI, Reg, TriCore_subreg_even,
|
||||
// MCRegisterInfo_getRegClass(MRI,
|
||||
//TriCore_PairAddrRegsRegClassID)));
|
||||
//
|
||||
// // Copy the rest operands into NewMI.
|
||||
// for(i = 2; i < MCInst_getNumOperands(MI); ++i)
|
||||
// MCInst_addOperand2(&NewMI, MCInst_getOperand(MI,
|
||||
//i));
|
||||
//
|
||||
// printInstruction(&NewMI, O, MRI);
|
||||
// return;
|
||||
// }
|
||||
// }
|
||||
// case TriCore_ST_DAabs:
|
||||
// case TriCore_ST_DAbo:
|
||||
// case TriCore_ST_DApreincbo:
|
||||
// case TriCore_ST_DApostincbo:
|
||||
// case TriCore_LD_Bcircbo:
|
||||
// case TriCore_LD_BUcircbo:
|
||||
// case TriCore_LD_Hcircbo:
|
||||
// case TriCore_LD_HUcircbo:
|
||||
// case TriCore_LD_Wcircbo:
|
||||
// case TriCore_LD_Dcircbo:
|
||||
// case TriCore_LD_Acircbo:
|
||||
// case TriCore_LD_Bbitrevbo:
|
||||
// case TriCore_LD_BUbitrevbo:
|
||||
// case TriCore_LD_Hbitrevbo:
|
||||
// case TriCore_LD_HUbitrevbo:
|
||||
// case TriCore_LD_Wbitrevbo:
|
||||
// case TriCore_LD_Dbitrevbo:
|
||||
// case TriCore_LD_Abitrevbo: {
|
||||
// const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI,
|
||||
//TriCore_AddrRegsRegClassID);
|
||||
//
|
||||
// unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI,
|
||||
//1)); if (MCRegisterClass_contains(MRC, Reg)) { MCInst NewMI;
|
||||
//
|
||||
// MCInst_Init(&NewMI);
|
||||
// MCInst_setOpcode(&NewMI, Opcode);
|
||||
//
|
||||
// MCInst_addOperand2(&NewMI, MCInst_getOperand(MI,
|
||||
//0));
|
||||
//
|
||||
// MCOperand_CreateReg0(&NewMI,
|
||||
//MCRegisterInfo_getMatchingSuperReg(MRI, Reg, TriCore_subreg_even,
|
||||
// MCRegisterInfo_getRegClass(MRI,
|
||||
//TriCore_PairAddrRegsRegClassID)));
|
||||
//
|
||||
// // Copy the rest operands into NewMI.
|
||||
// for(i = 3; i < MCInst_getNumOperands(MI); ++i)
|
||||
// MCInst_addOperand2(&NewMI, MCInst_getOperand(MI,
|
||||
//i));
|
||||
//
|
||||
// printInstruction(&NewMI, O, MRI);
|
||||
// return;
|
||||
// }
|
||||
// }
|
||||
// case TriCore_LD_DAcircbo:
|
||||
// case TriCore_ST_DAcircbo:
|
||||
// case TriCore_LD_DAbitrevbo:
|
||||
// case TriCore_ST_DAbitrevbo: {
|
||||
// const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI,
|
||||
//TriCore_AddrRegsRegClassID);
|
||||
//
|
||||
// unsigned Reg1 = MCOperand_getReg(MCInst_getOperand(MI,
|
||||
//0)); unsigned Reg2 = MCOperand_getReg(MCInst_getOperand(MI, 2)); if
|
||||
//(MCRegisterClass_contains(MRC, Reg2)) { MCInst NewMI;
|
||||
//
|
||||
// MCInst_Init(&NewMI);
|
||||
// MCInst_setOpcode(&NewMI, Opcode);
|
||||
//
|
||||
// MCOperand_CreateReg0(&NewMI,
|
||||
//MCRegisterInfo_getMatchingSuperReg(MRI, Reg1, TriCore_subreg_even,
|
||||
// MCRegisterInfo_getRegClass(MRI,
|
||||
//TriCore_PairAddrRegsRegClassID)));
|
||||
//
|
||||
// MCOperand_CreateReg0(&NewMI,
|
||||
//MCRegisterInfo_getMatchingSuperReg(MRI, Reg2, TriCore_subreg_even,
|
||||
// MCRegisterInfo_getRegClass(MRI,
|
||||
//TriCore_PairAddrRegsRegClassID)));
|
||||
//
|
||||
// // Copy the rest operands into NewMI.
|
||||
// for(i = 4; i < MCInst_getNumOperands(MI); ++i)
|
||||
// MCInst_addOperand2(&NewMI, MCInst_getOperand(MI,
|
||||
//i));
|
||||
//
|
||||
// printInstruction(&NewMI, O, MRI);
|
||||
// return;
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
printInstruction(MI, 0, O);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@ -265,27 +265,25 @@ multiclass mISC_D15<bits<8> op1, string asmstr> {
|
||||
def _src : ISC_D15<op1, asmstr>;
|
||||
}
|
||||
|
||||
let Constraints = "$s1 = $d" in {
|
||||
class ISRC<bits<8> op1, string asmstr>
|
||||
: SRC<op1, (outs DataRegs:$d), (ins DataRegs:$s1, s4imm:$const4),
|
||||
: SRC<op1, (outs DataRegs:$d), (ins s4imm:$const4),
|
||||
asmstr # " $d, $const4",
|
||||
[]>;
|
||||
|
||||
class ISRC_Aa<bits<8> op1, string asmstr>
|
||||
: SRC<op1, (outs AddrRegs:$d), (ins AddrRegs:$s1, s4imm:$const4),
|
||||
: SRC<op1, (outs AddrRegs:$d), (ins s4imm:$const4),
|
||||
asmstr # " $d, $const4",
|
||||
[]>;
|
||||
|
||||
class ISRC_a15<bits<8> op1, string asmstr>
|
||||
: SRC<op1, (outs DataRegs:$d), (ins DataRegs:$s1, s4imm:$const4),
|
||||
: SRC<op1, (outs DataRegs:$d), (ins s4imm:$const4),
|
||||
asmstr # " $d, %d15, $const4",
|
||||
[]>;
|
||||
|
||||
class ISRC_15a<bits<8> op1, string asmstr>
|
||||
: SRC<op1, (outs DataRegs:$d), (ins DataRegs:$s1, s4imm:$const4),
|
||||
: SRC<op1, (outs DataRegs:$d), (ins s4imm:$const4),
|
||||
asmstr # " %d15, $d, $const4",
|
||||
[]>;
|
||||
}
|
||||
|
||||
multiclass mISRC_s<bits<8> op1, string asmstr> {
|
||||
def _src : ISRC<op1, asmstr>;
|
||||
@ -383,27 +381,27 @@ class IRLC<bits<8> op1, string asmstr>
|
||||
asmstr # " $d, $s1, $const16",
|
||||
[]>;
|
||||
|
||||
let Constraints = "$s1 = $d" in {
|
||||
|
||||
class ISRR<bits<8> op1, string asmstr>
|
||||
: SRR<op1, (outs DataRegs:$d), (ins DataRegs:$s1, DataRegs:$s2),
|
||||
: SRR<op1, (outs DataRegs:$d), (ins DataRegs:$s2),
|
||||
asmstr # " $d, $s2",
|
||||
[]>;
|
||||
|
||||
class ISRR_AaAb<bits<8> op1, string asmstr>
|
||||
: SRR<op1, (outs AddrRegs:$d), (ins AddrRegs:$s1, DataRegs:$s2),
|
||||
: SRR<op1, (outs AddrRegs:$d), (ins AddrRegs:$s2),
|
||||
asmstr # " $d, $s2",
|
||||
[]>;
|
||||
|
||||
class ISRR_a15<bits<8> op1, string asmstr>
|
||||
: SRR<op1, (outs DataRegs:$d), (ins DataRegs:$s1, DataRegs:$s2),
|
||||
: SRR<op1, (outs DataRegs:$d), (ins DataRegs:$s2),
|
||||
asmstr # " $d, %d15, $s2",
|
||||
[]>;
|
||||
|
||||
class ISRR_15a<bits<8> op1, string asmstr>
|
||||
: SRR<op1, (outs DataRegs:$d), (ins DataRegs:$s1, DataRegs:$s2),
|
||||
: SRR<op1, (outs DataRegs:$d), (ins DataRegs:$s2),
|
||||
asmstr # " %d15, $d, $s2",
|
||||
[]>;
|
||||
}
|
||||
|
||||
|
||||
multiclass mISRR_s<bits<8> op1, string asmstr>{
|
||||
def _srr : ISRR<op1, asmstr>;
|
||||
@ -574,22 +572,22 @@ class IBO_bso<bits<8> op1, bits<6> op2, string asmstr>
|
||||
asmstr # " [$s2]$off10", []>;
|
||||
// P[b] (BO) (Bit Reverse Addressing Mode)
|
||||
class IBO_r<bits<8> op1, bits<6> op2, string asmstr>
|
||||
: BO<op1, op2, (outs AddrExtRegs:$b), (ins AddrRegs:$s2),
|
||||
asmstr # " [${b}+r]", []>;
|
||||
: BO<op1, op2, (outs), (ins AddrRegs:$s2),
|
||||
asmstr # " [${s2}+r]", []>;
|
||||
// P[b], off10 (BO) (Circular Addressing Mode)
|
||||
class IBO_c<bits<8> op1, bits<6> op2, string asmstr>
|
||||
: BO<op1, op2, (outs AddrExtRegs:$b), (ins s10imm:$off10),
|
||||
asmstr # " [${b}+c]", []>;
|
||||
: BO<op1, op2, (outs), (ins AddrExtRegs:$s2, s10imm:$off10),
|
||||
asmstr # " [${s2}+c]$off10", []>;
|
||||
// A[b], off10 (BO) (Post-increment Addressing Mode)
|
||||
let Constraints = "$s2 = $d" in {
|
||||
|
||||
class IBO_pos<bits<8> op1, bits<6> op2, string asmstr>
|
||||
: BO<op1, op2, (outs AddrRegs:$d), (ins AddrRegs:$s2, s10imm:$off10),
|
||||
: BO<op1, op2, (outs), (ins AddrRegs:$s2, s10imm:$off10),
|
||||
asmstr # " [+$s2]$off10", []>;
|
||||
// A[b], off10 (BO) (Pre-increment Addressing Mode)
|
||||
class IBO_pre<bits<8> op1, bits<6> op2, string asmstr>
|
||||
: BO<op1, op2, (outs AddrRegs:$d), (ins AddrRegs:$s2, s10imm:$off10),
|
||||
: BO<op1, op2, (outs), (ins AddrRegs:$s2, s10imm:$off10),
|
||||
asmstr # " [${s2}+]$off10", []>;
|
||||
}
|
||||
|
||||
|
||||
multiclass mIBO_a<bits<8> op11, bits<6> op12,
|
||||
bits<8> op21, bits<6> op22,
|
||||
@ -752,15 +750,14 @@ class IBO_cEa<bits<8> op1, bits<6> op2, string asmstr>
|
||||
: BO<op1, op2, (outs AddrExtRegs:$b), (ins s10imm:$off10, AddrExtRegs:$s1),
|
||||
asmstr # " $s1, [${b}+c]", []>;
|
||||
// A[b], off10, E[a] (BO)(Post-increment Addressing Mode)
|
||||
let Constraints = "$s2 = $d" in {
|
||||
class IBO_posEa<bits<8> op1, bits<6> op2, string asmstr>
|
||||
: BO<op1, op2, (outs AddrRegs:$d), (ins AddrRegs:$s2, s10imm:$off10, AddrExtRegs:$s1),
|
||||
: BO<op1, op2, (outs), (ins AddrExtRegs:$s1, AddrRegs:$s2, s10imm:$off10),
|
||||
asmstr # " $s1, [+$s2]$off10", []>;
|
||||
// A[b], off10, E[a] (BO)(Pre-increment Addressing Mode)
|
||||
class IBO_preEa<bits<8> op1, bits<6> op2, string asmstr>
|
||||
: BO<op1, op2, (outs AddrRegs:$d), (ins AddrRegs:$s2, s10imm:$off10, AddrExtRegs:$s1),
|
||||
: BO<op1, op2, (outs), (ins AddrExtRegs:$s1, AddrRegs:$s2, s10imm:$off10),
|
||||
asmstr # " $s1, [${s2}+]$off10", []>;
|
||||
}
|
||||
|
||||
|
||||
multiclass mIBO_Ea<bits<8> bso1, bits<6> bso2, ///_bso
|
||||
bits<8> r1, bits<6> r2, ///_r
|
||||
@ -790,9 +787,9 @@ def CSUBN_rrr : IRRR_DcDdDaDb<0x2B, 0x03, "csub">;
|
||||
class ISR_0<bits<8> op1, bits<4> op2, string asmstr>
|
||||
: SR<op1, op2, (outs), (ins),
|
||||
asmstr, []>;
|
||||
let Constraints = "$s1 = $d" in
|
||||
|
||||
class ISR_1<bits<8> op1, bits<4> op2, string asmstr>
|
||||
: SR<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1),
|
||||
: SR<op1, op2, (outs), (ins DataRegs:$s1),
|
||||
asmstr # " $s1", []>;
|
||||
|
||||
class ISYS_0<bits<8> op1, bits<6> op2, string asmstr>
|
||||
@ -1143,17 +1140,16 @@ class IBO_RPr<bits<8> op1, bits<6> op2, string asmstr, RegisterClass dc>
|
||||
// A|D[a], P[b], off10 (BO) (Circular Addressing Mode)
|
||||
class IBO_RPc<bits<8> op1, bits<6> op2, string asmstr, RegisterClass dc>
|
||||
: BO<op1, op2, (outs dc:$d), (ins AddrExtRegs:$s2, s10imm:$off10),
|
||||
asmstr # " $d, [${s2}+c]", []>;
|
||||
// A|D[a], A[b], off10 (BO) (Post-increment Addressing Mode)
|
||||
let Constraints = "$s2 = $d" in {
|
||||
asmstr # " $d, [${s2}+c]$off10", []>;
|
||||
// A|D[a], A[b], off10 (BO)(Post-increment Addressing Mode)
|
||||
class IBO_RApos<bits<8> op1, bits<6> op2, string asmstr, RegisterClass dc>
|
||||
: BO<op1, op2, (outs dc:$d), (ins AddrRegs:$s2, s10imm:$off10),
|
||||
asmstr # " $d, [+$s2]$off10", []>;
|
||||
: BO<op1, op2, (outs), (ins dc:$s1, AddrRegs:$s2, s10imm:$off10),
|
||||
asmstr # " $s1, [+$s2]$off10", []>;
|
||||
// A|D[a], A[b], off10 (BO) (Pre-increment Addressing Mode)
|
||||
class IBO_RApre<bits<8> op1, bits<6> op2, string asmstr, RegisterClass dc>
|
||||
: BO<op1, op2, (outs dc:$d), (ins AddrRegs:$s2, s10imm:$off10),
|
||||
asmstr # " $d, [${s2}+]$off10", []>;
|
||||
}
|
||||
: BO<op1, op2, (outs), (ins dc:$s1, AddrRegs:$s2, s10imm:$off10),
|
||||
asmstr # " $s1, [${s2}+]$off10", []>;
|
||||
|
||||
|
||||
multiclass mIABS_BO<bits<8> abs1, bits<2> abs2, ///_abs
|
||||
bits<8> prefix1, bits<8> prefix2,
|
||||
@ -1602,17 +1598,16 @@ class IBO_r_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc>
|
||||
// P[b], off10, A[a] (BO)(Circular Addressing Mode)
|
||||
class IBO_c_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc>
|
||||
: BO<op1, op2, (outs AddrExtRegs:$d), (ins rc:$s1, s10imm:$off10),
|
||||
asmstr # " $d, [${s1}+c]", []>;
|
||||
asmstr # " $d, [${s1}+c]$off10", []>;
|
||||
// A[b], off10, A[a] (BO)(Post-increment Addressing Mode)
|
||||
let Constraints = "$s1 = $d" in {
|
||||
class IBO_pos_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc>
|
||||
: BO<op1, op2, (outs AddrRegs:$d), (ins rc:$s1, s10imm:$off10),
|
||||
asmstr # " $d, [+$s1]$off10", []>;
|
||||
: BO<op1, op2, (outs), (ins rc:$s1, AddrRegs:$s2, s10imm:$off10),
|
||||
asmstr # " $s2, [+$s1]$off10", []>;
|
||||
// A[b], off10, A[a] (BO)(Pre-increment Addressing Mode)
|
||||
class IBO_pre_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc>
|
||||
: BO<op1, op2, (outs AddrRegs:$d), (ins rc:$s1, s10imm:$off10),
|
||||
asmstr # " $d, [${s1}+]$off10", []>;
|
||||
}
|
||||
: BO<op1, op2, (outs), (ins rc:$s1, AddrRegs:$s2, s10imm:$off10),
|
||||
asmstr # " $s2, [${s1}+]$off10", []>;
|
||||
|
||||
|
||||
multiclass mIBO_st<bits<8> prefix1, bits<8> prefix2,
|
||||
bits<6> bso2, ///_bso
|
||||
|
||||
@ -119,38 +119,26 @@ def FCX : TriCorePSReg<3, "fcx">, DwarfRegNum<[43]>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def DataRegs : RegisterClass<"TriCore", [i32], 32, (add
|
||||
// Implict Data
|
||||
D15,
|
||||
// Mostly Used
|
||||
D2, D3,
|
||||
D4, D5, D6, D7,
|
||||
D8, D9, D10, D11,
|
||||
D12, D13, D14,
|
||||
// Others - Compiler Specific
|
||||
D0, D1)>;
|
||||
D0, D1, D2, D3, D4,
|
||||
D5, D6, D7, D8, D9,
|
||||
D10, D11, D12, D13, D14,
|
||||
D15)>;
|
||||
|
||||
def AddrRegs : RegisterClass<"TriCore", [i32], 32, (add
|
||||
// Implicit Address
|
||||
A15,
|
||||
// Others
|
||||
A2, A3, A4, A5, A6,
|
||||
A7, A12, A13, A14,
|
||||
// Stack Pointer
|
||||
A10,
|
||||
// Return Address
|
||||
A11,
|
||||
// Global Address
|
||||
A0, A1, A8, A9)>;
|
||||
A0, A1, A2, A3, A4,
|
||||
A5, A6, A7, A8, A9,
|
||||
A10, A11, A12, A13, A14,
|
||||
A15)>;
|
||||
|
||||
def ExtRegs : RegisterClass<"TriCore", [i64], 64, (add
|
||||
E2, E4,
|
||||
E0, E2, E4,
|
||||
E6, E8, E10,
|
||||
E12, E14, E0)>;
|
||||
E12, E14)>;
|
||||
|
||||
def AddrExtRegs : RegisterClass<"TriCore", [i64], 64, (add
|
||||
P2, P4,
|
||||
P0, P2, P4,
|
||||
P6, P8, P10,
|
||||
P12, P14, P0)>;
|
||||
P12, P14)>;
|
||||
|
||||
def PSRegs : RegisterClass<"TriCore", [i32], 32, (add
|
||||
PSW, PCXI, PC, FCX)>;
|
||||
|
||||
23
suite/MC/TriCore/ADC_Background_Scan_1_KIT_TC275_LK.s.cs
Normal file
23
suite/MC/TriCore/ADC_Background_Scan_1_KIT_TC275_LK.s.cs
Normal file
@ -0,0 +1,23 @@
|
||||
# CS_ARCH_TRICORE, CS_MODE_TRICORE, None
|
||||
0x40,0x4f = mov.aa %a15, %a4
|
||||
0x02,0x48 = mov %d8, %d4
|
||||
0x02,0x29 = mov %d9, %d2
|
||||
0x02,0x94 = mov %d4, %d9
|
||||
0x3c,0x0b = j 80001c56 <IfxVadc_disableAccess+0x3c>
|
||||
0x02,0x94 = mov %d4, %d9
|
||||
0xa6,0x0f = or %d15, %d0
|
||||
0xa6,0x10 = or %d0, %d1
|
||||
0x82,0x11 = mov %d1, 1
|
||||
0xda,0x20 = mov %d15, 32
|
||||
0x82,0x10 = mov %d0, 1
|
||||
0x00,0x90 = ret
|
||||
0x09,0xf0,0x0c,0x29 = ld.w %d0, [%a15]140
|
||||
0x8f,0xf8,0x01,0xf1 = and %d15, %d8, 31
|
||||
0x0f,0xf1,0x10,0x10 = sha %d1, %d1, %d15
|
||||
0x89,0xf0,0x0c,0x29 = st.w [%a15]140, %d0
|
||||
0x6d,0xff,0xb3,0xff = call 80001bbe <IfxScuWdt_setSafetyEndinit>
|
||||
0x6d,0xff,0x02,0xfe = call 8000182a <IfxScuWdt_clearSafetyEndinit>
|
||||
0x7f,0xf8,0x0b,0x80 = jge.u %d8, %d15, 80001c42 <IfxVadc_disableAccess+0x28>
|
||||
0x89,0xff,0x08,0x29 = st.w [%a15]136, %d15
|
||||
0x0f,0x80,0x10,0x00 = sha %d0, %d0, %d8
|
||||
0x09,0xff,0x08,0x29 = ld.w %d15, [%a15]136
|
||||
Loading…
Reference in New Issue
Block a user