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x86: fix some compilation issues about missing instructions on CAPSTONE_X86_REDUCE setup
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2c24d88f89
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@ -211,6 +211,7 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
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break;
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}
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} else if (type == TYPE_IMM3) {
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#ifndef CAPSTONE_X86_REDUCE
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// Check for immediates that printSSECC can't handle.
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if (immediate >= 8) {
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unsigned NewOpc = 0;
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@ -229,7 +230,9 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
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// Switch opcode to the one that doesn't get special printing.
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MCInst_setOpcode(mcInst, NewOpc);
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}
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#endif
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} else if (type == TYPE_IMM5) {
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#ifndef CAPSTONE_X86_REDUCE
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// Check for immediates that printAVXCC can't handle.
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if (immediate >= 32) {
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unsigned NewOpc = 0;
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@ -260,6 +263,7 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
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// Switch opcode to the one that doesn't get special printing.
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MCInst_setOpcode(mcInst, NewOpc);
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}
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#endif
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}
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switch (type) {
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@ -950,6 +950,12 @@ static int readOpcode(struct InternalInstruction *insn)
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return 0;
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}
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// Hacky for FEMMS
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#ifndef CAPSTONE_X86_REDUCE
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#define GET_INSTRINFO_ENUM
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#include "X86GenInstrInfo.inc"
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#endif
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/*
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* getIDWithAttrMask - Determines the ID of an instruction, consuming
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* the ModR/M byte as appropriate for extended and escape opcodes,
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@ -970,11 +976,13 @@ static int getIDWithAttrMask(uint16_t *instructionID,
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InstructionContext instructionClass;
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#ifndef CAPSTONE_X86_REDUCE
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// HACK for femms. to be handled properly in next version 3.x
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if (insn->opcode == 0x0e && insn->opcodeType == T3DNOW_MAP) {
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*instructionID = 764;
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*instructionID = X86_FEMMS;
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return 0;
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}
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#endif
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if (insn->opcodeType == T3DNOW_MAP)
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instructionClass = IC_OF;
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@ -3055,7 +3055,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
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const char *AsmString;
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char *tmp, *AsmMnem, *AsmOps, *c;
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int OpIdx, PrintMethodIdx;
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MCRegisterInfo *MRI = (MCRegisterInfo *)info;
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switch (MCInst_getOpcode(MI)) {
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default: return NULL;
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case X86_AAD8i8:
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