Magic-Mirror/capstone
1
0
Fork 0
mirror of https://github.com/capstone-engine/capstone.git synced 2024-12-14 08:59:18 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

x86: fix some compilation issues about missing instructions on CAPSTONE_X86_REDUCE setup

Browse Source
This commit is contained in:
Nguyen Anh Quynh 2014-12-31 10:42:16 +08:00
parent 2c24d88f89
commit 599b559455
3 changed files with 13 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/X86/X86Disassembler.c
View File

@ -211,6 +211,7 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
break; break;
} }
} else if (type == TYPE_IMM3) { } else if (type == TYPE_IMM3) {
#ifndef CAPSTONE_X86_REDUCE
// Check for immediates that printSSECC can't handle. // Check for immediates that printSSECC can't handle.
if (immediate >= 8) { if (immediate >= 8) {
unsigned NewOpc = 0; unsigned NewOpc = 0;
@ -229,7 +230,9 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
// Switch opcode to the one that doesn't get special printing. // Switch opcode to the one that doesn't get special printing.
MCInst_setOpcode(mcInst, NewOpc); MCInst_setOpcode(mcInst, NewOpc);
} }
#endif
} else if (type == TYPE_IMM5) { } else if (type == TYPE_IMM5) {
#ifndef CAPSTONE_X86_REDUCE
// Check for immediates that printAVXCC can't handle. // Check for immediates that printAVXCC can't handle.
if (immediate >= 32) { if (immediate >= 32) {
unsigned NewOpc = 0; unsigned NewOpc = 0;
@ -260,6 +263,7 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
// Switch opcode to the one that doesn't get special printing. // Switch opcode to the one that doesn't get special printing.
MCInst_setOpcode(mcInst, NewOpc); MCInst_setOpcode(mcInst, NewOpc);
} }
#endif
} }
switch (type) { switch (type) {

10
arch/X86/X86DisassemblerDecoder.c
View File

@ -950,6 +950,12 @@ static int readOpcode(struct InternalInstruction *insn)
return 0; return 0;
} }
// Hacky for FEMMS
#ifndef CAPSTONE_X86_REDUCE
#define GET_INSTRINFO_ENUM
#include "X86GenInstrInfo.inc"
#endif
/* /*
* getIDWithAttrMask - Determines the ID of an instruction, consuming * getIDWithAttrMask - Determines the ID of an instruction, consuming
* the ModR/M byte as appropriate for extended and escape opcodes, * the ModR/M byte as appropriate for extended and escape opcodes,
@ -970,11 +976,13 @@ static int getIDWithAttrMask(uint16_t *instructionID,
InstructionContext instructionClass; InstructionContext instructionClass;
#ifndef CAPSTONE_X86_REDUCE
// HACK for femms. to be handled properly in next version 3.x // HACK for femms. to be handled properly in next version 3.x
if (insn->opcode == 0x0e && insn->opcodeType == T3DNOW_MAP) { if (insn->opcode == 0x0e && insn->opcodeType == T3DNOW_MAP) {
*instructionID = 764; *instructionID = X86_FEMMS;
return 0; return 0;
} }
#endif
if (insn->opcodeType == T3DNOW_MAP) if (insn->opcodeType == T3DNOW_MAP)
instructionClass = IC_OF; instructionClass = IC_OF;

1
arch/X86/X86GenAsmWriter_reduce.inc
View File

@ -3055,7 +3055,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
const char *AsmString; const char *AsmString;
char *tmp, *AsmMnem, *AsmOps, *c; char *tmp, *AsmMnem, *AsmOps, *c;
int OpIdx, PrintMethodIdx; int OpIdx, PrintMethodIdx;
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
switch (MCInst_getOpcode(MI)) { switch (MCInst_getOpcode(MI)) {
default: return NULL; default: return NULL;
case X86_AAD8i8: case X86_AAD8i8: