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x86: fix some compilation issues about missing instructions on CAPSTONE_X86_REDUCE setup

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This commit is contained in:
Nguyen Anh Quynh 2014-12-31 10:42:16 +08:00
parent 2c24d88f89
commit 599b559455
3 changed files with 13 additions and 2 deletions
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4
arch/X86/X86Disassembler.c
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@ -211,6 +211,7 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
break;
}
} else if (type == TYPE_IMM3) {
#ifndef CAPSTONE_X86_REDUCE
// Check for immediates that printSSECC can't handle.
if (immediate >= 8) {
unsigned NewOpc = 0;
@ -229,7 +230,9 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
// Switch opcode to the one that doesn't get special printing.
MCInst_setOpcode(mcInst, NewOpc);
}
#endif
} else if (type == TYPE_IMM5) {
#ifndef CAPSTONE_X86_REDUCE
// Check for immediates that printAVXCC can't handle.
if (immediate >= 32) {
unsigned NewOpc = 0;
@ -260,6 +263,7 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
// Switch opcode to the one that doesn't get special printing.
MCInst_setOpcode(mcInst, NewOpc);
}
#endif
}
switch (type) {

10
arch/X86/X86DisassemblerDecoder.c
View File

@ -950,6 +950,12 @@ static int readOpcode(struct InternalInstruction *insn)
return 0;
}
// Hacky for FEMMS
#ifndef CAPSTONE_X86_REDUCE
#define GET_INSTRINFO_ENUM
#include "X86GenInstrInfo.inc"
#endif
/*
* getIDWithAttrMask - Determines the ID of an instruction, consuming
* the ModR/M byte as appropriate for extended and escape opcodes,
@ -970,11 +976,13 @@ static int getIDWithAttrMask(uint16_t *instructionID,
InstructionContext instructionClass;
#ifndef CAPSTONE_X86_REDUCE
// HACK for femms. to be handled properly in next version 3.x
if (insn->opcode == 0x0e && insn->opcodeType == T3DNOW_MAP) {
*instructionID = 764;
*instructionID = X86_FEMMS;
return 0;
}
#endif
if (insn->opcodeType == T3DNOW_MAP)
instructionClass = IC_OF;

1
arch/X86/X86GenAsmWriter_reduce.inc
View File

@ -3055,7 +3055,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
const char *AsmString;
char *tmp, *AsmMnem, *AsmOps, *c;
int OpIdx, PrintMethodIdx;
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
switch (MCInst_getOpcode(MI)) {
default: return NULL;
case X86_AAD8i8: