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https://github.com/capstone-engine/capstone.git
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fix: TriCore Instruction Formats and Printing
- Add new operand type `off18imm` - Add `printOff18Imm` function for printing specific immediate value
This commit is contained in:
billow
parent
7e937d10ad
commit
5b7e20ad55
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -159,6 +159,18 @@ static void printSExtImm(MCInst *MI, int OpNum, SStream *O) {
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printOperand(MI, OpNum, O);
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}
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static inline void fill_tricore_imm(MCInst *MI, int64_t imm) {
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.type = TRICORE_OP_IMM;
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.imm = (int) imm;
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MI->flat_insn->detail->tricore.op_count++;
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}
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}
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static void sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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@ -178,15 +190,7 @@ static void sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
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else
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SStream_concat(O, "-%u", -imm);
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}
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.type = TRICORE_OP_IMM;
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.imm = (unsigned short int) imm;
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MI->flat_insn->detail->tricore.op_count++;
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}
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fill_tricore_imm(MI, imm);
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} else
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printOperand(MI, OpNum, O);
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}
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@ -236,15 +240,7 @@ static void zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
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else
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SStream_concat(O, "-%u", -imm);
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}
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if (MI->csh->detail) {
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.type = TRICORE_OP_IMM;
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MI->flat_insn->detail->tricore
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.operands[MI->flat_insn->detail->tricore.op_count]
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.imm = (unsigned short int) imm;
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MI->flat_insn->detail->tricore.op_count++;
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}
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fill_tricore_imm(MI, imm);
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} else
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printOperand(MI, OpNum, O);
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}
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@ -304,6 +300,17 @@ printZExtImm_(2)
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printZExtImm_(1)
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static void printOff18Imm(MCInst *MI, int OpNum, SStream *O) {
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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uint32_t imm = (uint32_t) MCOperand_getImm(MO);
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imm = ((imm & 0x3C000)<< 14) | (imm & 0x3fff);
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SStream_concat(O, "0x%x", imm);
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fill_tricore_imm(MI, imm);
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} else
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printOperand(MI, OpNum, O);
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}
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static void printPCRelImmOperand(MCInst *MI, int OpNum, SStream *O) {
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MCOperand *Op = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(Op)) {
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@ -184,6 +184,9 @@ def u4imm : Operand<i32> { let PrintMethod = "printZExtImm<4>"; }
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def u2imm : Operand<i32> { let PrintMethod = "printZExtImm<2>"; }
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def u9imm : Operand<i32> { let PrintMethod = "printZExtImm<9>"; }
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def u16imm : Operand<i32> { let PrintMethod = "printZExtImm<16>"; }
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def off18imm : Operand<i32> { let PrintMethod = "printOff18Imm"; }
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def bl_target : Operand<i32>;
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def b_target : Operand<OtherVT>;
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def cc_val : Operand<i32> { let PrintMethod = "printCondCode"; }
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@ -752,25 +755,25 @@ def CMOVN_src : ISRC_a15<0xEA, "cmovn">;
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def CMOVN_srr : ISRR_a15<0x6A, "cmovn">;
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// A[b], off10, E[a] (BO)(Base + Short Offset Addressing Mode)
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class IBO_bsoEa<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs), (ins AddrRegs:$s2, s10imm:$off10, AddrExtRegs:$s1),
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asmstr # " $s1, [$s2]$off10", []>;
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class IBO_bsoAbOEa<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs), (ins ExtRegs:$s1, AddrRegs:$s2, s10imm:$off10),
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asmstr # " [$s2]$off10, $s1", []>;
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// P[b], E[a] (BO)(Bit-reverse Addressing Mode)
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class IBO_rEa<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs AddrExtRegs:$b), (ins AddrRegs:$s2, AddrExtRegs:$s1),
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asmstr # " $s1, [${b}+r]", []>;
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class IBO_rPbEa<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs), (ins ExtRegs:$s1, AddrExtRegs:$s2),
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asmstr # " $s2, $s1", []>;
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// P[b], off10, E[a] (BO)(Circular Addressing Mode)
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class IBO_cEa<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs AddrExtRegs:$b), (ins s10imm:$off10, AddrExtRegs:$s1),
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asmstr # " $s1, [${b}+c]", []>;
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class IBO_cPbOEa<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs), (ins ExtRegs:$s1, AddrExtRegs:$s2, s10imm:$off10),
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asmstr # " [$s2]$off10, $s1", []>;
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// A[b], off10, E[a] (BO)(Post-increment Addressing Mode)
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class IBO_posEa<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs), (ins AddrExtRegs:$s1, AddrRegs:$s2, s10imm:$off10),
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asmstr # " $s1, [${s2}+]$off10", []>;
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class IBO_posAbOEa<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs), (ins ExtRegs:$s1, AddrRegs:$s2, s10imm:$off10),
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asmstr # " [$s2+]$off10, $s1", []>;
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// A[b], off10, E[a] (BO)(Pre-increment Addressing Mode)
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class IBO_preEa<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs), (ins AddrExtRegs:$s1, AddrRegs:$s2, s10imm:$off10),
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asmstr # " $s1, [+${s2}]$off10", []>;
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class IBO_preAbOEa<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs), (ins ExtRegs:$s1, AddrRegs:$s2, s10imm:$off10),
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asmstr # " [+$s2]$off10, $s1", []>;
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multiclass mIBO_Ea<bits<8> bso1, bits<6> bso2, ///_bso
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@ -779,11 +782,11 @@ multiclass mIBO_Ea<bits<8> bso1, bits<6> bso2, ///_bso
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bits<8> pos1, bits<6> pos_r, ///_post
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bits<8> pre1, bits<6> pre_c, ///_pre
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string asmstr>{
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def _bo_bso : IBO_bsoEa<bso1, bso2, asmstr>;
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def _bo_pos : IBO_posEa<pos1, pos_r, asmstr>;
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def _bo_pre : IBO_preEa<pre1, pre_c, asmstr>;
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def _bo_r : IBO_rEa<r1, r2, asmstr>;
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def _bo_c : IBO_cEa<c1, c2, asmstr>;
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def _bo_bso : IBO_bsoAbOEa<bso1, bso2, asmstr>;
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def _bo_pos : IBO_posAbOEa<pos1, pos_r, asmstr>;
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def _bo_pre : IBO_preAbOEa<pre1, pre_c, asmstr>;
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def _bo_r : IBO_rPbEa<r1, r2, asmstr>;
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def _bo_c : IBO_cPbOEa<c1, c2, asmstr>;
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}
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defm CMPSWAP_W : mIBO_Ea<0x49, 0x23, 0x69, 0x03,
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@ -1115,13 +1118,13 @@ defm JZ : mISB_SBR_T_BRN_SBRN<0x6E, 0x76, 0xBD, 0x00, 0xBC, 0x6F, 0x00, 0x2E, "
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class IABS_off18<bits<8> op1, bits<2> op2, string asmstr>
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: ABS<op1, op2, (outs), (ins i32imm:$off18),
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: ABS<op1, op2, (outs), (ins off18imm:$off18),
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asmstr # " $off18", []>;
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class IABS_RO<bits<8> op1, bits<2> op2, string asmstr, RegisterClass dc>
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: ABS<op1, op2, (outs dc:$d), (ins i32imm:$off18),
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: ABS<op1, op2, (outs dc:$d), (ins off18imm:$off18),
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asmstr # " $d, $off18", []>;
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class IABS_OR<bits<8> op1, bits<2> op2, string asmstr, RegisterClass s1c>
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: ABS<op1, op2, (outs), (ins s1c:$s1, i32imm:$off18),
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: ABS<op1, op2, (outs), (ins s1c:$s1, off18imm:$off18),
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asmstr # " $off18, $s1", []>;
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class IBOL_RAaO<bits<8> op1, string asmstr, RegisterClass rc>
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@ -1129,7 +1132,7 @@ class IBOL_RAaO<bits<8> op1, string asmstr, RegisterClass rc>
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asmstr # " $s1, [$s2]$off16", []>;
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class IBOL_AbOR<bits<8> op1, string asmstr, RegisterClass rc>
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: BOL<op1, (outs AddrRegs:$s2), (ins rc:$s1, i32imm:$off16),
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: BOL<op1, (outs AddrRegs:$s2), (ins rc:$s1, s16imm:$off16),
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asmstr # " [$s2]$off16, $s1", []>;
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class ISLR<bits<8> op1, string asmstr, RegisterClass dc>
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@ -1701,7 +1704,7 @@ defm ST_B : mISRO_SSR_SSRO_st<0x2C, 0x34, 0x24, 0x28, "st.b", DataRegs>;
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def ST_H_bol : IBOL_AbOR<0xF9, "st.h", DataRegs>;
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defm ST_H : mISRO_SSR_SSRO_st<0xAC, 0xB4, 0xA4, 0xA8, "st.h", DataRegs>;
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def ST_T : ABSB<0xD5, 0x00, (outs), (ins i32imm:$off18, i32imm:$bpos3, i32imm:$b),
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def ST_T : ABSB<0xD5, 0x00, (outs), (ins off18imm:$off18, i32imm:$bpos3, i32imm:$b),
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"st.t $off18, $bpos3, $b", []>;
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defm ST_W : mIABS_BO_st<0xA5, 0x00, 0x89, 0xA9, 0x24, 0x04, 0x14, "st.w", DataRegs>
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@ -80,7 +80,7 @@
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0x4c,0xe2 = ld.w %d15, [%a14]8
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0x6c,0xe2 = st.w [%a14]8, %d15
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0x08,0xb0 = ld.bu %d0, [%a15]11
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0x09,0xc2,0x00,0x08 = ld.b %d2, [%a12]
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0x09,0xc2,0x00,0x08 = ld.b %d2, [%a12]0
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0x09,0xe1,0x20,0x49 = ld.w %d1, [%a14]288
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0x89,0xe1,0x20,0x49 = st.w [%a14]288, %d1
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0x09,0xef,0x20,0x49 = ld.w %d15, [%a14]288
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@ -301,45 +301,45 @@
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0x74,0x2f = st.w [%a2], %d15
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0x39,0x2f,0x30,0x46 = ld.bu %d15, [%a2]24880
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0x39,0x2f,0x30,0x46 = ld.bu %d15, [%a2]24880
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0xe9,0x2f,0x30,0x46 = st.b [%a2]24880
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0xe9,0x2f,0x30,0x46 = st.b [%a2]24880, %d15
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0x39,0x2f,0x33,0x06 = ld.bu %d15, [%a2]24627
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0x39,0x2f,0x33,0x06 = ld.bu %d15, [%a2]24627
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0xe9,0x2f,0x33,0x06 = st.b [%a2]24627
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0xe9,0x2f,0x33,0x06 = st.b [%a2]24627, %d15
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0x39,0x2f,0x33,0x06 = ld.bu %d15, [%a2]24627
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0xe9,0x2f,0x33,0x06 = st.b [%a2]24627
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0xe9,0x2f,0x33,0x06 = st.b [%a2]24627, %d15
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0x39,0x2f,0x18,0x06 = ld.bu %d15, [%a2]24600
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0xe9,0x2f,0x18,0x06 = st.b [%a2]24600
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0xe9,0x2f,0x18,0x06 = st.b [%a2]24600, %d15
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0x39,0x2f,0x33,0x06 = ld.bu %d15, [%a2]24627
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0x39,0x2f,0x37,0x06 = ld.bu %d15, [%a2]24631
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0xe9,0x2f,0x37,0x06 = st.b [%a2]24631
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0xe9,0x2f,0x37,0x06 = st.b [%a2]24631, %d15
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0x39,0x2f,0x37,0x06 = ld.bu %d15, [%a2]24631
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0xe9,0x2f,0x37,0x06 = st.b [%a2]24631
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0xe9,0x2f,0x37,0x06 = st.b [%a2]24631, %d15
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0x39,0x2f,0x14,0x06 = ld.bu %d15, [%a2]24596
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0x39,0x20,0x1c,0x06 = ld.bu %d0, [%a2]24604
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0x08,0xaf = ld.bu %d15, [%a15]10
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0xe9,0x2f,0x1c,0x06 = st.b [%a2]24604
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0xe9,0x2f,0x1c,0x06 = st.b [%a2]24604, %d15
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0x39,0x20,0x1b,0x06 = ld.bu %d0, [%a2]24603
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0x08,0x8f = ld.bu %d15, [%a15]8
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0xe9,0x2f,0x1b,0x06 = st.b [%a2]24603
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0xe9,0x2f,0x1b,0x06 = st.b [%a2]24603, %d15
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0x39,0x20,0x19,0x06 = ld.bu %d0, [%a2]24601
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0x08,0x9f = ld.bu %d15, [%a15]9
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0xe9,0x2f,0x19,0x06 = st.b [%a2]24601
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0xe9,0x2f,0x19,0x06 = st.b [%a2]24601, %d15
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0x39,0x2f,0x18,0x06 = ld.bu %d15, [%a2]24600
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0xe9,0x2f,0x18,0x06 = st.b [%a2]24600
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0xe9,0x2f,0x18,0x06 = st.b [%a2]24600, %d15
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0x39,0x2f,0x1a,0x06 = ld.bu %d15, [%a2]24602
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0xe9,0x2f,0x1a,0x06 = st.b [%a2]24602
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0xe9,0x2f,0x1a,0x06 = st.b [%a2]24602, %d15
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0x39,0x2f,0x18,0x06 = ld.bu %d15, [%a2]24600
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0xe9,0x2f,0x18,0x06 = st.b [%a2]24600
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0xe9,0x2f,0x18,0x06 = st.b [%a2]24600, %d15
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0x39,0x2f,0x1a,0x06 = ld.bu %d15, [%a2]24602
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0xe9,0x2f,0x1a,0x06 = st.b [%a2]24602
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0xe9,0x2f,0x1a,0x06 = st.b [%a2]24602, %d15
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0x39,0x2f,0x1a,0x06 = ld.bu %d15, [%a2]24602
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0xe9,0x2f,0x1a,0x06 = st.b [%a2]24602
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0xe9,0x2f,0x1a,0x06 = st.b [%a2]24602, %d15
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0x39,0x2f,0x14,0x06 = ld.bu %d15, [%a2]24596
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0x39,0x2f,0x18,0x06 = ld.bu %d15, [%a2]24600
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0xe9,0x2f,0x18,0x06 = st.b [%a2]24600
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0xe9,0x2f,0x18,0x06 = st.b [%a2]24600, %d15
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0x39,0x2f,0x33,0x06 = ld.bu %d15, [%a2]24627
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0x39,0x2f,0x33,0x06 = ld.bu %d15, [%a2]24627
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0xe9,0x2f,0x33,0x06 = st.b [%a2]24627
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0xe9,0x2f,0x33,0x06 = st.b [%a2]24627, %d15
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0x39,0x2f,0x33,0x06 = ld.bu %d15, [%a2]24627
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0x48,0x34 = ld.w %d4, [%a15]12
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0x19,0x20,0x30,0x06 = ld.w %d0, [%a2]24624
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@ -390,7 +390,7 @@
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0x39,0x20,0x1c,0x06 = ld.bu %d0, [%a2]24604
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0xc8,0x12 = ld.a %a2, [%a15]4
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0x14,0x2f = ld.bu %d15, [%a2]
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0xe9,0x2f,0x1c,0x06 = st.b [%a2]24604
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0xe9,0x2f,0x1c,0x06 = st.b [%a2]24604, %d15
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0xc8,0x12 = ld.a %a2, [%a15]4
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0x4c,0x22 = ld.w %d15, [%a2]8
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0xc8,0x12 = ld.a %a2, [%a15]4
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@ -399,27 +399,27 @@
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0x09,0x24,0x02,0x09 = ld.w %d4, [%a2]2
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0x14,0xff = ld.bu %d15, [%a15]
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0x39,0xff,0x18,0x06 = ld.bu %d15, [%a15]24600
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0xe9,0xff,0x18,0x06 = st.b [%a15]24600
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0xe9,0xff,0x18,0x06 = st.b [%a15]24600, %d15
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0x39,0xff,0x2c,0x46 = ld.bu %d15, [%a15]24876
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0xe9,0xff,0x2c,0x46 = st.b [%a15]24876
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0xe9,0xff,0x2c,0x46 = st.b [%a15]24876, %d15
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0x39,0xff,0x30,0x46 = ld.bu %d15, [%a15]24880
|
||||
0xe9,0xff,0x30,0x46 = st.b [%a15]24880
|
||||
0xe9,0xff,0x30,0x46 = st.b [%a15]24880, %d15
|
||||
0x39,0xf0,0x10,0x06 = ld.bu %d0, [%a15]24592
|
||||
0xe9,0xf0,0x10,0x06 = st.b [%a15]24592
|
||||
0xe9,0xf0,0x10,0x06 = st.b [%a15]24592, %d0
|
||||
0x39,0xf0,0x12,0x06 = ld.bu %d0, [%a15]24594
|
||||
0x54,0xf1 = ld.w %d1, [%a15]
|
||||
0xe9,0xff,0x12,0x06 = st.b [%a15]24594
|
||||
0xe9,0xff,0x12,0x06 = st.b [%a15]24594, %d15
|
||||
0x39,0xff,0x10,0x06 = ld.bu %d15, [%a15]24592
|
||||
0xe9,0xff,0x10,0x06 = st.b [%a15]24592
|
||||
0xe9,0xff,0x10,0x06 = st.b [%a15]24592, %d15
|
||||
0x39,0xff,0x10,0x06 = ld.bu %d15, [%a15]24592
|
||||
0x39,0xff,0x11,0x06 = ld.bu %d15, [%a15]24593
|
||||
0x39,0xff,0x2c,0x46 = ld.bu %d15, [%a15]24876
|
||||
0xe9,0xff,0x2c,0x46 = st.b [%a15]24876
|
||||
0xe9,0xff,0x2c,0x46 = st.b [%a15]24876, %d15
|
||||
0x39,0xff,0x30,0x46 = ld.bu %d15, [%a15]24880
|
||||
0xe9,0xff,0x30,0x46 = st.b [%a15]24880
|
||||
0xe9,0xff,0x30,0x46 = st.b [%a15]24880, %d15
|
||||
0x39,0xff,0x35,0x06 = ld.bu %d15, [%a15]24629
|
||||
0x85,0xf1,0x10,0x00 = ld.w %d1, f0000010
|
||||
0x85,0xf0,0x10,0x00 = ld.w %d0, f0000010
|
||||
0x85,0xf1,0x10,0x00 = ld.w %d1, 0xf0000010
|
||||
0x85,0xf0,0x10,0x00 = ld.w %d0, 0xf0000010
|
||||
0x54,0xff = ld.w %d15, [%a15]
|
||||
0x54,0xf0 = ld.w %d0, [%a15]
|
||||
0x74,0xff = st.w [%a15], %d15
|
||||
@ -428,9 +428,9 @@
|
||||
0x54,0xff = ld.w %d15, [%a15]
|
||||
0x19,0xff,0x30,0x36 = ld.w %d15, [%a15]24816
|
||||
0x19,0xf0,0x30,0x36 = ld.w %d0, [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816, %d15
|
||||
0x19,0xf0,0x30,0x36 = ld.w %d0, [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816, %d15
|
||||
0x19,0xff,0x30,0x36 = ld.w %d15, [%a15]24816
|
||||
0x54,0xff = ld.w %d15, [%a15]
|
||||
0x54,0xf0 = ld.w %d0, [%a15]
|
||||
@ -448,17 +448,17 @@
|
||||
0x54,0xff = ld.w %d15, [%a15]
|
||||
0x19,0xff,0x30,0x36 = ld.w %d15, [%a15]24816
|
||||
0x19,0xf0,0x30,0x36 = ld.w %d0, [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816, %d15
|
||||
0x19,0xf0,0x30,0x36 = ld.w %d0, [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816, %d15
|
||||
0x19,0xff,0x30,0x36 = ld.w %d15, [%a15]24816
|
||||
0x39,0xff,0x34,0x36 = ld.bu %d15, [%a15]24820
|
||||
0xe9,0xff,0x34,0x36 = st.b [%a15]24820
|
||||
0xe9,0xff,0x34,0x36 = st.b [%a15]24820, %d15
|
||||
0x19,0xff,0x30,0x36 = ld.w %d15, [%a15]24816
|
||||
0x19,0xf0,0x30,0x36 = ld.w %d0, [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816, %d15
|
||||
0x19,0xf0,0x30,0x36 = ld.w %d0, [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816, %d15
|
||||
0x19,0xff,0x30,0x36 = ld.w %d15, [%a15]24816
|
||||
0x54,0xff = ld.w %d15, [%a15]
|
||||
0x54,0xf0 = ld.w %d0, [%a15]
|
||||
@ -476,17 +476,17 @@
|
||||
0x54,0xff = ld.w %d15, [%a15]
|
||||
0x19,0xff,0x30,0x36 = ld.w %d15, [%a15]24816
|
||||
0x19,0xf0,0x30,0x36 = ld.w %d0, [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816, %d15
|
||||
0x19,0xf0,0x30,0x36 = ld.w %d0, [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816, %d15
|
||||
0x19,0xff,0x30,0x36 = ld.w %d15, [%a15]24816
|
||||
0x39,0xff,0x34,0x36 = ld.bu %d15, [%a15]24820
|
||||
0xe9,0xff,0x34,0x36 = st.b [%a15]24820
|
||||
0xe9,0xff,0x34,0x36 = st.b [%a15]24820, %d15
|
||||
0x19,0xff,0x30,0x36 = ld.w %d15, [%a15]24816
|
||||
0x19,0xf0,0x30,0x36 = ld.w %d0, [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816, %d15
|
||||
0x19,0xf0,0x30,0x36 = ld.w %d0, [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816, %d15
|
||||
0x19,0xff,0x30,0x36 = ld.w %d15, [%a15]24816
|
||||
0x54,0xff = ld.w %d15, [%a15]
|
||||
0x54,0xff = ld.w %d15, [%a15]
|
||||
@ -498,24 +498,24 @@
|
||||
0x54,0xff = ld.w %d15, [%a15]
|
||||
0x19,0xff,0x30,0x36 = ld.w %d15, [%a15]24816
|
||||
0x19,0xf0,0x30,0x36 = ld.w %d0, [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816, %d15
|
||||
0x19,0xf0,0x30,0x36 = ld.w %d0, [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816
|
||||
0x59,0xff,0x30,0x36 = st.w [%a15]24816, %d15
|
||||
0x19,0xff,0x30,0x36 = ld.w %d15, [%a15]24816
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp], %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp], %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp], %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp], %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp], %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp], %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp], %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp]0, %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]0
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp]0, %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]0
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp]0, %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]0
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp]0, %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]0
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp]0, %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]0
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp]0, %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]0
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp]0, %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]0
|
||||
0x54,0x31 = ld.w %d1, [%a3]
|
||||
0x08,0x1f = ld.bu %d15, [%a15]1
|
||||
0x08,0x1f = ld.bu %d15, [%a15]1
|
||||
@ -531,8 +531,8 @@
|
||||
0x54,0x3f = ld.w %d15, [%a3]
|
||||
0x74,0x3f = st.w [%a3], %d15
|
||||
0x39,0x2f,0x35,0x06 = ld.bu %d15, [%a2]24629
|
||||
0x85,0xf1,0x10,0x00 = ld.w %d1, f0000010
|
||||
0x85,0xff,0x10,0x00 = ld.w %d15, f0000010
|
||||
0x85,0xf1,0x10,0x00 = ld.w %d1, 0xf0000010
|
||||
0x85,0xff,0x10,0x00 = ld.w %d15, 0xf0000010
|
||||
0x54,0xff = ld.w %d15, [%a15]
|
||||
0x49,0x40,0x40,0x08 = ldmst [%a4]0, %e0
|
||||
0x54,0xff = ld.w %d15, [%a15]
|
||||
@ -658,11 +658,11 @@
|
||||
0x54,0xff = ld.w %d15, [%a15]
|
||||
0x74,0x41 = st.w [%a4], %d1
|
||||
0x74,0x4f = st.w [%a4], %d15
|
||||
0x15,0xd0,0xc0,0xe3 = stlcx d0003f80
|
||||
0x15,0xd0,0xc0,0xf7 = stucx d0003fc0
|
||||
0x85,0xdf,0xc4,0xf3 = ld.w %d15, d0003fc4
|
||||
0x15,0xd0,0xc0,0xff = lducx d0003fc0
|
||||
0x15,0xd0,0xc0,0xeb = ldlcx d0003f80
|
||||
0x15,0xd0,0xc0,0xe3 = stlcx 0xd0003f80
|
||||
0x15,0xd0,0xc0,0xf7 = stucx 0xd0003fc0
|
||||
0x85,0xdf,0xc4,0xf3 = ld.w %d15, 0xd0003fc4
|
||||
0x15,0xd0,0xc0,0xff = lducx 0xd0003fc0
|
||||
0x15,0xd0,0xc0,0xeb = ldlcx 0xd0003f80
|
||||
0xd4,0xff = ld.a %a15, [%a15]
|
||||
0x39,0xff,0x05,0x80 = ld.bu %d15, [%a15]517
|
||||
0xe9,0xff,0x05,0x80 = st.b [%a15]517, %d15
|
||||
@ -671,7 +671,7 @@
|
||||
0x89,0xaf,0x31,0x08 = st.b [%sp]49, %d15
|
||||
0x89,0xaf,0x24,0x08 = st.b [%sp]36, %d15
|
||||
0x89,0xaf,0x28,0x08 = st.b [%sp]40, %d15
|
||||
0x09,0x2f,0x00,0x08 = ld.b %d15, [%a2]
|
||||
0x09,0x2f,0x00,0x08 = ld.b %d15, [%a2]0
|
||||
0x2c,0xfc = st.b [%a15]12, %d15
|
||||
0x28,0xf8 = st.b [%a15]15, %d8
|
||||
0x2c,0xf2 = st.b [%a15]2, %d15
|
||||
@ -713,5 +713,5 @@
|
||||
0x44,0x21 = ld.w %d1, [%a2+]
|
||||
0x64,0xc1 = st.w [%a12+], %d1
|
||||
0x64,0xc8 = st.w [%a12+], %d8
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp], %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]
|
||||
0x89,0xa2,0x40,0x09 = st.d [%sp]0, %e2
|
||||
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]0
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user