mirror of
https://github.com/capstone-engine/capstone.git
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add MTCR
This commit is contained in:
billow
parent
1c190c49cc
commit
6381b0750e
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -831,262 +831,263 @@
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TriCore_MSUB_rcr_e = 820,
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TriCore_MSUB_rrr2 = 821,
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TriCore_MSUB_rrr2_e = 822,
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TriCore_MULM_H_rr1_LL2e = 823,
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TriCore_MULM_H_rr1_LU2e = 824,
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TriCore_MULM_H_rr1_UL2e = 825,
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TriCore_MULM_H_rr1_UU2e = 826,
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TriCore_MULR_H_rr1_LL2e = 827,
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TriCore_MULR_H_rr1_LU2e = 828,
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TriCore_MULR_H_rr1_UL2e = 829,
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TriCore_MULR_H_rr1_UU2e = 830,
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TriCore_MULR_Q_rr1_2LL = 831,
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TriCore_MULR_Q_rr1_2UU = 832,
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TriCore_MULS_U_rc = 833,
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TriCore_MULS_U_rr2 = 834,
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TriCore_MULS_rc = 835,
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TriCore_MULS_rr2 = 836,
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TriCore_MUL_F_rrr = 837,
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TriCore_MUL_H_rr1_LL2e = 838,
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TriCore_MUL_H_rr1_LU2e = 839,
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TriCore_MUL_H_rr1_UL2e = 840,
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TriCore_MUL_H_rr1_UU2e = 841,
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TriCore_MUL_Q_rr1_2LL = 842,
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TriCore_MUL_Q_rr1_2UU = 843,
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TriCore_MUL_Q_rr1_2_L = 844,
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TriCore_MUL_Q_rr1_2_Le = 845,
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TriCore_MUL_Q_rr1_2_U = 846,
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TriCore_MUL_Q_rr1_2_Ue = 847,
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TriCore_MUL_Q_rr1_2__ = 848,
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TriCore_MUL_Q_rr1_2__e = 849,
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TriCore_MUL_U_rc = 850,
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TriCore_MUL_U_rr2 = 851,
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TriCore_MUL_rc = 852,
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TriCore_MUL_rc_e = 853,
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TriCore_MUL_rr2 = 854,
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TriCore_MUL_rr2_e = 855,
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TriCore_MUL_srr = 856,
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TriCore_NAND_T = 857,
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TriCore_NAND_rc = 858,
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TriCore_NAND_rr = 859,
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TriCore_NEZ_A = 860,
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TriCore_NE_A = 861,
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TriCore_NE_rc = 862,
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TriCore_NE_rr = 863,
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TriCore_NOP_sr = 864,
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TriCore_NOP_sys = 865,
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TriCore_NOR_T = 866,
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TriCore_NOR_rc = 867,
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TriCore_NOR_rr = 868,
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TriCore_NOT_sr = 869,
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TriCore_ORN_T = 870,
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TriCore_ORN_rc = 871,
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TriCore_ORN_rr = 872,
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TriCore_OR_ANDN_T = 873,
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TriCore_OR_AND_T = 874,
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TriCore_OR_EQ_rc = 875,
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TriCore_OR_EQ_rr = 876,
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TriCore_OR_GE_U_rc = 877,
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TriCore_OR_GE_U_rr = 878,
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TriCore_OR_GE_rc = 879,
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TriCore_OR_GE_rr = 880,
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TriCore_OR_LT_U_rc = 881,
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TriCore_OR_LT_U_rr = 882,
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TriCore_OR_LT_rc = 883,
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TriCore_OR_LT_rr = 884,
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TriCore_OR_NE_rc = 885,
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TriCore_OR_NE_rr = 886,
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TriCore_OR_NOR_T = 887,
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TriCore_OR_OR_T = 888,
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TriCore_OR_T = 889,
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TriCore_OR_rc = 890,
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TriCore_OR_rr = 891,
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TriCore_OR_sc = 892,
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TriCore_OR_srr = 893,
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TriCore_PACK_rrr = 894,
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TriCore_PARITY_rr = 895,
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TriCore_POPCNT_W_rr = 896,
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TriCore_Q31TOF_rr = 897,
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TriCore_QSEED_F_rr = 898,
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TriCore_RESTORE_sys = 899,
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TriCore_RET_sr = 900,
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TriCore_RET_sys = 901,
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TriCore_RFE_sr = 902,
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TriCore_RFE_sys = 903,
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TriCore_RFM_sys = 904,
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TriCore_RSLCX_sys = 905,
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TriCore_RSTV_sys = 906,
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TriCore_RSUBS_U_rc = 907,
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TriCore_RSUBS_rc = 908,
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TriCore_RSUB_rc = 909,
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TriCore_RSUB_sr = 910,
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TriCore_SAT_BU_rr = 911,
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TriCore_SAT_BU_sr = 912,
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TriCore_SAT_B_rr = 913,
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TriCore_SAT_B_sr = 914,
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TriCore_SAT_HU_rr = 915,
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TriCore_SAT_HU_sr = 916,
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TriCore_SAT_H_rr = 917,
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TriCore_SAT_H_sr = 918,
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TriCore_SELN_rcr = 919,
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TriCore_SELN_rrr = 920,
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TriCore_SEL_rcr = 921,
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TriCore_SEL_rrr = 922,
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TriCore_SHAS_rc = 923,
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TriCore_SHAS_rr = 924,
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TriCore_SHA_H_rc = 925,
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TriCore_SHA_H_rr = 926,
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TriCore_SHA_rc = 927,
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TriCore_SHA_rr = 928,
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TriCore_SHA_src = 929,
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TriCore_SHUFFLE_rc = 930,
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TriCore_SH_ANDN_T = 931,
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TriCore_SH_AND_T = 932,
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TriCore_SH_EQ_rc = 933,
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TriCore_SH_EQ_rr = 934,
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TriCore_SH_GE_U_rc = 935,
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TriCore_SH_GE_U_rr = 936,
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TriCore_SH_GE_rc = 937,
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TriCore_SH_GE_rr = 938,
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TriCore_SH_H_rc = 939,
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TriCore_SH_H_rr = 940,
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TriCore_SH_LT_U_rc = 941,
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TriCore_SH_LT_U_rr = 942,
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TriCore_SH_LT_rc = 943,
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TriCore_SH_LT_rr = 944,
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TriCore_SH_NAND_T = 945,
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TriCore_SH_NE_rc = 946,
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TriCore_SH_NE_rr = 947,
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TriCore_SH_NOR_T = 948,
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TriCore_SH_ORN_T = 949,
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TriCore_SH_OR_T = 950,
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TriCore_SH_XNOR_T = 951,
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TriCore_SH_XOR_T = 952,
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TriCore_SH_rc = 953,
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TriCore_SH_rr = 954,
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TriCore_SH_src = 955,
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TriCore_STLCX_abs = 956,
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TriCore_STLCX_bo_bso = 957,
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TriCore_STUCX_abs = 958,
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TriCore_STUCX_bo_bso = 959,
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TriCore_ST_A_abs = 960,
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TriCore_ST_A_bo_bso = 961,
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TriCore_ST_A_bo_c = 962,
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TriCore_ST_A_bo_pos = 963,
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TriCore_ST_A_bo_pre = 964,
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TriCore_ST_A_bo_r = 965,
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TriCore_ST_A_bol = 966,
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TriCore_ST_A_sc = 967,
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TriCore_ST_A_sro = 968,
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TriCore_ST_A_ssr = 969,
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TriCore_ST_A_ssr_pos = 970,
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TriCore_ST_A_ssro = 971,
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TriCore_ST_B_abs = 972,
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TriCore_ST_B_bo_bso = 973,
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TriCore_ST_B_bo_c = 974,
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TriCore_ST_B_bo_pos = 975,
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TriCore_ST_B_bo_pre = 976,
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TriCore_ST_B_bo_r = 977,
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TriCore_ST_B_bol = 978,
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TriCore_ST_B_sro = 979,
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TriCore_ST_B_ssr = 980,
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TriCore_ST_B_ssr_pos = 981,
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TriCore_ST_B_ssro = 982,
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TriCore_ST_DA_abs = 983,
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TriCore_ST_DA_bo_bso = 984,
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TriCore_ST_DA_bo_c = 985,
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TriCore_ST_DA_bo_pos = 986,
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TriCore_ST_DA_bo_pre = 987,
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TriCore_ST_DA_bo_r = 988,
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TriCore_ST_D_abs = 989,
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TriCore_ST_D_bo_bso = 990,
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TriCore_ST_D_bo_c = 991,
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TriCore_ST_D_bo_pos = 992,
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TriCore_ST_D_bo_pre = 993,
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TriCore_ST_D_bo_r = 994,
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TriCore_ST_H_abs = 995,
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TriCore_ST_H_bo_bso = 996,
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TriCore_ST_H_bo_c = 997,
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TriCore_ST_H_bo_pos = 998,
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TriCore_ST_H_bo_pre = 999,
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TriCore_ST_H_bo_r = 1000,
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TriCore_ST_H_bol = 1001,
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TriCore_ST_H_sro = 1002,
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TriCore_ST_H_ssr = 1003,
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TriCore_ST_H_ssr_pos = 1004,
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TriCore_ST_H_ssro = 1005,
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TriCore_ST_Q_abs = 1006,
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TriCore_ST_Q_bo_bso = 1007,
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TriCore_ST_Q_bo_c = 1008,
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TriCore_ST_Q_bo_pos = 1009,
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TriCore_ST_Q_bo_pre = 1010,
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TriCore_ST_Q_bo_r = 1011,
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TriCore_ST_T = 1012,
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TriCore_ST_W_abs = 1013,
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TriCore_ST_W_bo_bso = 1014,
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TriCore_ST_W_bo_c = 1015,
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TriCore_ST_W_bo_pos = 1016,
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TriCore_ST_W_bo_pre = 1017,
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TriCore_ST_W_bo_r = 1018,
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TriCore_ST_W_bol = 1019,
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TriCore_ST_W_sro = 1020,
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TriCore_ST_W_ssr = 1021,
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TriCore_ST_W_ssr_pos = 1022,
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TriCore_ST_W_ssro = 1023,
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TriCore_SUBC_rr = 1024,
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TriCore_SUBS_HU_rr = 1025,
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TriCore_SUBS_H_rr = 1026,
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TriCore_SUBS_U_rr = 1027,
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TriCore_SUBS_rr = 1028,
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TriCore_SUBS_srr = 1029,
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TriCore_SUBX_rr = 1030,
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TriCore_SUB_A_rr = 1031,
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TriCore_SUB_A_sc = 1032,
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TriCore_SUB_B_rr = 1033,
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TriCore_SUB_F_rrr = 1034,
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TriCore_SUB_H_rr = 1035,
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TriCore_SUB_rr = 1036,
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TriCore_SUB_srr = 1037,
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TriCore_SUB_srr_15a = 1038,
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TriCore_SUB_srr_a15 = 1039,
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TriCore_SVLCX_sys = 1040,
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TriCore_SWAPMSK_W_bo_bso = 1041,
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TriCore_SWAPMSK_W_bo_c = 1042,
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TriCore_SWAPMSK_W_bo_pos = 1043,
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TriCore_SWAPMSK_W_bo_pre = 1044,
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TriCore_SWAPMSK_W_bo_r = 1045,
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TriCore_SWAP_W_abs = 1046,
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TriCore_SWAP_W_bo_bso = 1047,
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TriCore_SWAP_W_bo_c = 1048,
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TriCore_SWAP_W_bo_pos = 1049,
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TriCore_SWAP_W_bo_pre = 1050,
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TriCore_SWAP_W_bo_r = 1051,
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TriCore_SYSCALL_rc = 1052,
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TriCore_TRAPSV_sys = 1053,
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TriCore_TRAPV_sys = 1054,
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TriCore_UNPACK_rr = 1055,
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TriCore_UPDFL_rr = 1056,
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TriCore_UTOF_rr = 1057,
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TriCore_WAIT_sys = 1058,
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TriCore_XNOR_T = 1059,
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TriCore_XNOR_rc = 1060,
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TriCore_XNOR_rr = 1061,
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TriCore_XOR_EQ_rc = 1062,
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TriCore_XOR_EQ_rr = 1063,
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TriCore_XOR_GE_U_rc = 1064,
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TriCore_XOR_GE_U_rr = 1065,
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TriCore_XOR_GE_rc = 1066,
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TriCore_XOR_GE_rr = 1067,
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TriCore_XOR_LT_U_rc = 1068,
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TriCore_XOR_LT_U_rr = 1069,
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TriCore_XOR_LT_rc = 1070,
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TriCore_XOR_LT_rr = 1071,
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TriCore_XOR_NE_rc = 1072,
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TriCore_XOR_NE_rr = 1073,
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TriCore_XOR_T = 1074,
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TriCore_XOR_rc = 1075,
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TriCore_XOR_rr = 1076,
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TriCore_XOR_srr = 1077,
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INSTRUCTION_LIST_END = 1078
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TriCore_MTCR_rlc = 823,
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TriCore_MULM_H_rr1_LL2e = 824,
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TriCore_MULM_H_rr1_LU2e = 825,
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TriCore_MULM_H_rr1_UL2e = 826,
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TriCore_MULM_H_rr1_UU2e = 827,
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TriCore_MULR_H_rr1_LL2e = 828,
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TriCore_MULR_H_rr1_LU2e = 829,
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TriCore_MULR_H_rr1_UL2e = 830,
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TriCore_MULR_H_rr1_UU2e = 831,
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TriCore_MULR_Q_rr1_2LL = 832,
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TriCore_MULR_Q_rr1_2UU = 833,
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TriCore_MULS_U_rc = 834,
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TriCore_MULS_U_rr2 = 835,
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TriCore_MULS_rc = 836,
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TriCore_MULS_rr2 = 837,
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TriCore_MUL_F_rrr = 838,
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TriCore_MUL_H_rr1_LL2e = 839,
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TriCore_MUL_H_rr1_LU2e = 840,
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TriCore_MUL_H_rr1_UL2e = 841,
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TriCore_MUL_H_rr1_UU2e = 842,
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TriCore_MUL_Q_rr1_2LL = 843,
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TriCore_MUL_Q_rr1_2UU = 844,
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TriCore_MUL_Q_rr1_2_L = 845,
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TriCore_MUL_Q_rr1_2_Le = 846,
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TriCore_MUL_Q_rr1_2_U = 847,
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TriCore_MUL_Q_rr1_2_Ue = 848,
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TriCore_MUL_Q_rr1_2__ = 849,
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TriCore_MUL_Q_rr1_2__e = 850,
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TriCore_MUL_U_rc = 851,
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TriCore_MUL_U_rr2 = 852,
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TriCore_MUL_rc = 853,
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TriCore_MUL_rc_e = 854,
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TriCore_MUL_rr2 = 855,
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TriCore_MUL_rr2_e = 856,
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TriCore_MUL_srr = 857,
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TriCore_NAND_T = 858,
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TriCore_NAND_rc = 859,
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TriCore_NAND_rr = 860,
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TriCore_NEZ_A = 861,
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TriCore_NE_A = 862,
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TriCore_NE_rc = 863,
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TriCore_NE_rr = 864,
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TriCore_NOP_sr = 865,
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TriCore_NOP_sys = 866,
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TriCore_NOR_T = 867,
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TriCore_NOR_rc = 868,
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TriCore_NOR_rr = 869,
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TriCore_NOT_sr = 870,
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TriCore_ORN_T = 871,
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TriCore_ORN_rc = 872,
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TriCore_ORN_rr = 873,
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TriCore_OR_ANDN_T = 874,
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TriCore_OR_AND_T = 875,
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TriCore_OR_EQ_rc = 876,
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TriCore_OR_EQ_rr = 877,
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TriCore_OR_GE_U_rc = 878,
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TriCore_OR_GE_U_rr = 879,
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TriCore_OR_GE_rc = 880,
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TriCore_OR_GE_rr = 881,
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TriCore_OR_LT_U_rc = 882,
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TriCore_OR_LT_U_rr = 883,
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TriCore_OR_LT_rc = 884,
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TriCore_OR_LT_rr = 885,
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TriCore_OR_NE_rc = 886,
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TriCore_OR_NE_rr = 887,
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TriCore_OR_NOR_T = 888,
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TriCore_OR_OR_T = 889,
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TriCore_OR_T = 890,
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TriCore_OR_rc = 891,
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TriCore_OR_rr = 892,
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TriCore_OR_sc = 893,
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TriCore_OR_srr = 894,
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TriCore_PACK_rrr = 895,
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TriCore_PARITY_rr = 896,
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TriCore_POPCNT_W_rr = 897,
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TriCore_Q31TOF_rr = 898,
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TriCore_QSEED_F_rr = 899,
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TriCore_RESTORE_sys = 900,
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TriCore_RET_sr = 901,
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TriCore_RET_sys = 902,
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TriCore_RFE_sr = 903,
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TriCore_RFE_sys = 904,
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TriCore_RFM_sys = 905,
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TriCore_RSLCX_sys = 906,
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TriCore_RSTV_sys = 907,
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TriCore_RSUBS_U_rc = 908,
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TriCore_RSUBS_rc = 909,
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TriCore_RSUB_rc = 910,
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TriCore_RSUB_sr = 911,
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TriCore_SAT_BU_rr = 912,
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TriCore_SAT_BU_sr = 913,
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TriCore_SAT_B_rr = 914,
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TriCore_SAT_B_sr = 915,
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TriCore_SAT_HU_rr = 916,
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TriCore_SAT_HU_sr = 917,
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TriCore_SAT_H_rr = 918,
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TriCore_SAT_H_sr = 919,
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TriCore_SELN_rcr = 920,
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TriCore_SELN_rrr = 921,
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TriCore_SEL_rcr = 922,
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TriCore_SEL_rrr = 923,
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TriCore_SHAS_rc = 924,
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TriCore_SHAS_rr = 925,
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TriCore_SHA_H_rc = 926,
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TriCore_SHA_H_rr = 927,
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TriCore_SHA_rc = 928,
|
||||
TriCore_SHA_rr = 929,
|
||||
TriCore_SHA_src = 930,
|
||||
TriCore_SHUFFLE_rc = 931,
|
||||
TriCore_SH_ANDN_T = 932,
|
||||
TriCore_SH_AND_T = 933,
|
||||
TriCore_SH_EQ_rc = 934,
|
||||
TriCore_SH_EQ_rr = 935,
|
||||
TriCore_SH_GE_U_rc = 936,
|
||||
TriCore_SH_GE_U_rr = 937,
|
||||
TriCore_SH_GE_rc = 938,
|
||||
TriCore_SH_GE_rr = 939,
|
||||
TriCore_SH_H_rc = 940,
|
||||
TriCore_SH_H_rr = 941,
|
||||
TriCore_SH_LT_U_rc = 942,
|
||||
TriCore_SH_LT_U_rr = 943,
|
||||
TriCore_SH_LT_rc = 944,
|
||||
TriCore_SH_LT_rr = 945,
|
||||
TriCore_SH_NAND_T = 946,
|
||||
TriCore_SH_NE_rc = 947,
|
||||
TriCore_SH_NE_rr = 948,
|
||||
TriCore_SH_NOR_T = 949,
|
||||
TriCore_SH_ORN_T = 950,
|
||||
TriCore_SH_OR_T = 951,
|
||||
TriCore_SH_XNOR_T = 952,
|
||||
TriCore_SH_XOR_T = 953,
|
||||
TriCore_SH_rc = 954,
|
||||
TriCore_SH_rr = 955,
|
||||
TriCore_SH_src = 956,
|
||||
TriCore_STLCX_abs = 957,
|
||||
TriCore_STLCX_bo_bso = 958,
|
||||
TriCore_STUCX_abs = 959,
|
||||
TriCore_STUCX_bo_bso = 960,
|
||||
TriCore_ST_A_abs = 961,
|
||||
TriCore_ST_A_bo_bso = 962,
|
||||
TriCore_ST_A_bo_c = 963,
|
||||
TriCore_ST_A_bo_pos = 964,
|
||||
TriCore_ST_A_bo_pre = 965,
|
||||
TriCore_ST_A_bo_r = 966,
|
||||
TriCore_ST_A_bol = 967,
|
||||
TriCore_ST_A_sc = 968,
|
||||
TriCore_ST_A_sro = 969,
|
||||
TriCore_ST_A_ssr = 970,
|
||||
TriCore_ST_A_ssr_pos = 971,
|
||||
TriCore_ST_A_ssro = 972,
|
||||
TriCore_ST_B_abs = 973,
|
||||
TriCore_ST_B_bo_bso = 974,
|
||||
TriCore_ST_B_bo_c = 975,
|
||||
TriCore_ST_B_bo_pos = 976,
|
||||
TriCore_ST_B_bo_pre = 977,
|
||||
TriCore_ST_B_bo_r = 978,
|
||||
TriCore_ST_B_bol = 979,
|
||||
TriCore_ST_B_sro = 980,
|
||||
TriCore_ST_B_ssr = 981,
|
||||
TriCore_ST_B_ssr_pos = 982,
|
||||
TriCore_ST_B_ssro = 983,
|
||||
TriCore_ST_DA_abs = 984,
|
||||
TriCore_ST_DA_bo_bso = 985,
|
||||
TriCore_ST_DA_bo_c = 986,
|
||||
TriCore_ST_DA_bo_pos = 987,
|
||||
TriCore_ST_DA_bo_pre = 988,
|
||||
TriCore_ST_DA_bo_r = 989,
|
||||
TriCore_ST_D_abs = 990,
|
||||
TriCore_ST_D_bo_bso = 991,
|
||||
TriCore_ST_D_bo_c = 992,
|
||||
TriCore_ST_D_bo_pos = 993,
|
||||
TriCore_ST_D_bo_pre = 994,
|
||||
TriCore_ST_D_bo_r = 995,
|
||||
TriCore_ST_H_abs = 996,
|
||||
TriCore_ST_H_bo_bso = 997,
|
||||
TriCore_ST_H_bo_c = 998,
|
||||
TriCore_ST_H_bo_pos = 999,
|
||||
TriCore_ST_H_bo_pre = 1000,
|
||||
TriCore_ST_H_bo_r = 1001,
|
||||
TriCore_ST_H_bol = 1002,
|
||||
TriCore_ST_H_sro = 1003,
|
||||
TriCore_ST_H_ssr = 1004,
|
||||
TriCore_ST_H_ssr_pos = 1005,
|
||||
TriCore_ST_H_ssro = 1006,
|
||||
TriCore_ST_Q_abs = 1007,
|
||||
TriCore_ST_Q_bo_bso = 1008,
|
||||
TriCore_ST_Q_bo_c = 1009,
|
||||
TriCore_ST_Q_bo_pos = 1010,
|
||||
TriCore_ST_Q_bo_pre = 1011,
|
||||
TriCore_ST_Q_bo_r = 1012,
|
||||
TriCore_ST_T = 1013,
|
||||
TriCore_ST_W_abs = 1014,
|
||||
TriCore_ST_W_bo_bso = 1015,
|
||||
TriCore_ST_W_bo_c = 1016,
|
||||
TriCore_ST_W_bo_pos = 1017,
|
||||
TriCore_ST_W_bo_pre = 1018,
|
||||
TriCore_ST_W_bo_r = 1019,
|
||||
TriCore_ST_W_bol = 1020,
|
||||
TriCore_ST_W_sro = 1021,
|
||||
TriCore_ST_W_ssr = 1022,
|
||||
TriCore_ST_W_ssr_pos = 1023,
|
||||
TriCore_ST_W_ssro = 1024,
|
||||
TriCore_SUBC_rr = 1025,
|
||||
TriCore_SUBS_HU_rr = 1026,
|
||||
TriCore_SUBS_H_rr = 1027,
|
||||
TriCore_SUBS_U_rr = 1028,
|
||||
TriCore_SUBS_rr = 1029,
|
||||
TriCore_SUBS_srr = 1030,
|
||||
TriCore_SUBX_rr = 1031,
|
||||
TriCore_SUB_A_rr = 1032,
|
||||
TriCore_SUB_A_sc = 1033,
|
||||
TriCore_SUB_B_rr = 1034,
|
||||
TriCore_SUB_F_rrr = 1035,
|
||||
TriCore_SUB_H_rr = 1036,
|
||||
TriCore_SUB_rr = 1037,
|
||||
TriCore_SUB_srr = 1038,
|
||||
TriCore_SUB_srr_15a = 1039,
|
||||
TriCore_SUB_srr_a15 = 1040,
|
||||
TriCore_SVLCX_sys = 1041,
|
||||
TriCore_SWAPMSK_W_bo_bso = 1042,
|
||||
TriCore_SWAPMSK_W_bo_c = 1043,
|
||||
TriCore_SWAPMSK_W_bo_pos = 1044,
|
||||
TriCore_SWAPMSK_W_bo_pre = 1045,
|
||||
TriCore_SWAPMSK_W_bo_r = 1046,
|
||||
TriCore_SWAP_W_abs = 1047,
|
||||
TriCore_SWAP_W_bo_bso = 1048,
|
||||
TriCore_SWAP_W_bo_c = 1049,
|
||||
TriCore_SWAP_W_bo_pos = 1050,
|
||||
TriCore_SWAP_W_bo_pre = 1051,
|
||||
TriCore_SWAP_W_bo_r = 1052,
|
||||
TriCore_SYSCALL_rc = 1053,
|
||||
TriCore_TRAPSV_sys = 1054,
|
||||
TriCore_TRAPV_sys = 1055,
|
||||
TriCore_UNPACK_rr = 1056,
|
||||
TriCore_UPDFL_rr = 1057,
|
||||
TriCore_UTOF_rr = 1058,
|
||||
TriCore_WAIT_sys = 1059,
|
||||
TriCore_XNOR_T = 1060,
|
||||
TriCore_XNOR_rc = 1061,
|
||||
TriCore_XNOR_rr = 1062,
|
||||
TriCore_XOR_EQ_rc = 1063,
|
||||
TriCore_XOR_EQ_rr = 1064,
|
||||
TriCore_XOR_GE_U_rc = 1065,
|
||||
TriCore_XOR_GE_U_rr = 1066,
|
||||
TriCore_XOR_GE_rc = 1067,
|
||||
TriCore_XOR_GE_rr = 1068,
|
||||
TriCore_XOR_LT_U_rc = 1069,
|
||||
TriCore_XOR_LT_U_rr = 1070,
|
||||
TriCore_XOR_LT_rc = 1071,
|
||||
TriCore_XOR_LT_rr = 1072,
|
||||
TriCore_XOR_NE_rc = 1073,
|
||||
TriCore_XOR_NE_rr = 1074,
|
||||
TriCore_XOR_T = 1075,
|
||||
TriCore_XOR_rc = 1076,
|
||||
TriCore_XOR_rr = 1077,
|
||||
TriCore_XOR_srr = 1078,
|
||||
INSTRUCTION_LIST_END = 1079
|
||||
};
|
||||
|
||||
#endif // GET_INSTRINFO_ENUM
|
||||
@ -1200,17 +1201,18 @@ static const MCOperandInfo OperandInfo103[] = { { TriCore_ExtRegsRegClassID, 0,
|
||||
static const MCOperandInfo OperandInfo104[] = { { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo105[] = { { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo106[] = { { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo107[] = { { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo108[] = { { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo109[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo110[] = { { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo111[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo112[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo113[] = { { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo114[] = { { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo115[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo116[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo117[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo107[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo108[] = { { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo109[] = { { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo110[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo111[] = { { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo112[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo113[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo114[] = { { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo115[] = { { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo116[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo117[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo118[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
|
||||
static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 1, OperandInfo2 },
|
||||
@ -1919,7 +1921,7 @@ static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 3, OperandInfo45 },
|
||||
{ 3, OperandInfo46 },
|
||||
{ 3, OperandInfo45 },
|
||||
{ 3, OperandInfo46 },
|
||||
{ 2, OperandInfo53 },
|
||||
{ 3, OperandInfo45 },
|
||||
{ 3, OperandInfo45 },
|
||||
{ 3, OperandInfo45 },
|
||||
@ -2036,37 +2038,38 @@ static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 4, OperandInfo103 },
|
||||
{ 4, OperandInfo59 },
|
||||
{ 4, OperandInfo104 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 2, OperandInfo107 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo58 },
|
||||
{ 4, OperandInfo58 },
|
||||
{ 3, OperandInfo108 },
|
||||
{ 3, OperandInfo109 },
|
||||
{ 3, OperandInfo66 },
|
||||
{ 3, OperandInfo46 },
|
||||
{ 3, OperandInfo45 },
|
||||
{ 3, OperandInfo45 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo58 },
|
||||
{ 4, OperandInfo58 },
|
||||
{ 4, OperandInfo58 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo58 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 4, OperandInfo58 },
|
||||
{ 4, OperandInfo107 },
|
||||
{ 3, OperandInfo108 },
|
||||
{ 4, OperandInfo108 },
|
||||
{ 3, OperandInfo109 },
|
||||
{ 3, OperandInfo66 },
|
||||
{ 3, OperandInfo46 },
|
||||
{ 3, OperandInfo108 },
|
||||
{ 3, OperandInfo109 },
|
||||
{ 3, OperandInfo45 },
|
||||
{ 3, OperandInfo66 },
|
||||
{ 2, OperandInfo47 },
|
||||
@ -2178,7 +2181,7 @@ static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 3, OperandInfo62 },
|
||||
{ 3, OperandInfo49 },
|
||||
{ 3, OperandInfo49 },
|
||||
{ 2, OperandInfo109 },
|
||||
{ 2, OperandInfo110 },
|
||||
{ 3, OperandInfo81 },
|
||||
{ 1, OperandInfo2 },
|
||||
{ 2, OperandInfo51 },
|
||||
@ -2186,12 +2189,12 @@ static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 2, OperandInfo52 },
|
||||
{ 2, OperandInfo51 },
|
||||
{ 2, OperandInfo89 },
|
||||
{ 3, OperandInfo110 },
|
||||
{ 3, OperandInfo111 },
|
||||
{ 3, OperandInfo112 },
|
||||
{ 3, OperandInfo90 },
|
||||
{ 3, OperandInfo90 },
|
||||
{ 2, OperandInfo112 },
|
||||
{ 3, OperandInfo113 },
|
||||
{ 2, OperandInfo113 },
|
||||
{ 3, OperandInfo114 },
|
||||
{ 2, OperandInfo51 },
|
||||
{ 2, OperandInfo52 },
|
||||
{ 2, OperandInfo52 },
|
||||
@ -2203,36 +2206,36 @@ static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 3, OperandInfo62 },
|
||||
{ 2, OperandInfo96 },
|
||||
{ 2, OperandInfo85 },
|
||||
{ 3, OperandInfo114 },
|
||||
{ 3, OperandInfo115 },
|
||||
{ 3, OperandInfo116 },
|
||||
{ 3, OperandInfo97 },
|
||||
{ 3, OperandInfo97 },
|
||||
{ 2, OperandInfo116 },
|
||||
{ 2, OperandInfo117 },
|
||||
{ 2, OperandInfo89 },
|
||||
{ 3, OperandInfo110 },
|
||||
{ 3, OperandInfo111 },
|
||||
{ 3, OperandInfo112 },
|
||||
{ 3, OperandInfo90 },
|
||||
{ 3, OperandInfo90 },
|
||||
{ 2, OperandInfo112 },
|
||||
{ 3, OperandInfo113 },
|
||||
{ 2, OperandInfo113 },
|
||||
{ 3, OperandInfo114 },
|
||||
{ 2, OperandInfo51 },
|
||||
{ 2, OperandInfo52 },
|
||||
{ 2, OperandInfo52 },
|
||||
{ 2, OperandInfo51 },
|
||||
{ 2, OperandInfo89 },
|
||||
{ 3, OperandInfo110 },
|
||||
{ 3, OperandInfo111 },
|
||||
{ 3, OperandInfo112 },
|
||||
{ 3, OperandInfo90 },
|
||||
{ 3, OperandInfo90 },
|
||||
{ 2, OperandInfo112 },
|
||||
{ 3, OperandInfo117 },
|
||||
{ 2, OperandInfo113 },
|
||||
{ 3, OperandInfo118 },
|
||||
{ 2, OperandInfo89 },
|
||||
{ 3, OperandInfo110 },
|
||||
{ 3, OperandInfo111 },
|
||||
{ 3, OperandInfo112 },
|
||||
{ 3, OperandInfo90 },
|
||||
{ 3, OperandInfo90 },
|
||||
{ 2, OperandInfo112 },
|
||||
{ 3, OperandInfo113 },
|
||||
{ 2, OperandInfo113 },
|
||||
{ 3, OperandInfo114 },
|
||||
{ 2, OperandInfo53 },
|
||||
{ 2, OperandInfo105 },
|
||||
{ 2, OperandInfo105 },
|
||||
@ -2254,17 +2257,17 @@ static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 2, OperandInfo47 },
|
||||
{ 2, OperandInfo47 },
|
||||
{ 0, 0 },
|
||||
{ 3, OperandInfo114 },
|
||||
{ 3, OperandInfo115 },
|
||||
{ 3, OperandInfo116 },
|
||||
{ 3, OperandInfo97 },
|
||||
{ 3, OperandInfo97 },
|
||||
{ 2, OperandInfo116 },
|
||||
{ 2, OperandInfo117 },
|
||||
{ 2, OperandInfo89 },
|
||||
{ 3, OperandInfo110 },
|
||||
{ 3, OperandInfo111 },
|
||||
{ 3, OperandInfo112 },
|
||||
{ 3, OperandInfo90 },
|
||||
{ 3, OperandInfo90 },
|
||||
{ 2, OperandInfo112 },
|
||||
{ 2, OperandInfo113 },
|
||||
{ 1, OperandInfo2 },
|
||||
{ 0, 0 },
|
||||
{ 0, 0 },
|
||||
|
||||
@ -1357,8 +1357,6 @@ defm MAX_U : mIRR_RC<0x0B, 0x1B, 0x8B, 0x1B, "max.u">;
|
||||
defm MAX_B : mIU__RR_ab<0x0B, 0x5A, 0x0B, 0x5B, "max.b">;
|
||||
defm MAX_H : mIU__RR_ab<0x0B, 0x7A, 0x0B, 0x7B, "max.h">;
|
||||
|
||||
def MFCR_rlc : IRLC<0x4D, "mfcr">;
|
||||
|
||||
defm MIN : mIRR_RC<0x0B, 0x18, 0x8B, 0x18, "min">;
|
||||
defm MIN_U : mIRR_RC<0x0B, 0x19, 0x8B, 0x19, "min.u">;
|
||||
|
||||
@ -1441,9 +1439,8 @@ class IRLC_CR<bits<8> op1, string asmstr, RegisterClass rc>
|
||||
: RLC<op1, (outs), (ins s16imm:$const16, rc:$d),
|
||||
asmstr # " $const16, $d", []>;
|
||||
|
||||
// TODO: CSFR
|
||||
// def MTCR_rlc : IRLC_CR<0xCD, "mtcr", CRRegs>;
|
||||
|
||||
def MTCR_rlc : IRLC_CR<0xCD, "mtcr", DataRegs>;
|
||||
def MFCR_rlc : IRLC_1 <0x4D, "mfcr", DataRegs>;
|
||||
|
||||
class IRR2<bits<8> op1, bits<12> op2, string asmstr, RegisterClass rcd, RegisterClass rca, RegisterClass rcb>
|
||||
: RR2<op1, op2, (outs rcd:$d), (ins rca:$s1, rcb:$s2), asmstr # " $d, $s1, $s2", []>;
|
||||
|
||||
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Reference in New Issue
Block a user