add new API cs_group_name() to return group name in string, given the group id

arch/AArch64/AArch64Mapping.c

@@ -17034,6 +17034,29 @@ const char *AArch64_insn_name(csh handle, unsigned int id)
 #endif
 }
 
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+	{ ARM64_GRP_INVALID, NULL },
+	{ ARM64_GRP_CRYPTO, "crypto" },
+	{ ARM64_GRP_FPARMV8, "fparmv8" },
+	{ ARM64_GRP_NEON, "neon" },
+
+	{ ARM64_GRP_JUMP, "jump" },
+};
+#endif
+
+const char *AArch64_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= ARM64_GRP_MAX)
+		return NULL;
+
+	return group_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
 // map instruction name to public instruction ID
 arm64_reg AArch64_map_insn(const char *name)
 {

arch/AArch64/AArch64Mapping.h

@@ -14,6 +14,8 @@ void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
 
 const char *AArch64_insn_name(csh handle, unsigned int id);
 
+const char *AArch64_group_name(csh handle, unsigned int id);
+
 // map instruction name to public instruction ID
 arm64_reg AArch64_map_insn(const char *name);
 

arch/AArch64/AArch64Module.c

@@ -27,6 +27,7 @@ static cs_err init(cs_struct *ud)
 	ud->reg_name = AArch64_reg_name;
 	ud->insn_id = AArch64_get_insn_id;
 	ud->insn_name = AArch64_insn_name;
+	ud->group_name = AArch64_group_name;
 	ud->post_printer = AArch64_post_printer;
 
 	return CS_ERR_OK;

arch/ARM/ARMMapping.c

@@ -13888,6 +13888,57 @@ const char *ARM_insn_name(csh handle, unsigned int id)
 #endif
 }
 
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+	{ ARM_GRP_INVALID, NULL },
+	{ ARM_GRP_CRYPTO, "crypto" },
+	{ ARM_GRP_DATABARRIER, "databarrier" },
+	{ ARM_GRP_DIVIDE, "divide" },
+	{ ARM_GRP_FPARMV8, "fparmv8" },
+	{ ARM_GRP_MULTPRO, "multpro" },
+	{ ARM_GRP_NEON, "neon" },
+	{ ARM_GRP_T2EXTRACTPACK, "T2EXTRACTPACK" },
+	{ ARM_GRP_THUMB2DSP, "THUMB2DSP" },
+	{ ARM_GRP_TRUSTZONE, "TRUSTZONE" },
+	{ ARM_GRP_V4T, "v4t" },
+	{ ARM_GRP_V5T, "v5t" },
+	{ ARM_GRP_V5TE, "v5te" },
+	{ ARM_GRP_V6, "v6" },
+	{ ARM_GRP_V6T2, "v6t2" },
+	{ ARM_GRP_V7, "v7" },
+	{ ARM_GRP_V8, "v8" },
+	{ ARM_GRP_VFP2, "vfp2" },
+	{ ARM_GRP_VFP3, "vfp3" },
+	{ ARM_GRP_VFP4, "vfp4" },
+	{ ARM_GRP_ARM, "arm" },
+	{ ARM_GRP_MCLASS, "mclass" },
+	{ ARM_GRP_NOTMCLASS, "notmclass" },
+	{ ARM_GRP_THUMB, "thumb" },
+	{ ARM_GRP_THUMB1ONLY, "thumb1only" },
+	{ ARM_GRP_THUMB2, "thumb2" },
+	{ ARM_GRP_PREV8, "prev8" },
+	{ ARM_GRP_FPVMLX, "fpvmlx" },
+	{ ARM_GRP_MULOPS, "mulops" },
+	{ ARM_GRP_CRC, "crc" },
+	{ ARM_GRP_DPVFP, "dpvfp" },
+	{ ARM_GRP_V6M, "v6m" },
+
+	{ ARM_GRP_JUMP,	"jump" }
+};
+#endif
+
+const char *ARM_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= ARM_GRP_MAX)
+		return NULL;
+
+	return group_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
 // list all relative branch instructions
 // ie: insns[i].branch && !insns[i].indirect_branch
 static unsigned int insn_rel[] = {

arch/ARM/ARMMapping.h

@@ -15,6 +15,8 @@ void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
 
 const char *ARM_insn_name(csh handle, unsigned int id);
 
+const char *ARM_group_name(csh handle, unsigned int id);
+
 // check if this insn is relative branch
 bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
 

arch/ARM/ARMModule.c

@@ -28,6 +28,7 @@ static cs_err init(cs_struct *ud)
 	ud->reg_name = ARM_reg_name;
 	ud->insn_id = ARM_get_insn_id;
 	ud->insn_name = ARM_insn_name;
+	ud->group_name = ARM_group_name;
 	ud->post_printer = ARM_post_printer;
 
 	if (ud->mode & CS_MODE_THUMB)

arch/Mips/MipsMapping.c

@@ -8422,6 +8422,44 @@ const char *Mips_insn_name(csh handle, unsigned int id)
 #endif
 }
 
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+	{ MIPS_GRP_INVALID, NULL },
+	{ MIPS_GRP_BITCOUNT, "bitcount" },
+	{ MIPS_GRP_DSP, "dsp" },
+	{ MIPS_GRP_DSPR2, "dspr2" },
+	{ MIPS_GRP_FPIDX, "fpidx" },
+	{ MIPS_GRP_MSA, "msa" },
+	{ MIPS_GRP_MIPS32R2, "mips32r2" },
+	{ MIPS_GRP_MIPS64, "mips64" },
+	{ MIPS_GRP_MIPS64R2, "mips64r2" },
+	{ MIPS_GRP_SEINREG, "seinreg" },
+	{ MIPS_GRP_STDENC, "stdenc" },
+	{ MIPS_GRP_SWAP, "swap" },
+	{ MIPS_GRP_MICROMIPS, "micromips" },
+	{ MIPS_GRP_MIPS16MODE, "mips16mode" },
+	{ MIPS_GRP_FP64BIT, "fp64bit" },
+	{ MIPS_GRP_NONANSFPMATH, "nonansfpmath" },
+	{ MIPS_GRP_NOTFP64BIT, "notfp64bit" },
+	{ MIPS_GRP_NOTINMICROMIPS, "notinmicromips" },
+	{ MIPS_GRP_NOTNACL, "notnacl" },
+
+	{ MIPS_GRP_JUMP, "jump" }
+};
+#endif
+
+const char *Mips_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= MIPS_GRP_MAX)
+		return NULL;
+
+	return group_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
 mips_reg Mips_map_insn(const char *name)
 {
 	// handle special alias first

arch/Mips/MipsMapping.h

@@ -12,9 +12,10 @@ const char *Mips_reg_name(csh handle, unsigned int reg);
 // given internal insn id, return public instruction info
 void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
 
-// given public insn id, return internal insn id
 const char *Mips_insn_name(csh handle, unsigned int id);
 
+const char *Mips_group_name(csh handle, unsigned int id);
+
 // map instruction name to instruction ID
 mips_reg Mips_map_insn(const char *name);
 

arch/Mips/MipsModule.c

@@ -27,6 +27,7 @@ static cs_err init(cs_struct *ud)
 	ud->reg_name = Mips_reg_name;
 	ud->insn_id = Mips_get_insn_id;
 	ud->insn_name = Mips_insn_name;
+	ud->group_name = Mips_group_name;
 
 	if (ud->mode & CS_MODE_32)
 		ud->disasm = Mips_getInstruction;

arch/PowerPC/PPCMapping.c

@@ -5177,6 +5177,31 @@ const char *PPC_insn_name(csh handle, unsigned int id)
 #endif
 }
 
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+	{ PPC_GRP_INVALID, NULL },
+	{ PPC_GRP_ALTIVEC, "altivec" },
+	{ PPC_GRP_MODE32, "mode32" },
+	{ PPC_GRP_MODE64, "mode64" },
+	{ PPC_GRP_BOOKE, "booke" },
+	{ PPC_GRP_NOTBOOKE, "notbooke" },
+
+	{ PPC_GRP_JUMP,	"jump" },
+};
+#endif
+
+const char *PPC_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= PPC_GRP_MAX)
+		return NULL;
+
+	return group_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
 // map internal raw register to 'public' register
 ppc_reg PPC_map_register(unsigned int r)
 {

arch/PowerPC/PPCMapping.h

@@ -13,6 +13,7 @@ const char *PPC_reg_name(csh handle, unsigned int reg);
 void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
 
 const char *PPC_insn_name(csh handle, unsigned int id);
+const char *PPC_group_name(csh handle, unsigned int id);
 
 // map internal raw register to 'public' register
 ppc_reg PPC_map_register(unsigned int r);

arch/PowerPC/PPCModule.c

@@ -30,6 +30,7 @@ static cs_err init(cs_struct *ud)
 	ud->reg_name = PPC_reg_name;
 	ud->insn_id = PPC_get_insn_id;
 	ud->insn_name = PPC_insn_name;
+	ud->group_name = PPC_group_name;
 
 	return CS_ERR_OK;
 }

arch/Sparc/SparcMapping.c

@@ -3140,6 +3140,33 @@ const char *Sparc_insn_name(csh handle, unsigned int id)
 #endif
 }
 
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+	{ SPARC_GRP_INVALID, NULL },
+	{ SPARC_GRP_HARDQUAD, "hardquad" },
+	{ SPARC_GRP_V9, "v9" },
+	{ SPARC_GRP_VIS, "vis" },
+	{ SPARC_GRP_VIS2, "vis2" },
+	{ SPARC_GRP_VIS3,  "vis3" },
+	{ SPARC_GRP_32BIT, "32bit" },
+	{ SPARC_GRP_64BIT, "64bit" },
+
+	{ SPARC_GRP_JUMP, "jump" },
+};
+#endif
+
+const char *Sparc_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= SPARC_GRP_MAX)
+		return NULL;
+
+	return group_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
 // map internal raw register to 'public' register
 sparc_reg Sparc_map_register(unsigned int r)
 {

arch/Sparc/SparcMapping.h

@@ -14,6 +14,8 @@ void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
 
 const char *Sparc_insn_name(csh handle, unsigned int id);
 
+const char *Sparc_group_name(csh handle, unsigned int id);
+
 // map internal raw register to 'public' register
 sparc_reg Sparc_map_register(unsigned int r);
 

arch/Sparc/SparcModule.c

@@ -29,6 +29,7 @@ static cs_err init(cs_struct *ud)
 	ud->reg_name = Sparc_reg_name;
 	ud->insn_id = Sparc_get_insn_id;
 	ud->insn_name = Sparc_insn_name;
+	ud->group_name = Sparc_group_name;
 
 	return CS_ERR_OK;
 }

arch/SystemZ/SystemZMapping.h

@@ -14,6 +14,8 @@ void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
 
 const char *SystemZ_insn_name(csh handle, unsigned int id);
 
+const char *SystemZ_group_name(csh handle, unsigned int id);
+
 // map internal raw register to 'public' register
 sysz_reg SystemZ_map_register(unsigned int r);
 

arch/SystemZ/SystemZModule.c

@@ -25,6 +25,7 @@ static cs_err init(cs_struct *ud)
 	ud->reg_name = SystemZ_reg_name;
 	ud->insn_id = SystemZ_get_insn_id;
 	ud->insn_name = SystemZ_insn_name;
+	ud->group_name = SystemZ_group_name;
 
 	return CS_ERR_OK;
 }

arch/X86/X86Mapping.c

@@ -2086,6 +2086,64 @@ const char *X86_insn_name(csh handle, unsigned int id)
 #endif
 }
 
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+	{ X86_GRP_INVALID, NULL },
+	{ X86_GRP_3DNOW, "3dnow" },
+	{ X86_GRP_AES, "aes" },
+	{ X86_GRP_ADX, "adx" },
+	{ X86_GRP_AVX, "avx" },
+	{ X86_GRP_AVX2, "avx2" },
+	{ X86_GRP_AVX512, "avx512" },
+	{ X86_GRP_BMI, "bmi" },
+	{ X86_GRP_BMI2, "bmi2" },
+	{ X86_GRP_CMOV, "cmov" },
+	{ X86_GRP_F16C, "fc16" },
+	{ X86_GRP_FMA, "fma" },
+	{ X86_GRP_FMA4, "fma4" },
+	{ X86_GRP_FSGSBASE, "fsgsbase" },
+	{ X86_GRP_HLE, "hle" },
+	{ X86_GRP_MMX, "mmx" },
+	{ X86_GRP_MODE32, "mode32" },
+	{ X86_GRP_MODE64, "mode64" },
+	{ X86_GRP_RTM, "rtm" },
+	{ X86_GRP_SHA, "sha" },
+	{ X86_GRP_SSE1, "sse1" },
+	{ X86_GRP_SSE2, "sse2" },
+	{ X86_GRP_SSE3, "sse3" },
+	{ X86_GRP_SSE41, "sse41" },
+	{ X86_GRP_SSE42, "sse42" },
+	{ X86_GRP_SSE4A, "sse4a" },
+	{ X86_GRP_SSSE3, "ssse3" },
+	{ X86_GRP_PCLMUL, "pclmul" },
+	{ X86_GRP_XOP, "xop" },
+	{ X86_GRP_CDI, "cdi" },
+	{ X86_GRP_ERI, "eri" },
+	{ X86_GRP_TBM, "tbm" },
+	{ X86_GRP_16BITMODE, "16bitmode" },
+	{ X86_GRP_NOT64BITMODE, "not64bitmode" },
+
+	{ X86_GRP_JUMP,	"jump" },
+	{ X86_GRP_VM, "vm" },
+	{ X86_GRP_INT, "int" },
+	{ X86_GRP_IRET,	"iret" },
+	{ X86_GRP_CALL,	"call" },
+	{ X86_GRP_RET, "ret" },
+};
+#endif
+
+const char *X86_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= X86_GRP_MAX)
+		return NULL;
+
+	return group_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
 #define GET_INSTRINFO_ENUM
 #ifdef CAPSTONE_X86_REDUCE
 #include "X86GenInstrInfo_reduce.inc"

arch/X86/X86Mapping.h

@@ -25,6 +25,9 @@ void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
 // return insn name, given insn id
 const char *X86_insn_name(csh handle, unsigned int id);
 
+// return group name, given group id
+const char *X86_group_name(csh handle, unsigned int id);
+
 // post printer for X86.
 void X86_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, MCInst *mci);
 

arch/X86/X86Module.c

@@ -23,6 +23,7 @@ static cs_err init(cs_struct *ud)
 	ud->reg_name = X86_reg_name;
 	ud->insn_id = X86_get_insn_id;
 	ud->insn_name = X86_insn_name;
+	ud->group_name = X86_group_name;
 	ud->post_printer = X86_post_printer;
 
 	if (ud->mode == CS_MODE_64)

arch/XCore/XCoreMapping.c

@@ -1548,6 +1548,23 @@ const char *XCore_insn_name(csh handle, unsigned int id)
 #endif
 }
 
+static name_map group_name_maps[] = {
+	{ XCORE_GRP_INVALID, NULL },
+	{ XCORE_GRP_JUMP, "jump" },
+};
+
+const char *XCore_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= XCORE_GRP_MAX)
+		return NULL;
+
+	return group_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
 // map internal raw register to 'public' register
 xcore_reg XCore_map_register(unsigned int r)
 {

arch/XCore/XCoreMapping.h

@@ -14,6 +14,8 @@ void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
 
 const char *XCore_insn_name(csh handle, unsigned int id);
 
+const char *XCore_group_name(csh handle, unsigned int id);
+
 // map internal raw register to 'public' register
 xcore_reg XCore_map_register(unsigned int r);
 

arch/XCore/XCoreModule.c

@@ -25,6 +25,7 @@ static cs_err init(cs_struct *ud)
 	ud->reg_name = XCore_reg_name;
 	ud->insn_id = XCore_get_insn_id;
 	ud->insn_name = XCore_insn_name;
+	ud->group_name = XCore_group_name;
 
 	return CS_ERR_OK;
 }

cs.c

@@ -635,6 +635,18 @@ const char *cs_insn_name(csh ud, unsigned int insn)
 	return handle->insn_name(ud, insn);
 }
 
+CAPSTONE_EXPORT
+const char *cs_group_name(csh ud, unsigned int group)
+{
+	struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
+
+	if (!handle || handle->group_name == NULL) {
+		return NULL;
+	}
+
+	return handle->group_name(ud, group);
+}
+
 static bool arr_exist(unsigned char *arr, unsigned char max, unsigned int id)
 {
 	int i;

cs_priv.h

@@ -17,7 +17,7 @@ typedef void (*PostPrinter_t)(csh handle, cs_insn *, char *mnem, MCInst *mci);
 
 typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
 
-typedef const char *(*GetName_t)(csh handle, unsigned int reg);
+typedef const char *(*GetName_t)(csh handle, unsigned int id);
 
 typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id);
 
@@ -40,6 +40,7 @@ struct cs_struct {
 	bool big_endian;
 	GetName_t reg_name;
 	GetName_t insn_name;
+	GetName_t group_name;
 	GetID_t insn_id;
 	PostPrinter_t post_printer;
 	cs_err errnum;

include/capstone.h

@@ -389,7 +389,7 @@ CAPSTONE_EXPORT
 void cs_free(cs_insn *insn, size_t count);
 
 /*
- Return friendly name of regiser in a string
+ Return friendly name of regiser in a string.
  Find the instruction id from header file of corresponding architecture (arm.h for ARM,
  x86.h for X86, ...)
 
@@ -397,27 +397,42 @@ void cs_free(cs_insn *insn, size_t count);
  store register name.
 
  @handle: handle returned by cs_open()
- @reg: register id
+ @reg_id: register id
  @return: string name of the register, or NULL if @reg_id is invalid.
 */
 CAPSTONE_EXPORT
 const char *cs_reg_name(csh handle, unsigned int reg_id);
 
 /*
- Return friendly name of an instruction in a string
+ Return friendly name of an instruction in a string.
  Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
 
  WARN: when in 'diet' mode, this API is irrelevant because the engine does not
  store instruction name.
 
  @handle: handle returned by cs_open()
- @insn: instruction id
+ @insn_id: instruction id
 
  @return: string name of the instruction, or NULL if @insn_id is invalid.
 */
 CAPSTONE_EXPORT
 const char *cs_insn_name(csh handle, unsigned int insn_id);
 
+/*
+ Return friendly name of a group id (that an instruction can belong to)
+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ store group name.
+
+ @handle: handle returned by cs_open()
+ @group_id: group id
+
+ @return: string name of the group, or NULL if @group_id is invalid.
+*/
+CAPSTONE_EXPORT
+const char *cs_group_name(csh handle, unsigned int insn_id);
+
 /*
  Check if a disassembled instruction belong to a particular group.
  Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)

include/systemz.h

@@ -803,11 +803,11 @@ typedef enum sysz_insn {
 //> Group of SystemZ instructions
 typedef enum sysz_insn_group {
 	SYSZ_GRP_INVALID = 0,
-	SYSZ_GRP_FEATUREDISTINCTOPS,
-	SYSZ_GRP_FEATUREFPEXTENSION,
-	SYSZ_GRP_FEATUREHIGHWORD,
-	SYSZ_GRP_FEATUREINTERLOCKEDACCESS1,
-	SYSZ_GRP_FEATURELOADSTOREONCOND,
+	SYSZ_GRP_DISTINCTOPS,
+	SYSZ_GRP_FPEXTENSION,
+	SYSZ_GRP_HIGHWORD,
+	SYSZ_GRP_INTERLOCKEDACCESS1,
+	SYSZ_GRP_LOADSTOREONCOND,
 
 	SYSZ_GRP_JUMP,	// all jump instructions (conditional+direct+indirect jumps)