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https://github.com/capstone-engine/capstone.git
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add cache inst
This commit is contained in:
billow
parent
69e051687a
commit
688ee6a07c
@ -175,6 +175,7 @@ def imm0_31 : PatLeaf<(imm),
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def s4imm : Operand<i32> { let PrintMethod = "printSExtImm<4>"; }
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def s6imm : Operand<i32> { let PrintMethod = "printSExtImm<6>"; }
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def s9imm : Operand<i32> { let PrintMethod = "printSExtImm<9>"; }
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def s10imm : Operand<i32> { let PrintMethod = "printSExtImm<10>"; }
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def s16imm : Operand<i32> { let PrintMethod = "printSExtImm<16>"; }
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def s24imm : Operand<i32> { let PrintMethod = "printSExtImm<24>"; }
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def u8imm : Operand<i32> { let PrintMethod = "printZExtImm<8>"; }
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@ -225,6 +226,7 @@ def bitrevbo : Operand<i32> {
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def immSExt4 : PatLeaf<(imm), [{ return isInt<4>(N->getSExtValue()); }]>;
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def immSExt6 : PatLeaf<(imm), [{ return isInt<6>(N->getSExtValue()); }]>;
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def immSExt9 : PatLeaf<(imm), [{ return isInt<9>(N->getSExtValue()); }]>;
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def immSExt10 : PatLeaf<(imm), [{ return isInt<10>(N->getSExtValue()); }]>;
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def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
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def immSExt24 : PatLeaf<(imm), [{ return isInt<24>(N->getSExtValue()); }]>;
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@ -241,8 +243,11 @@ def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
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class ISC<bits<8> op1, string asmstr>
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: SC<op1, (outs), (ins u8imm:$const8),
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asmstr # " %d15, $const8",
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[]>;
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asmstr # " %d15, $const8", []>;
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class IUnarySC<bits<8> op1, string asmstr>
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: SC<op1, (outs), (ins u8imm:$const8),
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asmstr # " $const8", []>;
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multiclass mISC_s<bits<8> op1, string asmstr> {
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def _src : ISC<op1, asmstr>;
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@ -282,23 +287,35 @@ class ISRRS<bits<6> op1, string asmstr>
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/// 32-Bit Opcode Formats
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class IRR<bits<8> op1, bits<8> op2, string asmstr>
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: RR<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1, DataRegs:$s2),
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asmstr # " $d, $s1, $s2", []>;
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/// RC
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class IRC<bits<8> op1, bits<7> op2, string asmstr>
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class IUnaryRC<bits<8> op1, bits<7> op2, string asmstr>
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: RC<op1, op2, (outs), (ins s9imm:$const9),
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asmstr # " $const9", []>;
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class IBinRC<bits<8> op1, bits<7> op2, string asmstr, SDNode node>
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: RC<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1, s9imm:$const9),
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asmstr # " $d, $s1, $const9",
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[(set DataRegs:$d, (node DataRegs:$s1, immSExt9:$const9))]>;
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class IBinRC_<bits<8> op1, bits<7> op2, string asmstr>
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: RC<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1, s9imm:$const9),
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asmstr # " $d, $s1, $const9", []>;
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/// RR
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class IUnaryRR_E<bits<8> op1, bits<8> op2, string asmstr>
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: RR<op1, op2, (outs ExtRegs:$d), (ins DataRegs:$s1),
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asmstr # " $d, $s1", []>;
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class IBinRR<bits<8> op1, bits<8> op2, string asmstr, SDNode node>
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: RR<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1, DataRegs:$s2),
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asmstr # " $d, $s1, $s2",
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[(set DataRegs:$d, (node DataRegs:$s1, DataRegs:$s2))]>;
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class IBinRC<bits<8> op1, bits<7> op2, string asmstr, SDNode node>
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: RC<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1, s9imm:$const9),
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asmstr # " $d, $s1, $const9",
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[(set DataRegs:$d, (node DataRegs:$s1, immSExt9:$const9))]>;
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class IBinRR_<bits<8> op1, bits<8> op2, string asmstr>
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: RR<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1, DataRegs:$s2),
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asmstr # " $d, $s1, $s2", []>;
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multiclass mIBinRR_RC<bits<8> rr1, bits<8> rr2, bits<8> rc1, bits<7> rc2,
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string asmstr, SDNode node> {
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@ -306,10 +323,10 @@ multiclass mIBinRR_RC<bits<8> rr1, bits<8> rr2, bits<8> rc1, bits<7> rc2,
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def _rc : IBinRC<rc1, rc2, asmstr, node>;
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}
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multiclass mIRR_RC<bits<8> rr1, bits<8> rr2, bits<8> rc1, bits<7> rc2,
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multiclass mIBinRR_RC_<bits<8> rr1, bits<8> rr2, bits<8> rc1, bits<7> rc2,
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string asmstr> {
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def _rr : IRR<rr1, rr2, asmstr>;
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def _rc : IRC<rc1, rc2, asmstr>;
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def _rr : IBinRR_<rr1, rr2, asmstr>;
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def _rc : IBinRC_<rc1, rc2, asmstr>;
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}
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class IRLC<bits<8> op1, string asmstr, SDNode node>
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@ -366,6 +383,8 @@ class IBIT<bits<8> op1, bits<2> op2, string asmstr>
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// Instructions
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions
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// Absolute Value Instructions
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let Defs = [PSW] in {
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def ABSrr : RR<0x0B, 0x1C, (outs DataRegs:$d),
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@ -425,7 +444,6 @@ multiclass mIB_H<bits<8> brr1, bits<8> brr2, bits<8> hrr1, bits<8> hrr2,
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def _H_rr : IBinRR<hrr1, hrr2, asmstr # ".h", node>;
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}
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// Arithmetic Instructions
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// - ADD Instructions
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defm ADD : mIBinRR_RC<0x0B, 0x00, 0x8B, 0x00, "add", add>,
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@ -477,15 +495,115 @@ def AND_OR_T : IBIT<0x47, 0x01, "and.or.t">;
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def AND_T : IBIT<0x87, 0x00, "and.t">;
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def ANDN_T : IBIT<0x87, 0x03, "andn.t">;
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defm AND_EQ : mIRR_RC<0x0B, 0x20, 0x8B, 0x20, "and.eq">;
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defm AND_GE : mIRR_RC<0x0B, 0x24, 0x8B, 0x24, "and.ge">;
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defm AND_GE_U : mIRR_RC<0x0B, 0x25, 0x8B, 0x25, "and.ge.u">;
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defm AND_LT : mIRR_RC<0x0B, 0x22, 0x8B, 0x22, "and.lt">;
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defm AND_LT_U : mIRR_RC<0x0B, 0x23, 0x8B, 0x23, "and.lt.u">;
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defm AND_NE : mIRR_RC<0x0B, 0x21, 0x8B, 0x21, "and.ne">;
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defm AND_EQ : mIBinRR_RC_<0x0B, 0x20, 0x8B, 0x20, "and.eq">;
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defm AND_GE : mIBinRR_RC_<0x0B, 0x24, 0x8B, 0x24, "and.ge">;
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defm AND_GE_U : mIBinRR_RC_<0x0B, 0x25, 0x8B, 0x25, "and.ge.u">;
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defm AND_LT : mIBinRR_RC_<0x0B, 0x22, 0x8B, 0x22, "and.lt">;
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defm AND_LT_U : mIBinRR_RC_<0x0B, 0x23, 0x8B, 0x23, "and.lt.u">;
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defm AND_NE : mIBinRR_RC_<0x0B, 0x21, 0x8B, 0x21, "and.ne">;
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defm ANDN : mIRR_RC<0x0F, 0x0E, 0x8F, 0x0E, "andn">;
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defm ANDN : mIBinRR_RC_<0x0F, 0x0E, 0x8F, 0x0E, "andn">;
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/// BISR
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def BISR_rc : IUnaryRC<0xAD, 0x00, "bisr">;
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def BISR_sc : IUnarySC<0xE0, "bisr">;
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/// Multiple Instructions (RR)
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def BMAERGE_rr : IBinRR_<0x4B, 0x01, "bmerge">;
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def BSPLIT_rr : IUnaryRR_E<0x4B, 0x09, "bsplit">;
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/// CACHEA.* Instructions
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class IBO_base_short_offset<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs), (ins AddrRegs:$s2, s10imm:$off10),
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asmstr # " [$s2]$off10", []>;
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class IBO_bit_reverse<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs AddrExtRegs:$b), (ins AddrRegs:$s2),
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asmstr # " [${b}+r]", []>;
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class IBO_circular<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs AddrExtRegs:$b), (ins s10imm:$off10),
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asmstr # " [${b}+c]", []>;
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let Constraints = "$s2 = $d" in {
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class IBO_post_increment<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs AddrRegs:$d), (ins AddrRegs:$s2, s10imm:$off10),
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asmstr # " [+$s2]$off10", []>;
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class IBO_pre_increment<bits<8> op1, bits<6> op2, string asmstr>
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: BO<op1, op2, (outs AddrRegs:$d), (ins AddrRegs:$s2, s10imm:$off10),
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asmstr # " [${s2}+]$off10", []>;
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}
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multiclass mIBO_a<bits<8> op11, bits<6> op12,
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bits<8> op21, bits<6> op22,
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bits<8> op31, bits<6> op32,
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string asmstr> {
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def _bo_bso : IBO_base_short_offset<op11, op12, asmstr>;
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def _bo_post : IBO_post_increment<op21, op22, asmstr>;
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def _bo_pre : IBO_pre_increment<op31, op32, asmstr>;
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}
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multiclass mIBO_b<bits<8> op11, bits<6> op12,
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bits<8> op21, bits<6> op22,
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string asmstr> {
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def _bo_r : IBO_bit_reverse<op11, op12, asmstr>;
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def _bo_c : IBO_circular<op21, op22, asmstr>;
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}
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multiclass mIBO_ab<bits<8> op11, bits<6> op12,//_bso
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bits<8> op21, bits<6> op22,//_r
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bits<8> op31, bits<6> op32,//_c
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bits<8> op41, bits<6> op42,//post
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bits<8> op51, bits<6> op52,//pre
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string asmstr>{
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defm "" : mIBO_a<op11,op12,
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op41,op42,
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op51,op52,
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asmstr>,
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mIBO_b<op21,op22,
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op31,op32,
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asmstr>;
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}
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defm CACHE_I : mIBO_ab<0x89, 0x2E,
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0xA9, 0x0E,
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0xA9, 0x1E,
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0x89, 0x0E,
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0x89, 0x1E,
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"cache.i">;
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defm CACHE_W : mIBO_ab<0x89, 0x2C,
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0xA9, 0x0C,
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0xA9, 0x1C,
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0x89, 0x0C,
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0x89, 0x1C,
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"cache.w">;
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defm CACHE_WI : mIBO_ab<0x89, 0x2D,
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0xA9, 0x0D,
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0xA9, 0x1D,
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0x89, 0x0D,
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0x89, 0x1D,
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"cache.wi">;
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defm CACHEI_W : mIBO_ab<0x89, 0x2B,
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0xA9, 0x0B,
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0xA9, 0x1B,
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0x89, 0x0B,
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0x89, 0x1B,
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"cachei.w">;
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defm CACHEI_I : mIBO_a<0x89, 0x2A,
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0x89, 0x0A,
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0x89, 0x1A,
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"cachei.i">;
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defm CACHEI_WI : mIBO_a<0x89, 0x2F,
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0x89, 0x0F,
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0x89, 0x1F,
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"cachei.wi">;
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let Defs = [PSW], Uses = [PSW] in {
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def SUBCrr : RR<0x0B, 0x0D, (outs DataRegs:$d),
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@ -87,26 +87,26 @@ def subreg_odd : SubRegIndex<32, 32>;
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//Extended 64-bit registers
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let SubRegIndices = [subreg_even, subreg_odd] in {
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def E0 : TriCoreRegWithSubregs<0, "e0", [D0,D1] >, DwarfRegNum<[32]>;
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def E2 : TriCoreRegWithSubregs<2, "e2", [D2,D3] >, DwarfRegNum<[33]>;
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def E4 : TriCoreRegWithSubregs<4, "e4", [D4,D5] >, DwarfRegNum<[34]>;
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def E6 : TriCoreRegWithSubregs<6, "e6", [D6,D7] >, DwarfRegNum<[35]>;
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def E8 : TriCoreRegWithSubregs<8, "e8", [D8,D9] >, DwarfRegNum<[36]>;
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def E0 : TriCoreRegWithSubregs<0, "e0", [D0,D1] >, DwarfRegNum<[32]>;
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def E2 : TriCoreRegWithSubregs<2, "e2", [D2,D3] >, DwarfRegNum<[33]>;
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def E4 : TriCoreRegWithSubregs<4, "e4", [D4,D5] >, DwarfRegNum<[34]>;
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def E6 : TriCoreRegWithSubregs<6, "e6", [D6,D7] >, DwarfRegNum<[35]>;
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def E8 : TriCoreRegWithSubregs<8, "e8", [D8,D9] >, DwarfRegNum<[36]>;
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def E10 : TriCoreRegWithSubregs<10, "e10", [D10,D11] >, DwarfRegNum<[37]>;
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def E12 : TriCoreRegWithSubregs<12, "e12", [D12,D13] >, DwarfRegNum<[38]>;
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def E14 : TriCoreRegWithSubregs<14, "e14", [D14,D15] >, DwarfRegNum<[39]>;
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}
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//let SubRegIndices = [subreg_even, subreg_odd] in {
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//def P0 : TriCoreRegWithSubregs<0, "p0", [A0,A1] >;
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//def P2 : TriCoreRegWithSubregs<2, "p2", [A2,A3] >;
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//def P4 : TriCoreRegWithSubregs<4, "p4", [A4,A5] >;
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//def P6 : TriCoreRegWithSubregs<6, "p6", [A6,A7] >;
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//def P8 : TriCoreRegWithSubregs<8, "p8", [A8,A9] >;
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//def P10 : TriCoreRegWithSubregs<10, "p10", [A10,A11] >;
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//def P12 : TriCoreRegWithSubregs<12, "p12", [A12,A13] >;
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//def P14 : TriCoreRegWithSubregs<14, "p14", [A14,A15] >;
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//}
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let SubRegIndices = [subreg_even, subreg_odd] in {
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def P0 : TriCoreRegWithSubregs<0, "p0", [A0,A1] >, DwarfRegNum<[40]>;
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def P2 : TriCoreRegWithSubregs<2, "p2", [A2,A3] >, DwarfRegNum<[41]>;
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def P4 : TriCoreRegWithSubregs<4, "p4", [A4,A5] >, DwarfRegNum<[42]>;
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def P6 : TriCoreRegWithSubregs<6, "p6", [A6,A7] >, DwarfRegNum<[43]>;
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def P8 : TriCoreRegWithSubregs<8, "p8", [A8,A9] >, DwarfRegNum<[44]>;
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def P10 : TriCoreRegWithSubregs<10, "p10", [A10,A11] >, DwarfRegNum<[45]>;
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def P12 : TriCoreRegWithSubregs<12, "p12", [A12,A13] >, DwarfRegNum<[46]>;
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def P14 : TriCoreRegWithSubregs<14, "p14", [A14,A15] >, DwarfRegNum<[47]>;
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}
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//Program Status Information Registers
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def PSW : TriCorePSReg<0, "psw">, DwarfRegNum<[40]>;
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@ -147,6 +147,11 @@ def ExtRegs : RegisterClass<"TriCore", [i64], 64, (add
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E6, E8, E10,
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E12, E14, E0)>;
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def AddrExtRegs : RegisterClass<"TriCore", [i64], 64, (add
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P2, P4,
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P6, P8, P10,
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P12, P14, P0)>;
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def PSRegs : RegisterClass<"TriCore", [i32], 32, (add
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PSW, PCXI, PC, FCX)>;
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