diff --git a/.github/workflows/auto-sync.yml b/.github/workflows/auto-sync.yml index d22729333..d1428d065 100644 --- a/.github/workflows/auto-sync.yml +++ b/.github/workflows/auto-sync.yml @@ -77,6 +77,7 @@ jobs: ./src/autosync/ASUpdater.py -d -a ARM -s IncGen ./src/autosync/ASUpdater.py -d -a PPC -s IncGen ./src/autosync/ASUpdater.py -d -a LoongArch -s IncGen + ./src/autosync/ASUpdater.py -d -a Mips -s IncGen - name: CppTranslator - Patch tests run: | @@ -92,6 +93,7 @@ jobs: ./src/autosync/ASUpdater.py --ci -d -a ARM -s Translate ./src/autosync/ASUpdater.py --ci -d -a PPC -s Translate ./src/autosync/ASUpdater.py --ci -d -a LoongArch -s Translate + ./src/autosync/ASUpdater.py --ci -d -a Mips -s Translate - name: Differ - Test save file is up-to-date run: | diff --git a/.gitignore b/.gitignore index 698c6d154..2e28a3061 100644 --- a/.gitignore +++ b/.gitignore @@ -143,7 +143,7 @@ cstool/cstool android-ndk-* # python virtual env -.venv/ +.ven*/ # Auto-sync files suite/auto-sync/src/autosync.egg-info diff --git a/MCInstPrinter.c b/MCInstPrinter.c index 9671dca9d..4e509c6ee 100644 --- a/MCInstPrinter.c +++ b/MCInstPrinter.c @@ -7,6 +7,7 @@ extern bool ARM_getFeatureBits(unsigned int mode, unsigned int feature); extern bool PPC_getFeatureBits(unsigned int mode, unsigned int feature); +extern bool Mips_getFeatureBits(unsigned int mode, unsigned int feature); extern bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature); extern bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature); @@ -25,6 +26,10 @@ static bool testFeatureBits(const MCInst *MI, uint32_t Value) case CS_ARCH_PPC: return PPC_getFeatureBits(MI->csh->mode, Value); #endif +#ifdef CAPSTONE_HAS_MIPS + case CS_ARCH_MIPS: + return Mips_getFeatureBits(MI->csh->mode, Value); +#endif #ifdef CAPSTONE_HAS_AARCH64 case CS_ARCH_AARCH64: return AArch64_getFeatureBits(MI->csh->mode, Value); diff --git a/MCRegisterInfo.c b/MCRegisterInfo.c index ce9a237a4..e8007fae6 100644 --- a/MCRegisterInfo.c +++ b/MCRegisterInfo.c @@ -149,3 +149,7 @@ bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg) return (c->RegSet[Byte] & (1 << InByte)) != 0; } + +unsigned MCRegisterClass_getRegister(const MCRegisterClass *c, unsigned RegNo) { + return c->RegsBegin[RegNo]; +} diff --git a/MCRegisterInfo.h b/MCRegisterInfo.h index 471a04a9d..8432e5e2c 100644 --- a/MCRegisterInfo.h +++ b/MCRegisterInfo.h @@ -113,4 +113,6 @@ const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsi bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg); +unsigned MCRegisterClass_getRegister(const MCRegisterClass *c, unsigned i); + #endif diff --git a/Mapping.c b/Mapping.c index c4f352185..2548f1cc4 100644 --- a/Mapping.c +++ b/Mapping.c @@ -338,6 +338,7 @@ DEFINE_get_detail_op(aarch64, AArch64); DEFINE_get_detail_op(alpha, Alpha); DEFINE_get_detail_op(hppa, HPPA); DEFINE_get_detail_op(loongarch, LoongArch); +DEFINE_get_detail_op(mips, Mips); DEFINE_get_detail_op(riscv, RISCV); /// Returns true if for this architecture the diff --git a/Mapping.h b/Mapping.h index a2f60cabf..7bbcfec00 100644 --- a/Mapping.h +++ b/Mapping.h @@ -138,6 +138,7 @@ DECL_get_detail_op(aarch64, AArch64); DECL_get_detail_op(alpha, Alpha); DECL_get_detail_op(hppa, HPPA); DECL_get_detail_op(loongarch, LoongArch); +DECL_get_detail_op(mips, Mips); DECL_get_detail_op(riscv, RISCV); /// Increments the detail->arch.op_count by one. @@ -168,6 +169,8 @@ DEFINE_inc_detail_op_count(hppa, HPPA); DEFINE_dec_detail_op_count(hppa, HPPA); DEFINE_inc_detail_op_count(loongarch, LoongArch); DEFINE_dec_detail_op_count(loongarch, LoongArch); +DEFINE_inc_detail_op_count(mips, Mips); +DEFINE_dec_detail_op_count(mips, Mips); DEFINE_inc_detail_op_count(riscv, RISCV); DEFINE_dec_detail_op_count(riscv, RISCV); @@ -198,6 +201,7 @@ DEFINE_get_arch_detail(aarch64, AArch64); DEFINE_get_arch_detail(alpha, Alpha); DEFINE_get_arch_detail(hppa, HPPA); DEFINE_get_arch_detail(loongarch, LoongArch); +DEFINE_get_arch_detail(mips, Mips); DEFINE_get_arch_detail(riscv, RISCV); static inline bool detail_is_set(const MCInst *MI) diff --git a/arch/Mips/MipsCP0RegisterMap.h b/arch/Mips/MipsCP0RegisterMap.h new file mode 100644 index 000000000..83951094f --- /dev/null +++ b/arch/Mips/MipsCP0RegisterMap.h @@ -0,0 +1,190 @@ +//===- MipsCP0RegisterMap.h - Co-processor register names for Mips/nanoMIPS -===// +// This has been created by hand. + +#ifndef LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H +#define LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H + +struct CP0SelRegister_t { + const char *Name; + int RegNum; + int Select; + int Index; +}; + +static const struct CP0SelRegister_t CP0SelRegs[] = { + {"index", 0, 0}, + {"mvpcontrol", 0, 1}, + {"mvpconf0", 0, 2}, + {"mvpconf1", 0, 3}, + {"vpcontrol", 0, 4}, + {"random", 1, 0}, + {"vpecontrol", 1, 1}, + {"vpeconf0", 1, 2}, + {"vpeconf1", 1, 3}, + {"yqmask", 1, 4}, + {"vpeschedule", 1, 5}, + {"vpeschefback", 1, 6}, + {"vpeopt", 1, 7}, + {"entrylo0", 2, 0}, + {"tcstatus", 2, 1}, + {"tcbind", 2, 2}, + {"tcrestart", 2, 3}, + {"tchalt", 2, 4}, + {"tccontext", 2, 5}, + {"tcschedule", 2, 6}, + {"tcschefback", 2, 7}, + {"entrylo1", 3, 0}, + {"globalnumber", 3, 1}, + {"tcopt", 3, 7}, + {"context", 4, 0}, + {"contextconfig", 4, 1}, + {"userlocal", 4, 2}, + {"xcontextconfig", 4, 3}, + {"debugcontextid", 4, 4}, + {"memorymapid", 4, 5}, + {"pagemask", 5, 0}, + {"pagegrain", 5, 1}, + {"segctl0", 5, 2}, + {"segctl1", 5, 3}, + {"segctl2", 5, 4}, + {"pwbase", 5, 5}, + {"pwfield", 5, 6}, + {"pwsize", 5, 7}, + {"wired", 6, 0}, + {"srsconf0", 6, 1}, + {"srsconf1", 6, 2}, + {"srsconf2", 6, 3}, + {"srsconf3", 6, 4}, + {"srsconf4", 6, 5}, + {"pwctl", 6, 6}, + {"hwrena", 7, 0}, + {"badvaddr", 8, 0}, + {"badinst", 8, 1}, + {"badinstrp", 8, 2}, + {"badinstrx", 8, 3}, + {"count", 9, 0}, + {"entryhi", 10, 0}, + {"guestctl1", 10, 4}, + {"guestctl2", 10, 5}, + {"guestctl3", 10, 6}, + {"compare", 11, 0}, + {"guestctl0ext", 11, 4}, + {"status", 12, 0}, + {"intctl", 12, 1}, + {"srsctl", 12, 2}, + {"srsmap", 12, 3}, + {"view_ipl", 12, 4}, + {"srsmap2", 12, 5}, + {"guestctl0", 12, 6}, + {"gtoffset", 12, 7}, + {"cause", 13, 0}, + {"view_ripl", 13, 4}, + {"nestedexc", 13, 5}, + {"epc", 14, 0}, + {"nestedepc", 14, 2}, + {"prid", 15, 0}, + {"ebase", 15, 1}, + {"cdmmbase", 15, 2}, + {"cmgcrbase", 15, 3}, + {"bevva", 15, 4}, + {"config", 16, 0}, + {"config1", 16, 1}, + {"config2", 16, 2}, + {"config3", 16, 3}, + {"config4", 16, 4}, + {"config5", 16, 5}, + {"lladdr", 17, 0}, + {"maar", 17, 1}, + {"maari", 17, 2}, + {"watchlo0", 18, 0}, + {"watchlo1", 18, 1}, + {"watchlo2", 18, 2}, + {"watchlo3", 18, 3}, + {"watchlo4", 18, 4}, + {"watchlo5", 18, 5}, + {"watchlo6", 18, 6}, + {"watchlo7", 18, 7}, + {"watchlo8", 18, 8}, + {"watchlo9", 18, 9}, + {"watchlo10", 18,10}, + {"watchlo11", 18,11}, + {"watchlo12", 18,12}, + {"watchlo13", 18,13}, + {"watchlo14", 18,14}, + {"watchlo15", 18,15}, + {"watchhi0", 19, 0}, + {"watchhi1", 19, 1}, + {"watchhi2", 19, 2}, + {"watchhi3", 19, 3}, + {"watchhi4", 19, 4}, + {"watchhi5", 19, 5}, + {"watchhi6", 19, 6}, + {"watchhi7", 19, 7}, + {"watchhi8", 19, 8}, + {"watchhi9", 19, 9}, + {"watchhi10", 19,10}, + {"watchhi11", 19,11}, + {"watchhi12", 19,12}, + {"watchhi13", 19,13}, + {"watchhi14", 19,14}, + {"watchhi15", 19,15}, + {"xcontext", 20, 0}, + {"debug", 23, 0}, + {"tracecontrol", 23, 1}, + {"tracecontrol2", 23, 2}, + {"usertracedata1", 23, 3}, + {"traceibpc", 23, 4}, + {"tracedbpc", 23, 5}, + {"debug2", 23, 6}, + {"depc", 24, 0}, + {"tracecontrol3", 24, 2}, + {"usertracedata2", 24, 3}, + {"perfctl0", 25, 0}, + {"perfcnt0", 25, 1}, + {"perfctl1", 25, 2}, + {"perfcnt1", 25, 3}, + {"perfctl2", 25, 4}, + {"perfcnt2", 25, 5}, + {"perfctl3", 25, 6}, + {"perfcnt3", 25, 7}, + {"perfctl4", 25, 8}, + {"perfcnt4", 25, 9}, + {"perfctl5", 25,10}, + {"perfcnt5", 25,11}, + {"perfctl6", 25,12}, + {"perfcnt6", 25,13}, + {"perfctl7", 25,14}, + {"perfcnt7", 25,15}, + {"errctl", 26, 0}, + {"cacheerr", 27, 0}, + {"itaglo", 28, 0}, + {"idatalo", 28, 1}, + {"dtaglo", 28, 2}, + {"ddatalo", 28, 3}, + {"itaghi", 29, 0}, + {"idatahi", 29, 1}, + {"dtaghi", 29, 2}, + {"ddatahi", 29, 3}, + {"errorepc", 30, 0}, + {"desave", 31, 0}, + {"kscratch1", 31, 2}, + {"kscratch2", 31, 3}, + {"kscratch3", 31, 4}, + {"kscratch4", 31, 5}, + {"kscratch5", 31, 6}, + {"kscratch6", 31, 7} +}; + +inline static int COP0Map_getEncIndexMap(int RegNo) +{ + int i; + for (i = 0; i < (sizeof(CP0SelRegs) / sizeof(CP0SelRegs[0])); ++i) { + unsigned RegEnc = (CP0SelRegs[i].RegNum << 5) | CP0SelRegs[i].Select; + if (RegEnc == RegNo) { + return i; + } + } + return -1; +} + +#endif // LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c index c5c6b5c97..7196de3db 100644 --- a/arch/Mips/MipsDisassembler.c +++ b/arch/Mips/MipsDisassembler.c @@ -1,9 +1,22 @@ -//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + +//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -11,527 +24,778 @@ // //===----------------------------------------------------------------------===// -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#ifdef CAPSTONE_HAS_MIPS - #include #include +#include +#include -#include "capstone/platform.h" - -#include "MipsDisassembler.h" - -#include "../../utils.h" - -#include "../../MCRegisterInfo.h" -#include "../../SStream.h" - -#include "../../MathExtras.h" - -//#include "Mips.h" -//#include "MipsRegisterInfo.h" -//#include "MipsSubtarget.h" -#include "../../MCFixedLenDisassembler.h" #include "../../MCInst.h" -//#include "llvm/MC/MCSubtargetInfo.h" -#include "../../MCRegisterInfo.h" +#include "../../MathExtras.h" +#include "../../MCInstPrinter.h" #include "../../MCDisassembler.h" - -// Forward declare these because the autogenerated code will reference them. -// Definitions are further down. -static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBranchTarget(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeJumpTarget(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBranchTarget21(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBranchTarget26(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is -// shifted left by 1 bit. -static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); - -// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is -// shifted left by 1 bit. -static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); - -// DecodeBranchTargetMM - Decode microMIPS branch offset, which is -// shifted left by 1 bit. -static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -// DecodeJumpTargetMM - Decode microMIPS jump target, which is -// shifted left by 1 bit. -static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCacheOp(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCacheOpR6(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCacheOpMM(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSyncI(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128Mem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMImm4(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMImm12(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMImm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, - uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeLiSimm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm4(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -// Decode the immediate field of an LSA instruction which -// is off by one. -static DecodeStatus DecodeLSAImm(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeInsSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeExtSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm9SP(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeANDI16Imm(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't -/// handle. -static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeRegListOperand(MCInst *Inst, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeRegListOperand16(MCInst *Inst, - uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMovePRegPair(MCInst *Inst, - uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); - +#include "../../MCRegisterInfo.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../cs_priv.h" +#include "../../utils.h" #define GET_SUBTARGETINFO_ENUM #include "MipsGenSubtargetInfo.inc" -// Hacky: enable all features for disassembler -static uint64_t getFeatureBits(int mode) -{ - uint64_t Bits = (uint64_t)-1; // include every features at first - - // By default we do not support Mips1 - Bits &= ~Mips_FeatureMips1; - - // No MicroMips - Bits &= ~Mips_FeatureMicroMips; - - // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate() - // some features are mutually execlusive - if (mode & CS_MODE_16) { - //Bits &= ~Mips_FeatureMips32r2; - //Bits &= ~Mips_FeatureMips32; - //Bits &= ~Mips_FeatureFPIdx; - //Bits &= ~Mips_FeatureBitCount; - //Bits &= ~Mips_FeatureSwap; - //Bits &= ~Mips_FeatureSEInReg; - //Bits &= ~Mips_FeatureMips64r2; - //Bits &= ~Mips_FeatureFP64Bit; - } else if (mode & CS_MODE_32) { - Bits &= ~Mips_FeatureMips16; - Bits &= ~Mips_FeatureFP64Bit; - Bits &= ~Mips_FeatureMips64r2; - Bits &= ~Mips_FeatureMips32r6; - Bits &= ~Mips_FeatureMips64r6; - } else if (mode & CS_MODE_64) { - Bits &= ~Mips_FeatureMips16; - Bits &= ~Mips_FeatureMips64r6; - Bits &= ~Mips_FeatureMips32r6; - } else if (mode & CS_MODE_MIPS32R6) { - Bits |= Mips_FeatureMips32r6; - Bits &= ~Mips_FeatureMips16; - Bits &= ~Mips_FeatureFP64Bit; - Bits &= ~Mips_FeatureMips64r6; - Bits &= ~Mips_FeatureMips64r2; - } - - if (mode & CS_MODE_MICRO) { - Bits |= Mips_FeatureMicroMips; - Bits &= ~Mips_FeatureMips4_32r2; - Bits &= ~Mips_FeatureMips2; - } - - return Bits; -} - -#include "MipsGenDisassemblerTables.inc" - -#define GET_REGINFO_ENUM -#include "MipsGenRegisterInfo.inc" - -#define GET_REGINFO_MC_DESC -#include "MipsGenRegisterInfo.inc" - #define GET_INSTRINFO_ENUM #include "MipsGenInstrInfo.inc" -void Mips_init(MCRegisterInfo *MRI) +#define GET_REGINFO_ENUM +#include "MipsGenRegisterInfo.inc" + +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b + +#define DEBUG_TYPE "mips-disassembler" + +bool Mips_getFeatureBits(unsigned int mode, unsigned int feature) { - // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC, - // MipsMCRegisterClasses, 62, - // MipsRegUnitRoots, - // 273, - // MipsRegDiffLists, - // MipsLaneMaskLists, - // MipsRegStrings, - // MipsRegClassStrings, - // MipsSubRegIdxLists, - // 12, - // MipsSubRegIdxRanges, - // MipsRegEncodingTable); - - - MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394, - 0, 0, - MipsMCRegisterClasses, 62, - 0, 0, - MipsRegDiffLists, - 0, - MipsSubRegIdxLists, 12, - 0); -} - -/// Read two bytes from the ArrayRef and return 16 bit halfword sorted -/// according to the given endianness. -static void readInstruction16(unsigned char *code, uint32_t *insn, - bool isBigEndian) -{ - // We want to read exactly 2 Bytes of data. - if (isBigEndian) - *insn = (code[0] << 8) | code[1]; - else - *insn = (code[1] << 8) | code[0]; -} - -/// readInstruction - read four bytes from the MemoryObject -/// and return 32 bit word sorted according to the given endianness -static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips) -{ - // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) - // always precede the low 16 bits in the instruction stream (that is, they - // are placed at lower addresses in the instruction stream). - // - // microMIPS byte ordering: - // Big-endian: 0 | 1 | 2 | 3 - // Little-endian: 1 | 0 | 3 | 2 - - // We want to read exactly 4 Bytes of data. - if (isBigEndian) { - // Encoded as a big-endian 32-bit word in the stream. - *insn = - (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); - } else { - if (isMicroMips) { - *insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) | - ((uint32_t) code[1] << 24); - } else { - *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | - ((uint32_t) code[3] << 24); + switch(feature) { + case Mips_FeatureGP64Bit: + return mode & (CS_MODE_MIPS3 | CS_MODE_MIPS4 | + CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureFP64Bit: + return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS3 | + CS_MODE_MIPS4 | CS_MODE_MIPS5 | + CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | + CS_MODE_MIPS32R5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureNaN2008: + return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS64R6); + case Mips_FeatureAbs2008: + return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS64R6); + case Mips_FeatureMips1: + return mode & (CS_MODE_MIPS1 | CS_MODE_MIPS2 | + CS_MODE_MIPS32 | CS_MODE_MIPS32R2 | + CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | + CS_MODE_MIPS32R6 | CS_MODE_MIPS3 | + CS_MODE_MIPS4 | CS_MODE_MIPS5 | + CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | + CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | + CS_MODE_MIPS64R6 | CS_MODE_OCTEON | + CS_MODE_OCTEONP); + case Mips_FeatureMips2: + return mode & (CS_MODE_MIPS2 | CS_MODE_MIPS32 | + CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | + CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | + CS_MODE_MIPS3 | CS_MODE_MIPS4 | + CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips3_32: + return mode & (CS_MODE_MIPS32 | CS_MODE_MIPS32R2 | + CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | + CS_MODE_MIPS32R6 | CS_MODE_MIPS3 | + CS_MODE_MIPS4 | CS_MODE_MIPS5 | + CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | + CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | + CS_MODE_MIPS64R6 | CS_MODE_OCTEON | + CS_MODE_OCTEONP); + case Mips_FeatureMips3_32r2: + return mode & (CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | + CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | + CS_MODE_MIPS3 | CS_MODE_MIPS4 | + CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips3: + return mode & (CS_MODE_MIPS3 | CS_MODE_MIPS4 | + CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips4_32: + return mode & (CS_MODE_MIPS32 | CS_MODE_MIPS32R2 | + CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | + CS_MODE_MIPS32R6 | CS_MODE_MIPS4 | + CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips4_32r2: + return mode & (CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | + CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | + CS_MODE_MIPS4 | CS_MODE_MIPS5 | + CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | + CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | + CS_MODE_MIPS64R6 | CS_MODE_OCTEON | + CS_MODE_OCTEONP); + case Mips_FeatureMips4: + return mode & (CS_MODE_MIPS4 | CS_MODE_MIPS5 | + CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | + CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | + CS_MODE_MIPS64R6 | CS_MODE_OCTEON | + CS_MODE_OCTEONP); + case Mips_FeatureMips5_32r2: + return mode & (CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | + CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | + CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips5: + return mode & (CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips32: + return mode & (CS_MODE_MIPS32 | CS_MODE_MIPS32R2 | + CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | + CS_MODE_MIPS32R6 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips32r2: + return mode & (CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | + CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips32r3: + return mode & (CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | + CS_MODE_MIPS32R6 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6); + case Mips_FeatureMips32r5: + return mode & (CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6); + case Mips_FeatureMips32r6: + return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS64R6); + case Mips_FeatureMips64: + return mode & (CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | + CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | + CS_MODE_MIPS64R6 | CS_MODE_OCTEON | + CS_MODE_OCTEONP); + case Mips_FeatureMips64r2: + return mode & (CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips64r3: + return mode & (CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | + CS_MODE_MIPS64R6); + case Mips_FeatureMips64r5: + return mode & (CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6); + case Mips_FeatureMips64r6: + return mode & CS_MODE_MIPS64R6; + case Mips_FeatureMips16: + return mode & CS_MODE_MIPS16; + case Mips_FeatureMicroMips: + return mode & CS_MODE_MICRO; + case Mips_FeatureNanoMips: + return mode & (CS_MODE_NANOMIPS | CS_MODE_NMS1 | + CS_MODE_I7200); + case Mips_FeatureNMS1: + return mode & CS_MODE_NMS1; + case Mips_FeatureTLB: + return mode & CS_MODE_I7200; + case Mips_FeatureCnMips: + return mode & (CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureCnMipsP: + return mode & CS_MODE_OCTEONP; + case Mips_FeaturePTR64Bit: + return mode & CS_MODE_MIPS_PTR64; + case Mips_FeatureSoftFloat: + return mode & CS_MODE_MIPS_NOFLOAT; + case Mips_FeatureI7200: + return mode & CS_MODE_I7200; + // optional features always enabled + case Mips_FeatureDSP: // Mips DSP ASE + return true; + case Mips_FeatureDSPR2: // Mips DSP-R2 ASE + return true; + case Mips_FeatureDSPR3: // Mips DSP-R3 ASE + return true; + case Mips_FeatureMips3D: // Mips 3D ASE + return true; + case Mips_FeatureMSA: // Mips MSA ASE + return true; + case Mips_FeatureEVA: { // Mips EVA ASE + if (mode & CS_MODE_NANOMIPS) { + return mode & CS_MODE_I7200; } + return true; + } + case Mips_FeatureCRC: // Mips R6 CRC ASE + return true; + case Mips_FeatureVirt: // Mips Virtualization ASE + return true; + case Mips_FeatureGINV: // Mips Global Invalidate ASE + return true; + case Mips_FeatureMT: { // Mips MT ASE + if (mode & CS_MODE_NANOMIPS) { + return mode & CS_MODE_I7200; + } + return true; + } + case Mips_FeatureUseIndirectJumpsHazard: + return true; + default: + return false; } } -static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr, - const uint8_t *code, size_t code_len, - uint16_t *Size, - uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI) +static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes, + size_t BytesLen, uint64_t Address, SStream *CStream); + +// end anonymous namespace + +// Forward declare these because the autogenerated code will reference them. +// Definitions are further down. +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRNM3RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRNM4RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRNMRARegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRNM3ZRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRNM4ZRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRNM32NZRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRNM32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRNM2R1RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRNM1R1RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeCOP0RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeCOP0SelRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeBranchTarget(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeBranchTarget1SImm16(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeJumpTarget(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeBranchTarget21(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeBranchTarget21MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeBranchTarget26(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder); + +// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder); + +// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder); + +// DecodeBranchTargetMM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder); + +// DecodeBranchTarget26MM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTarget26MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder); + +// DecodeBranchTargetMM - Decode nanoMIPS branch offset, which is +// shifted left by 1 bit. +#define DECLARE_DecodeBranchTargetNM(bits) \ + static DecodeStatus CONCAT(DecodeBranchTargetNM, bits)( \ + MCInst * Inst, unsigned Offset, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeBranchTargetNM(10); +DECLARE_DecodeBranchTargetNM(7); +DECLARE_DecodeBranchTargetNM(21); +DECLARE_DecodeBranchTargetNM(25); +DECLARE_DecodeBranchTargetNM(14); +DECLARE_DecodeBranchTargetNM(11); +DECLARE_DecodeBranchTargetNM(5); + +// DecodeJumpTargetMM - Decode microMIPS jump target, which is +// shifted left by 1 bit. +static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +// DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target, +// which is shifted left by 2 bit. +static DecodeStatus DecodeJumpTargetXMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeMem(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +#define DECLARE_DecodeMemNM(Offbits, isSigned, rt) \ + static DecodeStatus CONCAT(DecodeMemNM, \ + CONCAT(Offbits, CONCAT(isSigned, rt)))( \ + MCInst * Inst, uint32_t Insn, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeMemNM(6, 0, Mips_GPRNM3RegClassID); +DECLARE_DecodeMemNM(7, 0, Mips_GPRNMSPRegClassID); +DECLARE_DecodeMemNM(9, 0, Mips_GPRNMGPRegClassID); +DECLARE_DecodeMemNM(2, 0, Mips_GPRNM3RegClassID); +DECLARE_DecodeMemNM(3, 0, Mips_GPRNM3RegClassID); +DECLARE_DecodeMemNM(21, 0, Mips_GPRNMGPRegClassID); +DECLARE_DecodeMemNM(18, 0, Mips_GPRNMGPRegClassID); +DECLARE_DecodeMemNM(12, 0, Mips_GPRNM32RegClassID); +DECLARE_DecodeMemNM(9, 1, Mips_GPRNM32RegClassID); + +static DecodeStatus DecodeMemZeroNM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +#define DECLARE_DecodeMemNMRX(rt) \ + static DecodeStatus CONCAT(DecodeMemNMRX, \ + rt)(MCInst * Inst, uint32_t Insn, \ + uint64_t Address, const void *Decoder); +DECLARE_DecodeMemNMRX(Mips_GPRNM3RegClassID); +DECLARE_DecodeMemNMRX(Mips_GPRNM32RegClassID); + +static DecodeStatus DecodeMemNM4x4(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeMemEVA(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeLoadByte15(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeCacheOp(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeCacheOpMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodePrefeOpMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeSyncI(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeSyncI_MM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeSynciR6(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMSA128Mem(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeMemMMImm4(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMemMMImm9(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeMemMMImm12(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeMemMMImm16(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeFMem(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFMemMMR2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeFMem2(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFMem3(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeFMemCop2MMR6(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeLi16Imm(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodePOOL16BEncodedField(MCInst *Inst, unsigned Value, + uint64_t Address, + const void *Decoder); + +#define DECLARE_DecodeUImmWithOffsetAndScale(Bits, Offset, Scale) \ + static DecodeStatus CONCAT(DecodeUImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, Scale)))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeUImmWithOffsetAndScale(5, 0, 4); +DECLARE_DecodeUImmWithOffsetAndScale(6, 0, 4); +DECLARE_DecodeUImmWithOffsetAndScale(2, 1, 1); +DECLARE_DecodeUImmWithOffsetAndScale(5, 1, 1); +DECLARE_DecodeUImmWithOffsetAndScale(8, 0, 1); +DECLARE_DecodeUImmWithOffsetAndScale(18, 0, 1); +DECLARE_DecodeUImmWithOffsetAndScale(21, 0, 1); + +#define DEFINE_DecodeUImmWithOffset(Bits, Offset) \ + static DecodeStatus CONCAT(DecodeUImmWithOffset, \ + CONCAT(Bits, Offset))(MCInst * Inst, \ + unsigned Value, \ + uint64_t Address, \ + const void *Decoder) \ + { \ + return CONCAT(DecodeUImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, 1)))( \ + Inst, Value, Address, Decoder); \ + } +DEFINE_DecodeUImmWithOffset(5, 1); +DEFINE_DecodeUImmWithOffset(2, 1); + +#define DECLARE_DecodeSImmWithOffsetAndScale(Bits, Offset, ScaleBy) \ + static DecodeStatus CONCAT( \ + DecodeSImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, ScaleBy)))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder); + +#define DECLARE_DecodeSImmWithOffsetAndScale_2(Bits, Offset) DECLARE_DecodeSImmWithOffsetAndScale(Bits, Offset, 1) +#define DECLARE_DecodeSImmWithOffsetAndScale_3(Bits) DECLARE_DecodeSImmWithOffsetAndScale(Bits, 0, 1) + +DECLARE_DecodeSImmWithOffsetAndScale_3(16); +DECLARE_DecodeSImmWithOffsetAndScale_3(10); +DECLARE_DecodeSImmWithOffsetAndScale_3(4); +DECLARE_DecodeSImmWithOffsetAndScale_3(6); +DECLARE_DecodeSImmWithOffsetAndScale_3(32); + +static DecodeStatus DecodeInsSize(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeImmM1To126(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeUImm4Mask(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeUImm3Shift(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeNMRegListOperand(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeNMRegList16Operand(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeNegImm12(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +#define DECLARE_DecodeSImmWithReg(Bits, Offset, Scale, RegNum) \ + static DecodeStatus CONCAT( \ + DecodeSImmWithReg, \ + CONCAT(Bits, CONCAT(Offset, CONCAT(Scale, RegNum))))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeSImmWithReg(32, 0, 1, Mips_GP_NM); + +#define DECLARE_DecodeUImmWithReg(Bits, Offset, Scale, RegNum) \ + static DecodeStatus CONCAT( \ + DecodeUImmWithReg, \ + CONCAT(Bits, CONCAT(Offset, CONCAT(Scale, RegNum))))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeUImmWithReg(8, 0, 1, Mips_SP_NM); +DECLARE_DecodeUImmWithReg(21, 0, 1, Mips_GP_NM); +DECLARE_DecodeUImmWithReg(18, 0, 1, Mips_GP_NM); + +static DecodeStatus DecodeSImm32s12(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +#define DECLARE_DecodeAddressPCRelNM(Bits) \ + static DecodeStatus CONCAT(DecodeAddressPCRelNM, Bits)( \ + MCInst * Inst, uint32_t Insn, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeAddressPCRelNM(22); +DECLARE_DecodeAddressPCRelNM(32); + +static DecodeStatus DecodeBranchConflictNM(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeSimm9SP(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeANDI16Imm(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't +/// handle. +static DecodeStatus DecodeINSVE_DF(MCInst *MI, uint32_t insn, uint64_t Address, + const void *Decoder); + +/* +static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, const void *Decoder); +*/ + +static DecodeStatus DecodeDAHIDATI(MCInst *MI, uint32_t insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeAddiGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeDaddiGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeBlezlGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeBgtzlGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeBgtzGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeBlezGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeDINS(MCInst *MI, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeDEXT(MCInst *MI, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeCRC(MCInst *MI, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeRegListOperand(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeRegListOperand16(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned RegPair, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeMovePOperands(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeFIXMEInstruction(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +#include "MipsGenDisassemblerTables.inc" + +static unsigned getReg(const MCInst *Inst, unsigned RC, unsigned RegNo) { - uint32_t Insn; - DecodeStatus Result; - - if (instr->flat_insn->detail) { - memset(instr->flat_insn->detail, 0, offsetof(cs_detail, mips)+sizeof(cs_mips)); - } - - if (mode & CS_MODE_MICRO) { - if (code_len < 2) - // not enough data - return MCDisassembler_Fail; - - readInstruction16((unsigned char*)code, &Insn, isBigEndian); - - // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 2; - return Result; - } - - if (code_len < 4) - // not enough data - return MCDisassembler_Fail; - - readInstruction32((unsigned char*)code, &Insn, isBigEndian, true); - - //DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); - // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - return MCDisassembler_Fail; - } - - if (code_len < 4) - // not enough data - return MCDisassembler_Fail; - - readInstruction32((unsigned char*)code, &Insn, isBigEndian, false); - - if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) { - // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - } - - if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) { - // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn, - Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - } - - if (mode & CS_MODE_MIPS32R6) { - // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn, - Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - } - - if (mode & CS_MODE_MIPS64) { - // DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips6432, instr, Insn, - Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - } - - // DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); - // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - - return MCDisassembler_Fail; + const MCRegisterClass* c = MCRegisterInfo_getRegClass(Inst->MRI, RC); + return MCRegisterClass_getRegister(c, RegNo); } -bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, - uint16_t *size, uint64_t address, void *info) +typedef DecodeStatus (*DecodeFN)(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeINSVE_DF(MCInst *MI, uint32_t insn, uint64_t Address, + const void *Decoder) { - cs_struct *handle = (cs_struct *)(uintptr_t)ud; - - DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr, - code, code_len, - size, - address, MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info); - - return status == MCDisassembler_Success; -} - -static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) -{ - const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); - return rc->RegsBegin[RegNo]; -} - -static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *); // The size of the n field depends on the element size // The register class also depends on this. - uint32_t tmp = fieldFromInstruction(insn, 17, 5); + uint32_t tmp = fieldFromInstruction_4(insn, 17, 5); unsigned NSize = 0; DecodeFN RegDecoder = NULL; - - if ((tmp & 0x18) == 0x00) { // INSVE_B + if ((tmp & 0x18) == 0x00) { // INSVE_B NSize = 4; RegDecoder = DecodeMSA128BRegisterClass; } else if ((tmp & 0x1c) == 0x10) { // INSVE_H @@ -543,38 +807,57 @@ static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn, } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D NSize = 1; RegDecoder = DecodeMSA128DRegisterClass; - } //else llvm_unreachable("Invalid encoding"); - - //assert(NSize != 0 && RegDecoder != nullptr); - if (NSize == 0 || RegDecoder == NULL) - return MCDisassembler_Fail; + } else + assert(0 && "Invalid encoding"); // $wd - tmp = fieldFromInstruction(insn, 6, 5); + tmp = fieldFromInstruction_4(insn, 6, 5); if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; - // $wd_in if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; - // $n - tmp = fieldFromInstruction(insn, 16, NSize); - MCOperand_CreateImm0(MI, tmp); - + tmp = fieldFromInstruction_4(insn, 16, NSize); + MCOperand_CreateImm0(MI, (tmp)); // $ws - tmp = fieldFromInstruction(insn, 11, 5); + tmp = fieldFromInstruction_4(insn, 11, 5); if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; - // $n2 - MCOperand_CreateImm0(MI, 0); + MCOperand_CreateImm0(MI, (0)); return MCDisassembler_Success; } -static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +/* +static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, const void *Decoder) +{ + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + uint32_t Imm = fieldFromInstruction_4(insn, 0, 16); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} +*/ + +static DecodeStatus DecodeDAHIDATI(MCInst *MI, uint32_t insn, uint64_t Address, + const void *Decoder) + { + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Imm = fieldFromInstruction_4(insn, 0, 16); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; + } + +static DecodeStatus DecodeAddiGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, const void *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the ADDI instruction from the earlier @@ -586,31 +869,74 @@ static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn, // BEQZALC if rs == 0 && rt != 0 // BEQC if rs < rt && rs != 0 - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; if (Rs >= Rt) { - MCInst_setOpcode(MI, Mips_BOVC); + MCInst_setOpcode(MI, (Mips_BOVC)); HasRs = true; } else if (Rs != 0 && Rs < Rt) { - MCInst_setOpcode(MI, Mips_BEQC); + MCInst_setOpcode(MI, (Mips_BEQC)); HasRs = true; } else - MCInst_setOpcode(MI, Mips_BEQZALC); + MCInst_setOpcode(MI, (Mips_BEQZALC)); if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - MCOperand_CreateImm0(MI, Imm); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) +{ + uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = 0; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, (Mips_BOVC_MMR6)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, (Mips_BEQC_MMR6)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 4 + + 4; + } else { + MCInst_setOpcode(MI, (Mips_BEQZALC_MMR6)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } + + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDaddiGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the ADDI instruction from the earlier @@ -622,31 +948,152 @@ static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, // BNEZALC if rs == 0 && rt != 0 // BNEC if rs < rt && rs != 0 - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; if (Rs >= Rt) { - MCInst_setOpcode(MI, Mips_BNVC); + MCInst_setOpcode(MI, (Mips_BNVC)); HasRs = true; } else if (Rs != 0 && Rs < Rt) { - MCInst_setOpcode(MI, Mips_BNEC); + MCInst_setOpcode(MI, (Mips_BNEC)); HasRs = true; } else - MCInst_setOpcode(MI, Mips_BNEZALC); + MCInst_setOpcode(MI, (Mips_BNEZALC)); if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - MCOperand_CreateImm0(MI, Imm); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) +{ + uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = 0; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, (Mips_BNVC_MMR6)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, (Mips_BNEC_MMR6)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 4 + + 4; + } else { + MCInst_setOpcode(MI, (Mips_BNEZALC_MMR6)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } + + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) +{ + // We have: + // 0b110101 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BGTZC_MMR6 if rs == 0 && rt != 0 + // BLTZC_MMR6 if rs == rt && rt != 0 + // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 + + uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, (Mips_BGTZC_MMR6)); + else if (Rs == Rt) + MCInst_setOpcode(MI, (Mips_BLTZC_MMR6)); + else { + MCInst_setOpcode(MI, (Mips_BLTC_MMR6)); + HasRs = true; + } + + if (HasRs) + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) +{ + // We have: + // 0b111101 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BLEZC_MMR6 if rs == 0 && rt != 0 + // BGEZC_MMR6 if rs == rt && rt != 0 + // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 + + uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, (Mips_BLEZC_MMR6)); + else if (Rs == Rt) + MCInst_setOpcode(MI, (Mips_BGEZC_MMR6)); + else { + HasRs = true; + MCInst_setOpcode(MI, (Mips_BGEC_MMR6)); + } + + if (HasRs) + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBlezlGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BLEZL instruction from the earlier @@ -659,34 +1106,37 @@ static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn, // BGEZC if rs == rt && rt != 0 // BGEC if rs != rt && rs != 0 && rt != 0 - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; if (Rt == 0) return MCDisassembler_Fail; else if (Rs == 0) - MCInst_setOpcode(MI, Mips_BLEZC); + MCInst_setOpcode(MI, (Mips_BLEZC)); else if (Rs == Rt) - MCInst_setOpcode(MI, Mips_BGEZC); + MCInst_setOpcode(MI, (Mips_BGEZC)); else { HasRs = true; - MCInst_setOpcode(MI, Mips_BGEC); + MCInst_setOpcode(MI, (Mips_BGEC)); } if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); - MCOperand_CreateImm0(MI, Imm); + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBgtzlGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BGTZL instruction from the earlier @@ -701,32 +1151,35 @@ static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn, bool HasRs = false; - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; if (Rt == 0) return MCDisassembler_Fail; else if (Rs == 0) - MCInst_setOpcode(MI, Mips_BGTZC); + MCInst_setOpcode(MI, (Mips_BGTZC)); else if (Rs == Rt) - MCInst_setOpcode(MI, Mips_BLTZC); + MCInst_setOpcode(MI, (Mips_BLTZC)); else { - MCInst_setOpcode(MI, Mips_BLTC); + MCInst_setOpcode(MI, (Mips_BLTC)); HasRs = true; } if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - MCOperand_CreateImm0(MI, Imm); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBgtzGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, const void *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BGTZ instruction from the earlier @@ -739,40 +1192,43 @@ static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn, // BLTZALC if rs != 0 && rs == rt // BLTUC if rs != 0 && rs != rt - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; bool HasRt = false; if (Rt == 0) { - MCInst_setOpcode(MI, Mips_BGTZ); + MCInst_setOpcode(MI, (Mips_BGTZ)); HasRs = true; } else if (Rs == 0) { - MCInst_setOpcode(MI, Mips_BGTZALC); + MCInst_setOpcode(MI, (Mips_BGTZALC)); HasRt = true; } else if (Rs == Rt) { - MCInst_setOpcode(MI, Mips_BLTZALC); + MCInst_setOpcode(MI, (Mips_BLTZALC)); HasRs = true; } else { - MCInst_setOpcode(MI, Mips_BLTUC); + MCInst_setOpcode(MI, (Mips_BLTUC)); HasRs = true; HasRt = true; } if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); if (HasRt) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); - MCOperand_CreateImm0(MI, Imm); + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBlezGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, const void *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BLEZL instruction from the earlier @@ -785,294 +1241,984 @@ static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn, // BGEZALC if rs == rt && rt != 0 // BGEUC if rs != rt && rs != 0 && rt != 0 - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; if (Rt == 0) return MCDisassembler_Fail; else if (Rs == 0) - MCInst_setOpcode(MI, Mips_BLEZALC); + MCInst_setOpcode(MI, (Mips_BLEZALC)); else if (Rs == Rt) - MCInst_setOpcode(MI, Mips_BGEZALC); + MCInst_setOpcode(MI, (Mips_BGEZALC)); else { HasRs = true; - MCInst_setOpcode(MI, Mips_BGEUC); + MCInst_setOpcode(MI, (Mips_BGEUC)); } if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - - MCOperand_CreateImm0(MI, Imm); + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +// Override the generated disassembler to produce DEXT all the time. This is +// for feature / behaviour parity with binutils. +static DecodeStatus DecodeDEXT(MCInst *MI, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Msbd = fieldFromInstruction_4(Insn, 11, 5); + unsigned Lsb = fieldFromInstruction_4(Insn, 6, 5); + unsigned Size = 0; + unsigned Pos = 0; + + switch (MCInst_getOpcode(MI)) { + case Mips_DEXT: + Pos = Lsb; + Size = Msbd + 1; + break; + case Mips_DEXTM: + Pos = Lsb; + Size = Msbd + 1 + 32; + break; + case Mips_DEXTU: + Pos = Lsb + 32; + Size = Msbd + 1; + break; + default: + assert(0 && "Unknown DEXT instruction!"); + } + + MCInst_setOpcode(MI, (Mips_DEXT)); + + uint32_t Rs = fieldFromInstruction_4(Insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(Insn, 16, 5); + + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rt))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateImm0(MI, (Pos)); + MCOperand_CreateImm0(MI, (Size)); + + return MCDisassembler_Success; +} + +// Override the generated disassembler to produce DINS all the time. This is +// for feature / behaviour parity with binutils. +static DecodeStatus DecodeDINS(MCInst *MI, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Msbd = fieldFromInstruction_4(Insn, 11, 5); + unsigned Lsb = fieldFromInstruction_4(Insn, 6, 5); + unsigned Size = 0; + unsigned Pos = 0; + + switch (MCInst_getOpcode(MI)) { + case Mips_DINS: + Pos = Lsb; + Size = Msbd + 1 - Pos; + break; + case Mips_DINSM: + Pos = Lsb; + Size = Msbd + 33 - Pos; + break; + case Mips_DINSU: + Pos = Lsb + 32; + // mbsd = pos + size - 33 + // mbsd - pos + 33 = size + Size = Msbd + 33 - Pos; + break; + default: + assert(0 && "Unknown DINS instruction!"); + } + + uint32_t Rs = fieldFromInstruction_4(Insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(Insn, 16, 5); + + MCInst_setOpcode(MI, (Mips_DINS)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rt))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateImm0(MI, (Pos)); + MCOperand_CreateImm0(MI, (Size)); + + return MCDisassembler_Success; +} + +// Auto-generated decoder wouldn't add the third operand for CRC32*. +static DecodeStatus DecodeCRC(MCInst *MI, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + uint32_t Rs = fieldFromInstruction_4(Insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(Insn, 16, 5); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + return MCDisassembler_Success; +} + +/// Read two bytes from the ArrayRef and return 16 bit halfword sorted +/// according to the given endianness. +static DecodeStatus readInstruction16(const uint8_t *Bytes, size_t BytesLen, + uint64_t Address, uint64_t *Size, + uint64_t *Insn, bool IsBigEndian) +{ + // We want to read exactly 2 Bytes of data. + if (BytesLen < 2) { + *Size = 0; + return MCDisassembler_Fail; + } + + if (IsBigEndian) { + *Insn = (Bytes[0] << 8) | Bytes[1]; + } else { + *Insn = (Bytes[1] << 8) | Bytes[0]; + } + + return MCDisassembler_Success; +} + +/// Read four bytes from the ArrayRef and return 32 bit word sorted +/// according to the given endianness. +static DecodeStatus readInstruction32(const uint8_t *Bytes, size_t BytesLen, + uint64_t Address, uint64_t *Size, + uint64_t *Insn, bool IsBigEndian, + bool IsMicroMips) +{ + // We want to read exactly 4 Bytes of data. + if (BytesLen < 4) { + *Size = 0; + return MCDisassembler_Fail; + } + + // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) + // always precede the low 16 bits in the instruction stream (that is, they + // are placed at lower addresses in the instruction stream). + // + // microMIPS byte ordering: + // Big-endian: 0 | 1 | 2 | 3 + // Little-endian: 1 | 0 | 3 | 2 + + if (IsBigEndian) { + // Encoded as a big-endian 32-bit word in the stream. + *Insn = (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | + (Bytes[0] << 24); + } else { + if (IsMicroMips) { + *Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | + (Bytes[0] << 16) | (Bytes[1] << 24); + } else { + *Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | + (Bytes[2] << 16) | (Bytes[3] << 24); + } + } + + return MCDisassembler_Success; +} + +/// Read 6 bytes from the ArrayRef and return in a 64-bit bit word sorted +/// according to the given endianness and encoding byte-order. +static DecodeStatus readInstruction48(const uint8_t *Bytes, size_t BytesLen, + uint64_t Address, uint64_t *Size, + uint64_t *Insn, bool IsBigEndian, + bool IsNanoMips) +{ + // We want to read exactly 6 Bytes of little-endian data in nanoMIPS mode. + if (BytesLen < 6 || IsBigEndian || !IsNanoMips) { + *Size = 0; + return MCDisassembler_Fail; + } + + // High 16 bits of a 32-bit nanoMIPS instruction (where the opcode is) + // always precede the low 16 bits in the instruction stream (that is, they + // are placed at lower addresses in the instruction stream). + // + // nanoMIPS byte ordering: + // Little-endian: 1 | 0 | 3 | 2 | 5 | 4 + + *Insn = (Bytes[0] << 0) | (Bytes[1] << 8); + *Insn = ((*Insn << 32) | (Bytes[4] << 0) | (Bytes[5] << 8) | + (Bytes[2] << 16) | ((unsigned)Bytes[3] << 24)); + return MCDisassembler_Success; +} + +static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes, + size_t BytesLen, uint64_t Address, SStream *CStream) +{ + uint64_t Insn; + DecodeStatus Result; + *Size = 0; + + cs_mode mode = Instr->csh->mode; + bool IsBigEndian = mode & CS_MODE_BIG_ENDIAN; + bool IsMicroMips = Mips_getFeatureBits(mode, Mips_FeatureMicroMips); + bool IsNanoMips = Mips_getFeatureBits(mode, Mips_FeatureNanoMips); + bool IsMips32r6 = Mips_getFeatureBits(mode, Mips_FeatureMips32r6); + bool IsMips2 = Mips_getFeatureBits(mode, Mips_FeatureMips2); + bool IsCnMips = Mips_getFeatureBits(mode, Mips_FeatureCnMips); + bool IsCnMipsP = Mips_getFeatureBits(mode, Mips_FeatureCnMipsP); + bool IsFP64 = Mips_getFeatureBits(mode, Mips_FeatureFP64Bit); + bool IsGP64 = Mips_getFeatureBits(mode, Mips_FeatureGP64Bit); + bool IsPTR64 = Mips_getFeatureBits(mode, Mips_FeaturePTR64Bit); + // Only present in MIPS-I and MIPS-II + bool HasCOP3 = !Mips_getFeatureBits(mode, Mips_FeatureMips32) && + !Mips_getFeatureBits(mode, Mips_FeatureMips3); + + if (IsNanoMips) { + uint64_t Insn2; + Result = readInstruction48(Bytes, BytesLen, Address, Size, + &Insn2, IsBigEndian, IsNanoMips); + if (Result != MCDisassembler_Fail) { + // Calling the auto-generated decoder function. + Result = decodeInstruction_8(DecoderTableNanoMips48, + Instr, Insn2, Address, NULL); + if (Result != MCDisassembler_Fail) { + *Size = 6; + return Result; + } + } + + Result = readInstruction32(Bytes, BytesLen, Address, Size, + &Insn, IsBigEndian, IsNanoMips); + if (Result != MCDisassembler_Fail) { + // Calling the auto-generated decoder function. + Result = decodeInstruction_4(DecoderTableNanoMips32, + Instr, Insn, Address, + NULL); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + Result = readInstruction16(Bytes, BytesLen, Address, Size, + &Insn, IsBigEndian); + if (Result != MCDisassembler_Fail) { + // Calling the auto-generated decoder function for NanoMips + // 16-bit instructions. + Result = decodeInstruction_2(DecoderTableNanoMips16, + Instr, Insn, Address, + NULL); + if (Result != MCDisassembler_Fail) { + *Size = 2; + return Result; + } + } + + // This is an invalid instruction. Claim that the Size is 2 bytes. Since + // nanoMIPS instructions have a minimum alignment of 2, the next 2 bytes + // could form a valid instruction. + *Size = 2; + return MCDisassembler_Fail; + } + + if (IsMicroMips) { + Result = readInstruction16(Bytes, BytesLen, Address, Size, + &Insn, IsBigEndian); + if (Result == MCDisassembler_Fail) + return MCDisassembler_Fail; + + if (IsMips32r6) { + // Calling the auto-generated decoder function for microMIPS32R6 + // 16-bit instructions. + Result = decodeInstruction_2(DecoderTableMicroMipsR616, + Instr, Insn, Address, + NULL); + if (Result != MCDisassembler_Fail) { + *Size = 2; + return Result; + } + } + + // Calling the auto-generated decoder function for microMIPS 16-bit + // instructions. + Result = decodeInstruction_2(DecoderTableMicroMips16, Instr, + Insn, Address, NULL); + if (Result != MCDisassembler_Fail) { + *Size = 2; + return Result; + } + + Result = readInstruction32(Bytes, BytesLen, Address, Size, + &Insn, IsBigEndian, IsMicroMips); + if (Result == MCDisassembler_Fail) + return MCDisassembler_Fail; + + if (IsMips32r6) { + // Calling the auto-generated decoder function. + Result = decodeInstruction_4(DecoderTableMicroMipsR632, + Instr, Insn, Address, + NULL); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + // Calling the auto-generated decoder function. + Result = decodeInstruction_4(DecoderTableMicroMips32, Instr, + Insn, Address, NULL); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + + if (IsFP64) { + Result = + decodeInstruction_4(DecoderTableMicroMipsFP6432, + Instr, Insn, Address, NULL); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + // This is an invalid instruction. Claim that the Size is 2 bytes. Since + // microMIPS instructions have a minimum alignment of 2, the next 2 bytes + // could form a valid instruction. The two bytes we rejected as an + // instruction could have actually beeen an inline constant pool that is + // unconditionally branched over. + *Size = 2; + return MCDisassembler_Fail; + } + + // Attempt to read the instruction so that we can attempt to decode it. If + // the buffer is not 4 bytes long, let the higher level logic figure out + // what to do with a size of zero and MCDisassembler::Fail. + Result = readInstruction32(Bytes, BytesLen, Address, Size, &Insn, IsBigEndian, + IsMicroMips); + if (Result == MCDisassembler_Fail) + return MCDisassembler_Fail; + + // The only instruction size for standard encoded MIPS. + *Size = 4; + + if (HasCOP3) { + Result = decodeInstruction_4(DecoderTableCOP3_32, Instr, Insn, + Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsMips32r6 && IsGP64) { + Result = decodeInstruction_4(DecoderTableMips32r6_64r6_GP6432, + Instr, Insn, Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsMips32r6 && IsPTR64) { + Result = decodeInstruction_4(DecoderTableMips32r6_64r6_PTR6432, + Instr, Insn, Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsMips32r6) { + Result = decodeInstruction_4(DecoderTableMips32r6_64r632, Instr, + Insn, Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsMips2 && IsPTR64) { + Result = decodeInstruction_4(DecoderTableMips32_64_PTR6432, + Instr, Insn, Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsCnMips) { + Result = decodeInstruction_4(DecoderTableCnMips32, Instr, Insn, + Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsCnMipsP) { + Result = decodeInstruction_4(DecoderTableCnMipsP32, Instr, Insn, + Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsGP64) { + Result = decodeInstruction_4(DecoderTableMips6432, Instr, Insn, + Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsFP64) { + Result = decodeInstruction_4(DecoderTableMipsFP6432, Instr, + Insn, Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + // Calling the auto-generated decoder function. + Result = decodeInstruction_4(DecoderTableMips32, Instr, Insn, Address, + NULL); + if (Result != MCDisassembler_Fail) + return Result; + + return MCDisassembler_Fail; +} + +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { return MCDisassembler_Fail; } -static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_GPR64RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 7) return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_GPRMM16RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 7) return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_GPRMM16ZeroRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) + unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 7) return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_GPRMM16MovePRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_GPR32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeGPRNM3RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - // if (static_cast(Decoder)->isGP64()) - if (Inst->csh->mode & CS_MODE_MIPS64) + if (RegNo > 7) + return MCDisassembler_Fail; + RegNo |= ((RegNo & 0x4) ^ 0x4) << 2; + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNMRARegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + MCOperand_CreateReg0(Inst, (Mips_RA_NM)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM3ZRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 7) + return MCDisassembler_Fail; + if (RegNo != 0) + RegNo |= ((RegNo & 0x4) ^ 0x4) << 2; + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM4RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + RegNo &= ~0x8; + RegNo += (RegNo < 4 ? 8 : 0); + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM4ZRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + RegNo &= ~0x8; + if (RegNo == 3) + RegNo = 0; + else + RegNo += (RegNo < 3 ? 8 : 0); + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM32NZRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo == 0) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM2R1RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + RegNo += 4; + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Reg + 1)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM1R1RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo != 0 && RegNo != 1) + return MCDisassembler_Fail; + RegNo += 4; + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit)) return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_FGR64RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_FGR32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_CCRRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 7) return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_FCCRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_FGRCCRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeMem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMem(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - int opcode = MCInst_getOpcode(Inst); + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - if (opcode == Mips_SC || opcode == Mips_SCD) { - MCOperand_CreateReg0(Inst, Reg); + if (MCInst_getOpcode(Inst) == Mips_SC || + MCInst_getOpcode(Inst) == Mips_SCD) + MCOperand_CreateReg0(Inst, (Reg)); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + + return MCDisassembler_Success; +} + +#define DEFINE_DecodeMemNM(Offbits, isSigned, rt) \ + static DecodeStatus CONCAT(DecodeMemNM, \ + CONCAT(Offbits, CONCAT(isSigned, rt)))( \ + MCInst * Inst, uint32_t Insn, uint64_t Address, \ + const void *Decoder) \ + { \ + int Offset = (Insn & ((1 << Offbits) - 1)); \ + if (isSigned) \ + Offset = SignExtend32((Offset), Offbits); \ + unsigned Base; \ +\ + switch (rt) { \ + case Mips_GPRNMGPRegClassID: \ + case Mips_GPRNMSPRegClassID: \ + Base = 0; \ + break; \ + case Mips_GPRNM3RegClassID: \ + Base = fieldFromInstruction_4(Insn, Offbits, 3); \ + break; \ + case Mips_GPRNM4RegClassID: \ + case Mips_GPRNM4ZRegClassID: \ +\ + break; \ + default: \ + Base = fieldFromInstruction_4(Insn, Offbits, 5); \ + } \ + Base = getReg(Inst, rt, Base); \ +\ + MCOperand_CreateReg0(Inst, (Base)); \ + MCOperand_CreateImm0(Inst, (Offset)); \ +\ + return MCDisassembler_Success; \ } +DEFINE_DecodeMemNM(6, 0, Mips_GPRNM3RegClassID); +DEFINE_DecodeMemNM(7, 0, Mips_GPRNMSPRegClassID); +DEFINE_DecodeMemNM(9, 0, Mips_GPRNMGPRegClassID); +DEFINE_DecodeMemNM(2, 0, Mips_GPRNM3RegClassID); +DEFINE_DecodeMemNM(3, 0, Mips_GPRNM3RegClassID); +DEFINE_DecodeMemNM(21, 0, Mips_GPRNMGPRegClassID); +DEFINE_DecodeMemNM(18, 0, Mips_GPRNMGPRegClassID); +DEFINE_DecodeMemNM(12, 0, Mips_GPRNM32RegClassID); +DEFINE_DecodeMemNM(9, 1, Mips_GPRNM32RegClassID); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); +static DecodeStatus DecodeMemZeroNM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + unsigned Base; + Base = fieldFromInstruction_4(Insn, 0, 5); + Base = getReg(Inst, Mips_GPRNM32RegClassID, Base); + MCOperand_CreateReg0(Inst, (Base)); return MCDisassembler_Success; } -static DecodeStatus DecodeCacheOp(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +#define DEFINE_DecodeMemNMRX(RegClass) \ + static DecodeStatus CONCAT(DecodeMemNMRX, RegClass)( \ + MCInst * Inst, uint32_t Insn, uint64_t Address, \ + const void *Decoder) \ + { \ + unsigned Offset; \ + unsigned Base; \ + Offset = fieldFromInstruction_4(Insn, 0, 5); \ + Base = fieldFromInstruction_4(Insn, 5, 5); \ +\ + Base = getReg(Inst, RegClass, Base); \ + Offset = getReg(Inst, RegClass, Offset); \ + MCOperand_CreateReg0(Inst, (Base)); \ + MCOperand_CreateReg0(Inst, (Offset)); \ +\ + return MCDisassembler_Success; \ + } +DEFINE_DecodeMemNMRX(Mips_GPRNM3RegClassID); +DEFINE_DecodeMemNMRX(Mips_GPRNM32RegClassID); + +static DecodeStatus DecodeMemNM4x4(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Hint = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int Offset = fieldFromInstruction_4(Insn, 0, 4); + unsigned Base; - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Base = getReg(Inst, Mips_GPRNM32RegClassID, + fieldFromInstruction_4(Insn, 4, 5) & ~0x8); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - MCOperand_CreateImm0(Inst, Hint); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeCacheOpMM(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemEVA(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0xfff, 12); - unsigned Base = fieldFromInstruction(Insn, 16, 5); - unsigned Hint = fieldFromInstruction(Insn, 21, 5); + int Offset = SignExtend32((Insn >> 7), 9); + unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - MCOperand_CreateImm0(Inst, Hint); + if (MCInst_getOpcode(Inst) == Mips_SCE) + MCOperand_CreateReg0(Inst, (Reg)); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeCacheOpR6(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +#include "MipsCP0RegisterMap.h" + +static DecodeStatus DecodeCOP0SelRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - int Offset = fieldFromInstruction(Insn, 7, 9); - unsigned Hint = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int Reg = COP0Map_getEncIndexMap(RegNo); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + if (Reg != -1) { + Reg = getReg(Inst, Mips_COP0SelRegClassID, Reg); + MCOperand_CreateReg0(Inst, (Reg)); + } else { + // Not a named register encoding - print numeric register and select value + switch (MCInst_getOpcode(Inst)) { + case Mips_MFC0Sel_NM: + MCInst_setOpcode(Inst, (Mips_MFC0_NM)); + break; + case Mips_MFHC0Sel_NM: + MCInst_setOpcode(Inst, (Mips_MFHC0_NM)); + break; + case Mips_MTC0Sel_NM: + MCInst_setOpcode(Inst, (Mips_MTC0_NM)); + break; + case Mips_MTHC0Sel_NM: + MCInst_setOpcode(Inst, (Mips_MTHC0_NM)); + break; + default: + assert(0 && "Unknown instruction!"); + } + Reg = getReg(Inst, Mips_COP0RegClassID, RegNo >> 5); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateImm0(Inst, (RegNo & 0x1f)); + } + return MCDisassembler_Success; +} - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - MCOperand_CreateImm0(Inst, Hint); +static DecodeStatus DecodeLoadByte15(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); + + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeSyncI(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeCacheOp(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Hint = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + MCOperand_CreateImm0(Inst, (Hint)); return MCDisassembler_Success; } -static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeCacheOpMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); - unsigned Reg = fieldFromInstruction(Insn, 6, 5); - unsigned Base = fieldFromInstruction(Insn, 11, 5); + int Offset = SignExtend32((Insn & 0xfff), 12); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + unsigned Hint = fieldFromInstruction_4(Insn, 21, 5); - Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - // MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + MCOperand_CreateImm0(Inst, (Hint)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePrefeOpMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + int Offset = SignExtend32((Insn & 0x1ff), 9); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + unsigned Hint = fieldFromInstruction_4(Insn, 21, 5); + + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + MCOperand_CreateImm0(Inst, (Hint)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) +{ + int Offset = SignExtend32((Insn >> 7), 9); + unsigned Hint = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); + + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + MCOperand_CreateImm0(Inst, (Hint)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSyncI(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); + + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSyncI_MM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSynciR6(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + int Immediate = SignExtend32((Insn & 0xffff), 16); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Immediate)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128Mem(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + int Offset = SignExtend32((fieldFromInstruction_4(Insn, 16, 10)), 10); + unsigned Reg = fieldFromInstruction_4(Insn, 6, 5); + unsigned Base = fieldFromInstruction_4(Insn, 11, 5); + + Reg = getReg(Inst, Mips_MSA128BRegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); // The immediate field of an LD/ST instruction is scaled which means it must // be multiplied (when decoding) by the size (in bytes) of the instructions' @@ -1081,714 +2227,1133 @@ static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, // .h - 2 bytes // .w - 4 bytes // .d - 8 bytes - switch(MCInst_getOpcode(Inst)) { - default: - //assert (0 && "Unexpected instruction"); - return MCDisassembler_Fail; - break; - case Mips_LD_B: - case Mips_ST_B: - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_LD_H: - case Mips_ST_H: - MCOperand_CreateImm0(Inst, Offset * 2); - break; - case Mips_LD_W: - case Mips_ST_W: - MCOperand_CreateImm0(Inst, Offset * 4); - break; - case Mips_LD_D: - case Mips_ST_D: - MCOperand_CreateImm0(Inst, Offset * 8); - break; + switch (MCInst_getOpcode(Inst)) { + default: + + return MCDisassembler_Fail; + break; + case Mips_LD_B: + case Mips_ST_B: + MCOperand_CreateImm0(Inst, (Offset)); + break; + case Mips_LD_H: + case Mips_ST_H: + MCOperand_CreateImm0(Inst, (Offset * 2)); + break; + case Mips_LD_W: + case Mips_ST_W: + MCOperand_CreateImm0(Inst, (Offset * 4)); + break; + case Mips_LD_D: + case Mips_ST_D: + MCOperand_CreateImm0(Inst, (Offset * 8)); + break; } return MCDisassembler_Success; } -static DecodeStatus DecodeMemMMImm4(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemMMImm4(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { unsigned Offset = Insn & 0xf; - unsigned Reg = fieldFromInstruction(Insn, 7, 3); - unsigned Base = fieldFromInstruction(Insn, 4, 3); + unsigned Reg = fieldFromInstruction_4(Insn, 7, 3); + unsigned Base = fieldFromInstruction_4(Insn, 4, 3); switch (MCInst_getOpcode(Inst)) { - case Mips_LBU16_MM: - case Mips_LHU16_MM: - case Mips_LW16_MM: - if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - break; - case Mips_SB16_MM: - case Mips_SH16_MM: - case Mips_SW16_MM: - if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - break; + case Mips_LBU16_MM: + case Mips_LHU16_MM: + case Mips_LW16_MM: + if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + break; + case Mips_SB16_MM: + case Mips_SB16_MMR6: + case Mips_SH16_MM: + case Mips_SH16_MMR6: + case Mips_SW16_MM: + case Mips_SW16_MMR6: + if (DecodeGPRMM16ZeroRegisterClass( + Inst, Reg, Address, Decoder) == MCDisassembler_Fail) + return MCDisassembler_Fail; + break; } - if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) - == MCDisassembler_Fail) + if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) == + MCDisassembler_Fail) return MCDisassembler_Fail; switch (MCInst_getOpcode(Inst)) { - case Mips_LBU16_MM: - if (Offset == 0xf) - MCOperand_CreateImm0(Inst, -1); - else - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_SB16_MM: - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_LHU16_MM: - case Mips_SH16_MM: - MCOperand_CreateImm0(Inst, Offset << 1); - break; - case Mips_LW16_MM: - case Mips_SW16_MM: - MCOperand_CreateImm0(Inst, Offset << 2); - break; + case Mips_LBU16_MM: + if (Offset == 0xf) + MCOperand_CreateImm0(Inst, (-1)); + else + MCOperand_CreateImm0(Inst, (Offset)); + break; + case Mips_SB16_MM: + case Mips_SB16_MMR6: + MCOperand_CreateImm0(Inst, (Offset)); + break; + case Mips_LHU16_MM: + case Mips_SH16_MM: + case Mips_SH16_MMR6: + MCOperand_CreateImm0(Inst, (Offset << 1)); + break; + case Mips_LW16_MM: + case Mips_SW16_MM: + case Mips_SW16_MMR6: + MCOperand_CreateImm0(Inst, (Offset << 2)); + break; } return MCDisassembler_Success; } -static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { unsigned Offset = Insn & 0x1F; - unsigned Reg = fieldFromInstruction(Insn, 5, 5); + unsigned Reg = fieldFromInstruction_4(Insn, 5, 5); - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Mips_SP); - MCOperand_CreateImm0(Inst, Offset << 2); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Mips_SP)); + MCOperand_CreateImm0(Inst, (Offset << 2)); return MCDisassembler_Success; } -static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { unsigned Offset = Insn & 0x7F; - unsigned Reg = fieldFromInstruction(Insn, 7, 3); + unsigned Reg = fieldFromInstruction_4(Insn, 7, 3); - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Mips_GP); - MCOperand_CreateImm0(Inst, Offset << 2); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Mips_GP)); + MCOperand_CreateImm0(Inst, (Offset << 2)); return MCDisassembler_Success; } -static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0xf, 4); + int Offset; + switch (MCInst_getOpcode(Inst)) { + case Mips_LWM16_MMR6: + case Mips_SWM16_MMR6: + Offset = fieldFromInstruction_4(Insn, 4, 4); + break; + default: + Offset = SignExtend32((Insn & 0xf), 4); + break; + } - if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail) + if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == + MCDisassembler_Fail) return MCDisassembler_Fail; - MCOperand_CreateReg0(Inst, Mips_SP); - MCOperand_CreateImm0(Inst, Offset * 4); + MCOperand_CreateReg0(Inst, (Mips_SP)); + MCOperand_CreateImm0(Inst, (Offset << 2)); return MCDisassembler_Success; } -static DecodeStatus DecodeMemMMImm12(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemMMImm9(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Offset = SignExtend32(Insn & 0x0fff, 12); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); - unsigned Base = fieldFromInstruction(Insn, 16, 5); + int Offset = SignExtend32((Insn & 0x1ff), 9); + unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + if (MCInst_getOpcode(Inst) == Mips_SCE_MM || + MCInst_getOpcode(Inst) == Mips_SC_MMR6) + MCOperand_CreateReg0(Inst, (Reg)); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMImm12(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + int Offset = SignExtend32((Insn & 0x0fff), 12); + unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); switch (MCInst_getOpcode(Inst)) { - case Mips_SWM32_MM: - case Mips_LWM32_MM: - if (DecodeRegListOperand(Inst, Insn, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_SC_MM: - MCOperand_CreateReg0(Inst, Reg); - // fallthrough - default: - MCOperand_CreateReg0(Inst, Reg); - if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM) - MCOperand_CreateReg0(Inst, Reg + 1); + case Mips_SWM32_MM: + case Mips_LWM32_MM: + if (DecodeRegListOperand(Inst, Insn, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + break; + case Mips_SC_MM: + MCOperand_CreateReg0(Inst, (Reg)); + // fall through + default: + MCOperand_CreateReg0(Inst, (Reg)); + if (MCInst_getOpcode(Inst) == Mips_LWP_MM || + MCInst_getOpcode(Inst) == Mips_SWP_MM) + MCOperand_CreateReg0(Inst, (Reg + 1)); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); } return MCDisassembler_Success; } -static DecodeStatus DecodeMemMMImm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemMMImm16(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); - unsigned Base = fieldFromInstruction(Insn, 16, 5); + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeFMem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeFMem(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_FGR64RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeFMem2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeFMemMMR2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + // This function is the same as DecodeFMem but with the Reg and Base fields + // swapped according to microMIPS spec. + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); - Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_FGR64RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeFMem3(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeFMem2(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_COP2RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeFMem3(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0x07ff, 11); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 11, 5); + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_COP3RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9); - unsigned Rt = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int Offset = SignExtend32((Insn & 0x07ff), 11); + unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 11, 5); - Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_COP2RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFMemCop2MMR6(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + int Offset = SignExtend32((Insn & 0x07ff), 11); + unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + + Reg = getReg(Inst, Mips_COP2RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + int64_t Offset = SignExtend64(((Insn >> 7) & 0x1ff), 9); + unsigned Rt = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); + + Rt = getReg(Inst, Mips_GPR32RegClassID, Rt); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); if (MCInst_getOpcode(Inst) == Mips_SC_R6 || - MCInst_getOpcode(Inst) == Mips_SCD_R6) { - MCOperand_CreateReg0(Inst, Rt); + MCInst_getOpcode(Inst) == Mips_SCD_R6) { + MCOperand_CreateReg0(Inst, (Rt)); } - MCOperand_CreateReg0(Inst, Rt); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Rt)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { // Currently only hardware register 29 is supported. if (RegNo != 29) - return MCDisassembler_Fail; - - MCOperand_CreateReg0(Inst, Mips_HWR29); - + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, (Mips_HWR29)); return MCDisassembler_Success; } -static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 30 || RegNo % 2) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_AFGR64RegClassID, RegNo / 2); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo >= 4) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_ACC64DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo >= 4) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_HI32DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo >= 4) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_LO32DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_MSA128BRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_MSA128HRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_MSA128WRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_MSA128DRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 7) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_MSACtrlRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeCOP0RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_COP0RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeBranchTarget(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4; - MCOperand_CreateImm0(Inst, TargetAddress); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeJumpTarget(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF); - MCOperand_CreateImm0(Inst, TargetAddress); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget21(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 21) * 4; - - MCOperand_CreateImm0(Inst, BranchOffset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget26(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 26) * 4; - - MCOperand_CreateImm0(Inst, BranchOffset); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 7) * 2; - MCOperand_CreateImm0(Inst, BranchOffset); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 10) * 2; - MCOperand_CreateImm0(Inst, BranchOffset); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 16) * 2; - MCOperand_CreateImm0(Inst, BranchOffset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; - MCOperand_CreateImm0(Inst, JumpOffset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) -{ - if (Value == 0) - MCOperand_CreateImm0(Inst, 1); - else if (Value == 0x7) - MCOperand_CreateImm0(Inst, -1); - else - MCOperand_CreateImm0(Inst, Value << 2); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, Value << 2); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeLiSimm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) -{ - if (Value == 0x7F) - MCOperand_CreateImm0(Inst, -1); - else - MCOperand_CreateImm0(Inst, Value); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm4(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Value, 4)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeLSAImm(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - // We add one to the immediate field as it was encoded as 'imm - 1'. - MCOperand_CreateImm0(Inst, Insn + 1); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeInsSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - // First we need to grab the pos(lsb) from MCInst. - int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2)); - int Size = (int) Insn - Pos + 1; - MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeExtSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Size = (int)Insn + 1; - - MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - int32_t DecodedValue; - - switch (Insn) { - case 0: DecodedValue = 256; break; - case 1: DecodedValue = 257; break; - case 510: DecodedValue = -258; break; - case 511: DecodedValue = -257; break; - default: DecodedValue = SignExtend32(Insn, 9); break; - } - MCOperand_CreateImm0(Inst, DecodedValue * 4); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - // Insn must be >= 0, since it is unsigned that condition is always true. - // assert(Insn < 16); - int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, - 255, 32768, 65535}; - - if (Insn >= 16) + if (RegNo > 31) return MCDisassembler_Fail; - MCOperand_CreateImm0(Inst, DecodedValues[Insn]); - + unsigned Reg = getReg(Inst, Mips_COP2RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeBranchTarget(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder) { - MCOperand_CreateImm0(Inst, Insn << 2); - + int32_t BranchOffset = (SignExtend32((Offset), 16) * 4) + 4; + MCOperand_CreateImm0(Inst, (BranchOffset)); return MCDisassembler_Success; } -static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBranchTarget1SImm16(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder) { - unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, - Mips_S6, Mips_FP}; + int32_t BranchOffset = (SignExtend32((Offset), 16) * 2); + MCOperand_CreateImm0(Inst, (BranchOffset)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeJumpTarget(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + unsigned JumpOffset = fieldFromInstruction_4(Insn, 0, 26) << 2; + MCOperand_CreateImm0(Inst, (JumpOffset)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget21(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder) +{ + int32_t BranchOffset = SignExtend32((Offset), 21) * 4 + 4; + + MCOperand_CreateImm0(Inst, (BranchOffset)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget21MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder) +{ + int32_t BranchOffset = SignExtend32((Offset), 21) * 4 + 4; + + MCOperand_CreateImm0(Inst, (BranchOffset)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget26(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder) +{ + int32_t BranchOffset = SignExtend32((Offset), 26) * 4 + 4; + + MCOperand_CreateImm0(Inst, (BranchOffset)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder) +{ + int32_t BranchOffset = SignExtend32((Offset << 1), 8); + MCOperand_CreateImm0(Inst, (BranchOffset)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder) +{ + int32_t BranchOffset = SignExtend32((Offset << 1), 11); + MCOperand_CreateImm0(Inst, (BranchOffset)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder) +{ + int32_t BranchOffset = SignExtend32((Offset), 16) * 2 + 4; + MCOperand_CreateImm0(Inst, (BranchOffset)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget26MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder) +{ + int32_t BranchOffset = SignExtend32((Offset << 1), 27); + + MCOperand_CreateImm0(Inst, (BranchOffset)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + unsigned JumpOffset = fieldFromInstruction_4(Insn, 0, 26) << 1; + MCOperand_CreateImm0(Inst, (JumpOffset)); + return MCDisassembler_Success; +} + +#define DEFINE_DecodeBranchTargetNM(Bits) \ + static DecodeStatus CONCAT(DecodeBranchTargetNM, Bits)( \ + MCInst * Inst, unsigned Offset, uint64_t Address, \ + const void *Decoder) \ + { \ + uint32_t InsnSize = (Bits <= 10) ? 2 : 4; \ + int32_t BranchOffset = \ + SignExtend32((Offset), Bits + 1) + InsnSize; \ +\ + MCOperand_CreateImm0(Inst, (BranchOffset)); \ + return MCDisassembler_Success; \ + } +DEFINE_DecodeBranchTargetNM(10); +DEFINE_DecodeBranchTargetNM(7); +DEFINE_DecodeBranchTargetNM(21); +DEFINE_DecodeBranchTargetNM(25); +DEFINE_DecodeBranchTargetNM(14); +DEFINE_DecodeBranchTargetNM(11); +DEFINE_DecodeBranchTargetNM(5); + +static DecodeStatus DecodeJumpTargetXMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + unsigned JumpOffset = fieldFromInstruction_4(Insn, 0, 26) << 2; + MCOperand_CreateImm0(Inst, (JumpOffset)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder) +{ + if (Value == 0) + MCOperand_CreateImm0(Inst, (1)); + else if (Value == 0x7) + MCOperand_CreateImm0(Inst, (-1)); + else + MCOperand_CreateImm0(Inst, (Value << 2)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLi16Imm(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder) +{ + if (Value == 0x7F) + MCOperand_CreateImm0(Inst, (-1)); + else + MCOperand_CreateImm0(Inst, (Value)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOOL16BEncodedField(MCInst *Inst, unsigned Value, + uint64_t Address, + const void *Decoder) +{ + MCOperand_CreateImm0(Inst, (Value == 0x0 ? 8 : Value)); + return MCDisassembler_Success; +} + +#define DEFINE_DecodeUImmWithOffsetAndScale(Bits, Offset, Scale) \ + static DecodeStatus CONCAT(DecodeUImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, Scale)))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder) \ + { \ + Value &= ((1 << Bits) - 1); \ + Value *= Scale; \ + MCOperand_CreateImm0(Inst, (Value + Offset)); \ + return MCDisassembler_Success; \ + } +DEFINE_DecodeUImmWithOffsetAndScale(5, 0, 4); +DEFINE_DecodeUImmWithOffsetAndScale(6, 0, 4); +DEFINE_DecodeUImmWithOffsetAndScale(2, 1, 1); +DEFINE_DecodeUImmWithOffsetAndScale(5, 1, 1); +DEFINE_DecodeUImmWithOffsetAndScale(8, 0, 1); +DEFINE_DecodeUImmWithOffsetAndScale(18, 0, 1); +DEFINE_DecodeUImmWithOffsetAndScale(21, 0, 1); + +#define DEFINE_DecodeSImmWithOffsetAndScale(Bits, Offset, ScaleBy) \ + static DecodeStatus CONCAT(DecodeSImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, ScaleBy)))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder) \ + { \ + int32_t Imm = SignExtend32((Value), Bits) * ScaleBy; \ + MCOperand_CreateImm0(Inst, (Imm + Offset)); \ + return MCDisassembler_Success; \ + } + +#define DEFINE_DecodeSImmWithOffsetAndScale_2(Bits, Offset) DEFINE_DecodeSImmWithOffsetAndScale(Bits, Offset, 1) +#define DEFINE_DecodeSImmWithOffsetAndScale_3(Bits) DEFINE_DecodeSImmWithOffsetAndScale(Bits, 0, 1) + +DEFINE_DecodeSImmWithOffsetAndScale_3(16); +DEFINE_DecodeSImmWithOffsetAndScale_3(10); +DEFINE_DecodeSImmWithOffsetAndScale_3(4); +DEFINE_DecodeSImmWithOffsetAndScale_3(6); +DEFINE_DecodeSImmWithOffsetAndScale_3(32); + +static DecodeStatus DecodeInsSize(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + // First we need to grab the pos(lsb) from MCInst. + // This function only handles the 32 bit variants of ins, as dins + // variants are handled differently. + int Pos = MCOperand_getImm(MCInst_getOperand(Inst, (2))); + int Size = (int)Insn - Pos + 1; + MCOperand_CreateImm0(Inst, (SignExtend32((Size), 16))); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, (SignExtend32((Insn), 19) * 4)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, (SignExtend32((Insn), 18) * 8)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSimm9SP(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + int32_t DecodedValue; + switch (Insn) { + case 0: + DecodedValue = 256; + break; + case 1: + DecodedValue = 257; + break; + case 510: + DecodedValue = -258; + break; + case 511: + DecodedValue = -257; + break; + default: + DecodedValue = SignExtend32((Insn), 9); + break; + } + MCOperand_CreateImm0(Inst, (DecodedValue * 4)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeANDI16Imm(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + // Insn must be >= 0, since it is unsigned that condition is always true. + + int32_t DecodedValues[] = { 128, 1, 2, 3, 4, 7, 8, 15, + 16, 31, 32, 63, 64, 255, 32768, 65535 }; + MCOperand_CreateImm0(Inst, (DecodedValues[Insn])); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRegListOperand(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + unsigned Regs[] = { Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, + Mips_S5, Mips_S6, Mips_S7, Mips_FP }; unsigned RegNum; - unsigned int i; - unsigned RegLst = fieldFromInstruction(Insn, 21, 5); + unsigned RegLst = fieldFromInstruction_4(Insn, 21, 5); + // Empty register lists are not allowed. if (RegLst == 0) return MCDisassembler_Fail; RegNum = RegLst & 0xf; - for (i = 0; i < MIN(RegNum, ARR_SIZE(Regs)); i++) - MCOperand_CreateReg0(Inst, Regs[i]); + + // RegLst values 10-15, and 26-31 are reserved. + if (RegNum > 9) + return MCDisassembler_Fail; + + for (unsigned i = 0; i < RegNum; i++) + MCOperand_CreateReg0(Inst, (Regs[i])); if (RegLst & 0x10) - MCOperand_CreateReg0(Inst, Mips_RA); + MCOperand_CreateReg0(Inst, (Mips_RA)); return MCDisassembler_Success; } -static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeRegListOperand16(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) { - unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3}; - unsigned RegLst = fieldFromInstruction(Insn, 4, 2); + unsigned Regs[] = { Mips_S0, Mips_S1, Mips_S2, Mips_S3 }; + unsigned RegLst; + switch (MCInst_getOpcode(Inst)) { + default: + RegLst = fieldFromInstruction_4(Insn, 4, 2); + break; + case Mips_LWM16_MMR6: + case Mips_SWM16_MMR6: + RegLst = fieldFromInstruction_4(Insn, 8, 2); + break; + } unsigned RegNum = RegLst & 0x3; - unsigned int i; - for (i = 0; i <= RegNum; i++) - MCOperand_CreateReg0(Inst, Regs[i]); + for (unsigned i = 0; i <= RegNum; i++) + MCOperand_CreateReg0(Inst, (Regs[i])); - MCOperand_CreateReg0(Inst, Mips_RA); + MCOperand_CreateReg0(Inst, (Mips_RA)); return MCDisassembler_Success; } -static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeMovePOperands(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - unsigned RegPair = fieldFromInstruction(Insn, 7, 3); + unsigned RegPair = fieldFromInstruction_4(Insn, 7, 3); + if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + unsigned RegRs; + if (Inst->csh->mode & CS_MODE_MIPS32R6) + RegRs = fieldFromInstruction_4(Insn, 0, 2) | + (fieldFromInstruction_4(Insn, 3, 1) << 2); + else + RegRs = fieldFromInstruction_4(Insn, 1, 3); + if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + unsigned RegRt = fieldFromInstruction_4(Insn, 4, 3); + if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned RegPair, + uint64_t Address, const void *Decoder) +{ switch (RegPair) { - default: - return MCDisassembler_Fail; - case 0: - MCOperand_CreateReg0(Inst, Mips_A1); - MCOperand_CreateReg0(Inst, Mips_A2); - break; - case 1: - MCOperand_CreateReg0(Inst, Mips_A1); - MCOperand_CreateReg0(Inst, Mips_A3); - break; - case 2: - MCOperand_CreateReg0(Inst, Mips_A2); - MCOperand_CreateReg0(Inst, Mips_A3); - break; - case 3: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_S5); - break; - case 4: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_S6); - break; - case 5: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_A1); - break; - case 6: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_A2); - break; - case 7: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_A3); - break; + default: + return MCDisassembler_Fail; + case 0: + MCOperand_CreateReg0(Inst, (Mips_A1)); + MCOperand_CreateReg0(Inst, (Mips_A2)); + break; + case 1: + MCOperand_CreateReg0(Inst, (Mips_A1)); + MCOperand_CreateReg0(Inst, (Mips_A3)); + break; + case 2: + MCOperand_CreateReg0(Inst, (Mips_A2)); + MCOperand_CreateReg0(Inst, (Mips_A3)); + break; + case 3: + MCOperand_CreateReg0(Inst, (Mips_A0)); + MCOperand_CreateReg0(Inst, (Mips_S5)); + break; + case 4: + MCOperand_CreateReg0(Inst, (Mips_A0)); + MCOperand_CreateReg0(Inst, (Mips_S6)); + break; + case 5: + MCOperand_CreateReg0(Inst, (Mips_A0)); + MCOperand_CreateReg0(Inst, (Mips_A1)); + break; + case 6: + MCOperand_CreateReg0(Inst, (Mips_A0)); + MCOperand_CreateReg0(Inst, (Mips_A2)); + break; + case 7: + MCOperand_CreateReg0(Inst, (Mips_A0)); + MCOperand_CreateReg0(Inst, (Mips_A3)); + break; } return MCDisassembler_Success; } -static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4); + MCOperand_CreateImm0(Inst, (SignExtend32((Insn << 2), 25))); return MCDisassembler_Success; } -#endif +static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) +{ + // We have: + // 0b000111 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BGTZALC_MMR6 if rs == 0 && rt != 0 + // BLTZALC_MMR6 if rs != 0 && rs == rt + // BLTUC_MMR6 if rs != 0 && rs != rt + + uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + uint32_t Imm = 0; + bool HasRs = false; + bool HasRt = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) { + MCInst_setOpcode(MI, (Mips_BGTZALC_MMR6)); + HasRt = true; + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } else if (Rs == Rt) { + MCInst_setOpcode(MI, (Mips_BLTZALC_MMR6)); + HasRs = true; + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } else { + MCInst_setOpcode(MI, (Mips_BLTUC_MMR6)); + HasRs = true; + HasRt = true; + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 4 + + 4; + } + + if (HasRs) + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + + if (HasRt) + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) +{ + // We have: + // 0b000110 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BLEZALC_MMR6 if rs == 0 && rt != 0 + // BGEZALC_MMR6 if rs == rt && rt != 0 + // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 + + uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + uint32_t Imm = 0; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) { + MCInst_setOpcode(MI, (Mips_BLEZALC_MMR6)); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } else if (Rs == Rt) { + MCInst_setOpcode(MI, (Mips_BGEZALC_MMR6)); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } else { + HasRs = true; + MCInst_setOpcode(MI, (Mips_BGEUC_MMR6)); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 4 + + 4; + } + + if (HasRs) + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} + +// This instruction does not have a working decoder, and needs to be +// fixed. This "fixme" function was introduced to keep the backend compiling, +// while making changes to tablegen code. +static DecodeStatus DecodeFIXMEInstruction(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) +{ + return MCDisassembler_Fail; +} + +static DecodeStatus DecodeImmM1To126(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder) +{ + if (Value == 127) + MCOperand_CreateImm0(Inst, (-1)); + else + MCOperand_CreateImm0(Inst, (Value)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeUImm4Mask(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder) +{ + if (Value == 12) + MCOperand_CreateImm0(Inst, (0xff)); + else if (Value == 13) + MCOperand_CreateImm0(Inst, (0xffff)); + else + MCOperand_CreateImm0(Inst, (Value)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeUImm3Shift(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder) +{ + if (Value == 0) + MCOperand_CreateImm0(Inst, (8)); + else + MCOperand_CreateImm0(Inst, (Value)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeNMRegListOperand(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) +{ + unsigned RegStart = fieldFromInstruction_4(Insn, 5, 5); + unsigned RegCount = fieldFromInstruction_4(Insn, 1, 4); + unsigned GP_bit = fieldFromInstruction_4(Insn, 0, 1); + unsigned i; + unsigned RegNo; + + MCOperand_CreateReg0( + Inst, (getReg(Inst, Mips_GPRNM32RegClassID, RegStart))); + for (i = RegStart + 1; i < RegStart + RegCount; i++) { + if (i == RegStart + RegCount - 1 && GP_bit) + RegNo = 28; + else if (i > 31) + RegNo = 16 + (i % 32); // $ra+1 wraps to $s0 + else + RegNo = i; + MCOperand_CreateReg0( + Inst, (getReg(Inst, Mips_GPRNM32RegClassID, RegNo))); + } + return MCDisassembler_Success; +} + +static DecodeStatus DecodeNMRegList16Operand(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) +{ + unsigned RegStart = 30 + fieldFromInstruction_4(Insn, 4, 1); + unsigned RegCount = fieldFromInstruction_4(Insn, 0, 4); + // Re-encode the parameters for 32-bit instruction operand + // and call it's decoder + return DecodeNMRegListOperand(Inst, (RegStart << 5) | (RegCount << 1), + Address, Decoder); +} + +static DecodeStatus DecodeNegImm12(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + int Imm = fieldFromInstruction_4(Insn, 0, 12); + + MCOperand_CreateImm0(Inst, (-Imm)); + return MCDisassembler_Success; +} + +#define DEFINE_DecodeSImmWithReg(Bits, Offset, Scale, RegNum) \ + static DecodeStatus CONCAT( \ + DecodeSImmWithReg, \ + CONCAT(Bits, CONCAT(Offset, CONCAT(Scale, RegNum))))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder) \ + { \ + MCOperand_CreateReg0(Inst, (RegNum)); \ + return CONCAT(DecodeSImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, Scale)))( \ + Inst, Value, Address, Decoder); \ + } +DEFINE_DecodeSImmWithReg(32, 0, 1, Mips_GP_NM); + +#define DEFINE_DecodeUImmWithReg(Bits, Offset, Scale, RegNum) \ + static DecodeStatus CONCAT( \ + DecodeUImmWithReg, \ + CONCAT(Bits, CONCAT(Offset, CONCAT(Scale, RegNum))))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder) \ + { \ + MCOperand_CreateReg0(Inst, (RegNum)); \ + return CONCAT(DecodeUImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, Scale)))( \ + Inst, Value, Address, Decoder); \ + } +DEFINE_DecodeUImmWithReg(8, 0, 1, Mips_SP_NM); +DEFINE_DecodeUImmWithReg(21, 0, 1, Mips_GP_NM); +DEFINE_DecodeUImmWithReg(18, 0, 1, Mips_GP_NM); + +static DecodeStatus DecodeSImm32s12(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + uint64_t Imm = (Insn) << 12; + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +#define DEFINE_DecodeAddressPCRelNM(Bits) \ + static DecodeStatus CONCAT(DecodeAddressPCRelNM, Bits)( \ + MCInst * Inst, unsigned Offset, uint64_t Address, \ + const void *Decoder) \ + { \ + uint32_t InsnSize = Bits == 32 ? 6 : 4; \ + int32_t BranchOffset = \ + SignExtend32((Offset), Bits) + InsnSize; \ +\ + MCOperand_CreateImm0(Inst, (BranchOffset)); \ + return MCDisassembler_Success; \ + } +DEFINE_DecodeAddressPCRelNM(22); +DEFINE_DecodeAddressPCRelNM(32); + +static DecodeStatus DecodeBranchConflictNM(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) +{ + unsigned Rt = fieldFromInstruction_4(Insn, 7, 3); + unsigned Rs = fieldFromInstruction_4(Insn, 4, 3); + unsigned Offset = fieldFromInstruction_4(Insn, 0, 4) << 1; + if (Rs < Rt) + MCInst_setOpcode(Inst, (Mips_BEQC16_NM)); + else + MCInst_setOpcode(Inst, (Mips_BNEC16_NM)); + if (DecodeGPRNM3RegisterClass(Inst, Rt, Address, Decoder) == + MCDisassembler_Success && + DecodeGPRNM3RegisterClass(Inst, Rs, Address, Decoder) == + MCDisassembler_Success) + return CONCAT(DecodeBranchTargetNM, 5)(Inst, Offset, Address, + Decoder); + else + return MCDisassembler_Fail; +} + +DecodeStatus Mips_LLVM_getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes, + size_t BytesLen, uint64_t Address, SStream *CStream) +{ + return getInstruction(Instr, Size, Bytes, BytesLen, Address, CStream); +} diff --git a/arch/Mips/MipsDisassembler.h b/arch/Mips/MipsDisassembler.h index 961c5f1ae..3c9c2c892 100644 --- a/arch/Mips/MipsDisassembler.h +++ b/arch/Mips/MipsDisassembler.h @@ -10,7 +10,6 @@ void Mips_init(MCRegisterInfo *MRI); -bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, void *info); +bool Mips_getFeatureBits(unsigned int mode, unsigned int feature); #endif diff --git a/arch/Mips/MipsGenAsmWriter.inc b/arch/Mips/MipsGenAsmWriter.inc index 49fb8f5e1..45625228c 100644 --- a/arch/Mips/MipsGenAsmWriter.inc +++ b/arch/Mips/MipsGenAsmWriter.inc @@ -1,1390 +1,1949 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Assembly Writer Source Fragment *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ -/// printInstruction - This method is automatically generated by tablegen +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#include +#include + +/// getMnemonic - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) -{ - static const uint32_t OpInfo[] = { +static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ "ins \t\0" + /* 6 */ "dmfc0\t\0" + /* 13 */ "dmfgc0\t\0" + /* 21 */ "mfhgc0\t\0" + /* 29 */ "mthgc0\t\0" + /* 37 */ "dmtgc0\t\0" + /* 45 */ "mfhc0\t\0" + /* 52 */ "mthc0\t\0" + /* 59 */ "dmtc0\t\0" + /* 66 */ "vmm0\t\0" + /* 72 */ "mtm0\t\0" + /* 78 */ "mtp0\t\0" + /* 84 */ "bbit0\t\0" + /* 91 */ "ldc1\t\0" + /* 97 */ "sdc1\t\0" + /* 103 */ "cfc1\t\0" + /* 109 */ "dmfc1\t\0" + /* 116 */ "mfhc1\t\0" + /* 123 */ "mthc1\t\0" + /* 130 */ "ctc1\t\0" + /* 136 */ "dmtc1\t\0" + /* 143 */ "lwc1\t\0" + /* 149 */ "swc1\t\0" + /* 155 */ "ldxc1\t\0" + /* 162 */ "sdxc1\t\0" + /* 169 */ "luxc1\t\0" + /* 176 */ "suxc1\t\0" + /* 183 */ "lwxc1\t\0" + /* 190 */ "swxc1\t\0" + /* 197 */ "mtm1\t\0" + /* 203 */ "mtp1\t\0" + /* 209 */ "bbit1\t\0" + /* 216 */ "bbit032\t\0" + /* 225 */ "bbit132\t\0" + /* 234 */ "dsra32\t\0" + /* 242 */ "bposge32\t\0" + /* 252 */ "dsll32\t\0" + /* 260 */ "dsrl32\t\0" + /* 268 */ "lwm32\t\0" + /* 275 */ "swm32\t\0" + /* 282 */ "drotr32\t\0" + /* 291 */ "cins32\t\0" + /* 299 */ "exts32\t\0" + /* 307 */ "ldc2\t\0" + /* 313 */ "sdc2\t\0" + /* 319 */ "cfc2\t\0" + /* 325 */ "dmfc2\t\0" + /* 332 */ "mfhc2\t\0" + /* 339 */ "mthc2\t\0" + /* 346 */ "ctc2\t\0" + /* 352 */ "dmtc2\t\0" + /* 359 */ "lwc2\t\0" + /* 365 */ "swc2\t\0" + /* 371 */ "mtm2\t\0" + /* 377 */ "mtp2\t\0" + /* 383 */ "addiur2\t\0" + /* 392 */ "ldc3\t\0" + /* 398 */ "sdc3\t\0" + /* 404 */ "lwc3\t\0" + /* 410 */ "swc3\t\0" + /* 416 */ "addius5\t\0" + /* 425 */ "sb16\t\0" + /* 431 */ "bc16\t\0" + /* 437 */ "jrc16\t\0" + /* 444 */ "bnezc16\t\0" + /* 453 */ "beqzc16\t\0" + /* 462 */ "and16\t\0" + /* 469 */ "move16\t\0" + /* 477 */ "sh16\t\0" + /* 483 */ "andi16\t\0" + /* 491 */ "mfhi16\t\0" + /* 499 */ "li16\t\0" + /* 505 */ "break16\t\0" + /* 514 */ "sll16\t\0" + /* 521 */ "srl16\t\0" + /* 528 */ "lwm16\t\0" + /* 535 */ "swm16\t\0" + /* 542 */ "mflo16\t\0" + /* 550 */ "sdbbp16\t\0" + /* 559 */ "jr16\t\0" + /* 565 */ "xor16\t\0" + /* 572 */ "jalrs16\t\0" + /* 581 */ "not16\t\0" + /* 588 */ "lbu16\t\0" + /* 595 */ "subu16\t\0" + /* 603 */ "addu16\t\0" + /* 611 */ "lhu16\t\0" + /* 618 */ "lw16\t\0" + /* 624 */ "sw16\t\0" + /* 630 */ "bnez16\t\0" + /* 638 */ "beqz16\t\0" + /* 646 */ "andi[32]\t\0" + /* 656 */ "addiu[32]\t\0" + /* 667 */ "addiu[r2]\t\0" + /* 678 */ "addiu[rs5]\t\0" + /* 690 */ "balc[16]\t\0" + /* 700 */ "andi[16]\t\0" + /* 710 */ "li[48]\t\0" + /* 718 */ "addiu[48]\t\0" + /* 729 */ "addiu[gp48]\t\0" + /* 742 */ "addiu[gp.b]\t\0" + /* 755 */ "addiu[neg]\t\0" + /* 767 */ "addiu[r1.sp]\t\0" + /* 781 */ "addiu[gp.w]\t\0" + /* 794 */ "saa\t\0" + /* 799 */ "preceu.ph.qbla\t\0" + /* 815 */ "precequ.ph.qbla\t\0" + /* 832 */ "dla\t\0" + /* 837 */ "preceu.ph.qbra\t\0" + /* 853 */ "precequ.ph.qbra\t\0" + /* 870 */ "dsra\t\0" + /* 876 */ "dlsa\t\0" + /* 882 */ "cfcmsa\t\0" + /* 890 */ "ctcmsa\t\0" + /* 898 */ "add_a.b\t\0" + /* 907 */ "min_a.b\t\0" + /* 916 */ "adds_a.b\t\0" + /* 926 */ "max_a.b\t\0" + /* 935 */ "sra.b\t\0" + /* 942 */ "nloc.b\t\0" + /* 950 */ "lapc.b\t\0" + /* 958 */ "nlzc.b\t\0" + /* 966 */ "sld.b\t\0" + /* 973 */ "pckod.b\t\0" + /* 982 */ "ilvod.b\t\0" + /* 991 */ "insve.b\t\0" + /* 1000 */ "vshf.b\t\0" + /* 1008 */ "bneg.b\t\0" + /* 1016 */ "srai.b\t\0" + /* 1024 */ "sldi.b\t\0" + /* 1032 */ "andi.b\t\0" + /* 1040 */ "bnegi.b\t\0" + /* 1049 */ "bseli.b\t\0" + /* 1058 */ "slli.b\t\0" + /* 1066 */ "srli.b\t\0" + /* 1074 */ "binsli.b\t\0" + /* 1084 */ "ceqi.b\t\0" + /* 1092 */ "srari.b\t\0" + /* 1101 */ "bclri.b\t\0" + /* 1110 */ "srlri.b\t\0" + /* 1119 */ "nori.b\t\0" + /* 1127 */ "xori.b\t\0" + /* 1135 */ "binsri.b\t\0" + /* 1145 */ "splati.b\t\0" + /* 1155 */ "bseti.b\t\0" + /* 1164 */ "subvi.b\t\0" + /* 1173 */ "addvi.b\t\0" + /* 1182 */ "bmzi.b\t\0" + /* 1190 */ "bmnzi.b\t\0" + /* 1199 */ "fill.b\t\0" + /* 1207 */ "sll.b\t\0" + /* 1214 */ "srl.b\t\0" + /* 1221 */ "binsl.b\t\0" + /* 1230 */ "ilvl.b\t\0" + /* 1238 */ "ceq.b\t\0" + /* 1245 */ "srar.b\t\0" + /* 1253 */ "bclr.b\t\0" + /* 1261 */ "srlr.b\t\0" + /* 1269 */ "binsr.b\t\0" + /* 1278 */ "ilvr.b\t\0" + /* 1286 */ "asub_s.b\t\0" + /* 1296 */ "mod_s.b\t\0" + /* 1305 */ "cle_s.b\t\0" + /* 1314 */ "ave_s.b\t\0" + /* 1323 */ "clei_s.b\t\0" + /* 1333 */ "mini_s.b\t\0" + /* 1343 */ "clti_s.b\t\0" + /* 1353 */ "maxi_s.b\t\0" + /* 1363 */ "min_s.b\t\0" + /* 1372 */ "aver_s.b\t\0" + /* 1382 */ "subs_s.b\t\0" + /* 1392 */ "adds_s.b\t\0" + /* 1402 */ "sat_s.b\t\0" + /* 1411 */ "clt_s.b\t\0" + /* 1420 */ "subsuu_s.b\t\0" + /* 1432 */ "div_s.b\t\0" + /* 1441 */ "max_s.b\t\0" + /* 1450 */ "copy_s.b\t\0" + /* 1460 */ "splat.b\t\0" + /* 1469 */ "bset.b\t\0" + /* 1477 */ "pcnt.b\t\0" + /* 1485 */ "insert.b\t\0" + /* 1495 */ "st.b\t\0" + /* 1501 */ "asub_u.b\t\0" + /* 1511 */ "mod_u.b\t\0" + /* 1520 */ "cle_u.b\t\0" + /* 1529 */ "ave_u.b\t\0" + /* 1538 */ "clei_u.b\t\0" + /* 1548 */ "mini_u.b\t\0" + /* 1558 */ "clti_u.b\t\0" + /* 1568 */ "maxi_u.b\t\0" + /* 1578 */ "min_u.b\t\0" + /* 1587 */ "aver_u.b\t\0" + /* 1597 */ "subs_u.b\t\0" + /* 1607 */ "adds_u.b\t\0" + /* 1617 */ "subsus_u.b\t\0" + /* 1629 */ "sat_u.b\t\0" + /* 1638 */ "clt_u.b\t\0" + /* 1647 */ "div_u.b\t\0" + /* 1656 */ "max_u.b\t\0" + /* 1665 */ "copy_u.b\t\0" + /* 1675 */ "msubv.b\t\0" + /* 1684 */ "maddv.b\t\0" + /* 1693 */ "pckev.b\t\0" + /* 1702 */ "ilvev.b\t\0" + /* 1711 */ "mulv.b\t\0" + /* 1719 */ "bz.b\t\0" + /* 1725 */ "bnz.b\t\0" + /* 1732 */ "crc32b\t\0" + /* 1740 */ "crc32cb\t\0" + /* 1749 */ "seb\t\0" + /* 1754 */ "jalrc.hb\t\0" + /* 1764 */ "jr.hb\t\0" + /* 1771 */ "jalr.hb\t\0" + /* 1780 */ "lb\t\0" + /* 1784 */ "shra.qb\t\0" + /* 1793 */ "cmpgdu.le.qb\t\0" + /* 1807 */ "cmpgu.le.qb\t\0" + /* 1820 */ "cmpu.le.qb\t\0" + /* 1832 */ "subuh.qb\t\0" + /* 1842 */ "adduh.qb\t\0" + /* 1852 */ "pick.qb\t\0" + /* 1861 */ "shll.qb\t\0" + /* 1870 */ "repl.qb\t\0" + /* 1879 */ "shrl.qb\t\0" + /* 1888 */ "cmpgdu.eq.qb\t\0" + /* 1902 */ "cmpgu.eq.qb\t\0" + /* 1915 */ "cmpu.eq.qb\t\0" + /* 1927 */ "shra_r.qb\t\0" + /* 1938 */ "subuh_r.qb\t\0" + /* 1950 */ "adduh_r.qb\t\0" + /* 1962 */ "shrav_r.qb\t\0" + /* 1974 */ "absq_s.qb\t\0" + /* 1985 */ "subu_s.qb\t\0" + /* 1996 */ "addu_s.qb\t\0" + /* 2007 */ "cmpgdu.lt.qb\t\0" + /* 2021 */ "cmpgu.lt.qb\t\0" + /* 2034 */ "cmpu.lt.qb\t\0" + /* 2046 */ "subu.qb\t\0" + /* 2055 */ "addu.qb\t\0" + /* 2064 */ "shrav.qb\t\0" + /* 2074 */ "shllv.qb\t\0" + /* 2084 */ "replv.qb\t\0" + /* 2094 */ "shrlv.qb\t\0" + /* 2104 */ "raddu.w.qb\t\0" + /* 2116 */ "sb\t\0" + /* 2120 */ "modsub\t\0" + /* 2128 */ "msub\t\0" + /* 2134 */ "bposge32c\t\0" + /* 2145 */ "bc\t\0" + /* 2149 */ "bgec\t\0" + /* 2155 */ "bnec\t\0" + /* 2161 */ "bgeic\t\0" + /* 2168 */ "bneic\t\0" + /* 2175 */ "jic\t\0" + /* 2180 */ "beqic\t\0" + /* 2187 */ "bltic\t\0" + /* 2194 */ "move.balc\t\0" + /* 2205 */ "jialc\t\0" + /* 2212 */ "bgezalc\t\0" + /* 2221 */ "blezalc\t\0" + /* 2230 */ "bnezalc\t\0" + /* 2239 */ "beqzalc\t\0" + /* 2248 */ "bgtzalc\t\0" + /* 2257 */ "bltzalc\t\0" + /* 2266 */ "sync\t\0" + /* 2272 */ "ldpc\t\0" + /* 2278 */ "auipc\t\0" + /* 2285 */ "aluipc\t\0" + /* 2293 */ "addiupc\t\0" + /* 2302 */ "lwupc\t\0" + /* 2309 */ "lwpc\t\0" + /* 2315 */ "swpc\t\0" + /* 2321 */ "beqc\t\0" + /* 2327 */ "restore.jrc\t\0" + /* 2340 */ "jalrc\t\0" + /* 2347 */ "addsc\t\0" + /* 2354 */ "brsc\t\0" + /* 2360 */ "balrsc\t\0" + /* 2368 */ "bltc\t\0" + /* 2374 */ "bgeuc\t\0" + /* 2381 */ "bgeiuc\t\0" + /* 2389 */ "bltiuc\t\0" + /* 2397 */ "bltuc\t\0" + /* 2404 */ "bnvc\t\0" + /* 2410 */ "bovc\t\0" + /* 2416 */ "addwc\t\0" + /* 2423 */ "bgezc\t\0" + /* 2430 */ "blezc\t\0" + /* 2437 */ "bc1nezc\t\0" + /* 2446 */ "bc2nezc\t\0" + /* 2455 */ "bbnezc\t\0" + /* 2463 */ "bc1eqzc\t\0" + /* 2472 */ "bc2eqzc\t\0" + /* 2481 */ "bbeqzc\t\0" + /* 2489 */ "bgtzc\t\0" + /* 2496 */ "bltzc\t\0" + /* 2503 */ "flog2.d\t\0" + /* 2512 */ "fexp2.d\t\0" + /* 2521 */ "add_a.d\t\0" + /* 2530 */ "fmin_a.d\t\0" + /* 2540 */ "adds_a.d\t\0" + /* 2550 */ "fmax_a.d\t\0" + /* 2560 */ "mina.d\t\0" + /* 2568 */ "sra.d\t\0" + /* 2575 */ "maxa.d\t\0" + /* 2583 */ "fsub.d\t\0" + /* 2591 */ "fmsub.d\t\0" + /* 2600 */ "nmsub.d\t\0" + /* 2609 */ "nloc.d\t\0" + /* 2617 */ "nlzc.d\t\0" + /* 2625 */ "fadd.d\t\0" + /* 2633 */ "fmadd.d\t\0" + /* 2642 */ "nmadd.d\t\0" + /* 2651 */ "sld.d\t\0" + /* 2658 */ "pckod.d\t\0" + /* 2667 */ "ilvod.d\t\0" + /* 2676 */ "c.nge.d\t\0" + /* 2685 */ "c.le.d\t\0" + /* 2693 */ "cmp.le.d\t\0" + /* 2703 */ "fcle.d\t\0" + /* 2711 */ "c.ngle.d\t\0" + /* 2721 */ "c.ole.d\t\0" + /* 2730 */ "cmp.sle.d\t\0" + /* 2741 */ "fsle.d\t\0" + /* 2749 */ "c.ule.d\t\0" + /* 2758 */ "cmp.ule.d\t\0" + /* 2769 */ "fcule.d\t\0" + /* 2778 */ "cmp.sule.d\t\0" + /* 2790 */ "fsule.d\t\0" + /* 2799 */ "fcne.d\t\0" + /* 2807 */ "fsne.d\t\0" + /* 2815 */ "fcune.d\t\0" + /* 2824 */ "fsune.d\t\0" + /* 2833 */ "insve.d\t\0" + /* 2842 */ "c.f.d\t\0" + /* 2849 */ "cmp.af.d\t\0" + /* 2859 */ "fcaf.d\t\0" + /* 2867 */ "cmp.saf.d\t\0" + /* 2878 */ "fsaf.d\t\0" + /* 2886 */ "msubf.d\t\0" + /* 2895 */ "maddf.d\t\0" + /* 2904 */ "vshf.d\t\0" + /* 2912 */ "c.sf.d\t\0" + /* 2920 */ "movf.d\t\0" + /* 2928 */ "bneg.d\t\0" + /* 2936 */ "srai.d\t\0" + /* 2944 */ "sldi.d\t\0" + /* 2952 */ "bnegi.d\t\0" + /* 2961 */ "slli.d\t\0" + /* 2969 */ "srli.d\t\0" + /* 2977 */ "binsli.d\t\0" + /* 2987 */ "ceqi.d\t\0" + /* 2995 */ "srari.d\t\0" + /* 3004 */ "bclri.d\t\0" + /* 3013 */ "srlri.d\t\0" + /* 3022 */ "binsri.d\t\0" + /* 3032 */ "splati.d\t\0" + /* 3042 */ "bseti.d\t\0" + /* 3051 */ "subvi.d\t\0" + /* 3060 */ "addvi.d\t\0" + /* 3069 */ "trunc.l.d\t\0" + /* 3080 */ "round.l.d\t\0" + /* 3091 */ "ceil.l.d\t\0" + /* 3101 */ "floor.l.d\t\0" + /* 3112 */ "cvt.l.d\t\0" + /* 3121 */ "sel.d\t\0" + /* 3128 */ "c.ngl.d\t\0" + /* 3137 */ "fill.d\t\0" + /* 3145 */ "sll.d\t\0" + /* 3152 */ "fexupl.d\t\0" + /* 3162 */ "ffql.d\t\0" + /* 3170 */ "srl.d\t\0" + /* 3177 */ "binsl.d\t\0" + /* 3186 */ "fmul.d\t\0" + /* 3194 */ "ilvl.d\t\0" + /* 3202 */ "fmin.d\t\0" + /* 3210 */ "c.un.d\t\0" + /* 3218 */ "cmp.un.d\t\0" + /* 3228 */ "fcun.d\t\0" + /* 3236 */ "cmp.sun.d\t\0" + /* 3247 */ "fsun.d\t\0" + /* 3255 */ "movn.d\t\0" + /* 3263 */ "frcp.d\t\0" + /* 3271 */ "recip.d\t\0" + /* 3280 */ "c.eq.d\t\0" + /* 3288 */ "cmp.eq.d\t\0" + /* 3298 */ "fceq.d\t\0" + /* 3306 */ "c.seq.d\t\0" + /* 3315 */ "cmp.seq.d\t\0" + /* 3326 */ "fseq.d\t\0" + /* 3334 */ "c.ueq.d\t\0" + /* 3343 */ "cmp.ueq.d\t\0" + /* 3354 */ "fcueq.d\t\0" + /* 3363 */ "cmp.sueq.d\t\0" + /* 3375 */ "fsueq.d\t\0" + /* 3384 */ "srar.d\t\0" + /* 3392 */ "bclr.d\t\0" + /* 3400 */ "srlr.d\t\0" + /* 3408 */ "fcor.d\t\0" + /* 3416 */ "fsor.d\t\0" + /* 3424 */ "fexupr.d\t\0" + /* 3434 */ "ffqr.d\t\0" + /* 3442 */ "binsr.d\t\0" + /* 3451 */ "ilvr.d\t\0" + /* 3459 */ "cvt.s.d\t\0" + /* 3468 */ "asub_s.d\t\0" + /* 3478 */ "hsub_s.d\t\0" + /* 3488 */ "dpsub_s.d\t\0" + /* 3499 */ "ftrunc_s.d\t\0" + /* 3511 */ "hadd_s.d\t\0" + /* 3521 */ "dpadd_s.d\t\0" + /* 3532 */ "mod_s.d\t\0" + /* 3541 */ "cle_s.d\t\0" + /* 3550 */ "ave_s.d\t\0" + /* 3559 */ "clei_s.d\t\0" + /* 3569 */ "mini_s.d\t\0" + /* 3579 */ "clti_s.d\t\0" + /* 3589 */ "maxi_s.d\t\0" + /* 3599 */ "min_s.d\t\0" + /* 3608 */ "dotp_s.d\t\0" + /* 3618 */ "aver_s.d\t\0" + /* 3628 */ "subs_s.d\t\0" + /* 3638 */ "adds_s.d\t\0" + /* 3648 */ "sat_s.d\t\0" + /* 3657 */ "clt_s.d\t\0" + /* 3666 */ "ffint_s.d\t\0" + /* 3677 */ "ftint_s.d\t\0" + /* 3688 */ "subsuu_s.d\t\0" + /* 3700 */ "div_s.d\t\0" + /* 3709 */ "max_s.d\t\0" + /* 3718 */ "copy_s.d\t\0" + /* 3728 */ "abs.d\t\0" + /* 3735 */ "fclass.d\t\0" + /* 3745 */ "splat.d\t\0" + /* 3754 */ "bset.d\t\0" + /* 3762 */ "c.ngt.d\t\0" + /* 3771 */ "c.lt.d\t\0" + /* 3779 */ "cmp.lt.d\t\0" + /* 3789 */ "fclt.d\t\0" + /* 3797 */ "c.olt.d\t\0" + /* 3806 */ "cmp.slt.d\t\0" + /* 3817 */ "fslt.d\t\0" + /* 3825 */ "c.ult.d\t\0" + /* 3834 */ "cmp.ult.d\t\0" + /* 3845 */ "fcult.d\t\0" + /* 3854 */ "cmp.sult.d\t\0" + /* 3866 */ "fsult.d\t\0" + /* 3875 */ "pcnt.d\t\0" + /* 3883 */ "frint.d\t\0" + /* 3892 */ "insert.d\t\0" + /* 3902 */ "fsqrt.d\t\0" + /* 3911 */ "frsqrt.d\t\0" + /* 3921 */ "st.d\t\0" + /* 3927 */ "movt.d\t\0" + /* 3935 */ "asub_u.d\t\0" + /* 3945 */ "hsub_u.d\t\0" + /* 3955 */ "dpsub_u.d\t\0" + /* 3966 */ "ftrunc_u.d\t\0" + /* 3978 */ "hadd_u.d\t\0" + /* 3988 */ "dpadd_u.d\t\0" + /* 3999 */ "mod_u.d\t\0" + /* 4008 */ "cle_u.d\t\0" + /* 4017 */ "ave_u.d\t\0" + /* 4026 */ "clei_u.d\t\0" + /* 4036 */ "mini_u.d\t\0" + /* 4046 */ "clti_u.d\t\0" + /* 4056 */ "maxi_u.d\t\0" + /* 4066 */ "min_u.d\t\0" + /* 4075 */ "dotp_u.d\t\0" + /* 4085 */ "aver_u.d\t\0" + /* 4095 */ "subs_u.d\t\0" + /* 4105 */ "adds_u.d\t\0" + /* 4115 */ "subsus_u.d\t\0" + /* 4127 */ "sat_u.d\t\0" + /* 4136 */ "clt_u.d\t\0" + /* 4145 */ "ffint_u.d\t\0" + /* 4156 */ "ftint_u.d\t\0" + /* 4167 */ "div_u.d\t\0" + /* 4176 */ "max_u.d\t\0" + /* 4185 */ "msubv.d\t\0" + /* 4194 */ "maddv.d\t\0" + /* 4203 */ "pckev.d\t\0" + /* 4212 */ "ilvev.d\t\0" + /* 4221 */ "fdiv.d\t\0" + /* 4229 */ "mulv.d\t\0" + /* 4237 */ "mov.d\t\0" + /* 4244 */ "trunc.w.d\t\0" + /* 4255 */ "round.w.d\t\0" + /* 4266 */ "ceil.w.d\t\0" + /* 4276 */ "floor.w.d\t\0" + /* 4287 */ "cvt.w.d\t\0" + /* 4296 */ "fmax.d\t\0" + /* 4304 */ "bz.d\t\0" + /* 4310 */ "selnez.d\t\0" + /* 4320 */ "bnz.d\t\0" + /* 4327 */ "seleqz.d\t\0" + /* 4337 */ "movz.d\t\0" + /* 4345 */ "crc32d\t\0" + /* 4353 */ "saad\t\0" + /* 4359 */ "crc32cd\t\0" + /* 4368 */ "scd\t\0" + /* 4373 */ "dadd\t\0" + /* 4379 */ "madd\t\0" + /* 4385 */ "dshd\t\0" + /* 4391 */ "yield\t\0" + /* 4398 */ "lld\t\0" + /* 4403 */ "and\t\0" + /* 4408 */ "prepend\t\0" + /* 4417 */ "append\t\0" + /* 4425 */ "dmod\t\0" + /* 4431 */ "sd\t\0" + /* 4435 */ "lbe\t\0" + /* 4440 */ "sbe\t\0" + /* 4445 */ "sce\t\0" + /* 4450 */ "cachee\t\0" + /* 4458 */ "prefe\t\0" + /* 4465 */ "bge\t\0" + /* 4470 */ "sge\t\0" + /* 4475 */ "tge\t\0" + /* 4480 */ "cache\t\0" + /* 4487 */ "lhe\t\0" + /* 4492 */ "she\t\0" + /* 4497 */ "sigrie\t\0" + /* 4505 */ "ble\t\0" + /* 4510 */ "lle\t\0" + /* 4515 */ "sle\t\0" + /* 4520 */ "lwle\t\0" + /* 4526 */ "swle\t\0" + /* 4532 */ "bne\t\0" + /* 4537 */ "sne\t\0" + /* 4542 */ "tne\t\0" + /* 4547 */ "dvpe\t\0" + /* 4553 */ "evpe\t\0" + /* 4559 */ "restore\t\0" + /* 4568 */ "lwre\t\0" + /* 4574 */ "swre\t\0" + /* 4580 */ "lbue\t\0" + /* 4586 */ "lhue\t\0" + /* 4592 */ "save\t\0" + /* 4598 */ "move\t\0" + /* 4604 */ "lwe\t\0" + /* 4609 */ "swe\t\0" + /* 4614 */ "bc1f\t\0" + /* 4620 */ "pref\t\0" + /* 4626 */ "movf\t\0" + /* 4632 */ "neg\t\0" + /* 4637 */ "add_a.h\t\0" + /* 4646 */ "min_a.h\t\0" + /* 4655 */ "adds_a.h\t\0" + /* 4665 */ "max_a.h\t\0" + /* 4674 */ "sra.h\t\0" + /* 4681 */ "nloc.h\t\0" + /* 4689 */ "lapc.h\t\0" + /* 4697 */ "nlzc.h\t\0" + /* 4705 */ "sld.h\t\0" + /* 4712 */ "pckod.h\t\0" + /* 4721 */ "ilvod.h\t\0" + /* 4730 */ "insve.h\t\0" + /* 4739 */ "vshf.h\t\0" + /* 4747 */ "bneg.h\t\0" + /* 4755 */ "srai.h\t\0" + /* 4763 */ "sldi.h\t\0" + /* 4771 */ "bnegi.h\t\0" + /* 4780 */ "slli.h\t\0" + /* 4788 */ "srli.h\t\0" + /* 4796 */ "binsli.h\t\0" + /* 4806 */ "ceqi.h\t\0" + /* 4814 */ "srari.h\t\0" + /* 4823 */ "bclri.h\t\0" + /* 4832 */ "srlri.h\t\0" + /* 4841 */ "binsri.h\t\0" + /* 4851 */ "splati.h\t\0" + /* 4861 */ "bseti.h\t\0" + /* 4870 */ "subvi.h\t\0" + /* 4879 */ "addvi.h\t\0" + /* 4888 */ "fill.h\t\0" + /* 4896 */ "sll.h\t\0" + /* 4903 */ "srl.h\t\0" + /* 4910 */ "binsl.h\t\0" + /* 4919 */ "ilvl.h\t\0" + /* 4927 */ "fexdo.h\t\0" + /* 4936 */ "msub_q.h\t\0" + /* 4946 */ "madd_q.h\t\0" + /* 4956 */ "mul_q.h\t\0" + /* 4965 */ "msubr_q.h\t\0" + /* 4976 */ "maddr_q.h\t\0" + /* 4987 */ "mulr_q.h\t\0" + /* 4997 */ "ceq.h\t\0" + /* 5004 */ "ftq.h\t\0" + /* 5011 */ "srar.h\t\0" + /* 5019 */ "bclr.h\t\0" + /* 5027 */ "srlr.h\t\0" + /* 5035 */ "binsr.h\t\0" + /* 5044 */ "ilvr.h\t\0" + /* 5052 */ "asub_s.h\t\0" + /* 5062 */ "hsub_s.h\t\0" + /* 5072 */ "dpsub_s.h\t\0" + /* 5083 */ "hadd_s.h\t\0" + /* 5093 */ "dpadd_s.h\t\0" + /* 5104 */ "mod_s.h\t\0" + /* 5113 */ "cle_s.h\t\0" + /* 5122 */ "ave_s.h\t\0" + /* 5131 */ "clei_s.h\t\0" + /* 5141 */ "mini_s.h\t\0" + /* 5151 */ "clti_s.h\t\0" + /* 5161 */ "maxi_s.h\t\0" + /* 5171 */ "min_s.h\t\0" + /* 5180 */ "dotp_s.h\t\0" + /* 5190 */ "aver_s.h\t\0" + /* 5200 */ "extr_s.h\t\0" + /* 5210 */ "subs_s.h\t\0" + /* 5220 */ "adds_s.h\t\0" + /* 5230 */ "sat_s.h\t\0" + /* 5239 */ "clt_s.h\t\0" + /* 5248 */ "subsuu_s.h\t\0" + /* 5260 */ "div_s.h\t\0" + /* 5269 */ "extrv_s.h\t\0" + /* 5280 */ "max_s.h\t\0" + /* 5289 */ "copy_s.h\t\0" + /* 5299 */ "splat.h\t\0" + /* 5308 */ "bset.h\t\0" + /* 5316 */ "pcnt.h\t\0" + /* 5324 */ "insert.h\t\0" + /* 5334 */ "st.h\t\0" + /* 5340 */ "asub_u.h\t\0" + /* 5350 */ "hsub_u.h\t\0" + /* 5360 */ "dpsub_u.h\t\0" + /* 5371 */ "hadd_u.h\t\0" + /* 5381 */ "dpadd_u.h\t\0" + /* 5392 */ "mod_u.h\t\0" + /* 5401 */ "cle_u.h\t\0" + /* 5410 */ "ave_u.h\t\0" + /* 5419 */ "clei_u.h\t\0" + /* 5429 */ "mini_u.h\t\0" + /* 5439 */ "clti_u.h\t\0" + /* 5449 */ "maxi_u.h\t\0" + /* 5459 */ "min_u.h\t\0" + /* 5468 */ "dotp_u.h\t\0" + /* 5478 */ "aver_u.h\t\0" + /* 5488 */ "subs_u.h\t\0" + /* 5498 */ "adds_u.h\t\0" + /* 5508 */ "subsus_u.h\t\0" + /* 5520 */ "sat_u.h\t\0" + /* 5529 */ "clt_u.h\t\0" + /* 5538 */ "div_u.h\t\0" + /* 5547 */ "max_u.h\t\0" + /* 5556 */ "copy_u.h\t\0" + /* 5566 */ "msubv.h\t\0" + /* 5575 */ "maddv.h\t\0" + /* 5584 */ "pckev.h\t\0" + /* 5593 */ "ilvev.h\t\0" + /* 5602 */ "mulv.h\t\0" + /* 5610 */ "bz.h\t\0" + /* 5616 */ "bnz.h\t\0" + /* 5623 */ "crc32h\t\0" + /* 5631 */ "dsbh\t\0" + /* 5637 */ "wsbh\t\0" + /* 5643 */ "crc32ch\t\0" + /* 5652 */ "seh\t\0" + /* 5657 */ "ualh\t\0" + /* 5663 */ "ulh\t\0" + /* 5668 */ "shra.ph\t\0" + /* 5677 */ "precrq.qb.ph\t\0" + /* 5691 */ "precr.qb.ph\t\0" + /* 5704 */ "precrqu_s.qb.ph\t\0" + /* 5721 */ "cmp.le.ph\t\0" + /* 5732 */ "subqh.ph\t\0" + /* 5742 */ "addqh.ph\t\0" + /* 5752 */ "pick.ph\t\0" + /* 5761 */ "shll.ph\t\0" + /* 5770 */ "repl.ph\t\0" + /* 5779 */ "shrl.ph\t\0" + /* 5788 */ "packrl.ph\t\0" + /* 5799 */ "mul.ph\t\0" + /* 5807 */ "subq.ph\t\0" + /* 5816 */ "addq.ph\t\0" + /* 5825 */ "cmp.eq.ph\t\0" + /* 5836 */ "shra_r.ph\t\0" + /* 5847 */ "subqh_r.ph\t\0" + /* 5859 */ "addqh_r.ph\t\0" + /* 5871 */ "shrav_r.ph\t\0" + /* 5883 */ "shll_s.ph\t\0" + /* 5894 */ "mul_s.ph\t\0" + /* 5904 */ "subq_s.ph\t\0" + /* 5915 */ "addq_s.ph\t\0" + /* 5926 */ "mulq_s.ph\t\0" + /* 5937 */ "absq_s.ph\t\0" + /* 5948 */ "subu_s.ph\t\0" + /* 5959 */ "addu_s.ph\t\0" + /* 5970 */ "shllv_s.ph\t\0" + /* 5982 */ "mulq_rs.ph\t\0" + /* 5994 */ "cmp.lt.ph\t\0" + /* 6005 */ "subu.ph\t\0" + /* 6014 */ "addu.ph\t\0" + /* 6023 */ "shrav.ph\t\0" + /* 6033 */ "shllv.ph\t\0" + /* 6043 */ "replv.ph\t\0" + /* 6053 */ "shrlv.ph\t\0" + /* 6063 */ "dpa.w.ph\t\0" + /* 6073 */ "dpaqx_sa.w.ph\t\0" + /* 6088 */ "dpsqx_sa.w.ph\t\0" + /* 6103 */ "mulsa.w.ph\t\0" + /* 6115 */ "dpaq_s.w.ph\t\0" + /* 6128 */ "mulsaq_s.w.ph\t\0" + /* 6143 */ "dpsq_s.w.ph\t\0" + /* 6156 */ "dpaqx_s.w.ph\t\0" + /* 6170 */ "dpsqx_s.w.ph\t\0" + /* 6184 */ "dps.w.ph\t\0" + /* 6194 */ "dpax.w.ph\t\0" + /* 6205 */ "dpsx.w.ph\t\0" + /* 6216 */ "uash\t\0" + /* 6222 */ "ush\t\0" + /* 6227 */ "dmuh\t\0" + /* 6233 */ "synci\t\0" + /* 6240 */ "daddi\t\0" + /* 6247 */ "andi\t\0" + /* 6253 */ "tgei\t\0" + /* 6259 */ "snei\t\0" + /* 6265 */ "tnei\t\0" + /* 6271 */ "dahi\t\0" + /* 6277 */ "mfhi\t\0" + /* 6283 */ "mthi\t\0" + /* 6289 */ ".align 2\n\tli\t\0" + /* 6303 */ "dli\t\0" + /* 6308 */ "cmpi\t\0" + /* 6314 */ "seqi\t\0" + /* 6320 */ "teqi\t\0" + /* 6326 */ "xori\t\0" + /* 6332 */ "dati\t\0" + /* 6338 */ "slti\t\0" + /* 6344 */ "tlti\t\0" + /* 6350 */ "daui\t\0" + /* 6356 */ "lui\t\0" + /* 6361 */ "ginvi\t\0" + /* 6368 */ "j\t\0" + /* 6371 */ "break\t\0" + /* 6378 */ "fork\t\0" + /* 6384 */ "cvt.d.l\t\0" + /* 6393 */ "cvt.s.l\t\0" + /* 6402 */ "bal\t\0" + /* 6407 */ "jal\t\0" + /* 6412 */ "bgezal\t\0" + /* 6420 */ "bltzal\t\0" + /* 6428 */ "dpau.h.qbl\t\0" + /* 6440 */ "dpsu.h.qbl\t\0" + /* 6452 */ "muleu_s.ph.qbl\t\0" + /* 6468 */ "preceu.ph.qbl\t\0" + /* 6483 */ "precequ.ph.qbl\t\0" + /* 6499 */ "ldl\t\0" + /* 6504 */ "sdl\t\0" + /* 6509 */ "bgel\t\0" + /* 6515 */ "blel\t\0" + /* 6521 */ "bnel\t\0" + /* 6527 */ "bc1fl\t\0" + /* 6534 */ "maq_sa.w.phl\t\0" + /* 6548 */ "preceq.w.phl\t\0" + /* 6562 */ "maq_s.w.phl\t\0" + /* 6575 */ "muleq_s.w.phl\t\0" + /* 6590 */ "hypcall\t\0" + /* 6599 */ "syscall\t\0" + /* 6608 */ "bgezall\t\0" + /* 6617 */ "bltzall\t\0" + /* 6626 */ "dsll\t\0" + /* 6632 */ "drol\t\0" + /* 6638 */ "cvt.s.pl\t\0" + /* 6648 */ "beql\t\0" + /* 6654 */ "dsrl\t\0" + /* 6660 */ "bc1tl\t\0" + /* 6667 */ "bgtl\t\0" + /* 6673 */ "bltl\t\0" + /* 6679 */ "bgeul\t\0" + /* 6686 */ "bleul\t\0" + /* 6693 */ "dmul\t\0" + /* 6699 */ "bgtul\t\0" + /* 6706 */ "bltul\t\0" + /* 6713 */ "lwl\t\0" + /* 6718 */ "swl\t\0" + /* 6723 */ "bgezl\t\0" + /* 6730 */ "blezl\t\0" + /* 6737 */ "bgtzl\t\0" + /* 6744 */ "bltzl\t\0" + /* 6751 */ "drem\t\0" + /* 6757 */ "dinsm\t\0" + /* 6764 */ "dextm\t\0" + /* 6771 */ "ualwm\t\0" + /* 6778 */ "uaswm\t\0" + /* 6785 */ "balign\t\0" + /* 6793 */ "dalign\t\0" + /* 6801 */ "movn\t\0" + /* 6807 */ "dclo\t\0" + /* 6813 */ "mflo\t\0" + /* 6819 */ "shilo\t\0" + /* 6826 */ "mtlo\t\0" + /* 6832 */ "dmulo\t\0" + /* 6839 */ "dbitswap\t\0" + /* 6849 */ "sdbbp\t\0" + /* 6856 */ "extpdp\t\0" + /* 6864 */ "movep\t\0" + /* 6871 */ "mthlip\t\0" + /* 6879 */ "cmp\t\0" + /* 6884 */ "dpop\t\0" + /* 6890 */ "addiur1sp\t\0" + /* 6901 */ "load_ccond_dsp\t\0" + /* 6917 */ "store_ccond_dsp\t\0" + /* 6934 */ "rddsp\t\0" + /* 6941 */ "wrdsp\t\0" + /* 6948 */ "jrcaddiusp\t\0" + /* 6960 */ "jraddiusp\t\0" + /* 6971 */ "swsp\t\0" + /* 6977 */ "extp\t\0" + /* 6983 */ "dvp\t\0" + /* 6988 */ "evp\t\0" + /* 6993 */ "lwp\t\0" + /* 6998 */ "swp\t\0" + /* 7003 */ "beq\t\0" + /* 7008 */ "seq\t\0" + /* 7013 */ "teq\t\0" + /* 7018 */ "dpau.h.qbr\t\0" + /* 7030 */ "dpsu.h.qbr\t\0" + /* 7042 */ "muleu_s.ph.qbr\t\0" + /* 7058 */ "preceu.ph.qbr\t\0" + /* 7073 */ "precequ.ph.qbr\t\0" + /* 7089 */ "ldr\t\0" + /* 7094 */ "sdr\t\0" + /* 7099 */ "maq_sa.w.phr\t\0" + /* 7113 */ "preceq.w.phr\t\0" + /* 7127 */ "maq_s.w.phr\t\0" + /* 7140 */ "muleq_s.w.phr\t\0" + /* 7155 */ "jr\t\0" + /* 7159 */ "jalr\t\0" + /* 7165 */ "nor\t\0" + /* 7170 */ "dror\t\0" + /* 7176 */ "xor\t\0" + /* 7181 */ "rdpgpr\t\0" + /* 7189 */ "wrpgpr\t\0" + /* 7197 */ "mftr\t\0" + /* 7203 */ "drotr\t\0" + /* 7210 */ "mttr\t\0" + /* 7216 */ "rdhwr\t\0" + /* 7223 */ "lwr\t\0" + /* 7228 */ "swr\t\0" + /* 7233 */ "mina.s\t\0" + /* 7241 */ "maxa.s\t\0" + /* 7249 */ "nmsub.s\t\0" + /* 7258 */ "cvt.d.s\t\0" + /* 7267 */ "nmadd.s\t\0" + /* 7276 */ "c.nge.s\t\0" + /* 7285 */ "c.le.s\t\0" + /* 7293 */ "cmp.le.s\t\0" + /* 7303 */ "c.ngle.s\t\0" + /* 7313 */ "c.ole.s\t\0" + /* 7322 */ "cmp.sle.s\t\0" + /* 7333 */ "c.ule.s\t\0" + /* 7342 */ "cmp.ule.s\t\0" + /* 7353 */ "cmp.sule.s\t\0" + /* 7365 */ "c.f.s\t\0" + /* 7372 */ "cmp.af.s\t\0" + /* 7382 */ "cmp.saf.s\t\0" + /* 7393 */ "msubf.s\t\0" + /* 7402 */ "maddf.s\t\0" + /* 7411 */ "c.sf.s\t\0" + /* 7419 */ "movf.s\t\0" + /* 7427 */ "neg.s\t\0" + /* 7434 */ "li.s\t\0" + /* 7440 */ "trunc.l.s\t\0" + /* 7451 */ "round.l.s\t\0" + /* 7462 */ "ceil.l.s\t\0" + /* 7472 */ "floor.l.s\t\0" + /* 7483 */ "cvt.l.s\t\0" + /* 7492 */ "sel.s\t\0" + /* 7499 */ "c.ngl.s\t\0" + /* 7508 */ "mul.s\t\0" + /* 7515 */ "min.s\t\0" + /* 7522 */ "c.un.s\t\0" + /* 7530 */ "cmp.un.s\t\0" + /* 7540 */ "cmp.sun.s\t\0" + /* 7551 */ "movn.s\t\0" + /* 7559 */ "recip.s\t\0" + /* 7568 */ "c.eq.s\t\0" + /* 7576 */ "cmp.eq.s\t\0" + /* 7586 */ "c.seq.s\t\0" + /* 7595 */ "cmp.seq.s\t\0" + /* 7606 */ "c.ueq.s\t\0" + /* 7615 */ "cmp.ueq.s\t\0" + /* 7626 */ "cmp.sueq.s\t\0" + /* 7638 */ "abs.s\t\0" + /* 7645 */ "cvt.ps.s\t\0" + /* 7655 */ "class.s\t\0" + /* 7664 */ "c.ngt.s\t\0" + /* 7673 */ "c.lt.s\t\0" + /* 7681 */ "cmp.lt.s\t\0" + /* 7691 */ "c.olt.s\t\0" + /* 7700 */ "cmp.slt.s\t\0" + /* 7711 */ "c.ult.s\t\0" + /* 7720 */ "cmp.ult.s\t\0" + /* 7731 */ "cmp.sult.s\t\0" + /* 7743 */ "rint.s\t\0" + /* 7751 */ "rsqrt.s\t\0" + /* 7760 */ "movt.s\t\0" + /* 7768 */ "div.s\t\0" + /* 7775 */ "mov.s\t\0" + /* 7782 */ "trunc.w.s\t\0" + /* 7793 */ "round.w.s\t\0" + /* 7804 */ "ceil.w.s\t\0" + /* 7814 */ "floor.w.s\t\0" + /* 7825 */ "cvt.w.s\t\0" + /* 7834 */ "max.s\t\0" + /* 7841 */ "selnez.s\t\0" + /* 7851 */ "seleqz.s\t\0" + /* 7861 */ "movz.s\t\0" + /* 7869 */ "abs\t\0" + /* 7874 */ "jals\t\0" + /* 7880 */ "bgezals\t\0" + /* 7889 */ "bltzals\t\0" + /* 7898 */ "cins\t\0" + /* 7904 */ "dins\t\0" + /* 7910 */ "sub.ps\t\0" + /* 7918 */ "add.ps\t\0" + /* 7926 */ "pll.ps\t\0" + /* 7934 */ "mul.ps\t\0" + /* 7942 */ "pul.ps\t\0" + /* 7950 */ "addr.ps\t\0" + /* 7959 */ "mulr.ps\t\0" + /* 7968 */ "plu.ps\t\0" + /* 7976 */ "puu.ps\t\0" + /* 7984 */ "cvt.pw.ps\t\0" + /* 7995 */ "jalrs\t\0" + /* 8002 */ "exts\t\0" + /* 8008 */ "lhxs\t\0" + /* 8014 */ "shxs\t\0" + /* 8020 */ "lhuxs\t\0" + /* 8027 */ "lwxs\t\0" + /* 8033 */ "swxs\t\0" + /* 8039 */ "bc1t\t\0" + /* 8045 */ "bgt\t\0" + /* 8050 */ "sgt\t\0" + /* 8055 */ "wait\t\0" + /* 8061 */ "blt\t\0" + /* 8066 */ "slt\t\0" + /* 8071 */ "tlt\t\0" + /* 8076 */ "dmult\t\0" + /* 8083 */ "dmt\t\0" + /* 8088 */ "emt\t\0" + /* 8093 */ "not\t\0" + /* 8098 */ "ginvt\t\0" + /* 8105 */ "movt\t\0" + /* 8111 */ "dext\t\0" + /* 8117 */ "lbu\t\0" + /* 8122 */ "dsubu\t\0" + /* 8129 */ "msubu\t\0" + /* 8136 */ "baddu\t\0" + /* 8143 */ "daddu\t\0" + /* 8150 */ "maddu\t\0" + /* 8157 */ "dmodu\t\0" + /* 8164 */ "bgeu\t\0" + /* 8170 */ "sgeu\t\0" + /* 8176 */ "tgeu\t\0" + /* 8182 */ "bleu\t\0" + /* 8188 */ "sleu\t\0" + /* 8194 */ "ulhu\t\0" + /* 8200 */ "dmuhu\t\0" + /* 8207 */ "daddiu\t\0" + /* 8215 */ "tgeiu\t\0" + /* 8222 */ "sltiu\t\0" + /* 8229 */ "tltiu\t\0" + /* 8236 */ "v3mulu\t\0" + /* 8244 */ "dmulu\t\0" + /* 8251 */ "vmulu\t\0" + /* 8258 */ "dremu\t\0" + /* 8265 */ "dmulou\t\0" + /* 8273 */ "cvt.s.pu\t\0" + /* 8283 */ "dinsu\t\0" + /* 8290 */ "bgtu\t\0" + /* 8296 */ "sgtu\t\0" + /* 8302 */ "bltu\t\0" + /* 8308 */ "sltu\t\0" + /* 8314 */ "tltu\t\0" + /* 8320 */ "dmultu\t\0" + /* 8328 */ "dextu\t\0" + /* 8335 */ "ddivu\t\0" + /* 8342 */ "lwu\t\0" + /* 8347 */ "and.v\t\0" + /* 8354 */ "move.v\t\0" + /* 8362 */ "bsel.v\t\0" + /* 8370 */ "nor.v\t\0" + /* 8377 */ "xor.v\t\0" + /* 8384 */ "bz.v\t\0" + /* 8390 */ "bmz.v\t\0" + /* 8397 */ "bnz.v\t\0" + /* 8404 */ "bmnz.v\t\0" + /* 8412 */ "dsrav\t\0" + /* 8419 */ "bitrev\t\0" + /* 8427 */ "ddiv\t\0" + /* 8433 */ "dsllv\t\0" + /* 8440 */ "dsrlv\t\0" + /* 8447 */ "shilov\t\0" + /* 8455 */ "sov\t\0" + /* 8460 */ "extpdpv\t\0" + /* 8469 */ "extpv\t\0" + /* 8476 */ "drotrv\t\0" + /* 8484 */ "insv\t\0" + /* 8490 */ "flog2.w\t\0" + /* 8499 */ "fexp2.w\t\0" + /* 8508 */ "add_a.w\t\0" + /* 8517 */ "fmin_a.w\t\0" + /* 8527 */ "adds_a.w\t\0" + /* 8537 */ "fmax_a.w\t\0" + /* 8547 */ "sra.w\t\0" + /* 8554 */ "fsub.w\t\0" + /* 8562 */ "fmsub.w\t\0" + /* 8571 */ "nloc.w\t\0" + /* 8579 */ "nlzc.w\t\0" + /* 8587 */ "cvt.d.w\t\0" + /* 8596 */ "fadd.w\t\0" + /* 8604 */ "fmadd.w\t\0" + /* 8613 */ "sld.w\t\0" + /* 8620 */ "pckod.w\t\0" + /* 8629 */ "ilvod.w\t\0" + /* 8638 */ "fcle.w\t\0" + /* 8646 */ "fsle.w\t\0" + /* 8654 */ "fcule.w\t\0" + /* 8663 */ "fsule.w\t\0" + /* 8672 */ "fcne.w\t\0" + /* 8680 */ "fsne.w\t\0" + /* 8688 */ "fcune.w\t\0" + /* 8697 */ "fsune.w\t\0" + /* 8706 */ "insve.w\t\0" + /* 8715 */ "fcaf.w\t\0" + /* 8723 */ "fsaf.w\t\0" + /* 8731 */ "vshf.w\t\0" + /* 8739 */ "bneg.w\t\0" + /* 8747 */ "precr_sra.ph.w\t\0" + /* 8763 */ "precrq.ph.w\t\0" + /* 8776 */ "precr_sra_r.ph.w\t\0" + /* 8794 */ "precrq_rs.ph.w\t\0" + /* 8810 */ "subqh.w\t\0" + /* 8819 */ "addqh.w\t\0" + /* 8828 */ "srai.w\t\0" + /* 8836 */ "sldi.w\t\0" + /* 8844 */ "bnegi.w\t\0" + /* 8853 */ "slli.w\t\0" + /* 8861 */ "srli.w\t\0" + /* 8869 */ "binsli.w\t\0" + /* 8879 */ "ceqi.w\t\0" + /* 8887 */ "srari.w\t\0" + /* 8896 */ "bclri.w\t\0" + /* 8905 */ "srlri.w\t\0" + /* 8914 */ "binsri.w\t\0" + /* 8924 */ "splati.w\t\0" + /* 8934 */ "bseti.w\t\0" + /* 8943 */ "subvi.w\t\0" + /* 8952 */ "addvi.w\t\0" + /* 8961 */ "dpaq_sa.l.w\t\0" + /* 8974 */ "dpsq_sa.l.w\t\0" + /* 8987 */ "fill.w\t\0" + /* 8995 */ "sll.w\t\0" + /* 9002 */ "fexupl.w\t\0" + /* 9012 */ "ffql.w\t\0" + /* 9020 */ "srl.w\t\0" + /* 9027 */ "binsl.w\t\0" + /* 9036 */ "fmul.w\t\0" + /* 9044 */ "ilvl.w\t\0" + /* 9052 */ "fmin.w\t\0" + /* 9060 */ "fcun.w\t\0" + /* 9068 */ "fsun.w\t\0" + /* 9076 */ "fexdo.w\t\0" + /* 9085 */ "frcp.w\t\0" + /* 9093 */ "msub_q.w\t\0" + /* 9103 */ "madd_q.w\t\0" + /* 9113 */ "mul_q.w\t\0" + /* 9122 */ "msubr_q.w\t\0" + /* 9133 */ "maddr_q.w\t\0" + /* 9144 */ "mulr_q.w\t\0" + /* 9154 */ "fceq.w\t\0" + /* 9162 */ "fseq.w\t\0" + /* 9170 */ "fcueq.w\t\0" + /* 9179 */ "fsueq.w\t\0" + /* 9188 */ "ftq.w\t\0" + /* 9195 */ "shra_r.w\t\0" + /* 9205 */ "subqh_r.w\t\0" + /* 9216 */ "addqh_r.w\t\0" + /* 9227 */ "extr_r.w\t\0" + /* 9237 */ "shrav_r.w\t\0" + /* 9248 */ "extrv_r.w\t\0" + /* 9259 */ "srar.w\t\0" + /* 9267 */ "bclr.w\t\0" + /* 9275 */ "srlr.w\t\0" + /* 9283 */ "fcor.w\t\0" + /* 9291 */ "fsor.w\t\0" + /* 9299 */ "fexupr.w\t\0" + /* 9309 */ "ffqr.w\t\0" + /* 9317 */ "binsr.w\t\0" + /* 9326 */ "extr.w\t\0" + /* 9334 */ "ilvr.w\t\0" + /* 9342 */ "cvt.s.w\t\0" + /* 9351 */ "asub_s.w\t\0" + /* 9361 */ "hsub_s.w\t\0" + /* 9371 */ "dpsub_s.w\t\0" + /* 9382 */ "ftrunc_s.w\t\0" + /* 9394 */ "hadd_s.w\t\0" + /* 9404 */ "dpadd_s.w\t\0" + /* 9415 */ "mod_s.w\t\0" + /* 9424 */ "cle_s.w\t\0" + /* 9433 */ "ave_s.w\t\0" + /* 9442 */ "clei_s.w\t\0" + /* 9452 */ "mini_s.w\t\0" + /* 9462 */ "clti_s.w\t\0" + /* 9472 */ "maxi_s.w\t\0" + /* 9482 */ "shll_s.w\t\0" + /* 9492 */ "min_s.w\t\0" + /* 9501 */ "dotp_s.w\t\0" + /* 9511 */ "subq_s.w\t\0" + /* 9521 */ "addq_s.w\t\0" + /* 9531 */ "mulq_s.w\t\0" + /* 9541 */ "absq_s.w\t\0" + /* 9551 */ "aver_s.w\t\0" + /* 9561 */ "subs_s.w\t\0" + /* 9571 */ "adds_s.w\t\0" + /* 9581 */ "sat_s.w\t\0" + /* 9590 */ "clt_s.w\t\0" + /* 9599 */ "ffint_s.w\t\0" + /* 9610 */ "ftint_s.w\t\0" + /* 9621 */ "subsuu_s.w\t\0" + /* 9633 */ "div_s.w\t\0" + /* 9642 */ "shllv_s.w\t\0" + /* 9653 */ "max_s.w\t\0" + /* 9662 */ "copy_s.w\t\0" + /* 9672 */ "mulq_rs.w\t\0" + /* 9683 */ "extr_rs.w\t\0" + /* 9694 */ "extrv_rs.w\t\0" + /* 9706 */ "fclass.w\t\0" + /* 9716 */ "splat.w\t\0" + /* 9725 */ "bset.w\t\0" + /* 9733 */ "fclt.w\t\0" + /* 9741 */ "fslt.w\t\0" + /* 9749 */ "fcult.w\t\0" + /* 9758 */ "fsult.w\t\0" + /* 9767 */ "pcnt.w\t\0" + /* 9775 */ "frint.w\t\0" + /* 9784 */ "insert.w\t\0" + /* 9794 */ "fsqrt.w\t\0" + /* 9803 */ "frsqrt.w\t\0" + /* 9813 */ "st.w\t\0" + /* 9819 */ "asub_u.w\t\0" + /* 9829 */ "hsub_u.w\t\0" + /* 9839 */ "dpsub_u.w\t\0" + /* 9850 */ "ftrunc_u.w\t\0" + /* 9862 */ "hadd_u.w\t\0" + /* 9872 */ "dpadd_u.w\t\0" + /* 9883 */ "mod_u.w\t\0" + /* 9892 */ "cle_u.w\t\0" + /* 9901 */ "ave_u.w\t\0" + /* 9910 */ "clei_u.w\t\0" + /* 9920 */ "mini_u.w\t\0" + /* 9930 */ "clti_u.w\t\0" + /* 9940 */ "maxi_u.w\t\0" + /* 9950 */ "min_u.w\t\0" + /* 9959 */ "dotp_u.w\t\0" + /* 9969 */ "aver_u.w\t\0" + /* 9979 */ "subs_u.w\t\0" + /* 9989 */ "adds_u.w\t\0" + /* 9999 */ "subsus_u.w\t\0" + /* 10011 */ "sat_u.w\t\0" + /* 10020 */ "clt_u.w\t\0" + /* 10029 */ "ffint_u.w\t\0" + /* 10040 */ "ftint_u.w\t\0" + /* 10051 */ "div_u.w\t\0" + /* 10060 */ "max_u.w\t\0" + /* 10069 */ "copy_u.w\t\0" + /* 10079 */ "msubv.w\t\0" + /* 10088 */ "maddv.w\t\0" + /* 10097 */ "pckev.w\t\0" + /* 10106 */ "ilvev.w\t\0" + /* 10115 */ "fdiv.w\t\0" + /* 10123 */ "mulv.w\t\0" + /* 10131 */ "extrv.w\t\0" + /* 10140 */ "fmax.w\t\0" + /* 10148 */ "bz.w\t\0" + /* 10154 */ "bnz.w\t\0" + /* 10161 */ "crc32w\t\0" + /* 10169 */ "crc32cw\t\0" + /* 10178 */ "ualw\t\0" + /* 10184 */ "ulw\t\0" + /* 10189 */ "cvt.ps.pw\t\0" + /* 10200 */ "uasw\t\0" + /* 10206 */ "usw\t\0" + /* 10211 */ "extw\t\0" + /* 10217 */ "byterevw\t\0" + /* 10227 */ "bitrevw\t\0" + /* 10236 */ "lbx\t\0" + /* 10241 */ "sbx\t\0" + /* 10246 */ "prefx\t\0" + /* 10253 */ "lhx\t\0" + /* 10258 */ "shx\t\0" + /* 10263 */ "jalx\t\0" + /* 10269 */ "rotx\t\0" + /* 10275 */ "lbux\t\0" + /* 10281 */ "lhux\t\0" + /* 10287 */ "lwx\t\0" + /* 10292 */ "swx\t\0" + /* 10297 */ "bgez\t\0" + /* 10303 */ "blez\t\0" + /* 10309 */ "bnez\t\0" + /* 10315 */ "selnez\t\0" + /* 10323 */ "btnez\t\0" + /* 10330 */ "dclz\t\0" + /* 10336 */ "beqz\t\0" + /* 10342 */ "seleqz\t\0" + /* 10350 */ "bteqz\t\0" + /* 10357 */ "bgtz\t\0" + /* 10363 */ "bltz\t\0" + /* 10369 */ "movz\t\0" + /* 10375 */ "seb\t \0" + /* 10381 */ "seh\t \0" + /* 10387 */ "ddivu\t$zero, \0" + /* 10401 */ "ddiv\t$zero, \0" + /* 10414 */ "addiu\t$sp, \0" + /* 10426 */ "mftc0 \0" + /* 10433 */ "mttc0 \0" + /* 10440 */ "mfthc1 \0" + /* 10448 */ "mtthc1 \0" + /* 10456 */ "cftc1 \0" + /* 10463 */ "mftc1 \0" + /* 10470 */ "cttc1 \0" + /* 10477 */ "mttc1 \0" + /* 10484 */ "sync \0" + /* 10490 */ "ld \0" + /* 10494 */ "\t.word \0" + /* 10502 */ "sd \0" + /* 10506 */ "sne \0" + /* 10511 */ "mfthi \0" + /* 10518 */ "mtthi \0" + /* 10525 */ "mftlo \0" + /* 10532 */ "mttlo \0" + /* 10539 */ "mftdsp \0" + /* 10547 */ "mttdsp \0" + /* 10555 */ "scwp \0" + /* 10561 */ "llwp \0" + /* 10567 */ "seq \0" + /* 10572 */ "mftgpr \0" + /* 10580 */ "mttgpr \0" + /* 10588 */ "dext \0" + /* 10594 */ "mftacx \0" + /* 10602 */ "mttacx \0" + /* 10610 */ "bc1nez \0" + /* 10618 */ "bc2nez \0" + /* 10626 */ "bc1eqz \0" + /* 10634 */ "bc2eqz \0" + /* 10642 */ "# XRay Function Patchable RET.\0" + /* 10673 */ "c.\0" + /* 10676 */ "# XRay Typed Event Log.\0" + /* 10700 */ "# XRay Custom Event Log.\0" + /* 10725 */ "# XRay Function Enter.\0" + /* 10748 */ "# XRay Tail Call Exit.\0" + /* 10771 */ "# XRay Function Exit.\0" + /* 10793 */ "break 0\0" + /* 10801 */ "nop32\0" + /* 10807 */ "LIFETIME_END\0" + /* 10820 */ "PSEUDO_PROBE\0" + /* 10833 */ "BUNDLE\0" + /* 10840 */ "DBG_VALUE\0" + /* 10850 */ "DBG_INSTR_REF\0" + /* 10864 */ "DBG_PHI\0" + /* 10872 */ "DBG_LABEL\0" + /* 10882 */ "LIFETIME_START\0" + /* 10897 */ "DBG_VALUE_LIST\0" + /* 10912 */ "jrc\t$ra\0" + /* 10920 */ "jr\t$ra\0" + /* 10927 */ "ehb\0" + /* 10931 */ "eretnc\0" + /* 10938 */ "pause\0" + /* 10944 */ "tlbinvf\0" + /* 10952 */ "tlbginvf\0" + /* 10961 */ "tlbwi\0" + /* 10967 */ "tlbgwi\0" + /* 10974 */ "# FEntry call\0" + /* 10988 */ "foo\0" + /* 10992 */ "tlbp\0" + /* 10997 */ "tlbgp\0" + /* 11003 */ "ssnop\0" + /* 11009 */ "tlbr\0" + /* 11014 */ "tlbgr\0" + /* 11020 */ "tlbwr\0" + /* 11026 */ "tlbgwr\0" + /* 11033 */ "deret\0" + /* 11039 */ "wait\0" + /* 11044 */ "tlbinv\0" + /* 11051 */ "tlbginv\0" +}; +#endif // CAPSTONE_DIET + + static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM + 0U, // INLINEASM_BR 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS - 9396U, // DBG_VALUE + 10841U, // DBG_VALUE + 10898U, // DBG_VALUE_LIST + 10851U, // DBG_INSTR_REF + 10865U, // DBG_PHI + 10873U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY - 9389U, // BUNDLE - 9406U, // LIFETIME_START - 9376U, // LIFETIME_END + 10834U, // BUNDLE + 10883U, // LIFETIME_START + 10808U, // LIFETIME_END + 10821U, // PSEUDO_PROBE + 0U, // ARITH_FENCE 0U, // STACKMAP + 10975U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG 0U, // STATEPOINT - 0U, // FRAME_ALLOC - 21660U, // ABSQ_S_PH - 18025U, // ABSQ_S_QB - 24850U, // ABSQ_S_W - 134237992U, // ADD - 18294U, // ADDIUPC - 18294U, // ADDIUPC_MM - 22527U, // ADDIUR1SP_MM - 134234410U, // ADDIUR2_MM - 8683851U, // ADDIUS5_MM - 546875U, // ADDIUSP_MM - 134239193U, // ADDQH_PH - 134239310U, // ADDQH_R_PH - 134242253U, // ADDQH_R_W - 134241856U, // ADDQH_W - 134239267U, // ADDQ_PH - 134239366U, // ADDQ_S_PH - 134242558U, // ADDQ_S_W - 134236055U, // ADDSC - 134234730U, // ADDS_A_B - 134236180U, // ADDS_A_D - 134238138U, // ADDS_A_H - 134241564U, // ADDS_A_W - 134235198U, // ADDS_S_B - 134237269U, // ADDS_S_D - 134238695U, // ADDS_S_H - 134242608U, // ADDS_S_W - 134235413U, // ADDS_U_B - 134237736U, // ADDS_U_D - 134238973U, // ADDS_U_H - 134243026U, // ADDS_U_W - 134234575U, // ADDU16_MM - 134235621U, // ADDUH_QB - 134235729U, // ADDUH_R_QB - 134239465U, // ADDU_PH - 134235834U, // ADDU_QB - 134239410U, // ADDU_S_PH - 134235775U, // ADDU_S_QB - 2281718627U, // ADDVI_B - 2281720348U, // ADDVI_D - 2281722002U, // ADDVI_H - 2281725637U, // ADDVI_W - 134235491U, // ADDV_B - 134237836U, // ADDV_D - 134239051U, // ADDV_H - 134243126U, // ADDV_W - 134236094U, // ADDWC - 134234712U, // ADD_A_B - 134236161U, // ADD_A_D - 134238120U, // ADD_A_H - 134241545U, // ADD_A_W - 134237992U, // ADD_MM - 134239685U, // ADDi - 134239685U, // ADDi_MM - 134241307U, // ADDiu - 134241307U, // ADDiu_MM - 134241261U, // ADDu - 134241261U, // ADDu_MM + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 10726U, // PATCHABLE_FUNCTION_ENTER + 10643U, // PATCHABLE_RET + 10772U, // PATCHABLE_FUNCTION_EXIT + 10749U, // PATCHABLE_TAIL_CALL + 10701U, // PATCHABLE_EVENT_CALL + 10677U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // MEMBARRIER + 0U, // JUMP_TABLE_DEBUG_INFO + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ASSERT_ALIGN + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_CONSTANT_POOL + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_CONSTANT_FOLD_BARRIER + 0U, // G_INTRINSIC_FPTRUNC_ROUND + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_ATOMICRMW_FMAX + 0U, // G_ATOMICRMW_FMIN + 0U, // G_ATOMICRMW_UINC_WRAP + 0U, // G_ATOMICRMW_UDEC_WRAP + 0U, // G_FENCE + 0U, // G_PREFETCH + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INVOKE_REGION_START + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_INTRINSIC_CONVERGENT + 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FEXP10 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FLDEXP + 0U, // G_FFREXP + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_IS_FPCLASS + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_GET_FPENV + 0U, // G_SET_FPENV + 0U, // G_RESET_FPENV + 0U, // G_GET_FPMODE + 0U, // G_SET_FPMODE + 0U, // G_RESET_FPMODE + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STACKSAVE + 0U, // G_STACKRESTORE + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_STRICT_FLDEXP + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_FMAXIMUM + 0U, // G_VECREDUCE_FMINIMUM + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 24254U, // ABSMacro 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKDOWN_NM 0U, // ADJCALLSTACKUP - 134240158U, // ALIGN - 18286U, // ALUIPC - 134238014U, // AND - 835930U, // AND16_MM - 134238014U, // AND64 - 134234471U, // ANDI16_MM - 2281718486U, // ANDI_B - 134238014U, // AND_MM - 134241389U, // AND_V + 0U, // ADJCALLSTACKUP_NM + 536894083U, // ALIGN_NM 0U, // AND_V_D_PSEUDO 0U, // AND_V_H_PSEUDO 0U, // AND_V_W_PSEUDO - 134239691U, // ANDi - 134239691U, // ANDi64 - 134239691U, // ANDi_MM - 134238028U, // APPEND - 134235092U, // ASUB_S_B - 134237099U, // ASUB_S_D - 134238527U, // ASUB_S_H - 134242388U, // ASUB_S_W - 134235307U, // ASUB_U_B - 134237566U, // ASUB_U_D - 134238815U, // ASUB_U_H - 134242856U, // ASUB_U_W 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I16_POSTRA 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I32_POSTRA 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I64_POSTRA 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_CMP_SWAP_I8_POSTRA 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I16_POSTRA 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I32_POSTRA 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I64_POSTRA 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_ADD_I8_POSTRA 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I16_POSTRA 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I32_POSTRA 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I64_POSTRA 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_AND_I8_POSTRA + 0U, // ATOMIC_LOAD_MAX_I16 + 0U, // ATOMIC_LOAD_MAX_I16_POSTRA + 0U, // ATOMIC_LOAD_MAX_I32 + 0U, // ATOMIC_LOAD_MAX_I32_POSTRA + 0U, // ATOMIC_LOAD_MAX_I64 + 0U, // ATOMIC_LOAD_MAX_I64_POSTRA + 0U, // ATOMIC_LOAD_MAX_I8 + 0U, // ATOMIC_LOAD_MAX_I8_POSTRA + 0U, // ATOMIC_LOAD_MIN_I16 + 0U, // ATOMIC_LOAD_MIN_I16_POSTRA + 0U, // ATOMIC_LOAD_MIN_I32 + 0U, // ATOMIC_LOAD_MIN_I32_POSTRA + 0U, // ATOMIC_LOAD_MIN_I64 + 0U, // ATOMIC_LOAD_MIN_I64_POSTRA + 0U, // ATOMIC_LOAD_MIN_I8 + 0U, // ATOMIC_LOAD_MIN_I8_POSTRA 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I16_POSTRA 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I32_POSTRA 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I64_POSTRA 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_NAND_I8_POSTRA 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I16_POSTRA 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I32_POSTRA 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I64_POSTRA 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_OR_I8_POSTRA 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I16_POSTRA 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I32_POSTRA 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I64_POSTRA 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_SUB_I8_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I16 + 0U, // ATOMIC_LOAD_UMAX_I16_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I32 + 0U, // ATOMIC_LOAD_UMAX_I32_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I64 + 0U, // ATOMIC_LOAD_UMAX_I64_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I8 + 0U, // ATOMIC_LOAD_UMAX_I8_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I16 + 0U, // ATOMIC_LOAD_UMIN_I16_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I32 + 0U, // ATOMIC_LOAD_UMIN_I32_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I64 + 0U, // ATOMIC_LOAD_UMIN_I64_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I8 + 0U, // ATOMIC_LOAD_UMIN_I8_POSTRA 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I16_POSTRA 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I32_POSTRA 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I64_POSTRA 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_LOAD_XOR_I8_POSTRA 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I16_POSTRA 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I32_POSTRA 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I64_POSTRA 0U, // ATOMIC_SWAP_I8 - 134239795U, // AUI - 18279U, // AUIPC - 134235178U, // AVER_S_B - 134237249U, // AVER_S_D - 134238665U, // AVER_S_H - 134242588U, // AVER_S_W - 134235393U, // AVER_U_B - 134237716U, // AVER_U_D - 134238953U, // AVER_U_H - 134243006U, // AVER_U_W - 134235120U, // AVE_S_B - 134237181U, // AVE_S_D - 134238597U, // AVE_S_H - 134242470U, // AVE_S_W - 134235335U, // AVE_U_B - 134237648U, // AVE_U_D - 134238885U, // AVE_U_H - 134242938U, // AVE_U_W - 23579U, // AddiuRxImmX16 - 1072155U, // AddiuRxPcImmX16 - 285236251U, // AddiuRxRxImm16 - 16800795U, // AddiuRxRxImmX16 - 25189403U, // AddiuRxRyOffMemX16 - 1336343U, // AddiuSpImm16 - 549911U, // AddiuSpImmX16 - 134241261U, // AdduRxRyRz16 - 16797502U, // AndRxRxRy16 + 0U, // ATOMIC_SWAP_I8_POSTRA 0U, // B - 541013U, // B16_MM - 134241260U, // BADDu - 546393U, // BAL - 542494U, // BALC - 134240157U, // BALIGN 0U, // BAL_BR - 167788585U, // BBIT0 - 167788717U, // BBIT032 - 167788710U, // BBIT1 - 167788726U, // BBIT132 - 542473U, // BC - 20351U, // BC0F - 22218U, // BC0FL - 23455U, // BC0T - 22347U, // BC0TL - 25733U, // BC1EQZ - 20357U, // BC1F - 22225U, // BC1FL - 20357U, // BC1F_MM - 25717U, // BC1NEZ - 23461U, // BC1T - 22354U, // BC1TL - 23461U, // BC1T_MM - 25741U, // BC2EQZ - 20363U, // BC2F - 22232U, // BC2FL - 25725U, // BC2NEZ - 23467U, // BC2T - 22361U, // BC2TL - 20369U, // BC3F - 22239U, // BC3FL - 23473U, // BC3T - 22368U, // BC3TL - 2281718555U, // BCLRI_B - 2281720292U, // BCLRI_D - 2281721946U, // BCLRI_H - 2281725581U, // BCLRI_W - 134235059U, // BCLR_B - 134237023U, // BCLR_D - 134238494U, // BCLR_H - 134242304U, // BCLR_W - 134240340U, // BEQ - 134240340U, // BEQ64 - 134236044U, // BEQC - 134240063U, // BEQL - 16882U, // BEQZ16_MM - 18246U, // BEQZALC - 18394U, // BEQZC - 18394U, // BEQZC_MM - 134240340U, // BEQ_MM - 134235917U, // BGEC - 134236068U, // BGEUC - 25500U, // BGEZ - 25500U, // BGEZ64 - 22115U, // BGEZAL - 18219U, // BGEZALC - 22311U, // BGEZALL - 23424U, // BGEZALS_MM - 22115U, // BGEZAL_MM - 18373U, // BGEZC - 22391U, // BGEZL - 25500U, // BGEZ_MM - 25560U, // BGTZ - 25560U, // BGTZ64 - 18255U, // BGTZALC - 18401U, // BGTZC - 22405U, // BGTZL - 25560U, // BGTZ_MM - 2298495744U, // BINSLI_B - 2298497481U, // BINSLI_D - 2298499135U, // BINSLI_H - 2298502770U, // BINSLI_W - 151012243U, // BINSL_B - 151014033U, // BINSL_D - 151015601U, // BINSL_H - 151019280U, // BINSL_W - 2298495805U, // BINSRI_B - 2298497526U, // BINSRI_D - 2298499180U, // BINSRI_H - 2298502815U, // BINSRI_W - 151012291U, // BINSR_B - 151014289U, // BINSR_D - 151015726U, // BINSR_H - 151019570U, // BINSR_W - 23733U, // BITREV - 22477U, // BITSWAP - 25506U, // BLEZ - 25506U, // BLEZ64 - 18228U, // BLEZALC - 18380U, // BLEZC - 22398U, // BLEZL - 25506U, // BLEZ_MM - 134236062U, // BLTC - 134236075U, // BLTUC - 25566U, // BLTZ - 25566U, // BLTZ64 - 22123U, // BLTZAL - 18264U, // BLTZALC - 22320U, // BLTZALL - 23433U, // BLTZALS_MM - 22123U, // BLTZAL_MM - 18408U, // BLTZC - 22412U, // BLTZL - 25566U, // BLTZ_MM - 2298495860U, // BMNZI_B - 151018662U, // BMNZ_V - 2298495852U, // BMZI_B - 151018648U, // BMZ_V - 134238058U, // BNE - 134238058U, // BNE64 - 134235923U, // BNEC - 2281718494U, // BNEGI_B - 2281720240U, // BNEGI_D - 2281721894U, // BNEGI_H - 2281725529U, // BNEGI_W - 134234814U, // BNEG_B - 134236568U, // BNEG_D - 134238222U, // BNEG_H - 134241776U, // BNEG_W - 134239940U, // BNEL - 16874U, // BNEZ16_MM - 18237U, // BNEZALC - 18387U, // BNEZC - 18387U, // BNEZC_MM - 134238058U, // BNE_MM - 134236082U, // BNVC - 17803U, // BNZ_B - 20233U, // BNZ_D - 21363U, // BNZ_H - 23711U, // BNZ_V - 25463U, // BNZ_W - 134236088U, // BOVC - 540871U, // BPOSGE32 + 0U, // BAL_BR_MM + 536893945U, // BEQLImmMacro + 536891762U, // BGE + 536891762U, // BGEImmMacro + 536893806U, // BGEL + 536893806U, // BGELImmMacro + 536895461U, // BGEU + 536895461U, // BGEUImmMacro + 536893976U, // BGEUL + 536893976U, // BGEULImmMacro + 536895342U, // BGT + 536895342U, // BGTImmMacro + 536893964U, // BGTL + 536893964U, // BGTLImmMacro + 536895587U, // BGTU + 536895587U, // BGTUImmMacro + 536893996U, // BGTUL + 536893996U, // BGTULImmMacro + 536891802U, // BLE + 536891802U, // BLEImmMacro + 536893812U, // BLEL + 536893812U, // BLELImmMacro + 536895479U, // BLEU + 536895479U, // BLEUImmMacro + 536893983U, // BLEUL + 536893983U, // BLEULImmMacro + 536895358U, // BLT + 536895358U, // BLTImmMacro + 536893970U, // BLTL + 536893970U, // BLTLImmMacro + 536895599U, // BLTU + 536895599U, // BLTUImmMacro + 536894003U, // BLTUL + 536894003U, // BLTULImmMacro + 536893818U, // BNELImmMacro 0U, // BPOSGE32_PSEUDO - 22080U, // BREAK - 65909U, // BREAK16_MM - 22080U, // BREAK_MM - 2298495719U, // BSELI_B 0U, // BSEL_D_PSEUDO 0U, // BSEL_FD_PSEUDO 0U, // BSEL_FW_PSEUDO 0U, // BSEL_H_PSEUDO - 151018620U, // BSEL_V 0U, // BSEL_W_PSEUDO - 2281718609U, // BSETI_B - 2281720330U, // BSETI_D - 2281721984U, // BSETI_H - 2281725619U, // BSETI_W - 134235275U, // BSET_B - 134237385U, // BSET_D - 134238783U, // BSET_H - 134242762U, // BSET_W - 17797U, // BZ_B - 20217U, // BZ_D - 21357U, // BZ_H - 23698U, // BZ_V - 25457U, // BZ_W - 541278U, // B_MM_Pseudo - 402678723U, // BeqzRxImm16 - 25539U, // BeqzRxImmX16 - 1327710U, // Bimm16 - 541278U, // BimmX16 - 402678696U, // BnezRxImm16 - 25512U, // BnezRxImmX16 - 9368U, // Break16 - 1598417U, // Bteqz16 - 536893428U, // BteqzT8CmpX16 - 536892936U, // BteqzT8CmpiX16 - 536894397U, // BteqzT8SltX16 - 536892966U, // BteqzT8SltiX16 - 536894505U, // BteqzT8SltiuX16 - 536894541U, // BteqzT8SltuX16 - 549841U, // BteqzX16 - 1598390U, // Btnez16 - 671111156U, // BtnezT8CmpX16 - 671110664U, // BtnezT8CmpiX16 - 671112125U, // BtnezT8SltX16 - 671110694U, // BtnezT8SltiX16 - 671112233U, // BtnezT8SltiuX16 - 671112269U, // BtnezT8SltuX16 - 549814U, // BtnezX16 + 0U, // B_MM + 557961U, // B_MMR6_Pseudo + 557961U, // B_MM_Pseudo + 536894300U, // BeqImm + 536891829U, // BneImm + 1073765088U, // BteqzT8CmpX16 + 1073764517U, // BteqzT8CmpiX16 + 1073766275U, // BteqzT8SltX16 + 1073764547U, // BteqzT8SltiX16 + 1073766431U, // BteqzT8SltiuX16 + 1073766517U, // BteqzT8SltuX16 + 1610636000U, // BtnezT8CmpX16 + 1610635429U, // BtnezT8CmpiX16 + 1610637187U, // BtnezT8SltX16 + 1610635459U, // BtnezT8SltiX16 + 1610637343U, // BtnezT8SltiuX16 + 1610637429U, // BtnezT8SltuX16 0U, // BuildPairF64 0U, // BuildPairF64_64 - 85859U, // CACHE - 85859U, // CACHE_MM - 85859U, // CACHE_R6 - 19003U, // CEIL_L_D64 - 23031U, // CEIL_L_S - 20179U, // CEIL_W_D32 - 20179U, // CEIL_W_D64 - 20179U, // CEIL_W_MM - 23353U, // CEIL_W_S - 23353U, // CEIL_W_S_MM - 134234890U, // CEQI_B - 134236627U, // CEQI_D - 134238281U, // CEQI_H - 134241916U, // CEQI_W - 134235044U, // CEQ_B - 134236930U, // CEQ_D - 134238472U, // CEQ_H - 134242192U, // CEQ_W - 16444U, // CFC1 - 16444U, // CFC1_MM - 16968U, // CFCMSA - 134243407U, // CINS - 134243363U, // CINS32 - 19639U, // CLASS_D - 23205U, // CLASS_S - 134235129U, // CLEI_S_B - 134237190U, // CLEI_S_D - 134238606U, // CLEI_S_H - 134242479U, // CLEI_S_W - 2281718992U, // CLEI_U_B - 2281721305U, // CLEI_U_D - 2281722542U, // CLEI_U_H - 2281726595U, // CLEI_U_W - 134235111U, // CLE_S_B - 134237172U, // CLE_S_D - 134238588U, // CLE_S_H - 134242461U, // CLE_S_W - 134235326U, // CLE_U_B - 134237639U, // CLE_U_D - 134238876U, // CLE_U_H - 134242929U, // CLE_U_W - 22452U, // CLO - 22452U, // CLO_MM - 22452U, // CLO_R6 - 134235149U, // CLTI_S_B - 134237210U, // CLTI_S_D - 134238626U, // CLTI_S_H - 134242499U, // CLTI_S_W - 2281719012U, // CLTI_U_B - 2281721325U, // CLTI_U_D - 2281722562U, // CLTI_U_H - 2281726615U, // CLTI_U_W - 134235217U, // CLT_S_B - 134237288U, // CLT_S_D - 134238714U, // CLT_S_H - 134242627U, // CLT_S_W - 134235444U, // CLT_U_B - 134237767U, // CLT_U_D - 134239004U, // CLT_U_H - 134243057U, // CLT_U_W - 25534U, // CLZ - 25534U, // CLZ_MM - 25534U, // CLZ_R6 - 134235667U, // CMPGDU_EQ_QB - 134235572U, // CMPGDU_LE_QB - 134235786U, // CMPGDU_LT_QB - 134235681U, // CMPGU_EQ_QB - 134235586U, // CMPGU_LE_QB - 134235800U, // CMPGU_LT_QB - 17966U, // CMPU_EQ_QB - 17871U, // CMPU_LE_QB - 18085U, // CMPU_LT_QB - 134236919U, // CMP_EQ_D - 21548U, // CMP_EQ_PH - 134240864U, // CMP_EQ_S - 134236489U, // CMP_F_D - 134240675U, // CMP_F_S - 134236333U, // CMP_LE_D - 21444U, // CMP_LE_PH - 134240596U, // CMP_LE_S - 134237410U, // CMP_LT_D - 21717U, // CMP_LT_PH - 134240959U, // CMP_LT_S - 134236507U, // CMP_SAF_D - 134240685U, // CMP_SAF_S - 134236946U, // CMP_SEQ_D - 134240883U, // CMP_SEQ_S - 134236370U, // CMP_SLE_D - 134240625U, // CMP_SLE_S - 134237437U, // CMP_SLT_D - 134240978U, // CMP_SLT_S - 134236994U, // CMP_SUEQ_D - 134240914U, // CMP_SUEQ_S - 134236418U, // CMP_SULE_D - 134240656U, // CMP_SULE_S - 134237485U, // CMP_SULT_D - 134241009U, // CMP_SULT_S - 134236876U, // CMP_SUN_D - 134240837U, // CMP_SUN_S - 134236974U, // CMP_UEQ_D - 134240903U, // CMP_UEQ_S - 134236398U, // CMP_ULE_D - 134240645U, // CMP_ULE_S - 134237465U, // CMP_ULT_D - 134240998U, // CMP_ULT_S - 134236858U, // CMP_UN_D - 134240827U, // CMP_UN_S - 9454U, // CONSTPOOL_ENTRY + 26841U, // CFTC1 + 10989U, // CONSTPOOL_ENTRY 0U, // COPY_FD_PSEUDO 0U, // COPY_FW_PSEUDO - 2952807544U, // COPY_S_B - 2952809637U, // COPY_S_D - 2952811052U, // COPY_S_H - 2952814987U, // COPY_S_W - 2952807759U, // COPY_U_B - 2952810104U, // COPY_U_D - 2952811319U, // COPY_U_H - 2952815394U, // COPY_U_W - 1867863U, // CTC1 - 1867863U, // CTC1_MM - 16976U, // CTCMSA - 22833U, // CVT_D32_S - 23896U, // CVT_D32_W - 23896U, // CVT_D32_W_MM - 22087U, // CVT_D64_L - 22833U, // CVT_D64_S - 23896U, // CVT_D64_W - 22833U, // CVT_D_S_MM - 19024U, // CVT_L_D64 - 19024U, // CVT_L_D64_MM - 23052U, // CVT_L_S - 23052U, // CVT_L_S_MM - 19362U, // CVT_S_D32 - 19362U, // CVT_S_D32_MM - 19362U, // CVT_S_D64 - 22096U, // CVT_S_L - 24651U, // CVT_S_W - 24651U, // CVT_S_W_MM - 20200U, // CVT_W_D32 - 20200U, // CVT_W_D64 - 20200U, // CVT_W_MM - 23374U, // CVT_W_S - 23374U, // CVT_W_S_MM - 19183U, // C_EQ_D32 - 19183U, // C_EQ_D64 - 23128U, // C_EQ_S - 18754U, // C_F_D32 - 18754U, // C_F_D64 - 22940U, // C_F_S - 18597U, // C_LE_D32 - 18597U, // C_LE_D64 - 22860U, // C_LE_S - 19674U, // C_LT_D32 - 19674U, // C_LT_D64 - 23223U, // C_LT_S - 18588U, // C_NGE_D32 - 18588U, // C_NGE_D64 - 22851U, // C_NGE_S - 18623U, // C_NGLE_D32 - 18623U, // C_NGLE_D64 - 22878U, // C_NGLE_S - 19040U, // C_NGL_D32 - 19040U, // C_NGL_D64 - 23068U, // C_NGL_S - 19665U, // C_NGT_D32 - 19665U, // C_NGT_D64 - 23214U, // C_NGT_S - 18633U, // C_OLE_D32 - 18633U, // C_OLE_D64 - 22888U, // C_OLE_S - 19700U, // C_OLT_D32 - 19700U, // C_OLT_D64 - 23241U, // C_OLT_S - 19209U, // C_SEQ_D32 - 19209U, // C_SEQ_D64 - 23146U, // C_SEQ_S - 18824U, // C_SF_D32 - 18824U, // C_SF_D64 - 22986U, // C_SF_S - 19237U, // C_UEQ_D32 - 19237U, // C_UEQ_D64 - 23166U, // C_UEQ_S - 18661U, // C_ULE_D32 - 18661U, // C_ULE_D64 - 22908U, // C_ULE_S - 19728U, // C_ULT_D32 - 19728U, // C_ULT_D64 - 23261U, // C_ULT_S - 19122U, // C_UN_D32 - 19122U, // C_UN_D64 - 23091U, // C_UN_S - 22516U, // CmpRxRy16 - 939546120U, // CmpiRxImm16 - 22024U, // CmpiRxImmX16 - 549945U, // Constant32 - 134237991U, // DADD - 134239684U, // DADDi - 134241306U, // DADDiu - 134241267U, // DADDu - 8689123U, // DAHI - 134240165U, // DALIGN - 8689184U, // DATI - 134239794U, // DAUI - 22476U, // DBITSWAP - 22451U, // DCLO - 22451U, // DCLO_R6 - 25533U, // DCLZ - 25533U, // DCLZ_R6 - 134241469U, // DDIV - 134241377U, // DDIVU - 9480U, // DERET - 9480U, // DERET_MM - 134243425U, // DEXT - 134243400U, // DEXTM - 134243438U, // DEXTU - 546247U, // DI - 134243413U, // DINS - 134243393U, // DINSM - 134243431U, // DINSU - 134241470U, // DIV - 134241378U, // DIVU - 134235238U, // DIV_S_B - 134237331U, // DIV_S_D - 134238735U, // DIV_S_H - 134242670U, // DIV_S_W - 134235453U, // DIV_U_B - 134237798U, // DIV_U_D - 134239013U, // DIV_U_H - 134243088U, // DIV_U_W - 546247U, // DI_MM - 134234690U, // DLSA - 134234690U, // DLSA_R6 - 134234121U, // DMFC0 - 16450U, // DMFC1 - 134234372U, // DMFC2 - 134238036U, // DMOD - 134241281U, // DMODU - 134234128U, // DMTC0 - 1867869U, // DMTC1 - 134234379U, // DMTC2 - 134239671U, // DMUH - 134241299U, // DMUHU - 134240103U, // DMUL - 23495U, // DMULT - 23641U, // DMULTu - 134241343U, // DMULU - 134240103U, // DMUL_R6 - 134237239U, // DOTP_S_D - 134238655U, // DOTP_S_H - 134242538U, // DOTP_S_W - 134237706U, // DOTP_U_D - 134238943U, // DOTP_U_H - 134242996U, // DOTP_U_W - 151014368U, // DPADD_S_D - 151015784U, // DPADD_S_H - 151019657U, // DPADD_S_W - 151014835U, // DPADD_U_D - 151016072U, // DPADD_U_H - 151020125U, // DPADD_U_W - 134239524U, // DPAQX_SA_W_PH - 134239607U, // DPAQX_S_W_PH - 134241998U, // DPAQ_SA_L_W - 134239566U, // DPAQ_S_W_PH - 134239859U, // DPAU_H_QBL - 134240355U, // DPAU_H_QBR - 134239645U, // DPAX_W_PH - 134239514U, // DPA_W_PH - 22521U, // DPOP - 134239539U, // DPSQX_SA_W_PH - 134239621U, // DPSQX_S_W_PH - 134242011U, // DPSQ_SA_L_W - 134239594U, // DPSQ_S_W_PH - 151014335U, // DPSUB_S_D - 151015763U, // DPSUB_S_H - 151019624U, // DPSUB_S_W - 151014802U, // DPSUB_U_D - 151016051U, // DPSUB_U_H - 151020092U, // DPSUB_U_W - 134239871U, // DPSU_H_QBL - 134240367U, // DPSU_H_QBR - 134239656U, // DPSX_W_PH - 134239635U, // DPS_W_PH - 134240512U, // DROTR - 134234351U, // DROTR32 - 134241513U, // DROTRV - 21370U, // DSBH - 25610U, // DSDIV - 20275U, // DSHD - 134240057U, // DSLL - 134234321U, // DSLL32 - 1073764153U, // DSLL64_32 - 134241475U, // DSLLV - 134234684U, // DSRA - 134234303U, // DSRA32 - 134241454U, // DSRAV - 134240069U, // DSRL - 134234329U, // DSRL32 - 134241482U, // DSRLV - 134235901U, // DSUB - 134241246U, // DSUBu - 25596U, // DUDIV - 25611U, // DivRxRy16 - 25597U, // DivuRxRy16 - 9438U, // EHB - 9438U, // EHB_MM - 546259U, // EI - 546259U, // EI_MM - 9481U, // ERET - 9481U, // ERET_MM - 134243426U, // EXT - 134240324U, // EXTP - 134240221U, // EXTPDP - 134241497U, // EXTPDPV - 134241506U, // EXTPV - 134242731U, // EXTRV_RS_W - 134242285U, // EXTRV_R_W - 134238744U, // EXTRV_S_H - 134243168U, // EXTRV_W - 134242720U, // EXTR_RS_W - 134242264U, // EXTR_R_W - 134238675U, // EXTR_S_H - 134242363U, // EXTR_W - 134243419U, // EXTS - 134243371U, // EXTS32 - 134243426U, // EXT_MM + 17885415U, // CTTC1 + 551167U, // Constant32 + 536893990U, // DMULImmMacro + 536893990U, // DMULMacro + 536894129U, // DMULOMacro + 536895562U, // DMULOUMacro + 536893929U, // DROL + 536893929U, // DROLImm + 536894467U, // DROR + 536894467U, // DRORImm + 536895724U, // DSDivIMacro + 536895724U, // DSDivMacro + 536894048U, // DSRemIMacro + 536894048U, // DSRemMacro + 536895632U, // DUDivIMacro + 536895632U, // DUDivMacro + 536895555U, // DURemIMacro + 536895555U, // DURemMacro + 0U, // ERet 0U, // ExtractElementF64 0U, // ExtractElementF64_64 0U, // FABS_D - 19631U, // FABS_D32 - 19631U, // FABS_D64 - 19631U, // FABS_MM - 23198U, // FABS_S - 23198U, // FABS_S_MM 0U, // FABS_W - 134236265U, // FADD_D - 134236266U, // FADD_D32 - 134236266U, // FADD_D64 - 134236266U, // FADD_MM - 134240572U, // FADD_S - 134240572U, // FADD_S_MM - 134241633U, // FADD_W - 134236499U, // FCAF_D - 134241752U, // FCAF_W - 134236929U, // FCEQ_D - 134242191U, // FCEQ_W - 19638U, // FCLASS_D - 25015U, // FCLASS_W - 134236343U, // FCLE_D - 134241675U, // FCLE_W - 134237420U, // FCLT_D - 134242770U, // FCLT_W - 2204821U, // FCMP_D32 - 2204821U, // FCMP_D32_MM - 2204821U, // FCMP_D64 - 2466965U, // FCMP_S32 - 2466965U, // FCMP_S32_MM - 134236439U, // FCNE_D - 134241709U, // FCNE_W - 134237039U, // FCOR_D - 134242320U, // FCOR_W - 134236985U, // FCUEQ_D - 134242207U, // FCUEQ_W - 134236409U, // FCULE_D - 134241691U, // FCULE_W - 134237476U, // FCULT_D - 134242786U, // FCULT_W - 134236455U, // FCUNE_D - 134241725U, // FCUNE_W - 134236868U, // FCUN_D - 134242097U, // FCUN_W - 134237862U, // FDIV_D - 134237863U, // FDIV_D32 - 134237863U, // FDIV_D64 - 134237863U, // FDIV_MM - 134241045U, // FDIV_S - 134241045U, // FDIV_S_MM - 134243152U, // FDIV_W - 134238402U, // FEXDO_H - 134242113U, // FEXDO_W - 134236152U, // FEXP2_D 0U, // FEXP2_D_1_PSEUDO - 134241536U, // FEXP2_W 0U, // FEXP2_W_1_PSEUDO - 19064U, // FEXUPL_D - 24311U, // FEXUPL_W - 19327U, // FEXUPR_D - 24608U, // FEXUPR_W - 19569U, // FFINT_S_D - 24908U, // FFINT_S_W - 20048U, // FFINT_U_D - 25338U, // FFINT_U_W - 19074U, // FFQL_D - 24321U, // FFQL_W - 19337U, // FFQR_D - 24618U, // FFQR_W - 17277U, // FILL_B - 19049U, // FILL_D 0U, // FILL_FD_PSEUDO 0U, // FILL_FW_PSEUDO - 20635U, // FILL_H - 24296U, // FILL_W - 18415U, // FLOG2_D - 23799U, // FLOG2_W - 19013U, // FLOOR_L_D64 - 23041U, // FLOOR_L_S - 20189U, // FLOOR_W_D32 - 20189U, // FLOOR_W_D64 - 20189U, // FLOOR_W_MM - 23363U, // FLOOR_W_S - 23363U, // FLOOR_W_S_MM - 151013489U, // FMADD_D - 151018857U, // FMADD_W - 134236190U, // FMAX_A_D - 134241574U, // FMAX_A_W - 134237937U, // FMAX_D - 134243177U, // FMAX_W - 134236170U, // FMIN_A_D - 134241554U, // FMIN_A_W - 134236842U, // FMIN_D - 134242089U, // FMIN_W - 20150U, // FMOV_D32 - 20150U, // FMOV_D32_MM - 20150U, // FMOV_D64 - 23324U, // FMOV_S - 23324U, // FMOV_S_MM - 151013447U, // FMSUB_D - 151018815U, // FMSUB_W - 134236826U, // FMUL_D - 134236827U, // FMUL_D32 - 134236827U, // FMUL_D64 - 134236827U, // FMUL_MM - 134240805U, // FMUL_S - 134240805U, // FMUL_S_MM - 134242073U, // FMUL_W - 18841U, // FNEG_D32 - 18841U, // FNEG_D64 - 18841U, // FNEG_MM - 23002U, // FNEG_S - 23002U, // FNEG_S_MM - 19175U, // FRCP_D - 24394U, // FRCP_W - 19786U, // FRINT_D - 25084U, // FRINT_W - 19814U, // FRSQRT_D - 25112U, // FRSQRT_W - 134236518U, // FSAF_D - 134241760U, // FSAF_W - 134236957U, // FSEQ_D - 134242199U, // FSEQ_W - 134236381U, // FSLE_D - 134241683U, // FSLE_W - 134237448U, // FSLT_D - 134242778U, // FSLT_W - 134236447U, // FSNE_D - 134241717U, // FSNE_W - 134237047U, // FSOR_D - 134242328U, // FSOR_W - 19805U, // FSQRT_D - 19806U, // FSQRT_D32 - 19806U, // FSQRT_D64 - 19806U, // FSQRT_MM - 23301U, // FSQRT_S - 23301U, // FSQRT_S_MM - 25103U, // FSQRT_W - 134236223U, // FSUB_D - 134236224U, // FSUB_D32 - 134236224U, // FSUB_D64 - 134236224U, // FSUB_MM - 134240554U, // FSUB_S - 134240554U, // FSUB_S_MM - 134241591U, // FSUB_W - 134237006U, // FSUEQ_D - 134242216U, // FSUEQ_W - 134236430U, // FSULE_D - 134241700U, // FSULE_W - 134237497U, // FSULT_D - 134242795U, // FSULT_W - 134236464U, // FSUNE_D - 134241734U, // FSUNE_W - 134236887U, // FSUN_D - 134242105U, // FSUN_W - 19580U, // FTINT_S_D - 24919U, // FTINT_S_W - 20059U, // FTINT_U_D - 25349U, // FTINT_U_W - 134238479U, // FTQ_H - 134242225U, // FTQ_W - 19402U, // FTRUNC_S_D - 24691U, // FTRUNC_S_W - 19869U, // FTRUNC_U_D - 25159U, // FTRUNC_U_W - 1224758783U, // GotPrologue16 - 134237142U, // HADD_S_D - 134238558U, // HADD_S_H - 134242431U, // HADD_S_W - 134237609U, // HADD_U_D - 134238846U, // HADD_U_H - 134242899U, // HADD_U_W - 134237109U, // HSUB_S_D - 134238537U, // HSUB_S_H - 134242398U, // HSUB_S_W - 134237576U, // HSUB_U_D - 134238825U, // HSUB_U_H - 134242866U, // HSUB_U_W - 134235508U, // ILVEV_B - 134237853U, // ILVEV_D - 134239068U, // ILVEV_H - 134243143U, // ILVEV_W - 134235036U, // ILVL_B - 134236834U, // ILVL_D - 134238394U, // ILVL_H - 134242081U, // ILVL_W - 134234788U, // ILVOD_B - 134236307U, // ILVOD_D - 134238196U, // ILVOD_H - 134241666U, // ILVOD_W - 134235084U, // ILVR_B - 134237082U, // ILVR_D - 134238519U, // ILVR_H - 134242371U, // ILVR_W - 134243408U, // INS - 44582043U, // INSERT_B + 2181060764U, // GotPrologue16 + 0U, // INSERT_B_VIDX64_PSEUDO 0U, // INSERT_B_VIDX_PSEUDO - 44584275U, // INSERT_D + 0U, // INSERT_D_VIDX64_PSEUDO 0U, // INSERT_D_VIDX_PSEUDO 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX64_PSEUDO 0U, // INSERT_FD_VIDX_PSEUDO 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX64_PSEUDO 0U, // INSERT_FW_VIDX_PSEUDO - 44585551U, // INSERT_H + 0U, // INSERT_H_VIDX64_PSEUDO 0U, // INSERT_H_VIDX_PSEUDO - 44589573U, // INSERT_W + 0U, // INSERT_W_VIDX64_PSEUDO 0U, // INSERT_W_VIDX_PSEUDO - 16801009U, // INSV - 52970157U, // INSVE_B - 52971833U, // INSVE_D - 52973565U, // INSVE_H - 52977103U, // INSVE_W - 134243408U, // INS_MM - 546365U, // J - 546398U, // JAL - 22768U, // JALR - 547056U, // JALR16_MM - 22768U, // JALR64 0U, // JALR64Pseudo + 0U, // JALRCPseudo + 0U, // JALRHB64Pseudo + 0U, // JALRHBPseudo 0U, // JALRPseudo - 541104U, // JALRS16_MM - 23442U, // JALRS_MM - 17822U, // JALR_HB - 22768U, // JALR_MM - 547706U, // JALS_MM - 549771U, // JALX - 549771U, // JALX_MM - 546398U, // JAL_MM - 18212U, // JIALC - 18201U, // JIC - 547052U, // JR - 541091U, // JR16_MM - 547052U, // JR64 - 546873U, // JRADDIUSP - 542610U, // JRC16_MM - 542103U, // JR_HB - 542103U, // JR_HB_R6 - 547052U, // JR_MM - 546365U, // J_MM - 2905694U, // Jal16 - 3167838U, // JalB16 - 546398U, // JalOneReg - 22110U, // JalTwoReg - 9430U, // JrRa16 - 9421U, // JrcRa16 - 549872U, // JrcRx16 - 540673U, // JumpLinkReg16 - 58738087U, // LB - 58738087U, // LB64 - 58737088U, // LBU16_MM - 1358979985U, // LBUX - 58738087U, // LB_MM - 58743769U, // LBu - 58743769U, // LBu64 - 58743769U, // LBu_MM - 58740538U, // LD - 58736688U, // LDC1 - 58736688U, // LDC164 - 58736688U, // LDC1_MM - 58736888U, // LDC2 - 58736888U, // LDC2_R6 - 58736947U, // LDC3 - 17103U, // LDI_B - 18857U, // LDI_D - 20511U, // LDI_H - 24146U, // LDI_W - 58742458U, // LDL - 18273U, // LDPC - 58742954U, // LDR - 1358970992U, // LDXC1 - 1358970992U, // LDXC164 - 58737301U, // LD_B - 58738820U, // LD_D - 58740709U, // LD_H - 58744179U, // LD_W - 25189403U, // LEA_ADDiu - 25189402U, // LEA_ADDiu64 - 25189403U, // LEA_ADDiu_MM - 58741643U, // LH - 58741643U, // LH64 - 58737111U, // LHU16_MM - 1358979974U, // LHX - 58741643U, // LH_MM - 58743822U, // LHu - 58743822U, // LHu64 - 58743822U, // LHu_MM - 16751U, // LI16_MM - 58742563U, // LL - 58740537U, // LLD - 58740537U, // LLD_R6 - 58742563U, // LL_MM - 58742563U, // LL_R6 - 58736647U, // LOAD_ACC128 - 58736647U, // LOAD_ACC64 - 58736647U, // LOAD_ACC64DSP - 58742794U, // LOAD_CCOND_DSP + 0U, // JAL_MMR6 + 547080U, // JalOneReg + 22792U, // JalTwoReg + 50358523U, // LDMacro + 0U, // LDR_D + 0U, // LDR_W + 0U, // LD_F16 + 50348037U, // LOAD_ACC128 + 50348037U, // LOAD_ACC64 + 50348037U, // LOAD_ACC64DSP + 50354934U, // LOAD_CCOND_DSP 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_ADDiu2Op 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_DADDiu2Op 0U, // LONG_BRANCH_LUi - 134234691U, // LSA - 134234691U, // LSA_R6 - 1358971006U, // LUXC1 - 1358971006U, // LUXC164 - 1358971006U, // LUXC1_MM - 33576504U, // LUi - 33576504U, // LUi64 - 33576504U, // LUi_MM - 58745726U, // LW - 58737118U, // LW16_MM - 58745726U, // LW64 - 58736740U, // LWC1 - 58736740U, // LWC1_MM - 58736914U, // LWC2 - 58736914U, // LWC2_R6 - 58736959U, // LWC3 - 58745726U, // LWGP_MM - 58742637U, // LWL - 58742637U, // LWL64 - 58742637U, // LWL_MM - 3522956U, // LWM16_MM - 3522785U, // LWM32_MM - 3528595U, // LWM_MM - 18310U, // LWPC - 137290U, // LWP_MM - 58743054U, // LWR - 58743054U, // LWR64 - 58743054U, // LWR_MM - 58745726U, // LWSP_MM - 18303U, // LWUPC - 58743912U, // LWU_MM - 1358979991U, // LWX - 1358971020U, // LWXC1 - 1358971020U, // LWXC1_MM - 1358977945U, // LWXS_MM - 58745726U, // LW_MM - 58743912U, // LWu - 58738087U, // LbRxRyOffMemX16 - 58743769U, // LbuRxRyOffMemX16 - 58741643U, // LhRxRyOffMemX16 - 58743822U, // LhuRxRyOffMemX16 - 939546111U, // LiRxImm16 - 22005U, // LiRxImmAlignX16 - 22015U, // LiRxImmX16 - 33571334U, // LoadAddr32Imm - 58737158U, // LoadAddr32Reg - 33576447U, // LoadImm32Reg - 22019U, // LoadImm64Reg - 3695486U, // LwConstant32 - 268460926U, // LwRxPcTcp16 - 25470U, // LwRxPcTcpX16 - 58745726U, // LwRxRyOffMemX16 - 1493197694U, // LwRxSpImmX16 - 20269U, // MADD - 151013751U, // MADDF_D - 151017921U, // MADDF_S - 151015667U, // MADDR_Q_H - 151019386U, // MADDR_Q_W - 23546U, // MADDU - 134241274U, // MADDU_DSP - 23546U, // MADDU_MM - 151012706U, // MADDV_B - 151015051U, // MADDV_D - 151016266U, // MADDV_H - 151020341U, // MADDV_W - 134236274U, // MADD_D32 - 134236274U, // MADD_D32_MM - 134236274U, // MADD_D64 - 134237997U, // MADD_DSP - 20269U, // MADD_MM - 151015637U, // MADD_Q_H - 151019356U, // MADD_Q_W - 134240571U, // MADD_S - 134240571U, // MADD_S_MM - 134239974U, // MAQ_SA_W_PHL - 134240436U, // MAQ_SA_W_PHR - 134240002U, // MAQ_S_W_PHL - 134240464U, // MAQ_S_W_PHR - 134236215U, // MAXA_D - 134240544U, // MAXA_S - 134235159U, // MAXI_S_B - 134237220U, // MAXI_S_D - 134238636U, // MAXI_S_H - 134242509U, // MAXI_S_W - 2281719022U, // MAXI_U_B - 2281721335U, // MAXI_U_D - 2281722572U, // MAXI_U_H - 2281726625U, // MAXI_U_W - 134234740U, // MAX_A_B - 134236191U, // MAX_A_D - 134238148U, // MAX_A_H - 134241575U, // MAX_A_W - 134237938U, // MAX_D - 134241111U, // MAX_S - 134235247U, // MAX_S_B - 134237340U, // MAX_S_D - 134238755U, // MAX_S_H - 134242690U, // MAX_S_W - 134235462U, // MAX_U_B - 134237807U, // MAX_U_D - 134239022U, // MAX_U_H - 134243097U, // MAX_U_W - 134234122U, // MFC0 - 16451U, // MFC1 - 16451U, // MFC1_MM - 134234373U, // MFC2 - 16457U, // MFHC1_D32 - 16457U, // MFHC1_D64 - 16457U, // MFHC1_MM - 546281U, // MFHI - 546281U, // MFHI16_MM - 546281U, // MFHI64 - 21993U, // MFHI_DSP - 546281U, // MFHI_MM - 546745U, // MFLO - 546745U, // MFLO16_MM - 546745U, // MFLO64 - 22457U, // MFLO_DSP - 546745U, // MFLO_MM - 134236200U, // MINA_D - 134240536U, // MINA_S - 134235139U, // MINI_S_B - 134237200U, // MINI_S_D - 134238616U, // MINI_S_H - 134242489U, // MINI_S_W - 2281719002U, // MINI_U_B - 2281721315U, // MINI_U_D - 2281722552U, // MINI_U_H - 2281726605U, // MINI_U_W - 134234721U, // MIN_A_B - 134236171U, // MIN_A_D - 134238129U, // MIN_A_H - 134241555U, // MIN_A_W - 134236843U, // MIN_D - 134240812U, // MIN_S - 134235169U, // MIN_S_B - 134237230U, // MIN_S_D - 134238646U, // MIN_S_H - 134242529U, // MIN_S_W - 134235384U, // MIN_U_B - 134237697U, // MIN_U_D - 134238934U, // MIN_U_H - 134242987U, // MIN_U_W + 0U, // LONG_BRANCH_LUi2Op + 0U, // LONG_BRANCH_LUi2Op_64 + 72310U, // LWM_MM + 17196U, // LoadAddrImm32 + 17217U, // LoadAddrImm64 + 50348844U, // LoadAddrReg32 + 50348865U, // LoadAddrReg64 + 22684U, // LoadImm32 + 22688U, // LoadImm64 + 19348U, // LoadImmDoubleFGR + 19348U, // LoadImmDoubleFGR_32 + 19348U, // LoadImmDoubleGPR + 23819U, // LoadImmSingleFGR + 23819U, // LoadImmSingleGPR + 0U, // LoadJumpTableOffset + 1599429U, // LwConstant32 + 26979U, // MFTACX + 26979U, // MFTACX_NM + 536897723U, // MFTC0 + 536897723U, // MFTC0_NM + 26848U, // MFTC1 + 551212U, // MFTDSP + 551212U, // MFTDSP_NM + 26957U, // MFTGPR + 26957U, // MFTGPR_NM + 26825U, // MFTHC1 + 26896U, // MFTHI + 26896U, // MFTHI_NM + 26910U, // MFTLO + 26910U, // MFTLO_NM 0U, // MIPSeh_return32 0U, // MIPSeh_return64 - 134238037U, // MOD - 134235899U, // MODSUB - 134241282U, // MODU - 134235102U, // MOD_S_B - 134237163U, // MOD_S_D - 134238579U, // MOD_S_H - 134242452U, // MOD_S_W - 134235317U, // MOD_U_B - 134237630U, // MOD_U_D - 134238867U, // MOD_U_H - 134242920U, // MOD_U_W - 20345U, // MOVE16_MM - 67491813U, // MOVEP_MM - 23668U, // MOVE_V - 134236560U, // MOVF_D32 - 134236560U, // MOVF_D32_MM - 134236560U, // MOVF_D64 - 134238109U, // MOVF_I - 134238109U, // MOVF_I64 - 134238109U, // MOVF_I_MM - 134240722U, // MOVF_S - 134240722U, // MOVF_S_MM - 134236895U, // MOVN_I64_D64 - 134240173U, // MOVN_I64_I - 134240173U, // MOVN_I64_I64 - 134240848U, // MOVN_I64_S - 134236895U, // MOVN_I_D32 - 134236895U, // MOVN_I_D32_MM - 134236895U, // MOVN_I_D64 - 134240173U, // MOVN_I_I - 134240173U, // MOVN_I_I64 - 134240173U, // MOVN_I_MM - 134240848U, // MOVN_I_S - 134240848U, // MOVN_I_S_MM - 134237558U, // MOVT_D32 - 134237558U, // MOVT_D32_MM - 134237558U, // MOVT_D64 - 134241235U, // MOVT_I - 134241235U, // MOVT_I64 - 134241235U, // MOVT_I_MM - 134241037U, // MOVT_S - 134241037U, // MOVT_S_MM - 134237978U, // MOVZ_I64_D64 - 134243300U, // MOVZ_I64_I - 134243300U, // MOVZ_I64_I64 - 134241138U, // MOVZ_I64_S - 134237978U, // MOVZ_I_D32 - 134237978U, // MOVZ_I_D32_MM - 134237978U, // MOVZ_I_D64 - 134243300U, // MOVZ_I_I - 134243300U, // MOVZ_I_I64 - 134243300U, // MOVZ_I_MM - 134241138U, // MOVZ_I_S - 134241138U, // MOVZ_I_S_MM - 18179U, // MSUB - 151013742U, // MSUBF_D - 151017912U, // MSUBF_S - 151015656U, // MSUBR_Q_H - 151019375U, // MSUBR_Q_W - 23525U, // MSUBU - 134241253U, // MSUBU_DSP - 23525U, // MSUBU_MM - 151012697U, // MSUBV_B - 151015042U, // MSUBV_D - 151016257U, // MSUBV_H - 151020332U, // MSUBV_W - 134236232U, // MSUB_D32 - 134236232U, // MSUB_D32_MM - 134236232U, // MSUB_D64 - 134235907U, // MSUB_DSP - 18179U, // MSUB_MM - 151015627U, // MSUB_Q_H - 151019346U, // MSUB_Q_W - 134240553U, // MSUB_S - 134240553U, // MSUB_S_MM - 134234129U, // MTC0 - 1867870U, // MTC1 - 1867870U, // MTC1_MM - 134234380U, // MTC2 - 1884240U, // MTHC1_D32 - 1884240U, // MTHC1_D64 - 1884240U, // MTHC1_MM - 546287U, // MTHI - 546287U, // MTHI64 - 1873391U, // MTHI_DSP - 546287U, // MTHI_MM - 1873900U, // MTHLIP - 546758U, // MTLO - 546758U, // MTLO64 - 1873862U, // MTLO_DSP - 546758U, // MTLO_MM - 540701U, // MTM0 - 540826U, // MTM1 - 540958U, // MTM2 - 540707U, // MTP0 - 540832U, // MTP1 - 540964U, // MTP2 - 134239672U, // MUH - 134241300U, // MUHU - 134240104U, // MUL - 134240015U, // MULEQ_S_W_PHL - 134240477U, // MULEQ_S_W_PHR - 134239883U, // MULEU_S_PH_QBL - 134240379U, // MULEU_S_PH_QBR - 134239433U, // MULQ_RS_PH - 134242709U, // MULQ_RS_W - 134239377U, // MULQ_S_PH - 134242568U, // MULQ_S_W - 134238462U, // MULR_Q_H - 134242181U, // MULR_Q_W - 134239579U, // MULSAQ_S_W_PH - 134239554U, // MULSA_W_PH - 23496U, // MULT - 134241370U, // MULTU_DSP - 134241224U, // MULT_DSP - 23496U, // MULT_MM - 23642U, // MULTu - 23642U, // MULTu_MM - 134241337U, // MULU - 134235517U, // MULV_B - 134237870U, // MULV_D - 134239077U, // MULV_H - 134243160U, // MULV_W - 134240104U, // MUL_MM - 134239250U, // MUL_PH - 134238431U, // MUL_Q_H - 134242150U, // MUL_Q_W - 134240104U, // MUL_R6 - 134239345U, // MUL_S_PH - 546281U, // Mfhi16 - 546745U, // Mflo16 - 20345U, // Move32R16 - 20345U, // MoveR3216 - 23496U, // MultRxRy16 - 75799496U, // MultRxRyRz16 - 23642U, // MultuRxRy16 - 75799642U, // MultuRxRyRz16 - 17028U, // NLOC_B - 18521U, // NLOC_D - 20436U, // NLOC_H - 23880U, // NLOC_W - 17036U, // NLZC_B - 18529U, // NLZC_D - 20444U, // NLZC_H - 23888U, // NLZC_W - 134236282U, // NMADD_D32 - 134236282U, // NMADD_D32_MM - 134236282U, // NMADD_D64 - 134240570U, // NMADD_S - 134240570U, // NMADD_S_MM - 134236240U, // NMSUB_D32 - 134236240U, // NMSUB_D32_MM - 134236240U, // NMSUB_D64 - 134240552U, // NMSUB_S - 134240552U, // NMSUB_S_MM + 0U, // MSA_FP_EXTEND_D_PSEUDO + 0U, // MSA_FP_EXTEND_W_PSEUDO + 0U, // MSA_FP_ROUND_D_PSEUDO + 0U, // MSA_FP_ROUND_W_PSEUDO + 17885547U, // MTTACX + 17885547U, // MTTACX_NM + 2752571586U, // MTTC0 + 2752571586U, // MTTC0_NM + 17885422U, // MTTC1 + 551220U, // MTTDSP + 551220U, // MTTDSP_NM + 17885525U, // MTTGPR + 17885525U, // MTTGPR_NM + 17885393U, // MTTHC1 + 17885463U, // MTTHI + 17885463U, // MTTHI_NM + 17885477U, // MTTLO + 17885477U, // MTTLO_NM + 536893991U, // MULImmMacro + 536894130U, // MULOMacro + 536895563U, // MULOUMacro + 0U, // MUSTTAILCALLREG_NM + 0U, // MUSTTAILCALL_NM + 24462U, // MultRxRy16 + 86040462U, // MultRxRyRz16 + 24706U, // MultuRxRy16 + 86040706U, // MultuRxRyRz16 0U, // NOP - 134240502U, // NOR - 134240502U, // NOR64 - 2281718573U, // NORI_B - 134240502U, // NOR_MM - 134241412U, // NOR_V + 536894462U, // NORImm + 536894462U, // NORImm64 0U, // NOR_V_D_PSEUDO 0U, // NOR_V_H_PSEUDO 0U, // NOR_V_W_PSEUDO - 16825U, // NOT16_MM - 20387U, // NegRxRy16 - 23502U, // NotRxRy16 - 134240503U, // OR - 836010U, // OR16_MM - 134240503U, // OR64 - 2281718574U, // ORI_B - 134240503U, // OR_MM - 134241413U, // OR_V 0U, // OR_V_D_PSEUDO 0U, // OR_V_H_PSEUDO 0U, // OR_V_W_PSEUDO - 134239771U, // ORi - 134239771U, // ORi64 - 134239771U, // ORi_MM - 16799991U, // OrRxRxRy16 - 134239239U, // PACKRL_PH - 9442U, // PAUSE - 9442U, // PAUSE_MM - 134235499U, // PCKEV_B - 134237844U, // PCKEV_D - 134239059U, // PCKEV_H - 134243134U, // PCKEV_W - 134234779U, // PCKOD_B - 134236298U, // PCKOD_D - 134238187U, // PCKOD_H - 134241657U, // PCKOD_W - 17555U, // PCNT_B - 19778U, // PCNT_D - 21063U, // PCNT_H - 25076U, // PCNT_W - 134239203U, // PICK_PH - 134235631U, // PICK_QB - 22522U, // POP - 22186U, // PRECEQU_PH_QBL - 16906U, // PRECEQU_PH_QBLA - 22682U, // PRECEQU_PH_QBR - 16939U, // PRECEQU_PH_QBRA - 22260U, // PRECEQ_W_PHL - 22722U, // PRECEQ_W_PHR - 22171U, // PRECEU_PH_QBL - 16890U, // PRECEU_PH_QBLA - 22667U, // PRECEU_PH_QBR - 16923U, // PRECEU_PH_QBRA - 134239155U, // PRECRQU_S_QB_PH - 134241800U, // PRECRQ_PH_W - 134239128U, // PRECRQ_QB_PH - 134241831U, // PRECRQ_RS_PH_W - 134239142U, // PRECR_QB_PH - 134241784U, // PRECR_SRA_PH_W - 134241813U, // PRECR_SRA_R_PH_W - 85911U, // PREF - 85911U, // PREF_MM - 85911U, // PREF_R6 - 134238019U, // PREPEND + 536895505U, // PseudoADDIU_NM + 536893544U, // PseudoANDI_NM 0U, // PseudoCMPU_EQ_QB 0U, // PseudoCMPU_LE_QB 0U, // PseudoCMPU_LT_QB 0U, // PseudoCMP_EQ_PH 0U, // PseudoCMP_LE_PH 0U, // PseudoCMP_LT_PH - 16391U, // PseudoCVT_D32_W - 16391U, // PseudoCVT_D64_L - 16391U, // PseudoCVT_D64_W - 16391U, // PseudoCVT_S_L - 16391U, // PseudoCVT_S_W + 16389U, // PseudoCVT_D32_W + 16389U, // PseudoCVT_D64_L + 16389U, // PseudoCVT_D64_W + 16389U, // PseudoCVT_S_L + 16389U, // PseudoCVT_S_W 0U, // PseudoDMULT 0U, // PseudoDMULTu 0U, // PseudoDSDIV 0U, // PseudoDUDIV + 0U, // PseudoD_SELECT_I + 0U, // PseudoD_SELECT_I64 0U, // PseudoIndirectBranch 0U, // PseudoIndirectBranch64 + 0U, // PseudoIndirectBranch64R6 + 0U, // PseudoIndirectBranchNM + 0U, // PseudoIndirectBranchR6 + 0U, // PseudoIndirectBranch_MM + 0U, // PseudoIndirectBranch_MMR6 + 0U, // PseudoIndirectHazardBranch + 0U, // PseudoIndirectHazardBranch64 + 0U, // PseudoIndrectHazardBranch64R6 + 0U, // PseudoIndrectHazardBranchR6 + 100680492U, // PseudoLA_NM + 100685980U, // PseudoLI_NM 0U, // PseudoMADD 0U, // PseudoMADDU + 0U, // PseudoMADDU_MM + 0U, // PseudoMADD_MM 0U, // PseudoMFHI 0U, // PseudoMFHI64 + 0U, // PseudoMFHI_MM 0U, // PseudoMFLO 0U, // PseudoMFLO64 + 0U, // PseudoMFLO_MM 0U, // PseudoMSUB 0U, // PseudoMSUBU + 0U, // PseudoMSUBU_MM + 0U, // PseudoMSUB_MM 0U, // PseudoMTLOHI 0U, // PseudoMTLOHI64 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMTLOHI_MM 0U, // PseudoMULT + 0U, // PseudoMULT_MM 0U, // PseudoMULTu + 0U, // PseudoMULTu_MM 0U, // PseudoPICK_PH 0U, // PseudoPICK_QB 0U, // PseudoReturn 0U, // PseudoReturn64 + 0U, // PseudoReturnNM 0U, // PseudoSDIV 0U, // PseudoSELECTFP_F_D32 0U, // PseudoSELECTFP_F_D64 @@ -1401,413 +1960,2502 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) 0U, // PseudoSELECT_I 0U, // PseudoSELECT_I64 0U, // PseudoSELECT_S + 536895420U, // PseudoSUBU_NM + 536891541U, // PseudoTRUNC_W_D + 536891541U, // PseudoTRUNC_W_D32 + 536895079U, // PseudoTRUNC_W_S 0U, // PseudoUDIV - 18155U, // RADDU_W_QB - 33577003U, // RDDSP - 22791U, // RDHWR - 22791U, // RDHWR64 - 22791U, // RDHWR_MM - 21766U, // REPLV_PH - 18135U, // REPLV_QB - 33575925U, // REPL_PH - 33572353U, // REPL_QB - 19787U, // RINT_D - 23293U, // RINT_S - 134240513U, // ROTR - 134241514U, // ROTRV - 134241514U, // ROTRV_MM - 134240513U, // ROTR_MM - 18992U, // ROUND_L_D64 - 23020U, // ROUND_L_S - 20168U, // ROUND_W_D32 - 20168U, // ROUND_W_D64 - 20168U, // ROUND_W_MM - 23342U, // ROUND_W_S - 23342U, // ROUND_W_S_MM - 0U, // Restore16 - 0U, // RestoreX16 + 536893930U, // ROL + 536893930U, // ROLImm + 536894468U, // ROR + 536894468U, // RORImm 0U, // RetRA 0U, // RetRA16 - 134235208U, // SAT_S_B - 134237279U, // SAT_S_D - 2281722353U, // SAT_S_H - 134242618U, // SAT_S_W - 134235435U, // SAT_U_B - 134237758U, // SAT_U_D - 2281722643U, // SAT_U_H - 134243048U, // SAT_U_W - 58738423U, // SB - 58736980U, // SB16_MM - 58738423U, // SB64 - 58738423U, // SB_MM - 3966874U, // SC - 3968802U, // SCD - 3968802U, // SCD_R6 - 3966874U, // SC_MM - 3966874U, // SC_R6 - 58740570U, // SD - 546774U, // SDBBP - 65946U, // SDBBP16_MM - 546774U, // SDBBP_MM - 546774U, // SDBBP_R6 - 58736694U, // SDC1 - 58736694U, // SDC164 - 58736694U, // SDC1_MM - 58736894U, // SDC2 - 58736894U, // SDC2_R6 - 58736953U, // SDC3 - 25611U, // SDIV - 25611U, // SDIV_MM - 58742463U, // SDL - 58742959U, // SDR - 1358970999U, // SDXC1 - 1358970999U, // SDXC164 - 17810U, // SEB - 17810U, // SEB64 - 17810U, // SEB_MM - 21382U, // SEH - 21382U, // SEH64 - 21382U, // SEH_MM - 134243273U, // SELEQZ - 134243273U, // SELEQZ64 - 134237968U, // SELEQZ_D - 134241128U, // SELEQZ_S - 134243246U, // SELNEZ - 134243246U, // SELNEZ64 - 134237951U, // SELNEZ_D - 134241118U, // SELNEZ_S - 151013977U, // SEL_D - 151018005U, // SEL_S - 134240345U, // SEQ - 134239758U, // SEQi - 58742195U, // SH - 58736993U, // SH16_MM - 58742195U, // SH64 - 2281718455U, // SHF_B - 2281721863U, // SHF_H - 2281725417U, // SHF_W - 22463U, // SHILO - 23761U, // SHILOV - 134239484U, // SHLLV_PH - 134235853U, // SHLLV_QB - 134239421U, // SHLLV_S_PH - 134242679U, // SHLLV_S_W - 134239212U, // SHLL_PH - 134235640U, // SHLL_QB - 134239334U, // SHLL_S_PH - 134242519U, // SHLL_S_W - 134239474U, // SHRAV_PH - 134235843U, // SHRAV_QB - 134239322U, // SHRAV_R_PH - 134235741U, // SHRAV_R_QB - 134242274U, // SHRAV_R_W - 134239119U, // SHRA_PH - 134235563U, // SHRA_QB - 134239287U, // SHRA_R_PH - 134235706U, // SHRA_R_QB - 134242232U, // SHRA_R_W - 134239504U, // SHRLV_PH - 134235873U, // SHRLV_QB - 134239230U, // SHRL_PH - 134235658U, // SHRL_QB - 58742195U, // SH_MM - 2969584334U, // SLDI_B - 2969586088U, // SLDI_D - 2969587742U, // SLDI_H - 2969591377U, // SLDI_W - 822100628U, // SLD_B - 822102147U, // SLD_D - 822104036U, // SLD_H - 822107506U, // SLD_W - 134240058U, // SLL - 134234494U, // SLL16_MM - 1610635066U, // SLL64_32 - 1610635066U, // SLL64_64 - 2281718512U, // SLLI_B - 2281720249U, // SLLI_D - 2281721903U, // SLLI_H - 2281725538U, // SLLI_W - 134241476U, // SLLV - 134241476U, // SLLV_MM - 134235013U, // SLL_B - 134236785U, // SLL_D - 134238371U, // SLL_H - 134240058U, // SLL_MM - 134242032U, // SLL_W - 134241213U, // SLT - 134241213U, // SLT64 - 134241213U, // SLT_MM - 134239782U, // SLTi - 134239782U, // SLTi64 - 134239782U, // SLTi_MM - 134241321U, // SLTiu - 134241321U, // SLTiu64 - 134241321U, // SLTiu_MM - 134241357U, // SLTu - 134241357U, // SLTu64 - 134241357U, // SLTu_MM - 134238063U, // SNE - 134239703U, // SNEi + 50351496U, // SDC1_M1 + 0U, // SDIV_MM_Pseudo + 50358535U, // SDMacro + 536895725U, // SDivIMacro + 536895725U, // SDivMacro + 536897864U, // SEQIMacro + 536897864U, // SEQMacro + 536891767U, // SGE + 536891767U, // SGEImm + 536891767U, // SGEImm64 + 536895467U, // SGEU + 536895467U, // SGEUImm + 536895467U, // SGEUImm64 + 536895347U, // SGTImm + 536895347U, // SGTImm64 + 536895593U, // SGTUImm + 536895593U, // SGTUImm64 + 536891812U, // SLE + 536891812U, // SLEImm + 536891812U, // SLEImm64 + 536895485U, // SLEU + 536895485U, // SLEUImm + 536895485U, // SLEUImm64 + 536895363U, // SLTImm64 + 536895605U, // SLTUImm64 + 536897803U, // SNEIMacro + 536897803U, // SNEMacro 0U, // SNZ_B_PSEUDO 0U, // SNZ_D_PSEUDO 0U, // SNZ_H_PSEUDO 0U, // SNZ_V_PSEUDO 0U, // SNZ_W_PSEUDO - 2952807239U, // SPLATI_B - 2952808960U, // SPLATI_D - 2952810614U, // SPLATI_H - 2952814249U, // SPLATI_W - 805323906U, // SPLAT_B - 805326016U, // SPLAT_D - 805327414U, // SPLAT_H - 805331393U, // SPLAT_W - 134234685U, // SRA - 2281718470U, // SRAI_B - 2281720224U, // SRAI_D - 2281721878U, // SRAI_H - 2281725513U, // SRAI_W - 134234898U, // SRARI_B - 134236635U, // SRARI_D - 2281721937U, // SRARI_H - 134241924U, // SRARI_W - 134235051U, // SRAR_B - 134237015U, // SRAR_D - 134238486U, // SRAR_H - 134242296U, // SRAR_W - 134241455U, // SRAV - 134241455U, // SRAV_MM - 134234749U, // SRA_B - 134236208U, // SRA_D - 134238157U, // SRA_H - 134234685U, // SRA_MM - 134241584U, // SRA_W - 134240070U, // SRL - 134234501U, // SRL16_MM - 2281718520U, // SRLI_B - 2281720257U, // SRLI_D - 2281721911U, // SRLI_H - 2281725546U, // SRLI_W - 134234916U, // SRLRI_B - 134236653U, // SRLRI_D - 2281721955U, // SRLRI_H - 134241942U, // SRLRI_W - 134235067U, // SRLR_B - 134237031U, // SRLR_D - 134238502U, // SRLR_H - 134242312U, // SRLR_W - 134241483U, // SRLV - 134241483U, // SRLV_MM - 134235020U, // SRL_B - 134236810U, // SRL_D - 134238378U, // SRL_H - 134240070U, // SRL_MM - 134242057U, // SRL_W - 9463U, // SSNOP - 9463U, // SSNOP_MM - 58736647U, // STORE_ACC128 - 58736647U, // STORE_ACC64 - 58736647U, // STORE_ACC64DSP - 58742810U, // STORE_CCOND_DSP - 58737829U, // ST_B - 58740080U, // ST_D - 58741337U, // ST_H - 58745378U, // ST_W - 134235902U, // SUB - 134239183U, // SUBQH_PH - 134239298U, // SUBQH_R_PH - 134242242U, // SUBQH_R_W - 134241847U, // SUBQH_W - 134239258U, // SUBQ_PH - 134239355U, // SUBQ_S_PH - 134242548U, // SUBQ_S_W - 134235423U, // SUBSUS_U_B - 134237746U, // SUBSUS_U_D - 134238983U, // SUBSUS_U_H - 134243036U, // SUBSUS_U_W - 134235226U, // SUBSUU_S_B - 134237319U, // SUBSUU_S_D - 134238723U, // SUBSUU_S_H - 134242658U, // SUBSUU_S_W - 134235188U, // SUBS_S_B - 134237259U, // SUBS_S_D - 134238685U, // SUBS_S_H - 134242598U, // SUBS_S_W - 134235403U, // SUBS_U_B - 134237726U, // SUBS_U_D - 134238963U, // SUBS_U_H - 134243016U, // SUBS_U_W - 134234567U, // SUBU16_MM - 134235611U, // SUBUH_QB - 134235717U, // SUBUH_R_QB - 134239456U, // SUBU_PH - 134235825U, // SUBU_QB - 134239399U, // SUBU_S_PH - 134235764U, // SUBU_S_QB - 2281718618U, // SUBVI_B - 2281720339U, // SUBVI_D - 2281721993U, // SUBVI_H - 2281725628U, // SUBVI_W - 134235482U, // SUBV_B - 134237827U, // SUBV_D - 134239042U, // SUBV_H - 134243117U, // SUBV_W - 134235902U, // SUB_MM - 134241247U, // SUBu - 134241247U, // SUBu_MM - 1358971013U, // SUXC1 - 1358971013U, // SUXC164 - 1358971013U, // SUXC1_MM - 58745730U, // SW - 58737124U, // SW16_MM - 58745730U, // SW64 - 58736746U, // SWC1 - 58736746U, // SWC1_MM - 58736920U, // SWC2 - 58736920U, // SWC2_R6 - 58736965U, // SWC3 - 58742642U, // SWL - 58742642U, // SWL64 - 58742642U, // SWL_MM - 3522963U, // SWM16_MM - 3522792U, // SWM32_MM - 3528600U, // SWM_MM - 137295U, // SWP_MM - 58743059U, // SWR - 58743059U, // SWR64 - 58743059U, // SWR_MM - 58745730U, // SWSP_MM - 1358971027U, // SWXC1 - 1358971027U, // SWXC1_MM - 58745730U, // SW_MM - 549939U, // SYNC - 153021U, // SYNCI - 549939U, // SYNC_MM - 546590U, // SYSCALL - 546590U, // SYSCALL_MM + 536894049U, // SRemIMacro + 536894049U, // SRemMacro + 50348037U, // STORE_ACC128 + 50348037U, // STORE_ACC64 + 50348037U, // STORE_ACC64DSP + 50354950U, // STORE_CCOND_DSP + 0U, // STR_D + 0U, // STR_W + 0U, // ST_F16 + 72317U, // SWM_MM 0U, // SZ_B_PSEUDO 0U, // SZ_D_PSEUDO 0U, // SZ_H_PSEUDO 0U, // SZ_V_PSEUDO 0U, // SZ_W_PSEUDO - 0U, // Save16 - 0U, // SaveX16 - 58738423U, // SbRxRyOffMemX16 - 549866U, // SebRx16 - 549878U, // SehRx16 - 4367299U, // SelBeqZ - 4367272U, // SelBneZ - 1828886516U, // SelTBteqZCmp - 1828886024U, // SelTBteqZCmpi - 1828887485U, // SelTBteqZSlt - 1828886054U, // SelTBteqZSlti - 1828887593U, // SelTBteqZSltiu - 1828887629U, // SelTBteqZSltu - 1963104244U, // SelTBtneZCmp - 1963103752U, // SelTBtneZCmpi - 1963105213U, // SelTBtneZSlt - 1963103782U, // SelTBtneZSlti - 1963105321U, // SelTBtneZSltiu - 1963105357U, // SelTBtneZSltu - 58742195U, // ShRxRyOffMemX16 - 134240058U, // SllX16 - 16800964U, // SllvRxRy16 - 92576701U, // SltCCRxRy16 - 23485U, // SltRxRy16 - 92575270U, // SltiCCRxImmX16 - 939546150U, // SltiRxImm16 - 22054U, // SltiRxImmX16 - 92576809U, // SltiuCCRxImmX16 - 939547689U, // SltiuRxImm16 - 23593U, // SltiuRxImmX16 - 92576845U, // SltuCCRxRy16 - 23629U, // SltuRxRy16 - 92576845U, // SltuRxRyRz16 - 134234685U, // SraX16 - 16800943U, // SravRxRy16 - 134240070U, // SrlX16 - 16800971U, // SrlvRxRy16 - 134241247U, // SubuRxRyRz16 - 58745730U, // SwRxRyOffMemX16 - 1493197698U, // SwRxSpImmX16 + 50348827U, // SaaAddr + 50352386U, // SaadAddr + 2713697U, // SelBeqZ + 2713670U, // SelBneZ + 3338754784U, // SelTBteqZCmp + 3338754213U, // SelTBteqZCmpi + 3338755971U, // SelTBteqZSlt + 3338754243U, // SelTBteqZSlti + 3338756127U, // SelTBteqZSltiu + 3338756213U, // SelTBteqZSltu + 3875625696U, // SelTBtneZCmp + 3875625125U, // SelTBtneZCmpi + 3875626883U, // SelTBtneZSlt + 3875625155U, // SelTBtneZSlti + 3875627039U, // SelTBtneZSltiu + 3875627125U, // SelTBtneZSltu + 136372099U, // SltCCRxRy16 + 136370371U, // SltiCCRxImmX16 + 136372255U, // SltiuCCRxImmX16 + 136372341U, // SltuCCRxRy16 + 136372341U, // SltuRxRyRz16 0U, // TAILCALL - 0U, // TAILCALL64_R - 0U, // TAILCALL_R - 134240350U, // TEQ - 33576468U, // TEQI - 33576468U, // TEQI_MM - 134240350U, // TEQ_MM - 134238046U, // TGE - 33576401U, // TGEI - 33578018U, // TGEIU - 33578018U, // TGEIU_MM - 33576401U, // TGEI_MM - 134241288U, // TGEU - 134241288U, // TGEU_MM - 134238046U, // TGE_MM - 9458U, // TLBP - 9458U, // TLBP_MM - 9469U, // TLBR - 9469U, // TLBR_MM - 9448U, // TLBWI - 9448U, // TLBWI_MM - 9474U, // TLBWR - 9474U, // TLBWR_MM - 134241218U, // TLT - 33576492U, // TLTI - 33578032U, // TLTIU_MM - 33576492U, // TLTI_MM - 134241363U, // TLTU - 134241363U, // TLTU_MM - 134241218U, // TLT_MM - 134238068U, // TNE - 33576413U, // TNEI - 33576413U, // TNEI_MM - 134238068U, // TNE_MM + 0U, // TAILCALL64R6REG + 0U, // TAILCALLHB64R6REG + 0U, // TAILCALLHBR6REG + 0U, // TAILCALLR6REG + 0U, // TAILCALLREG + 0U, // TAILCALLREG64 + 0U, // TAILCALLREGHB + 0U, // TAILCALLREGHB64 + 0U, // TAILCALLREG_MM + 0U, // TAILCALLREG_MMR6 + 0U, // TAILCALLREG_NM + 0U, // TAILCALL_MM + 0U, // TAILCALL_MMR6 + 0U, // TAILCALL_NM 0U, // TRAP - 18981U, // TRUNC_L_D64 - 23009U, // TRUNC_L_S - 20157U, // TRUNC_W_D32 - 20157U, // TRUNC_W_D64 - 20157U, // TRUNC_W_MM - 23331U, // TRUNC_W_S - 23331U, // TRUNC_W_S_MM - 33578032U, // TTLTIU - 25597U, // UDIV - 25597U, // UDIV_MM - 134241335U, // V3MULU - 134234135U, // VMM0 - 134241350U, // VMULU - 151012022U, // VSHF_B - 151013760U, // VSHF_D - 151015430U, // VSHF_H - 151018984U, // VSHF_W - 9486U, // WAIT - 547767U, // WAIT_MM - 33577010U, // WRDSP - 21376U, // WSBH - 21376U, // WSBH_MM - 134240507U, // XOR - 836009U, // XOR16_MM - 134240507U, // XOR64 - 2281718581U, // XORI_B - 134240507U, // XOR_MM - 134241419U, // XOR_V + 0U, // TRAP_MM + 0U, // UDIV_MM_Pseudo + 536895633U, // UDivIMacro + 536895633U, // UDivMacro + 536895556U, // URemIMacro + 536895556U, // URemMacro + 50353696U, // Ulh + 50356227U, // Ulhu + 50358217U, // Ulw + 50354255U, // Ush + 50358239U, // Usw 0U, // XOR_V_D_PSEUDO 0U, // XOR_V_H_PSEUDO 0U, // XOR_V_W_PSEUDO - 134239770U, // XORi - 134239770U, // XORi64 - 134239770U, // XORi_MM - 16799995U, // XorRxRxRy16 - 0U + 22322U, // ABSQ_S_PH + 22322U, // ABSQ_S_PH_MM + 18359U, // ABSQ_S_QB + 18359U, // ABSQ_S_QB_MMR2 + 25926U, // ABSQ_S_W + 25926U, // ABSQ_S_W_MM + 536891671U, // ADD + 536888015U, // ADDIU48_NM + 536888026U, // ADDIUGP48_NM + 536888039U, // ADDIUGPB_NM + 536888078U, // ADDIUGPW_NM + 536888052U, // ADDIUNEG_NM + 18678U, // ADDIUPC + 18678U, // ADDIUPC_MM + 18678U, // ADDIUPC_MMR6 + 23275U, // ADDIUR1SP_MM + 536888064U, // ADDIUR1SP_NM + 536887680U, // ADDIUR2_MM + 536887964U, // ADDIUR2_NM + 536887975U, // ADDIURS5_NM + 18923937U, // ADDIUS5_MM + 547624U, // ADDIUSP_MM + 536895505U, // ADDIU_MMR6 + 536887953U, // ADDIU_NM + 536893039U, // ADDQH_PH + 536893039U, // ADDQH_PH_MMR2 + 536893156U, // ADDQH_R_PH + 536893156U, // ADDQH_R_PH_MMR2 + 536896513U, // ADDQH_R_W + 536896513U, // ADDQH_R_W_MMR2 + 536896116U, // ADDQH_W + 536896116U, // ADDQH_W_MMR2 + 536893113U, // ADDQ_PH + 536893113U, // ADDQ_PH_MM + 536893212U, // ADDQ_S_PH + 536893212U, // ADDQ_S_PH_MM + 536896818U, // ADDQ_S_W + 536896818U, // ADDQ_S_W_MM + 536895247U, // ADDR_PS64 + 536889644U, // ADDSC + 536889644U, // ADDSC_MM + 536888213U, // ADDS_A_B + 536889837U, // ADDS_A_D + 536891952U, // ADDS_A_H + 536895824U, // ADDS_A_W + 536888689U, // ADDS_S_B + 536890935U, // ADDS_S_D + 536892517U, // ADDS_S_H + 536896868U, // ADDS_S_W + 536888904U, // ADDS_U_B + 536891402U, // ADDS_U_D + 536892795U, // ADDS_U_H + 536897286U, // ADDS_U_W + 536887900U, // ADDU16_MM + 536887900U, // ADDU16_MMR6 + 536889139U, // ADDUH_QB + 536889139U, // ADDUH_QB_MMR2 + 536889247U, // ADDUH_R_QB + 536889247U, // ADDUH_R_QB_MMR2 + 536895434U, // ADDU_MMR6 + 536893311U, // ADDU_PH + 536893311U, // ADDU_PH_MMR2 + 536889352U, // ADDU_QB + 536889352U, // ADDU_QB_MM + 536893256U, // ADDU_S_PH + 536893256U, // ADDU_S_PH_MMR2 + 536889293U, // ADDU_S_QB + 536889293U, // ADDU_S_QB_MM + 536888470U, // ADDVI_B + 536890357U, // ADDVI_D + 536892176U, // ADDVI_H + 536896249U, // ADDVI_W + 536888982U, // ADDV_B + 536891492U, // ADDV_D + 536892873U, // ADDV_H + 536897386U, // ADDV_W + 536889713U, // ADDWC + 536889713U, // ADDWC_MM + 536888195U, // ADD_A_B + 536889818U, // ADD_A_D + 536891934U, // ADD_A_H + 536895805U, // ADD_A_W + 536891671U, // ADD_MM + 536891671U, // ADD_MMR6 + 536891671U, // ADD_NM + 536893538U, // ADDi + 536893538U, // ADDi_MM + 536895505U, // ADDiu + 536895505U, // ADDiu_MM + 536895434U, // ADDu + 536895434U, // ADDu16_NM + 536895434U, // ADDu4x4_NM + 536895434U, // ADDu_MM + 536895434U, // ADDu_NM + 536894083U, // ALIGN + 536894083U, // ALIGN_MMR6 + 18670U, // ALUIPC + 18670U, // ALUIPC_MMR6 + 151013614U, // ALUIPC_NM + 536891700U, // AND + 20021711U, // AND16_MM + 20021711U, // AND16_MMR6 + 536891700U, // AND16_NM + 536891700U, // AND64 + 536887780U, // ANDI16_MM + 536887780U, // ANDI16_MMR6 + 536887997U, // ANDI16_NM + 536888329U, // ANDI_B + 536893544U, // ANDI_MMR6 + 536887943U, // ANDI_NM + 536891700U, // AND_MM + 536891700U, // AND_MMR6 + 536891700U, // AND_NM + 536895644U, // AND_V + 536893544U, // ANDi + 536893544U, // ANDi64 + 536893544U, // ANDi_MM + 536891714U, // APPEND + 536891714U, // APPEND_MMR2 + 536888583U, // ASUB_S_B + 536890765U, // ASUB_S_D + 536892349U, // ASUB_S_H + 536896648U, // ASUB_S_W + 536888798U, // ASUB_U_B + 536891232U, // ASUB_U_D + 536892637U, // ASUB_U_H + 536897116U, // ASUB_U_W + 536893648U, // AUI + 18663U, // AUIPC + 18663U, // AUIPC_MMR6 + 536893648U, // AUI_MMR6 + 536888669U, // AVER_S_B + 536890915U, // AVER_S_D + 536892487U, // AVER_S_H + 536896848U, // AVER_S_W + 536888884U, // AVER_U_B + 536891382U, // AVER_U_D + 536892775U, // AVER_U_H + 536897266U, // AVER_U_W + 536888611U, // AVE_S_B + 536890847U, // AVE_S_D + 536892419U, // AVE_S_H + 536896730U, // AVE_S_W + 536888826U, // AVE_U_B + 536891314U, // AVE_U_D + 536892707U, // AVE_U_H + 536897198U, // AVE_U_W + 24593U, // AddiuRxImmX16 + 3694609U, // AddiuRxPcImmX16 + 33579025U, // AddiuRxRxImm16 + 33579025U, // AddiuRxRxImmX16 + 167796753U, // AddiuRxRyOffMemX16 + 4221103U, // AddiuSpImm16 + 551087U, // AddiuSpImmX16 + 536895434U, // AdduRxRyRz16 + 33575220U, // AndRxRxRy16 + 557483U, // B16_MM + 536895433U, // BADDu + 563459U, // BAL + 559256U, // BALC + 115379U, // BALC16_NM + 559256U, // BALC_MMR6 + 116888U, // BALC_NM + 536894082U, // BALIGN + 536894082U, // BALIGN_MMR2 + 18745U, // BALRSC_NM + 536889778U, // BBEQZC_NM + 184565845U, // BBIT0 + 184565977U, // BBIT032 + 184565970U, // BBIT1 + 184565986U, // BBIT132 + 536889752U, // BBNEZC_NM + 559202U, // BC + 557488U, // BC16_MMR6 + 559202U, // BC16_NM + 201353603U, // BC1EQZ + 201345440U, // BC1EQZC_MMR6 + 201347591U, // BC1F + 201349504U, // BC1FL + 201347591U, // BC1F_MM + 201353587U, // BC1NEZ + 201345414U, // BC1NEZC_MMR6 + 201351016U, // BC1T + 201349637U, // BC1TL + 201351016U, // BC1T_MM + 201353611U, // BC2EQZ + 201345449U, // BC2EQZC_MMR6 + 201353595U, // BC2NEZ + 201345423U, // BC2NEZC_MMR6 + 536888398U, // BCLRI_B + 536890301U, // BCLRI_D + 536892120U, // BCLRI_H + 536896193U, // BCLRI_W + 536888550U, // BCLR_B + 536890689U, // BCLR_D + 536892316U, // BCLR_H + 536896564U, // BCLR_W + 559202U, // BC_MMR6 + 559202U, // BC_NM + 536894300U, // BEQ + 536894300U, // BEQ64 + 536889618U, // BEQC + 536889618U, // BEQC16_NM + 536889618U, // BEQC64 + 536889618U, // BEQC_MMR6 + 536889618U, // BEQC_NM + 536889618U, // BEQCzero_NM + 754993285U, // BEQIC_NM + 536893945U, // BEQL + 201343615U, // BEQZ16_MM + 201345216U, // BEQZALC + 201345216U, // BEQZALC_MMR6 + 201345459U, // BEQZC + 201343430U, // BEQZC16_MMR6 + 201345459U, // BEQZC16_NM + 201345459U, // BEQZC64 + 201345459U, // BEQZC_MM + 201345459U, // BEQZC_MMR6 + 201345459U, // BEQZC_NM + 536894300U, // BEQ_MM + 536889446U, // BGEC + 536889446U, // BGEC64 + 536889446U, // BGEC_MMR6 + 536889446U, // BGEC_NM + 754993266U, // BGEIC_NM + 754993486U, // BGEIUC_NM + 536889671U, // BGEUC + 536889671U, // BGEUC64 + 536889671U, // BGEUC_MMR6 + 536889671U, // BGEUC_NM + 201353274U, // BGEZ + 201353274U, // BGEZ64 + 201349389U, // BGEZAL + 201345189U, // BGEZALC + 201345189U, // BGEZALC_MMR6 + 201349585U, // BGEZALL + 201350857U, // BGEZALS_MM + 201349389U, // BGEZAL_MM + 201345400U, // BGEZC + 201345400U, // BGEZC64 + 201345400U, // BGEZC_MMR6 + 201349700U, // BGEZL + 201353274U, // BGEZ_MM + 201353334U, // BGTZ + 201353334U, // BGTZ64 + 201345225U, // BGTZALC + 201345225U, // BGTZALC_MMR6 + 201345466U, // BGTZC + 201345466U, // BGTZC64 + 201345466U, // BGTZC_MMR6 + 201349714U, // BGTZL + 201353334U, // BGTZ_MM + 570442803U, // BINSLI_B + 570444706U, // BINSLI_D + 570446525U, // BINSLI_H + 570450598U, // BINSLI_W + 570442950U, // BINSL_B + 570444906U, // BINSL_D + 570446639U, // BINSL_H + 570450756U, // BINSL_W + 570442864U, // BINSRI_B + 570444751U, // BINSRI_D + 570446570U, // BINSRI_H + 570450643U, // BINSRI_W + 570442998U, // BINSR_B + 570445171U, // BINSR_D + 570446764U, // BINSR_H + 570451046U, // BINSR_W + 24804U, // BITREV + 26612U, // BITREVW_NM + 24804U, // BITREV_MM + 23225U, // BITSWAP + 23225U, // BITSWAP_MMR6 + 201353280U, // BLEZ + 201353280U, // BLEZ64 + 201345198U, // BLEZALC + 201345198U, // BLEZALC_MMR6 + 201345407U, // BLEZC + 201345407U, // BLEZC64 + 201345407U, // BLEZC_MMR6 + 201349707U, // BLEZL + 201353280U, // BLEZ_MM + 536889665U, // BLTC + 536889665U, // BLTC64 + 536889665U, // BLTC_MMR6 + 536889665U, // BLTC_NM + 754993292U, // BLTIC_NM + 754993494U, // BLTIUC_NM + 536889694U, // BLTUC + 536889694U, // BLTUC64 + 536889694U, // BLTUC_MMR6 + 536889694U, // BLTUC_NM + 201353340U, // BLTZ + 201353340U, // BLTZ64 + 201349397U, // BLTZAL + 201345234U, // BLTZALC + 201345234U, // BLTZALC_MMR6 + 201349594U, // BLTZALL + 201350866U, // BLTZALS_MM + 201349397U, // BLTZAL_MM + 201345473U, // BLTZC + 201345473U, // BLTZC64 + 201345473U, // BLTZC_MMR6 + 201349721U, // BLTZL + 201353340U, // BLTZ_MM + 570442919U, // BMNZI_B + 570450133U, // BMNZ_V + 570442911U, // BMZI_B + 570450119U, // BMZ_V + 536891829U, // BNE + 536891829U, // BNE64 + 536889452U, // BNEC + 536889452U, // BNEC16_NM + 536889452U, // BNEC64 + 536889452U, // BNEC_MMR6 + 536889452U, // BNEC_NM + 536889452U, // BNECzero_NM + 536888337U, // BNEGI_B + 536890249U, // BNEGI_D + 536892068U, // BNEGI_H + 536896141U, // BNEGI_W + 536888305U, // BNEG_B + 536890225U, // BNEG_D + 536892044U, // BNEG_H + 536896036U, // BNEG_W + 754993273U, // BNEIC_NM + 536893818U, // BNEL + 201343607U, // BNEZ16_MM + 201345207U, // BNEZALC + 201345207U, // BNEZALC_MMR6 + 201345433U, // BNEZC + 201343421U, // BNEZC16_MMR6 + 201345433U, // BNEZC16_NM + 201345433U, // BNEZC64 + 201345433U, // BNEZC_MM + 201345433U, // BNEZC_MMR6 + 201345433U, // BNEZC_NM + 536891829U, // BNE_MM + 536889701U, // BNVC + 536889701U, // BNVC_MMR6 + 201344702U, // BNZ_B + 201347297U, // BNZ_D + 201348593U, // BNZ_H + 201351374U, // BNZ_V + 201353131U, // BNZ_W + 536889707U, // BOVC + 536889707U, // BOVC_MMR6 + 557299U, // BPOSGE32 + 559191U, // BPOSGE32C_MMR3 + 557299U, // BPOSGE32_MM + 235018468U, // BREAK + 147962U, // BREAK16_MM + 147962U, // BREAK16_MMR6 + 547044U, // BREAK16_NM + 235018468U, // BREAK_MM + 235018468U, // BREAK_MMR6 + 547044U, // BREAK_NM + 543027U, // BRSC_NM + 570442778U, // BSELI_B + 570450091U, // BSEL_V + 536888452U, // BSETI_B + 536890339U, // BSETI_D + 536892158U, // BSETI_H + 536896231U, // BSETI_W + 536888766U, // BSET_B + 536891051U, // BSET_D + 536892605U, // BSET_H + 536897022U, // BSET_W + 26602U, // BYTEREVW_NM + 201344696U, // BZ_B + 201347281U, // BZ_D + 201348587U, // BZ_H + 201351361U, // BZ_V + 201353125U, // BZ_W + 738224225U, // BeqzRxImm16 + 201353313U, // BeqzRxImmX16 + 4227977U, // Bimm16 + 557961U, // BimmX16 + 738224198U, // BnezRxImm16 + 201353286U, // BnezRxImmX16 + 10794U, // Break16 + 4745327U, // Bteqz16 + 551023U, // BteqzX16 + 4745300U, // Btnez16 + 550996U, // BtnezX16 + 5411201U, // CACHE + 5411171U, // CACHEE + 5411171U, // CACHEE_MM + 5411201U, // CACHE_MM + 5411201U, // CACHE_MMR6 + 50516353U, // CACHE_NM + 5411201U, // CACHE_R6 + 19476U, // CEIL_L_D64 + 19476U, // CEIL_L_D_MMR6 + 23847U, // CEIL_L_S + 23847U, // CEIL_L_S_MMR6 + 20651U, // CEIL_W_D32 + 20651U, // CEIL_W_D64 + 20651U, // CEIL_W_D_MMR6 + 20651U, // CEIL_W_MM + 24189U, // CEIL_W_S + 24189U, // CEIL_W_S_MM + 24189U, // CEIL_W_S_MMR6 + 536888381U, // CEQI_B + 536890284U, // CEQI_D + 536892103U, // CEQI_H + 536896176U, // CEQI_W + 536888535U, // CEQ_B + 536890596U, // CEQ_D + 536892294U, // CEQ_H + 536896452U, // CEQ_W + 16488U, // CFC1 + 16488U, // CFC1_MM + 16704U, // CFC2_MM + 17267U, // CFCMSA + 536895195U, // CINS + 536887588U, // CINS32 + 536895195U, // CINS64_32 + 536895195U, // CINS_i32 + 20121U, // CLASS_D + 20121U, // CLASS_D_MMR6 + 24040U, // CLASS_S + 24040U, // CLASS_S_MMR6 + 536888620U, // CLEI_S_B + 536890856U, // CLEI_S_D + 536892428U, // CLEI_S_H + 536896739U, // CLEI_S_W + 536888835U, // CLEI_U_B + 536891323U, // CLEI_U_D + 536892716U, // CLEI_U_H + 536897207U, // CLEI_U_W + 536888602U, // CLE_S_B + 536890838U, // CLE_S_D + 536892410U, // CLE_S_H + 536896721U, // CLE_S_W + 536888817U, // CLE_U_B + 536891305U, // CLE_U_D + 536892698U, // CLE_U_H + 536897189U, // CLE_U_W + 23193U, // CLO + 23193U, // CLO_MM + 23193U, // CLO_MMR6 + 23193U, // CLO_NM + 23193U, // CLO_R6 + 536888640U, // CLTI_S_B + 536890876U, // CLTI_S_D + 536892448U, // CLTI_S_H + 536896759U, // CLTI_S_W + 536888855U, // CLTI_U_B + 536891343U, // CLTI_U_D + 536892736U, // CLTI_U_H + 536897227U, // CLTI_U_W + 536888708U, // CLT_S_B + 536890954U, // CLT_S_D + 536892536U, // CLT_S_H + 536896887U, // CLT_S_W + 536888935U, // CLT_U_B + 536891433U, // CLT_U_D + 536892826U, // CLT_U_H + 536897317U, // CLT_U_W + 26716U, // CLZ + 26716U, // CLZ_MM + 26716U, // CLZ_MMR6 + 26716U, // CLZ_NM + 26716U, // CLZ_R6 + 536889185U, // CMPGDU_EQ_QB + 536889185U, // CMPGDU_EQ_QB_MMR2 + 536889090U, // CMPGDU_LE_QB + 536889090U, // CMPGDU_LE_QB_MMR2 + 536889304U, // CMPGDU_LT_QB + 536889304U, // CMPGDU_LT_QB_MMR2 + 536889199U, // CMPGU_EQ_QB + 536889199U, // CMPGU_EQ_QB_MM + 536889104U, // CMPGU_LE_QB + 536889104U, // CMPGU_LE_QB_MM + 536889318U, // CMPGU_LT_QB + 536889318U, // CMPGU_LT_QB_MM + 18300U, // CMPU_EQ_QB + 18300U, // CMPU_EQ_QB_MM + 18205U, // CMPU_LE_QB + 18205U, // CMPU_LE_QB_MM + 18419U, // CMPU_LT_QB + 18419U, // CMPU_LT_QB_MM + 536890146U, // CMP_AF_D_MMR6 + 536894669U, // CMP_AF_S_MMR6 + 536890585U, // CMP_EQ_D + 536890585U, // CMP_EQ_D_MMR6 + 22210U, // CMP_EQ_PH + 22210U, // CMP_EQ_PH_MM + 536894873U, // CMP_EQ_S + 536894873U, // CMP_EQ_S_MMR6 + 536890146U, // CMP_F_D + 536894669U, // CMP_F_S + 536889990U, // CMP_LE_D + 536889990U, // CMP_LE_D_MMR6 + 22106U, // CMP_LE_PH + 22106U, // CMP_LE_PH_MM + 536894590U, // CMP_LE_S + 536894590U, // CMP_LE_S_MMR6 + 536891076U, // CMP_LT_D + 536891076U, // CMP_LT_D_MMR6 + 22379U, // CMP_LT_PH + 22379U, // CMP_LT_PH_MM + 536894978U, // CMP_LT_S + 536894978U, // CMP_LT_S_MMR6 + 536890164U, // CMP_SAF_D + 536890164U, // CMP_SAF_D_MMR6 + 536894679U, // CMP_SAF_S + 536894679U, // CMP_SAF_S_MMR6 + 536890612U, // CMP_SEQ_D + 536890612U, // CMP_SEQ_D_MMR6 + 536894892U, // CMP_SEQ_S + 536894892U, // CMP_SEQ_S_MMR6 + 536890027U, // CMP_SLE_D + 536890027U, // CMP_SLE_D_MMR6 + 536894619U, // CMP_SLE_S + 536894619U, // CMP_SLE_S_MMR6 + 536891103U, // CMP_SLT_D + 536891103U, // CMP_SLT_D_MMR6 + 536894997U, // CMP_SLT_S + 536894997U, // CMP_SLT_S_MMR6 + 536890660U, // CMP_SUEQ_D + 536890660U, // CMP_SUEQ_D_MMR6 + 536894923U, // CMP_SUEQ_S + 536894923U, // CMP_SUEQ_S_MMR6 + 536890075U, // CMP_SULE_D + 536890075U, // CMP_SULE_D_MMR6 + 536894650U, // CMP_SULE_S + 536894650U, // CMP_SULE_S_MMR6 + 536891151U, // CMP_SULT_D + 536891151U, // CMP_SULT_D_MMR6 + 536895028U, // CMP_SULT_S + 536895028U, // CMP_SULT_S_MMR6 + 536890533U, // CMP_SUN_D + 536890533U, // CMP_SUN_D_MMR6 + 536894837U, // CMP_SUN_S + 536894837U, // CMP_SUN_S_MMR6 + 536890640U, // CMP_UEQ_D + 536890640U, // CMP_UEQ_D_MMR6 + 536894912U, // CMP_UEQ_S + 536894912U, // CMP_UEQ_S_MMR6 + 536890055U, // CMP_ULE_D + 536890055U, // CMP_ULE_D_MMR6 + 536894639U, // CMP_ULE_S + 536894639U, // CMP_ULE_S_MMR6 + 536891131U, // CMP_ULT_D + 536891131U, // CMP_ULT_D_MMR6 + 536895017U, // CMP_ULT_S + 536895017U, // CMP_ULT_S_MMR6 + 536890515U, // CMP_UN_D + 536890515U, // CMP_UN_D_MMR6 + 536894827U, // CMP_UN_S + 536894827U, // CMP_UN_S_MMR6 + 1073759659U, // COPY_S_B + 1073761927U, // COPY_S_D + 1073763498U, // COPY_S_H + 1073767871U, // COPY_S_W + 1073759874U, // COPY_U_B + 1073763765U, // COPY_U_H + 1073768278U, // COPY_U_W + 536889029U, // CRC32B + 33572549U, // CRC32B_NM + 536889037U, // CRC32CB + 33572557U, // CRC32CB_NM + 536891656U, // CRC32CD + 536892940U, // CRC32CH + 33576460U, // CRC32CH_NM + 536897466U, // CRC32CW + 33580986U, // CRC32CW_NM + 536891642U, // CRC32D + 536892920U, // CRC32H + 33576440U, // CRC32H_NM + 536897458U, // CRC32W + 33580978U, // CRC32W_NM + 17875075U, // CTC1 + 17875075U, // CTC1_MM + 17875291U, // CTC2_MM + 17275U, // CTCMSA + 23643U, // CVT_D32_S + 23643U, // CVT_D32_S_MM + 24972U, // CVT_D32_W + 24972U, // CVT_D32_W_MM + 22769U, // CVT_D64_L + 23643U, // CVT_D64_S + 23643U, // CVT_D64_S_MM + 24972U, // CVT_D64_W + 24972U, // CVT_D64_W_MM + 22769U, // CVT_D_L_MMR6 + 19497U, // CVT_L_D64 + 19497U, // CVT_L_D64_MM + 19497U, // CVT_L_D_MMR6 + 23868U, // CVT_L_S + 23868U, // CVT_L_S_MM + 23868U, // CVT_L_S_MMR6 + 26574U, // CVT_PS_PW64 + 536894942U, // CVT_PS_S64 + 24369U, // CVT_PW_PS64 + 19844U, // CVT_S_D32 + 19844U, // CVT_S_D32_MM + 19844U, // CVT_S_D64 + 19844U, // CVT_S_D64_MM + 22778U, // CVT_S_L + 22778U, // CVT_S_L_MMR6 + 23023U, // CVT_S_PL64 + 24658U, // CVT_S_PU64 + 25727U, // CVT_S_W + 25727U, // CVT_S_W_MM + 25727U, // CVT_S_W_MMR6 + 20672U, // CVT_W_D32 + 20672U, // CVT_W_D32_MM + 20672U, // CVT_W_D64 + 20672U, // CVT_W_D64_MM + 24210U, // CVT_W_S + 24210U, // CVT_W_S_MM + 24210U, // CVT_W_S_MMR6 + 536890577U, // C_EQ_D32 + 536890577U, // C_EQ_D32_MM + 536890577U, // C_EQ_D64 + 536890577U, // C_EQ_D64_MM + 536894865U, // C_EQ_S + 536894865U, // C_EQ_S_MM + 536890139U, // C_F_D32 + 536890139U, // C_F_D32_MM + 536890139U, // C_F_D64 + 536890139U, // C_F_D64_MM + 536894662U, // C_F_S + 536894662U, // C_F_S_MM + 536889982U, // C_LE_D32 + 536889982U, // C_LE_D32_MM + 536889982U, // C_LE_D64 + 536889982U, // C_LE_D64_MM + 536894582U, // C_LE_S + 536894582U, // C_LE_S_MM + 536891068U, // C_LT_D32 + 536891068U, // C_LT_D32_MM + 536891068U, // C_LT_D64 + 536891068U, // C_LT_D64_MM + 536894970U, // C_LT_S + 536894970U, // C_LT_S_MM + 536889973U, // C_NGE_D32 + 536889973U, // C_NGE_D32_MM + 536889973U, // C_NGE_D64 + 536889973U, // C_NGE_D64_MM + 536894573U, // C_NGE_S + 536894573U, // C_NGE_S_MM + 536890008U, // C_NGLE_D32 + 536890008U, // C_NGLE_D32_MM + 536890008U, // C_NGLE_D64 + 536890008U, // C_NGLE_D64_MM + 536894600U, // C_NGLE_S + 536894600U, // C_NGLE_S_MM + 536890425U, // C_NGL_D32 + 536890425U, // C_NGL_D32_MM + 536890425U, // C_NGL_D64 + 536890425U, // C_NGL_D64_MM + 536894796U, // C_NGL_S + 536894796U, // C_NGL_S_MM + 536891059U, // C_NGT_D32 + 536891059U, // C_NGT_D32_MM + 536891059U, // C_NGT_D64 + 536891059U, // C_NGT_D64_MM + 536894961U, // C_NGT_S + 536894961U, // C_NGT_S_MM + 536890018U, // C_OLE_D32 + 536890018U, // C_OLE_D32_MM + 536890018U, // C_OLE_D64 + 536890018U, // C_OLE_D64_MM + 536894610U, // C_OLE_S + 536894610U, // C_OLE_S_MM + 536891094U, // C_OLT_D32 + 536891094U, // C_OLT_D32_MM + 536891094U, // C_OLT_D64 + 536891094U, // C_OLT_D64_MM + 536894988U, // C_OLT_S + 536894988U, // C_OLT_S_MM + 536890603U, // C_SEQ_D32 + 536890603U, // C_SEQ_D32_MM + 536890603U, // C_SEQ_D64 + 536890603U, // C_SEQ_D64_MM + 536894883U, // C_SEQ_S + 536894883U, // C_SEQ_S_MM + 536890209U, // C_SF_D32 + 536890209U, // C_SF_D32_MM + 536890209U, // C_SF_D64 + 536890209U, // C_SF_D64_MM + 536894708U, // C_SF_S + 536894708U, // C_SF_S_MM + 536890631U, // C_UEQ_D32 + 536890631U, // C_UEQ_D32_MM + 536890631U, // C_UEQ_D64 + 536890631U, // C_UEQ_D64_MM + 536894903U, // C_UEQ_S + 536894903U, // C_UEQ_S_MM + 536890046U, // C_ULE_D32 + 536890046U, // C_ULE_D32_MM + 536890046U, // C_ULE_D64 + 536890046U, // C_ULE_D64_MM + 536894630U, // C_ULE_S + 536894630U, // C_ULE_S_MM + 536891122U, // C_ULT_D32 + 536891122U, // C_ULT_D32_MM + 536891122U, // C_ULT_D64 + 536891122U, // C_ULT_D64_MM + 536895008U, // C_ULT_S + 536895008U, // C_ULT_S_MM + 536890507U, // C_UN_D32 + 536890507U, // C_UN_D32_MM + 536890507U, // C_UN_D64 + 536890507U, // C_UN_D64_MM + 536894819U, // C_UN_S + 536894819U, // C_UN_S_MM + 23264U, // CmpRxRy16 + 1610635429U, // CmpiRxImm16 + 22693U, // CmpiRxImmX16 + 536891670U, // DADD + 536893537U, // DADDi + 536895504U, // DADDiu + 536895440U, // DADDu + 536893568U, // DAHI + 536894090U, // DALIGN + 536893629U, // DATI + 536893647U, // DAUI + 23224U, // DBITSWAP + 23192U, // DCLO + 23192U, // DCLO_R6 + 26715U, // DCLZ + 26715U, // DCLZ_R6 + 536895724U, // DDIV + 536895632U, // DDIVU + 11034U, // DERET + 11034U, // DERET_MM + 11034U, // DERET_MMR6 + 11034U, // DERET_NM + 536895408U, // DEXT + 536897885U, // DEXT64_32 + 536894061U, // DEXTM + 536895625U, // DEXTU + 546916U, // DI + 536895201U, // DINS + 536894054U, // DINSM + 536895580U, // DINSU + 536895725U, // DIV + 536895633U, // DIVU + 536895633U, // DIVU_MMR6 + 536895633U, // DIVU_NM + 536895725U, // DIV_MMR6 + 536895725U, // DIV_NM + 536888729U, // DIV_S_B + 536890997U, // DIV_S_D + 536892557U, // DIV_S_H + 536896930U, // DIV_S_W + 536888944U, // DIV_U_B + 536891464U, // DIV_U_D + 536892835U, // DIV_U_H + 536897348U, // DIV_U_W + 546916U, // DI_MM + 546916U, // DI_MMR6 + 546916U, // DI_NM + 536888173U, // DLSA + 536888173U, // DLSA_R6 + 536887303U, // DMFC0 + 16494U, // DMFC1 + 536887622U, // DMFC2 + 251674950U, // DMFC2_OCTEON + 536887310U, // DMFGC0 + 536891722U, // DMOD + 536895454U, // DMODU + 548756U, // DMT + 2752561212U, // DMTC0 + 17875081U, // DMTC1 + 2752561505U, // DMTC2 + 251674977U, // DMTC2_OCTEON + 2752561190U, // DMTGC0 + 548756U, // DMT_NM + 536893524U, // DMUH + 536895497U, // DMUHU + 536893990U, // DMUL + 24461U, // DMULT + 24705U, // DMULTu + 536895541U, // DMULU + 536893990U, // DMUL_R6 + 536890905U, // DOTP_S_D + 536892477U, // DOTP_S_H + 536896798U, // DOTP_S_W + 536891372U, // DOTP_U_D + 536892765U, // DOTP_U_H + 536897256U, // DOTP_U_W + 570445250U, // DPADD_S_D + 570446822U, // DPADD_S_H + 570451133U, // DPADD_S_W + 570445717U, // DPADD_U_D + 570447110U, // DPADD_U_H + 570451601U, // DPADD_U_W + 536893370U, // DPAQX_SA_W_PH + 536893370U, // DPAQX_SA_W_PH_MMR2 + 536893453U, // DPAQX_S_W_PH + 536893453U, // DPAQX_S_W_PH_MMR2 + 536896258U, // DPAQ_SA_L_W + 536896258U, // DPAQ_SA_L_W_MM + 536893412U, // DPAQ_S_W_PH + 536893412U, // DPAQ_S_W_PH_MM + 536893725U, // DPAU_H_QBL + 536893725U, // DPAU_H_QBL_MM + 536894315U, // DPAU_H_QBR + 536894315U, // DPAU_H_QBR_MM + 536893491U, // DPAX_W_PH + 536893491U, // DPAX_W_PH_MMR2 + 536893360U, // DPA_W_PH + 536893360U, // DPA_W_PH_MMR2 + 23269U, // DPOP + 536893385U, // DPSQX_SA_W_PH + 536893385U, // DPSQX_SA_W_PH_MMR2 + 536893467U, // DPSQX_S_W_PH + 536893467U, // DPSQX_S_W_PH_MMR2 + 536896271U, // DPSQ_SA_L_W + 536896271U, // DPSQ_SA_L_W_MM + 536893440U, // DPSQ_S_W_PH + 536893440U, // DPSQ_S_W_PH_MM + 570445217U, // DPSUB_S_D + 570446801U, // DPSUB_S_H + 570451100U, // DPSUB_S_W + 570445684U, // DPSUB_U_D + 570447089U, // DPSUB_U_H + 570451568U, // DPSUB_U_W + 536893737U, // DPSU_H_QBL + 536893737U, // DPSU_H_QBL_MM + 536894327U, // DPSU_H_QBR + 536894327U, // DPSU_H_QBR_MM + 536893502U, // DPSX_W_PH + 536893502U, // DPSX_W_PH_MMR2 + 536893481U, // DPS_W_PH + 536893481U, // DPS_W_PH_MMR2 + 536894500U, // DROTR + 536887579U, // DROTR32 + 536895773U, // DROTRV + 22016U, // DSBH + 26786U, // DSDIV + 20770U, // DSHD + 536893923U, // DSLL + 536887549U, // DSLL32 + 2147506659U, // DSLL64_32 + 536895730U, // DSLLV + 536888167U, // DSRA + 536887531U, // DSRA32 + 536895709U, // DSRAV + 536893951U, // DSRL + 536887557U, // DSRL32 + 536895737U, // DSRLV + 536889419U, // DSUB + 536895419U, // DSUBu + 26772U, // DUDIV + 547656U, // DVP + 545220U, // DVPE + 545220U, // DVPE_NM + 547656U, // DVP_MMR6 + 26787U, // DivRxRy16 + 26773U, // DivuRxRy16 + 10928U, // EHB + 10928U, // EHB_MM + 10928U, // EHB_MMR6 + 10928U, // EHB_NM + 546928U, // EI + 546928U, // EI_MM + 546928U, // EI_MMR6 + 546928U, // EI_NM + 548761U, // EMT + 548761U, // EMT_NM + 11035U, // ERET + 10932U, // ERETNC + 10932U, // ERETNC_MMR6 + 10932U, // ERETNC_NM + 11035U, // ERET_MM + 11035U, // ERET_MMR6 + 11035U, // ERET_NM + 547661U, // EVP + 545226U, // EVPE + 545226U, // EVPE_NM + 547661U, // EVP_MMR6 + 536895409U, // EXT + 536894274U, // EXTP + 536894153U, // EXTPDP + 536895757U, // EXTPDPV + 536895757U, // EXTPDPV_MM + 536894153U, // EXTPDP_MM + 536895766U, // EXTPV + 536895766U, // EXTPV_MM + 536894274U, // EXTP_MM + 536896991U, // EXTRV_RS_W + 536896991U, // EXTRV_RS_W_MM + 536896545U, // EXTRV_R_W + 536896545U, // EXTRV_R_W_MM + 536892566U, // EXTRV_S_H + 536892566U, // EXTRV_S_H_MM + 536897428U, // EXTRV_W + 536897428U, // EXTRV_W_MM + 536896980U, // EXTR_RS_W + 536896980U, // EXTR_RS_W_MM + 536896524U, // EXTR_R_W + 536896524U, // EXTR_R_W_MM + 536892497U, // EXTR_S_H + 536892497U, // EXTR_S_H_MM + 536896623U, // EXTR_W + 536896623U, // EXTR_W_MM + 536895299U, // EXTS + 536887596U, // EXTS32 + 536897508U, // EXTW_NM + 536895409U, // EXT_MM + 536895409U, // EXT_MMR6 + 536895409U, // EXT_NM + 20113U, // FABS_D32 + 20113U, // FABS_D32_MM + 20113U, // FABS_D64 + 20113U, // FABS_D64_MM + 24023U, // FABS_S + 24023U, // FABS_S_MM + 536889922U, // FADD_D + 536889923U, // FADD_D32 + 536889923U, // FADD_D32_MM + 536889923U, // FADD_D64 + 536889923U, // FADD_D64_MM + 536895215U, // FADD_PS64 + 536894566U, // FADD_S + 536894566U, // FADD_S_MM + 570448998U, // FADD_S_MMR6 + 536895893U, // FADD_W + 536890156U, // FCAF_D + 536896012U, // FCAF_W + 536890595U, // FCEQ_D + 536896451U, // FCEQ_W + 20120U, // FCLASS_D + 26091U, // FCLASS_W + 536890000U, // FCLE_D + 536895935U, // FCLE_W + 536891086U, // FCLT_D + 536897030U, // FCLT_W + 5974450U, // FCMP_D32 + 5974450U, // FCMP_D32_MM + 5974450U, // FCMP_D64 + 6498738U, // FCMP_S32 + 6498738U, // FCMP_S32_MM + 536890096U, // FCNE_D + 536895969U, // FCNE_W + 536890705U, // FCOR_D + 536896580U, // FCOR_W + 536890651U, // FCUEQ_D + 536896467U, // FCUEQ_W + 536890066U, // FCULE_D + 536895951U, // FCULE_W + 536891142U, // FCULT_D + 536897046U, // FCULT_W + 536890112U, // FCUNE_D + 536895985U, // FCUNE_W + 536890525U, // FCUN_D + 536896357U, // FCUN_W + 536891518U, // FDIV_D + 536891519U, // FDIV_D32 + 536891519U, // FDIV_D32_MM + 536891519U, // FDIV_D64 + 536891519U, // FDIV_D64_MM + 536895065U, // FDIV_S + 536895065U, // FDIV_S_MM + 570449497U, // FDIV_S_MMR6 + 536897412U, // FDIV_W + 536892224U, // FEXDO_H + 536896373U, // FEXDO_W + 536889809U, // FEXP2_D + 536895796U, // FEXP2_W + 19537U, // FEXUPL_D + 25387U, // FEXUPL_W + 19809U, // FEXUPR_D + 25684U, // FEXUPR_W + 20051U, // FFINT_S_D + 25984U, // FFINT_S_W + 20530U, // FFINT_U_D + 26414U, // FFINT_U_W + 19547U, // FFQL_D + 25397U, // FFQL_W + 19819U, // FFQR_D + 25694U, // FFQR_W + 17584U, // FILL_B + 19522U, // FILL_D + 21273U, // FILL_H + 25372U, // FILL_W + 18888U, // FLOG2_D + 24875U, // FLOG2_W + 19486U, // FLOOR_L_D64 + 19486U, // FLOOR_L_D_MMR6 + 23857U, // FLOOR_L_S + 23857U, // FLOOR_L_S_MMR6 + 20661U, // FLOOR_W_D32 + 20661U, // FLOOR_W_D64 + 20661U, // FLOOR_W_D_MMR6 + 20661U, // FLOOR_W_MM + 24199U, // FLOOR_W_S + 24199U, // FLOOR_W_S_MM + 24199U, // FLOOR_W_S_MMR6 + 570444362U, // FMADD_D + 570450333U, // FMADD_W + 536889847U, // FMAX_A_D + 536895834U, // FMAX_A_W + 536891593U, // FMAX_D + 536897437U, // FMAX_W + 536889827U, // FMIN_A_D + 536895814U, // FMIN_A_W + 536890499U, // FMIN_D + 536896349U, // FMIN_W + 20622U, // FMOV_D32 + 20622U, // FMOV_D32_MM + 20622U, // FMOV_D64 + 20622U, // FMOV_D64_MM + 20622U, // FMOV_D_MMR6 + 24160U, // FMOV_S + 24160U, // FMOV_S_MM + 24160U, // FMOV_S_MMR6 + 570444320U, // FMSUB_D + 570450291U, // FMSUB_W + 536890483U, // FMUL_D + 536890484U, // FMUL_D32 + 536890484U, // FMUL_D32_MM + 536890484U, // FMUL_D64 + 536890484U, // FMUL_D64_MM + 536895231U, // FMUL_PS64 + 536894805U, // FMUL_S + 536894805U, // FMUL_S_MM + 570449237U, // FMUL_S_MMR6 + 536896333U, // FMUL_W + 19314U, // FNEG_D32 + 19314U, // FNEG_D32_MM + 19314U, // FNEG_D64 + 19314U, // FNEG_D64_MM + 23812U, // FNEG_S + 23812U, // FNEG_S_MM + 23812U, // FNEG_S_MMR6 + 2752567531U, // FORK + 2752567531U, // FORK_NM + 19648U, // FRCP_D + 25470U, // FRCP_W + 20268U, // FRINT_D + 26160U, // FRINT_W + 20296U, // FRSQRT_D + 26188U, // FRSQRT_W + 536890175U, // FSAF_D + 536896020U, // FSAF_W + 536890623U, // FSEQ_D + 536896459U, // FSEQ_W + 536890038U, // FSLE_D + 536895943U, // FSLE_W + 536891114U, // FSLT_D + 536897038U, // FSLT_W + 536890104U, // FSNE_D + 536895977U, // FSNE_W + 536890713U, // FSOR_D + 536896588U, // FSOR_W + 20287U, // FSQRT_D + 20288U, // FSQRT_D32 + 20288U, // FSQRT_D32_MM + 20288U, // FSQRT_D64 + 20288U, // FSQRT_D64_MM + 24137U, // FSQRT_S + 24137U, // FSQRT_S_MM + 26179U, // FSQRT_W + 536889880U, // FSUB_D + 536889881U, // FSUB_D32 + 536889881U, // FSUB_D32_MM + 536889881U, // FSUB_D64 + 536889881U, // FSUB_D64_MM + 536895207U, // FSUB_PS64 + 536894548U, // FSUB_S + 536894548U, // FSUB_S_MM + 570448980U, // FSUB_S_MMR6 + 536895851U, // FSUB_W + 536890672U, // FSUEQ_D + 536896476U, // FSUEQ_W + 536890087U, // FSULE_D + 536895960U, // FSULE_W + 536891163U, // FSULT_D + 536897055U, // FSULT_W + 536890121U, // FSUNE_D + 536895994U, // FSUNE_W + 536890544U, // FSUN_D + 536896365U, // FSUN_W + 20062U, // FTINT_S_D + 25995U, // FTINT_S_W + 20541U, // FTINT_U_D + 26425U, // FTINT_U_W + 536892301U, // FTQ_H + 536896485U, // FTQ_W + 19884U, // FTRUNC_S_D + 25767U, // FTRUNC_S_W + 20351U, // FTRUNC_U_D + 26235U, // FTRUNC_U_W + 547034U, // GINVI + 547034U, // GINVI_MMR6 + 547034U, // GINVI_NM + 268459939U, // GINVT + 268459939U, // GINVT_MMR6 + 268459939U, // GINVT_NM + 536890808U, // HADD_S_D + 536892380U, // HADD_S_H + 536896691U, // HADD_S_W + 536891275U, // HADD_U_D + 536892668U, // HADD_U_H + 536897159U, // HADD_U_W + 536890775U, // HSUB_S_D + 536892359U, // HSUB_S_H + 536896658U, // HSUB_S_W + 536891242U, // HSUB_U_D + 536892647U, // HSUB_U_H + 536897126U, // HSUB_U_W + 661951U, // HYPCALL + 661951U, // HYPCALL_MM + 536888999U, // ILVEV_B + 536891509U, // ILVEV_D + 536892890U, // ILVEV_H + 536897403U, // ILVEV_W + 536888527U, // ILVL_B + 536890491U, // ILVL_D + 536892216U, // ILVL_H + 536896341U, // ILVL_W + 536888279U, // ILVOD_B + 536889964U, // ILVOD_D + 536892018U, // ILVOD_H + 536895926U, // ILVOD_W + 536888575U, // ILVR_B + 536890748U, // ILVR_D + 536892341U, // ILVR_H + 536896631U, // ILVR_W + 536895196U, // INS + 292046286U, // INSERT_B + 308825909U, // INSERT_D + 325604557U, // INSERT_H + 342386233U, // INSERT_W + 33579301U, // INSV + 359154656U, // INSVE_B + 375933714U, // INSVE_D + 392712827U, // INSVE_H + 409494019U, // INSVE_W + 33579301U, // INSV_MM + 536895196U, // INS_MM + 536895196U, // INS_MMR6 + 536887297U, // INS_NM + 219361U, // J + 219400U, // JAL + 23544U, // JALR + 547832U, // JALR16_MM + 23544U, // JALR64 + 547832U, // JALRC16_MMR6 + 18725U, // JALRC16_NM + 18139U, // JALRCHB_NM + 18139U, // JALRC_HB_MMR6 + 18725U, // JALRC_MMR6 + 18725U, // JALRC_NM + 541245U, // JALRS16_MM + 24380U, // JALRS_MM + 18156U, // JALR_HB + 18156U, // JALR_HB64 + 23544U, // JALR_MM + 220867U, // JALS_MM + 223256U, // JALX + 223256U, // JALX_MM + 219400U, // JAL_MM + 18590U, // JIALC + 18590U, // JIALC64 + 18590U, // JIALC_MMR6 + 18560U, // JIC + 18560U, // JIC64 + 18560U, // JIC_MMR6 + 547828U, // JR + 541232U, // JR16_MM + 547828U, // JR64 + 547633U, // JRADDIUSP + 543008U, // JRC16_MM + 541110U, // JRC16_MMR6 + 547621U, // JRCADDIUSP_MMR6 + 543008U, // JRC_NM + 542437U, // JR_HB + 542437U, // JR_HB64 + 542437U, // JR_HB64_R6 + 542437U, // JR_HB_R6 + 547828U, // JR_MM + 219361U, // J_MM + 7575816U, // Jal16 + 8100104U, // JalB16 + 10921U, // JrRa16 + 10913U, // JrcRa16 + 543008U, // JrcRx16 + 543013U, // JumpLinkReg16 + 419451474U, // LAPC32_NM + 419447735U, // LAPC48_NM + 50349813U, // LB + 50349813U, // LB16_NM + 50349813U, // LB64 + 50352468U, // LBE + 50352468U, // LBE_MM + 50349813U, // LBGP_NM + 50348621U, // LBU16_MM + 50356150U, // LBU16_NM + 50356150U, // LBUGP_NM + 3254806564U, // LBUX + 3254806564U, // LBUX_MM + 50358308U, // LBUX_NM + 50356150U, // LBU_MMR6 + 50356150U, // LBU_NM + 50356150U, // LBUs9_NM + 50358269U, // LBX_NM + 50349813U, // LB_MM + 50349813U, // LB_MMR6 + 50349813U, // LB_NM + 50349813U, // LBs9_NM + 50356150U, // LBu + 50356150U, // LBu64 + 50352613U, // LBuE + 50352613U, // LBuE_MM + 50356150U, // LBu_MM + 50352427U, // LD + 50348124U, // LDC1 + 50348124U, // LDC164 + 50348124U, // LDC1_D64_MMR6 + 50348124U, // LDC1_MM_D32 + 50348124U, // LDC1_MM_D64 + 50348340U, // LDC2 + 50348340U, // LDC2_MMR6 + 50348340U, // LDC2_R6 + 50348425U, // LDC3 + 17410U, // LDI_B + 19330U, // LDI_D + 21149U, // LDI_H + 25222U, // LDI_W + 50354532U, // LDL + 18657U, // LDPC + 50355122U, // LDR + 3254796444U, // LDXC1 + 3254796444U, // LDXC164 + 50349000U, // LD_B + 50350685U, // LD_D + 50352739U, // LD_H + 50356647U, // LD_W + 167796753U, // LEA_ADDIU_NM + 167796753U, // LEA_ADDiu + 167796752U, // LEA_ADDiu64 + 167796753U, // LEA_ADDiu_MM + 50353692U, // LH + 50353692U, // LH16_NM + 50353692U, // LH64 + 50352520U, // LHE + 50352520U, // LHE_MM + 50353692U, // LHGP_NM + 50348644U, // LHU16_MM + 50356228U, // LHU16_NM + 50356228U, // LHUGP_NM + 50356053U, // LHUXS_NM + 50358314U, // LHUX_NM + 50356228U, // LHU_NM + 50356228U, // LHUs9_NM + 3254806542U, // LHX + 50356041U, // LHXS_NM + 3254806542U, // LHX_MM + 50358286U, // LHX_NM + 50353692U, // LH_MM + 50353692U, // LH_NM + 50353692U, // LHs9_NM + 50356228U, // LHu + 50356228U, // LHu64 + 50352619U, // LHuE + 50352619U, // LHuE_MM + 50356228U, // LHu_MM + 16884U, // LI16_MM + 16884U, // LI16_MMR6 + 218126492U, // LI16_NM + 100680391U, // LI48_NM + 50354628U, // LL + 50354628U, // LL64 + 50354628U, // LL64_R6 + 50352431U, // LLD + 50352431U, // LLD_R6 + 50352543U, // LLE + 50352543U, // LLE_MM + 536897858U, // LLWP_NM + 50354628U, // LL_MM + 50354628U, // LL_MMR6 + 50354628U, // LL_NM + 50354628U, // LL_R6 + 536888174U, // LSA + 3828450158U, // LSA_MMR6 + 536888174U, // LSA_NM + 536888174U, // LSA_R6 + 251680981U, // LUI_MMR6 + 436230357U, // LUI_NM + 3254796458U, // LUXC1 + 3254796458U, // LUXC164 + 3254796458U, // LUXC1_MM + 251680981U, // LUi + 251680981U, // LUi64 + 251680981U, // LUi_MM + 50358213U, // LW + 50348651U, // LW16_MM + 50358213U, // LW16_NM + 50358213U, // LW4x4_NM + 50358213U, // LW64 + 50348176U, // LWC1 + 50348176U, // LWC1_MM + 50348392U, // LWC2 + 50348392U, // LWC2_MMR6 + 50348392U, // LWC2_R6 + 50348437U, // LWC3 + 50358213U, // LWDSP + 50358213U, // LWDSP_MM + 50352637U, // LWE + 50352637U, // LWE_MM + 50358213U, // LWGP16_NM + 50358213U, // LWGP_MM + 50358213U, // LWGP_NM + 50354746U, // LWL + 50354746U, // LWL64 + 50352553U, // LWLE + 50352553U, // LWLE_MM + 50354746U, // LWL_MM + 66065U, // LWM16_MM + 66065U, // LWM16_MMR6 + 65805U, // LWM32_MM + 587225718U, // LWM_NM + 18694U, // LWPC + 18694U, // LWPC_MMR6 + 419449094U, // LWPC_NM + 453008210U, // LWP_MM + 50355256U, // LWR + 50355256U, // LWR64 + 50352601U, // LWRE + 50352601U, // LWRE_MM + 50355256U, // LWR_MM + 50358213U, // LWSP16_NM + 50358213U, // LWSP_MM + 18687U, // LWUPC + 50356375U, // LWU_MM + 3254806576U, // LWX + 3254796472U, // LWXC1 + 3254796472U, // LWXC1_MM + 50356060U, // LWXS16_NM + 3254804316U, // LWXS_MM + 50356060U, // LWXS_NM + 3254806576U, // LWX_MM + 50358320U, // LWX_NM + 50358213U, // LW_MM + 50358213U, // LW_MMR6 + 50358213U, // LW_NM + 50358213U, // LWs9_NM + 50356375U, // LWu + 50349813U, // LbRxRyOffMemX16 + 50356150U, // LbuRxRyOffMemX16 + 50353692U, // LhRxRyOffMemX16 + 50356228U, // LhuRxRyOffMemX16 + 1610635420U, // LiRxImm16 + 22674U, // LiRxImmAlignX16 + 22684U, // LiRxImmX16 + 26565U, // LwRxPcTcp16 + 26565U, // LwRxPcTcpX16 + 50358213U, // LwRxRyOffMemX16 + 50358213U, // LwRxSpImmX16 + 20764U, // MADD + 570444624U, // MADDF_D + 570444624U, // MADDF_D_MMR6 + 570449131U, // MADDF_S + 570449131U, // MADDF_S_MMR6 + 570446705U, // MADDR_Q_H + 570450862U, // MADDR_Q_W + 24535U, // MADDU + 536895447U, // MADDU_DSP + 536895447U, // MADDU_DSP_MM + 24535U, // MADDU_MM + 570443413U, // MADDV_B + 570445923U, // MADDV_D + 570447304U, // MADDV_H + 570451817U, // MADDV_W + 536889931U, // MADD_D32 + 536889931U, // MADD_D32_MM + 536889931U, // MADD_D64 + 536891676U, // MADD_DSP + 536891676U, // MADD_DSP_MM + 20764U, // MADD_MM + 570446675U, // MADD_Q_H + 570450832U, // MADD_Q_W + 536894565U, // MADD_S + 536894565U, // MADD_S_MM + 536893831U, // MAQ_SA_W_PHL + 536893831U, // MAQ_SA_W_PHL_MM + 536894396U, // MAQ_SA_W_PHR + 536894396U, // MAQ_SA_W_PHR_MM + 536893859U, // MAQ_S_W_PHL + 536893859U, // MAQ_S_W_PHL_MM + 536894424U, // MAQ_S_W_PHR + 536894424U, // MAQ_S_W_PHR_MM + 536889872U, // MAXA_D + 536889872U, // MAXA_D_MMR6 + 536894538U, // MAXA_S + 536894538U, // MAXA_S_MMR6 + 536888650U, // MAXI_S_B + 536890886U, // MAXI_S_D + 536892458U, // MAXI_S_H + 536896769U, // MAXI_S_W + 536888865U, // MAXI_U_B + 536891353U, // MAXI_U_D + 536892746U, // MAXI_U_H + 536897237U, // MAXI_U_W + 536888223U, // MAX_A_B + 536889848U, // MAX_A_D + 536891962U, // MAX_A_H + 536895835U, // MAX_A_W + 536891594U, // MAX_D + 536891594U, // MAX_D_MMR6 + 536895131U, // MAX_S + 536888738U, // MAX_S_B + 536891006U, // MAX_S_D + 536892577U, // MAX_S_H + 536895131U, // MAX_S_MMR6 + 536896950U, // MAX_S_W + 536888953U, // MAX_U_B + 536891473U, // MAX_U_D + 536892844U, // MAX_U_H + 536897357U, // MAX_U_W + 536887304U, // MFC0 + 16392U, // MFC0Sel_NM + 536887304U, // MFC0_MMR6 + 536887304U, // MFC0_NM + 16495U, // MFC1 + 16495U, // MFC1_D64 + 16495U, // MFC1_MM + 16495U, // MFC1_MMR6 + 536887623U, // MFC2 + 16711U, // MFC2_MMR6 + 536887311U, // MFGC0 + 536887311U, // MFGC0_MM + 16430U, // MFHC0Sel_NM + 536887342U, // MFHC0_MMR6 + 536887342U, // MFHC0_NM + 16501U, // MFHC1_D32 + 16501U, // MFHC1_D32_MM + 16501U, // MFHC1_D64 + 16501U, // MFHC1_D64_MM + 16717U, // MFHC2_MMR6 + 536887318U, // MFHGC0 + 536887318U, // MFHGC0_MM + 546950U, // MFHI + 541164U, // MFHI16_MM + 546950U, // MFHI64 + 22662U, // MFHI_DSP + 22662U, // MFHI_DSP_MM + 546950U, // MFHI_MM + 547486U, // MFLO + 541215U, // MFLO16_MM + 547486U, // MFLO64 + 23198U, // MFLO_DSP + 23198U, // MFLO_DSP_MM + 547486U, // MFLO_MM + 536894494U, // MFTR + 536894494U, // MFTR_NM + 536889857U, // MINA_D + 536889857U, // MINA_D_MMR6 + 536894530U, // MINA_S + 536894530U, // MINA_S_MMR6 + 536888630U, // MINI_S_B + 536890866U, // MINI_S_D + 536892438U, // MINI_S_H + 536896749U, // MINI_S_W + 536888845U, // MINI_U_B + 536891333U, // MINI_U_D + 536892726U, // MINI_U_H + 536897217U, // MINI_U_W + 536888204U, // MIN_A_B + 536889828U, // MIN_A_D + 536891943U, // MIN_A_H + 536895815U, // MIN_A_W + 536890500U, // MIN_D + 536890500U, // MIN_D_MMR6 + 536894812U, // MIN_S + 536888660U, // MIN_S_B + 536890896U, // MIN_S_D + 536892468U, // MIN_S_H + 536894812U, // MIN_S_MMR6 + 536896789U, // MIN_S_W + 536888875U, // MIN_U_B + 536891363U, // MIN_U_D + 536892756U, // MIN_U_H + 536897247U, // MIN_U_W + 536891723U, // MOD + 536889417U, // MODSUB + 536889417U, // MODSUB_MM + 536895455U, // MODU + 536895455U, // MODU_MMR6 + 536895455U, // MODU_NM + 536891723U, // MOD_MMR6 + 536891723U, // MOD_NM + 536888593U, // MOD_S_B + 536890829U, // MOD_S_D + 536892401U, // MOD_S_H + 536896712U, // MOD_S_W + 536888808U, // MOD_U_B + 536891296U, // MOD_U_D + 536892689U, // MOD_U_H + 536897180U, // MOD_U_W + 20983U, // MOVE16_MM + 16854U, // MOVE16_MMR6 + 536889491U, // MOVEBALC_NM + 536894161U, // MOVEPREV_NM + 536894161U, // MOVEP_MM + 536894161U, // MOVEP_MMR6 + 536894161U, // MOVEP_NM + 20983U, // MOVE_NM + 24739U, // MOVE_V + 536890217U, // MOVF_D32 + 536890217U, // MOVF_D32_MM + 536890217U, // MOVF_D64 + 536891923U, // MOVF_I + 536891923U, // MOVF_I64 + 536891923U, // MOVF_I_MM + 536894716U, // MOVF_S + 536894716U, // MOVF_S_MM + 536890552U, // MOVN_I64_D64 + 536894098U, // MOVN_I64_I + 536894098U, // MOVN_I64_I64 + 536894848U, // MOVN_I64_S + 536890552U, // MOVN_I_D32 + 536890552U, // MOVN_I_D32_MM + 536890552U, // MOVN_I_D64 + 536894098U, // MOVN_I_I + 536894098U, // MOVN_I_I64 + 536894098U, // MOVN_I_MM + 536894848U, // MOVN_I_S + 536894848U, // MOVN_I_S_MM + 536894098U, // MOVN_NM + 536891224U, // MOVT_D32 + 536891224U, // MOVT_D32_MM + 536891224U, // MOVT_D64 + 536895402U, // MOVT_I + 536895402U, // MOVT_I64 + 536895402U, // MOVT_I_MM + 536895057U, // MOVT_S + 536895057U, // MOVT_S_MM + 536891634U, // MOVZ_I64_D64 + 536897666U, // MOVZ_I64_I + 536897666U, // MOVZ_I64_I64 + 536895158U, // MOVZ_I64_S + 536891634U, // MOVZ_I_D32 + 536891634U, // MOVZ_I_D32_MM + 536891634U, // MOVZ_I_D64 + 536897666U, // MOVZ_I_I + 536897666U, // MOVZ_I_I64 + 536897666U, // MOVZ_I_MM + 536895158U, // MOVZ_I_S + 536895158U, // MOVZ_I_S_MM + 536897666U, // MOVZ_NM + 18513U, // MSUB + 570444615U, // MSUBF_D + 570444615U, // MSUBF_D_MMR6 + 570449122U, // MSUBF_S + 570449122U, // MSUBF_S_MMR6 + 570446694U, // MSUBR_Q_H + 570450851U, // MSUBR_Q_W + 24514U, // MSUBU + 536895426U, // MSUBU_DSP + 536895426U, // MSUBU_DSP_MM + 24514U, // MSUBU_MM + 570443404U, // MSUBV_B + 570445914U, // MSUBV_D + 570447295U, // MSUBV_H + 570451808U, // MSUBV_W + 536889889U, // MSUB_D32 + 536889889U, // MSUB_D32_MM + 536889889U, // MSUB_D64 + 536889425U, // MSUB_DSP + 536889425U, // MSUB_DSP_MM + 18513U, // MSUB_MM + 570446665U, // MSUB_Q_H + 570450822U, // MSUB_Q_W + 536894547U, // MSUB_S + 536894547U, // MSUB_S_MM + 2752561213U, // MTC0 + 16445U, // MTC0Sel_NM + 2752561213U, // MTC0_MMR6 + 536887357U, // MTC0_NM + 17875082U, // MTC1 + 17875082U, // MTC1_D64 + 17875082U, // MTC1_D64_MM + 17875082U, // MTC1_MM + 17875082U, // MTC1_MMR6 + 2752561506U, // MTC2 + 17875298U, // MTC2_MMR6 + 2752561191U, // MTGC0 + 2752561191U, // MTGC0_MM + 16437U, // MTHC0Sel_NM + 2752561205U, // MTHC0_MMR6 + 536887349U, // MTHC0_NM + 17924220U, // MTHC1_D32 + 17924220U, // MTHC1_D32_MM + 17924220U, // MTHC1_D64 + 17924220U, // MTHC1_D64_MM + 17875284U, // MTHC2_MMR6 + 2752561182U, // MTHGC0 + 2752561182U, // MTHGC0_MM + 546956U, // MTHI + 546956U, // MTHI64 + 17881228U, // MTHI_DSP + 17881228U, // MTHI_DSP_MM + 546956U, // MTHI_MM + 17881816U, // MTHLIP + 17881816U, // MTHLIP_MM + 547499U, // MTLO + 547499U, // MTLO64 + 17881771U, // MTLO_DSP + 17881771U, // MTLO_DSP_MM + 547499U, // MTLO_MM + 540745U, // MTM0 + 540870U, // MTM1 + 541044U, // MTM2 + 540751U, // MTP0 + 540876U, // MTP1 + 541050U, // MTP2 + 68213803U, // MTTR + 68213803U, // MTTR_NM + 536893525U, // MUH + 536895498U, // MUHU + 536895498U, // MUHU_MMR6 + 536895498U, // MUHU_NM + 536893525U, // MUH_MMR6 + 536893525U, // MUH_NM + 536893991U, // MUL + 536893991U, // MUL4x4_NM + 536893872U, // MULEQ_S_W_PHL + 536893872U, // MULEQ_S_W_PHL_MM + 536894437U, // MULEQ_S_W_PHR + 536894437U, // MULEQ_S_W_PHR_MM + 536893749U, // MULEU_S_PH_QBL + 536893749U, // MULEU_S_PH_QBL_MM + 536894339U, // MULEU_S_PH_QBR + 536894339U, // MULEU_S_PH_QBR_MM + 536893279U, // MULQ_RS_PH + 536893279U, // MULQ_RS_PH_MM + 536896969U, // MULQ_RS_W + 536896969U, // MULQ_RS_W_MMR2 + 536893223U, // MULQ_S_PH + 536893223U, // MULQ_S_PH_MMR2 + 536896828U, // MULQ_S_W + 536896828U, // MULQ_S_W_MMR2 + 536895256U, // MULR_PS64 + 536892284U, // MULR_Q_H + 536896441U, // MULR_Q_W + 536893425U, // MULSAQ_S_W_PH + 536893425U, // MULSAQ_S_W_PH_MM + 536893400U, // MULSA_W_PH + 536893400U, // MULSA_W_PH_MMR2 + 24462U, // MULT + 536895618U, // MULTU_DSP + 536895618U, // MULTU_DSP_MM + 536895374U, // MULT_DSP + 536895374U, // MULT_DSP_MM + 24462U, // MULT_MM + 24706U, // MULTu + 24706U, // MULTu_MM + 536895535U, // MULU + 536895535U, // MULU_MMR6 + 536895535U, // MULU_NM + 536889008U, // MULV_B + 536891526U, // MULV_D + 536892899U, // MULV_H + 536897420U, // MULV_W + 536893991U, // MUL_MM + 536893991U, // MUL_MMR6 + 536893991U, // MUL_NM + 536893096U, // MUL_PH + 536893096U, // MUL_PH_MMR2 + 536892253U, // MUL_Q_H + 536896410U, // MUL_Q_W + 536893991U, // MUL_R6 + 536893191U, // MUL_S_PH + 536893191U, // MUL_S_PH_MMR2 + 546950U, // Mfhi16 + 547486U, // Mflo16 + 20983U, // Move32R16 + 20983U, // MoveR3216 + 17327U, // NLOC_B + 18994U, // NLOC_D + 21066U, // NLOC_H + 24956U, // NLOC_W + 17343U, // NLZC_B + 19002U, // NLZC_D + 21082U, // NLZC_H + 24964U, // NLZC_W + 536889939U, // NMADD_D32 + 536889939U, // NMADD_D32_MM + 536889939U, // NMADD_D64 + 536894564U, // NMADD_S + 536894564U, // NMADD_S_MM + 536889897U, // NMSUB_D32 + 536889897U, // NMSUB_D32_MM + 536889897U, // NMSUB_D64 + 536894546U, // NMSUB_S + 536894546U, // NMSUB_S_MM + 10802U, // NOP32_NM + 11006U, // NOP_NM + 536894462U, // NOR + 536894462U, // NOR64 + 536888416U, // NORI_B + 536894462U, // NOR_MM + 536894462U, // NOR_MMR6 + 536894462U, // NOR_NM + 536895667U, // NOR_V + 16966U, // NOT16_MM + 16966U, // NOT16_MMR6 + 24478U, // NOT16_NM + 21017U, // NegRxRy16 + 24478U, // NotRxRy16 + 536894463U, // OR + 20021815U, // OR16_MM + 20021815U, // OR16_MMR6 + 536894463U, // OR16_NM + 536894463U, // OR64 + 536888417U, // ORI_B + 536893624U, // ORI_MMR6 + 536893624U, // ORI_NM + 536894463U, // OR_MM + 536894463U, // OR_MMR6 + 536894463U, // OR_NM + 536895668U, // OR_V + 536893624U, // ORi + 536893624U, // ORi64 + 536893624U, // ORi_MM + 33577983U, // OrRxRxRy16 + 536893085U, // PACKRL_PH + 536893085U, // PACKRL_PH_MM + 10939U, // PAUSE + 10939U, // PAUSE_MM + 10939U, // PAUSE_MMR6 + 10939U, // PAUSE_NM + 536888990U, // PCKEV_B + 536891500U, // PCKEV_D + 536892881U, // PCKEV_H + 536897394U, // PCKEV_W + 536888270U, // PCKOD_B + 536889955U, // PCKOD_D + 536892009U, // PCKOD_H + 536895917U, // PCKOD_W + 17862U, // PCNT_B + 20260U, // PCNT_D + 21701U, // PCNT_H + 26152U, // PCNT_W + 536893049U, // PICK_PH + 536893049U, // PICK_PH_MM + 536889149U, // PICK_QB + 536889149U, // PICK_QB_MM + 536895223U, // PLL_PS64 + 536895265U, // PLU_PS64 + 23270U, // POP + 22868U, // PRECEQU_PH_QBL + 17200U, // PRECEQU_PH_QBLA + 17200U, // PRECEQU_PH_QBLA_MM + 22868U, // PRECEQU_PH_QBL_MM + 23458U, // PRECEQU_PH_QBR + 17238U, // PRECEQU_PH_QBRA + 17238U, // PRECEQU_PH_QBRA_MM + 23458U, // PRECEQU_PH_QBR_MM + 22933U, // PRECEQ_W_PHL + 22933U, // PRECEQ_W_PHL_MM + 23498U, // PRECEQ_W_PHR + 23498U, // PRECEQ_W_PHR_MM + 22853U, // PRECEU_PH_QBL + 17184U, // PRECEU_PH_QBLA + 17184U, // PRECEU_PH_QBLA_MM + 22853U, // PRECEU_PH_QBL_MM + 23443U, // PRECEU_PH_QBR + 17222U, // PRECEU_PH_QBRA + 17222U, // PRECEU_PH_QBRA_MM + 23443U, // PRECEU_PH_QBR_MM + 536893001U, // PRECRQU_S_QB_PH + 536893001U, // PRECRQU_S_QB_PH_MM + 536896060U, // PRECRQ_PH_W + 536896060U, // PRECRQ_PH_W_MM + 536892974U, // PRECRQ_QB_PH + 536892974U, // PRECRQ_QB_PH_MM + 536896091U, // PRECRQ_RS_PH_W + 536896091U, // PRECRQ_RS_PH_W_MM + 536892988U, // PRECR_QB_PH + 536892988U, // PRECR_QB_PH_MMR2 + 536896044U, // PRECR_SRA_PH_W + 536896044U, // PRECR_SRA_PH_W_MMR2 + 536896073U, // PRECR_SRA_R_PH_W + 536896073U, // PRECR_SRA_R_PH_W_MMR2 + 5411341U, // PREF + 5411179U, // PREFE + 5411179U, // PREFE_MM + 473081863U, // PREFX_MM + 5411341U, // PREF_MM + 5411341U, // PREF_MMR6 + 50516493U, // PREF_NM + 5411341U, // PREF_R6 + 50516493U, // PREFs9_NM + 536891705U, // PREPEND + 536891705U, // PREPEND_MMR2 + 536895239U, // PUL_PS64 + 536895273U, // PUU_PS64 + 18489U, // RADDU_W_QB + 18489U, // RADDU_W_QB_MM + 234904343U, // RDDSP + 218127127U, // RDDSP_MM + 536894513U, // RDHWR + 536894513U, // RDHWR64 + 536894513U, // RDHWR_MM + 536894513U, // RDHWR_MMR6 + 536894513U, // RDHWR_NM + 23566U, // RDPGPR_MMR6 + 23566U, // RDPGPR_NM + 19656U, // RECIP_D32 + 19656U, // RECIP_D32_MM + 19656U, // RECIP_D64 + 19656U, // RECIP_D64_MM + 23944U, // RECIP_S + 23944U, // RECIP_S_MM + 22428U, // REPLV_PH + 22428U, // REPLV_PH_MM + 18469U, // REPLV_QB + 18469U, // REPLV_QB_MM + 22155U, // REPL_PH + 22155U, // REPL_PH_MM + 486557519U, // REPL_QB + 486557519U, // REPL_QB_MM + 248088U, // RESTOREJRC16_NM + 264472U, // RESTOREJRC_NM + 266704U, // RESTORE_NM + 20269U, // RINT_D + 20269U, // RINT_D_MMR6 + 24128U, // RINT_S + 24128U, // RINT_S_MMR6 + 536894501U, // ROTR + 536895774U, // ROTRV + 536895774U, // ROTRV_MM + 536895774U, // ROTRV_NM + 536894501U, // ROTR_MM + 536894501U, // ROTR_NM + 536897566U, // ROTX_NM + 19465U, // ROUND_L_D64 + 19465U, // ROUND_L_D_MMR6 + 23836U, // ROUND_L_S + 23836U, // ROUND_L_S_MMR6 + 20640U, // ROUND_W_D32 + 20640U, // ROUND_W_D64 + 20640U, // ROUND_W_D_MMR6 + 20640U, // ROUND_W_MM + 24178U, // ROUND_W_S + 24178U, // ROUND_W_S_MM + 24178U, // ROUND_W_S_MMR6 + 20297U, // RSQRT_D32 + 20297U, // RSQRT_D32_MM + 20297U, // RSQRT_D64 + 20297U, // RSQRT_D64_MM + 24136U, // RSQRT_S + 24136U, // RSQRT_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 8405787U, // SAA + 8409346U, // SAAD + 536888699U, // SAT_S_B + 536890945U, // SAT_S_D + 536892527U, // SAT_S_H + 536896878U, // SAT_S_W + 536888926U, // SAT_U_B + 536891424U, // SAT_U_D + 536892817U, // SAT_U_H + 536897308U, // SAT_U_W + 250353U, // SAVE16_NM + 266737U, // SAVE_NM + 50350149U, // SB + 50348458U, // SB16_MM + 50348458U, // SB16_MMR6 + 50350149U, // SB16_NM + 50350149U, // SB64 + 50352473U, // SBE + 50352473U, // SBE_MM + 50350149U, // SBGP_NM + 50358274U, // SBX_NM + 50350149U, // SB_MM + 50350149U, // SB_MMR6 + 50350149U, // SB_NM + 50350149U, // SBs9_NM + 8964399U, // SC + 8964399U, // SC64 + 8964399U, // SC64_R6 + 8966417U, // SCD + 8966417U, // SCD_R6 + 8966494U, // SCE + 8966494U, // SCE_MM + 606136636U, // SCWP_NM + 8964399U, // SC_MM + 8964399U, // SC_MMR6 + 8964399U, // SC_NM + 8964399U, // SC_R6 + 50352464U, // SD + 285378U, // SDBBP + 148007U, // SDBBP16_MM + 148007U, // SDBBP16_MMR6 + 547522U, // SDBBP16_NM + 662210U, // SDBBP_MM + 285378U, // SDBBP_MMR6 + 547522U, // SDBBP_NM + 285378U, // SDBBP_R6 + 50348130U, // SDC1 + 50348130U, // SDC164 + 50348130U, // SDC1_D64_MMR6 + 50348130U, // SDC1_MM_D32 + 50348130U, // SDC1_MM_D64 + 50348346U, // SDC2 + 50348346U, // SDC2_MMR6 + 50348346U, // SDC2_R6 + 50348431U, // SDC3 + 26787U, // SDIV + 26787U, // SDIV_MM + 50354537U, // SDL + 50355127U, // SDR + 3254796451U, // SDXC1 + 3254796451U, // SDXC164 + 18134U, // SEB + 18134U, // SEB64 + 18134U, // SEB_MM + 18134U, // SEB_NM + 22037U, // SEH + 22037U, // SEH64 + 22037U, // SEH_MM + 22037U, // SEH_NM + 536897639U, // SELEQZ + 536897639U, // SELEQZ64 + 536891624U, // SELEQZ_D + 536891624U, // SELEQZ_D_MMR6 + 536897639U, // SELEQZ_MMR6 + 536895148U, // SELEQZ_S + 536895148U, // SELEQZ_S_MMR6 + 536897612U, // SELNEZ + 536897612U, // SELNEZ64 + 536891607U, // SELNEZ_D + 536891607U, // SELNEZ_D_MMR6 + 536897612U, // SELNEZ_MMR6 + 536895138U, // SELNEZ_S + 536895138U, // SELNEZ_S_MMR6 + 570444850U, // SEL_D + 570444850U, // SEL_D_MMR6 + 570449221U, // SEL_S + 570449221U, // SEL_S_MMR6 + 536894305U, // SEQ + 536893611U, // SEQI_NM + 536893611U, // SEQi + 50354251U, // SH + 50348510U, // SH16_MM + 50348510U, // SH16_MMR6 + 50354251U, // SH16_NM + 50354251U, // SH64 + 50352525U, // SHE + 50352525U, // SHE_MM + 536888298U, // SHF_B + 536892037U, // SHF_H + 536896029U, // SHF_W + 50354251U, // SHGP_NM + 23204U, // SHILO + 24832U, // SHILOV + 24832U, // SHILOV_MM + 23204U, // SHILO_MM + 536893330U, // SHLLV_PH + 536893330U, // SHLLV_PH_MM + 536889371U, // SHLLV_QB + 536889371U, // SHLLV_QB_MM + 536893267U, // SHLLV_S_PH + 536893267U, // SHLLV_S_PH_MM + 536896939U, // SHLLV_S_W + 536896939U, // SHLLV_S_W_MM + 536893058U, // SHLL_PH + 536893058U, // SHLL_PH_MM + 536889158U, // SHLL_QB + 536889158U, // SHLL_QB_MM + 536893180U, // SHLL_S_PH + 536893180U, // SHLL_S_PH_MM + 536896779U, // SHLL_S_W + 536896779U, // SHLL_S_W_MM + 536893320U, // SHRAV_PH + 536893320U, // SHRAV_PH_MM + 536889361U, // SHRAV_QB + 536889361U, // SHRAV_QB_MMR2 + 536893168U, // SHRAV_R_PH + 536893168U, // SHRAV_R_PH_MM + 536889259U, // SHRAV_R_QB + 536889259U, // SHRAV_R_QB_MMR2 + 536896534U, // SHRAV_R_W + 536896534U, // SHRAV_R_W_MM + 536892965U, // SHRA_PH + 536892965U, // SHRA_PH_MM + 536889081U, // SHRA_QB + 536889081U, // SHRA_QB_MMR2 + 536893133U, // SHRA_R_PH + 536893133U, // SHRA_R_PH_MM + 536889224U, // SHRA_R_QB + 536889224U, // SHRA_R_QB_MMR2 + 536896492U, // SHRA_R_W + 536896492U, // SHRA_R_W_MM + 536893350U, // SHRLV_PH + 536893350U, // SHRLV_PH_MMR2 + 536889391U, // SHRLV_QB + 536889391U, // SHRLV_QB_MM + 536893076U, // SHRL_PH + 536893076U, // SHRL_PH_MMR2 + 536889176U, // SHRL_QB + 536889176U, // SHRL_QB_MM + 50356047U, // SHXS_NM + 50358291U, // SHX_NM + 50354251U, // SH_MM + 50354251U, // SH_MMR6 + 50354251U, // SH_NM + 50354251U, // SHs9_NM + 299410U, // SIGRIE + 299410U, // SIGRIE_MMR6 + 545170U, // SIGRIE_NM + 1107313665U, // SLDI_B + 1107315585U, // SLDI_D + 1107317404U, // SLDI_H + 1107321477U, // SLDI_W + 1107313607U, // SLD_B + 1107315292U, // SLD_D + 1107317346U, // SLD_H + 1107321254U, // SLD_W + 536893924U, // SLL + 536887811U, // SLL16_MM + 536887811U, // SLL16_MMR6 + 536893924U, // SLL16_NM + 1073764836U, // SLL64_32 + 1073764836U, // SLL64_64 + 536888355U, // SLLI_B + 536890258U, // SLLI_D + 536892077U, // SLLI_H + 536896150U, // SLLI_W + 536895731U, // SLLV + 536895731U, // SLLV_MM + 536895731U, // SLLV_NM + 536888504U, // SLL_B + 536890442U, // SLL_D + 536892193U, // SLL_H + 536893924U, // SLL_MM + 536893924U, // SLL_MMR6 + 536893924U, // SLL_NM + 536896292U, // SLL_W + 536895363U, // SLT + 536895363U, // SLT64 + 536895519U, // SLTIU_NM + 536893635U, // SLTI_NM + 536895605U, // SLTU_NM + 536895363U, // SLT_MM + 536895363U, // SLT_NM + 536893635U, // SLTi + 536893635U, // SLTi64 + 536893635U, // SLTi_MM + 536895519U, // SLTiu + 536895519U, // SLTiu64 + 536895519U, // SLTiu_MM + 536895605U, // SLTu + 536895605U, // SLTu64 + 536895605U, // SLTu_MM + 536891834U, // SNE + 536893556U, // SNEi + 536895752U, // SOV_NM + 1073759354U, // SPLATI_B + 1073761241U, // SPLATI_D + 1073763060U, // SPLATI_H + 1073767133U, // SPLATI_W + 1073759669U, // SPLAT_B + 1073761954U, // SPLAT_D + 1073763508U, // SPLAT_H + 1073767925U, // SPLAT_W + 536888168U, // SRA + 536888313U, // SRAI_B + 536890233U, // SRAI_D + 536892052U, // SRAI_H + 536896125U, // SRAI_W + 536888389U, // SRARI_B + 536890292U, // SRARI_D + 536892111U, // SRARI_H + 536896184U, // SRARI_W + 536888542U, // SRAR_B + 536890681U, // SRAR_D + 536892308U, // SRAR_H + 536896556U, // SRAR_W + 536895710U, // SRAV + 536895710U, // SRAV_MM + 536895710U, // SRAV_NM + 536888232U, // SRA_B + 536889865U, // SRA_D + 536891971U, // SRA_H + 536888168U, // SRA_MM + 536888168U, // SRA_NM + 536895844U, // SRA_W + 536893952U, // SRL + 536887818U, // SRL16_MM + 536887818U, // SRL16_MMR6 + 536893952U, // SRL16_NM + 536888363U, // SRLI_B + 536890266U, // SRLI_D + 536892085U, // SRLI_H + 536896158U, // SRLI_W + 536888407U, // SRLRI_B + 536890310U, // SRLRI_D + 536892129U, // SRLRI_H + 536896202U, // SRLRI_W + 536888558U, // SRLR_B + 536890697U, // SRLR_D + 536892324U, // SRLR_H + 536896572U, // SRLR_W + 536895738U, // SRLV + 536895738U, // SRLV_MM + 536895738U, // SRLV_NM + 536888511U, // SRL_B + 536890467U, // SRL_D + 536892200U, // SRL_H + 536893952U, // SRL_MM + 536893952U, // SRL_NM + 536896317U, // SRL_W + 11004U, // SSNOP + 11004U, // SSNOP_MM + 11004U, // SSNOP_MMR6 + 50349528U, // ST_B + 50351954U, // ST_D + 50353367U, // ST_H + 50357846U, // ST_W + 536889420U, // SUB + 536893029U, // SUBQH_PH + 536893029U, // SUBQH_PH_MMR2 + 536893144U, // SUBQH_R_PH + 536893144U, // SUBQH_R_PH_MMR2 + 536896502U, // SUBQH_R_W + 536896502U, // SUBQH_R_W_MMR2 + 536896107U, // SUBQH_W + 536896107U, // SUBQH_W_MMR2 + 536893104U, // SUBQ_PH + 536893104U, // SUBQ_PH_MM + 536893201U, // SUBQ_S_PH + 536893201U, // SUBQ_S_PH_MM + 536896808U, // SUBQ_S_W + 536896808U, // SUBQ_S_W_MM + 536888914U, // SUBSUS_U_B + 536891412U, // SUBSUS_U_D + 536892805U, // SUBSUS_U_H + 536897296U, // SUBSUS_U_W + 536888717U, // SUBSUU_S_B + 536890985U, // SUBSUU_S_D + 536892545U, // SUBSUU_S_H + 536896918U, // SUBSUU_S_W + 536888679U, // SUBS_S_B + 536890925U, // SUBS_S_D + 536892507U, // SUBS_S_H + 536896858U, // SUBS_S_W + 536888894U, // SUBS_U_B + 536891392U, // SUBS_U_D + 536892785U, // SUBS_U_H + 536897276U, // SUBS_U_W + 536887892U, // SUBU16_MM + 536887892U, // SUBU16_MMR6 + 536889129U, // SUBUH_QB + 536889129U, // SUBUH_QB_MMR2 + 536889235U, // SUBUH_R_QB + 536889235U, // SUBUH_R_QB_MMR2 + 536895420U, // SUBU_MMR6 + 536893302U, // SUBU_PH + 536893302U, // SUBU_PH_MMR2 + 536889343U, // SUBU_QB + 536889343U, // SUBU_QB_MM + 536893245U, // SUBU_S_PH + 536893245U, // SUBU_S_PH_MMR2 + 536889282U, // SUBU_S_QB + 536889282U, // SUBU_S_QB_MM + 536888461U, // SUBVI_B + 536890348U, // SUBVI_D + 536892167U, // SUBVI_H + 536896240U, // SUBVI_W + 536888973U, // SUBV_B + 536891483U, // SUBV_D + 536892864U, // SUBV_H + 536897377U, // SUBV_W + 536889420U, // SUB_MM + 536889420U, // SUB_MMR6 + 536889420U, // SUB_NM + 536895420U, // SUBu + 536895420U, // SUBu16_NM + 536895420U, // SUBu_MM + 536895420U, // SUBu_NM + 3254796465U, // SUXC1 + 3254796465U, // SUXC164 + 3254796465U, // SUXC1_MM + 50358235U, // SW + 50348657U, // SW16_MM + 50348657U, // SW16_MMR6 + 50358235U, // SW16_NM + 50358235U, // SW4x4_NM + 50358235U, // SW64 + 50348182U, // SWC1 + 50348182U, // SWC1_MM + 50348398U, // SWC2 + 50348398U, // SWC2_MMR6 + 50348398U, // SWC2_R6 + 50348443U, // SWC3 + 50358235U, // SWDSP + 50358235U, // SWDSP_MM + 50352642U, // SWE + 50352642U, // SWE_MM + 50358235U, // SWGP16_NM + 50358235U, // SWGP_NM + 50354751U, // SWL + 50354751U, // SWL64 + 50352559U, // SWLE + 50352559U, // SWLE_MM + 50354751U, // SWL_MM + 66072U, // SWM16_MM + 66072U, // SWM16_MMR6 + 65812U, // SWM32_MM + 587225725U, // SWM_NM + 419449100U, // SWPC_NM + 453008215U, // SWP_MM + 50355261U, // SWR + 50355261U, // SWR64 + 50352607U, // SWRE + 50352607U, // SWRE_MM + 50355261U, // SWR_MM + 50358235U, // SWSP16_NM + 50355004U, // SWSP_MM + 50358235U, // SWSP_MMR6 + 3254796479U, // SWXC1 + 3254796479U, // SWXC1_MM + 50356066U, // SWXS_NM + 50358325U, // SWX_NM + 50358235U, // SW_MM + 50358235U, // SW_MMR6 + 50358235U, // SW_NM + 50358235U, // SWs9_NM + 714997U, // SYNC + 317530U, // SYNCI + 317530U, // SYNCI_MM + 317530U, // SYNCI_MMR6 + 317530U, // SYNCI_NM + 317530U, // SYNCIs9_NM + 714997U, // SYNC_MM + 706779U, // SYNC_MMR6 + 706779U, // SYNC_NM + 285128U, // SYSCALL + 547272U, // SYSCALL16_NM + 661960U, // SYSCALL_MM + 547272U, // SYSCALL_NM + 0U, // Save16 + 0U, // SaveX16 + 50350149U, // SbRxRyOffMemX16 + 551048U, // SebRx16 + 551054U, // SehRx16 + 50354251U, // ShRxRyOffMemX16 + 536893924U, // SllX16 + 33579251U, // SllvRxRy16 + 24451U, // SltRxRy16 + 1610635459U, // SltiRxImm16 + 22723U, // SltiRxImmX16 + 1610637343U, // SltiuRxImm16 + 24607U, // SltiuRxImmX16 + 24693U, // SltuRxRy16 + 536888168U, // SraX16 + 33579230U, // SravRxRy16 + 536893952U, // SrlX16 + 33579258U, // SrlvRxRy16 + 536895420U, // SubuRxRyRz16 + 50358235U, // SwRxRyOffMemX16 + 50358235U, // SwRxSpImmX16 + 536894310U, // TEQ + 22705U, // TEQI + 22705U, // TEQI_MM + 536894310U, // TEQ_MM + 536894310U, // TEQ_NM + 536891772U, // TGE + 22638U, // TGEI + 24600U, // TGEIU + 24600U, // TGEIU_MM + 22638U, // TGEI_MM + 536895473U, // TGEU + 536895473U, // TGEU_MM + 536891772U, // TGE_MM + 11052U, // TLBGINV + 10953U, // TLBGINVF + 10953U, // TLBGINVF_MM + 11052U, // TLBGINV_MM + 10998U, // TLBGP + 10998U, // TLBGP_MM + 11015U, // TLBGR + 11015U, // TLBGR_MM + 10968U, // TLBGWI + 10968U, // TLBGWI_MM + 11027U, // TLBGWR + 11027U, // TLBGWR_MM + 11045U, // TLBINV + 10945U, // TLBINVF + 10945U, // TLBINVF_MMR6 + 10945U, // TLBINVF_NM + 11045U, // TLBINV_MMR6 + 11045U, // TLBINV_NM + 10993U, // TLBP + 10993U, // TLBP_MM + 10993U, // TLBP_NM + 11010U, // TLBR + 11010U, // TLBR_MM + 11010U, // TLBR_NM + 10962U, // TLBWI + 10962U, // TLBWI_MM + 10962U, // TLBWI_NM + 11021U, // TLBWR + 11021U, // TLBWR_MM + 11021U, // TLBWR_NM + 536895368U, // TLT + 22729U, // TLTI + 24614U, // TLTIU_MM + 22729U, // TLTI_MM + 536895611U, // TLTU + 536895611U, // TLTU_MM + 536895368U, // TLT_MM + 536891839U, // TNE + 22650U, // TNEI + 22650U, // TNEI_MM + 536891839U, // TNE_MM + 536891839U, // TNE_NM + 19454U, // TRUNC_L_D64 + 19454U, // TRUNC_L_D_MMR6 + 23825U, // TRUNC_L_S + 23825U, // TRUNC_L_S_MMR6 + 20629U, // TRUNC_W_D32 + 20629U, // TRUNC_W_D64 + 20629U, // TRUNC_W_D_MMR6 + 20629U, // TRUNC_W_MM + 24167U, // TRUNC_W_S + 24167U, // TRUNC_W_S_MM + 24167U, // TRUNC_W_S_MMR6 + 24614U, // TTLTIU + 50353690U, // UALH_NM + 587225716U, // UALWM_NM + 50358211U, // UALW_NM + 50354249U, // UASH_NM + 587225723U, // UASWM_NM + 50358233U, // UASW_NM + 26773U, // UDIV + 26773U, // UDIV_MM + 536895533U, // V3MULU + 536887363U, // VMM0 + 536895548U, // VMULU + 570442729U, // VSHF_B + 570444633U, // VSHF_D + 570446468U, // VSHF_H + 570450460U, // VSHF_W + 11040U, // WAIT + 663416U, // WAIT_MM + 663416U, // WAIT_MMR6 + 663416U, // WAIT_NM + 234904350U, // WRDSP + 218127134U, // WRDSP_MM + 23574U, // WRPGPR_MMR6 + 23574U, // WRPGPR_NM + 22022U, // WSBH + 22022U, // WSBH_MM + 22022U, // WSBH_MMR6 + 536894473U, // XOR + 20021814U, // XOR16_MM + 20021814U, // XOR16_MMR6 + 536894473U, // XOR16_NM + 536894473U, // XOR64 + 536888424U, // XORI_B + 536893623U, // XORI_MMR6 + 536893623U, // XORI_NM + 536894473U, // XOR_MM + 536894473U, // XOR_MMR6 + 536894473U, // XOR_NM + 536895674U, // XOR_V + 536893623U, // XORi + 536893623U, // XORi64 + 536893623U, // XORi_MM + 33577993U, // XorRxRxRy16 + 20776U, // YIELD + 20776U, // YIELD_NM }; - static const uint8_t OpInfo2[] = { + static const uint16_t OpInfo1[] = { 0U, // PHI 0U, // INLINEASM + 0U, // INLINEASM_BR 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG @@ -1815,1331 +4463,567 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE 0U, // STACKMAP + 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG 0U, // STATEPOINT - 0U, // FRAME_ALLOC - 0U, // ABSQ_S_PH - 0U, // ABSQ_S_QB - 0U, // ABSQ_S_W - 0U, // ADD - 0U, // ADDIUPC - 0U, // ADDIUPC_MM - 0U, // ADDIUR1SP_MM - 0U, // ADDIUR2_MM - 0U, // ADDIUS5_MM - 0U, // ADDIUSP_MM - 0U, // ADDQH_PH - 0U, // ADDQH_R_PH - 0U, // ADDQH_R_W - 0U, // ADDQH_W - 0U, // ADDQ_PH - 0U, // ADDQ_S_PH - 0U, // ADDQ_S_W - 0U, // ADDSC - 0U, // ADDS_A_B - 0U, // ADDS_A_D - 0U, // ADDS_A_H - 0U, // ADDS_A_W - 0U, // ADDS_S_B - 0U, // ADDS_S_D - 0U, // ADDS_S_H - 0U, // ADDS_S_W - 0U, // ADDS_U_B - 0U, // ADDS_U_D - 0U, // ADDS_U_H - 0U, // ADDS_U_W - 0U, // ADDU16_MM - 0U, // ADDUH_QB - 0U, // ADDUH_R_QB - 0U, // ADDU_PH - 0U, // ADDU_QB - 0U, // ADDU_S_PH - 0U, // ADDU_S_QB - 0U, // ADDVI_B - 0U, // ADDVI_D - 0U, // ADDVI_H - 0U, // ADDVI_W - 0U, // ADDV_B - 0U, // ADDV_D - 0U, // ADDV_H - 0U, // ADDV_W - 0U, // ADDWC - 0U, // ADD_A_B - 0U, // ADD_A_D - 0U, // ADD_A_H - 0U, // ADD_A_W - 0U, // ADD_MM - 0U, // ADDi - 0U, // ADDi_MM - 0U, // ADDiu - 0U, // ADDiu_MM - 0U, // ADDu - 0U, // ADDu_MM + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // MEMBARRIER + 0U, // JUMP_TABLE_DEBUG_INFO + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ASSERT_ALIGN + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_CONSTANT_POOL + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_CONSTANT_FOLD_BARRIER + 0U, // G_INTRINSIC_FPTRUNC_ROUND + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_ATOMICRMW_FMAX + 0U, // G_ATOMICRMW_FMIN + 0U, // G_ATOMICRMW_UINC_WRAP + 0U, // G_ATOMICRMW_UDEC_WRAP + 0U, // G_FENCE + 0U, // G_PREFETCH + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INVOKE_REGION_START + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_INTRINSIC_CONVERGENT + 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FEXP10 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FLDEXP + 0U, // G_FFREXP + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_IS_FPCLASS + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_GET_FPENV + 0U, // G_SET_FPENV + 0U, // G_RESET_FPENV + 0U, // G_GET_FPMODE + 0U, // G_SET_FPMODE + 0U, // G_RESET_FPMODE + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STACKSAVE + 0U, // G_STACKRESTORE + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_STRICT_FLDEXP + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_FMAXIMUM + 0U, // G_VECREDUCE_FMINIMUM + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ABSMacro 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKDOWN_NM 0U, // ADJCALLSTACKUP - 4U, // ALIGN - 0U, // ALUIPC - 0U, // AND - 0U, // AND16_MM - 0U, // AND64 - 0U, // ANDI16_MM - 0U, // ANDI_B - 0U, // AND_MM - 0U, // AND_V + 0U, // ADJCALLSTACKUP_NM + 0U, // ALIGN_NM 0U, // AND_V_D_PSEUDO 0U, // AND_V_H_PSEUDO 0U, // AND_V_W_PSEUDO - 1U, // ANDi - 1U, // ANDi64 - 1U, // ANDi_MM - 1U, // APPEND - 0U, // ASUB_S_B - 0U, // ASUB_S_D - 0U, // ASUB_S_H - 0U, // ASUB_S_W - 0U, // ASUB_U_B - 0U, // ASUB_U_D - 0U, // ASUB_U_H - 0U, // ASUB_U_W 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I16_POSTRA 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I32_POSTRA 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I64_POSTRA 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_CMP_SWAP_I8_POSTRA 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I16_POSTRA 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I32_POSTRA 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I64_POSTRA 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_ADD_I8_POSTRA 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I16_POSTRA 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I32_POSTRA 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I64_POSTRA 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_AND_I8_POSTRA + 0U, // ATOMIC_LOAD_MAX_I16 + 0U, // ATOMIC_LOAD_MAX_I16_POSTRA + 0U, // ATOMIC_LOAD_MAX_I32 + 0U, // ATOMIC_LOAD_MAX_I32_POSTRA + 0U, // ATOMIC_LOAD_MAX_I64 + 0U, // ATOMIC_LOAD_MAX_I64_POSTRA + 0U, // ATOMIC_LOAD_MAX_I8 + 0U, // ATOMIC_LOAD_MAX_I8_POSTRA + 0U, // ATOMIC_LOAD_MIN_I16 + 0U, // ATOMIC_LOAD_MIN_I16_POSTRA + 0U, // ATOMIC_LOAD_MIN_I32 + 0U, // ATOMIC_LOAD_MIN_I32_POSTRA + 0U, // ATOMIC_LOAD_MIN_I64 + 0U, // ATOMIC_LOAD_MIN_I64_POSTRA + 0U, // ATOMIC_LOAD_MIN_I8 + 0U, // ATOMIC_LOAD_MIN_I8_POSTRA 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I16_POSTRA 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I32_POSTRA 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I64_POSTRA 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_NAND_I8_POSTRA 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I16_POSTRA 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I32_POSTRA 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I64_POSTRA 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_OR_I8_POSTRA 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I16_POSTRA 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I32_POSTRA 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I64_POSTRA 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_SUB_I8_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I16 + 0U, // ATOMIC_LOAD_UMAX_I16_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I32 + 0U, // ATOMIC_LOAD_UMAX_I32_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I64 + 0U, // ATOMIC_LOAD_UMAX_I64_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I8 + 0U, // ATOMIC_LOAD_UMAX_I8_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I16 + 0U, // ATOMIC_LOAD_UMIN_I16_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I32 + 0U, // ATOMIC_LOAD_UMIN_I32_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I64 + 0U, // ATOMIC_LOAD_UMIN_I64_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I8 + 0U, // ATOMIC_LOAD_UMIN_I8_POSTRA 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I16_POSTRA 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I32_POSTRA 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I64_POSTRA 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_LOAD_XOR_I8_POSTRA 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I16_POSTRA 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I32_POSTRA 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I64_POSTRA 0U, // ATOMIC_SWAP_I8 - 0U, // AUI - 0U, // AUIPC - 0U, // AVER_S_B - 0U, // AVER_S_D - 0U, // AVER_S_H - 0U, // AVER_S_W - 0U, // AVER_U_B - 0U, // AVER_U_D - 0U, // AVER_U_H - 0U, // AVER_U_W - 0U, // AVE_S_B - 0U, // AVE_S_D - 0U, // AVE_S_H - 0U, // AVE_S_W - 0U, // AVE_U_B - 0U, // AVE_U_D - 0U, // AVE_U_H - 0U, // AVE_U_W - 0U, // AddiuRxImmX16 - 0U, // AddiuRxPcImmX16 - 0U, // AddiuRxRxImm16 - 0U, // AddiuRxRxImmX16 - 0U, // AddiuRxRyOffMemX16 - 0U, // AddiuSpImm16 - 0U, // AddiuSpImmX16 - 0U, // AdduRxRyRz16 - 0U, // AndRxRxRy16 + 0U, // ATOMIC_SWAP_I8_POSTRA 0U, // B - 0U, // B16_MM - 0U, // BADDu - 0U, // BAL - 0U, // BALC - 1U, // BALIGN 0U, // BAL_BR - 0U, // BBIT0 - 0U, // BBIT032 - 0U, // BBIT1 - 0U, // BBIT132 - 0U, // BC - 0U, // BC0F - 0U, // BC0FL - 0U, // BC0T - 0U, // BC0TL - 0U, // BC1EQZ - 0U, // BC1F - 0U, // BC1FL - 0U, // BC1F_MM - 0U, // BC1NEZ - 0U, // BC1T - 0U, // BC1TL - 0U, // BC1T_MM - 0U, // BC2EQZ - 0U, // BC2F - 0U, // BC2FL - 0U, // BC2NEZ - 0U, // BC2T - 0U, // BC2TL - 0U, // BC3F - 0U, // BC3FL - 0U, // BC3T - 0U, // BC3TL - 0U, // BCLRI_B - 0U, // BCLRI_D - 0U, // BCLRI_H - 0U, // BCLRI_W - 0U, // BCLR_B - 0U, // BCLR_D - 0U, // BCLR_H - 0U, // BCLR_W - 0U, // BEQ - 0U, // BEQ64 - 0U, // BEQC - 0U, // BEQL - 0U, // BEQZ16_MM - 0U, // BEQZALC - 0U, // BEQZC - 0U, // BEQZC_MM - 0U, // BEQ_MM - 0U, // BGEC - 0U, // BGEUC - 0U, // BGEZ - 0U, // BGEZ64 - 0U, // BGEZAL - 0U, // BGEZALC - 0U, // BGEZALL - 0U, // BGEZALS_MM - 0U, // BGEZAL_MM - 0U, // BGEZC - 0U, // BGEZL - 0U, // BGEZ_MM - 0U, // BGTZ - 0U, // BGTZ64 - 0U, // BGTZALC - 0U, // BGTZC - 0U, // BGTZL - 0U, // BGTZ_MM - 1U, // BINSLI_B - 1U, // BINSLI_D - 1U, // BINSLI_H - 1U, // BINSLI_W - 2U, // BINSL_B - 2U, // BINSL_D - 2U, // BINSL_H - 2U, // BINSL_W - 1U, // BINSRI_B - 1U, // BINSRI_D - 1U, // BINSRI_H - 1U, // BINSRI_W - 2U, // BINSR_B - 2U, // BINSR_D - 2U, // BINSR_H - 2U, // BINSR_W - 0U, // BITREV - 0U, // BITSWAP - 0U, // BLEZ - 0U, // BLEZ64 - 0U, // BLEZALC - 0U, // BLEZC - 0U, // BLEZL - 0U, // BLEZ_MM - 0U, // BLTC - 0U, // BLTUC - 0U, // BLTZ - 0U, // BLTZ64 - 0U, // BLTZAL - 0U, // BLTZALC - 0U, // BLTZALL - 0U, // BLTZALS_MM - 0U, // BLTZAL_MM - 0U, // BLTZC - 0U, // BLTZL - 0U, // BLTZ_MM - 1U, // BMNZI_B - 2U, // BMNZ_V - 1U, // BMZI_B - 2U, // BMZ_V - 0U, // BNE - 0U, // BNE64 - 0U, // BNEC - 0U, // BNEGI_B - 0U, // BNEGI_D - 0U, // BNEGI_H - 0U, // BNEGI_W - 0U, // BNEG_B - 0U, // BNEG_D - 0U, // BNEG_H - 0U, // BNEG_W - 0U, // BNEL - 0U, // BNEZ16_MM - 0U, // BNEZALC - 0U, // BNEZC - 0U, // BNEZC_MM - 0U, // BNE_MM - 0U, // BNVC - 0U, // BNZ_B - 0U, // BNZ_D - 0U, // BNZ_H - 0U, // BNZ_V - 0U, // BNZ_W - 0U, // BOVC - 0U, // BPOSGE32 + 0U, // BAL_BR_MM + 4U, // BEQLImmMacro + 4U, // BGE + 4U, // BGEImmMacro + 4U, // BGEL + 4U, // BGELImmMacro + 4U, // BGEU + 4U, // BGEUImmMacro + 4U, // BGEUL + 4U, // BGEULImmMacro + 4U, // BGT + 4U, // BGTImmMacro + 4U, // BGTL + 4U, // BGTLImmMacro + 4U, // BGTU + 4U, // BGTUImmMacro + 4U, // BGTUL + 4U, // BGTULImmMacro + 4U, // BLE + 4U, // BLEImmMacro + 4U, // BLEL + 4U, // BLELImmMacro + 4U, // BLEU + 4U, // BLEUImmMacro + 4U, // BLEUL + 4U, // BLEULImmMacro + 4U, // BLT + 4U, // BLTImmMacro + 4U, // BLTL + 4U, // BLTLImmMacro + 4U, // BLTU + 4U, // BLTUImmMacro + 4U, // BLTUL + 4U, // BLTULImmMacro + 4U, // BNELImmMacro 0U, // BPOSGE32_PSEUDO - 0U, // BREAK - 0U, // BREAK16_MM - 0U, // BREAK_MM - 1U, // BSELI_B 0U, // BSEL_D_PSEUDO 0U, // BSEL_FD_PSEUDO 0U, // BSEL_FW_PSEUDO 0U, // BSEL_H_PSEUDO - 2U, // BSEL_V 0U, // BSEL_W_PSEUDO - 0U, // BSETI_B - 0U, // BSETI_D - 0U, // BSETI_H - 0U, // BSETI_W - 0U, // BSET_B - 0U, // BSET_D - 0U, // BSET_H - 0U, // BSET_W - 0U, // BZ_B - 0U, // BZ_D - 0U, // BZ_H - 0U, // BZ_V - 0U, // BZ_W + 0U, // B_MM + 0U, // B_MMR6_Pseudo 0U, // B_MM_Pseudo - 0U, // BeqzRxImm16 - 0U, // BeqzRxImmX16 - 0U, // Bimm16 - 0U, // BimmX16 - 0U, // BnezRxImm16 - 0U, // BnezRxImmX16 - 0U, // Break16 - 0U, // Bteqz16 + 4U, // BeqImm + 4U, // BneImm 0U, // BteqzT8CmpX16 0U, // BteqzT8CmpiX16 0U, // BteqzT8SltX16 0U, // BteqzT8SltiX16 0U, // BteqzT8SltiuX16 0U, // BteqzT8SltuX16 - 0U, // BteqzX16 - 0U, // Btnez16 0U, // BtnezT8CmpX16 0U, // BtnezT8CmpiX16 0U, // BtnezT8SltX16 0U, // BtnezT8SltiX16 0U, // BtnezT8SltiuX16 0U, // BtnezT8SltuX16 - 0U, // BtnezX16 0U, // BuildPairF64 0U, // BuildPairF64_64 - 0U, // CACHE - 0U, // CACHE_MM - 0U, // CACHE_R6 - 0U, // CEIL_L_D64 - 0U, // CEIL_L_S - 0U, // CEIL_W_D32 - 0U, // CEIL_W_D64 - 0U, // CEIL_W_MM - 0U, // CEIL_W_S - 0U, // CEIL_W_S_MM - 0U, // CEQI_B - 0U, // CEQI_D - 0U, // CEQI_H - 0U, // CEQI_W - 0U, // CEQ_B - 0U, // CEQ_D - 0U, // CEQ_H - 0U, // CEQ_W - 0U, // CFC1 - 0U, // CFC1_MM - 0U, // CFCMSA - 5U, // CINS - 5U, // CINS32 - 0U, // CLASS_D - 0U, // CLASS_S - 0U, // CLEI_S_B - 0U, // CLEI_S_D - 0U, // CLEI_S_H - 0U, // CLEI_S_W - 0U, // CLEI_U_B - 0U, // CLEI_U_D - 0U, // CLEI_U_H - 0U, // CLEI_U_W - 0U, // CLE_S_B - 0U, // CLE_S_D - 0U, // CLE_S_H - 0U, // CLE_S_W - 0U, // CLE_U_B - 0U, // CLE_U_D - 0U, // CLE_U_H - 0U, // CLE_U_W - 0U, // CLO - 0U, // CLO_MM - 0U, // CLO_R6 - 0U, // CLTI_S_B - 0U, // CLTI_S_D - 0U, // CLTI_S_H - 0U, // CLTI_S_W - 0U, // CLTI_U_B - 0U, // CLTI_U_D - 0U, // CLTI_U_H - 0U, // CLTI_U_W - 0U, // CLT_S_B - 0U, // CLT_S_D - 0U, // CLT_S_H - 0U, // CLT_S_W - 0U, // CLT_U_B - 0U, // CLT_U_D - 0U, // CLT_U_H - 0U, // CLT_U_W - 0U, // CLZ - 0U, // CLZ_MM - 0U, // CLZ_R6 - 0U, // CMPGDU_EQ_QB - 0U, // CMPGDU_LE_QB - 0U, // CMPGDU_LT_QB - 0U, // CMPGU_EQ_QB - 0U, // CMPGU_LE_QB - 0U, // CMPGU_LT_QB - 0U, // CMPU_EQ_QB - 0U, // CMPU_LE_QB - 0U, // CMPU_LT_QB - 0U, // CMP_EQ_D - 0U, // CMP_EQ_PH - 0U, // CMP_EQ_S - 0U, // CMP_F_D - 0U, // CMP_F_S - 0U, // CMP_LE_D - 0U, // CMP_LE_PH - 0U, // CMP_LE_S - 0U, // CMP_LT_D - 0U, // CMP_LT_PH - 0U, // CMP_LT_S - 0U, // CMP_SAF_D - 0U, // CMP_SAF_S - 0U, // CMP_SEQ_D - 0U, // CMP_SEQ_S - 0U, // CMP_SLE_D - 0U, // CMP_SLE_S - 0U, // CMP_SLT_D - 0U, // CMP_SLT_S - 0U, // CMP_SUEQ_D - 0U, // CMP_SUEQ_S - 0U, // CMP_SULE_D - 0U, // CMP_SULE_S - 0U, // CMP_SULT_D - 0U, // CMP_SULT_S - 0U, // CMP_SUN_D - 0U, // CMP_SUN_S - 0U, // CMP_UEQ_D - 0U, // CMP_UEQ_S - 0U, // CMP_ULE_D - 0U, // CMP_ULE_S - 0U, // CMP_ULT_D - 0U, // CMP_ULT_S - 0U, // CMP_UN_D - 0U, // CMP_UN_S + 0U, // CFTC1 0U, // CONSTPOOL_ENTRY 0U, // COPY_FD_PSEUDO 0U, // COPY_FW_PSEUDO - 8U, // COPY_S_B - 8U, // COPY_S_D - 8U, // COPY_S_H - 8U, // COPY_S_W - 8U, // COPY_U_B - 8U, // COPY_U_D - 8U, // COPY_U_H - 8U, // COPY_U_W - 0U, // CTC1 - 0U, // CTC1_MM - 0U, // CTCMSA - 0U, // CVT_D32_S - 0U, // CVT_D32_W - 0U, // CVT_D32_W_MM - 0U, // CVT_D64_L - 0U, // CVT_D64_S - 0U, // CVT_D64_W - 0U, // CVT_D_S_MM - 0U, // CVT_L_D64 - 0U, // CVT_L_D64_MM - 0U, // CVT_L_S - 0U, // CVT_L_S_MM - 0U, // CVT_S_D32 - 0U, // CVT_S_D32_MM - 0U, // CVT_S_D64 - 0U, // CVT_S_L - 0U, // CVT_S_W - 0U, // CVT_S_W_MM - 0U, // CVT_W_D32 - 0U, // CVT_W_D64 - 0U, // CVT_W_MM - 0U, // CVT_W_S - 0U, // CVT_W_S_MM - 0U, // C_EQ_D32 - 0U, // C_EQ_D64 - 0U, // C_EQ_S - 0U, // C_F_D32 - 0U, // C_F_D64 - 0U, // C_F_S - 0U, // C_LE_D32 - 0U, // C_LE_D64 - 0U, // C_LE_S - 0U, // C_LT_D32 - 0U, // C_LT_D64 - 0U, // C_LT_S - 0U, // C_NGE_D32 - 0U, // C_NGE_D64 - 0U, // C_NGE_S - 0U, // C_NGLE_D32 - 0U, // C_NGLE_D64 - 0U, // C_NGLE_S - 0U, // C_NGL_D32 - 0U, // C_NGL_D64 - 0U, // C_NGL_S - 0U, // C_NGT_D32 - 0U, // C_NGT_D64 - 0U, // C_NGT_S - 0U, // C_OLE_D32 - 0U, // C_OLE_D64 - 0U, // C_OLE_S - 0U, // C_OLT_D32 - 0U, // C_OLT_D64 - 0U, // C_OLT_S - 0U, // C_SEQ_D32 - 0U, // C_SEQ_D64 - 0U, // C_SEQ_S - 0U, // C_SF_D32 - 0U, // C_SF_D64 - 0U, // C_SF_S - 0U, // C_UEQ_D32 - 0U, // C_UEQ_D64 - 0U, // C_UEQ_S - 0U, // C_ULE_D32 - 0U, // C_ULE_D64 - 0U, // C_ULE_S - 0U, // C_ULT_D32 - 0U, // C_ULT_D64 - 0U, // C_ULT_S - 0U, // C_UN_D32 - 0U, // C_UN_D64 - 0U, // C_UN_S - 0U, // CmpRxRy16 - 0U, // CmpiRxImm16 - 0U, // CmpiRxImmX16 + 0U, // CTTC1 0U, // Constant32 - 0U, // DADD - 0U, // DADDi - 0U, // DADDiu - 0U, // DADDu - 0U, // DAHI - 4U, // DALIGN - 0U, // DATI - 0U, // DAUI - 0U, // DBITSWAP - 0U, // DCLO - 0U, // DCLO_R6 - 0U, // DCLZ - 0U, // DCLZ_R6 - 0U, // DDIV - 0U, // DDIVU - 0U, // DERET - 0U, // DERET_MM - 21U, // DEXT - 21U, // DEXTM - 21U, // DEXTU - 0U, // DI - 21U, // DINS - 21U, // DINSM - 21U, // DINSU - 0U, // DIV - 0U, // DIVU - 0U, // DIV_S_B - 0U, // DIV_S_D - 0U, // DIV_S_H - 0U, // DIV_S_W - 0U, // DIV_U_B - 0U, // DIV_U_D - 0U, // DIV_U_H - 0U, // DIV_U_W - 0U, // DI_MM - 4U, // DLSA - 4U, // DLSA_R6 - 1U, // DMFC0 - 0U, // DMFC1 - 1U, // DMFC2 - 0U, // DMOD - 0U, // DMODU - 1U, // DMTC0 - 0U, // DMTC1 - 1U, // DMTC2 - 0U, // DMUH - 0U, // DMUHU - 0U, // DMUL - 0U, // DMULT - 0U, // DMULTu - 0U, // DMULU - 0U, // DMUL_R6 - 0U, // DOTP_S_D - 0U, // DOTP_S_H - 0U, // DOTP_S_W - 0U, // DOTP_U_D - 0U, // DOTP_U_H - 0U, // DOTP_U_W - 2U, // DPADD_S_D - 2U, // DPADD_S_H - 2U, // DPADD_S_W - 2U, // DPADD_U_D - 2U, // DPADD_U_H - 2U, // DPADD_U_W - 0U, // DPAQX_SA_W_PH - 0U, // DPAQX_S_W_PH - 0U, // DPAQ_SA_L_W - 0U, // DPAQ_S_W_PH - 0U, // DPAU_H_QBL - 0U, // DPAU_H_QBR - 0U, // DPAX_W_PH - 0U, // DPA_W_PH - 0U, // DPOP - 0U, // DPSQX_SA_W_PH - 0U, // DPSQX_S_W_PH - 0U, // DPSQ_SA_L_W - 0U, // DPSQ_S_W_PH - 2U, // DPSUB_S_D - 2U, // DPSUB_S_H - 2U, // DPSUB_S_W - 2U, // DPSUB_U_D - 2U, // DPSUB_U_H - 2U, // DPSUB_U_W - 0U, // DPSU_H_QBL - 0U, // DPSU_H_QBR - 0U, // DPSX_W_PH - 0U, // DPS_W_PH - 1U, // DROTR - 1U, // DROTR32 - 0U, // DROTRV - 0U, // DSBH - 0U, // DSDIV - 0U, // DSHD - 1U, // DSLL - 1U, // DSLL32 - 0U, // DSLL64_32 - 0U, // DSLLV - 1U, // DSRA - 1U, // DSRA32 - 0U, // DSRAV - 1U, // DSRL - 1U, // DSRL32 - 0U, // DSRLV - 0U, // DSUB - 0U, // DSUBu - 0U, // DUDIV - 0U, // DivRxRy16 - 0U, // DivuRxRy16 - 0U, // EHB - 0U, // EHB_MM - 0U, // EI - 0U, // EI_MM - 0U, // ERET - 0U, // ERET_MM - 21U, // EXT - 1U, // EXTP - 1U, // EXTPDP - 0U, // EXTPDPV - 0U, // EXTPV - 0U, // EXTRV_RS_W - 0U, // EXTRV_R_W - 0U, // EXTRV_S_H - 0U, // EXTRV_W - 1U, // EXTR_RS_W - 1U, // EXTR_R_W - 1U, // EXTR_S_H - 1U, // EXTR_W - 5U, // EXTS - 5U, // EXTS32 - 21U, // EXT_MM + 128U, // DMULImmMacro + 128U, // DMULMacro + 128U, // DMULOMacro + 128U, // DMULOUMacro + 128U, // DROL + 128U, // DROLImm + 128U, // DROR + 128U, // DRORImm + 128U, // DSDivIMacro + 128U, // DSDivMacro + 128U, // DSRemIMacro + 128U, // DSRemMacro + 128U, // DUDivIMacro + 128U, // DUDivMacro + 128U, // DURemIMacro + 128U, // DURemMacro + 0U, // ERet 0U, // ExtractElementF64 0U, // ExtractElementF64_64 0U, // FABS_D - 0U, // FABS_D32 - 0U, // FABS_D64 - 0U, // FABS_MM - 0U, // FABS_S - 0U, // FABS_S_MM 0U, // FABS_W - 0U, // FADD_D - 0U, // FADD_D32 - 0U, // FADD_D64 - 0U, // FADD_MM - 0U, // FADD_S - 0U, // FADD_S_MM - 0U, // FADD_W - 0U, // FCAF_D - 0U, // FCAF_W - 0U, // FCEQ_D - 0U, // FCEQ_W - 0U, // FCLASS_D - 0U, // FCLASS_W - 0U, // FCLE_D - 0U, // FCLE_W - 0U, // FCLT_D - 0U, // FCLT_W - 0U, // FCMP_D32 - 0U, // FCMP_D32_MM - 0U, // FCMP_D64 - 0U, // FCMP_S32 - 0U, // FCMP_S32_MM - 0U, // FCNE_D - 0U, // FCNE_W - 0U, // FCOR_D - 0U, // FCOR_W - 0U, // FCUEQ_D - 0U, // FCUEQ_W - 0U, // FCULE_D - 0U, // FCULE_W - 0U, // FCULT_D - 0U, // FCULT_W - 0U, // FCUNE_D - 0U, // FCUNE_W - 0U, // FCUN_D - 0U, // FCUN_W - 0U, // FDIV_D - 0U, // FDIV_D32 - 0U, // FDIV_D64 - 0U, // FDIV_MM - 0U, // FDIV_S - 0U, // FDIV_S_MM - 0U, // FDIV_W - 0U, // FEXDO_H - 0U, // FEXDO_W - 0U, // FEXP2_D 0U, // FEXP2_D_1_PSEUDO - 0U, // FEXP2_W 0U, // FEXP2_W_1_PSEUDO - 0U, // FEXUPL_D - 0U, // FEXUPL_W - 0U, // FEXUPR_D - 0U, // FEXUPR_W - 0U, // FFINT_S_D - 0U, // FFINT_S_W - 0U, // FFINT_U_D - 0U, // FFINT_U_W - 0U, // FFQL_D - 0U, // FFQL_W - 0U, // FFQR_D - 0U, // FFQR_W - 0U, // FILL_B - 0U, // FILL_D 0U, // FILL_FD_PSEUDO 0U, // FILL_FW_PSEUDO - 0U, // FILL_H - 0U, // FILL_W - 0U, // FLOG2_D - 0U, // FLOG2_W - 0U, // FLOOR_L_D64 - 0U, // FLOOR_L_S - 0U, // FLOOR_W_D32 - 0U, // FLOOR_W_D64 - 0U, // FLOOR_W_MM - 0U, // FLOOR_W_S - 0U, // FLOOR_W_S_MM - 2U, // FMADD_D - 2U, // FMADD_W - 0U, // FMAX_A_D - 0U, // FMAX_A_W - 0U, // FMAX_D - 0U, // FMAX_W - 0U, // FMIN_A_D - 0U, // FMIN_A_W - 0U, // FMIN_D - 0U, // FMIN_W - 0U, // FMOV_D32 - 0U, // FMOV_D32_MM - 0U, // FMOV_D64 - 0U, // FMOV_S - 0U, // FMOV_S_MM - 2U, // FMSUB_D - 2U, // FMSUB_W - 0U, // FMUL_D - 0U, // FMUL_D32 - 0U, // FMUL_D64 - 0U, // FMUL_MM - 0U, // FMUL_S - 0U, // FMUL_S_MM - 0U, // FMUL_W - 0U, // FNEG_D32 - 0U, // FNEG_D64 - 0U, // FNEG_MM - 0U, // FNEG_S - 0U, // FNEG_S_MM - 0U, // FRCP_D - 0U, // FRCP_W - 0U, // FRINT_D - 0U, // FRINT_W - 0U, // FRSQRT_D - 0U, // FRSQRT_W - 0U, // FSAF_D - 0U, // FSAF_W - 0U, // FSEQ_D - 0U, // FSEQ_W - 0U, // FSLE_D - 0U, // FSLE_W - 0U, // FSLT_D - 0U, // FSLT_W - 0U, // FSNE_D - 0U, // FSNE_W - 0U, // FSOR_D - 0U, // FSOR_W - 0U, // FSQRT_D - 0U, // FSQRT_D32 - 0U, // FSQRT_D64 - 0U, // FSQRT_MM - 0U, // FSQRT_S - 0U, // FSQRT_S_MM - 0U, // FSQRT_W - 0U, // FSUB_D - 0U, // FSUB_D32 - 0U, // FSUB_D64 - 0U, // FSUB_MM - 0U, // FSUB_S - 0U, // FSUB_S_MM - 0U, // FSUB_W - 0U, // FSUEQ_D - 0U, // FSUEQ_W - 0U, // FSULE_D - 0U, // FSULE_W - 0U, // FSULT_D - 0U, // FSULT_W - 0U, // FSUNE_D - 0U, // FSUNE_W - 0U, // FSUN_D - 0U, // FSUN_W - 0U, // FTINT_S_D - 0U, // FTINT_S_W - 0U, // FTINT_U_D - 0U, // FTINT_U_W - 0U, // FTQ_H - 0U, // FTQ_W - 0U, // FTRUNC_S_D - 0U, // FTRUNC_S_W - 0U, // FTRUNC_U_D - 0U, // FTRUNC_U_W 0U, // GotPrologue16 - 0U, // HADD_S_D - 0U, // HADD_S_H - 0U, // HADD_S_W - 0U, // HADD_U_D - 0U, // HADD_U_H - 0U, // HADD_U_W - 0U, // HSUB_S_D - 0U, // HSUB_S_H - 0U, // HSUB_S_W - 0U, // HSUB_U_D - 0U, // HSUB_U_H - 0U, // HSUB_U_W - 0U, // ILVEV_B - 0U, // ILVEV_D - 0U, // ILVEV_H - 0U, // ILVEV_W - 0U, // ILVL_B - 0U, // ILVL_D - 0U, // ILVL_H - 0U, // ILVL_W - 0U, // ILVOD_B - 0U, // ILVOD_D - 0U, // ILVOD_H - 0U, // ILVOD_W - 0U, // ILVR_B - 0U, // ILVR_D - 0U, // ILVR_H - 0U, // ILVR_W - 21U, // INS - 0U, // INSERT_B + 0U, // INSERT_B_VIDX64_PSEUDO 0U, // INSERT_B_VIDX_PSEUDO - 0U, // INSERT_D + 0U, // INSERT_D_VIDX64_PSEUDO 0U, // INSERT_D_VIDX_PSEUDO 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX64_PSEUDO 0U, // INSERT_FD_VIDX_PSEUDO 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX64_PSEUDO 0U, // INSERT_FW_VIDX_PSEUDO - 0U, // INSERT_H + 0U, // INSERT_H_VIDX64_PSEUDO 0U, // INSERT_H_VIDX_PSEUDO - 0U, // INSERT_W + 0U, // INSERT_W_VIDX64_PSEUDO 0U, // INSERT_W_VIDX_PSEUDO - 0U, // INSV - 0U, // INSVE_B - 0U, // INSVE_D - 0U, // INSVE_H - 0U, // INSVE_W - 21U, // INS_MM - 0U, // J - 0U, // JAL - 0U, // JALR - 0U, // JALR16_MM - 0U, // JALR64 0U, // JALR64Pseudo + 0U, // JALRCPseudo + 0U, // JALRHB64Pseudo + 0U, // JALRHBPseudo 0U, // JALRPseudo - 0U, // JALRS16_MM - 0U, // JALRS_MM - 0U, // JALR_HB - 0U, // JALR_MM - 0U, // JALS_MM - 0U, // JALX - 0U, // JALX_MM - 0U, // JAL_MM - 0U, // JIALC - 0U, // JIC - 0U, // JR - 0U, // JR16_MM - 0U, // JR64 - 0U, // JRADDIUSP - 0U, // JRC16_MM - 0U, // JR_HB - 0U, // JR_HB_R6 - 0U, // JR_MM - 0U, // J_MM - 0U, // Jal16 - 0U, // JalB16 + 0U, // JAL_MMR6 0U, // JalOneReg 0U, // JalTwoReg - 0U, // JrRa16 - 0U, // JrcRa16 - 0U, // JrcRx16 - 0U, // JumpLinkReg16 - 0U, // LB - 0U, // LB64 - 0U, // LBU16_MM - 0U, // LBUX - 0U, // LB_MM - 0U, // LBu - 0U, // LBu64 - 0U, // LBu_MM - 0U, // LD - 0U, // LDC1 - 0U, // LDC164 - 0U, // LDC1_MM - 0U, // LDC2 - 0U, // LDC2_R6 - 0U, // LDC3 - 0U, // LDI_B - 0U, // LDI_D - 0U, // LDI_H - 0U, // LDI_W - 0U, // LDL - 0U, // LDPC - 0U, // LDR - 0U, // LDXC1 - 0U, // LDXC164 - 0U, // LD_B - 0U, // LD_D - 0U, // LD_H - 0U, // LD_W - 0U, // LEA_ADDiu - 0U, // LEA_ADDiu64 - 0U, // LEA_ADDiu_MM - 0U, // LH - 0U, // LH64 - 0U, // LHU16_MM - 0U, // LHX - 0U, // LH_MM - 0U, // LHu - 0U, // LHu64 - 0U, // LHu_MM - 0U, // LI16_MM - 0U, // LL - 0U, // LLD - 0U, // LLD_R6 - 0U, // LL_MM - 0U, // LL_R6 + 0U, // LDMacro + 0U, // LDR_D + 0U, // LDR_W + 0U, // LD_F16 0U, // LOAD_ACC128 0U, // LOAD_ACC64 0U, // LOAD_ACC64DSP 0U, // LOAD_CCOND_DSP 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_ADDiu2Op 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_DADDiu2Op 0U, // LONG_BRANCH_LUi - 4U, // LSA - 4U, // LSA_R6 - 0U, // LUXC1 - 0U, // LUXC164 - 0U, // LUXC1_MM - 0U, // LUi - 0U, // LUi64 - 0U, // LUi_MM - 0U, // LW - 0U, // LW16_MM - 0U, // LW64 - 0U, // LWC1 - 0U, // LWC1_MM - 0U, // LWC2 - 0U, // LWC2_R6 - 0U, // LWC3 - 0U, // LWGP_MM - 0U, // LWL - 0U, // LWL64 - 0U, // LWL_MM - 0U, // LWM16_MM - 0U, // LWM32_MM + 0U, // LONG_BRANCH_LUi2Op + 0U, // LONG_BRANCH_LUi2Op_64 0U, // LWM_MM - 0U, // LWPC - 0U, // LWP_MM - 0U, // LWR - 0U, // LWR64 - 0U, // LWR_MM - 0U, // LWSP_MM - 0U, // LWUPC - 0U, // LWU_MM - 0U, // LWX - 0U, // LWXC1 - 0U, // LWXC1_MM - 0U, // LWXS_MM - 0U, // LW_MM - 0U, // LWu - 0U, // LbRxRyOffMemX16 - 0U, // LbuRxRyOffMemX16 - 0U, // LhRxRyOffMemX16 - 0U, // LhuRxRyOffMemX16 - 0U, // LiRxImm16 - 0U, // LiRxImmAlignX16 - 0U, // LiRxImmX16 - 0U, // LoadAddr32Imm - 0U, // LoadAddr32Reg - 0U, // LoadImm32Reg - 0U, // LoadImm64Reg + 0U, // LoadAddrImm32 + 0U, // LoadAddrImm64 + 0U, // LoadAddrReg32 + 0U, // LoadAddrReg64 + 0U, // LoadImm32 + 0U, // LoadImm64 + 0U, // LoadImmDoubleFGR + 0U, // LoadImmDoubleFGR_32 + 0U, // LoadImmDoubleGPR + 0U, // LoadImmSingleFGR + 0U, // LoadImmSingleGPR + 0U, // LoadJumpTableOffset 0U, // LwConstant32 - 0U, // LwRxPcTcp16 - 0U, // LwRxPcTcpX16 - 0U, // LwRxRyOffMemX16 - 0U, // LwRxSpImmX16 - 0U, // MADD - 2U, // MADDF_D - 2U, // MADDF_S - 2U, // MADDR_Q_H - 2U, // MADDR_Q_W - 0U, // MADDU - 0U, // MADDU_DSP - 0U, // MADDU_MM - 2U, // MADDV_B - 2U, // MADDV_D - 2U, // MADDV_H - 2U, // MADDV_W - 20U, // MADD_D32 - 20U, // MADD_D32_MM - 20U, // MADD_D64 - 0U, // MADD_DSP - 0U, // MADD_MM - 2U, // MADD_Q_H - 2U, // MADD_Q_W - 20U, // MADD_S - 20U, // MADD_S_MM - 0U, // MAQ_SA_W_PHL - 0U, // MAQ_SA_W_PHR - 0U, // MAQ_S_W_PHL - 0U, // MAQ_S_W_PHR - 0U, // MAXA_D - 0U, // MAXA_S - 0U, // MAXI_S_B - 0U, // MAXI_S_D - 0U, // MAXI_S_H - 0U, // MAXI_S_W - 0U, // MAXI_U_B - 0U, // MAXI_U_D - 0U, // MAXI_U_H - 0U, // MAXI_U_W - 0U, // MAX_A_B - 0U, // MAX_A_D - 0U, // MAX_A_H - 0U, // MAX_A_W - 0U, // MAX_D - 0U, // MAX_S - 0U, // MAX_S_B - 0U, // MAX_S_D - 0U, // MAX_S_H - 0U, // MAX_S_W - 0U, // MAX_U_B - 0U, // MAX_U_D - 0U, // MAX_U_H - 0U, // MAX_U_W - 1U, // MFC0 - 0U, // MFC1 - 0U, // MFC1_MM - 1U, // MFC2 - 0U, // MFHC1_D32 - 0U, // MFHC1_D64 - 0U, // MFHC1_MM - 0U, // MFHI - 0U, // MFHI16_MM - 0U, // MFHI64 - 0U, // MFHI_DSP - 0U, // MFHI_MM - 0U, // MFLO - 0U, // MFLO16_MM - 0U, // MFLO64 - 0U, // MFLO_DSP - 0U, // MFLO_MM - 0U, // MINA_D - 0U, // MINA_S - 0U, // MINI_S_B - 0U, // MINI_S_D - 0U, // MINI_S_H - 0U, // MINI_S_W - 0U, // MINI_U_B - 0U, // MINI_U_D - 0U, // MINI_U_H - 0U, // MINI_U_W - 0U, // MIN_A_B - 0U, // MIN_A_D - 0U, // MIN_A_H - 0U, // MIN_A_W - 0U, // MIN_D - 0U, // MIN_S - 0U, // MIN_S_B - 0U, // MIN_S_D - 0U, // MIN_S_H - 0U, // MIN_S_W - 0U, // MIN_U_B - 0U, // MIN_U_D - 0U, // MIN_U_H - 0U, // MIN_U_W + 0U, // MFTACX + 0U, // MFTACX_NM + 136U, // MFTC0 + 136U, // MFTC0_NM + 0U, // MFTC1 + 0U, // MFTDSP + 0U, // MFTDSP_NM + 0U, // MFTGPR + 0U, // MFTGPR_NM + 0U, // MFTHC1 + 0U, // MFTHI + 0U, // MFTHI_NM + 0U, // MFTLO + 0U, // MFTLO_NM 0U, // MIPSeh_return32 0U, // MIPSeh_return64 - 0U, // MOD - 0U, // MODSUB - 0U, // MODU - 0U, // MOD_S_B - 0U, // MOD_S_D - 0U, // MOD_S_H - 0U, // MOD_S_W - 0U, // MOD_U_B - 0U, // MOD_U_D - 0U, // MOD_U_H - 0U, // MOD_U_W - 0U, // MOVE16_MM - 0U, // MOVEP_MM - 0U, // MOVE_V - 0U, // MOVF_D32 - 0U, // MOVF_D32_MM - 0U, // MOVF_D64 - 0U, // MOVF_I - 0U, // MOVF_I64 - 0U, // MOVF_I_MM - 0U, // MOVF_S - 0U, // MOVF_S_MM - 0U, // MOVN_I64_D64 - 0U, // MOVN_I64_I - 0U, // MOVN_I64_I64 - 0U, // MOVN_I64_S - 0U, // MOVN_I_D32 - 0U, // MOVN_I_D32_MM - 0U, // MOVN_I_D64 - 0U, // MOVN_I_I - 0U, // MOVN_I_I64 - 0U, // MOVN_I_MM - 0U, // MOVN_I_S - 0U, // MOVN_I_S_MM - 0U, // MOVT_D32 - 0U, // MOVT_D32_MM - 0U, // MOVT_D64 - 0U, // MOVT_I - 0U, // MOVT_I64 - 0U, // MOVT_I_MM - 0U, // MOVT_S - 0U, // MOVT_S_MM - 0U, // MOVZ_I64_D64 - 0U, // MOVZ_I64_I - 0U, // MOVZ_I64_I64 - 0U, // MOVZ_I64_S - 0U, // MOVZ_I_D32 - 0U, // MOVZ_I_D32_MM - 0U, // MOVZ_I_D64 - 0U, // MOVZ_I_I - 0U, // MOVZ_I_I64 - 0U, // MOVZ_I_MM - 0U, // MOVZ_I_S - 0U, // MOVZ_I_S_MM - 0U, // MSUB - 2U, // MSUBF_D - 2U, // MSUBF_S - 2U, // MSUBR_Q_H - 2U, // MSUBR_Q_W - 0U, // MSUBU - 0U, // MSUBU_DSP - 0U, // MSUBU_MM - 2U, // MSUBV_B - 2U, // MSUBV_D - 2U, // MSUBV_H - 2U, // MSUBV_W - 20U, // MSUB_D32 - 20U, // MSUB_D32_MM - 20U, // MSUB_D64 - 0U, // MSUB_DSP - 0U, // MSUB_MM - 2U, // MSUB_Q_H - 2U, // MSUB_Q_W - 20U, // MSUB_S - 20U, // MSUB_S_MM - 1U, // MTC0 - 0U, // MTC1 - 0U, // MTC1_MM - 1U, // MTC2 - 0U, // MTHC1_D32 - 0U, // MTHC1_D64 - 0U, // MTHC1_MM - 0U, // MTHI - 0U, // MTHI64 - 0U, // MTHI_DSP - 0U, // MTHI_MM - 0U, // MTHLIP - 0U, // MTLO - 0U, // MTLO64 - 0U, // MTLO_DSP - 0U, // MTLO_MM - 0U, // MTM0 - 0U, // MTM1 - 0U, // MTM2 - 0U, // MTP0 - 0U, // MTP1 - 0U, // MTP2 - 0U, // MUH - 0U, // MUHU - 0U, // MUL - 0U, // MULEQ_S_W_PHL - 0U, // MULEQ_S_W_PHR - 0U, // MULEU_S_PH_QBL - 0U, // MULEU_S_PH_QBR - 0U, // MULQ_RS_PH - 0U, // MULQ_RS_W - 0U, // MULQ_S_PH - 0U, // MULQ_S_W - 0U, // MULR_Q_H - 0U, // MULR_Q_W - 0U, // MULSAQ_S_W_PH - 0U, // MULSA_W_PH - 0U, // MULT - 0U, // MULTU_DSP - 0U, // MULT_DSP - 0U, // MULT_MM - 0U, // MULTu - 0U, // MULTu_MM - 0U, // MULU - 0U, // MULV_B - 0U, // MULV_D - 0U, // MULV_H - 0U, // MULV_W - 0U, // MUL_MM - 0U, // MUL_PH - 0U, // MUL_Q_H - 0U, // MUL_Q_W - 0U, // MUL_R6 - 0U, // MUL_S_PH - 0U, // Mfhi16 - 0U, // Mflo16 - 0U, // Move32R16 - 0U, // MoveR3216 + 0U, // MSA_FP_EXTEND_D_PSEUDO + 0U, // MSA_FP_EXTEND_W_PSEUDO + 0U, // MSA_FP_ROUND_D_PSEUDO + 0U, // MSA_FP_ROUND_W_PSEUDO + 0U, // MTTACX + 0U, // MTTACX_NM + 0U, // MTTC0 + 0U, // MTTC0_NM + 0U, // MTTC1 + 0U, // MTTDSP + 0U, // MTTDSP_NM + 0U, // MTTGPR + 0U, // MTTGPR_NM + 0U, // MTTHC1 + 0U, // MTTHI + 0U, // MTTHI_NM + 0U, // MTTLO + 0U, // MTTLO_NM + 128U, // MULImmMacro + 128U, // MULOMacro + 128U, // MULOUMacro + 0U, // MUSTTAILCALLREG_NM + 0U, // MUSTTAILCALL_NM 0U, // MultRxRy16 0U, // MultRxRyRz16 0U, // MultuRxRy16 0U, // MultuRxRyRz16 - 0U, // NLOC_B - 0U, // NLOC_D - 0U, // NLOC_H - 0U, // NLOC_W - 0U, // NLZC_B - 0U, // NLZC_D - 0U, // NLZC_H - 0U, // NLZC_W - 20U, // NMADD_D32 - 20U, // NMADD_D32_MM - 20U, // NMADD_D64 - 20U, // NMADD_S - 20U, // NMADD_S_MM - 20U, // NMSUB_D32 - 20U, // NMSUB_D32_MM - 20U, // NMSUB_D64 - 20U, // NMSUB_S - 20U, // NMSUB_S_MM 0U, // NOP - 0U, // NOR - 0U, // NOR64 - 0U, // NORI_B - 0U, // NOR_MM - 0U, // NOR_V + 128U, // NORImm + 128U, // NORImm64 0U, // NOR_V_D_PSEUDO 0U, // NOR_V_H_PSEUDO 0U, // NOR_V_W_PSEUDO - 0U, // NOT16_MM - 0U, // NegRxRy16 - 0U, // NotRxRy16 - 0U, // OR - 0U, // OR16_MM - 0U, // OR64 - 0U, // ORI_B - 0U, // OR_MM - 0U, // OR_V 0U, // OR_V_D_PSEUDO 0U, // OR_V_H_PSEUDO 0U, // OR_V_W_PSEUDO - 1U, // ORi - 1U, // ORi64 - 1U, // ORi_MM - 0U, // OrRxRxRy16 - 0U, // PACKRL_PH - 0U, // PAUSE - 0U, // PAUSE_MM - 0U, // PCKEV_B - 0U, // PCKEV_D - 0U, // PCKEV_H - 0U, // PCKEV_W - 0U, // PCKOD_B - 0U, // PCKOD_D - 0U, // PCKOD_H - 0U, // PCKOD_W - 0U, // PCNT_B - 0U, // PCNT_D - 0U, // PCNT_H - 0U, // PCNT_W - 0U, // PICK_PH - 0U, // PICK_QB - 0U, // POP - 0U, // PRECEQU_PH_QBL - 0U, // PRECEQU_PH_QBLA - 0U, // PRECEQU_PH_QBR - 0U, // PRECEQU_PH_QBRA - 0U, // PRECEQ_W_PHL - 0U, // PRECEQ_W_PHR - 0U, // PRECEU_PH_QBL - 0U, // PRECEU_PH_QBLA - 0U, // PRECEU_PH_QBR - 0U, // PRECEU_PH_QBRA - 0U, // PRECRQU_S_QB_PH - 0U, // PRECRQ_PH_W - 0U, // PRECRQ_QB_PH - 0U, // PRECRQ_RS_PH_W - 0U, // PRECR_QB_PH - 1U, // PRECR_SRA_PH_W - 1U, // PRECR_SRA_R_PH_W - 0U, // PREF - 0U, // PREF_MM - 0U, // PREF_R6 - 1U, // PREPEND + 12U, // PseudoADDIU_NM + 16U, // PseudoANDI_NM 0U, // PseudoCMPU_EQ_QB 0U, // PseudoCMPU_LE_QB 0U, // PseudoCMPU_LT_QB @@ -3155,25 +5039,48 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) 0U, // PseudoDMULTu 0U, // PseudoDSDIV 0U, // PseudoDUDIV + 0U, // PseudoD_SELECT_I + 0U, // PseudoD_SELECT_I64 0U, // PseudoIndirectBranch 0U, // PseudoIndirectBranch64 + 0U, // PseudoIndirectBranch64R6 + 0U, // PseudoIndirectBranchNM + 0U, // PseudoIndirectBranchR6 + 0U, // PseudoIndirectBranch_MM + 0U, // PseudoIndirectBranch_MMR6 + 0U, // PseudoIndirectHazardBranch + 0U, // PseudoIndirectHazardBranch64 + 0U, // PseudoIndrectHazardBranch64R6 + 0U, // PseudoIndrectHazardBranchR6 + 0U, // PseudoLA_NM + 0U, // PseudoLI_NM 0U, // PseudoMADD 0U, // PseudoMADDU + 0U, // PseudoMADDU_MM + 0U, // PseudoMADD_MM 0U, // PseudoMFHI 0U, // PseudoMFHI64 + 0U, // PseudoMFHI_MM 0U, // PseudoMFLO 0U, // PseudoMFLO64 + 0U, // PseudoMFLO_MM 0U, // PseudoMSUB 0U, // PseudoMSUBU + 0U, // PseudoMSUBU_MM + 0U, // PseudoMSUB_MM 0U, // PseudoMTLOHI 0U, // PseudoMTLOHI64 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMTLOHI_MM 0U, // PseudoMULT + 0U, // PseudoMULT_MM 0U, // PseudoMULTu + 0U, // PseudoMULTu_MM 0U, // PseudoPICK_PH 0U, // PseudoPICK_QB 0U, // PseudoReturn 0U, // PseudoReturn64 + 0U, // PseudoReturnNM 0U, // PseudoSDIV 0U, // PseudoSELECTFP_F_D32 0U, // PseudoSELECTFP_F_D64 @@ -3190,299 +5097,66 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) 0U, // PseudoSELECT_I 0U, // PseudoSELECT_I64 0U, // PseudoSELECT_S + 128U, // PseudoSUBU_NM + 128U, // PseudoTRUNC_W_D + 128U, // PseudoTRUNC_W_D32 + 128U, // PseudoTRUNC_W_S 0U, // PseudoUDIV - 0U, // RADDU_W_QB - 0U, // RDDSP - 0U, // RDHWR - 0U, // RDHWR64 - 0U, // RDHWR_MM - 0U, // REPLV_PH - 0U, // REPLV_QB - 0U, // REPL_PH - 0U, // REPL_QB - 0U, // RINT_D - 0U, // RINT_S - 1U, // ROTR - 0U, // ROTRV - 0U, // ROTRV_MM - 1U, // ROTR_MM - 0U, // ROUND_L_D64 - 0U, // ROUND_L_S - 0U, // ROUND_W_D32 - 0U, // ROUND_W_D64 - 0U, // ROUND_W_MM - 0U, // ROUND_W_S - 0U, // ROUND_W_S_MM - 0U, // Restore16 - 0U, // RestoreX16 + 128U, // ROL + 128U, // ROLImm + 128U, // ROR + 128U, // RORImm 0U, // RetRA 0U, // RetRA16 - 1U, // SAT_S_B - 1U, // SAT_S_D - 0U, // SAT_S_H - 1U, // SAT_S_W - 1U, // SAT_U_B - 1U, // SAT_U_D - 0U, // SAT_U_H - 1U, // SAT_U_W - 0U, // SB - 0U, // SB16_MM - 0U, // SB64 - 0U, // SB_MM - 0U, // SC - 0U, // SCD - 0U, // SCD_R6 - 0U, // SC_MM - 0U, // SC_R6 - 0U, // SD - 0U, // SDBBP - 0U, // SDBBP16_MM - 0U, // SDBBP_MM - 0U, // SDBBP_R6 - 0U, // SDC1 - 0U, // SDC164 - 0U, // SDC1_MM - 0U, // SDC2 - 0U, // SDC2_R6 - 0U, // SDC3 - 0U, // SDIV - 0U, // SDIV_MM - 0U, // SDL - 0U, // SDR - 0U, // SDXC1 - 0U, // SDXC164 - 0U, // SEB - 0U, // SEB64 - 0U, // SEB_MM - 0U, // SEH - 0U, // SEH64 - 0U, // SEH_MM - 0U, // SELEQZ - 0U, // SELEQZ64 - 0U, // SELEQZ_D - 0U, // SELEQZ_S - 0U, // SELNEZ - 0U, // SELNEZ64 - 0U, // SELNEZ_D - 0U, // SELNEZ_S - 2U, // SEL_D - 2U, // SEL_S - 0U, // SEQ - 0U, // SEQi - 0U, // SH - 0U, // SH16_MM - 0U, // SH64 - 0U, // SHF_B - 0U, // SHF_H - 0U, // SHF_W - 0U, // SHILO - 0U, // SHILOV - 0U, // SHLLV_PH - 0U, // SHLLV_QB - 0U, // SHLLV_S_PH - 0U, // SHLLV_S_W - 1U, // SHLL_PH - 1U, // SHLL_QB - 1U, // SHLL_S_PH - 1U, // SHLL_S_W - 0U, // SHRAV_PH - 0U, // SHRAV_QB - 0U, // SHRAV_R_PH - 0U, // SHRAV_R_QB - 0U, // SHRAV_R_W - 1U, // SHRA_PH - 1U, // SHRA_QB - 1U, // SHRA_R_PH - 1U, // SHRA_R_QB - 1U, // SHRA_R_W - 0U, // SHRLV_PH - 0U, // SHRLV_QB - 1U, // SHRL_PH - 1U, // SHRL_QB - 0U, // SH_MM - 9U, // SLDI_B - 9U, // SLDI_D - 9U, // SLDI_H - 9U, // SLDI_W - 10U, // SLD_B - 10U, // SLD_D - 10U, // SLD_H - 10U, // SLD_W - 1U, // SLL - 0U, // SLL16_MM - 0U, // SLL64_32 - 0U, // SLL64_64 - 0U, // SLLI_B - 0U, // SLLI_D - 0U, // SLLI_H - 0U, // SLLI_W - 0U, // SLLV - 0U, // SLLV_MM - 0U, // SLL_B - 0U, // SLL_D - 0U, // SLL_H - 1U, // SLL_MM - 0U, // SLL_W - 0U, // SLT - 0U, // SLT64 - 0U, // SLT_MM - 0U, // SLTi - 0U, // SLTi64 - 0U, // SLTi_MM - 0U, // SLTiu - 0U, // SLTiu64 - 0U, // SLTiu_MM - 0U, // SLTu - 0U, // SLTu64 - 0U, // SLTu_MM - 0U, // SNE - 0U, // SNEi + 0U, // SDC1_M1 + 0U, // SDIV_MM_Pseudo + 0U, // SDMacro + 128U, // SDivIMacro + 128U, // SDivMacro + 128U, // SEQIMacro + 128U, // SEQMacro + 128U, // SGE + 128U, // SGEImm + 128U, // SGEImm64 + 128U, // SGEU + 128U, // SGEUImm + 128U, // SGEUImm64 + 128U, // SGTImm + 128U, // SGTImm64 + 128U, // SGTUImm + 128U, // SGTUImm64 + 128U, // SLE + 128U, // SLEImm + 128U, // SLEImm64 + 128U, // SLEU + 128U, // SLEUImm + 128U, // SLEUImm64 + 128U, // SLTImm64 + 128U, // SLTUImm64 + 128U, // SNEIMacro + 128U, // SNEMacro 0U, // SNZ_B_PSEUDO 0U, // SNZ_D_PSEUDO 0U, // SNZ_H_PSEUDO 0U, // SNZ_V_PSEUDO 0U, // SNZ_W_PSEUDO - 8U, // SPLATI_B - 8U, // SPLATI_D - 8U, // SPLATI_H - 8U, // SPLATI_W - 8U, // SPLAT_B - 8U, // SPLAT_D - 8U, // SPLAT_H - 8U, // SPLAT_W - 1U, // SRA - 0U, // SRAI_B - 0U, // SRAI_D - 0U, // SRAI_H - 0U, // SRAI_W - 1U, // SRARI_B - 1U, // SRARI_D - 0U, // SRARI_H - 1U, // SRARI_W - 0U, // SRAR_B - 0U, // SRAR_D - 0U, // SRAR_H - 0U, // SRAR_W - 0U, // SRAV - 0U, // SRAV_MM - 0U, // SRA_B - 0U, // SRA_D - 0U, // SRA_H - 1U, // SRA_MM - 0U, // SRA_W - 1U, // SRL - 0U, // SRL16_MM - 0U, // SRLI_B - 0U, // SRLI_D - 0U, // SRLI_H - 0U, // SRLI_W - 1U, // SRLRI_B - 1U, // SRLRI_D - 0U, // SRLRI_H - 1U, // SRLRI_W - 0U, // SRLR_B - 0U, // SRLR_D - 0U, // SRLR_H - 0U, // SRLR_W - 0U, // SRLV - 0U, // SRLV_MM - 0U, // SRL_B - 0U, // SRL_D - 0U, // SRL_H - 1U, // SRL_MM - 0U, // SRL_W - 0U, // SSNOP - 0U, // SSNOP_MM + 128U, // SRemIMacro + 128U, // SRemMacro 0U, // STORE_ACC128 0U, // STORE_ACC64 0U, // STORE_ACC64DSP 0U, // STORE_CCOND_DSP - 0U, // ST_B - 0U, // ST_D - 0U, // ST_H - 0U, // ST_W - 0U, // SUB - 0U, // SUBQH_PH - 0U, // SUBQH_R_PH - 0U, // SUBQH_R_W - 0U, // SUBQH_W - 0U, // SUBQ_PH - 0U, // SUBQ_S_PH - 0U, // SUBQ_S_W - 0U, // SUBSUS_U_B - 0U, // SUBSUS_U_D - 0U, // SUBSUS_U_H - 0U, // SUBSUS_U_W - 0U, // SUBSUU_S_B - 0U, // SUBSUU_S_D - 0U, // SUBSUU_S_H - 0U, // SUBSUU_S_W - 0U, // SUBS_S_B - 0U, // SUBS_S_D - 0U, // SUBS_S_H - 0U, // SUBS_S_W - 0U, // SUBS_U_B - 0U, // SUBS_U_D - 0U, // SUBS_U_H - 0U, // SUBS_U_W - 0U, // SUBU16_MM - 0U, // SUBUH_QB - 0U, // SUBUH_R_QB - 0U, // SUBU_PH - 0U, // SUBU_QB - 0U, // SUBU_S_PH - 0U, // SUBU_S_QB - 0U, // SUBVI_B - 0U, // SUBVI_D - 0U, // SUBVI_H - 0U, // SUBVI_W - 0U, // SUBV_B - 0U, // SUBV_D - 0U, // SUBV_H - 0U, // SUBV_W - 0U, // SUB_MM - 0U, // SUBu - 0U, // SUBu_MM - 0U, // SUXC1 - 0U, // SUXC164 - 0U, // SUXC1_MM - 0U, // SW - 0U, // SW16_MM - 0U, // SW64 - 0U, // SWC1 - 0U, // SWC1_MM - 0U, // SWC2 - 0U, // SWC2_R6 - 0U, // SWC3 - 0U, // SWL - 0U, // SWL64 - 0U, // SWL_MM - 0U, // SWM16_MM - 0U, // SWM32_MM + 0U, // STR_D + 0U, // STR_W + 0U, // ST_F16 0U, // SWM_MM - 0U, // SWP_MM - 0U, // SWR - 0U, // SWR64 - 0U, // SWR_MM - 0U, // SWSP_MM - 0U, // SWXC1 - 0U, // SWXC1_MM - 0U, // SW_MM - 0U, // SYNC - 0U, // SYNCI - 0U, // SYNC_MM - 0U, // SYSCALL - 0U, // SYSCALL_MM 0U, // SZ_B_PSEUDO 0U, // SZ_D_PSEUDO 0U, // SZ_H_PSEUDO 0U, // SZ_V_PSEUDO 0U, // SZ_W_PSEUDO - 0U, // Save16 - 0U, // SaveX16 - 0U, // SbRxRyOffMemX16 - 0U, // SebRx16 - 0U, // SehRx16 + 0U, // SaaAddr + 0U, // SaadAddr 0U, // SelBeqZ 0U, // SelBneZ 0U, // SelTBteqZCmp @@ -3497,2229 +5171,6072 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) 0U, // SelTBtneZSlti 0U, // SelTBtneZSltiu 0U, // SelTBtneZSltu - 0U, // ShRxRyOffMemX16 - 1U, // SllX16 - 0U, // SllvRxRy16 0U, // SltCCRxRy16 - 0U, // SltRxRy16 0U, // SltiCCRxImmX16 - 0U, // SltiRxImm16 - 0U, // SltiRxImmX16 0U, // SltiuCCRxImmX16 - 0U, // SltiuRxImm16 - 0U, // SltiuRxImmX16 0U, // SltuCCRxRy16 - 0U, // SltuRxRy16 0U, // SltuRxRyRz16 - 1U, // SraX16 + 0U, // TAILCALL + 0U, // TAILCALL64R6REG + 0U, // TAILCALLHB64R6REG + 0U, // TAILCALLHBR6REG + 0U, // TAILCALLR6REG + 0U, // TAILCALLREG + 0U, // TAILCALLREG64 + 0U, // TAILCALLREGHB + 0U, // TAILCALLREGHB64 + 0U, // TAILCALLREG_MM + 0U, // TAILCALLREG_MMR6 + 0U, // TAILCALLREG_NM + 0U, // TAILCALL_MM + 0U, // TAILCALL_MMR6 + 0U, // TAILCALL_NM + 0U, // TRAP + 0U, // TRAP_MM + 0U, // UDIV_MM_Pseudo + 128U, // UDivIMacro + 128U, // UDivMacro + 128U, // URemIMacro + 128U, // URemMacro + 0U, // Ulh + 0U, // Ulhu + 0U, // Ulw + 0U, // Ush + 0U, // Usw + 0U, // XOR_V_D_PSEUDO + 0U, // XOR_V_H_PSEUDO + 0U, // XOR_V_W_PSEUDO + 0U, // ABSQ_S_PH + 0U, // ABSQ_S_PH_MM + 0U, // ABSQ_S_QB + 0U, // ABSQ_S_QB_MMR2 + 0U, // ABSQ_S_W + 0U, // ABSQ_S_W_MM + 128U, // ADD + 12U, // ADDIU48_NM + 128U, // ADDIUGP48_NM + 128U, // ADDIUGPB_NM + 128U, // ADDIUGPW_NM + 128U, // ADDIUNEG_NM + 0U, // ADDIUPC + 0U, // ADDIUPC_MM + 0U, // ADDIUPC_MMR6 + 0U, // ADDIUR1SP_MM + 20U, // ADDIUR1SP_NM + 128U, // ADDIUR2_MM + 152U, // ADDIUR2_NM + 128U, // ADDIURS5_NM + 0U, // ADDIUS5_MM + 0U, // ADDIUSP_MM + 128U, // ADDIU_MMR6 + 16U, // ADDIU_NM + 128U, // ADDQH_PH + 128U, // ADDQH_PH_MMR2 + 128U, // ADDQH_R_PH + 128U, // ADDQH_R_PH_MMR2 + 128U, // ADDQH_R_W + 128U, // ADDQH_R_W_MMR2 + 128U, // ADDQH_W + 128U, // ADDQH_W_MMR2 + 128U, // ADDQ_PH + 128U, // ADDQ_PH_MM + 128U, // ADDQ_S_PH + 128U, // ADDQ_S_PH_MM + 128U, // ADDQ_S_W + 128U, // ADDQ_S_W_MM + 128U, // ADDR_PS64 + 128U, // ADDSC + 128U, // ADDSC_MM + 128U, // ADDS_A_B + 128U, // ADDS_A_D + 128U, // ADDS_A_H + 128U, // ADDS_A_W + 128U, // ADDS_S_B + 128U, // ADDS_S_D + 128U, // ADDS_S_H + 128U, // ADDS_S_W + 128U, // ADDS_U_B + 128U, // ADDS_U_D + 128U, // ADDS_U_H + 128U, // ADDS_U_W + 128U, // ADDU16_MM + 128U, // ADDU16_MMR6 + 128U, // ADDUH_QB + 128U, // ADDUH_QB_MMR2 + 128U, // ADDUH_R_QB + 128U, // ADDUH_R_QB_MMR2 + 128U, // ADDU_MMR6 + 128U, // ADDU_PH + 128U, // ADDU_PH_MMR2 + 128U, // ADDU_QB + 128U, // ADDU_QB_MM + 128U, // ADDU_S_PH + 128U, // ADDU_S_PH_MMR2 + 128U, // ADDU_S_QB + 128U, // ADDU_S_QB_MM + 152U, // ADDVI_B + 152U, // ADDVI_D + 152U, // ADDVI_H + 152U, // ADDVI_W + 128U, // ADDV_B + 128U, // ADDV_D + 128U, // ADDV_H + 128U, // ADDV_W + 128U, // ADDWC + 128U, // ADDWC_MM + 128U, // ADD_A_B + 128U, // ADD_A_D + 128U, // ADD_A_H + 128U, // ADD_A_W + 128U, // ADD_MM + 128U, // ADD_MMR6 + 128U, // ADD_NM + 128U, // ADDi + 128U, // ADDi_MM + 128U, // ADDiu + 128U, // ADDiu_MM + 128U, // ADDu + 128U, // ADDu16_NM + 128U, // ADDu4x4_NM + 128U, // ADDu_MM + 128U, // ADDu_NM + 1024U, // ALIGN + 1024U, // ALIGN_MMR6 + 0U, // ALUIPC + 0U, // ALUIPC_MMR6 + 0U, // ALUIPC_NM + 128U, // AND + 0U, // AND16_MM + 0U, // AND16_MMR6 + 128U, // AND16_NM + 128U, // AND64 + 128U, // ANDI16_MM + 128U, // ANDI16_MMR6 + 16U, // ANDI16_NM + 20U, // ANDI_B + 16U, // ANDI_MMR6 + 128U, // ANDI_NM + 128U, // AND_MM + 128U, // AND_MMR6 + 128U, // AND_NM + 128U, // AND_V + 16U, // ANDi + 16U, // ANDi64 + 16U, // ANDi_MM + 152U, // APPEND + 152U, // APPEND_MMR2 + 128U, // ASUB_S_B + 128U, // ASUB_S_D + 128U, // ASUB_S_H + 128U, // ASUB_S_W + 128U, // ASUB_U_B + 128U, // ASUB_U_D + 128U, // ASUB_U_H + 128U, // ASUB_U_W + 16U, // AUI + 0U, // AUIPC + 0U, // AUIPC_MMR6 + 16U, // AUI_MMR6 + 128U, // AVER_S_B + 128U, // AVER_S_D + 128U, // AVER_S_H + 128U, // AVER_S_W + 128U, // AVER_U_B + 128U, // AVER_U_D + 128U, // AVER_U_H + 128U, // AVER_U_W + 128U, // AVE_S_B + 128U, // AVE_S_D + 128U, // AVE_S_H + 128U, // AVE_S_W + 128U, // AVE_U_B + 128U, // AVE_U_D + 128U, // AVE_U_H + 128U, // AVE_U_W + 0U, // AddiuRxImmX16 + 0U, // AddiuRxPcImmX16 + 1U, // AddiuRxRxImm16 + 0U, // AddiuRxRxImmX16 + 0U, // AddiuRxRyOffMemX16 + 0U, // AddiuSpImm16 + 0U, // AddiuSpImmX16 + 128U, // AdduRxRyRz16 + 0U, // AndRxRxRy16 + 0U, // B16_MM + 128U, // BADDu + 0U, // BAL + 0U, // BALC + 0U, // BALC16_NM + 0U, // BALC_MMR6 + 0U, // BALC_NM + 156U, // BALIGN + 156U, // BALIGN_MMR2 + 0U, // BALRSC_NM + 4U, // BBEQZC_NM + 0U, // BBIT0 + 0U, // BBIT032 + 0U, // BBIT1 + 0U, // BBIT132 + 4U, // BBNEZC_NM + 0U, // BC + 0U, // BC16_MMR6 + 0U, // BC16_NM + 0U, // BC1EQZ + 0U, // BC1EQZC_MMR6 + 0U, // BC1F + 0U, // BC1FL + 0U, // BC1F_MM + 0U, // BC1NEZ + 0U, // BC1NEZC_MMR6 + 0U, // BC1T + 0U, // BC1TL + 0U, // BC1T_MM + 0U, // BC2EQZ + 0U, // BC2EQZC_MMR6 + 0U, // BC2NEZ + 0U, // BC2NEZC_MMR6 + 136U, // BCLRI_B + 160U, // BCLRI_D + 164U, // BCLRI_H + 152U, // BCLRI_W + 128U, // BCLR_B + 128U, // BCLR_D + 128U, // BCLR_H + 128U, // BCLR_W + 0U, // BC_MMR6 + 0U, // BC_NM + 4U, // BEQ + 4U, // BEQ64 + 4U, // BEQC + 4U, // BEQC16_NM + 4U, // BEQC64 + 4U, // BEQC_MMR6 + 4U, // BEQC_NM + 4U, // BEQCzero_NM + 4U, // BEQIC_NM + 4U, // BEQL + 0U, // BEQZ16_MM + 0U, // BEQZALC + 0U, // BEQZALC_MMR6 + 0U, // BEQZC + 0U, // BEQZC16_MMR6 + 0U, // BEQZC16_NM + 0U, // BEQZC64 + 0U, // BEQZC_MM + 0U, // BEQZC_MMR6 + 0U, // BEQZC_NM + 4U, // BEQ_MM + 4U, // BGEC + 4U, // BGEC64 + 4U, // BGEC_MMR6 + 4U, // BGEC_NM + 4U, // BGEIC_NM + 4U, // BGEIUC_NM + 4U, // BGEUC + 4U, // BGEUC64 + 4U, // BGEUC_MMR6 + 4U, // BGEUC_NM + 0U, // BGEZ + 0U, // BGEZ64 + 0U, // BGEZAL + 0U, // BGEZALC + 0U, // BGEZALC_MMR6 + 0U, // BGEZALL + 0U, // BGEZALS_MM + 0U, // BGEZAL_MM + 0U, // BGEZC + 0U, // BGEZC64 + 0U, // BGEZC_MMR6 + 0U, // BGEZL + 0U, // BGEZ_MM + 0U, // BGTZ + 0U, // BGTZ64 + 0U, // BGTZALC + 0U, // BGTZALC_MMR6 + 0U, // BGTZC + 0U, // BGTZC64 + 0U, // BGTZC_MMR6 + 0U, // BGTZL + 0U, // BGTZ_MM + 168U, // BINSLI_B + 44U, // BINSLI_D + 176U, // BINSLI_H + 52U, // BINSLI_W + 184U, // BINSL_B + 184U, // BINSL_D + 184U, // BINSL_H + 184U, // BINSL_W + 168U, // BINSRI_B + 44U, // BINSRI_D + 176U, // BINSRI_H + 52U, // BINSRI_W + 184U, // BINSR_B + 184U, // BINSR_D + 184U, // BINSR_H + 184U, // BINSR_W + 0U, // BITREV + 0U, // BITREVW_NM + 0U, // BITREV_MM + 0U, // BITSWAP + 0U, // BITSWAP_MMR6 + 0U, // BLEZ + 0U, // BLEZ64 + 0U, // BLEZALC + 0U, // BLEZALC_MMR6 + 0U, // BLEZC + 0U, // BLEZC64 + 0U, // BLEZC_MMR6 + 0U, // BLEZL + 0U, // BLEZ_MM + 4U, // BLTC + 4U, // BLTC64 + 4U, // BLTC_MMR6 + 4U, // BLTC_NM + 4U, // BLTIC_NM + 4U, // BLTIUC_NM + 4U, // BLTUC + 4U, // BLTUC64 + 4U, // BLTUC_MMR6 + 4U, // BLTUC_NM + 0U, // BLTZ + 0U, // BLTZ64 + 0U, // BLTZAL + 0U, // BLTZALC + 0U, // BLTZALC_MMR6 + 0U, // BLTZALL + 0U, // BLTZALS_MM + 0U, // BLTZAL_MM + 0U, // BLTZC + 0U, // BLTZC64 + 0U, // BLTZC_MMR6 + 0U, // BLTZL + 0U, // BLTZ_MM + 60U, // BMNZI_B + 184U, // BMNZ_V + 60U, // BMZI_B + 184U, // BMZ_V + 4U, // BNE + 4U, // BNE64 + 4U, // BNEC + 4U, // BNEC16_NM + 4U, // BNEC64 + 4U, // BNEC_MMR6 + 4U, // BNEC_NM + 4U, // BNECzero_NM + 136U, // BNEGI_B + 160U, // BNEGI_D + 164U, // BNEGI_H + 152U, // BNEGI_W + 128U, // BNEG_B + 128U, // BNEG_D + 128U, // BNEG_H + 128U, // BNEG_W + 4U, // BNEIC_NM + 4U, // BNEL + 0U, // BNEZ16_MM + 0U, // BNEZALC + 0U, // BNEZALC_MMR6 + 0U, // BNEZC + 0U, // BNEZC16_MMR6 + 0U, // BNEZC16_NM + 0U, // BNEZC64 + 0U, // BNEZC_MM + 0U, // BNEZC_MMR6 + 0U, // BNEZC_NM + 4U, // BNE_MM + 4U, // BNVC + 4U, // BNVC_MMR6 + 0U, // BNZ_B + 0U, // BNZ_D + 0U, // BNZ_H + 0U, // BNZ_V + 0U, // BNZ_W + 4U, // BOVC + 4U, // BOVC_MMR6 + 0U, // BPOSGE32 + 0U, // BPOSGE32C_MMR3 + 0U, // BPOSGE32_MM + 0U, // BREAK + 0U, // BREAK16_MM + 0U, // BREAK16_MMR6 + 0U, // BREAK16_NM + 0U, // BREAK_MM + 0U, // BREAK_MMR6 + 0U, // BREAK_NM + 0U, // BRSC_NM + 60U, // BSELI_B + 184U, // BSEL_V + 136U, // BSETI_B + 160U, // BSETI_D + 164U, // BSETI_H + 152U, // BSETI_W + 128U, // BSET_B + 128U, // BSET_D + 128U, // BSET_H + 128U, // BSET_W + 0U, // BYTEREVW_NM + 0U, // BZ_B + 0U, // BZ_D + 0U, // BZ_H + 0U, // BZ_V + 0U, // BZ_W + 1U, // BeqzRxImm16 + 0U, // BeqzRxImmX16 + 0U, // Bimm16 + 0U, // BimmX16 + 1U, // BnezRxImm16 + 0U, // BnezRxImmX16 + 0U, // Break16 + 0U, // Bteqz16 + 0U, // BteqzX16 + 0U, // Btnez16 + 0U, // BtnezX16 + 0U, // CACHE + 0U, // CACHEE + 0U, // CACHEE_MM + 0U, // CACHE_MM + 0U, // CACHE_MMR6 + 0U, // CACHE_NM + 0U, // CACHE_R6 + 0U, // CEIL_L_D64 + 0U, // CEIL_L_D_MMR6 + 0U, // CEIL_L_S + 0U, // CEIL_L_S_MMR6 + 0U, // CEIL_W_D32 + 0U, // CEIL_W_D64 + 0U, // CEIL_W_D_MMR6 + 0U, // CEIL_W_MM + 0U, // CEIL_W_S + 0U, // CEIL_W_S_MM + 0U, // CEIL_W_S_MMR6 + 128U, // CEQI_B + 128U, // CEQI_D + 128U, // CEQI_H + 128U, // CEQI_W + 128U, // CEQ_B + 128U, // CEQ_D + 128U, // CEQ_H + 128U, // CEQ_W + 0U, // CFC1 + 0U, // CFC1_MM + 0U, // CFC2_MM + 0U, // CFCMSA + 2072U, // CINS + 2072U, // CINS32 + 2072U, // CINS64_32 + 2072U, // CINS_i32 + 0U, // CLASS_D + 0U, // CLASS_D_MMR6 + 0U, // CLASS_S + 0U, // CLASS_S_MMR6 + 128U, // CLEI_S_B + 128U, // CLEI_S_D + 128U, // CLEI_S_H + 128U, // CLEI_S_W + 152U, // CLEI_U_B + 152U, // CLEI_U_D + 152U, // CLEI_U_H + 152U, // CLEI_U_W + 128U, // CLE_S_B + 128U, // CLE_S_D + 128U, // CLE_S_H + 128U, // CLE_S_W + 128U, // CLE_U_B + 128U, // CLE_U_D + 128U, // CLE_U_H + 128U, // CLE_U_W + 0U, // CLO + 0U, // CLO_MM + 0U, // CLO_MMR6 + 0U, // CLO_NM + 0U, // CLO_R6 + 128U, // CLTI_S_B + 128U, // CLTI_S_D + 128U, // CLTI_S_H + 128U, // CLTI_S_W + 152U, // CLTI_U_B + 152U, // CLTI_U_D + 152U, // CLTI_U_H + 152U, // CLTI_U_W + 128U, // CLT_S_B + 128U, // CLT_S_D + 128U, // CLT_S_H + 128U, // CLT_S_W + 128U, // CLT_U_B + 128U, // CLT_U_D + 128U, // CLT_U_H + 128U, // CLT_U_W + 0U, // CLZ + 0U, // CLZ_MM + 0U, // CLZ_MMR6 + 0U, // CLZ_NM + 0U, // CLZ_R6 + 128U, // CMPGDU_EQ_QB + 128U, // CMPGDU_EQ_QB_MMR2 + 128U, // CMPGDU_LE_QB + 128U, // CMPGDU_LE_QB_MMR2 + 128U, // CMPGDU_LT_QB + 128U, // CMPGDU_LT_QB_MMR2 + 128U, // CMPGU_EQ_QB + 128U, // CMPGU_EQ_QB_MM + 128U, // CMPGU_LE_QB + 128U, // CMPGU_LE_QB_MM + 128U, // CMPGU_LT_QB + 128U, // CMPGU_LT_QB_MM + 0U, // CMPU_EQ_QB + 0U, // CMPU_EQ_QB_MM + 0U, // CMPU_LE_QB + 0U, // CMPU_LE_QB_MM + 0U, // CMPU_LT_QB + 0U, // CMPU_LT_QB_MM + 128U, // CMP_AF_D_MMR6 + 128U, // CMP_AF_S_MMR6 + 128U, // CMP_EQ_D + 128U, // CMP_EQ_D_MMR6 + 0U, // CMP_EQ_PH + 0U, // CMP_EQ_PH_MM + 128U, // CMP_EQ_S + 128U, // CMP_EQ_S_MMR6 + 128U, // CMP_F_D + 128U, // CMP_F_S + 128U, // CMP_LE_D + 128U, // CMP_LE_D_MMR6 + 0U, // CMP_LE_PH + 0U, // CMP_LE_PH_MM + 128U, // CMP_LE_S + 128U, // CMP_LE_S_MMR6 + 128U, // CMP_LT_D + 128U, // CMP_LT_D_MMR6 + 0U, // CMP_LT_PH + 0U, // CMP_LT_PH_MM + 128U, // CMP_LT_S + 128U, // CMP_LT_S_MMR6 + 128U, // CMP_SAF_D + 128U, // CMP_SAF_D_MMR6 + 128U, // CMP_SAF_S + 128U, // CMP_SAF_S_MMR6 + 128U, // CMP_SEQ_D + 128U, // CMP_SEQ_D_MMR6 + 128U, // CMP_SEQ_S + 128U, // CMP_SEQ_S_MMR6 + 128U, // CMP_SLE_D + 128U, // CMP_SLE_D_MMR6 + 128U, // CMP_SLE_S + 128U, // CMP_SLE_S_MMR6 + 128U, // CMP_SLT_D + 128U, // CMP_SLT_D_MMR6 + 128U, // CMP_SLT_S + 128U, // CMP_SLT_S_MMR6 + 128U, // CMP_SUEQ_D + 128U, // CMP_SUEQ_D_MMR6 + 128U, // CMP_SUEQ_S + 128U, // CMP_SUEQ_S_MMR6 + 128U, // CMP_SULE_D + 128U, // CMP_SULE_D_MMR6 + 128U, // CMP_SULE_S + 128U, // CMP_SULE_S_MMR6 + 128U, // CMP_SULT_D + 128U, // CMP_SULT_D_MMR6 + 128U, // CMP_SULT_S + 128U, // CMP_SULT_S_MMR6 + 128U, // CMP_SUN_D + 128U, // CMP_SUN_D_MMR6 + 128U, // CMP_SUN_S + 128U, // CMP_SUN_S_MMR6 + 128U, // CMP_UEQ_D + 128U, // CMP_UEQ_D_MMR6 + 128U, // CMP_UEQ_S + 128U, // CMP_UEQ_S_MMR6 + 128U, // CMP_ULE_D + 128U, // CMP_ULE_D_MMR6 + 128U, // CMP_ULE_S + 128U, // CMP_ULE_S_MMR6 + 128U, // CMP_ULT_D + 128U, // CMP_ULT_D_MMR6 + 128U, // CMP_ULT_S + 128U, // CMP_ULT_S_MMR6 + 128U, // CMP_UN_D + 128U, // CMP_UN_D_MMR6 + 128U, // CMP_UN_S + 128U, // CMP_UN_S_MMR6 + 293U, // COPY_S_B + 321U, // COPY_S_D + 265U, // COPY_S_H + 285U, // COPY_S_W + 293U, // COPY_U_B + 265U, // COPY_U_H + 285U, // COPY_U_W + 128U, // CRC32B + 0U, // CRC32B_NM + 128U, // CRC32CB + 0U, // CRC32CB_NM + 128U, // CRC32CD + 128U, // CRC32CH + 0U, // CRC32CH_NM + 128U, // CRC32CW + 0U, // CRC32CW_NM + 128U, // CRC32D + 128U, // CRC32H + 0U, // CRC32H_NM + 128U, // CRC32W + 0U, // CRC32W_NM + 0U, // CTC1 + 0U, // CTC1_MM + 0U, // CTC2_MM + 0U, // CTCMSA + 0U, // CVT_D32_S + 0U, // CVT_D32_S_MM + 0U, // CVT_D32_W + 0U, // CVT_D32_W_MM + 0U, // CVT_D64_L + 0U, // CVT_D64_S + 0U, // CVT_D64_S_MM + 0U, // CVT_D64_W + 0U, // CVT_D64_W_MM + 0U, // CVT_D_L_MMR6 + 0U, // CVT_L_D64 + 0U, // CVT_L_D64_MM + 0U, // CVT_L_D_MMR6 + 0U, // CVT_L_S + 0U, // CVT_L_S_MM + 0U, // CVT_L_S_MMR6 + 0U, // CVT_PS_PW64 + 128U, // CVT_PS_S64 + 0U, // CVT_PW_PS64 + 0U, // CVT_S_D32 + 0U, // CVT_S_D32_MM + 0U, // CVT_S_D64 + 0U, // CVT_S_D64_MM + 0U, // CVT_S_L + 0U, // CVT_S_L_MMR6 + 0U, // CVT_S_PL64 + 0U, // CVT_S_PU64 + 0U, // CVT_S_W + 0U, // CVT_S_W_MM + 0U, // CVT_S_W_MMR6 + 0U, // CVT_W_D32 + 0U, // CVT_W_D32_MM + 0U, // CVT_W_D64 + 0U, // CVT_W_D64_MM + 0U, // CVT_W_S + 0U, // CVT_W_S_MM + 0U, // CVT_W_S_MMR6 + 128U, // C_EQ_D32 + 128U, // C_EQ_D32_MM + 128U, // C_EQ_D64 + 128U, // C_EQ_D64_MM + 128U, // C_EQ_S + 128U, // C_EQ_S_MM + 128U, // C_F_D32 + 128U, // C_F_D32_MM + 128U, // C_F_D64 + 128U, // C_F_D64_MM + 128U, // C_F_S + 128U, // C_F_S_MM + 128U, // C_LE_D32 + 128U, // C_LE_D32_MM + 128U, // C_LE_D64 + 128U, // C_LE_D64_MM + 128U, // C_LE_S + 128U, // C_LE_S_MM + 128U, // C_LT_D32 + 128U, // C_LT_D32_MM + 128U, // C_LT_D64 + 128U, // C_LT_D64_MM + 128U, // C_LT_S + 128U, // C_LT_S_MM + 128U, // C_NGE_D32 + 128U, // C_NGE_D32_MM + 128U, // C_NGE_D64 + 128U, // C_NGE_D64_MM + 128U, // C_NGE_S + 128U, // C_NGE_S_MM + 128U, // C_NGLE_D32 + 128U, // C_NGLE_D32_MM + 128U, // C_NGLE_D64 + 128U, // C_NGLE_D64_MM + 128U, // C_NGLE_S + 128U, // C_NGLE_S_MM + 128U, // C_NGL_D32 + 128U, // C_NGL_D32_MM + 128U, // C_NGL_D64 + 128U, // C_NGL_D64_MM + 128U, // C_NGL_S + 128U, // C_NGL_S_MM + 128U, // C_NGT_D32 + 128U, // C_NGT_D32_MM + 128U, // C_NGT_D64 + 128U, // C_NGT_D64_MM + 128U, // C_NGT_S + 128U, // C_NGT_S_MM + 128U, // C_OLE_D32 + 128U, // C_OLE_D32_MM + 128U, // C_OLE_D64 + 128U, // C_OLE_D64_MM + 128U, // C_OLE_S + 128U, // C_OLE_S_MM + 128U, // C_OLT_D32 + 128U, // C_OLT_D32_MM + 128U, // C_OLT_D64 + 128U, // C_OLT_D64_MM + 128U, // C_OLT_S + 128U, // C_OLT_S_MM + 128U, // C_SEQ_D32 + 128U, // C_SEQ_D32_MM + 128U, // C_SEQ_D64 + 128U, // C_SEQ_D64_MM + 128U, // C_SEQ_S + 128U, // C_SEQ_S_MM + 128U, // C_SF_D32 + 128U, // C_SF_D32_MM + 128U, // C_SF_D64 + 128U, // C_SF_D64_MM + 128U, // C_SF_S + 128U, // C_SF_S_MM + 128U, // C_UEQ_D32 + 128U, // C_UEQ_D32_MM + 128U, // C_UEQ_D64 + 128U, // C_UEQ_D64_MM + 128U, // C_UEQ_S + 128U, // C_UEQ_S_MM + 128U, // C_ULE_D32 + 128U, // C_ULE_D32_MM + 128U, // C_ULE_D64 + 128U, // C_ULE_D64_MM + 128U, // C_ULE_S + 128U, // C_ULE_S_MM + 128U, // C_ULT_D32 + 128U, // C_ULT_D32_MM + 128U, // C_ULT_D64 + 128U, // C_ULT_D64_MM + 128U, // C_ULT_S + 128U, // C_ULT_S_MM + 128U, // C_UN_D32 + 128U, // C_UN_D32_MM + 128U, // C_UN_D64 + 128U, // C_UN_D64_MM + 128U, // C_UN_S + 128U, // C_UN_S_MM + 0U, // CmpRxRy16 + 1U, // CmpiRxImm16 + 0U, // CmpiRxImmX16 + 128U, // DADD + 128U, // DADDi + 128U, // DADDiu + 128U, // DADDu + 16U, // DAHI + 3072U, // DALIGN + 16U, // DATI + 16U, // DAUI + 0U, // DBITSWAP + 0U, // DCLO + 0U, // DCLO_R6 + 0U, // DCLZ + 0U, // DCLZ_R6 + 128U, // DDIV + 128U, // DDIVU + 0U, // DERET + 0U, // DERET_MM + 0U, // DERET_MMR6 + 0U, // DERET_NM + 4128U, // DEXT + 5152U, // DEXT64_32 + 6168U, // DEXTM + 452U, // DEXTU + 0U, // DI + 7200U, // DINS + 8216U, // DINSM + 580U, // DINSU + 128U, // DIV + 128U, // DIVU + 128U, // DIVU_MMR6 + 128U, // DIVU_NM + 128U, // DIV_MMR6 + 128U, // DIV_NM + 128U, // DIV_S_B + 128U, // DIV_S_D + 128U, // DIV_S_H + 128U, // DIV_S_W + 128U, // DIV_U_B + 128U, // DIV_U_D + 128U, // DIV_U_H + 128U, // DIV_U_W + 0U, // DI_MM + 0U, // DI_MMR6 + 0U, // DI_NM + 9216U, // DLSA + 9216U, // DLSA_R6 + 136U, // DMFC0 + 0U, // DMFC1 + 136U, // DMFC2 + 0U, // DMFC2_OCTEON + 136U, // DMFGC0 + 128U, // DMOD + 128U, // DMODU + 0U, // DMT + 0U, // DMTC0 + 0U, // DMTC1 + 0U, // DMTC2 + 0U, // DMTC2_OCTEON + 0U, // DMTGC0 + 0U, // DMT_NM + 128U, // DMUH + 128U, // DMUHU + 128U, // DMUL + 0U, // DMULT + 0U, // DMULTu + 128U, // DMULU + 128U, // DMUL_R6 + 128U, // DOTP_S_D + 128U, // DOTP_S_H + 128U, // DOTP_S_W + 128U, // DOTP_U_D + 128U, // DOTP_U_H + 128U, // DOTP_U_W + 184U, // DPADD_S_D + 184U, // DPADD_S_H + 184U, // DPADD_S_W + 184U, // DPADD_U_D + 184U, // DPADD_U_H + 184U, // DPADD_U_W + 128U, // DPAQX_SA_W_PH + 128U, // DPAQX_SA_W_PH_MMR2 + 128U, // DPAQX_S_W_PH + 128U, // DPAQX_S_W_PH_MMR2 + 128U, // DPAQ_SA_L_W + 128U, // DPAQ_SA_L_W_MM + 128U, // DPAQ_S_W_PH + 128U, // DPAQ_S_W_PH_MM + 128U, // DPAU_H_QBL + 128U, // DPAU_H_QBL_MM + 128U, // DPAU_H_QBR + 128U, // DPAU_H_QBR_MM + 128U, // DPAX_W_PH + 128U, // DPAX_W_PH_MMR2 + 128U, // DPA_W_PH + 128U, // DPA_W_PH_MMR2 + 0U, // DPOP + 128U, // DPSQX_SA_W_PH + 128U, // DPSQX_SA_W_PH_MMR2 + 128U, // DPSQX_S_W_PH + 128U, // DPSQX_S_W_PH_MMR2 + 128U, // DPSQ_SA_L_W + 128U, // DPSQ_SA_L_W_MM + 128U, // DPSQ_S_W_PH + 128U, // DPSQ_S_W_PH_MM + 184U, // DPSUB_S_D + 184U, // DPSUB_S_H + 184U, // DPSUB_S_W + 184U, // DPSUB_U_D + 184U, // DPSUB_U_H + 184U, // DPSUB_U_W + 128U, // DPSU_H_QBL + 128U, // DPSU_H_QBL_MM + 128U, // DPSU_H_QBR + 128U, // DPSU_H_QBR_MM + 128U, // DPSX_W_PH + 128U, // DPSX_W_PH_MMR2 + 128U, // DPS_W_PH + 128U, // DPS_W_PH_MMR2 + 160U, // DROTR + 152U, // DROTR32 + 128U, // DROTRV + 0U, // DSBH + 0U, // DSDIV + 0U, // DSHD + 160U, // DSLL + 152U, // DSLL32 + 1U, // DSLL64_32 + 128U, // DSLLV + 160U, // DSRA + 152U, // DSRA32 + 128U, // DSRAV + 160U, // DSRL + 152U, // DSRL32 + 128U, // DSRLV + 128U, // DSUB + 128U, // DSUBu + 0U, // DUDIV + 0U, // DVP + 0U, // DVPE + 0U, // DVPE_NM + 0U, // DVP_MMR6 + 0U, // DivRxRy16 + 0U, // DivuRxRy16 + 0U, // EHB + 0U, // EHB_MM + 0U, // EHB_MMR6 + 0U, // EHB_NM + 0U, // EI + 0U, // EI_MM + 0U, // EI_MMR6 + 0U, // EI_NM + 0U, // EMT + 0U, // EMT_NM + 0U, // ERET + 0U, // ERETNC + 0U, // ERETNC_MMR6 + 0U, // ERETNC_NM + 0U, // ERET_MM + 0U, // ERET_MMR6 + 0U, // ERET_NM + 0U, // EVP + 0U, // EVPE + 0U, // EVPE_NM + 0U, // EVP_MMR6 + 5144U, // EXT + 152U, // EXTP + 152U, // EXTPDP + 128U, // EXTPDPV + 128U, // EXTPDPV_MM + 152U, // EXTPDP_MM + 128U, // EXTPV + 128U, // EXTPV_MM + 152U, // EXTP_MM + 128U, // EXTRV_RS_W + 128U, // EXTRV_RS_W_MM + 128U, // EXTRV_R_W + 128U, // EXTRV_R_W_MM + 128U, // EXTRV_S_H + 128U, // EXTRV_S_H_MM + 128U, // EXTRV_W + 128U, // EXTRV_W_MM + 152U, // EXTR_RS_W + 152U, // EXTR_RS_W_MM + 152U, // EXTR_R_W + 152U, // EXTR_R_W_MM + 152U, // EXTR_S_H + 152U, // EXTR_S_H_MM + 152U, // EXTR_W + 152U, // EXTR_W_MM + 2072U, // EXTS + 2072U, // EXTS32 + 2048U, // EXTW_NM + 5144U, // EXT_MM + 5144U, // EXT_MMR6 + 5144U, // EXT_NM + 0U, // FABS_D32 + 0U, // FABS_D32_MM + 0U, // FABS_D64 + 0U, // FABS_D64_MM + 0U, // FABS_S + 0U, // FABS_S_MM + 128U, // FADD_D + 128U, // FADD_D32 + 128U, // FADD_D32_MM + 128U, // FADD_D64 + 128U, // FADD_D64_MM + 128U, // FADD_PS64 + 128U, // FADD_S + 128U, // FADD_S_MM + 72U, // FADD_S_MMR6 + 128U, // FADD_W + 128U, // FCAF_D + 128U, // FCAF_W + 128U, // FCEQ_D + 128U, // FCEQ_W + 0U, // FCLASS_D + 0U, // FCLASS_W + 128U, // FCLE_D + 128U, // FCLE_W + 128U, // FCLT_D + 128U, // FCLT_W + 0U, // FCMP_D32 + 0U, // FCMP_D32_MM + 0U, // FCMP_D64 + 0U, // FCMP_S32 + 0U, // FCMP_S32_MM + 128U, // FCNE_D + 128U, // FCNE_W + 128U, // FCOR_D + 128U, // FCOR_W + 128U, // FCUEQ_D + 128U, // FCUEQ_W + 128U, // FCULE_D + 128U, // FCULE_W + 128U, // FCULT_D + 128U, // FCULT_W + 128U, // FCUNE_D + 128U, // FCUNE_W + 128U, // FCUN_D + 128U, // FCUN_W + 128U, // FDIV_D + 128U, // FDIV_D32 + 128U, // FDIV_D32_MM + 128U, // FDIV_D64 + 128U, // FDIV_D64_MM + 128U, // FDIV_S + 128U, // FDIV_S_MM + 72U, // FDIV_S_MMR6 + 128U, // FDIV_W + 128U, // FEXDO_H + 128U, // FEXDO_W + 128U, // FEXP2_D + 128U, // FEXP2_W + 0U, // FEXUPL_D + 0U, // FEXUPL_W + 0U, // FEXUPR_D + 0U, // FEXUPR_W + 0U, // FFINT_S_D + 0U, // FFINT_S_W + 0U, // FFINT_U_D + 0U, // FFINT_U_W + 0U, // FFQL_D + 0U, // FFQL_W + 0U, // FFQR_D + 0U, // FFQR_W + 0U, // FILL_B + 0U, // FILL_D + 0U, // FILL_H + 0U, // FILL_W + 0U, // FLOG2_D + 0U, // FLOG2_W + 0U, // FLOOR_L_D64 + 0U, // FLOOR_L_D_MMR6 + 0U, // FLOOR_L_S + 0U, // FLOOR_L_S_MMR6 + 0U, // FLOOR_W_D32 + 0U, // FLOOR_W_D64 + 0U, // FLOOR_W_D_MMR6 + 0U, // FLOOR_W_MM + 0U, // FLOOR_W_S + 0U, // FLOOR_W_S_MM + 0U, // FLOOR_W_S_MMR6 + 184U, // FMADD_D + 184U, // FMADD_W + 128U, // FMAX_A_D + 128U, // FMAX_A_W + 128U, // FMAX_D + 128U, // FMAX_W + 128U, // FMIN_A_D + 128U, // FMIN_A_W + 128U, // FMIN_D + 128U, // FMIN_W + 0U, // FMOV_D32 + 0U, // FMOV_D32_MM + 0U, // FMOV_D64 + 0U, // FMOV_D64_MM + 0U, // FMOV_D_MMR6 + 0U, // FMOV_S + 0U, // FMOV_S_MM + 0U, // FMOV_S_MMR6 + 184U, // FMSUB_D + 184U, // FMSUB_W + 128U, // FMUL_D + 128U, // FMUL_D32 + 128U, // FMUL_D32_MM + 128U, // FMUL_D64 + 128U, // FMUL_D64_MM + 128U, // FMUL_PS64 + 128U, // FMUL_S + 128U, // FMUL_S_MM + 72U, // FMUL_S_MMR6 + 128U, // FMUL_W + 0U, // FNEG_D32 + 0U, // FNEG_D32_MM + 0U, // FNEG_D64 + 0U, // FNEG_D64_MM + 0U, // FNEG_S + 0U, // FNEG_S_MM + 0U, // FNEG_S_MMR6 + 1U, // FORK + 1U, // FORK_NM + 0U, // FRCP_D + 0U, // FRCP_W + 0U, // FRINT_D + 0U, // FRINT_W + 0U, // FRSQRT_D + 0U, // FRSQRT_W + 128U, // FSAF_D + 128U, // FSAF_W + 128U, // FSEQ_D + 128U, // FSEQ_W + 128U, // FSLE_D + 128U, // FSLE_W + 128U, // FSLT_D + 128U, // FSLT_W + 128U, // FSNE_D + 128U, // FSNE_W + 128U, // FSOR_D + 128U, // FSOR_W + 0U, // FSQRT_D + 0U, // FSQRT_D32 + 0U, // FSQRT_D32_MM + 0U, // FSQRT_D64 + 0U, // FSQRT_D64_MM + 0U, // FSQRT_S + 0U, // FSQRT_S_MM + 0U, // FSQRT_W + 128U, // FSUB_D + 128U, // FSUB_D32 + 128U, // FSUB_D32_MM + 128U, // FSUB_D64 + 128U, // FSUB_D64_MM + 128U, // FSUB_PS64 + 128U, // FSUB_S + 128U, // FSUB_S_MM + 72U, // FSUB_S_MMR6 + 128U, // FSUB_W + 128U, // FSUEQ_D + 128U, // FSUEQ_W + 128U, // FSULE_D + 128U, // FSULE_W + 128U, // FSULT_D + 128U, // FSULT_W + 128U, // FSUNE_D + 128U, // FSUNE_W + 128U, // FSUN_D + 128U, // FSUN_W + 0U, // FTINT_S_D + 0U, // FTINT_S_W + 0U, // FTINT_U_D + 0U, // FTINT_U_W + 128U, // FTQ_H + 128U, // FTQ_W + 0U, // FTRUNC_S_D + 0U, // FTRUNC_S_W + 0U, // FTRUNC_U_D + 0U, // FTRUNC_U_W + 0U, // GINVI + 0U, // GINVI_MMR6 + 0U, // GINVI_NM + 0U, // GINVT + 0U, // GINVT_MMR6 + 0U, // GINVT_NM + 128U, // HADD_S_D + 128U, // HADD_S_H + 128U, // HADD_S_W + 128U, // HADD_U_D + 128U, // HADD_U_H + 128U, // HADD_U_W + 128U, // HSUB_S_D + 128U, // HSUB_S_H + 128U, // HSUB_S_W + 128U, // HSUB_U_D + 128U, // HSUB_U_H + 128U, // HSUB_U_W + 0U, // HYPCALL + 0U, // HYPCALL_MM + 128U, // ILVEV_B + 128U, // ILVEV_D + 128U, // ILVEV_H + 128U, // ILVEV_W + 128U, // ILVL_B + 128U, // ILVL_D + 128U, // ILVL_H + 128U, // ILVL_W + 128U, // ILVOD_B + 128U, // ILVOD_D + 128U, // ILVOD_H + 128U, // ILVOD_W + 128U, // ILVR_B + 128U, // ILVR_D + 128U, // ILVR_H + 128U, // ILVR_W + 7192U, // INS + 0U, // INSERT_B + 0U, // INSERT_D + 0U, // INSERT_H + 0U, // INSERT_W + 0U, // INSV + 0U, // INSVE_B + 0U, // INSVE_D + 0U, // INSVE_H + 0U, // INSVE_W + 0U, // INSV_MM + 7192U, // INS_MM + 7192U, // INS_MMR6 + 7192U, // INS_NM + 0U, // J + 0U, // JAL + 0U, // JALR + 0U, // JALR16_MM + 0U, // JALR64 + 0U, // JALRC16_MMR6 + 0U, // JALRC16_NM + 0U, // JALRCHB_NM + 0U, // JALRC_HB_MMR6 + 0U, // JALRC_MMR6 + 0U, // JALRC_NM + 0U, // JALRS16_MM + 0U, // JALRS_MM + 0U, // JALR_HB + 0U, // JALR_HB64 + 0U, // JALR_MM + 0U, // JALS_MM + 0U, // JALX + 0U, // JALX_MM + 0U, // JAL_MM + 0U, // JIALC + 0U, // JIALC64 + 0U, // JIALC_MMR6 + 0U, // JIC + 0U, // JIC64 + 0U, // JIC_MMR6 + 0U, // JR + 0U, // JR16_MM + 0U, // JR64 + 0U, // JRADDIUSP + 0U, // JRC16_MM + 0U, // JRC16_MMR6 + 0U, // JRCADDIUSP_MMR6 + 0U, // JRC_NM + 0U, // JR_HB + 0U, // JR_HB64 + 0U, // JR_HB64_R6 + 0U, // JR_HB_R6 + 0U, // JR_MM + 0U, // J_MM + 0U, // Jal16 + 0U, // JalB16 + 0U, // JrRa16 + 0U, // JrcRa16 + 0U, // JrcRx16 + 0U, // JumpLinkReg16 + 0U, // LAPC32_NM + 0U, // LAPC48_NM + 0U, // LB + 0U, // LB16_NM + 0U, // LB64 + 0U, // LBE + 0U, // LBE_MM + 0U, // LBGP_NM + 0U, // LBU16_MM + 0U, // LBU16_NM + 0U, // LBUGP_NM + 1U, // LBUX + 1U, // LBUX_MM + 0U, // LBUX_NM + 0U, // LBU_MMR6 + 0U, // LBU_NM + 0U, // LBUs9_NM + 0U, // LBX_NM + 0U, // LB_MM + 0U, // LB_MMR6 + 0U, // LB_NM + 0U, // LBs9_NM + 0U, // LBu + 0U, // LBu64 + 0U, // LBuE + 0U, // LBuE_MM + 0U, // LBu_MM + 0U, // LD + 0U, // LDC1 + 0U, // LDC164 + 0U, // LDC1_D64_MMR6 + 0U, // LDC1_MM_D32 + 0U, // LDC1_MM_D64 + 0U, // LDC2 + 0U, // LDC2_MMR6 + 0U, // LDC2_R6 + 0U, // LDC3 + 0U, // LDI_B + 0U, // LDI_D + 0U, // LDI_H + 0U, // LDI_W + 0U, // LDL + 0U, // LDPC + 0U, // LDR + 1U, // LDXC1 + 1U, // LDXC164 + 0U, // LD_B + 0U, // LD_D + 0U, // LD_H + 0U, // LD_W + 0U, // LEA_ADDIU_NM + 0U, // LEA_ADDiu + 0U, // LEA_ADDiu64 + 0U, // LEA_ADDiu_MM + 0U, // LH + 0U, // LH16_NM + 0U, // LH64 + 0U, // LHE + 0U, // LHE_MM + 0U, // LHGP_NM + 0U, // LHU16_MM + 0U, // LHU16_NM + 0U, // LHUGP_NM + 0U, // LHUXS_NM + 0U, // LHUX_NM + 0U, // LHU_NM + 0U, // LHUs9_NM + 1U, // LHX + 0U, // LHXS_NM + 1U, // LHX_MM + 0U, // LHX_NM + 0U, // LH_MM + 0U, // LH_NM + 0U, // LHs9_NM + 0U, // LHu + 0U, // LHu64 + 0U, // LHuE + 0U, // LHuE_MM + 0U, // LHu_MM + 0U, // LI16_MM + 0U, // LI16_MMR6 + 0U, // LI16_NM + 0U, // LI48_NM + 0U, // LL + 0U, // LL64 + 0U, // LL64_R6 + 0U, // LLD + 0U, // LLD_R6 + 0U, // LLE + 0U, // LLE_MM + 76U, // LLWP_NM + 0U, // LL_MM + 0U, // LL_MMR6 + 0U, // LL_NM + 0U, // LL_R6 + 9216U, // LSA + 1U, // LSA_MMR6 + 1024U, // LSA_NM + 9216U, // LSA_R6 + 0U, // LUI_MMR6 + 0U, // LUI_NM + 1U, // LUXC1 + 1U, // LUXC164 + 1U, // LUXC1_MM + 0U, // LUi + 0U, // LUi64 + 0U, // LUi_MM + 0U, // LW + 0U, // LW16_MM + 0U, // LW16_NM + 0U, // LW4x4_NM + 0U, // LW64 + 0U, // LWC1 + 0U, // LWC1_MM + 0U, // LWC2 + 0U, // LWC2_MMR6 + 0U, // LWC2_R6 + 0U, // LWC3 + 0U, // LWDSP + 0U, // LWDSP_MM + 0U, // LWE + 0U, // LWE_MM + 0U, // LWGP16_NM + 0U, // LWGP_MM + 0U, // LWGP_NM + 0U, // LWL + 0U, // LWL64 + 0U, // LWLE + 0U, // LWLE_MM + 0U, // LWL_MM + 0U, // LWM16_MM + 0U, // LWM16_MMR6 + 0U, // LWM32_MM + 184U, // LWM_NM + 0U, // LWPC + 0U, // LWPC_MMR6 + 0U, // LWPC_NM + 0U, // LWP_MM + 0U, // LWR + 0U, // LWR64 + 0U, // LWRE + 0U, // LWRE_MM + 0U, // LWR_MM + 0U, // LWSP16_NM + 0U, // LWSP_MM + 0U, // LWUPC + 0U, // LWU_MM + 1U, // LWX + 1U, // LWXC1 + 1U, // LWXC1_MM + 0U, // LWXS16_NM + 1U, // LWXS_MM + 0U, // LWXS_NM + 1U, // LWX_MM + 0U, // LWX_NM + 0U, // LW_MM + 0U, // LW_MMR6 + 0U, // LW_NM + 0U, // LWs9_NM + 0U, // LWu + 0U, // LbRxRyOffMemX16 + 0U, // LbuRxRyOffMemX16 + 0U, // LhRxRyOffMemX16 + 0U, // LhuRxRyOffMemX16 + 1U, // LiRxImm16 + 0U, // LiRxImmAlignX16 + 0U, // LiRxImmX16 + 1U, // LwRxPcTcp16 + 0U, // LwRxPcTcpX16 + 0U, // LwRxRyOffMemX16 + 0U, // LwRxSpImmX16 + 0U, // MADD + 184U, // MADDF_D + 184U, // MADDF_D_MMR6 + 184U, // MADDF_S + 184U, // MADDF_S_MMR6 + 184U, // MADDR_Q_H + 184U, // MADDR_Q_W + 0U, // MADDU + 128U, // MADDU_DSP + 128U, // MADDU_DSP_MM + 0U, // MADDU_MM + 184U, // MADDV_B + 184U, // MADDV_D + 184U, // MADDV_H + 184U, // MADDV_W + 0U, // MADD_D32 + 0U, // MADD_D32_MM + 0U, // MADD_D64 + 128U, // MADD_DSP + 128U, // MADD_DSP_MM + 0U, // MADD_MM + 184U, // MADD_Q_H + 184U, // MADD_Q_W + 0U, // MADD_S + 0U, // MADD_S_MM + 128U, // MAQ_SA_W_PHL + 128U, // MAQ_SA_W_PHL_MM + 128U, // MAQ_SA_W_PHR + 128U, // MAQ_SA_W_PHR_MM + 128U, // MAQ_S_W_PHL + 128U, // MAQ_S_W_PHL_MM + 128U, // MAQ_S_W_PHR + 128U, // MAQ_S_W_PHR_MM + 128U, // MAXA_D + 128U, // MAXA_D_MMR6 + 128U, // MAXA_S + 128U, // MAXA_S_MMR6 + 128U, // MAXI_S_B + 128U, // MAXI_S_D + 128U, // MAXI_S_H + 128U, // MAXI_S_W + 152U, // MAXI_U_B + 152U, // MAXI_U_D + 152U, // MAXI_U_H + 152U, // MAXI_U_W + 128U, // MAX_A_B + 128U, // MAX_A_D + 128U, // MAX_A_H + 128U, // MAX_A_W + 128U, // MAX_D + 128U, // MAX_D_MMR6 + 128U, // MAX_S + 128U, // MAX_S_B + 128U, // MAX_S_D + 128U, // MAX_S_H + 128U, // MAX_S_MMR6 + 128U, // MAX_S_W + 128U, // MAX_U_B + 128U, // MAX_U_D + 128U, // MAX_U_H + 128U, // MAX_U_W + 136U, // MFC0 + 0U, // MFC0Sel_NM + 136U, // MFC0_MMR6 + 152U, // MFC0_NM + 0U, // MFC1 + 0U, // MFC1_D64 + 0U, // MFC1_MM + 0U, // MFC1_MMR6 + 136U, // MFC2 + 0U, // MFC2_MMR6 + 136U, // MFGC0 + 136U, // MFGC0_MM + 0U, // MFHC0Sel_NM + 136U, // MFHC0_MMR6 + 152U, // MFHC0_NM + 0U, // MFHC1_D32 + 0U, // MFHC1_D32_MM + 0U, // MFHC1_D64 + 0U, // MFHC1_D64_MM + 0U, // MFHC2_MMR6 + 136U, // MFHGC0 + 136U, // MFHGC0_MM + 0U, // MFHI + 0U, // MFHI16_MM + 0U, // MFHI64 + 0U, // MFHI_DSP + 0U, // MFHI_DSP_MM + 0U, // MFHI_MM + 0U, // MFLO + 0U, // MFLO16_MM + 0U, // MFLO64 + 0U, // MFLO_DSP + 0U, // MFLO_DSP_MM + 0U, // MFLO_MM + 19520U, // MFTR + 19520U, // MFTR_NM + 128U, // MINA_D + 128U, // MINA_D_MMR6 + 128U, // MINA_S + 128U, // MINA_S_MMR6 + 128U, // MINI_S_B + 128U, // MINI_S_D + 128U, // MINI_S_H + 128U, // MINI_S_W + 152U, // MINI_U_B + 152U, // MINI_U_D + 152U, // MINI_U_H + 152U, // MINI_U_W + 128U, // MIN_A_B + 128U, // MIN_A_D + 128U, // MIN_A_H + 128U, // MIN_A_W + 128U, // MIN_D + 128U, // MIN_D_MMR6 + 128U, // MIN_S + 128U, // MIN_S_B + 128U, // MIN_S_D + 128U, // MIN_S_H + 128U, // MIN_S_MMR6 + 128U, // MIN_S_W + 128U, // MIN_U_B + 128U, // MIN_U_D + 128U, // MIN_U_H + 128U, // MIN_U_W + 128U, // MOD + 128U, // MODSUB + 128U, // MODSUB_MM + 128U, // MODU + 128U, // MODU_MMR6 + 128U, // MODU_NM + 128U, // MOD_MMR6 + 128U, // MOD_NM + 128U, // MOD_S_B + 128U, // MOD_S_D + 128U, // MOD_S_H + 128U, // MOD_S_W + 128U, // MOD_U_B + 128U, // MOD_U_D + 128U, // MOD_U_H + 128U, // MOD_U_W + 0U, // MOVE16_MM + 0U, // MOVE16_MMR6 + 80U, // MOVEBALC_NM + 0U, // MOVEPREV_NM + 0U, // MOVEP_MM + 0U, // MOVEP_MMR6 + 0U, // MOVEP_NM + 0U, // MOVE_NM + 0U, // MOVE_V + 128U, // MOVF_D32 + 128U, // MOVF_D32_MM + 128U, // MOVF_D64 + 128U, // MOVF_I + 128U, // MOVF_I64 + 128U, // MOVF_I_MM + 128U, // MOVF_S + 128U, // MOVF_S_MM + 128U, // MOVN_I64_D64 + 128U, // MOVN_I64_I + 128U, // MOVN_I64_I64 + 128U, // MOVN_I64_S + 128U, // MOVN_I_D32 + 128U, // MOVN_I_D32_MM + 128U, // MOVN_I_D64 + 128U, // MOVN_I_I + 128U, // MOVN_I_I64 + 128U, // MOVN_I_MM + 128U, // MOVN_I_S + 128U, // MOVN_I_S_MM + 128U, // MOVN_NM + 128U, // MOVT_D32 + 128U, // MOVT_D32_MM + 128U, // MOVT_D64 + 128U, // MOVT_I + 128U, // MOVT_I64 + 128U, // MOVT_I_MM + 128U, // MOVT_S + 128U, // MOVT_S_MM + 128U, // MOVZ_I64_D64 + 128U, // MOVZ_I64_I + 128U, // MOVZ_I64_I64 + 128U, // MOVZ_I64_S + 128U, // MOVZ_I_D32 + 128U, // MOVZ_I_D32_MM + 128U, // MOVZ_I_D64 + 128U, // MOVZ_I_I + 128U, // MOVZ_I_I64 + 128U, // MOVZ_I_MM + 128U, // MOVZ_I_S + 128U, // MOVZ_I_S_MM + 128U, // MOVZ_NM + 0U, // MSUB + 184U, // MSUBF_D + 184U, // MSUBF_D_MMR6 + 184U, // MSUBF_S + 184U, // MSUBF_S_MMR6 + 184U, // MSUBR_Q_H + 184U, // MSUBR_Q_W + 0U, // MSUBU + 128U, // MSUBU_DSP + 128U, // MSUBU_DSP_MM + 0U, // MSUBU_MM + 184U, // MSUBV_B + 184U, // MSUBV_D + 184U, // MSUBV_H + 184U, // MSUBV_W + 0U, // MSUB_D32 + 0U, // MSUB_D32_MM + 0U, // MSUB_D64 + 128U, // MSUB_DSP + 128U, // MSUB_DSP_MM + 0U, // MSUB_MM + 184U, // MSUB_Q_H + 184U, // MSUB_Q_W + 0U, // MSUB_S + 0U, // MSUB_S_MM + 0U, // MTC0 + 0U, // MTC0Sel_NM + 0U, // MTC0_MMR6 + 152U, // MTC0_NM + 0U, // MTC1 + 0U, // MTC1_D64 + 0U, // MTC1_D64_MM + 0U, // MTC1_MM + 0U, // MTC1_MMR6 + 0U, // MTC2 + 0U, // MTC2_MMR6 + 0U, // MTGC0 + 0U, // MTGC0_MM + 0U, // MTHC0Sel_NM + 0U, // MTHC0_MMR6 + 152U, // MTHC0_NM + 0U, // MTHC1_D32 + 0U, // MTHC1_D32_MM + 0U, // MTHC1_D64 + 0U, // MTHC1_D64_MM + 0U, // MTHC2_MMR6 + 0U, // MTHGC0 + 0U, // MTHGC0_MM + 0U, // MTHI + 0U, // MTHI64 + 0U, // MTHI_DSP + 0U, // MTHI_DSP_MM + 0U, // MTHI_MM + 0U, // MTHLIP + 0U, // MTHLIP_MM + 0U, // MTLO + 0U, // MTLO64 + 0U, // MTLO_DSP + 0U, // MTLO_DSP_MM + 0U, // MTLO_MM + 0U, // MTM0 + 0U, // MTM1 + 0U, // MTM2 + 0U, // MTP0 + 0U, // MTP1 + 0U, // MTP2 + 2U, // MTTR + 2U, // MTTR_NM + 128U, // MUH + 128U, // MUHU + 128U, // MUHU_MMR6 + 128U, // MUHU_NM + 128U, // MUH_MMR6 + 128U, // MUH_NM + 128U, // MUL + 128U, // MUL4x4_NM + 128U, // MULEQ_S_W_PHL + 128U, // MULEQ_S_W_PHL_MM + 128U, // MULEQ_S_W_PHR + 128U, // MULEQ_S_W_PHR_MM + 128U, // MULEU_S_PH_QBL + 128U, // MULEU_S_PH_QBL_MM + 128U, // MULEU_S_PH_QBR + 128U, // MULEU_S_PH_QBR_MM + 128U, // MULQ_RS_PH + 128U, // MULQ_RS_PH_MM + 128U, // MULQ_RS_W + 128U, // MULQ_RS_W_MMR2 + 128U, // MULQ_S_PH + 128U, // MULQ_S_PH_MMR2 + 128U, // MULQ_S_W + 128U, // MULQ_S_W_MMR2 + 128U, // MULR_PS64 + 128U, // MULR_Q_H + 128U, // MULR_Q_W + 128U, // MULSAQ_S_W_PH + 128U, // MULSAQ_S_W_PH_MM + 128U, // MULSA_W_PH + 128U, // MULSA_W_PH_MMR2 + 0U, // MULT + 128U, // MULTU_DSP + 128U, // MULTU_DSP_MM + 128U, // MULT_DSP + 128U, // MULT_DSP_MM + 0U, // MULT_MM + 0U, // MULTu + 0U, // MULTu_MM + 128U, // MULU + 128U, // MULU_MMR6 + 128U, // MULU_NM + 128U, // MULV_B + 128U, // MULV_D + 128U, // MULV_H + 128U, // MULV_W + 128U, // MUL_MM + 128U, // MUL_MMR6 + 128U, // MUL_NM + 128U, // MUL_PH + 128U, // MUL_PH_MMR2 + 128U, // MUL_Q_H + 128U, // MUL_Q_W + 128U, // MUL_R6 + 128U, // MUL_S_PH + 128U, // MUL_S_PH_MMR2 + 0U, // Mfhi16 + 0U, // Mflo16 + 0U, // Move32R16 + 0U, // MoveR3216 + 0U, // NLOC_B + 0U, // NLOC_D + 0U, // NLOC_H + 0U, // NLOC_W + 0U, // NLZC_B + 0U, // NLZC_D + 0U, // NLZC_H + 0U, // NLZC_W + 0U, // NMADD_D32 + 0U, // NMADD_D32_MM + 0U, // NMADD_D64 + 0U, // NMADD_S + 0U, // NMADD_S_MM + 0U, // NMSUB_D32 + 0U, // NMSUB_D32_MM + 0U, // NMSUB_D64 + 0U, // NMSUB_S + 0U, // NMSUB_S_MM + 0U, // NOP32_NM + 0U, // NOP_NM + 128U, // NOR + 128U, // NOR64 + 20U, // NORI_B + 128U, // NOR_MM + 128U, // NOR_MMR6 + 128U, // NOR_NM + 128U, // NOR_V + 0U, // NOT16_MM + 0U, // NOT16_MMR6 + 0U, // NOT16_NM + 0U, // NegRxRy16 + 0U, // NotRxRy16 + 128U, // OR + 0U, // OR16_MM + 0U, // OR16_MMR6 + 128U, // OR16_NM + 128U, // OR64 + 20U, // ORI_B + 16U, // ORI_MMR6 + 128U, // ORI_NM + 128U, // OR_MM + 128U, // OR_MMR6 + 128U, // OR_NM + 128U, // OR_V + 16U, // ORi + 16U, // ORi64 + 16U, // ORi_MM + 0U, // OrRxRxRy16 + 128U, // PACKRL_PH + 128U, // PACKRL_PH_MM + 0U, // PAUSE + 0U, // PAUSE_MM + 0U, // PAUSE_MMR6 + 0U, // PAUSE_NM + 128U, // PCKEV_B + 128U, // PCKEV_D + 128U, // PCKEV_H + 128U, // PCKEV_W + 128U, // PCKOD_B + 128U, // PCKOD_D + 128U, // PCKOD_H + 128U, // PCKOD_W + 0U, // PCNT_B + 0U, // PCNT_D + 0U, // PCNT_H + 0U, // PCNT_W + 128U, // PICK_PH + 128U, // PICK_PH_MM + 128U, // PICK_QB + 128U, // PICK_QB_MM + 128U, // PLL_PS64 + 128U, // PLU_PS64 + 0U, // POP + 0U, // PRECEQU_PH_QBL + 0U, // PRECEQU_PH_QBLA + 0U, // PRECEQU_PH_QBLA_MM + 0U, // PRECEQU_PH_QBL_MM + 0U, // PRECEQU_PH_QBR + 0U, // PRECEQU_PH_QBRA + 0U, // PRECEQU_PH_QBRA_MM + 0U, // PRECEQU_PH_QBR_MM + 0U, // PRECEQ_W_PHL + 0U, // PRECEQ_W_PHL_MM + 0U, // PRECEQ_W_PHR + 0U, // PRECEQ_W_PHR_MM + 0U, // PRECEU_PH_QBL + 0U, // PRECEU_PH_QBLA + 0U, // PRECEU_PH_QBLA_MM + 0U, // PRECEU_PH_QBL_MM + 0U, // PRECEU_PH_QBR + 0U, // PRECEU_PH_QBRA + 0U, // PRECEU_PH_QBRA_MM + 0U, // PRECEU_PH_QBR_MM + 128U, // PRECRQU_S_QB_PH + 128U, // PRECRQU_S_QB_PH_MM + 128U, // PRECRQ_PH_W + 128U, // PRECRQ_PH_W_MM + 128U, // PRECRQ_QB_PH + 128U, // PRECRQ_QB_PH_MM + 128U, // PRECRQ_RS_PH_W + 128U, // PRECRQ_RS_PH_W_MM + 128U, // PRECR_QB_PH + 128U, // PRECR_QB_PH_MMR2 + 152U, // PRECR_SRA_PH_W + 152U, // PRECR_SRA_PH_W_MMR2 + 152U, // PRECR_SRA_R_PH_W + 152U, // PRECR_SRA_R_PH_W_MMR2 + 0U, // PREF + 0U, // PREFE + 0U, // PREFE_MM + 0U, // PREFX_MM + 0U, // PREF_MM + 0U, // PREF_MMR6 + 0U, // PREF_NM + 0U, // PREF_R6 + 0U, // PREFs9_NM + 152U, // PREPEND + 152U, // PREPEND_MMR2 + 128U, // PUL_PS64 + 128U, // PUU_PS64 + 0U, // RADDU_W_QB + 0U, // RADDU_W_QB_MM + 0U, // RDDSP + 0U, // RDDSP_MM + 20U, // RDHWR + 20U, // RDHWR64 + 20U, // RDHWR_MM + 136U, // RDHWR_MMR6 + 152U, // RDHWR_NM + 0U, // RDPGPR_MMR6 + 0U, // RDPGPR_NM + 0U, // RECIP_D32 + 0U, // RECIP_D32_MM + 0U, // RECIP_D64 + 0U, // RECIP_D64_MM + 0U, // RECIP_S + 0U, // RECIP_S_MM + 0U, // REPLV_PH + 0U, // REPLV_PH_MM + 0U, // REPLV_QB + 0U, // REPLV_QB_MM + 0U, // REPL_PH + 0U, // REPL_PH_MM + 0U, // REPL_QB + 0U, // REPL_QB_MM + 0U, // RESTOREJRC16_NM + 0U, // RESTOREJRC_NM + 0U, // RESTORE_NM + 0U, // RINT_D + 0U, // RINT_D_MMR6 + 0U, // RINT_S + 0U, // RINT_S_MMR6 + 152U, // ROTR + 128U, // ROTRV + 128U, // ROTRV_MM + 128U, // ROTRV_NM + 152U, // ROTR_MM + 152U, // ROTR_NM + 18456U, // ROTX_NM + 0U, // ROUND_L_D64 + 0U, // ROUND_L_D_MMR6 + 0U, // ROUND_L_S + 0U, // ROUND_L_S_MMR6 + 0U, // ROUND_W_D32 + 0U, // ROUND_W_D64 + 0U, // ROUND_W_D_MMR6 + 0U, // ROUND_W_MM + 0U, // ROUND_W_S + 0U, // ROUND_W_S_MM + 0U, // ROUND_W_S_MMR6 + 0U, // RSQRT_D32 + 0U, // RSQRT_D32_MM + 0U, // RSQRT_D64 + 0U, // RSQRT_D64_MM + 0U, // RSQRT_S + 0U, // RSQRT_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 0U, // SAA + 0U, // SAAD + 136U, // SAT_S_B + 160U, // SAT_S_D + 164U, // SAT_S_H + 152U, // SAT_S_W + 136U, // SAT_U_B + 160U, // SAT_U_D + 164U, // SAT_U_H + 152U, // SAT_U_W + 0U, // SAVE16_NM + 0U, // SAVE_NM + 0U, // SB + 0U, // SB16_MM + 0U, // SB16_MMR6 + 0U, // SB16_NM + 0U, // SB64 + 0U, // SBE + 0U, // SBE_MM + 0U, // SBGP_NM + 0U, // SBX_NM + 0U, // SB_MM + 0U, // SB_MMR6 + 0U, // SB_NM + 0U, // SBs9_NM + 0U, // SC + 0U, // SC64 + 0U, // SC64_R6 + 0U, // SCD + 0U, // SCD_R6 + 0U, // SCE + 0U, // SCE_MM + 2U, // SCWP_NM + 0U, // SC_MM + 0U, // SC_MMR6 + 0U, // SC_NM + 0U, // SC_R6 + 0U, // SD + 0U, // SDBBP + 0U, // SDBBP16_MM + 0U, // SDBBP16_MMR6 + 0U, // SDBBP16_NM + 0U, // SDBBP_MM + 0U, // SDBBP_MMR6 + 0U, // SDBBP_NM + 0U, // SDBBP_R6 + 0U, // SDC1 + 0U, // SDC164 + 0U, // SDC1_D64_MMR6 + 0U, // SDC1_MM_D32 + 0U, // SDC1_MM_D64 + 0U, // SDC2 + 0U, // SDC2_MMR6 + 0U, // SDC2_R6 + 0U, // SDC3 + 0U, // SDIV + 0U, // SDIV_MM + 0U, // SDL + 0U, // SDR + 1U, // SDXC1 + 1U, // SDXC164 + 0U, // SEB + 0U, // SEB64 + 0U, // SEB_MM + 0U, // SEB_NM + 0U, // SEH + 0U, // SEH64 + 0U, // SEH_MM + 0U, // SEH_NM + 128U, // SELEQZ + 128U, // SELEQZ64 + 128U, // SELEQZ_D + 128U, // SELEQZ_D_MMR6 + 128U, // SELEQZ_MMR6 + 128U, // SELEQZ_S + 128U, // SELEQZ_S_MMR6 + 128U, // SELNEZ + 128U, // SELNEZ64 + 128U, // SELNEZ_D + 128U, // SELNEZ_D_MMR6 + 128U, // SELNEZ_MMR6 + 128U, // SELNEZ_S + 128U, // SELNEZ_S_MMR6 + 184U, // SEL_D + 184U, // SEL_D_MMR6 + 184U, // SEL_S + 184U, // SEL_S_MMR6 + 128U, // SEQ + 128U, // SEQI_NM + 128U, // SEQi + 0U, // SH + 0U, // SH16_MM + 0U, // SH16_MMR6 + 0U, // SH16_NM + 0U, // SH64 + 0U, // SHE + 0U, // SHE_MM + 20U, // SHF_B + 20U, // SHF_H + 20U, // SHF_W + 0U, // SHGP_NM + 0U, // SHILO + 0U, // SHILOV + 0U, // SHILOV_MM + 0U, // SHILO_MM + 128U, // SHLLV_PH + 128U, // SHLLV_PH_MM + 128U, // SHLLV_QB + 128U, // SHLLV_QB_MM + 128U, // SHLLV_S_PH + 128U, // SHLLV_S_PH_MM + 128U, // SHLLV_S_W + 128U, // SHLLV_S_W_MM + 164U, // SHLL_PH + 164U, // SHLL_PH_MM + 136U, // SHLL_QB + 136U, // SHLL_QB_MM + 164U, // SHLL_S_PH + 164U, // SHLL_S_PH_MM + 152U, // SHLL_S_W + 152U, // SHLL_S_W_MM + 128U, // SHRAV_PH + 128U, // SHRAV_PH_MM + 128U, // SHRAV_QB + 128U, // SHRAV_QB_MMR2 + 128U, // SHRAV_R_PH + 128U, // SHRAV_R_PH_MM + 128U, // SHRAV_R_QB + 128U, // SHRAV_R_QB_MMR2 + 128U, // SHRAV_R_W + 128U, // SHRAV_R_W_MM + 164U, // SHRA_PH + 164U, // SHRA_PH_MM + 136U, // SHRA_QB + 136U, // SHRA_QB_MMR2 + 164U, // SHRA_R_PH + 164U, // SHRA_R_PH_MM + 136U, // SHRA_R_QB + 136U, // SHRA_R_QB_MMR2 + 152U, // SHRA_R_W + 152U, // SHRA_R_W_MM + 128U, // SHRLV_PH + 128U, // SHRLV_PH_MMR2 + 128U, // SHRLV_QB + 128U, // SHRLV_QB_MM + 164U, // SHRL_PH + 164U, // SHRL_PH_MMR2 + 136U, // SHRL_QB + 136U, // SHRL_QB_MM + 0U, // SHXS_NM + 0U, // SHX_NM + 0U, // SH_MM + 0U, // SH_MMR6 + 0U, // SH_NM + 0U, // SHs9_NM + 0U, // SIGRIE + 0U, // SIGRIE_MMR6 + 0U, // SIGRIE_NM + 305U, // SLDI_B + 85U, // SLDI_D + 297U, // SLDI_H + 89U, // SLDI_W + 313U, // SLD_B + 313U, // SLD_D + 313U, // SLD_H + 313U, // SLD_W + 152U, // SLL + 128U, // SLL16_MM + 128U, // SLL16_MMR6 + 164U, // SLL16_NM + 2U, // SLL64_32 + 2U, // SLL64_64 + 136U, // SLLI_B + 160U, // SLLI_D + 164U, // SLLI_H + 152U, // SLLI_W + 128U, // SLLV + 128U, // SLLV_MM + 128U, // SLLV_NM + 128U, // SLL_B + 128U, // SLL_D + 128U, // SLL_H + 152U, // SLL_MM + 152U, // SLL_MMR6 + 152U, // SLL_NM + 128U, // SLL_W + 128U, // SLT + 128U, // SLT64 + 128U, // SLTIU_NM + 128U, // SLTI_NM + 128U, // SLTU_NM + 128U, // SLT_MM + 128U, // SLT_NM + 128U, // SLTi + 128U, // SLTi64 + 128U, // SLTi_MM + 128U, // SLTiu + 128U, // SLTiu64 + 128U, // SLTiu_MM + 128U, // SLTu + 128U, // SLTu64 + 128U, // SLTu_MM + 128U, // SNE + 128U, // SNEi + 128U, // SOV_NM + 293U, // SPLATI_B + 321U, // SPLATI_D + 265U, // SPLATI_H + 285U, // SPLATI_W + 257U, // SPLAT_B + 257U, // SPLAT_D + 257U, // SPLAT_H + 257U, // SPLAT_W + 152U, // SRA + 136U, // SRAI_B + 160U, // SRAI_D + 164U, // SRAI_H + 152U, // SRAI_W + 136U, // SRARI_B + 160U, // SRARI_D + 164U, // SRARI_H + 152U, // SRARI_W + 128U, // SRAR_B + 128U, // SRAR_D + 128U, // SRAR_H + 128U, // SRAR_W + 128U, // SRAV + 128U, // SRAV_MM + 128U, // SRAV_NM + 128U, // SRA_B + 128U, // SRA_D + 128U, // SRA_H + 152U, // SRA_MM + 152U, // SRA_NM + 128U, // SRA_W + 152U, // SRL + 128U, // SRL16_MM + 128U, // SRL16_MMR6 + 164U, // SRL16_NM + 136U, // SRLI_B + 160U, // SRLI_D + 164U, // SRLI_H + 152U, // SRLI_W + 136U, // SRLRI_B + 160U, // SRLRI_D + 164U, // SRLRI_H + 152U, // SRLRI_W + 128U, // SRLR_B + 128U, // SRLR_D + 128U, // SRLR_H + 128U, // SRLR_W + 128U, // SRLV + 128U, // SRLV_MM + 128U, // SRLV_NM + 128U, // SRL_B + 128U, // SRL_D + 128U, // SRL_H + 152U, // SRL_MM + 152U, // SRL_NM + 128U, // SRL_W + 0U, // SSNOP + 0U, // SSNOP_MM + 0U, // SSNOP_MMR6 + 0U, // ST_B + 0U, // ST_D + 0U, // ST_H + 0U, // ST_W + 128U, // SUB + 128U, // SUBQH_PH + 128U, // SUBQH_PH_MMR2 + 128U, // SUBQH_R_PH + 128U, // SUBQH_R_PH_MMR2 + 128U, // SUBQH_R_W + 128U, // SUBQH_R_W_MMR2 + 128U, // SUBQH_W + 128U, // SUBQH_W_MMR2 + 128U, // SUBQ_PH + 128U, // SUBQ_PH_MM + 128U, // SUBQ_S_PH + 128U, // SUBQ_S_PH_MM + 128U, // SUBQ_S_W + 128U, // SUBQ_S_W_MM + 128U, // SUBSUS_U_B + 128U, // SUBSUS_U_D + 128U, // SUBSUS_U_H + 128U, // SUBSUS_U_W + 128U, // SUBSUU_S_B + 128U, // SUBSUU_S_D + 128U, // SUBSUU_S_H + 128U, // SUBSUU_S_W + 128U, // SUBS_S_B + 128U, // SUBS_S_D + 128U, // SUBS_S_H + 128U, // SUBS_S_W + 128U, // SUBS_U_B + 128U, // SUBS_U_D + 128U, // SUBS_U_H + 128U, // SUBS_U_W + 128U, // SUBU16_MM + 128U, // SUBU16_MMR6 + 128U, // SUBUH_QB + 128U, // SUBUH_QB_MMR2 + 128U, // SUBUH_R_QB + 128U, // SUBUH_R_QB_MMR2 + 128U, // SUBU_MMR6 + 128U, // SUBU_PH + 128U, // SUBU_PH_MMR2 + 128U, // SUBU_QB + 128U, // SUBU_QB_MM + 128U, // SUBU_S_PH + 128U, // SUBU_S_PH_MMR2 + 128U, // SUBU_S_QB + 128U, // SUBU_S_QB_MM + 152U, // SUBVI_B + 152U, // SUBVI_D + 152U, // SUBVI_H + 152U, // SUBVI_W + 128U, // SUBV_B + 128U, // SUBV_D + 128U, // SUBV_H + 128U, // SUBV_W + 128U, // SUB_MM + 128U, // SUB_MMR6 + 128U, // SUB_NM + 128U, // SUBu + 128U, // SUBu16_NM + 128U, // SUBu_MM + 128U, // SUBu_NM + 1U, // SUXC1 + 1U, // SUXC164 + 1U, // SUXC1_MM + 0U, // SW + 0U, // SW16_MM + 0U, // SW16_MMR6 + 0U, // SW16_NM + 0U, // SW4x4_NM + 0U, // SW64 + 0U, // SWC1 + 0U, // SWC1_MM + 0U, // SWC2 + 0U, // SWC2_MMR6 + 0U, // SWC2_R6 + 0U, // SWC3 + 0U, // SWDSP + 0U, // SWDSP_MM + 0U, // SWE + 0U, // SWE_MM + 0U, // SWGP16_NM + 0U, // SWGP_NM + 0U, // SWL + 0U, // SWL64 + 0U, // SWLE + 0U, // SWLE_MM + 0U, // SWL_MM + 0U, // SWM16_MM + 0U, // SWM16_MMR6 + 0U, // SWM32_MM + 184U, // SWM_NM + 0U, // SWPC_NM + 0U, // SWP_MM + 0U, // SWR + 0U, // SWR64 + 0U, // SWRE + 0U, // SWRE_MM + 0U, // SWR_MM + 0U, // SWSP16_NM + 0U, // SWSP_MM + 0U, // SWSP_MMR6 + 1U, // SWXC1 + 1U, // SWXC1_MM + 0U, // SWXS_NM + 0U, // SWX_NM + 0U, // SW_MM + 0U, // SW_MMR6 + 0U, // SW_NM + 0U, // SWs9_NM + 0U, // SYNC + 0U, // SYNCI + 0U, // SYNCI_MM + 0U, // SYNCI_MMR6 + 0U, // SYNCI_NM + 0U, // SYNCIs9_NM + 0U, // SYNC_MM + 0U, // SYNC_MMR6 + 0U, // SYNC_NM + 0U, // SYSCALL + 0U, // SYSCALL16_NM + 0U, // SYSCALL_MM + 0U, // SYSCALL_NM + 0U, // Save16 + 0U, // SaveX16 + 0U, // SbRxRyOffMemX16 + 0U, // SebRx16 + 0U, // SehRx16 + 0U, // ShRxRyOffMemX16 + 152U, // SllX16 + 0U, // SllvRxRy16 + 0U, // SltRxRy16 + 1U, // SltiRxImm16 + 0U, // SltiRxImmX16 + 1U, // SltiuRxImm16 + 0U, // SltiuRxImmX16 + 0U, // SltuRxRy16 + 152U, // SraX16 0U, // SravRxRy16 - 1U, // SrlX16 + 152U, // SrlX16 0U, // SrlvRxRy16 - 0U, // SubuRxRyRz16 + 128U, // SubuRxRyRz16 0U, // SwRxRyOffMemX16 0U, // SwRxSpImmX16 - 0U, // TAILCALL - 0U, // TAILCALL64_R - 0U, // TAILCALL_R - 1U, // TEQ + 92U, // TEQ 0U, // TEQI 0U, // TEQI_MM - 1U, // TEQ_MM - 1U, // TGE + 164U, // TEQ_MM + 152U, // TEQ_NM + 92U, // TGE 0U, // TGEI 0U, // TGEIU 0U, // TGEIU_MM 0U, // TGEI_MM - 1U, // TGEU - 1U, // TGEU_MM - 1U, // TGE_MM + 92U, // TGEU + 164U, // TGEU_MM + 164U, // TGE_MM + 0U, // TLBGINV + 0U, // TLBGINVF + 0U, // TLBGINVF_MM + 0U, // TLBGINV_MM + 0U, // TLBGP + 0U, // TLBGP_MM + 0U, // TLBGR + 0U, // TLBGR_MM + 0U, // TLBGWI + 0U, // TLBGWI_MM + 0U, // TLBGWR + 0U, // TLBGWR_MM + 0U, // TLBINV + 0U, // TLBINVF + 0U, // TLBINVF_MMR6 + 0U, // TLBINVF_NM + 0U, // TLBINV_MMR6 + 0U, // TLBINV_NM 0U, // TLBP 0U, // TLBP_MM + 0U, // TLBP_NM 0U, // TLBR 0U, // TLBR_MM + 0U, // TLBR_NM 0U, // TLBWI 0U, // TLBWI_MM + 0U, // TLBWI_NM 0U, // TLBWR 0U, // TLBWR_MM - 1U, // TLT + 0U, // TLBWR_NM + 92U, // TLT 0U, // TLTI 0U, // TLTIU_MM 0U, // TLTI_MM - 1U, // TLTU - 1U, // TLTU_MM - 1U, // TLT_MM - 1U, // TNE + 92U, // TLTU + 164U, // TLTU_MM + 164U, // TLT_MM + 92U, // TNE 0U, // TNEI 0U, // TNEI_MM - 1U, // TNE_MM - 0U, // TRAP + 164U, // TNE_MM + 152U, // TNE_NM 0U, // TRUNC_L_D64 + 0U, // TRUNC_L_D_MMR6 0U, // TRUNC_L_S + 0U, // TRUNC_L_S_MMR6 0U, // TRUNC_W_D32 0U, // TRUNC_W_D64 + 0U, // TRUNC_W_D_MMR6 0U, // TRUNC_W_MM 0U, // TRUNC_W_S 0U, // TRUNC_W_S_MM + 0U, // TRUNC_W_S_MMR6 0U, // TTLTIU + 0U, // UALH_NM + 184U, // UALWM_NM + 0U, // UALW_NM + 0U, // UASH_NM + 184U, // UASWM_NM + 0U, // UASW_NM 0U, // UDIV 0U, // UDIV_MM - 0U, // V3MULU - 0U, // VMM0 - 0U, // VMULU - 2U, // VSHF_B - 2U, // VSHF_D - 2U, // VSHF_H - 2U, // VSHF_W + 128U, // V3MULU + 128U, // VMM0 + 128U, // VMULU + 184U, // VSHF_B + 184U, // VSHF_D + 184U, // VSHF_H + 184U, // VSHF_W 0U, // WAIT 0U, // WAIT_MM + 0U, // WAIT_MMR6 + 0U, // WAIT_NM 0U, // WRDSP + 0U, // WRDSP_MM + 0U, // WRPGPR_MMR6 + 0U, // WRPGPR_NM 0U, // WSBH 0U, // WSBH_MM - 0U, // XOR + 0U, // WSBH_MMR6 + 128U, // XOR 0U, // XOR16_MM - 0U, // XOR64 - 0U, // XORI_B - 0U, // XOR_MM - 0U, // XOR_V - 0U, // XOR_V_D_PSEUDO - 0U, // XOR_V_H_PSEUDO - 0U, // XOR_V_W_PSEUDO - 1U, // XORi - 1U, // XORi64 - 1U, // XORi_MM + 0U, // XOR16_MMR6 + 128U, // XOR16_NM + 128U, // XOR64 + 20U, // XORI_B + 16U, // XORI_MMR6 + 128U, // XORI_NM + 128U, // XOR_MM + 128U, // XOR_MMR6 + 128U, // XOR_NM + 128U, // XOR_V + 16U, // XORi + 16U, // XORi64 + 16U, // XORi_MM 0U, // XorRxRxRy16 - 0U + 0U, // YIELD + 0U, // YIELD_NM }; -#ifndef CAPSTONE_DIET - static const char AsmStrs[] = { - /* 0 */ 'j', 'a', 'l', 'r', 'c', 32, 9, 0, - /* 8 */ 'd', 'm', 'f', 'c', '0', 9, 0, - /* 15 */ 'd', 'm', 't', 'c', '0', 9, 0, - /* 22 */ 'v', 'm', 'm', '0', 9, 0, - /* 28 */ 'm', 't', 'm', '0', 9, 0, - /* 34 */ 'm', 't', 'p', '0', 9, 0, - /* 40 */ 'b', 'b', 'i', 't', '0', 9, 0, - /* 47 */ 'l', 'd', 'c', '1', 9, 0, - /* 53 */ 's', 'd', 'c', '1', 9, 0, - /* 59 */ 'c', 'f', 'c', '1', 9, 0, - /* 65 */ 'd', 'm', 'f', 'c', '1', 9, 0, - /* 72 */ 'm', 'f', 'h', 'c', '1', 9, 0, - /* 79 */ 'm', 't', 'h', 'c', '1', 9, 0, - /* 86 */ 'c', 't', 'c', '1', 9, 0, - /* 92 */ 'd', 'm', 't', 'c', '1', 9, 0, - /* 99 */ 'l', 'w', 'c', '1', 9, 0, - /* 105 */ 's', 'w', 'c', '1', 9, 0, - /* 111 */ 'l', 'd', 'x', 'c', '1', 9, 0, - /* 118 */ 's', 'd', 'x', 'c', '1', 9, 0, - /* 125 */ 'l', 'u', 'x', 'c', '1', 9, 0, - /* 132 */ 's', 'u', 'x', 'c', '1', 9, 0, - /* 139 */ 'l', 'w', 'x', 'c', '1', 9, 0, - /* 146 */ 's', 'w', 'x', 'c', '1', 9, 0, - /* 153 */ 'm', 't', 'm', '1', 9, 0, - /* 159 */ 'm', 't', 'p', '1', 9, 0, - /* 165 */ 'b', 'b', 'i', 't', '1', 9, 0, - /* 172 */ 'b', 'b', 'i', 't', '0', '3', '2', 9, 0, - /* 181 */ 'b', 'b', 'i', 't', '1', '3', '2', 9, 0, - /* 190 */ 'd', 's', 'r', 'a', '3', '2', 9, 0, - /* 198 */ 'b', 'p', 'o', 's', 'g', 'e', '3', '2', 9, 0, - /* 208 */ 'd', 's', 'l', 'l', '3', '2', 9, 0, - /* 216 */ 'd', 's', 'r', 'l', '3', '2', 9, 0, - /* 224 */ 'l', 'w', 'm', '3', '2', 9, 0, - /* 231 */ 's', 'w', 'm', '3', '2', 9, 0, - /* 238 */ 'd', 'r', 'o', 't', 'r', '3', '2', 9, 0, - /* 247 */ 'l', 'd', 'c', '2', 9, 0, - /* 253 */ 's', 'd', 'c', '2', 9, 0, - /* 259 */ 'd', 'm', 'f', 'c', '2', 9, 0, - /* 266 */ 'd', 'm', 't', 'c', '2', 9, 0, - /* 273 */ 'l', 'w', 'c', '2', 9, 0, - /* 279 */ 's', 'w', 'c', '2', 9, 0, - /* 285 */ 'm', 't', 'm', '2', 9, 0, - /* 291 */ 'm', 't', 'p', '2', 9, 0, - /* 297 */ 'a', 'd', 'd', 'i', 'u', 'r', '2', 9, 0, - /* 306 */ 'l', 'd', 'c', '3', 9, 0, - /* 312 */ 's', 'd', 'c', '3', 9, 0, - /* 318 */ 'l', 'w', 'c', '3', 9, 0, - /* 324 */ 's', 'w', 'c', '3', 9, 0, - /* 330 */ 'a', 'd', 'd', 'i', 'u', 's', '5', 9, 0, - /* 339 */ 's', 'b', '1', '6', 9, 0, - /* 345 */ 'a', 'n', 'd', '1', '6', 9, 0, - /* 352 */ 's', 'h', '1', '6', 9, 0, - /* 358 */ 'a', 'n', 'd', 'i', '1', '6', 9, 0, - /* 366 */ 'l', 'i', '1', '6', 9, 0, - /* 372 */ 'b', 'r', 'e', 'a', 'k', '1', '6', 9, 0, - /* 381 */ 's', 'l', 'l', '1', '6', 9, 0, - /* 388 */ 's', 'r', 'l', '1', '6', 9, 0, - /* 395 */ 'l', 'w', 'm', '1', '6', 9, 0, - /* 402 */ 's', 'w', 'm', '1', '6', 9, 0, - /* 409 */ 's', 'd', 'b', 'b', 'p', '1', '6', 9, 0, - /* 418 */ 'j', 'r', '1', '6', 9, 0, - /* 424 */ 'x', 'o', 'r', '1', '6', 9, 0, - /* 431 */ 'j', 'a', 'l', 'r', 's', '1', '6', 9, 0, - /* 440 */ 'n', 'o', 't', '1', '6', 9, 0, - /* 447 */ 'l', 'b', 'u', '1', '6', 9, 0, - /* 454 */ 's', 'u', 'b', 'u', '1', '6', 9, 0, - /* 462 */ 'a', 'd', 'd', 'u', '1', '6', 9, 0, - /* 470 */ 'l', 'h', 'u', '1', '6', 9, 0, - /* 477 */ 'l', 'w', '1', '6', 9, 0, - /* 483 */ 's', 'w', '1', '6', 9, 0, - /* 489 */ 'b', 'n', 'e', 'z', '1', '6', 9, 0, - /* 497 */ 'b', 'e', 'q', 'z', '1', '6', 9, 0, - /* 505 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, - /* 521 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, - /* 538 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, - /* 554 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, - /* 571 */ 'd', 's', 'r', 'a', 9, 0, - /* 577 */ 'd', 'l', 's', 'a', 9, 0, - /* 583 */ 'c', 'f', 'c', 'm', 's', 'a', 9, 0, - /* 591 */ 'c', 't', 'c', 'm', 's', 'a', 9, 0, - /* 599 */ 'a', 'd', 'd', '_', 'a', '.', 'b', 9, 0, - /* 608 */ 'm', 'i', 'n', '_', 'a', '.', 'b', 9, 0, - /* 617 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'b', 9, 0, - /* 627 */ 'm', 'a', 'x', '_', 'a', '.', 'b', 9, 0, - /* 636 */ 's', 'r', 'a', '.', 'b', 9, 0, - /* 643 */ 'n', 'l', 'o', 'c', '.', 'b', 9, 0, - /* 651 */ 'n', 'l', 'z', 'c', '.', 'b', 9, 0, - /* 659 */ 's', 'l', 'd', '.', 'b', 9, 0, - /* 666 */ 'p', 'c', 'k', 'o', 'd', '.', 'b', 9, 0, - /* 675 */ 'i', 'l', 'v', 'o', 'd', '.', 'b', 9, 0, - /* 684 */ 'i', 'n', 's', 'v', 'e', '.', 'b', 9, 0, - /* 693 */ 'v', 's', 'h', 'f', '.', 'b', 9, 0, - /* 701 */ 'b', 'n', 'e', 'g', '.', 'b', 9, 0, - /* 709 */ 's', 'r', 'a', 'i', '.', 'b', 9, 0, - /* 717 */ 's', 'l', 'd', 'i', '.', 'b', 9, 0, - /* 725 */ 'a', 'n', 'd', 'i', '.', 'b', 9, 0, - /* 733 */ 'b', 'n', 'e', 'g', 'i', '.', 'b', 9, 0, - /* 742 */ 'b', 's', 'e', 'l', 'i', '.', 'b', 9, 0, - /* 751 */ 's', 'l', 'l', 'i', '.', 'b', 9, 0, - /* 759 */ 's', 'r', 'l', 'i', '.', 'b', 9, 0, - /* 767 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'b', 9, 0, - /* 777 */ 'c', 'e', 'q', 'i', '.', 'b', 9, 0, - /* 785 */ 's', 'r', 'a', 'r', 'i', '.', 'b', 9, 0, - /* 794 */ 'b', 'c', 'l', 'r', 'i', '.', 'b', 9, 0, - /* 803 */ 's', 'r', 'l', 'r', 'i', '.', 'b', 9, 0, - /* 812 */ 'n', 'o', 'r', 'i', '.', 'b', 9, 0, - /* 820 */ 'x', 'o', 'r', 'i', '.', 'b', 9, 0, - /* 828 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'b', 9, 0, - /* 838 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'b', 9, 0, - /* 848 */ 'b', 's', 'e', 't', 'i', '.', 'b', 9, 0, - /* 857 */ 's', 'u', 'b', 'v', 'i', '.', 'b', 9, 0, - /* 866 */ 'a', 'd', 'd', 'v', 'i', '.', 'b', 9, 0, - /* 875 */ 'b', 'm', 'z', 'i', '.', 'b', 9, 0, - /* 883 */ 'b', 'm', 'n', 'z', 'i', '.', 'b', 9, 0, - /* 892 */ 'f', 'i', 'l', 'l', '.', 'b', 9, 0, - /* 900 */ 's', 'l', 'l', '.', 'b', 9, 0, - /* 907 */ 's', 'r', 'l', '.', 'b', 9, 0, - /* 914 */ 'b', 'i', 'n', 's', 'l', '.', 'b', 9, 0, - /* 923 */ 'i', 'l', 'v', 'l', '.', 'b', 9, 0, - /* 931 */ 'c', 'e', 'q', '.', 'b', 9, 0, - /* 938 */ 's', 'r', 'a', 'r', '.', 'b', 9, 0, - /* 946 */ 'b', 'c', 'l', 'r', '.', 'b', 9, 0, - /* 954 */ 's', 'r', 'l', 'r', '.', 'b', 9, 0, - /* 962 */ 'b', 'i', 'n', 's', 'r', '.', 'b', 9, 0, - /* 971 */ 'i', 'l', 'v', 'r', '.', 'b', 9, 0, - /* 979 */ 'a', 's', 'u', 'b', '_', 's', '.', 'b', 9, 0, - /* 989 */ 'm', 'o', 'd', '_', 's', '.', 'b', 9, 0, - /* 998 */ 'c', 'l', 'e', '_', 's', '.', 'b', 9, 0, - /* 1007 */ 'a', 'v', 'e', '_', 's', '.', 'b', 9, 0, - /* 1016 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'b', 9, 0, - /* 1026 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'b', 9, 0, - /* 1036 */ 'c', 'l', 't', 'i', '_', 's', '.', 'b', 9, 0, - /* 1046 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'b', 9, 0, - /* 1056 */ 'm', 'i', 'n', '_', 's', '.', 'b', 9, 0, - /* 1065 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'b', 9, 0, - /* 1075 */ 's', 'u', 'b', 's', '_', 's', '.', 'b', 9, 0, - /* 1085 */ 'a', 'd', 'd', 's', '_', 's', '.', 'b', 9, 0, - /* 1095 */ 's', 'a', 't', '_', 's', '.', 'b', 9, 0, - /* 1104 */ 'c', 'l', 't', '_', 's', '.', 'b', 9, 0, - /* 1113 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'b', 9, 0, - /* 1125 */ 'd', 'i', 'v', '_', 's', '.', 'b', 9, 0, - /* 1134 */ 'm', 'a', 'x', '_', 's', '.', 'b', 9, 0, - /* 1143 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'b', 9, 0, - /* 1153 */ 's', 'p', 'l', 'a', 't', '.', 'b', 9, 0, - /* 1162 */ 'b', 's', 'e', 't', '.', 'b', 9, 0, - /* 1170 */ 'p', 'c', 'n', 't', '.', 'b', 9, 0, - /* 1178 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'b', 9, 0, - /* 1188 */ 's', 't', '.', 'b', 9, 0, - /* 1194 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'b', 9, 0, - /* 1204 */ 'm', 'o', 'd', '_', 'u', '.', 'b', 9, 0, - /* 1213 */ 'c', 'l', 'e', '_', 'u', '.', 'b', 9, 0, - /* 1222 */ 'a', 'v', 'e', '_', 'u', '.', 'b', 9, 0, - /* 1231 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1241 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1251 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1261 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1271 */ 'm', 'i', 'n', '_', 'u', '.', 'b', 9, 0, - /* 1280 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'b', 9, 0, - /* 1290 */ 's', 'u', 'b', 's', '_', 'u', '.', 'b', 9, 0, - /* 1300 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'b', 9, 0, - /* 1310 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'b', 9, 0, - /* 1322 */ 's', 'a', 't', '_', 'u', '.', 'b', 9, 0, - /* 1331 */ 'c', 'l', 't', '_', 'u', '.', 'b', 9, 0, - /* 1340 */ 'd', 'i', 'v', '_', 'u', '.', 'b', 9, 0, - /* 1349 */ 'm', 'a', 'x', '_', 'u', '.', 'b', 9, 0, - /* 1358 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'b', 9, 0, - /* 1368 */ 'm', 's', 'u', 'b', 'v', '.', 'b', 9, 0, - /* 1377 */ 'm', 'a', 'd', 'd', 'v', '.', 'b', 9, 0, - /* 1386 */ 'p', 'c', 'k', 'e', 'v', '.', 'b', 9, 0, - /* 1395 */ 'i', 'l', 'v', 'e', 'v', '.', 'b', 9, 0, - /* 1404 */ 'm', 'u', 'l', 'v', '.', 'b', 9, 0, - /* 1412 */ 'b', 'z', '.', 'b', 9, 0, - /* 1418 */ 'b', 'n', 'z', '.', 'b', 9, 0, - /* 1425 */ 's', 'e', 'b', 9, 0, - /* 1430 */ 'j', 'r', '.', 'h', 'b', 9, 0, - /* 1437 */ 'j', 'a', 'l', 'r', '.', 'h', 'b', 9, 0, - /* 1446 */ 'l', 'b', 9, 0, - /* 1450 */ 's', 'h', 'r', 'a', '.', 'q', 'b', 9, 0, - /* 1459 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, - /* 1473 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, - /* 1486 */ 'c', 'm', 'p', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, - /* 1498 */ 's', 'u', 'b', 'u', 'h', '.', 'q', 'b', 9, 0, - /* 1508 */ 'a', 'd', 'd', 'u', 'h', '.', 'q', 'b', 9, 0, - /* 1518 */ 'p', 'i', 'c', 'k', '.', 'q', 'b', 9, 0, - /* 1527 */ 's', 'h', 'l', 'l', '.', 'q', 'b', 9, 0, - /* 1536 */ 'r', 'e', 'p', 'l', '.', 'q', 'b', 9, 0, - /* 1545 */ 's', 'h', 'r', 'l', '.', 'q', 'b', 9, 0, - /* 1554 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, - /* 1568 */ 'c', 'm', 'p', 'g', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, - /* 1581 */ 'c', 'm', 'p', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, - /* 1593 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'q', 'b', 9, 0, - /* 1604 */ 's', 'u', 'b', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0, - /* 1616 */ 'a', 'd', 'd', 'u', 'h', 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9, 0, - /* 1794 */ 'm', 's', 'u', 'b', 9, 0, - /* 1800 */ 'b', 'c', 9, 0, - /* 1804 */ 'b', 'g', 'e', 'c', 9, 0, - /* 1810 */ 'b', 'n', 'e', 'c', 9, 0, - /* 1816 */ 'j', 'i', 'c', 9, 0, - /* 1821 */ 'b', 'a', 'l', 'c', 9, 0, - /* 1827 */ 'j', 'i', 'a', 'l', 'c', 9, 0, - /* 1834 */ 'b', 'g', 'e', 'z', 'a', 'l', 'c', 9, 0, - /* 1843 */ 'b', 'l', 'e', 'z', 'a', 'l', 'c', 9, 0, - /* 1852 */ 'b', 'n', 'e', 'z', 'a', 'l', 'c', 9, 0, - /* 1861 */ 'b', 'e', 'q', 'z', 'a', 'l', 'c', 9, 0, - /* 1870 */ 'b', 'g', 't', 'z', 'a', 'l', 'c', 9, 0, - /* 1879 */ 'b', 'l', 't', 'z', 'a', 'l', 'c', 9, 0, - /* 1888 */ 'l', 'd', 'p', 'c', 9, 0, - /* 1894 */ 'a', 'u', 'i', 'p', 'c', 9, 0, - /* 1901 */ 'a', 'l', 'u', 'i', 'p', 'c', 9, 0, - /* 1909 */ 'a', 'd', 'd', 'i', 'u', 'p', 'c', 9, 0, - /* 1918 */ 'l', 'w', 'u', 'p', 'c', 9, 0, - /* 1925 */ 'l', 'w', 'p', 'c', 9, 0, - /* 1931 */ 'b', 'e', 'q', 'c', 9, 0, - /* 1937 */ 'j', 'r', 'c', 9, 0, - /* 1942 */ 'a', 'd', 'd', 's', 'c', 9, 0, - /* 1949 */ 'b', 'l', 't', 'c', 9, 0, - /* 1955 */ 'b', 'g', 'e', 'u', 'c', 9, 0, - /* 1962 */ 'b', 'l', 't', 'u', 'c', 9, 0, - /* 1969 */ 'b', 'n', 'v', 'c', 9, 0, - /* 1975 */ 'b', 'o', 'v', 'c', 9, 0, - /* 1981 */ 'a', 'd', 'd', 'w', 'c', 9, 0, - /* 1988 */ 'b', 'g', 'e', 'z', 'c', 9, 0, - /* 1995 */ 'b', 'l', 'e', 'z', 'c', 9, 0, - /* 2002 */ 'b', 'n', 'e', 'z', 'c', 9, 0, - /* 2009 */ 'b', 'e', 'q', 'z', 'c', 9, 0, - /* 2016 */ 'b', 'g', 't', 'z', 'c', 9, 0, - /* 2023 */ 'b', 'l', 't', 'z', 'c', 9, 0, - /* 2030 */ 'f', 'l', 'o', 'g', '2', '.', 'd', 9, 0, - /* 2039 */ 'f', 'e', 'x', 'p', '2', '.', 'd', 9, 0, - /* 2048 */ 'a', 'd', 'd', '_', 'a', '.', 'd', 9, 0, - /* 2057 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'd', 9, 0, - /* 2067 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'd', 9, 0, - /* 2077 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'd', 9, 0, - /* 2087 */ 'm', 'i', 'n', 'a', '.', 'd', 9, 0, - /* 2095 */ 's', 'r', 'a', '.', 'd', 9, 0, - /* 2102 */ 'm', 'a', 'x', 'a', '.', 'd', 9, 0, - /* 2110 */ 'f', 's', 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*/ 'c', '.', 'n', 'g', 't', '.', 'd', 9, 0, - /* 3289 */ 'c', '.', 'l', 't', '.', 'd', 9, 0, - /* 3297 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'd', 9, 0, - /* 3307 */ 'f', 'c', 'l', 't', '.', 'd', 9, 0, - /* 3315 */ 'c', '.', 'o', 'l', 't', '.', 'd', 9, 0, - /* 3324 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 'd', 9, 0, - /* 3335 */ 'f', 's', 'l', 't', '.', 'd', 9, 0, - /* 3343 */ 'c', '.', 'u', 'l', 't', '.', 'd', 9, 0, - /* 3352 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 'd', 9, 0, - /* 3363 */ 'f', 'c', 'u', 'l', 't', '.', 'd', 9, 0, - /* 3372 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 'd', 9, 0, - /* 3384 */ 'f', 's', 'u', 'l', 't', '.', 'd', 9, 0, - /* 3393 */ 'p', 'c', 'n', 't', '.', 'd', 9, 0, - /* 3401 */ 'f', 'r', 'i', 'n', 't', '.', 'd', 9, 0, - /* 3410 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'd', 9, 0, - /* 3420 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0, - /* 3429 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'd', 9, 0, - /* 3439 */ 's', 't', '.', 'd', 9, 0, - /* 3445 */ 'm', 'o', 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*/ 's', 'r', 'a', 'i', '.', 'w', 9, 0, - /* 7760 */ 's', 'l', 'd', 'i', '.', 'w', 9, 0, - /* 7768 */ 'b', 'n', 'e', 'g', 'i', '.', 'w', 9, 0, - /* 7777 */ 's', 'l', 'l', 'i', '.', 'w', 9, 0, - /* 7785 */ 's', 'r', 'l', 'i', '.', 'w', 9, 0, - /* 7793 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'w', 9, 0, - /* 7803 */ 'c', 'e', 'q', 'i', '.', 'w', 9, 0, - /* 7811 */ 's', 'r', 'a', 'r', 'i', '.', 'w', 9, 0, - /* 7820 */ 'b', 'c', 'l', 'r', 'i', '.', 'w', 9, 0, - /* 7829 */ 's', 'r', 'l', 'r', 'i', '.', 'w', 9, 0, - /* 7838 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'w', 9, 0, - /* 7848 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'w', 9, 0, - /* 7858 */ 'b', 's', 'e', 't', 'i', '.', 'w', 9, 0, - /* 7867 */ 's', 'u', 'b', 'v', 'i', '.', 'w', 9, 0, - /* 7876 */ 'a', 'd', 'd', 'v', 'i', '.', 'w', 9, 0, - /* 7885 */ 'd', 'p', 'a', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, - /* 7898 */ 'd', 'p', 's', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, - /* 7911 */ 'f', 'i', 'l', 'l', '.', 'w', 9, 0, - /* 7919 */ 's', 'l', 'l', '.', 'w', 9, 0, - /* 7926 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'w', 9, 0, - /* 7936 */ 'f', 'f', 'q', 'l', '.', 'w', 9, 0, - /* 7944 */ 's', 'r', 'l', '.', 'w', 9, 0, - /* 7951 */ 'b', 'i', 'n', 's', 'l', '.', 'w', 9, 0, - /* 7960 */ 'f', 'm', 'u', 'l', '.', 'w', 9, 0, - /* 7968 */ 'i', 'l', 'v', 'l', '.', 'w', 9, 0, - /* 7976 */ 'f', 'm', 'i', 'n', '.', 'w', 9, 0, - /* 7984 */ 'f', 'c', 'u', 'n', '.', 'w', 9, 0, - /* 7992 */ 'f', 's', 'u', 'n', '.', 'w', 9, 0, - /* 8000 */ 'f', 'e', 'x', 'd', 'o', '.', 'w', 9, 0, - /* 8009 */ 'f', 'r', 'c', 'p', '.', 'w', 9, 0, - /* 8017 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'w', 9, 0, - /* 8027 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'w', 9, 0, - /* 8037 */ 'm', 'u', 'l', '_', 'q', '.', 'w', 9, 0, - /* 8046 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'w', 9, 0, - /* 8057 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'w', 9, 0, - /* 8068 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'w', 9, 0, - /* 8078 */ 'f', 'c', 'e', 'q', '.', 'w', 9, 0, - /* 8086 */ 'f', 's', 'e', 'q', '.', 'w', 9, 0, - /* 8094 */ 'f', 'c', 'u', 'e', 'q', '.', 'w', 9, 0, - /* 8103 */ 'f', 's', 'u', 'e', 'q', '.', 'w', 9, 0, - /* 8112 */ 'f', 't', 'q', '.', 'w', 9, 0, - /* 8119 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'w', 9, 0, - /* 8129 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'w', 9, 0, - /* 8140 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'w', 9, 0, - /* 8151 */ 'e', 'x', 't', 'r', '_', 'r', '.', 'w', 9, 0, - /* 8161 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'w', 9, 0, - /* 8172 */ 'e', 'x', 't', 'r', 'v', '_', 'r', '.', 'w', 9, 0, - /* 8183 */ 's', 'r', 'a', 'r', '.', 'w', 9, 0, - /* 8191 */ 'b', 'c', 'l', 'r', '.', 'w', 9, 0, - /* 8199 */ 's', 'r', 'l', 'r', '.', 'w', 9, 0, - /* 8207 */ 'f', 'c', 'o', 'r', '.', 'w', 9, 0, - /* 8215 */ 'f', 's', 'o', 'r', '.', 'w', 9, 0, - /* 8223 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'w', 9, 0, - /* 8233 */ 'f', 'f', 'q', 'r', '.', 'w', 9, 0, - /* 8241 */ 'b', 'i', 'n', 's', 'r', '.', 'w', 9, 0, - /* 8250 */ 'e', 'x', 't', 'r', '.', 'w', 9, 0, - /* 8258 */ 'i', 'l', 'v', 'r', '.', 'w', 9, 0, - /* 8266 */ 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, - /* 8275 */ 'a', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, - /* 8285 */ 'h', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, - /* 8295 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, - /* 8306 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'w', 9, 0, - /* 8318 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, - /* 8328 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, - /* 8339 */ 'm', 'o', 'd', '_', 's', '.', 'w', 9, 0, - /* 8348 */ 'c', 'l', 'e', '_', 's', '.', 'w', 9, 0, - /* 8357 */ 'a', 'v', 'e', '_', 's', '.', 'w', 9, 0, - /* 8366 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'w', 9, 0, - /* 8376 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'w', 9, 0, - /* 8386 */ 'c', 'l', 't', 'i', '_', 's', '.', 'w', 9, 0, - /* 8396 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'w', 9, 0, - /* 8406 */ 's', 'h', 'l', 'l', '_', 's', '.', 'w', 9, 0, - /* 8416 */ 'm', 'i', 'n', '_', 's', '.', 'w', 9, 0, - /* 8425 */ 'd', 'o', 't', 'p', '_', 's', '.', 'w', 9, 0, - /* 8435 */ 's', 'u', 'b', 'q', '_', 's', '.', 'w', 9, 0, - /* 8445 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'w', 9, 0, - /* 8455 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'w', 9, 0, - /* 8465 */ 'a', 'b', 's', 'q', '_', 's', '.', 'w', 9, 0, - /* 8475 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'w', 9, 0, - /* 8485 */ 's', 'u', 'b', 's', '_', 's', '.', 'w', 9, 0, - /* 8495 */ 'a', 'd', 'd', 's', '_', 's', '.', 'w', 9, 0, - /* 8505 */ 's', 'a', 't', '_', 's', '.', 'w', 9, 0, - /* 8514 */ 'c', 'l', 't', '_', 's', '.', 'w', 9, 0, - /* 8523 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, - /* 8534 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, - /* 8545 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'w', 9, 0, - /* 8557 */ 'd', 'i', 'v', '_', 's', '.', 'w', 9, 0, - /* 8566 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'w', 9, 0, - /* 8577 */ 'm', 'a', 'x', '_', 's', '.', 'w', 9, 0, - /* 8586 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'w', 9, 0, - /* 8596 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'w', 9, 0, - /* 8607 */ 'e', 'x', 't', 'r', '_', 'r', 's', '.', 'w', 9, 0, - /* 8618 */ 'e', 'x', 't', 'r', 'v', '_', 'r', 's', '.', 'w', 9, 0, - /* 8630 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'w', 9, 0, - /* 8640 */ 's', 'p', 'l', 'a', 't', '.', 'w', 9, 0, - /* 8649 */ 'b', 's', 'e', 't', '.', 'w', 9, 0, - /* 8657 */ 'f', 'c', 'l', 't', '.', 'w', 9, 0, - /* 8665 */ 'f', 's', 'l', 't', '.', 'w', 9, 0, - /* 8673 */ 'f', 'c', 'u', 'l', 't', '.', 'w', 9, 0, - /* 8682 */ 'f', 's', 'u', 'l', 't', '.', 'w', 9, 0, - /* 8691 */ 'p', 'c', 'n', 't', '.', 'w', 9, 0, - /* 8699 */ 'f', 'r', 'i', 'n', 't', '.', 'w', 9, 0, - /* 8708 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'w', 9, 0, - /* 8718 */ 'f', 's', 'q', 'r', 't', '.', 'w', 9, 0, - /* 8727 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'w', 9, 0, - /* 8737 */ 's', 't', '.', 'w', 9, 0, - /* 8743 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, - /* 8753 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, - /* 8763 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, - /* 8774 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'w', 9, 0, - /* 8786 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, - /* 8796 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, - /* 8807 */ 'm', 'o', 'd', '_', 'u', '.', 'w', 9, 0, - /* 8816 */ 'c', 'l', 'e', '_', 'u', '.', 'w', 9, 0, - /* 8825 */ 'a', 'v', 'e', '_', 'u', '.', 'w', 9, 0, - /* 8834 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8844 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8854 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8864 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8874 */ 'm', 'i', 'n', '_', 'u', '.', 'w', 9, 0, - /* 8883 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'w', 9, 0, - /* 8893 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'w', 9, 0, - /* 8903 */ 's', 'u', 'b', 's', '_', 'u', '.', 'w', 9, 0, - /* 8913 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'w', 9, 0, - /* 8923 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'w', 9, 0, - /* 8935 */ 's', 'a', 't', '_', 'u', '.', 'w', 9, 0, - /* 8944 */ 'c', 'l', 't', '_', 'u', '.', 'w', 9, 0, - /* 8953 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, - /* 8964 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, - /* 8975 */ 'd', 'i', 'v', '_', 'u', '.', 'w', 9, 0, - /* 8984 */ 'm', 'a', 'x', '_', 'u', '.', 'w', 9, 0, - /* 8993 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'w', 9, 0, - /* 9003 */ 'm', 's', 'u', 'b', 'v', '.', 'w', 9, 0, - /* 9012 */ 'm', 'a', 'd', 'd', 'v', '.', 'w', 9, 0, - /* 9021 */ 'p', 'c', 'k', 'e', 'v', '.', 'w', 9, 0, - /* 9030 */ 'i', 'l', 'v', 'e', 'v', '.', 'w', 9, 0, - /* 9039 */ 'f', 'd', 'i', 'v', '.', 'w', 9, 0, - /* 9047 */ 'm', 'u', 'l', 'v', '.', 'w', 9, 0, - /* 9055 */ 'e', 'x', 't', 'r', 'v', '.', 'w', 9, 0, - /* 9064 */ 'f', 'm', 'a', 'x', '.', 'w', 9, 0, - /* 9072 */ 'b', 'z', '.', 'w', 9, 0, - /* 9078 */ 'b', 'n', 'z', '.', 'w', 9, 0, - /* 9085 */ 'l', 'w', 9, 0, - /* 9089 */ 's', 'w', 9, 0, - /* 9093 */ 'l', 'h', 'x', 9, 0, - /* 9098 */ 'j', 'a', 'l', 'x', 9, 0, - /* 9104 */ 'l', 'b', 'u', 'x', 9, 0, - /* 9110 */ 'l', 'w', 'x', 9, 0, - /* 9115 */ 'b', 'g', 'e', 'z', 9, 0, - /* 9121 */ 'b', 'l', 'e', 'z', 9, 0, - /* 9127 */ 'b', 'n', 'e', 'z', 9, 0, - /* 9133 */ 's', 'e', 'l', 'n', 'e', 'z', 9, 0, - /* 9141 */ 'b', 't', 'n', 'e', 'z', 9, 0, - /* 9148 */ 'd', 'c', 'l', 'z', 9, 0, - /* 9154 */ 'b', 'e', 'q', 'z', 9, 0, - /* 9160 */ 's', 'e', 'l', 'e', 'q', 'z', 9, 0, - /* 9168 */ 'b', 't', 'e', 'q', 'z', 9, 0, - /* 9175 */ 'b', 'g', 't', 'z', 9, 0, - /* 9181 */ 'b', 'l', 't', 'z', 9, 0, - /* 9187 */ 'm', 'o', 'v', 'z', 9, 0, - /* 9193 */ 's', 'e', 'b', 9, 32, 0, - /* 9199 */ 'j', 'r', 'c', 9, 32, 0, - /* 9205 */ 's', 'e', 'h', 9, 32, 0, - /* 9211 */ 'd', 'd', 'i', 'v', 'u', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, - /* 9225 */ 'd', 'd', 'i', 'v', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, - /* 9238 */ 'a', 'd', 'd', 'i', 'u', 9, '$', 's', 'p', ',', 32, 0, - /* 9250 */ 'c', 'i', 'n', 's', '3', '2', 32, 0, - /* 9258 */ 'e', 'x', 't', 's', '3', '2', 32, 0, - /* 9266 */ 's', 'y', 'n', 'c', 32, 0, - /* 9272 */ 9, '.', 'w', 'o', 'r', 'd', 32, 0, - /* 9280 */ 'd', 'i', 'n', 's', 'm', 32, 0, - /* 9287 */ 'd', 'e', 'x', 't', 'm', 32, 0, - /* 9294 */ 'c', 'i', 'n', 's', 32, 0, - /* 9300 */ 'd', 'i', 'n', 's', 32, 0, - /* 9306 */ 'e', 'x', 't', 's', 32, 0, - /* 9312 */ 'd', 'e', 'x', 't', 32, 0, - /* 9318 */ 'd', 'i', 'n', 's', 'u', 32, 0, - /* 9325 */ 'd', 'e', 'x', 't', 'u', 32, 0, - /* 9332 */ 'b', 'c', '1', 'n', 'e', 'z', 32, 0, - /* 9340 */ 'b', 'c', '2', 'n', 'e', 'z', 32, 0, - /* 9348 */ 'b', 'c', '1', 'e', 'q', 'z', 32, 0, - /* 9356 */ 'b', 'c', '2', 'e', 'q', 'z', 32, 0, - /* 9364 */ 'c', '.', 0, - /* 9367 */ 'b', 'r', 'e', 'a', 'k', 32, '0', 0, - /* 9375 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 9388 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 9395 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 9405 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 9420 */ 'j', 'r', 'c', 9, 32, '$', 'r', 'a', 0, - /* 9429 */ 'j', 'r', 9, 32, '$', 'r', 'a', 0, - /* 9437 */ 'e', 'h', 'b', 0, - /* 9441 */ 'p', 'a', 'u', 's', 'e', 0, - /* 9447 */ 't', 'l', 'b', 'w', 'i', 0, - /* 9453 */ 'f', 'o', 'o', 0, - /* 9457 */ 't', 'l', 'b', 'p', 0, - /* 9462 */ 's', 's', 'n', 'o', 'p', 0, - /* 9468 */ 't', 'l', 'b', 'r', 0, - /* 9473 */ 't', 'l', 'b', 'w', 'r', 0, - /* 9479 */ 'd', 'e', 'r', 'e', 't', 0, - /* 9485 */ 'w', 'a', 'i', 't', 0, - }; -#endif - // Emit the opcode for the instruction. - uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; - uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; - uint64_t Bits = (Bits2 << 32) | Bits1; - // assert(Bits != 0 && "Cannot print this instruction."); + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; + MnemonicBitsInfo MBI = { #ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 16383)-1); -#endif + AsmStrs+(Bits & 16383)-1, +#else + NULL, +#endif // CAPSTONE_DIET + Bits + }; + return MBI; +} +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) { + SStream_concat0(O, ""); + MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O); - // Fragment 0 encoded into 4 bits for 11 unique commands. - //printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 15); - switch ((uint32_t)((Bits >> 14) & 15)) { - default: // llvm_unreachable("Invalid command number."); + SStream_concat0(O, MnemonicInfo.first); + + uint64_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 5 bits for 20 unique commands. + switch ((Bits >> 14) & 31) { + default: assert(0 && "Invalid command number."); case 0: - // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, Break16, CONSTPOOL_EN... + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... return; break; case 1: - // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... - printOperand(MI, 0, O); + // ABSMacro, ALIGN_NM, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro... + printOperand(MI, 0, O); break; case 2: - // ADDIUS5_MM, CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHI_DSP,... - printOperand(MI, 1, O); - SStream_concat0(O, ", "); + // B_MMR6_Pseudo, B_MM_Pseudo, B16_MM, BAL, BALC, BALC_MMR6, BC, BC16_MMR... + printBranchOperand(MI, Address, 0, O); break; case 3: - // AND16_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, OR16_MM, XOR16_MM - printOperand(MI, 2, O); - SStream_concat0(O, ", "); + // CTTC1, MTTACX, MTTACX_NM, MTTC0, MTTC0_NM, MTTC1, MTTGPR, MTTGPR_NM, M... + printOperand(MI, 1, O); + SStream_concat0(O, ", "); break; case 4: - // BREAK16_MM, SDBBP16_MM - printUnsignedImm8(MI, 0, O); + // LWM_MM, SWM_MM, LWM16_MM, LWM16_MMR6, LWM32_MM, SWM16_MM, SWM16_MMR6, ... + printRegisterList(MI, 0, O); + SStream_concat0(O, ", "); + printMemOperand(MI, 1, O); return; break; case 5: - // CACHE, CACHE_MM, CACHE_R6, PREF, PREF_MM, PREF_R6 - printUnsignedImm(MI, 2, O); - SStream_concat0(O, ", "); - printMemOperand(MI, 0, O); - return; - break; - case 6: - // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM - printFCCOperand(MI, 2, O); - break; - case 7: - // LWM16_MM, LWM32_MM, LWM_MM, MOVEP_MM, SWM16_MM, SWM32_MM, SWM_MM - printRegisterList(MI, 0, O); - SStream_concat0(O, ", "); - break; - case 8: - // LWP_MM, SWP_MM - printRegisterPair(MI, 0, O); - SStream_concat0(O, ", "); - printMemOperand(MI, 2, O); - return; - break; - case 9: - // SYNCI - printMemOperand(MI, 0, O); - return; - break; - case 10: // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... - printOperand(MI, 3, O); - break; - } - - - // Fragment 1 encoded into 5 bits for 17 unique commands. - //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 31); - switch ((uint32_t)((Bits >> 18) & 31)) { - default: // llvm_unreachable("Invalid command number."); - case 0: - // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... - SStream_concat0(O, ", "); - break; - case 1: - // ADDIUS5_MM, DAHI, DATI, MOVEP_MM, MultRxRyRz16, MultuRxRyRz16, SltCCRx... - printOperand(MI, 2, O); - break; - case 2: - // ADDIUSP_MM, AddiuSpImmX16, B16_MM, BAL, BALC, BC, BPOSGE32, B_MM_Pseud... - return; - break; - case 3: - // AND16_MM, OR16_MM, XOR16_MM - printOperand(MI, 1, O); - return; - break; - case 4: - // AddiuRxPcImmX16 - SStream_concat0(O, ", $pc, "); - printOperand(MI, 1, O); - return; - break; - case 5: - // AddiuSpImm16, Bimm16 - SStream_concat0(O, " # 16 bit inst"); - return; + printOperand(MI, 3, O); break; case 6: - // Bteqz16, Btnez16 - SStream_concat0(O, " # 16 bit inst"); - return; + // AND16_MM, AND16_MMR6, LSA_MMR6, MTHC1_D32, MTHC1_D32_MM, MTHC1_D64, MT... + printOperand(MI, 2, O); + SStream_concat0(O, ", "); break; case 7: - // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, M... - printOperand(MI, 0, O); + // BALC16_NM, BALC_NM + printPCRel(MI, Address, 0, O); return; break; case 8: - // FCMP_D32, FCMP_D32_MM, FCMP_D64 - SStream_concat0(O, ".d\t"); - printOperand(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); - return; + // BREAK, BREAK_MM, BREAK_MMR6, HYPCALL, HYPCALL_MM, SDBBP_MM, SYSCALL_MM... + printUImm_10_0(MI, 0, O); break; case 9: - // FCMP_S32, FCMP_S32_MM - SStream_concat0(O, ".s\t"); - printOperand(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); + // BREAK16_MM, BREAK16_MMR6, SDBBP16_MM, SDBBP16_MMR6 + printUImm_4_0(MI, 0, O); return; break; case 10: - // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... - SStream_concat0(O, "["); + // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... + printUImm_5_0(MI, 2, O); + SStream_concat0(O, ", "); break; case 11: - // Jal16 - SStream_concat0(O, "\n\tnop"); - return; + // CACHE_NM, PREF_NM, PREFs9_NM, SYNC, SYNC_MM, SYNC_MMR6, SYNC_NM + printUImm_5_0(MI, 0, O); break; case 12: - // JalB16 - SStream_concat0(O, "\t# branch\n\tnop"); - return; + // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM + printFCCOperand(MI, 2, O); break; case 13: - // LWM16_MM, LWM32_MM, LWM_MM, SWM16_MM, SWM32_MM, SWM_MM - printMemOperand(MI, 1, O); + // J, JAL, JALS_MM, JALX, JALX_MM, JAL_MM, J_MM + printJumpOperand(MI, 0, O); return; break; case 14: - // LwConstant32 - SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); - printOperand(MI, 1, O); - SStream_concat0(O, "\n2:"); - return; + // Jal16, JalB16 + printUImm_26_0(MI, 0, O); break; case 15: - // SC, SCD, SCD_R6, SC_MM, SC_R6 - printMemOperand(MI, 2, O); + // RESTOREJRC16_NM, SAVE16_NM + printUImm_8_0(MI, 0, O); + printNanoMipsRegisterList(MI, 1, O); return; break; case 16: + // RESTOREJRC_NM, RESTORE_NM, SAVE_NM + printUImm_12_0(MI, 0, O); + printNanoMipsRegisterList(MI, 1, O); + return; + break; + case 17: + // SDBBP, SDBBP_MMR6, SDBBP_R6, SYSCALL + printUImm_20_0(MI, 0, O); + return; + break; + case 18: + // SIGRIE, SIGRIE_MMR6 + printUImm_16_0(MI, 0, O); + return; + break; + case 19: + // SYNCI, SYNCI_MM, SYNCI_MMR6, SYNCI_NM, SYNCIs9_NM + printMemOperand(MI, 0, O); + return; + break; + } + + + // Fragment 1 encoded into 5 bits for 18 unique commands. + switch ((Bits >> 19) & 31) { + default: assert(0 && "Invalid command number."); + case 0: + // ABSMacro, ALIGN_NM, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro... + SStream_concat0(O, ", "); + break; + case 1: + // B_MMR6_Pseudo, B_MM_Pseudo, Constant32, JalOneReg, MFTDSP, MFTDSP_NM, ... + return; + break; + case 2: + // CTTC1, MTTACX, MTTACX_NM, MTTC0, MTTC0_NM, MTTC1, MTTGPR, MTTGPR_NM, M... + printOperand(MI, 0, O); + break; + case 3: + // LwConstant32 + SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); + printOperand(MI, 1, O); + SStream_concat0(O, "\n2:"); + return; + break; + case 4: + // MultRxRyRz16, MultuRxRyRz16, SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImm... + printOperand(MI, 2, O); + break; + case 5: // SelBeqZ, SelBneZ - SStream_concat0(O, ", .+4\n\t\n\tmove "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); - return; - break; - } - - - // Fragment 2 encoded into 4 bits for 12 unique commands. - //printf("Frag-2: %"PRIu64"\n", (Bits >> 23) & 15); - switch ((uint32_t)((Bits >> 23) & 15)) { - default: // llvm_unreachable("Invalid command number."); - case 0: - // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... - printOperand(MI, 1, O); - break; - case 1: - // ADDIUS5_MM, DAHI, DATI - return; - break; - case 2: - // AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B, BINSLI_D, BINS... - printOperand(MI, 2, O); - break; - case 3: - // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM - printMemOperandEA(MI, 1, O); - return; - break; - case 4: - // BBIT0, BBIT032, BBIT1, BBIT132, LUi, LUi64, LUi_MM, LoadAddr32Imm, Loa... - printUnsignedImm(MI, 1, O); - break; - case 5: - // INSERT_B, INSERT_D, INSERT_H, INSERT_W - printUnsignedImm(MI, 3, O); - SStream_concat0(O, "], "); - printOperand(MI, 2, O); + SStream_concat0(O, ", .+4\n\t\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); return; break; case 6: - // INSVE_B, INSVE_D, INSVE_H, INSVE_W - printUnsignedImm(MI, 2, O); - SStream_concat0(O, "], "); - printOperand(MI, 3, O); - SStream_concat0(O, "["); - printUnsignedImm(MI, 4, O); - SStream_concat0(O, "]"); - return; + // AND16_MM, AND16_MMR6, LSA_MMR6, OR16_MM, OR16_MMR6, PREFX_MM, XOR16_MM... + printOperand(MI, 1, O); break; case 7: - // LB, LB64, LBU16_MM, LB_MM, LBu, LBu64, LBu_MM, LD, LDC1, LDC164, LDC1_... - printMemOperand(MI, 1, O); + // AddiuRxPcImmX16 + SStream_concat0(O, ", $pc, "); + printOperand(MI, 1, O); return; break; case 8: - // MOVEP_MM - SStream_concat0(O, ", "); - printOperand(MI, 3, O); + // AddiuSpImm16, Bimm16 + SStream_concat0(O, " # 16 bit inst"); return; break; case 9: - // MultRxRyRz16, MultuRxRyRz16 - SStream_concat0(O, "\n\tmflo\t"); - printOperand(MI, 0, O); + // Bteqz16, Btnez16 + SStream_concat0(O, " # 16 bit inst"); return; break; case 10: - // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... - printOperand(MI, 4, O); - break; - case 11: - // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... - SStream_concat0(O, "\n\tmove\t"); - printOperand(MI, 0, O); - SStream_concat0(O, ", $t8"); - return; - break; - } - - - // Fragment 3 encoded into 4 bits for 15 unique commands. - //printf("Frag-3: %"PRIu64"\n", (Bits >> 27) & 15); - switch ((uint32_t)((Bits >> 27) & 15)) { - default: // llvm_unreachable("Invalid command number."); - case 0: - // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM, ALU... - return; - break; - case 1: - // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... - SStream_concat0(O, ", "); - break; - case 2: - // AddiuRxRxImm16, LwRxPcTcp16 - SStream_concat0(O, "\t# 16 bit inst"); - return; - break; - case 3: - // BeqzRxImm16, BnezRxImm16 - SStream_concat0(O, " # 16 bit inst"); - return; - break; - case 4: - // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... - SStream_concat0(O, "\n\tbteqz\t"); - printOperand(MI, 2, O); - return; - break; - case 5: - // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... - SStream_concat0(O, "\n\tbtnez\t"); - printOperand(MI, 2, O); - return; - break; - case 6: - // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... - SStream_concat0(O, "["); - break; - case 7: - // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 - SStream_concat0(O, " \t# 16 bit inst"); - return; - break; - case 8: - // DSLL64_32 - SStream_concat0(O, ", 32"); - return; - break; - case 9: - // GotPrologue16 - SStream_concat0(O, "\n\taddiu\t"); - printOperand(MI, 1, O); - SStream_concat0(O, ", $pc, "); - printOperand(MI, 3, O); - SStream_concat0(O, "\n "); - return; - break; - case 10: - // LBUX, LDXC1, LDXC164, LHX, LUXC1, LUXC164, LUXC1_MM, LWX, LWXC1, LWXC1... - SStream_concat0(O, "("); - printOperand(MI, 1, O); - SStream_concat0(O, ")"); + // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... + printMemOperand(MI, 0, O); return; break; case 11: - // LwRxSpImmX16, SwRxSpImmX16 - SStream_concat0(O, " ( "); - printOperand(MI, 1, O); - SStream_concat0(O, " ); "); + // FCMP_D32, FCMP_D32_MM, FCMP_D64 + SStream_concat0(O, ".d\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); return; break; case 12: - // SLL64_32, SLL64_64 - SStream_concat0(O, ", 0"); + // FCMP_S32, FCMP_S32_MM + SStream_concat0(O, ".s\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); return; break; case 13: + // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... + SStream_concat1(O, '['); + break; + case 14: + // Jal16 + SStream_concat0(O, "\n\tnop"); + return; + break; + case 15: + // JalB16 + SStream_concat0(O, "\t# branch\n\tnop"); + return; + break; + case 16: + // SAA, SAAD + SStream_concat0(O, ", ("); + printOperand(MI, 1, O); + SStream_concat1(O, ')'); + return; + break; + case 17: + // SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_NM, SC... + printMemOperand(MI, 2, O); + return; + break; + } + + + // Fragment 2 encoded into 5 bits for 30 unique commands. + switch ((Bits >> 24) & 31) { + default: assert(0 && "Invalid command number."); + case 0: + // ABSMacro, ALIGN_NM, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro... + printOperand(MI, 1, O); + break; + case 1: + // CTTC1, MTTACX, MTTACX_NM, MTTC1, MTTGPR, MTTGPR_NM, MTTHC1, MTTHI, MTT... + return; + break; + case 2: + // GotPrologue16, AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B,... + printOperand(MI, 2, O); + break; + case 3: + // LDMacro, LOAD_ACC128, LOAD_ACC64, LOAD_ACC64DSP, LOAD_CCOND_DSP, LoadA... + printMemOperand(MI, 1, O); + break; + case 4: + // MTTC0, MTTC0_NM, DMTC0, DMTC2, DMTGC0, FORK, FORK_NM, LSA_MMR6, MTC0, ... + SStream_concat0(O, ", "); + break; + case 5: + // MultRxRyRz16, MultuRxRyRz16 + SStream_concat0(O, "\n\tmflo\t"); + printOperand(MI, 0, O); + return; + break; + case 6: + // PseudoLA_NM, PseudoLI_NM, LI48_NM + printUImm_32_0(MI, 1, O); + return; + break; + case 7: // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... - SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); + printOperand(MI, 4, O); + break; + case 8: + // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... + SStream_concat0(O, "\n\tmove\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", $t8"); + return; + break; + case 9: + // ALUIPC_NM + printHi20PCRel(MI, Address, 1, O); + return; + break; + case 10: + // AddiuRxRyOffMemX16, LEA_ADDIU_NM, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM + printMemOperandEA(MI, 1, O); + return; + break; + case 11: + // BBIT0, BBIT032, BBIT1, BBIT132 + printUImm_5_0(MI, 1, O); + SStream_concat0(O, ", "); + printBranchOperand(MI, Address, 2, O); + return; + break; + case 12: + // BC1EQZ, BC1EQZC_MMR6, BC1F, BC1FL, BC1F_MM, BC1NEZ, BC1NEZC_MMR6, BC1T... + printBranchOperand(MI, Address, 1, O); + break; + case 13: + // BEQIC_NM, BGEIC_NM, BGEIUC_NM, BLTIC_NM, BLTIUC_NM, BNEIC_NM, LI16_NM,... + printUImm_7_0(MI, 1, O); + break; + case 14: + // BREAK, BREAK_MM, BREAK_MMR6, RDDSP, WRDSP + printUImm_10_0(MI, 1, O); + return; + break; + case 15: + // DMFC2_OCTEON, DMTC2_OCTEON, LUI_MMR6, LUi, LUi64, LUi_MM + printUImm_16_0(MI, 1, O); + return; + break; + case 16: + // GINVT, GINVT_MMR6, GINVT_NM + printUImm_2_0(MI, 1, O); + return; + break; + case 17: + // INSERT_B + printUImm_4_0(MI, 3, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); + return; + break; + case 18: + // INSERT_D + printUImm_1_0(MI, 3, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); + return; + break; + case 19: + // INSERT_H + printUImm_3_0(MI, 3, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); + return; + break; + case 20: + // INSERT_W + printUImm_2_0(MI, 3, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); + return; + break; + case 21: + // INSVE_B + printUImm_4_0(MI, 2, O); + SStream_concat0(O, "], "); + printOperand(MI, 3, O); + SStream_concat1(O, '['); + printUImm_0_0(MI, 4, O); + SStream_concat1(O, ']'); + return; + break; + case 22: + // INSVE_D + printUImm_1_0(MI, 2, O); + SStream_concat0(O, "], "); + printOperand(MI, 3, O); + SStream_concat1(O, '['); + printUImm_0_0(MI, 4, O); + SStream_concat1(O, ']'); + return; + break; + case 23: + // INSVE_H + printUImm_3_0(MI, 2, O); + SStream_concat0(O, "], "); + printOperand(MI, 3, O); + SStream_concat1(O, '['); + printUImm_0_0(MI, 4, O); + SStream_concat1(O, ']'); + return; + break; + case 24: + // INSVE_W + printUImm_2_0(MI, 2, O); + SStream_concat0(O, "], "); + printOperand(MI, 3, O); + SStream_concat1(O, '['); + printUImm_0_0(MI, 4, O); + SStream_concat1(O, ']'); + return; + break; + case 25: + // LAPC32_NM, LAPC48_NM, LWPC_NM, SWPC_NM + printPCRel(MI, Address, 1, O); + return; + break; + case 26: + // LUI_NM + printHi20(MI, 1, O); + return; + break; + case 27: + // LWP_MM, SWP_MM + printMemOperand(MI, 2, O); + return; + break; + case 28: + // PREFX_MM + SStream_concat1(O, '('); + printOperand(MI, 0, O); + SStream_concat1(O, ')'); + return; + break; + case 29: + // REPL_QB, REPL_QB_MM + printUImm_8_0(MI, 1, O); + return; + break; + } + + + // Fragment 3 encoded into 5 bits for 19 unique commands. + switch ((Bits >> 29) & 31) { + default: assert(0 && "Invalid command number."); + case 0: + // ABSMacro, CFTC1, JalTwoReg, LDMacro, LOAD_ACC128, LOAD_ACC64, LOAD_ACC... + return; + break; + case 1: + // ALIGN_NM, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... + SStream_concat0(O, ", "); + break; + case 2: + // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... + SStream_concat0(O, "\n\tbteqz\t"); + printBranchOperand(MI, Address, 2, O); + return; + break; + case 3: + // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... + SStream_concat0(O, "\n\tbtnez\t"); + printBranchOperand(MI, Address, 2, O); + return; + break; + case 4: + // GotPrologue16 + SStream_concat0(O, "\n\taddiu\t"); + printOperand(MI, 1, O); + SStream_concat0(O, ", $pc, "); + printOperand(MI, 3, O); + SStream_concat0(O, "\n "); + return; + break; + case 5: + // MTTC0, MTTC0_NM, DMTC0, DMTC2, DMTGC0, MTC0, MTC0_MMR6, MTC2, MTGC0, M... + printUImm_3_0(MI, 2, O); + return; + break; + case 6: + // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... + SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 7: + // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... + SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 8: + // AddiuRxRxImm16, LwRxPcTcp16 + SStream_concat0(O, "\t# 16 bit inst"); + return; + break; + case 9: + // BeqzRxImm16, BnezRxImm16 + SStream_concat0(O, " # 16 bit inst"); + return; + break; + case 10: + // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... + SStream_concat1(O, '['); + break; + case 11: + // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 + SStream_concat0(O, " \t# 16 bit inst"); + return; + break; + case 12: + // DSLL64_32 + SStream_concat0(O, ", 32"); + return; + break; + case 13: + // FORK, FORK_NM + printOperand(MI, 2, O); return; break; case 14: - // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... - SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); + // LBUX, LBUX_MM, LDXC1, LDXC164, LHX, LHX_MM, LUXC1, LUXC164, LUXC1_MM, ... + SStream_concat1(O, '('); + printOperand(MI, 1, O); + SStream_concat1(O, ')'); + return; + break; + case 15: + // LSA_MMR6 + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printUImm_2_1(MI, 3, O); + return; + break; + case 16: + // MTTR, MTTR_NM + printUImm_1_0(MI, 2, O); + SStream_concat0(O, ", "); + printUImm_3_0(MI, 3, O); + SStream_concat0(O, ", "); + printUImm_1_0(MI, 4, O); + return; + break; + case 17: + // SCWP_NM + printMemOperand(MI, 3, O); + return; + break; + case 18: + // SLL64_32, SLL64_64 + SStream_concat0(O, ", 0"); return; break; } - // Fragment 4 encoded into 3 bits for 5 unique commands. - //printf("Frag-4: %"PRIu64"\n", (Bits >> 31) & 7); - switch ((uint32_t)((Bits >> 31) & 7)) { - default: // llvm_unreachable("Invalid command number."); + // Fragment 4 encoded into 5 bits for 24 unique commands. + switch ((Bits >> 34) & 31) { + default: assert(0 && "Invalid command number."); case 0: - // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... - printOperand(MI, 2, O); + // ALIGN_NM, DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROL... + printOperand(MI, 2, O); break; case 1: - // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, ANDI_B, BCLRI_B, BCLRI_D, BCLRI_H,... - printUnsignedImm8(MI, 2, O); + // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... + printBranchOperand(MI, Address, 2, O); + return; break; case 2: - // ANDi, ANDi64, ANDi_MM, APPEND, BALIGN, CINS, CINS32, DEXT, DEXTM, DEXT... - printUnsignedImm(MI, 2, O); + // MFTC0, MFTC0_NM, BCLRI_B, BNEGI_B, BSETI_B, COPY_S_H, COPY_U_H, DMFC0,... + printUImm_3_0(MI, 2, O); break; case 3: - // BINSLI_B, BINSLI_D, BINSLI_H, BINSLI_W, BINSRI_B, BINSRI_D, BINSRI_H, ... - printUnsignedImm8(MI, 3, O); + // PseudoADDIU_NM, ADDIU48_NM + printUImm_32_0(MI, 2, O); + return; break; case 4: + // PseudoANDI_NM, ADDIU_NM, ANDI16_NM, ANDI_MMR6, ANDi, ANDi64, ANDi_MM, ... + printUImm_16_0(MI, 2, O); + return; + break; + case 5: + // ADDIUR1SP_NM, ANDI_B, NORI_B, ORI_B, RDHWR, RDHWR64, RDHWR_MM, SHF_B, ... + printUImm_8_0(MI, 2, O); + return; + break; + case 6: + // ADDIUR2_NM, ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, B... + printUImm_5_0(MI, 2, O); + break; + case 7: + // BALIGN, BALIGN_MMR2, COPY_S_W, COPY_U_W, SPLATI_W + printUImm_2_0(MI, 2, O); + break; + case 8: + // BCLRI_D, BNEGI_D, BSETI_D, DEXT, DEXT64_32, DINS, DROTR, DSLL, DSRA, D... + printUImm_6_0(MI, 2, O); + break; + case 9: + // BCLRI_H, BNEGI_H, BSETI_H, COPY_S_B, COPY_U_B, SAT_S_H, SAT_U_H, SHLL_... + printUImm_4_0(MI, 2, O); + break; + case 10: + // BINSLI_B, BINSRI_B, SLDI_H + printUImm_3_0(MI, 3, O); + break; + case 11: + // BINSLI_D, BINSRI_D + printUImm_6_0(MI, 3, O); + return; + break; + case 12: + // BINSLI_H, BINSRI_H, SLDI_B + printUImm_4_0(MI, 3, O); + break; + case 13: + // BINSLI_W, BINSRI_W + printUImm_5_0(MI, 3, O); + return; + break; + case 14: // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... - printOperand(MI, 3, O); + printOperand(MI, 3, O); + break; + case 15: + // BMNZI_B, BMZI_B, BSELI_B + printUImm_8_0(MI, 3, O); + return; + break; + case 16: + // COPY_S_D, MFTR, MFTR_NM, SPLATI_D + printUImm_1_0(MI, 2, O); + break; + case 17: + // DEXTU, DINSU + printUImm_5_32(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 18: + // FADD_S_MMR6, FDIV_S_MMR6, FMUL_S_MMR6, FSUB_S_MMR6 + printOperand(MI, 1, O); + return; + break; + case 19: + // LLWP_NM + printMemOperand(MI, 2, O); + return; + break; + case 20: + // MOVEBALC_NM + printPCRel(MI, Address, 2, O); + return; + break; + case 21: + // SLDI_D + printUImm_1_0(MI, 3, O); + SStream_concat1(O, ']'); + return; + break; + case 22: + // SLDI_W + printUImm_2_0(MI, 3, O); + SStream_concat1(O, ']'); + return; + break; + case 23: + // TEQ, TGE, TGEU, TLT, TLTU, TNE + printUImm_10_0(MI, 2, O); + return; break; } - // Fragment 5 encoded into 2 bits for 3 unique commands. - //printf("Frag-5: %"PRIu64"\n", (Bits >> 34) & 3); - switch ((uint32_t)((Bits >> 34) & 3)) { - default: // llvm_unreachable("Invalid command number."); + // Fragment 5 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 39) & 7) { + default: assert(0 && "Invalid command number."); case 0: - // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... + // ALIGN_NM, ALIGN, ALIGN_MMR6, CINS, CINS32, CINS64_32, CINS_i32, DALIGN... + SStream_concat0(O, ", "); + break; + case 1: + // DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROLImm, DROR,... + return; + break; + case 2: + // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... + SStream_concat1(O, ']'); + return; + break; + case 3: + // DEXTU + printUImm_5_1(MI, 3, O); + return; + break; + case 4: + // DINSU + printUImm_6_0(MI, 3, O); + return; + break; + } + + + // Fragment 6 encoded into 4 bits for 10 unique commands. + switch ((Bits >> 42) & 15) { + default: assert(0 && "Invalid command number."); + case 0: + // ALIGN_NM, MADD_D32, MADD_D32_MM, MADD_D64, MADD_S, MADD_S_MM, MOVEPREV... + printOperand(MI, 3, O); return; break; case 1: - // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D... - SStream_concat0(O, ", "); + // ALIGN, ALIGN_MMR6, LSA_NM + printUImm_2_0(MI, 3, O); + return; break; case 2: - // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... - SStream_concat0(O, "]"); + // CINS, CINS32, CINS64_32, CINS_i32, EXTS, EXTS32, EXTW_NM, ROTX_NM + printUImm_5_0(MI, 3, O); + break; + case 3: + // DALIGN, MFTR, MFTR_NM + printUImm_3_0(MI, 3, O); + break; + case 4: + // DEXT + printUImm_6_1(MI, 3, O); + return; + break; + case 5: + // DEXT64_32, EXT, EXT_MM, EXT_MMR6, EXT_NM + printUImm_5_1(MI, 3, O); + return; + break; + case 6: + // DEXTM + printUImm_5_33(MI, 3, O); + return; + break; + case 7: + // DINS, INS, INS_MM, INS_MMR6, INS_NM + printUImm_6_0(MI, 3, O); + return; + break; + case 8: + // DINSM + printUImm_6_2(MI, 3, O); + return; + break; + case 9: + // DLSA, DLSA_R6, LSA, LSA_R6 + printUImm_2_1(MI, 3, O); return; break; } - // Fragment 6 encoded into 1 bits for 2 unique commands. - //printf("Frag-6: %"PRIu64"\n", (Bits >> 36) & 1); - if ((Bits >> 36) & 1) { - // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD... - printOperand(MI, 3, O); + // Fragment 7 encoded into 1 bits for 2 unique commands. + if ((Bits >> 46) & 1) { + // MFTR, MFTR_NM, ROTX_NM + SStream_concat0(O, ", "); + printUImm_1_0(MI, 4, O); return; } else { - // ALIGN, CINS, CINS32, DALIGN, DLSA, DLSA_R6, EXTS, EXTS32, LSA, LSA_R6 - printUnsignedImm(MI, 3, O); + // CINS, CINS32, CINS64_32, CINS_i32, DALIGN, EXTS, EXTS32, EXTW_NM return; } + } /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. -static const char *getRegisterName(unsigned RegNo) -{ - // assert(RegNo && RegNo < 394 && "Invalid register number!"); - +static const char *getRegisterName(unsigned RegNo) { #ifndef CAPSTONE_DIET + assert(RegNo && RegNo < 635 && "Invalid register number!"); + static const char AsmStrs[] = { - /* 0 */ 'f', '1', '0', 0, - /* 4 */ 'w', '1', '0', 0, - /* 8 */ 'f', '2', '0', 0, - /* 12 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0, - /* 25 */ 'w', '2', '0', 0, - /* 29 */ 'f', '3', '0', 0, - /* 33 */ 'w', '3', '0', 0, - /* 37 */ 'a', '0', 0, - /* 40 */ 'a', 'c', '0', 0, - /* 44 */ 'f', 'c', 'c', '0', 0, - /* 49 */ 'f', '0', 0, - /* 52 */ 'k', '0', 0, - /* 55 */ 'm', 'p', 'l', '0', 0, - /* 60 */ 'p', '0', 0, - /* 63 */ 's', '0', 0, - /* 66 */ 't', '0', 0, - /* 69 */ 'v', '0', 0, - /* 72 */ 'w', '0', 0, - /* 75 */ 'f', '1', '1', 0, - /* 79 */ 'w', '1', '1', 0, - /* 83 */ 'f', '2', '1', 0, - /* 87 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0, - /* 100 */ 'w', '2', '1', 0, - /* 104 */ 'f', '3', '1', 0, - /* 108 */ 'w', '3', '1', 0, - /* 112 */ 'a', '1', 0, - /* 115 */ 'a', 'c', '1', 0, - /* 119 */ 'f', 'c', 'c', '1', 0, - /* 124 */ 'f', '1', 0, - /* 127 */ 'k', '1', 0, - /* 130 */ 'm', 'p', 'l', '1', 0, - /* 135 */ 'p', '1', 0, - /* 138 */ 's', '1', 0, - /* 141 */ 't', '1', 0, - /* 144 */ 'v', '1', 0, - /* 147 */ 'w', '1', 0, - /* 150 */ 'f', '1', '2', 0, - /* 154 */ 'w', '1', '2', 0, - /* 158 */ 'f', '2', '2', 0, - /* 162 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0, - /* 175 */ 'w', '2', '2', 0, - /* 179 */ 'a', '2', 0, - /* 182 */ 'a', 'c', '2', 0, - /* 186 */ 'f', 'c', 'c', '2', 0, - /* 191 */ 'f', '2', 0, - /* 194 */ 'm', 'p', 'l', '2', 0, - /* 199 */ 'p', '2', 0, - /* 202 */ 's', '2', 0, - /* 205 */ 't', '2', 0, - /* 208 */ 'w', '2', 0, - /* 211 */ 'f', '1', '3', 0, - /* 215 */ 'w', '1', '3', 0, - /* 219 */ 'f', '2', '3', 0, - /* 223 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0, - /* 236 */ 'w', '2', '3', 0, - /* 240 */ 'a', '3', 0, - /* 243 */ 'a', 'c', '3', 0, - /* 247 */ 'f', 'c', 'c', '3', 0, - /* 252 */ 'f', '3', 0, - /* 255 */ 's', '3', 0, - /* 258 */ 't', '3', 0, - /* 261 */ 'w', '3', 0, - /* 264 */ 'f', '1', '4', 0, - /* 268 */ 'w', '1', '4', 0, - /* 272 */ 'f', '2', '4', 0, - /* 276 */ 'w', '2', '4', 0, - /* 280 */ 'f', 'c', 'c', '4', 0, - /* 285 */ 'f', '4', 0, - /* 288 */ 's', '4', 0, - /* 291 */ 't', '4', 0, - /* 294 */ 'w', '4', 0, - /* 297 */ 'f', '1', '5', 0, - /* 301 */ 'w', '1', '5', 0, - /* 305 */ 'f', '2', '5', 0, - /* 309 */ 'w', '2', '5', 0, - /* 313 */ 'f', 'c', 'c', '5', 0, - /* 318 */ 'f', '5', 0, - /* 321 */ 's', '5', 0, - /* 324 */ 't', '5', 0, - /* 327 */ 'w', '5', 0, - /* 330 */ 'f', '1', '6', 0, - /* 334 */ 'w', '1', '6', 0, - /* 338 */ 'f', '2', '6', 0, - /* 342 */ 'w', '2', '6', 0, - /* 346 */ 'f', 'c', 'c', '6', 0, - /* 351 */ 'f', '6', 0, - /* 354 */ 's', '6', 0, - /* 357 */ 't', '6', 0, - /* 360 */ 'w', '6', 0, - /* 363 */ 'f', '1', '7', 0, - /* 367 */ 'w', '1', '7', 0, - /* 371 */ 'f', '2', '7', 0, - /* 375 */ 'w', '2', '7', 0, - /* 379 */ 'f', 'c', 'c', '7', 0, - /* 384 */ 'f', '7', 0, - /* 387 */ 's', '7', 0, - /* 390 */ 't', '7', 0, - /* 393 */ 'w', '7', 0, - /* 396 */ 'f', '1', '8', 0, - /* 400 */ 'w', '1', '8', 0, - /* 404 */ 'f', '2', '8', 0, - /* 408 */ 'w', '2', '8', 0, - /* 412 */ 'f', '8', 0, - /* 415 */ 't', '8', 0, - /* 418 */ 'w', '8', 0, - /* 421 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0, - /* 437 */ 'f', '1', '9', 0, - /* 441 */ 'w', '1', '9', 0, - /* 445 */ 'f', '2', '9', 0, - /* 449 */ 'w', '2', '9', 0, - /* 453 */ 'f', '9', 0, - /* 456 */ 't', '9', 0, - /* 459 */ 'w', '9', 0, - /* 462 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, - /* 469 */ 'r', 'a', 0, - /* 472 */ 'h', 'w', 'r', '_', 'c', 'c', 0, - /* 479 */ 'p', 'c', 0, - /* 482 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, - /* 491 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, - /* 502 */ 'h', 'i', 0, - /* 505 */ 'h', 'w', 'r', '_', 'c', 'p', 'u', 'n', 'u', 'm', 0, - /* 516 */ 'l', 'o', 0, - /* 519 */ 'z', 'e', 'r', 'o', 0, - /* 524 */ 'h', 'w', 'r', '_', 's', 'y', 'n', 'c', 'i', '_', 's', 't', 'e', 'p', 0, - /* 539 */ 'f', 'p', 0, - /* 542 */ 'g', 'p', 0, - /* 545 */ 's', 'p', 0, - /* 548 */ 'h', 'w', 'r', '_', 'c', 'c', 'r', 'e', 's', 0, - /* 558 */ 'D', 'S', 'P', 'P', 'o', 's', 0, - /* 565 */ 'a', 't', 0, - /* 568 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, - /* 578 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, - }; - + /* 0 */ "f10\0" + /* 4 */ "watchhi10\0" + /* 14 */ "watchlo10\0" + /* 24 */ "w10\0" + /* 28 */ "f20\0" + /* 32 */ "DSPOutFlag20\0" + /* 45 */ "w20\0" + /* 49 */ "f30\0" + /* 53 */ "w30\0" + /* 57 */ "a0\0" + /* 60 */ "ac0\0" + /* 64 */ "fcc0\0" + /* 69 */ "vpeconf0\0" + /* 78 */ "mvpconf0\0" + /* 87 */ "srsconf0\0" + /* 96 */ "watchhi0\0" + /* 105 */ "k0\0" + /* 108 */ "mpl0\0" + /* 113 */ "perfctl0\0" + /* 122 */ "segctl0\0" + /* 130 */ "guestctl0\0" + /* 140 */ "watchlo0\0" + /* 149 */ "entrylo0\0" + /* 158 */ "p0\0" + /* 161 */ "s0\0" + /* 164 */ "perfcnt0\0" + /* 173 */ "w0\0" + /* 176 */ "f11\0" + /* 180 */ "watchhi11\0" + /* 190 */ "watchlo11\0" + /* 200 */ "w11\0" + /* 204 */ "f21\0" + /* 208 */ "DSPOutFlag21\0" + /* 221 */ "w21\0" + /* 225 */ "f31\0" + /* 229 */ "w31\0" + /* 233 */ "usertracedata1\0" + /* 248 */ "ac1\0" + /* 252 */ "fcc1\0" + /* 257 */ "vpeconf1\0" + /* 266 */ "mvpconf1\0" + /* 275 */ "srsconf1\0" + /* 284 */ "config1\0" + /* 292 */ "kscratch1\0" + /* 302 */ "watchhi1\0" + /* 311 */ "k1\0" + /* 314 */ "mpl1\0" + /* 319 */ "perfctl1\0" + /* 328 */ "segctl1\0" + /* 336 */ "guestctl1\0" + /* 346 */ "watchlo1\0" + /* 355 */ "entrylo1\0" + /* 364 */ "p1\0" + /* 367 */ "s1\0" + /* 370 */ "perfcnt1\0" + /* 379 */ "w1\0" + /* 382 */ "f12\0" + /* 386 */ "watchhi12\0" + /* 396 */ "watchlo12\0" + /* 406 */ "w12\0" + /* 410 */ "f22\0" + /* 414 */ "DSPOutFlag22\0" + /* 427 */ "w22\0" + /* 431 */ "usertracedata2\0" + /* 446 */ "ac2\0" + /* 450 */ "fcc2\0" + /* 455 */ "srsconf2\0" + /* 464 */ "config2\0" + /* 472 */ "debug2\0" + /* 479 */ "kscratch2\0" + /* 489 */ "watchhi2\0" + /* 498 */ "tracecontrol2\0" + /* 512 */ "mpl2\0" + /* 517 */ "perfctl2\0" + /* 526 */ "segctl2\0" + /* 534 */ "guestctl2\0" + /* 544 */ "watchlo2\0" + /* 553 */ "srsmap2\0" + /* 561 */ "s2\0" + /* 564 */ "perfcnt2\0" + /* 573 */ "w2\0" + /* 576 */ "f13\0" + /* 580 */ "watchhi13\0" + /* 590 */ "watchlo13\0" + /* 600 */ "w13\0" + /* 604 */ "f23\0" + /* 608 */ "DSPOutFlag23\0" + /* 621 */ "w23\0" + /* 625 */ "a3\0" + /* 628 */ "ac3\0" + /* 632 */ "fcc3\0" + /* 637 */ "srsconf3\0" + /* 646 */ "config3\0" + /* 654 */ "kscratch3\0" + /* 664 */ "watchhi3\0" + /* 673 */ "tracecontrol3\0" + /* 687 */ "perfctl3\0" + /* 696 */ "guestctl3\0" + /* 706 */ "watchlo3\0" + /* 715 */ "s3\0" + /* 718 */ "perfcnt3\0" + /* 727 */ "w3\0" + /* 730 */ "f14\0" + /* 734 */ "watchhi14\0" + /* 744 */ "watchlo14\0" + /* 754 */ "w14\0" + /* 758 */ "f24\0" + /* 762 */ "w24\0" + /* 766 */ "a4\0" + /* 769 */ "fcc4\0" + /* 774 */ "srsconf4\0" + /* 783 */ "config4\0" + /* 791 */ "kscratch4\0" + /* 801 */ "watchhi4\0" + /* 810 */ "perfctl4\0" + /* 819 */ "watchlo4\0" + /* 828 */ "s4\0" + /* 831 */ "perfcnt4\0" + /* 840 */ "w4\0" + /* 843 */ "f15\0" + /* 847 */ "watchhi15\0" + /* 857 */ "watchlo15\0" + /* 867 */ "w15\0" + /* 871 */ "f25\0" + /* 875 */ "w25\0" + /* 879 */ "a5\0" + /* 882 */ "fcc5\0" + /* 887 */ "f5\0" + /* 890 */ "config5\0" + /* 898 */ "kscratch5\0" + /* 908 */ "watchhi5\0" + /* 917 */ "perfctl5\0" + /* 926 */ "watchlo5\0" + /* 935 */ "s5\0" + /* 938 */ "perfcnt5\0" + /* 947 */ "w5\0" + /* 950 */ "f16\0" + /* 954 */ "w16\0" + /* 958 */ "f26\0" + /* 962 */ "w26\0" + /* 966 */ "a6\0" + /* 969 */ "fcc6\0" + /* 974 */ "f6\0" + /* 977 */ "kscratch6\0" + /* 987 */ "watchhi6\0" + /* 996 */ "perfctl6\0" + /* 1005 */ "watchlo6\0" + /* 1014 */ "s6\0" + /* 1017 */ "perfcnt6\0" + /* 1026 */ "w6\0" + /* 1029 */ "f17\0" + /* 1033 */ "w17\0" + /* 1037 */ "f27\0" + /* 1041 */ "w27\0" + /* 1045 */ "a7\0" + /* 1048 */ "fcc7\0" + /* 1053 */ "f7\0" + /* 1056 */ "watchhi7\0" + /* 1065 */ "perfctl7\0" + /* 1074 */ "watchlo7\0" + /* 1083 */ "s7\0" + /* 1086 */ "perfcnt7\0" + /* 1095 */ "w7\0" + /* 1098 */ "f18\0" + /* 1102 */ "w18\0" + /* 1106 */ "f28\0" + /* 1110 */ "w28\0" + /* 1114 */ "f8\0" + /* 1117 */ "watchhi8\0" + /* 1126 */ "watchlo8\0" + /* 1135 */ "t8\0" + /* 1138 */ "w8\0" + /* 1141 */ "DSPOutFlag16_19\0" + /* 1157 */ "f19\0" + /* 1161 */ "w19\0" + /* 1165 */ "f29\0" + /* 1169 */ "w29\0" + /* 1173 */ "f9\0" + /* 1176 */ "watchhi9\0" + /* 1185 */ "watchlo9\0" + /* 1194 */ "t9\0" + /* 1197 */ "w9\0" + /* 1200 */ "DSPEFI\0" + /* 1207 */ "hwrena\0" + /* 1214 */ "ra\0" + /* 1217 */ "bevva\0" + /* 1223 */ "hwr_cc\0" + /* 1230 */ "tracedbpc\0" + /* 1240 */ "traceibpc\0" + /* 1250 */ "nestedepc\0" + /* 1260 */ "errorepc\0" + /* 1269 */ "nestedexc\0" + /* 1279 */ "wired\0" + /* 1285 */ "memorymapid\0" + /* 1297 */ "prid\0" + /* 1302 */ "debugcontextid\0" + /* 1317 */ "pwfield\0" + /* 1325 */ "tcbind\0" + /* 1332 */ "DSPCCond\0" + /* 1341 */ "tcschedule\0" + /* 1352 */ "vpeschedule\0" + /* 1364 */ "compare\0" + /* 1372 */ "ebase\0" + /* 1378 */ "cdmmbase\0" + /* 1387 */ "cmgcrbase\0" + /* 1397 */ "pwbase\0" + /* 1404 */ "cause\0" + /* 1410 */ "desave\0" + /* 1417 */ "pwsize\0" + /* 1424 */ "DSPOutFlag\0" + /* 1435 */ "xcontextconfig\0" + /* 1450 */ "debug\0" + /* 1456 */ "ddatahi\0" + /* 1464 */ "idatahi\0" + /* 1472 */ "dtaghi\0" + /* 1479 */ "itaghi\0" + /* 1486 */ "entryhi\0" + /* 1494 */ "maari\0" + /* 1500 */ "tcschefback\0" + /* 1512 */ "vpeschefback\0" + /* 1525 */ "pagemask\0" + /* 1534 */ "yqmask\0" + /* 1541 */ "userlocal\0" + /* 1551 */ "tracecontrol\0" + /* 1564 */ "vpecontrol\0" + /* 1575 */ "mvpcontrol\0" + /* 1586 */ "view_ipl\0" + /* 1595 */ "view_ripl\0" + /* 1605 */ "errctl\0" + /* 1612 */ "srsctl\0" + /* 1619 */ "intctl\0" + /* 1626 */ "pwctl\0" + /* 1632 */ "random\0" + /* 1639 */ "hwr_cpunum\0" + /* 1650 */ "pagegrain\0" + /* 1660 */ "ddatalo\0" + /* 1668 */ "idatalo\0" + /* 1676 */ "dtaglo\0" + /* 1683 */ "itaglo\0" + /* 1690 */ "zero\0" + /* 1695 */ "srsmap\0" + /* 1702 */ "hwr_synci_step\0" + /* 1717 */ "fp\0" + /* 1720 */ "gp\0" + /* 1723 */ "badinstrp\0" + /* 1733 */ "sp\0" + /* 1736 */ "maar\0" + /* 1741 */ "lladdr\0" + /* 1748 */ "badvaddr\0" + /* 1757 */ "globalnumber\0" + /* 1770 */ "cacheerr\0" + /* 1779 */ "hwr_ccres\0" + /* 1789 */ "DSPPos\0" + /* 1796 */ "tcstatus\0" + /* 1805 */ "at\0" + /* 1808 */ "gtoffset\0" + /* 1817 */ "tchalt\0" + /* 1824 */ "DSPSCount\0" + /* 1834 */ "count\0" + /* 1840 */ "tcopt\0" + /* 1846 */ "vpeopt\0" + /* 1853 */ "tcrestart\0" + /* 1863 */ "badinst\0" + /* 1871 */ "guestctl0ext\0" + /* 1884 */ "tccontext\0" + /* 1894 */ "xcontext\0" + /* 1903 */ "index\0" + /* 1909 */ "badinstrx\0" + /* 1919 */ "DSPCarry\0" +}; static const uint16_t RegAsmOffset[] = { - 565, 482, 578, 462, 491, 558, 568, 539, 542, 152, 77, 2, 332, 266, - 299, 213, 365, 479, 469, 545, 519, 37, 112, 179, 240, 40, 115, 182, - 243, 565, 45, 120, 187, 248, 281, 314, 347, 380, 2, 77, 152, 213, - 266, 299, 332, 365, 398, 435, 2, 77, 152, 213, 266, 299, 332, 365, - 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, - 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 1, 76, 151, 212, - 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, - 405, 446, 30, 105, 49, 191, 285, 351, 412, 0, 150, 264, 330, 396, - 8, 158, 272, 338, 404, 29, 12, 87, 162, 223, 49, 124, 191, 252, - 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, 297, 330, 363, - 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, 29, 104, - 44, 119, 186, 247, 280, 313, 346, 379, 2, 77, 152, 213, 266, 299, - 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, - 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 539, 49, - 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, - 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, - 445, 29, 104, 542, 40, 115, 182, 243, 505, 524, 472, 548, 266, 299, - 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, - 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 52, 127, - 40, 115, 182, 243, 55, 130, 194, 60, 135, 199, 469, 63, 138, 202, - 255, 288, 321, 354, 387, 545, 66, 141, 205, 258, 291, 324, 357, 390, - 415, 456, 69, 144, 72, 147, 208, 261, 294, 327, 360, 393, 418, 459, - 4, 79, 154, 215, 268, 301, 334, 367, 400, 441, 25, 100, 175, 236, - 276, 309, 342, 375, 408, 449, 33, 108, 519, 37, 112, 179, 240, 40, - 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, - 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, - 404, 445, 29, 104, 421, 502, 52, 127, 516, 63, 138, 202, 255, 288, - 321, 354, 387, 66, 141, 205, 258, 291, 324, 357, 390, 415, 456, 69, - 144, + 178, 1805, 1332, 1919, 1200, 1424, 1789, 1824, 1717, 1717, 1720, 1720, 384, 178, + 2, 952, 732, 845, 578, 1031, 1237, 1214, 1214, 1733, 1733, 1690, 1690, 732, + 845, 952, 1031, 60, 248, 446, 628, 178, 2, 178, 384, 578, 732, 845, + 952, 1031, 1100, 1155, 2, 178, 384, 578, 732, 845, 952, 1031, 1100, 1155, + 2, 178, 384, 578, 732, 845, 952, 1031, 1100, 1155, 1, 177, 383, 577, + 731, 844, 951, 1030, 1099, 1154, 29, 205, 411, 605, 759, 872, 959, 1038, + 1107, 1166, 50, 226, 1, 177, 383, 577, 731, 844, 951, 1030, 1099, 1154, + 29, 205, 411, 605, 759, 872, 959, 1038, 1107, 1166, 50, 226, 1, 177, + 383, 577, 731, 844, 951, 1030, 1099, 1154, 29, 205, 411, 605, 759, 872, + 959, 1038, 1107, 1166, 50, 226, 75, 461, 780, 974, 1114, 0, 382, 730, + 950, 1098, 28, 410, 758, 958, 1106, 49, 32, 208, 414, 608, 75, 263, + 461, 643, 780, 887, 974, 1053, 1114, 1173, 0, 176, 382, 576, 730, 843, + 950, 1029, 1098, 1157, 28, 204, 410, 604, 758, 871, 958, 1037, 1106, 1165, + 49, 225, 64, 252, 450, 632, 769, 882, 969, 1048, 2, 178, 384, 578, + 732, 845, 952, 1031, 1100, 1155, 1, 177, 383, 577, 731, 844, 951, 1030, + 1099, 1154, 29, 205, 411, 605, 759, 872, 959, 1038, 1107, 1166, 50, 226, + 1717, 75, 263, 461, 643, 780, 887, 974, 1053, 1114, 1173, 0, 176, 382, + 576, 730, 843, 950, 1029, 1098, 1157, 28, 204, 410, 604, 758, 871, 958, + 1037, 1106, 1165, 49, 225, 1720, 60, 248, 446, 628, 1639, 1702, 1223, 1779, + 732, 845, 952, 1031, 1100, 1155, 1, 177, 383, 577, 731, 844, 951, 1030, + 1099, 1154, 29, 205, 411, 605, 759, 872, 959, 1038, 1107, 1166, 50, 226, + 959, 1038, 60, 248, 446, 628, 108, 314, 512, 1100, 1155, 1, 177, 383, + 577, 731, 844, 951, 1030, 1099, 1154, 29, 205, 411, 605, 759, 872, 959, + 1038, 1107, 1166, 50, 226, 158, 364, 558, 1214, 951, 1030, 1099, 1154, 29, + 205, 411, 605, 1733, 1100, 1155, 1, 177, 383, 577, 731, 844, 759, 872, + 384, 578, 173, 379, 573, 727, 840, 947, 1026, 1095, 1138, 1197, 24, 200, + 406, 600, 754, 867, 954, 1033, 1102, 1161, 45, 221, 427, 621, 762, 875, + 962, 1041, 1110, 1169, 53, 229, 1690, 57, 245, 443, 625, 766, 879, 966, + 1045, 1863, 1723, 1909, 1748, 1217, 1770, 1404, 1378, 1387, 1364, 1443, 1886, 1436, + 1834, 1456, 1660, 1450, 1302, 1255, 1410, 1472, 1676, 1372, 1486, 1256, 1605, 1260, + 1757, 1808, 1207, 1464, 1668, 1903, 1619, 1479, 1683, 1741, 1736, 1494, 1285, 1575, + 1250, 1269, 1650, 1525, 1297, 1397, 1626, 1317, 1417, 1632, 1612, 1695, 1798, 1325, + 1884, 1817, 1840, 1853, 1341, 1500, 1796, 1551, 1230, 1240, 1541, 1586, 1595, 1576, + 1564, 1846, 1352, 1512, 1279, 1894, 1435, 1534, 105, 311, 161, 367, 561, 715, + 828, 935, 1014, 1083, 170, 376, 570, 724, 837, 944, 1135, 1194, 732, 845, + 952, 1031, 60, 284, 464, 646, 783, 890, 472, 149, 355, 130, 336, 534, + 696, 292, 479, 654, 791, 898, 977, 78, 266, 164, 370, 564, 718, 831, + 938, 1017, 1086, 113, 319, 517, 687, 810, 917, 996, 1065, 122, 328, 526, + 87, 275, 455, 637, 774, 553, 498, 673, 233, 431, 69, 257, 96, 302, + 489, 664, 801, 908, 987, 1056, 1117, 1176, 4, 180, 386, 580, 734, 847, + 140, 346, 544, 706, 819, 926, 1005, 1074, 1126, 1185, 14, 190, 396, 590, + 744, 857, 75, 263, 461, 643, 780, 887, 974, 1053, 1114, 1173, 0, 176, + 382, 576, 730, 843, 950, 1029, 1098, 1157, 28, 204, 410, 604, 758, 871, + 958, 1037, 1106, 1165, 49, 225, 1141, 1461, 959, 1038, 1665, 951, 1030, 1099, + 1154, 29, 205, 411, 605, 1100, 1155, 1, 177, 383, 577, 731, 844, 759, + 872, 384, 578, 1871, }; - //printf("==== RegNo = %u, id = %s\n", RegNo, AsmStrs+RegAsmOffset[RegNo-1]); - //int i; - //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) - // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); - //printf("-------------------------\n"); + assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && + "Invalid alt name index for register!"); return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; -#endif +#endif // CAPSTONE_DIET } - #ifdef PRINT_ALIAS_INSTR #undef PRINT_ALIAS_INSTR -static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, SStream *OS) -{ +static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) { +#ifndef CAPSTONE_DIET + static const PatternsForOpcode OpToPatterns[] = { + {Mips_MFTACX, 0, 1 }, + {Mips_MFTACX_NM, 1, 1 }, + {Mips_MFTC0, 2, 1 }, + {Mips_MFTC0_NM, 3, 1 }, + {Mips_MFTHI, 4, 1 }, + {Mips_MFTHI_NM, 5, 1 }, + {Mips_MFTLO, 6, 1 }, + {Mips_MFTLO_NM, 7, 1 }, + {Mips_MTTACX, 8, 1 }, + {Mips_MTTACX_NM, 9, 1 }, + {Mips_MTTC0, 10, 1 }, + {Mips_MTTC0_NM, 11, 1 }, + {Mips_MTTHI, 12, 1 }, + {Mips_MTTHI_NM, 13, 1 }, + {Mips_MTTLO, 14, 1 }, + {Mips_MTTLO_NM, 15, 1 }, + {Mips_NORImm, 16, 1 }, + {Mips_NORImm64, 17, 1 }, + {Mips_SLTImm64, 18, 1 }, + {Mips_SLTUImm64, 19, 1 }, + {Mips_ADDIUGP48_NM, 20, 1 }, + {Mips_ADDIUGPB_NM, 21, 1 }, + {Mips_ADDIUGPW_NM, 22, 1 }, + {Mips_ADDIUPC, 23, 1 }, + {Mips_ADDIUPC_MMR6, 24, 1 }, + {Mips_ADDu, 25, 1 }, + {Mips_BC1F, 26, 1 }, + {Mips_BC1FL, 27, 1 }, + {Mips_BC1F_MM, 28, 1 }, + {Mips_BC1T, 29, 1 }, + {Mips_BC1TL, 30, 1 }, + {Mips_BC1T_MM, 31, 1 }, + {Mips_BEQC16_NM, 32, 1 }, + {Mips_BEQC_NM, 33, 2 }, + {Mips_BEQL, 35, 1 }, + {Mips_BGEZAL, 36, 1 }, + {Mips_BGEZAL_MM, 37, 1 }, + {Mips_BNEC16_NM, 38, 1 }, + {Mips_BNEC_NM, 39, 2 }, + {Mips_BNEL, 41, 1 }, + {Mips_BREAK, 42, 2 }, + {Mips_BREAK_MM, 44, 2 }, + {Mips_C_EQ_D32, 46, 1 }, + {Mips_C_EQ_D32_MM, 47, 1 }, + {Mips_C_EQ_D64, 48, 1 }, + {Mips_C_EQ_D64_MM, 49, 1 }, + {Mips_C_EQ_S, 50, 1 }, + {Mips_C_EQ_S_MM, 51, 1 }, + {Mips_C_F_D32, 52, 1 }, + {Mips_C_F_D32_MM, 53, 1 }, + {Mips_C_F_D64, 54, 1 }, + {Mips_C_F_D64_MM, 55, 1 }, + {Mips_C_F_S, 56, 1 }, + {Mips_C_F_S_MM, 57, 1 }, + {Mips_C_LE_D32, 58, 1 }, + {Mips_C_LE_D32_MM, 59, 1 }, + {Mips_C_LE_D64, 60, 1 }, + {Mips_C_LE_D64_MM, 61, 1 }, + {Mips_C_LE_S, 62, 1 }, + {Mips_C_LE_S_MM, 63, 1 }, + {Mips_C_LT_D32, 64, 1 }, + {Mips_C_LT_D32_MM, 65, 1 }, + {Mips_C_LT_D64, 66, 1 }, + {Mips_C_LT_D64_MM, 67, 1 }, + {Mips_C_LT_S, 68, 1 }, + {Mips_C_LT_S_MM, 69, 1 }, + {Mips_C_NGE_D32, 70, 1 }, + {Mips_C_NGE_D32_MM, 71, 1 }, + {Mips_C_NGE_D64, 72, 1 }, + {Mips_C_NGE_D64_MM, 73, 1 }, + {Mips_C_NGE_S, 74, 1 }, + {Mips_C_NGE_S_MM, 75, 1 }, + {Mips_C_NGLE_D32, 76, 1 }, + {Mips_C_NGLE_D32_MM, 77, 1 }, + {Mips_C_NGLE_D64, 78, 1 }, + {Mips_C_NGLE_D64_MM, 79, 1 }, + {Mips_C_NGLE_S, 80, 1 }, + {Mips_C_NGLE_S_MM, 81, 1 }, + {Mips_C_NGL_D32, 82, 1 }, + {Mips_C_NGL_D32_MM, 83, 1 }, + {Mips_C_NGL_D64, 84, 1 }, + {Mips_C_NGL_D64_MM, 85, 1 }, + {Mips_C_NGL_S, 86, 1 }, + {Mips_C_NGL_S_MM, 87, 1 }, + {Mips_C_NGT_D32, 88, 1 }, + {Mips_C_NGT_D32_MM, 89, 1 }, + {Mips_C_NGT_D64, 90, 1 }, + {Mips_C_NGT_D64_MM, 91, 1 }, + {Mips_C_NGT_S, 92, 1 }, + {Mips_C_NGT_S_MM, 93, 1 }, + {Mips_C_OLE_D32, 94, 1 }, + {Mips_C_OLE_D32_MM, 95, 1 }, + {Mips_C_OLE_D64, 96, 1 }, + {Mips_C_OLE_D64_MM, 97, 1 }, + {Mips_C_OLE_S, 98, 1 }, + {Mips_C_OLE_S_MM, 99, 1 }, + {Mips_C_OLT_D32, 100, 1 }, + {Mips_C_OLT_D32_MM, 101, 1 }, + {Mips_C_OLT_D64, 102, 1 }, + {Mips_C_OLT_D64_MM, 103, 1 }, + {Mips_C_OLT_S, 104, 1 }, + {Mips_C_OLT_S_MM, 105, 1 }, + {Mips_C_SEQ_D32, 106, 1 }, + {Mips_C_SEQ_D32_MM, 107, 1 }, + {Mips_C_SEQ_D64, 108, 1 }, + {Mips_C_SEQ_D64_MM, 109, 1 }, + {Mips_C_SEQ_S, 110, 1 }, + {Mips_C_SEQ_S_MM, 111, 1 }, + {Mips_C_SF_D32, 112, 1 }, + {Mips_C_SF_D32_MM, 113, 1 }, + {Mips_C_SF_D64, 114, 1 }, + {Mips_C_SF_D64_MM, 115, 1 }, + {Mips_C_SF_S, 116, 1 }, + {Mips_C_SF_S_MM, 117, 1 }, + {Mips_C_UEQ_D32, 118, 1 }, + {Mips_C_UEQ_D32_MM, 119, 1 }, + {Mips_C_UEQ_D64, 120, 1 }, + {Mips_C_UEQ_D64_MM, 121, 1 }, + {Mips_C_UEQ_S, 122, 1 }, + {Mips_C_UEQ_S_MM, 123, 1 }, + {Mips_C_ULE_D32, 124, 1 }, + {Mips_C_ULE_D32_MM, 125, 1 }, + {Mips_C_ULE_D64, 126, 1 }, + {Mips_C_ULE_D64_MM, 127, 1 }, + {Mips_C_ULE_S, 128, 1 }, + {Mips_C_ULE_S_MM, 129, 1 }, + {Mips_C_ULT_D32, 130, 1 }, + {Mips_C_ULT_D32_MM, 131, 1 }, + {Mips_C_ULT_D64, 132, 1 }, + {Mips_C_ULT_D64_MM, 133, 1 }, + {Mips_C_ULT_S, 134, 1 }, + {Mips_C_ULT_S_MM, 135, 1 }, + {Mips_C_UN_D32, 136, 1 }, + {Mips_C_UN_D32_MM, 137, 1 }, + {Mips_C_UN_D64, 138, 1 }, + {Mips_C_UN_D64_MM, 139, 1 }, + {Mips_C_UN_S, 140, 1 }, + {Mips_C_UN_S_MM, 141, 1 }, + {Mips_DADDu, 142, 1 }, + {Mips_DI, 143, 1 }, + {Mips_DIV, 144, 1 }, + {Mips_DIVU, 145, 1 }, + {Mips_DI_MM, 146, 1 }, + {Mips_DI_MMR6, 147, 1 }, + {Mips_DI_NM, 148, 1 }, + {Mips_DMT, 149, 1 }, + {Mips_DMT_NM, 150, 1 }, + {Mips_DSUB, 151, 2 }, + {Mips_DSUBu, 153, 2 }, + {Mips_DVPE, 155, 1 }, + {Mips_DVPE_NM, 156, 1 }, + {Mips_EI, 157, 1 }, + {Mips_EI_MM, 158, 1 }, + {Mips_EI_MMR6, 159, 1 }, + {Mips_EI_NM, 160, 1 }, + {Mips_EMT, 161, 1 }, + {Mips_EMT_NM, 162, 1 }, + {Mips_EVPE, 163, 1 }, + {Mips_EVPE_NM, 164, 1 }, + {Mips_HYPCALL, 165, 1 }, + {Mips_HYPCALL_MM, 166, 1 }, + {Mips_JALR, 167, 1 }, + {Mips_JALR64, 168, 1 }, + {Mips_JALRCHB_NM, 169, 1 }, + {Mips_JALRC_HB_MMR6, 170, 1 }, + {Mips_JALRC_MMR6, 171, 1 }, + {Mips_JALR_HB, 172, 1 }, + {Mips_JALR_HB64, 173, 1 }, + {Mips_JIALC, 174, 1 }, + {Mips_JIALC64, 175, 1 }, + {Mips_JIC, 176, 1 }, + {Mips_JIC64, 177, 1 }, + {Mips_MFC0_NM, 178, 1 }, + {Mips_MFHC0_NM, 179, 1 }, + {Mips_MOVE16_MM, 180, 1 }, + {Mips_MTC0_NM, 181, 1 }, + {Mips_MTHC0_NM, 182, 1 }, + {Mips_Move32R16, 183, 1 }, + {Mips_NOR_NM, 184, 1 }, + {Mips_OR, 185, 1 }, + {Mips_OR64, 186, 1 }, + {Mips_RDHWR, 187, 1 }, + {Mips_RDHWR64, 188, 1 }, + {Mips_RDHWR_MM, 189, 1 }, + {Mips_RDHWR_MMR6, 190, 1 }, + {Mips_RESTOREJRC16_NM, 191, 1 }, + {Mips_RESTOREJRC_NM, 192, 1 }, + {Mips_RESTORE_NM, 193, 1 }, + {Mips_ROTX_NM, 194, 3 }, + {Mips_SAVE16_NM, 197, 1 }, + {Mips_SAVE_NM, 198, 1 }, + {Mips_SDBBP, 199, 1 }, + {Mips_SDBBP_MMR6, 200, 1 }, + {Mips_SDBBP_R6, 201, 1 }, + {Mips_SIGRIE, 202, 1 }, + {Mips_SIGRIE_MMR6, 203, 1 }, + {Mips_SLL, 204, 1 }, + {Mips_SLL_MM, 205, 1 }, + {Mips_SLL_MMR6, 206, 1 }, + {Mips_SUB, 207, 2 }, + {Mips_SUBU_MMR6, 209, 2 }, + {Mips_SUB_MM, 211, 2 }, + {Mips_SUB_MMR6, 213, 2 }, + {Mips_SUBu, 215, 2 }, + {Mips_SUBu_MM, 217, 2 }, + {Mips_SWSP_MM, 219, 1 }, + {Mips_SYNC, 220, 1 }, + {Mips_SYNC_MM, 221, 1 }, + {Mips_SYNC_MMR6, 222, 1 }, + {Mips_SYNC_NM, 223, 6 }, + {Mips_SYSCALL, 229, 1 }, + {Mips_SYSCALL_MM, 230, 1 }, + {Mips_TEQ, 231, 1 }, + {Mips_TEQ_MM, 232, 1 }, + {Mips_TGE, 233, 1 }, + {Mips_TGEU, 234, 1 }, + {Mips_TGEU_MM, 235, 1 }, + {Mips_TGE_MM, 236, 1 }, + {Mips_TLT, 237, 1 }, + {Mips_TLTU, 238, 1 }, + {Mips_TLTU_MM, 239, 1 }, + {Mips_TLT_MM, 240, 1 }, + {Mips_TNE, 241, 1 }, + {Mips_TNE_MM, 242, 1 }, + {Mips_WAIT_MM, 243, 1 }, + {Mips_WAIT_NM, 244, 1 }, + {Mips_WRDSP, 245, 1 }, + {Mips_WRDSP_MM, 246, 1 }, + {Mips_YIELD, 247, 1 }, + {Mips_YIELD_NM, 248, 1 }, + {0}, }; + + static const AliasPattern Patterns[] = { + // Mips_MFTACX - 0 + {0, 0, 2, 5 }, + // Mips_MFTACX_NM - 1 + {0, 5, 2, 4 }, + // Mips_MFTC0 - 2 + {10, 9, 3, 6 }, + // Mips_MFTC0_NM - 3 + {10, 15, 3, 5 }, + // Mips_MFTHI - 4 + {23, 20, 2, 5 }, + // Mips_MFTHI_NM - 5 + {23, 25, 2, 4 }, + // Mips_MFTLO - 6 + {32, 29, 2, 5 }, + // Mips_MFTLO_NM - 7 + {32, 34, 2, 4 }, + // Mips_MTTACX - 8 + {41, 38, 2, 5 }, + // Mips_MTTACX_NM - 9 + {41, 43, 2, 4 }, + // Mips_MTTC0 - 10 + {51, 47, 3, 6 }, + // Mips_MTTC0_NM - 11 + {51, 53, 3, 5 }, + // Mips_MTTHI - 12 + {64, 58, 2, 5 }, + // Mips_MTTHI_NM - 13 + {64, 63, 2, 4 }, + // Mips_MTTLO - 14 + {73, 67, 2, 5 }, + // Mips_MTTLO_NM - 15 + {73, 72, 2, 4 }, + // Mips_NORImm - 16 + {82, 76, 3, 3 }, + // Mips_NORImm64 - 17 + {82, 79, 3, 3 }, + // Mips_SLTImm64 - 18 + {93, 82, 3, 3 }, + // Mips_SLTUImm64 - 19 + {104, 85, 3, 3 }, + // Mips_ADDIUGP48_NM - 20 + {116, 88, 3, 3 }, + // Mips_ADDIUGPB_NM - 21 + {137, 91, 3, 3 }, + // Mips_ADDIUGPW_NM - 22 + {156, 94, 3, 3 }, + // Mips_ADDIUPC - 23 + {175, 97, 2, 3 }, + // Mips_ADDIUPC_MMR6 - 24 + {175, 100, 2, 3 }, + // Mips_ADDu - 25 + {187, 103, 3, 7 }, + // Mips_BC1F - 26 + {199, 110, 2, 6 }, + // Mips_BC1FL - 27 + {209, 116, 2, 7 }, + // Mips_BC1F_MM - 28 + {199, 123, 2, 4 }, + // Mips_BC1T - 29 + {220, 127, 2, 6 }, + // Mips_BC1TL - 30 + {230, 133, 2, 7 }, + // Mips_BC1T_MM - 31 + {220, 140, 2, 4 }, + // Mips_BEQC16_NM - 32 + {241, 144, 3, 3 }, + // Mips_BEQC_NM - 33 + {259, 147, 3, 3 }, + {274, 150, 3, 3 }, + // Mips_BEQL - 35 + {289, 153, 3, 6 }, + // Mips_BGEZAL - 36 + {304, 159, 2, 6 }, + // Mips_BGEZAL_MM - 37 + {304, 165, 2, 3 }, + // Mips_BNEC16_NM - 38 + {313, 168, 3, 3 }, + // Mips_BNEC_NM - 39 + {331, 171, 3, 3 }, + {346, 174, 3, 3 }, + // Mips_BNEL - 41 + {361, 177, 3, 6 }, + // Mips_BREAK - 42 + {376, 183, 2, 5 }, + {382, 188, 2, 5 }, + // Mips_BREAK_MM - 44 + {376, 193, 2, 3 }, + {382, 196, 2, 3 }, + // Mips_C_EQ_D32 - 46 + {393, 199, 3, 9 }, + // Mips_C_EQ_D32_MM - 47 + {393, 208, 3, 7 }, + // Mips_C_EQ_D64 - 48 + {393, 215, 3, 9 }, + // Mips_C_EQ_D64_MM - 49 + {393, 224, 3, 7 }, + // Mips_C_EQ_S - 50 + {407, 231, 3, 8 }, + // Mips_C_EQ_S_MM - 51 + {407, 239, 3, 6 }, + // Mips_C_F_D32 - 52 + {421, 245, 3, 9 }, + // Mips_C_F_D32_MM - 53 + {421, 254, 3, 7 }, + // Mips_C_F_D64 - 54 + {421, 261, 3, 9 }, + // Mips_C_F_D64_MM - 55 + {421, 270, 3, 7 }, + // Mips_C_F_S - 56 + {434, 277, 3, 8 }, + // Mips_C_F_S_MM - 57 + {434, 285, 3, 6 }, + // Mips_C_LE_D32 - 58 + {447, 291, 3, 9 }, + // Mips_C_LE_D32_MM - 59 + {447, 300, 3, 7 }, + // Mips_C_LE_D64 - 60 + {447, 307, 3, 9 }, + // Mips_C_LE_D64_MM - 61 + {447, 316, 3, 7 }, + // Mips_C_LE_S - 62 + {461, 323, 3, 8 }, + // Mips_C_LE_S_MM - 63 + {461, 331, 3, 6 }, + // Mips_C_LT_D32 - 64 + {475, 337, 3, 9 }, + // Mips_C_LT_D32_MM - 65 + {475, 346, 3, 7 }, + // Mips_C_LT_D64 - 66 + {475, 353, 3, 9 }, + // Mips_C_LT_D64_MM - 67 + {475, 362, 3, 7 }, + // Mips_C_LT_S - 68 + {489, 369, 3, 8 }, + // Mips_C_LT_S_MM - 69 + {489, 377, 3, 6 }, + // Mips_C_NGE_D32 - 70 + {503, 383, 3, 9 }, + // Mips_C_NGE_D32_MM - 71 + {503, 392, 3, 7 }, + // Mips_C_NGE_D64 - 72 + {503, 399, 3, 9 }, + // Mips_C_NGE_D64_MM - 73 + {503, 408, 3, 7 }, + // Mips_C_NGE_S - 74 + {518, 415, 3, 8 }, + // Mips_C_NGE_S_MM - 75 + {518, 423, 3, 6 }, + // Mips_C_NGLE_D32 - 76 + {533, 429, 3, 9 }, + // Mips_C_NGLE_D32_MM - 77 + {533, 438, 3, 7 }, + // Mips_C_NGLE_D64 - 78 + {533, 445, 3, 9 }, + // Mips_C_NGLE_D64_MM - 79 + {533, 454, 3, 7 }, + // Mips_C_NGLE_S - 80 + {549, 461, 3, 8 }, + // Mips_C_NGLE_S_MM - 81 + {549, 469, 3, 6 }, + // Mips_C_NGL_D32 - 82 + {565, 475, 3, 9 }, + // Mips_C_NGL_D32_MM - 83 + {565, 484, 3, 7 }, + // Mips_C_NGL_D64 - 84 + {565, 491, 3, 9 }, + // Mips_C_NGL_D64_MM - 85 + {565, 500, 3, 7 }, + // Mips_C_NGL_S - 86 + {580, 507, 3, 8 }, + // Mips_C_NGL_S_MM - 87 + {580, 515, 3, 6 }, + // Mips_C_NGT_D32 - 88 + {595, 521, 3, 9 }, + // Mips_C_NGT_D32_MM - 89 + {595, 530, 3, 7 }, + // Mips_C_NGT_D64 - 90 + {595, 537, 3, 9 }, + // Mips_C_NGT_D64_MM - 91 + {595, 546, 3, 7 }, + // Mips_C_NGT_S - 92 + {610, 553, 3, 8 }, + // Mips_C_NGT_S_MM - 93 + {610, 561, 3, 6 }, + // Mips_C_OLE_D32 - 94 + {625, 567, 3, 9 }, + // Mips_C_OLE_D32_MM - 95 + {625, 576, 3, 7 }, + // Mips_C_OLE_D64 - 96 + {625, 583, 3, 9 }, + // Mips_C_OLE_D64_MM - 97 + {625, 592, 3, 7 }, + // Mips_C_OLE_S - 98 + {640, 599, 3, 8 }, + // Mips_C_OLE_S_MM - 99 + {640, 607, 3, 6 }, + // Mips_C_OLT_D32 - 100 + {655, 613, 3, 9 }, + // Mips_C_OLT_D32_MM - 101 + {655, 622, 3, 7 }, + // Mips_C_OLT_D64 - 102 + {655, 629, 3, 9 }, + // Mips_C_OLT_D64_MM - 103 + {655, 638, 3, 7 }, + // Mips_C_OLT_S - 104 + {670, 645, 3, 8 }, + // Mips_C_OLT_S_MM - 105 + {670, 653, 3, 6 }, + // Mips_C_SEQ_D32 - 106 + {685, 659, 3, 9 }, + // Mips_C_SEQ_D32_MM - 107 + {685, 668, 3, 7 }, + // Mips_C_SEQ_D64 - 108 + {685, 675, 3, 9 }, + // Mips_C_SEQ_D64_MM - 109 + {685, 684, 3, 7 }, + // Mips_C_SEQ_S - 110 + {700, 691, 3, 8 }, + // Mips_C_SEQ_S_MM - 111 + {700, 699, 3, 6 }, + // Mips_C_SF_D32 - 112 + {715, 705, 3, 9 }, + // Mips_C_SF_D32_MM - 113 + {715, 714, 3, 7 }, + // Mips_C_SF_D64 - 114 + {715, 721, 3, 9 }, + // Mips_C_SF_D64_MM - 115 + {715, 730, 3, 7 }, + // Mips_C_SF_S - 116 + {729, 737, 3, 8 }, + // Mips_C_SF_S_MM - 117 + {729, 745, 3, 6 }, + // Mips_C_UEQ_D32 - 118 + {743, 751, 3, 9 }, + // Mips_C_UEQ_D32_MM - 119 + {743, 760, 3, 7 }, + // Mips_C_UEQ_D64 - 120 + {743, 767, 3, 9 }, + // Mips_C_UEQ_D64_MM - 121 + {743, 776, 3, 7 }, + // Mips_C_UEQ_S - 122 + {758, 783, 3, 8 }, + // Mips_C_UEQ_S_MM - 123 + {758, 791, 3, 6 }, + // Mips_C_ULE_D32 - 124 + {773, 797, 3, 9 }, + // Mips_C_ULE_D32_MM - 125 + {773, 806, 3, 7 }, + // Mips_C_ULE_D64 - 126 + {773, 813, 3, 9 }, + // Mips_C_ULE_D64_MM - 127 + {773, 822, 3, 7 }, + // Mips_C_ULE_S - 128 + {788, 829, 3, 8 }, + // Mips_C_ULE_S_MM - 129 + {788, 837, 3, 6 }, + // Mips_C_ULT_D32 - 130 + {803, 843, 3, 9 }, + // Mips_C_ULT_D32_MM - 131 + {803, 852, 3, 7 }, + // Mips_C_ULT_D64 - 132 + {803, 859, 3, 9 }, + // Mips_C_ULT_D64_MM - 133 + {803, 868, 3, 7 }, + // Mips_C_ULT_S - 134 + {818, 875, 3, 8 }, + // Mips_C_ULT_S_MM - 135 + {818, 883, 3, 6 }, + // Mips_C_UN_D32 - 136 + {833, 889, 3, 9 }, + // Mips_C_UN_D32_MM - 137 + {833, 898, 3, 7 }, + // Mips_C_UN_D64 - 138 + {833, 905, 3, 9 }, + // Mips_C_UN_D64_MM - 139 + {833, 914, 3, 7 }, + // Mips_C_UN_S - 140 + {847, 921, 3, 8 }, + // Mips_C_UN_S_MM - 141 + {847, 929, 3, 6 }, + // Mips_DADDu - 142 + {187, 935, 3, 5 }, + // Mips_DI - 143 + {861, 940, 1, 5 }, + // Mips_DIV - 144 + {864, 945, 3, 5 }, + // Mips_DIVU - 145 + {875, 950, 3, 5 }, + // Mips_DI_MM - 146 + {861, 955, 1, 2 }, + // Mips_DI_MMR6 - 147 + {861, 957, 1, 3 }, + // Mips_DI_NM - 148 + {861, 960, 1, 2 }, + // Mips_DMT - 149 + {887, 962, 1, 4 }, + // Mips_DMT_NM - 150 + {887, 966, 1, 3 }, + // Mips_DSUB - 151 + {891, 969, 3, 6 }, + {903, 975, 3, 6 }, + // Mips_DSUBu - 153 + {911, 981, 3, 6 }, + {924, 987, 3, 6 }, + // Mips_DVPE - 155 + {933, 993, 1, 4 }, + // Mips_DVPE_NM - 156 + {933, 997, 1, 3 }, + // Mips_EI - 157 + {938, 1000, 1, 5 }, + // Mips_EI_MM - 158 + {938, 1005, 1, 2 }, + // Mips_EI_MMR6 - 159 + {938, 1007, 1, 3 }, + // Mips_EI_NM - 160 + {938, 1010, 1, 2 }, + // Mips_EMT - 161 + {941, 1012, 1, 4 }, + // Mips_EMT_NM - 162 + {941, 1016, 1, 3 }, + // Mips_EVPE - 163 + {945, 1019, 1, 4 }, + // Mips_EVPE_NM - 164 + {945, 1023, 1, 3 }, + // Mips_HYPCALL - 165 + {950, 1026, 1, 6 }, + // Mips_HYPCALL_MM - 166 + {950, 1032, 1, 4 }, + // Mips_JALR - 167 + {958, 1036, 2, 6 }, + // Mips_JALR64 - 168 + {958, 1042, 2, 4 }, + // Mips_JALRCHB_NM - 169 + {964, 1046, 2, 3 }, + // Mips_JALRC_HB_MMR6 - 170 + {974, 1049, 2, 4 }, + // Mips_JALRC_MMR6 - 171 + {986, 1053, 2, 4 }, + // Mips_JALR_HB - 172 + {995, 1057, 2, 6 }, + // Mips_JALR_HB64 - 173 + {995, 1063, 2, 5 }, + // Mips_JIALC - 174 + {1006, 1068, 2, 6 }, + // Mips_JIALC64 - 175 + {1006, 1074, 2, 4 }, + // Mips_JIC - 176 + {1015, 1078, 2, 5 }, + // Mips_JIC64 - 177 + {1015, 1083, 2, 4 }, + // Mips_MFC0_NM - 178 + {1022, 1087, 3, 4 }, + // Mips_MFHC0_NM - 179 + {1034, 1091, 3, 4 }, + // Mips_MOVE16_MM - 180 + {1047, 1095, 2, 3 }, + // Mips_MTC0_NM - 181 + {1051, 1098, 3, 4 }, + // Mips_MTHC0_NM - 182 + {1063, 1102, 3, 4 }, + // Mips_Move32R16 - 183 + {1047, 1106, 2, 3 }, + // Mips_NOR_NM - 184 + {1076, 1109, 3, 4 }, + // Mips_OR - 185 + {187, 1113, 3, 7 }, + // Mips_OR64 - 186 + {187, 1120, 3, 5 }, + // Mips_RDHWR - 187 + {1087, 1125, 3, 6 }, + // Mips_RDHWR64 - 188 + {1087, 1131, 3, 4 }, + // Mips_RDHWR_MM - 189 + {1087, 1135, 3, 5 }, + // Mips_RDHWR_MMR6 - 190 + {1087, 1140, 3, 5 }, + // Mips_RESTOREJRC16_NM - 191 + {1100, 1145, 2, 2 }, + // Mips_RESTOREJRC_NM - 192 + {1117, 1147, 2, 2 }, + // Mips_RESTORE_NM - 193 + {1134, 1149, 2, 2 }, + // Mips_ROTX_NM - 194 + {1147, 1151, 5, 6 }, + {1162, 1157, 5, 6 }, + {1177, 1163, 5, 6 }, + // Mips_SAVE16_NM - 197 + {1193, 1169, 2, 2 }, + // Mips_SAVE_NM - 198 + {1203, 1171, 2, 2 }, + // Mips_SDBBP - 199 + {1213, 1173, 1, 5 }, + // Mips_SDBBP_MMR6 - 200 + {1213, 1178, 1, 3 }, + // Mips_SDBBP_R6 - 201 + {1213, 1181, 1, 4 }, + // Mips_SIGRIE - 202 + {1219, 1185, 1, 4 }, + // Mips_SIGRIE_MMR6 - 203 + {1219, 1189, 1, 3 }, + // Mips_SLL - 204 + {1047, 1192, 3, 6 }, + // Mips_SLL_MM - 205 + {1047, 1198, 3, 4 }, + // Mips_SLL_MMR6 - 206 + {1047, 1202, 3, 5 }, + // Mips_SUB - 207 + {1226, 1207, 3, 6 }, + {1237, 1213, 3, 6 }, + // Mips_SUBU_MMR6 - 209 + {1244, 1219, 3, 5 }, + {1256, 1224, 3, 5 }, + // Mips_SUB_MM - 211 + {1226, 1229, 3, 5 }, + {1237, 1234, 3, 5 }, + // Mips_SUB_MMR6 - 213 + {1226, 1239, 3, 5 }, + {1237, 1244, 3, 5 }, + // Mips_SUBu - 215 + {1244, 1249, 3, 6 }, + {1256, 1255, 3, 6 }, + // Mips_SUBu_MM - 217 + {1244, 1261, 3, 5 }, + {1256, 1266, 3, 5 }, + // Mips_SWSP_MM - 219 + {1264, 1271, 3, 2 }, + // Mips_SYNC - 220 + {1276, 1273, 1, 5 }, + // Mips_SYNC_MM - 221 + {1276, 1278, 1, 2 }, + // Mips_SYNC_MMR6 - 222 + {1276, 1280, 1, 3 }, + // Mips_SYNC_NM - 223 + {1276, 1283, 1, 2 }, + {1281, 1285, 1, 2 }, + {1290, 1287, 1, 2 }, + {1298, 1289, 1, 2 }, + {1311, 1291, 1, 2 }, + {1324, 1293, 1, 2 }, + // Mips_SYSCALL - 229 + {1333, 1295, 1, 4 }, + // Mips_SYSCALL_MM - 230 + {1333, 1299, 1, 2 }, + // Mips_TEQ - 231 + {1341, 1301, 3, 7 }, + // Mips_TEQ_MM - 232 + {1341, 1308, 3, 4 }, + // Mips_TGE - 233 + {1352, 1312, 3, 7 }, + // Mips_TGEU - 234 + {1363, 1319, 3, 7 }, + // Mips_TGEU_MM - 235 + {1363, 1326, 3, 4 }, + // Mips_TGE_MM - 236 + {1352, 1330, 3, 4 }, + // Mips_TLT - 237 + {1375, 1334, 3, 7 }, + // Mips_TLTU - 238 + {1386, 1341, 3, 7 }, + // Mips_TLTU_MM - 239 + {1386, 1348, 3, 4 }, + // Mips_TLT_MM - 240 + {1375, 1352, 3, 4 }, + // Mips_TNE - 241 + {1398, 1356, 3, 7 }, + // Mips_TNE_MM - 242 + {1398, 1363, 3, 4 }, + // Mips_WAIT_MM - 243 + {1409, 1367, 1, 2 }, + // Mips_WAIT_NM - 244 + {1409, 1369, 1, 2 }, + // Mips_WRDSP - 245 + {1414, 1371, 2, 4 }, + // Mips_WRDSP_MM - 246 + {1414, 1375, 2, 4 }, + // Mips_YIELD - 247 + {1423, 1379, 2, 5 }, + // Mips_YIELD_NM - 248 + {1423, 1384, 2, 4 }, + {0}, }; + + static const AliasPatternCond Conds[] = { + // (MFTACX GPR32Opnd:$rt, AC0) - 0 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MFTACX_NM GPRNM32Opnd:$rt, AC0) - 5 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0) - 9 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MFTC0_NM GPRNM32Opnd:$rd, COP0Opnd:$rt, 0) - 15 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MFTHI GPR32Opnd:$rt, AC0) - 20 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MFTHI_NM GPRNM32Opnd:$rt, AC0) - 25 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MFTLO GPR32Opnd:$rt, AC0) - 29 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MFTLO_NM GPRNM32Opnd:$rt, AC0) - 34 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MTTACX AC0, GPR32Opnd:$rt) - 38 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MTTACX_NM AC0, GPRNM32Opnd:$rt) - 43 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0) - 47 + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MTTC0_NM COP0Opnd:$rt, GPRNM32Opnd:$rd, 0) - 53 + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MTTHI AC0, GPR32Opnd:$rt) - 58 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MTTHI_NM AC0, GPRNM32Opnd:$rt) - 63 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MTTLO AC0, GPR32Opnd:$rt) - 67 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MTTLO_NM AC0, GPRNM32Opnd:$rt) - 72 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm) - 76 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureGP64Bit}, + // (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 79 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureGP64Bit}, + // (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 82 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureGP64Bit}, + // (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 85 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureGP64Bit}, + // (ADDIUGP48_NM GPRNM48Opnd:$rt, GPRNMGPOpnd:$rs, sym32_gp_nm:$addr) - 88 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNMGPRegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (ADDIUGPB_NM GPRNM32Opnd:$rt, GPRNMGPOpnd:$rs, sym32_gp_nm:$offset) - 91 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNMGPRegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (ADDIUGPW_NM GPRNM32Opnd:$rt, GPRNMGPOpnd:$rs, sym32_gp_nm:$offset) - 94 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNMGPRegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm) - 97 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm) - 100 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 103 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (BC1F FCC0, brtarget:$offset) - 110 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (BC1FL FCC0, brtarget:$offset) - 116 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (BC1F_MM FCC0, brtarget:$offset) - 123 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (BC1T FCC0, brtarget:$offset) - 127 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (BC1TL FCC0, brtarget:$offset) - 133 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (BC1T_MM FCC0, brtarget:$offset) - 140 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (BEQC16_NM GPRNM16R3Opnd:$rs, GPRNM16R3Opnd:$rt, brtarget4s1_nm:$offset) - 144 + {AliasPatternCond_K_RegClass, Mips_GPRNM3RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM3RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (BEQC_NM GPRNM32Opnd:$rt, ZERO_NM, brtarget14_nm:$offset) - 147 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (BEQC_NM ZERO_NM, GPRNM32Opnd:$rt, brtarget14_nm:$offset) - 150 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 153 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (BGEZAL ZERO, brtarget:$offset) - 159 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (BGEZAL_MM ZERO, brtarget_mm:$offset) - 165 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + // (BNEC16_NM GPRNM16R3Opnd:$rs, GPRNM16R3Opnd:$rt, brtarget4s1_nm:$offset) - 168 + {AliasPatternCond_K_RegClass, Mips_GPRNM3RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM3RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (BNEC_NM GPRNM32Opnd:$rt, ZERO_NM, brtarget14_nm:$offset) - 171 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (BNEC_NM ZERO_NM, GPRNM32Opnd:$rt, brtarget14_nm:$offset) - 174 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 177 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (BREAK 0, 0) - 183 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (BREAK uimm10:$imm, 0) - 188 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (BREAK_MM 0, 0) - 193 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (BREAK_MM uimm10:$imm, 0) - 196 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (C_EQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 199 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_EQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 208 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_EQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 215 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_EQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 224 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_EQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 231 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_EQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 239 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_F_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 245 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_F_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 254 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_F_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 261 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_F_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 270 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_F_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 277 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_F_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 285 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_LE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 291 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_LE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 300 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_LE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 307 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_LE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 316 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_LE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 323 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_LE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 331 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_LT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 337 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_LT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 346 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_LT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 353 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_LT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 362 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_LT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 369 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_LT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 377 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 383 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 392 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 399 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 408 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 415 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 423 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 429 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 438 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 445 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 454 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 461 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 469 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGL_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 475 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGL_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 484 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGL_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 491 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGL_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 500 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGL_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 507 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGL_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 515 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 521 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 530 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 537 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 546 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 553 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 561 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_OLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 567 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_OLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 576 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_OLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 583 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_OLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 592 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_OLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 599 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_OLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 607 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_OLT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 613 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_OLT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 622 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_OLT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 629 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_OLT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 638 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_OLT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 645 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_OLT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 653 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_SEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 659 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_SEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 668 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_SEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 675 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_SEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 684 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_SEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 691 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_SEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 699 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_SF_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 705 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_SF_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 714 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_SF_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 721 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_SF_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 730 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_SF_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 737 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_SF_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 745 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_UEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 751 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_UEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 760 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_UEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 767 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_UEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 776 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_UEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 783 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_UEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 791 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_ULE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 797 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_ULE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 806 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_ULE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 813 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_ULE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 822 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_ULE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 829 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_ULE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 837 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_ULT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 843 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_ULT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 852 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_ULT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 859 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_ULT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 868 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_ULT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 875 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_ULT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 883 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_UN_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 889 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_UN_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 898 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_UN_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 905 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_UN_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 914 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_UN_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 921 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_UN_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 929 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 935 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_Feature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (DI ZERO) - 940 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (DIV GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 945 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 950 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (DI_MM ZERO) - 955 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (DI_MMR6 ZERO) - 957 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (DI_NM ZERO_NM) - 960 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (DMT ZERO) - 962 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (DMT_NM ZERO_NM) - 966 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 969 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips3}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 975 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips3}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 981 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips3}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 987 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips3}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (DVPE ZERO) - 993 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (DVPE_NM ZERO_NM) - 997 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (EI ZERO) - 1000 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (EI_MM ZERO) - 1005 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (EI_MMR6 ZERO) - 1007 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (EI_NM ZERO_NM) - 1010 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (EMT ZERO) - 1012 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (EMT_NM ZERO_NM) - 1016 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (EVPE ZERO) - 1019 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (EVPE_NM ZERO_NM) - 1023 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (HYPCALL 0) - 1026 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r5}, + {AliasPatternCond_K_Feature, Mips_FeatureVirt}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (HYPCALL_MM 0) - 1032 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r5}, + {AliasPatternCond_K_Feature, Mips_FeatureVirt}, + // (JALR ZERO, GPR32Opnd:$rs) - 1036 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (JALR64 ZERO_64, GPR64Opnd:$rs) - 1042 + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips64r6}, + // (JALRCHB_NM ZERO_NM, GPRNM32Opnd:$rs) - 1046 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (JALRC_HB_MMR6 RA, GPR32Opnd:$rs) - 1049 + {AliasPatternCond_K_Reg, Mips_RA}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (JALRC_MMR6 RA, GPR32Opnd:$rs) - 1053 + {AliasPatternCond_K_Reg, Mips_RA}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (JALR_HB RA, GPR32Opnd:$rs) - 1057 + {AliasPatternCond_K_Reg, Mips_RA}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (JALR_HB64 RA_64, GPR64Opnd:$rs) - 1063 + {AliasPatternCond_K_Reg, Mips_RA_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips64}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (JIALC GPR32Opnd:$rs, 0) - 1068 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (JIALC64 GPR64Opnd:$rs, 0) - 1074 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips64r6}, + // (JIC GPR32Opnd:$rs, 0) - 1078 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (JIC64 GPR64Opnd:$rs, 0) - 1083 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips64r6}, + // (MFC0_NM GPRNM32Opnd:$rt, COP0Opnd:$c0s, 0) - 1087 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (MFHC0_NM GPRNM32Opnd:$rt, COP0Opnd:$c0s, 0) - 1091 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (MOVE16_MM ZERO, ZERO) - 1095 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (MTC0_NM GPRNM32Opnd:$rt, COP0Opnd:$c0s, 0) - 1098 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (MTHC0_NM GPRNM32Opnd:$rt, COP0Opnd:$c0s, 0) - 1102 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (Move32R16 ZERO, S0) - 1106 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_S0}, + {AliasPatternCond_K_Feature, Mips_FeatureMips16}, + // (NOR_NM GPRNM32Opnd:$rt, GPRNM32Opnd:$rs, ZERO_NM) - 1109 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 1113 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 1120 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_Feature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1125 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0) - 1131 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureGP64Bit}, + // (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1135 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + // (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1140 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (RESTOREJRC16_NM uimm8s4_nm:$adj, 0) - 1145 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RESTOREJRC_NM uimm12s3_nm:$adj, 0) - 1147 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RESTORE_NM uimm12s3_nm:$adj, 0) - 1149 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ROTX_NM GPRNM32Opnd:$rt, GPRNM32Opnd:$rs, 7, 8, 1) - 1151 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (ROTX_NM GPRNM32Opnd:$rt, GPRNM32Opnd:$rs, 15, 16, 0) - 1157 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (ROTX_NM GPRNM32Opnd:$rt, GPRNM32Opnd:$rs, 8, 24, 0) - 1163 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SAVE16_NM uimm8s4_nm:$adj, 0) - 1169 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SAVE_NM uimm12s3_nm:$adj, 0) - 1171 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SDBBP 0) - 1173 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + // (SDBBP_MMR6 0) - 1178 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SDBBP_R6 0) - 1181 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (SIGRIE 0) - 1185 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (SIGRIE_MMR6 0) - 1189 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SLL ZERO, ZERO, 0) - 1192 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SLL_MM ZERO, ZERO, 0) - 1198 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (SLL_MMR6 ZERO, ZERO, 0) - 1202 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1207 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1213 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1219 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1224 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1229 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1234 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1239 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1244 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1249 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1255 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1261 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1266 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + // (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset) - 1271 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (SYNC 0) - 1273 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SYNC_MM 0) - 1278 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (SYNC_MMR6 0) - 1280 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SYNC_NM 0) - 1283 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SYNC_NM 4) - 1285 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SYNC_NM 16) - 1287 + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SYNC_NM 17) - 1289 + {AliasPatternCond_K_Imm, (uint32_t)17}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SYNC_NM 18) - 1291 + {AliasPatternCond_K_Imm, (uint32_t)18}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SYNC_NM 19) - 1293 + {AliasPatternCond_K_Imm, (uint32_t)19}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SYSCALL 0) - 1295 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SYSCALL_MM 0) - 1299 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1301 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1308 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1312 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1319 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1326 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1330 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1334 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1341 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1348 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1352 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1356 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1363 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (WAIT_MM 0) - 1367 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (WAIT_NM 0) - 1369 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (WRDSP GPR32Opnd:$rt, 31) - 1371 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Feature, Mips_FeatureDSP}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (WRDSP_MM GPR32Opnd:$rt, 31) - 1375 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Feature, Mips_FeatureDSP}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (YIELD ZERO, GPR32Opnd:$rs) - 1379 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (YIELD_NM ZERO_NM, GPRNM32Opnd:$rs) - 1384 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {0}, }; + + static const char AsmStrings[] = + /* 0 */ "mftacx $\x01\0" + /* 10 */ "mftc0 $\x01, $\x02\0" + /* 23 */ "mfthi $\x01\0" + /* 32 */ "mftlo $\x01\0" + /* 41 */ "mttacx $\x02\0" + /* 51 */ "mttc0 $\x02, $\x01\0" + /* 64 */ "mtthi $\x02\0" + /* 73 */ "mttlo $\x02\0" + /* 82 */ "nor $\x01, $\x03\0" + /* 93 */ "slt $\x01, $\x03\0" + /* 104 */ "sltu $\x01, $\x03\0" + /* 116 */ "addiu.b32 $\x01, $\x02, $\x03\0" + /* 137 */ "addiu.b $\x01, $\x02, $\x03\0" + /* 156 */ "addiu.w $\x01, $\x02, $\x03\0" + /* 175 */ "lapc $\x01, $\x02\0" + /* 187 */ "move $\x01, $\x02\0" + /* 199 */ "bc1f $\xFF\x02\x01\0" + /* 209 */ "bc1fl $\xFF\x02\x01\0" + /* 220 */ "bc1t $\xFF\x02\x01\0" + /* 230 */ "bc1tl $\xFF\x02\x01\0" + /* 241 */ "beqc $\x02, $\x01, $\xFF\x03\x01\0" + /* 259 */ "beqzc $\x01, $\xFF\x03\x01\0" + /* 274 */ "beqzc $\x02, $\xFF\x03\x01\0" + /* 289 */ "beqzl $\x01, $\xFF\x03\x01\0" + /* 304 */ "bal $\xFF\x02\x01\0" + /* 313 */ "bnec $\x02, $\x01, $\xFF\x03\x01\0" + /* 331 */ "bnezc $\x01, $\xFF\x03\x01\0" + /* 346 */ "bnezc $\x02, $\xFF\x03\x01\0" + /* 361 */ "bnezl $\x01, $\xFF\x03\x01\0" + /* 376 */ "break\0" + /* 382 */ "break $\xFF\x01\x02\0" + /* 393 */ "c.eq.d $\x02, $\x03\0" + /* 407 */ "c.eq.s $\x02, $\x03\0" + /* 421 */ "c.f.d $\x02, $\x03\0" + /* 434 */ "c.f.s $\x02, $\x03\0" + /* 447 */ "c.le.d $\x02, $\x03\0" + /* 461 */ "c.le.s $\x02, $\x03\0" + /* 475 */ "c.lt.d $\x02, $\x03\0" + /* 489 */ "c.lt.s $\x02, $\x03\0" + /* 503 */ "c.nge.d $\x02, $\x03\0" + /* 518 */ "c.nge.s $\x02, $\x03\0" + /* 533 */ "c.ngle.d $\x02, $\x03\0" + /* 549 */ "c.ngle.s $\x02, $\x03\0" + /* 565 */ "c.ngl.d $\x02, $\x03\0" + /* 580 */ "c.ngl.s $\x02, $\x03\0" + /* 595 */ "c.ngt.d $\x02, $\x03\0" + /* 610 */ "c.ngt.s $\x02, $\x03\0" + /* 625 */ "c.ole.d $\x02, $\x03\0" + /* 640 */ "c.ole.s $\x02, $\x03\0" + /* 655 */ "c.olt.d $\x02, $\x03\0" + /* 670 */ "c.olt.s $\x02, $\x03\0" + /* 685 */ "c.seq.d $\x02, $\x03\0" + /* 700 */ "c.seq.s $\x02, $\x03\0" + /* 715 */ "c.sf.d $\x02, $\x03\0" + /* 729 */ "c.sf.s $\x02, $\x03\0" + /* 743 */ "c.ueq.d $\x02, $\x03\0" + /* 758 */ "c.ueq.s $\x02, $\x03\0" + /* 773 */ "c.ule.d $\x02, $\x03\0" + /* 788 */ "c.ule.s $\x02, $\x03\0" + /* 803 */ "c.ult.d $\x02, $\x03\0" + /* 818 */ "c.ult.s $\x02, $\x03\0" + /* 833 */ "c.un.d $\x02, $\x03\0" + /* 847 */ "c.un.s $\x02, $\x03\0" + /* 861 */ "di\0" + /* 864 */ "div $\x01, $\x03\0" + /* 875 */ "divu $\x01, $\x03\0" + /* 887 */ "dmt\0" + /* 891 */ "dneg $\x01, $\x03\0" + /* 903 */ "dneg $\x01\0" + /* 911 */ "dnegu $\x01, $\x03\0" + /* 924 */ "dnegu $\x01\0" + /* 933 */ "dvpe\0" + /* 938 */ "ei\0" + /* 941 */ "emt\0" + /* 945 */ "evpe\0" + /* 950 */ "hypcall\0" + /* 958 */ "jr $\x02\0" + /* 964 */ "jrc.hb $\x02\0" + /* 974 */ "jalrc.hb $\x02\0" + /* 986 */ "jalrc $\x02\0" + /* 995 */ "jalr.hb $\x02\0" + /* 1006 */ "jalrc $\x01\0" + /* 1015 */ "jrc $\x01\0" + /* 1022 */ "mfc0 $\x01, $\x02\0" + /* 1034 */ "mfhc0 $\x01, $\x02\0" + /* 1047 */ "nop\0" + /* 1051 */ "mtc0 $\x01, $\x02\0" + /* 1063 */ "mthc0 $\x01, $\x02\0" + /* 1076 */ "not $\x01, $\x02\0" + /* 1087 */ "rdhwr $\x01, $\x02\0" + /* 1100 */ "restore.jrc $\xFF\x01\x03\0" + /* 1117 */ "restore.jrc $\xFF\x01\x04\0" + /* 1134 */ "restore $\xFF\x01\x04\0" + /* 1147 */ "bitrevb $\x01, $\x02\0" + /* 1162 */ "bitrevh $\x01, $\x02\0" + /* 1177 */ "byterevh $\x01, $\x02\0" + /* 1193 */ "save $\xFF\x01\x03\0" + /* 1203 */ "save $\xFF\x01\x04\0" + /* 1213 */ "sdbbp\0" + /* 1219 */ "sigrie\0" + /* 1226 */ "neg $\x01, $\x03\0" + /* 1237 */ "neg $\x01\0" + /* 1244 */ "negu $\x01, $\x03\0" + /* 1256 */ "negu $\x01\0" + /* 1264 */ "sw $\x01, $\xFF\x02\x05\0" + /* 1276 */ "sync\0" + /* 1281 */ "sync_wmb\0" + /* 1290 */ "sync_mb\0" + /* 1298 */ "sync_acquire\0" + /* 1311 */ "sync_release\0" + /* 1324 */ "sync_rmb\0" + /* 1333 */ "syscall\0" + /* 1341 */ "teq $\x01, $\x02\0" + /* 1352 */ "tge $\x01, $\x02\0" + /* 1363 */ "tgeu $\x01, $\x02\0" + /* 1375 */ "tlt $\x01, $\x02\0" + /* 1386 */ "tltu $\x01, $\x02\0" + /* 1398 */ "tne $\x01, $\x02\0" + /* 1409 */ "wait\0" + /* 1414 */ "wrdsp $\x01\0" + /* 1423 */ "yield $\x02\0" + ; + +#ifndef NDEBUG + //static struct SortCheck { + // SortCheck(ArrayRef OpToPatterns) { + // assert(std::is_sorted( + // OpToPatterns.begin(), OpToPatterns.end(), + // [](const PatternsForOpcode &L, const //PatternsForOpcode &R) { + // return L.Opcode < R.Opcode; + // }) && + // "tablegen failed to sort opcode patterns"); + // } + //} sortCheckVar(OpToPatterns); +#endif + + AliasMatchingData M = { + OpToPatterns, + Patterns, + Conds, + AsmStrings, + NULL, + }; + const char *AsmString = matchAliasPatterns(MI, &M); + if (!AsmString) return false; + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && + AsmString[I] != '$' && AsmString[I] != '\0') + ++I; + SStream_concat1(OS, '\t'); + char *substr = malloc(I+1); + memcpy(substr, AsmString, I); + substr[I] = '\0'; + SStream_concat0(OS, substr); + free(substr); + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat1(OS, '\t'); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); + } else { + SStream_concat1(OS, AsmString[I++]); + } + } while (AsmString[I] != '\0'); + } + + return true; +#else + return false; +#endif // CAPSTONE_DIET } -static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) -{ - #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) - const char *AsmString; - char *tmp, *AsmMnem, *AsmOps, *c; - int OpIdx, PrintMethodIdx; - MCRegisterInfo *MRI = (MCRegisterInfo *)info; - switch (MCInst_getOpcode(MI)) { - default: return NULL; - case Mips_ADDu: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO) { - // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - AsmString = "move $\x01, $\x02"; - break; - } - return NULL; - case Mips_BC0F: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC0F CC0, brtarget:$offset) - AsmString = "bc0f $\x02"; - break; - } - return NULL; - case Mips_BC0FL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC0FL CC0, brtarget:$offset) - AsmString = "bc0fl $\x02"; - break; - } - return NULL; - case Mips_BC0T: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC0T CC0, brtarget:$offset) - AsmString = "bc0t $\x02"; - break; - } - return NULL; - case Mips_BC0TL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC0TL CC0, brtarget:$offset) - AsmString = "bc0tl $\x02"; - break; - } - return NULL; - case Mips_BC1F: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { - // (BC1F FCC0, brtarget:$offset) - AsmString = "bc1f $\x02"; - break; - } - return NULL; - case Mips_BC1FL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { - // (BC1FL FCC0, brtarget:$offset) - AsmString = "bc1fl $\x02"; - break; - } - return NULL; - case Mips_BC1T: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { - // (BC1T FCC0, brtarget:$offset) - AsmString = "bc1t $\x02"; - break; - } - return NULL; - case Mips_BC1TL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { - // (BC1TL FCC0, brtarget:$offset) - AsmString = "bc1tl $\x02"; - break; - } - return NULL; - case Mips_BC2F: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC2F CC0, brtarget:$offset) - AsmString = "bc2f $\x02"; - break; - } - return NULL; - case Mips_BC2FL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC2FL CC0, brtarget:$offset) - AsmString = "bc2fl $\x02"; - break; - } - return NULL; - case Mips_BC2T: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC2T CC0, brtarget:$offset) - AsmString = "bc2t $\x02"; - break; - } - return NULL; - case Mips_BC2TL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC2TL CC0, brtarget:$offset) - AsmString = "bc2tl $\x02"; - break; - } - return NULL; - case Mips_BC3F: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC3F CC0, brtarget:$offset) - AsmString = "bc3f $\x02"; - break; - } - return NULL; - case Mips_BC3FL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC3FL CC0, brtarget:$offset) - AsmString = "bc3fl $\x02"; - break; - } - return NULL; - case Mips_BC3T: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC3T CC0, brtarget:$offset) - AsmString = "bc3t $\x02"; - break; - } - return NULL; - case Mips_BC3TL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC3TL CC0, brtarget:$offset) - AsmString = "bc3tl $\x02"; - break; - } - return NULL; - case Mips_BREAK: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { - // (BREAK 0, 0) - AsmString = "break"; - break; - } - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { - // (BREAK uimm10:$imm, 0) - AsmString = "break $\x01"; - break; - } - return NULL; - case Mips_DADDu: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO_64) { - // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - AsmString = "move $\x01, $\x02"; - break; - } - return NULL; - case Mips_DI: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) { - // (DI ZERO) - AsmString = "di"; - break; - } - return NULL; - case Mips_EI: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) { - // (EI ZERO) - AsmString = "ei"; - break; - } - return NULL; - case Mips_JALR: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) { - // (JALR ZERO, GPR32Opnd:$rs) - AsmString = "jr $\x02"; - break; - } - return NULL; - case Mips_JALR64: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO_64 && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1)) { - // (JALR64 ZERO_64, GPR64Opnd:$rs) - AsmString = "jr $\x02"; - break; - } - return NULL; - case Mips_JALR_HB: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_RA && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) { - // (JALR_HB RA, GPR32Opnd:$rs) - AsmString = "jalr.hb $\x02"; - break; - } - return NULL; - case Mips_MOVE16_MM: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO) { - // (MOVE16_MM ZERO, ZERO) - AsmString = "nop"; - break; - } - return NULL; - case Mips_SDBBP: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { - // (SDBBP 0) - AsmString = "sdbbp"; - break; - } - return NULL; - case Mips_SDBBP_R6: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { - // (SDBBP_R6 0) - AsmString = "sdbbp"; - break; - } - return NULL; - case Mips_SLL: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (SLL ZERO, ZERO, 0) - AsmString = "nop"; - break; - } - return NULL; - case Mips_SLL_MM: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (SLL_MM ZERO, ZERO, 0) - AsmString = "nop"; - break; - } - return NULL; - case Mips_SUB: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) { - // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - AsmString = "neg $\x01, $\x03"; - break; - } - return NULL; - case Mips_SUBu: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) { - // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - AsmString = "negu $\x01, $\x03"; - break; - } - return NULL; - case Mips_SYNC: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { - // (SYNC 0) - AsmString = "sync"; - break; - } - return NULL; - case Mips_SYSCALL: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { - // (SYSCALL 0) - AsmString = "syscall"; - break; - } - return NULL; - case Mips_TEQ: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - AsmString = "teq $\x01, $\x02"; - break; - } - return NULL; - case Mips_TGE: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - AsmString = "tge $\x01, $\x02"; - break; - } - return NULL; - case Mips_TGEU: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - AsmString = "tgeu $\x01, $\x02"; - break; - } - return NULL; - case Mips_TLT: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - AsmString = "tlt $\x01, $\x02"; - break; - } - return NULL; - case Mips_TLTU: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - AsmString = "tltu $\x01, $\x02"; - break; - } - return NULL; - case Mips_TNE: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - AsmString = "tne $\x01, $\x02"; - break; - } - return NULL; - case Mips_WAIT_MM: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { - // (WAIT_MM 0) - AsmString = "wait"; - break; - } - return NULL; +static void printCustomAliasOperand( + MCInst *MI, uint64_t Address, unsigned OpIdx, + unsigned PrintMethodIdx, + SStream *OS) { +#ifndef CAPSTONE_DIET + switch (PrintMethodIdx) { + default: + assert(0 && "Unknown PrintMethod kind"); + break; + case 0: + printBranchOperand(MI, Address, OpIdx, OS); + break; + case 1: + printUImm_10_0(MI, OpIdx, OS); + break; + case 2: + printUImm_8_0(MI, OpIdx, OS); + break; + case 3: + printUImm_12_0(MI, OpIdx, OS); + break; + case 4: + printMemOperand(MI, OpIdx, OS); + break; } - - tmp = cs_strdup(AsmString); - AsmMnem = tmp; - for(AsmOps = tmp; *AsmOps; AsmOps++) { - if (*AsmOps == ' ' || *AsmOps == '\t') { - *AsmOps = '\0'; - AsmOps++; - break; - } - } - SStream_concat0(OS, AsmMnem); - if (*AsmOps) { - SStream_concat0(OS, "\t"); - for (c = AsmOps; *c; c++) { - if (*c == '$') { - c += 1; - if (*c == (char)0xff) { - c += 1; - OpIdx = *c - 1; - c += 1; - PrintMethodIdx = *c - 1; - printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); - } else - printOperand(MI, *c - 1, OS); - } else { - SStream_concat(OS, "%c", *c); - } - } - } - return tmp; +#endif // CAPSTONE_DIET } #endif // PRINT_ALIAS_INSTR diff --git a/arch/Mips/MipsGenCSAliasEnum.inc b/arch/Mips/MipsGenCSAliasEnum.inc new file mode 100644 index 000000000..95cd4e60c --- /dev/null +++ b/arch/Mips/MipsGenCSAliasEnum.inc @@ -0,0 +1,119 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + MIPS_INS_ALIAS_ADDIU_B32, // Real instr.: MIPS_ADDIUGP48_NM + MIPS_INS_ALIAS_BITREVB, // Real instr.: MIPS_ROTX_NM + MIPS_INS_ALIAS_BITREVH, // Real instr.: MIPS_ROTX_NM + MIPS_INS_ALIAS_BYTEREVH, // Real instr.: MIPS_ROTX_NM + MIPS_INS_ALIAS_NOT, // Real instr.: MIPS_NOR_NM + MIPS_INS_ALIAS_RESTORE_JRC, // Real instr.: MIPS_RESTOREJRC16_NM + MIPS_INS_ALIAS_RESTORE, // Real instr.: MIPS_RESTORE_NM + MIPS_INS_ALIAS_SAVE, // Real instr.: MIPS_SAVE16_NM + MIPS_INS_ALIAS_MOVE, // Real instr.: MIPS_OR + MIPS_INS_ALIAS_BAL, // Real instr.: MIPS_BGEZAL + MIPS_INS_ALIAS_JALR_HB, // Real instr.: MIPS_JALR_HB + MIPS_INS_ALIAS_NEG, // Real instr.: MIPS_SUB + MIPS_INS_ALIAS_NEGU, // Real instr.: MIPS_SUBu + MIPS_INS_ALIAS_NOP, // Real instr.: MIPS_SLL + MIPS_INS_ALIAS_BNEZL, // Real instr.: MIPS_BNEL + MIPS_INS_ALIAS_BEQZL, // Real instr.: MIPS_BEQL + MIPS_INS_ALIAS_SYSCALL, // Real instr.: MIPS_SYSCALL + MIPS_INS_ALIAS_BREAK, // Real instr.: MIPS_BREAK + MIPS_INS_ALIAS_EI, // Real instr.: MIPS_EI + MIPS_INS_ALIAS_DI, // Real instr.: MIPS_DI + MIPS_INS_ALIAS_TEQ, // Real instr.: MIPS_TEQ + MIPS_INS_ALIAS_TGE, // Real instr.: MIPS_TGE + MIPS_INS_ALIAS_TGEU, // Real instr.: MIPS_TGEU + MIPS_INS_ALIAS_TLT, // Real instr.: MIPS_TLT + MIPS_INS_ALIAS_TLTU, // Real instr.: MIPS_TLTU + MIPS_INS_ALIAS_TNE, // Real instr.: MIPS_TNE + MIPS_INS_ALIAS_RDHWR, // Real instr.: MIPS_RDHWR + MIPS_INS_ALIAS_SDBBP, // Real instr.: MIPS_SDBBP + MIPS_INS_ALIAS_SYNC, // Real instr.: MIPS_SYNC + MIPS_INS_ALIAS_HYPCALL, // Real instr.: MIPS_HYPCALL + MIPS_INS_ALIAS_NOR, // Real instr.: MIPS_NORImm + MIPS_INS_ALIAS_C_F_S, // Real instr.: MIPS_C_F_S + MIPS_INS_ALIAS_C_UN_S, // Real instr.: MIPS_C_UN_S + MIPS_INS_ALIAS_C_EQ_S, // Real instr.: MIPS_C_EQ_S + MIPS_INS_ALIAS_C_UEQ_S, // Real instr.: MIPS_C_UEQ_S + MIPS_INS_ALIAS_C_OLT_S, // Real instr.: MIPS_C_OLT_S + MIPS_INS_ALIAS_C_ULT_S, // Real instr.: MIPS_C_ULT_S + MIPS_INS_ALIAS_C_OLE_S, // Real instr.: MIPS_C_OLE_S + MIPS_INS_ALIAS_C_ULE_S, // Real instr.: MIPS_C_ULE_S + MIPS_INS_ALIAS_C_SF_S, // Real instr.: MIPS_C_SF_S + MIPS_INS_ALIAS_C_NGLE_S, // Real instr.: MIPS_C_NGLE_S + MIPS_INS_ALIAS_C_SEQ_S, // Real instr.: MIPS_C_SEQ_S + MIPS_INS_ALIAS_C_NGL_S, // Real instr.: MIPS_C_NGL_S + MIPS_INS_ALIAS_C_LT_S, // Real instr.: MIPS_C_LT_S + MIPS_INS_ALIAS_C_NGE_S, // Real instr.: MIPS_C_NGE_S + MIPS_INS_ALIAS_C_LE_S, // Real instr.: MIPS_C_LE_S + MIPS_INS_ALIAS_C_NGT_S, // Real instr.: MIPS_C_NGT_S + MIPS_INS_ALIAS_BC1T, // Real instr.: MIPS_BC1T + MIPS_INS_ALIAS_BC1F, // Real instr.: MIPS_BC1F + MIPS_INS_ALIAS_C_F_D, // Real instr.: MIPS_C_F_D32 + MIPS_INS_ALIAS_C_UN_D, // Real instr.: MIPS_C_UN_D32 + MIPS_INS_ALIAS_C_EQ_D, // Real instr.: MIPS_C_EQ_D32 + MIPS_INS_ALIAS_C_UEQ_D, // Real instr.: MIPS_C_UEQ_D32 + MIPS_INS_ALIAS_C_OLT_D, // Real instr.: MIPS_C_OLT_D32 + MIPS_INS_ALIAS_C_ULT_D, // Real instr.: MIPS_C_ULT_D32 + MIPS_INS_ALIAS_C_OLE_D, // Real instr.: MIPS_C_OLE_D32 + MIPS_INS_ALIAS_C_ULE_D, // Real instr.: MIPS_C_ULE_D32 + MIPS_INS_ALIAS_C_SF_D, // Real instr.: MIPS_C_SF_D32 + MIPS_INS_ALIAS_C_NGLE_D, // Real instr.: MIPS_C_NGLE_D32 + MIPS_INS_ALIAS_C_SEQ_D, // Real instr.: MIPS_C_SEQ_D32 + MIPS_INS_ALIAS_C_NGL_D, // Real instr.: MIPS_C_NGL_D32 + MIPS_INS_ALIAS_C_LT_D, // Real instr.: MIPS_C_LT_D32 + MIPS_INS_ALIAS_C_NGE_D, // Real instr.: MIPS_C_NGE_D32 + MIPS_INS_ALIAS_C_LE_D, // Real instr.: MIPS_C_LE_D32 + MIPS_INS_ALIAS_C_NGT_D, // Real instr.: MIPS_C_NGT_D32 + MIPS_INS_ALIAS_BC1TL, // Real instr.: MIPS_BC1TL + MIPS_INS_ALIAS_BC1FL, // Real instr.: MIPS_BC1FL + MIPS_INS_ALIAS_DNEG, // Real instr.: MIPS_DSUB + MIPS_INS_ALIAS_DNEGU, // Real instr.: MIPS_DSUBu + MIPS_INS_ALIAS_SLT, // Real instr.: MIPS_SLTImm64 + MIPS_INS_ALIAS_SLTU, // Real instr.: MIPS_SLTUImm64 + MIPS_INS_ALIAS_SIGRIE, // Real instr.: MIPS_SIGRIE + MIPS_INS_ALIAS_JR, // Real instr.: MIPS_JALR + MIPS_INS_ALIAS_JRC, // Real instr.: MIPS_JIC + MIPS_INS_ALIAS_JALRC, // Real instr.: MIPS_JIALC + MIPS_INS_ALIAS_DIV, // Real instr.: MIPS_DIV + MIPS_INS_ALIAS_DIVU, // Real instr.: MIPS_DIVU + MIPS_INS_ALIAS_LAPC, // Real instr.: MIPS_ADDIUPC + MIPS_INS_ALIAS_WRDSP, // Real instr.: MIPS_WRDSP + MIPS_INS_ALIAS_WAIT, // Real instr.: MIPS_WAIT_MM + MIPS_INS_ALIAS_SW, // Real instr.: MIPS_SWSP_MM + MIPS_INS_ALIAS_JALRC_HB, // Real instr.: MIPS_JALRC_HB_MMR6 + MIPS_INS_ALIAS_ADDIU_B, // Real instr.: MIPS_ADDIUGPB_NM + MIPS_INS_ALIAS_ADDIU_W, // Real instr.: MIPS_ADDIUGPW_NM + MIPS_INS_ALIAS_JRC_HB, // Real instr.: MIPS_JALRCHB_NM + MIPS_INS_ALIAS_BEQC, // Real instr.: MIPS_BEQC16_NM + MIPS_INS_ALIAS_BNEC, // Real instr.: MIPS_BNEC16_NM + MIPS_INS_ALIAS_BEQZC, // Real instr.: MIPS_BEQC_NM + MIPS_INS_ALIAS_BNEZC, // Real instr.: MIPS_BNEC_NM + MIPS_INS_ALIAS_MFC0, // Real instr.: MIPS_MFC0_NM + MIPS_INS_ALIAS_MFHC0, // Real instr.: MIPS_MFHC0_NM + MIPS_INS_ALIAS_MTC0, // Real instr.: MIPS_MTC0_NM + MIPS_INS_ALIAS_MTHC0, // Real instr.: MIPS_MTHC0_NM + MIPS_INS_ALIAS_DMT, // Real instr.: MIPS_DMT + MIPS_INS_ALIAS_EMT, // Real instr.: MIPS_EMT + MIPS_INS_ALIAS_DVPE, // Real instr.: MIPS_DVPE + MIPS_INS_ALIAS_EVPE, // Real instr.: MIPS_EVPE + MIPS_INS_ALIAS_YIELD, // Real instr.: MIPS_YIELD + MIPS_INS_ALIAS_MFTC0, // Real instr.: MIPS_MFTC0 + MIPS_INS_ALIAS_MFTLO, // Real instr.: MIPS_MFTLO + MIPS_INS_ALIAS_MFTHI, // Real instr.: MIPS_MFTHI + MIPS_INS_ALIAS_MFTACX, // Real instr.: MIPS_MFTACX + MIPS_INS_ALIAS_MTTC0, // Real instr.: MIPS_MTTC0 + MIPS_INS_ALIAS_MTTLO, // Real instr.: MIPS_MTTLO + MIPS_INS_ALIAS_MTTHI, // Real instr.: MIPS_MTTHI + MIPS_INS_ALIAS_MTTACX, // Real instr.: MIPS_MTTACX diff --git a/arch/Mips/MipsGenCSAliasMnemMap.inc b/arch/Mips/MipsGenCSAliasMnemMap.inc new file mode 100644 index 000000000..08b93c9ed --- /dev/null +++ b/arch/Mips/MipsGenCSAliasMnemMap.inc @@ -0,0 +1,119 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + { MIPS_INS_ALIAS_ADDIU_B32, "addiu_b32" }, + { MIPS_INS_ALIAS_BITREVB, "bitrevb" }, + { MIPS_INS_ALIAS_BITREVH, "bitrevh" }, + { MIPS_INS_ALIAS_BYTEREVH, "byterevh" }, + { MIPS_INS_ALIAS_NOT, "not" }, + { MIPS_INS_ALIAS_RESTORE_JRC, "restore_jrc" }, + { MIPS_INS_ALIAS_RESTORE, "restore" }, + { MIPS_INS_ALIAS_SAVE, "save" }, + { MIPS_INS_ALIAS_MOVE, "move" }, + { MIPS_INS_ALIAS_BAL, "bal" }, + { MIPS_INS_ALIAS_JALR_HB, "jalr_hb" }, + { MIPS_INS_ALIAS_NEG, "neg" }, + { MIPS_INS_ALIAS_NEGU, "negu" }, + { MIPS_INS_ALIAS_NOP, "nop" }, + { MIPS_INS_ALIAS_BNEZL, "bnezl" }, + { MIPS_INS_ALIAS_BEQZL, "beqzl" }, + { MIPS_INS_ALIAS_SYSCALL, "syscall" }, + { MIPS_INS_ALIAS_BREAK, "break" }, + { MIPS_INS_ALIAS_EI, "ei" }, + { MIPS_INS_ALIAS_DI, "di" }, + { MIPS_INS_ALIAS_TEQ, "teq" }, + { MIPS_INS_ALIAS_TGE, "tge" }, + { MIPS_INS_ALIAS_TGEU, "tgeu" }, + { MIPS_INS_ALIAS_TLT, "tlt" }, + { MIPS_INS_ALIAS_TLTU, "tltu" }, + { MIPS_INS_ALIAS_TNE, "tne" }, + { MIPS_INS_ALIAS_RDHWR, "rdhwr" }, + { MIPS_INS_ALIAS_SDBBP, "sdbbp" }, + { MIPS_INS_ALIAS_SYNC, "sync" }, + { MIPS_INS_ALIAS_HYPCALL, "hypcall" }, + { MIPS_INS_ALIAS_NOR, "nor" }, + { MIPS_INS_ALIAS_C_F_S, "c_f_s" }, + { MIPS_INS_ALIAS_C_UN_S, "c_un_s" }, + { MIPS_INS_ALIAS_C_EQ_S, "c_eq_s" }, + { MIPS_INS_ALIAS_C_UEQ_S, "c_ueq_s" }, + { MIPS_INS_ALIAS_C_OLT_S, "c_olt_s" }, + { MIPS_INS_ALIAS_C_ULT_S, "c_ult_s" }, + { MIPS_INS_ALIAS_C_OLE_S, "c_ole_s" }, + { MIPS_INS_ALIAS_C_ULE_S, "c_ule_s" }, + { MIPS_INS_ALIAS_C_SF_S, "c_sf_s" }, + { MIPS_INS_ALIAS_C_NGLE_S, "c_ngle_s" }, + { MIPS_INS_ALIAS_C_SEQ_S, "c_seq_s" }, + { MIPS_INS_ALIAS_C_NGL_S, "c_ngl_s" }, + { MIPS_INS_ALIAS_C_LT_S, "c_lt_s" }, + { MIPS_INS_ALIAS_C_NGE_S, "c_nge_s" }, + { MIPS_INS_ALIAS_C_LE_S, "c_le_s" }, + { MIPS_INS_ALIAS_C_NGT_S, "c_ngt_s" }, + { MIPS_INS_ALIAS_BC1T, "bc1t" }, + { MIPS_INS_ALIAS_BC1F, "bc1f" }, + { MIPS_INS_ALIAS_C_F_D, "c_f_d" }, + { MIPS_INS_ALIAS_C_UN_D, "c_un_d" }, + { MIPS_INS_ALIAS_C_EQ_D, "c_eq_d" }, + { MIPS_INS_ALIAS_C_UEQ_D, "c_ueq_d" }, + { MIPS_INS_ALIAS_C_OLT_D, "c_olt_d" }, + { MIPS_INS_ALIAS_C_ULT_D, "c_ult_d" }, + { MIPS_INS_ALIAS_C_OLE_D, "c_ole_d" }, + { MIPS_INS_ALIAS_C_ULE_D, "c_ule_d" }, + { MIPS_INS_ALIAS_C_SF_D, "c_sf_d" }, + { MIPS_INS_ALIAS_C_NGLE_D, "c_ngle_d" }, + { MIPS_INS_ALIAS_C_SEQ_D, "c_seq_d" }, + { MIPS_INS_ALIAS_C_NGL_D, "c_ngl_d" }, + { MIPS_INS_ALIAS_C_LT_D, "c_lt_d" }, + { MIPS_INS_ALIAS_C_NGE_D, "c_nge_d" }, + { MIPS_INS_ALIAS_C_LE_D, "c_le_d" }, + { MIPS_INS_ALIAS_C_NGT_D, "c_ngt_d" }, + { MIPS_INS_ALIAS_BC1TL, "bc1tl" }, + { MIPS_INS_ALIAS_BC1FL, "bc1fl" }, + { MIPS_INS_ALIAS_DNEG, "dneg" }, + { MIPS_INS_ALIAS_DNEGU, "dnegu" }, + { MIPS_INS_ALIAS_SLT, "slt" }, + { MIPS_INS_ALIAS_SLTU, "sltu" }, + { MIPS_INS_ALIAS_SIGRIE, "sigrie" }, + { MIPS_INS_ALIAS_JR, "jr" }, + { MIPS_INS_ALIAS_JRC, "jrc" }, + { MIPS_INS_ALIAS_JALRC, "jalrc" }, + { MIPS_INS_ALIAS_DIV, "div" }, + { MIPS_INS_ALIAS_DIVU, "divu" }, + { MIPS_INS_ALIAS_LAPC, "lapc" }, + { MIPS_INS_ALIAS_WRDSP, "wrdsp" }, + { MIPS_INS_ALIAS_WAIT, "wait" }, + { MIPS_INS_ALIAS_SW, "sw" }, + { MIPS_INS_ALIAS_JALRC_HB, "jalrc_hb" }, + { MIPS_INS_ALIAS_ADDIU_B, "addiu_b" }, + { MIPS_INS_ALIAS_ADDIU_W, "addiu_w" }, + { MIPS_INS_ALIAS_JRC_HB, "jrc_hb" }, + { MIPS_INS_ALIAS_BEQC, "beqc" }, + { MIPS_INS_ALIAS_BNEC, "bnec" }, + { MIPS_INS_ALIAS_BEQZC, "beqzc" }, + { MIPS_INS_ALIAS_BNEZC, "bnezc" }, + { MIPS_INS_ALIAS_MFC0, "mfc0" }, + { MIPS_INS_ALIAS_MFHC0, "mfhc0" }, + { MIPS_INS_ALIAS_MTC0, "mtc0" }, + { MIPS_INS_ALIAS_MTHC0, "mthc0" }, + { MIPS_INS_ALIAS_DMT, "dmt" }, + { MIPS_INS_ALIAS_EMT, "emt" }, + { MIPS_INS_ALIAS_DVPE, "dvpe" }, + { MIPS_INS_ALIAS_EVPE, "evpe" }, + { MIPS_INS_ALIAS_YIELD, "yield" }, + { MIPS_INS_ALIAS_MFTC0, "mftc0" }, + { MIPS_INS_ALIAS_MFTLO, "mftlo" }, + { MIPS_INS_ALIAS_MFTHI, "mfthi" }, + { MIPS_INS_ALIAS_MFTACX, "mftacx" }, + { MIPS_INS_ALIAS_MTTC0, "mttc0" }, + { MIPS_INS_ALIAS_MTTLO, "mttlo" }, + { MIPS_INS_ALIAS_MTTHI, "mtthi" }, + { MIPS_INS_ALIAS_MTTACX, "mttacx" }, diff --git a/arch/Mips/MipsGenCSFeatureEnum.inc b/arch/Mips/MipsGenCSFeatureEnum.inc new file mode 100644 index 000000000..46928ceb5 --- /dev/null +++ b/arch/Mips/MipsGenCSFeatureEnum.inc @@ -0,0 +1,69 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +MIPS_FEATURE_HASMIPS2 = 128, +MIPS_FEATURE_HASMIPS3_32, +MIPS_FEATURE_HASMIPS3_32R2, +MIPS_FEATURE_HASMIPS3, +MIPS_FEATURE_NOTMIPS3, +MIPS_FEATURE_HASMIPS4_32, +MIPS_FEATURE_NOTMIPS4_32, +MIPS_FEATURE_HASMIPS4_32R2, +MIPS_FEATURE_HASMIPS5_32R2, +MIPS_FEATURE_HASMIPS32, +MIPS_FEATURE_HASMIPS32R2, +MIPS_FEATURE_HASMIPS32R5, +MIPS_FEATURE_HASMIPS32R6, +MIPS_FEATURE_NOTMIPS32R6, +MIPS_FEATURE_HASNANOMIPS, +MIPS_FEATURE_NOTNANOMIPS, +MIPS_FEATURE_ISGP64BIT, +MIPS_FEATURE_ISGP32BIT, +MIPS_FEATURE_ISPTR64BIT, +MIPS_FEATURE_ISPTR32BIT, +MIPS_FEATURE_HASMIPS64, +MIPS_FEATURE_NOTMIPS64, +MIPS_FEATURE_HASMIPS64R2, +MIPS_FEATURE_HASMIPS64R5, +MIPS_FEATURE_HASMIPS64R6, +MIPS_FEATURE_NOTMIPS64R6, +MIPS_FEATURE_INMIPS16MODE, +MIPS_FEATURE_NOTINMIPS16MODE, +MIPS_FEATURE_HASCNMIPS, +MIPS_FEATURE_NOTCNMIPS, +MIPS_FEATURE_HASCNMIPSP, +MIPS_FEATURE_NOTCNMIPSP, +MIPS_FEATURE_ISSYM32, +MIPS_FEATURE_ISSYM64, +MIPS_FEATURE_HASSTDENC, +MIPS_FEATURE_INMICROMIPS, +MIPS_FEATURE_NOTINMICROMIPS, +MIPS_FEATURE_HASEVA, +MIPS_FEATURE_HASMSA, +MIPS_FEATURE_HASMADD4, +MIPS_FEATURE_HASMT, +MIPS_FEATURE_USEINDIRECTJUMPSHAZARD, +MIPS_FEATURE_NOINDIRECTJUMPGUARDS, +MIPS_FEATURE_HASCRC, +MIPS_FEATURE_HASVIRT, +MIPS_FEATURE_HASGINV, +MIPS_FEATURE_HASTLB, +MIPS_FEATURE_ISFP64BIT, +MIPS_FEATURE_NOTFP64BIT, +MIPS_FEATURE_ISSINGLEFLOAT, +MIPS_FEATURE_ISNOTSINGLEFLOAT, +MIPS_FEATURE_ISNOTSOFTFLOAT, +MIPS_FEATURE_HASMIPS3D, +MIPS_FEATURE_HASDSP, +MIPS_FEATURE_HASDSPR2, +MIPS_FEATURE_HASDSPR3, diff --git a/arch/Mips/MipsGenCSFeatureName.inc b/arch/Mips/MipsGenCSFeatureName.inc new file mode 100644 index 000000000..495cc3f21 --- /dev/null +++ b/arch/Mips/MipsGenCSFeatureName.inc @@ -0,0 +1,69 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{ MIPS_FEATURE_HASMIPS2, "HasMips2" }, +{ MIPS_FEATURE_HASMIPS3_32, "HasMips3_32" }, +{ MIPS_FEATURE_HASMIPS3_32R2, "HasMips3_32r2" }, +{ MIPS_FEATURE_HASMIPS3, "HasMips3" }, +{ MIPS_FEATURE_NOTMIPS3, "NotMips3" }, +{ MIPS_FEATURE_HASMIPS4_32, "HasMips4_32" }, +{ MIPS_FEATURE_NOTMIPS4_32, "NotMips4_32" }, +{ MIPS_FEATURE_HASMIPS4_32R2, "HasMips4_32r2" }, +{ MIPS_FEATURE_HASMIPS5_32R2, "HasMips5_32r2" }, +{ MIPS_FEATURE_HASMIPS32, "HasMips32" }, +{ MIPS_FEATURE_HASMIPS32R2, "HasMips32r2" }, +{ MIPS_FEATURE_HASMIPS32R5, "HasMips32r5" }, +{ MIPS_FEATURE_HASMIPS32R6, "HasMips32r6" }, +{ MIPS_FEATURE_NOTMIPS32R6, "NotMips32r6" }, +{ MIPS_FEATURE_HASNANOMIPS, "HasNanoMips" }, +{ MIPS_FEATURE_NOTNANOMIPS, "NotNanoMips" }, +{ MIPS_FEATURE_ISGP64BIT, "IsGP64bit" }, +{ MIPS_FEATURE_ISGP32BIT, "IsGP32bit" }, +{ MIPS_FEATURE_ISPTR64BIT, "IsPTR64bit" }, +{ MIPS_FEATURE_ISPTR32BIT, "IsPTR32bit" }, +{ MIPS_FEATURE_HASMIPS64, "HasMips64" }, +{ MIPS_FEATURE_NOTMIPS64, "NotMips64" }, +{ MIPS_FEATURE_HASMIPS64R2, "HasMips64r2" }, +{ MIPS_FEATURE_HASMIPS64R5, "HasMips64r5" }, +{ MIPS_FEATURE_HASMIPS64R6, "HasMips64r6" }, +{ MIPS_FEATURE_NOTMIPS64R6, "NotMips64r6" }, +{ MIPS_FEATURE_INMIPS16MODE, "InMips16Mode" }, +{ MIPS_FEATURE_NOTINMIPS16MODE, "NotInMips16Mode" }, +{ MIPS_FEATURE_HASCNMIPS, "HasCnMips" }, +{ MIPS_FEATURE_NOTCNMIPS, "NotCnMips" }, +{ MIPS_FEATURE_HASCNMIPSP, "HasCnMipsP" }, +{ MIPS_FEATURE_NOTCNMIPSP, "NotCnMipsP" }, +{ MIPS_FEATURE_ISSYM32, "IsSym32" }, +{ MIPS_FEATURE_ISSYM64, "IsSym64" }, +{ MIPS_FEATURE_HASSTDENC, "HasStdEnc" }, +{ MIPS_FEATURE_INMICROMIPS, "InMicroMips" }, +{ MIPS_FEATURE_NOTINMICROMIPS, "NotInMicroMips" }, +{ MIPS_FEATURE_HASEVA, "HasEVA" }, +{ MIPS_FEATURE_HASMSA, "HasMSA" }, +{ MIPS_FEATURE_HASMADD4, "HasMadd4" }, +{ MIPS_FEATURE_HASMT, "HasMT" }, +{ MIPS_FEATURE_USEINDIRECTJUMPSHAZARD, "UseIndirectJumpsHazard" }, +{ MIPS_FEATURE_NOINDIRECTJUMPGUARDS, "NoIndirectJumpGuards" }, +{ MIPS_FEATURE_HASCRC, "HasCRC" }, +{ MIPS_FEATURE_HASVIRT, "HasVirt" }, +{ MIPS_FEATURE_HASGINV, "HasGINV" }, +{ MIPS_FEATURE_HASTLB, "HasTLB" }, +{ MIPS_FEATURE_ISFP64BIT, "IsFP64bit" }, +{ MIPS_FEATURE_NOTFP64BIT, "NotFP64bit" }, +{ MIPS_FEATURE_ISSINGLEFLOAT, "IsSingleFloat" }, +{ MIPS_FEATURE_ISNOTSINGLEFLOAT, "IsNotSingleFloat" }, +{ MIPS_FEATURE_ISNOTSOFTFLOAT, "IsNotSoftFloat" }, +{ MIPS_FEATURE_HASMIPS3D, "HasMips3D" }, +{ MIPS_FEATURE_HASDSP, "HasDSP" }, +{ MIPS_FEATURE_HASDSPR2, "HasDSPR2" }, +{ MIPS_FEATURE_HASDSPR3, "HasDSPR3" }, diff --git a/arch/Mips/MipsGenCSInsnEnum.inc b/arch/Mips/MipsGenCSInsnEnum.inc new file mode 100644 index 000000000..202f97f4c --- /dev/null +++ b/arch/Mips/MipsGenCSInsnEnum.inc @@ -0,0 +1,1373 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + MIPS_INS_INVALID, + MIPS_INS_ABS, + MIPS_INS_ALIGN, + MIPS_INS_BEQL, + MIPS_INS_BGE, + MIPS_INS_BGEL, + MIPS_INS_BGEU, + MIPS_INS_BGEUL, + MIPS_INS_BGT, + MIPS_INS_BGTL, + MIPS_INS_BGTU, + MIPS_INS_BGTUL, + MIPS_INS_BLE, + MIPS_INS_BLEL, + MIPS_INS_BLEU, + MIPS_INS_BLEUL, + MIPS_INS_BLT, + MIPS_INS_BLTL, + MIPS_INS_BLTU, + MIPS_INS_BLTUL, + MIPS_INS_BNEL, + MIPS_INS_B, + MIPS_INS_BEQ, + MIPS_INS_BNE, + MIPS_INS_CFTC1, + MIPS_INS_CTTC1, + MIPS_INS_DMUL, + MIPS_INS_DMULO, + MIPS_INS_DMULOU, + MIPS_INS_DROL, + MIPS_INS_DROR, + MIPS_INS_DDIV, + MIPS_INS_DREM, + MIPS_INS_DDIVU, + MIPS_INS_DREMU, + MIPS_INS_JAL, + MIPS_INS_LD, + MIPS_INS_LWM, + MIPS_INS_LA, + MIPS_INS_DLA, + MIPS_INS_LI, + MIPS_INS_DLI, + MIPS_INS_LI_D, + MIPS_INS_LI_S, + MIPS_INS_MFTACX, + MIPS_INS_MFTC0, + MIPS_INS_MFTC1, + MIPS_INS_MFTDSP, + MIPS_INS_MFTGPR, + MIPS_INS_MFTHC1, + MIPS_INS_MFTHI, + MIPS_INS_MFTLO, + MIPS_INS_MTTACX, + MIPS_INS_MTTC0, + MIPS_INS_MTTC1, + MIPS_INS_MTTDSP, + MIPS_INS_MTTGPR, + MIPS_INS_MTTHC1, + MIPS_INS_MTTHI, + MIPS_INS_MTTLO, + MIPS_INS_MUL, + MIPS_INS_MULO, + MIPS_INS_MULOU, + MIPS_INS_NOR, + MIPS_INS_ADDIU, + MIPS_INS_ANDI, + MIPS_INS_SUBU, + MIPS_INS_TRUNC_W_D, + MIPS_INS_TRUNC_W_S, + MIPS_INS_ROL, + MIPS_INS_ROR, + MIPS_INS_S_D, + MIPS_INS_SD, + MIPS_INS_DIV, + MIPS_INS_SEQ, + MIPS_INS_SGE, + MIPS_INS_SGEU, + MIPS_INS_SGT, + MIPS_INS_SGTU, + MIPS_INS_SLE, + MIPS_INS_SLEU, + MIPS_INS_SLT, + MIPS_INS_SLTU, + MIPS_INS_SNE, + MIPS_INS_REM, + MIPS_INS_SWM, + MIPS_INS_SAA, + MIPS_INS_SAAD, + MIPS_INS_DIVU, + MIPS_INS_REMU, + MIPS_INS_ULH, + MIPS_INS_ULHU, + MIPS_INS_ULW, + MIPS_INS_USH, + MIPS_INS_USW, + MIPS_INS_ABSQ_S_PH, + MIPS_INS_ABSQ_S_QB, + MIPS_INS_ABSQ_S_W, + MIPS_INS_ADD, + MIPS_INS_ADDIUPC, + MIPS_INS_ADDIUR1SP, + MIPS_INS_ADDIUR2, + MIPS_INS_ADDIUS5, + MIPS_INS_ADDIUSP, + MIPS_INS_ADDQH_PH, + MIPS_INS_ADDQH_R_PH, + MIPS_INS_ADDQH_R_W, + MIPS_INS_ADDQH_W, + MIPS_INS_ADDQ_PH, + MIPS_INS_ADDQ_S_PH, + MIPS_INS_ADDQ_S_W, + MIPS_INS_ADDR_PS, + MIPS_INS_ADDSC, + MIPS_INS_ADDS_A_B, + MIPS_INS_ADDS_A_D, + MIPS_INS_ADDS_A_H, + MIPS_INS_ADDS_A_W, + MIPS_INS_ADDS_S_B, + MIPS_INS_ADDS_S_D, + MIPS_INS_ADDS_S_H, + MIPS_INS_ADDS_S_W, + MIPS_INS_ADDS_U_B, + MIPS_INS_ADDS_U_D, + MIPS_INS_ADDS_U_H, + MIPS_INS_ADDS_U_W, + MIPS_INS_ADDU16, + MIPS_INS_ADDUH_QB, + MIPS_INS_ADDUH_R_QB, + MIPS_INS_ADDU, + MIPS_INS_ADDU_PH, + MIPS_INS_ADDU_QB, + MIPS_INS_ADDU_S_PH, + MIPS_INS_ADDU_S_QB, + MIPS_INS_ADDVI_B, + MIPS_INS_ADDVI_D, + MIPS_INS_ADDVI_H, + MIPS_INS_ADDVI_W, + MIPS_INS_ADDV_B, + MIPS_INS_ADDV_D, + MIPS_INS_ADDV_H, + MIPS_INS_ADDV_W, + MIPS_INS_ADDWC, + MIPS_INS_ADD_A_B, + MIPS_INS_ADD_A_D, + MIPS_INS_ADD_A_H, + MIPS_INS_ADD_A_W, + MIPS_INS_ADDI, + MIPS_INS_ALUIPC, + MIPS_INS_AND, + MIPS_INS_AND16, + MIPS_INS_ANDI16, + MIPS_INS_ANDI_B, + MIPS_INS_AND_V, + MIPS_INS_APPEND, + MIPS_INS_ASUB_S_B, + MIPS_INS_ASUB_S_D, + MIPS_INS_ASUB_S_H, + MIPS_INS_ASUB_S_W, + MIPS_INS_ASUB_U_B, + MIPS_INS_ASUB_U_D, + MIPS_INS_ASUB_U_H, + MIPS_INS_ASUB_U_W, + MIPS_INS_AUI, + MIPS_INS_AUIPC, + MIPS_INS_AVER_S_B, + MIPS_INS_AVER_S_D, + MIPS_INS_AVER_S_H, + MIPS_INS_AVER_S_W, + MIPS_INS_AVER_U_B, + MIPS_INS_AVER_U_D, + MIPS_INS_AVER_U_H, + MIPS_INS_AVER_U_W, + MIPS_INS_AVE_S_B, + MIPS_INS_AVE_S_D, + MIPS_INS_AVE_S_H, + MIPS_INS_AVE_S_W, + MIPS_INS_AVE_U_B, + MIPS_INS_AVE_U_D, + MIPS_INS_AVE_U_H, + MIPS_INS_AVE_U_W, + MIPS_INS_B16, + MIPS_INS_BADDU, + MIPS_INS_BAL, + MIPS_INS_BALC, + MIPS_INS_BALIGN, + MIPS_INS_BALRSC, + MIPS_INS_BBEQZC, + MIPS_INS_BBIT0, + MIPS_INS_BBIT032, + MIPS_INS_BBIT1, + MIPS_INS_BBIT132, + MIPS_INS_BBNEZC, + MIPS_INS_BC, + MIPS_INS_BC16, + MIPS_INS_BC1EQZ, + MIPS_INS_BC1EQZC, + MIPS_INS_BC1F, + MIPS_INS_BC1FL, + MIPS_INS_BC1NEZ, + MIPS_INS_BC1NEZC, + MIPS_INS_BC1T, + MIPS_INS_BC1TL, + MIPS_INS_BC2EQZ, + MIPS_INS_BC2EQZC, + MIPS_INS_BC2NEZ, + MIPS_INS_BC2NEZC, + MIPS_INS_BCLRI_B, + MIPS_INS_BCLRI_D, + MIPS_INS_BCLRI_H, + MIPS_INS_BCLRI_W, + MIPS_INS_BCLR_B, + MIPS_INS_BCLR_D, + MIPS_INS_BCLR_H, + MIPS_INS_BCLR_W, + MIPS_INS_BEQC, + MIPS_INS_BEQIC, + MIPS_INS_BEQZ16, + MIPS_INS_BEQZALC, + MIPS_INS_BEQZC, + MIPS_INS_BEQZC16, + MIPS_INS_BGEC, + MIPS_INS_BGEIC, + MIPS_INS_BGEIUC, + MIPS_INS_BGEUC, + MIPS_INS_BGEZ, + MIPS_INS_BGEZAL, + MIPS_INS_BGEZALC, + MIPS_INS_BGEZALL, + MIPS_INS_BGEZALS, + MIPS_INS_BGEZC, + MIPS_INS_BGEZL, + MIPS_INS_BGTZ, + MIPS_INS_BGTZALC, + MIPS_INS_BGTZC, + MIPS_INS_BGTZL, + MIPS_INS_BINSLI_B, + MIPS_INS_BINSLI_D, + MIPS_INS_BINSLI_H, + MIPS_INS_BINSLI_W, + MIPS_INS_BINSL_B, + MIPS_INS_BINSL_D, + MIPS_INS_BINSL_H, + MIPS_INS_BINSL_W, + MIPS_INS_BINSRI_B, + MIPS_INS_BINSRI_D, + MIPS_INS_BINSRI_H, + MIPS_INS_BINSRI_W, + MIPS_INS_BINSR_B, + MIPS_INS_BINSR_D, + MIPS_INS_BINSR_H, + MIPS_INS_BINSR_W, + MIPS_INS_BITREV, + MIPS_INS_BITREVW, + MIPS_INS_BITSWAP, + MIPS_INS_BLEZ, + MIPS_INS_BLEZALC, + MIPS_INS_BLEZC, + MIPS_INS_BLEZL, + MIPS_INS_BLTC, + MIPS_INS_BLTIC, + MIPS_INS_BLTIUC, + MIPS_INS_BLTUC, + MIPS_INS_BLTZ, + MIPS_INS_BLTZAL, + MIPS_INS_BLTZALC, + MIPS_INS_BLTZALL, + MIPS_INS_BLTZALS, + MIPS_INS_BLTZC, + MIPS_INS_BLTZL, + MIPS_INS_BMNZI_B, + MIPS_INS_BMNZ_V, + MIPS_INS_BMZI_B, + MIPS_INS_BMZ_V, + MIPS_INS_BNEC, + MIPS_INS_BNEGI_B, + MIPS_INS_BNEGI_D, + MIPS_INS_BNEGI_H, + MIPS_INS_BNEGI_W, + MIPS_INS_BNEG_B, + MIPS_INS_BNEG_D, + MIPS_INS_BNEG_H, + MIPS_INS_BNEG_W, + MIPS_INS_BNEIC, + MIPS_INS_BNEZ16, + MIPS_INS_BNEZALC, + MIPS_INS_BNEZC, + MIPS_INS_BNEZC16, + MIPS_INS_BNVC, + MIPS_INS_BNZ_B, + MIPS_INS_BNZ_D, + MIPS_INS_BNZ_H, + MIPS_INS_BNZ_V, + MIPS_INS_BNZ_W, + MIPS_INS_BOVC, + MIPS_INS_BPOSGE32, + MIPS_INS_BPOSGE32C, + MIPS_INS_BREAK, + MIPS_INS_BREAK16, + MIPS_INS_BRSC, + MIPS_INS_BSELI_B, + MIPS_INS_BSEL_V, + MIPS_INS_BSETI_B, + MIPS_INS_BSETI_D, + MIPS_INS_BSETI_H, + MIPS_INS_BSETI_W, + MIPS_INS_BSET_B, + MIPS_INS_BSET_D, + MIPS_INS_BSET_H, + MIPS_INS_BSET_W, + MIPS_INS_BYTEREVW, + MIPS_INS_BZ_B, + MIPS_INS_BZ_D, + MIPS_INS_BZ_H, + MIPS_INS_BZ_V, + MIPS_INS_BZ_W, + MIPS_INS_BEQZ, + MIPS_INS_BNEZ, + MIPS_INS_BTEQZ, + MIPS_INS_BTNEZ, + MIPS_INS_CACHE, + MIPS_INS_CACHEE, + MIPS_INS_CEIL_L_D, + MIPS_INS_CEIL_L_S, + MIPS_INS_CEIL_W_D, + MIPS_INS_CEIL_W_S, + MIPS_INS_CEQI_B, + MIPS_INS_CEQI_D, + MIPS_INS_CEQI_H, + MIPS_INS_CEQI_W, + MIPS_INS_CEQ_B, + MIPS_INS_CEQ_D, + MIPS_INS_CEQ_H, + MIPS_INS_CEQ_W, + MIPS_INS_CFC1, + MIPS_INS_CFC2, + MIPS_INS_CFCMSA, + MIPS_INS_CINS, + MIPS_INS_CINS32, + MIPS_INS_CLASS_D, + MIPS_INS_CLASS_S, + MIPS_INS_CLEI_S_B, + MIPS_INS_CLEI_S_D, + MIPS_INS_CLEI_S_H, + MIPS_INS_CLEI_S_W, + MIPS_INS_CLEI_U_B, + MIPS_INS_CLEI_U_D, + MIPS_INS_CLEI_U_H, + MIPS_INS_CLEI_U_W, + MIPS_INS_CLE_S_B, + MIPS_INS_CLE_S_D, + MIPS_INS_CLE_S_H, + MIPS_INS_CLE_S_W, + MIPS_INS_CLE_U_B, + MIPS_INS_CLE_U_D, + MIPS_INS_CLE_U_H, + MIPS_INS_CLE_U_W, + MIPS_INS_CLO, + MIPS_INS_CLTI_S_B, + MIPS_INS_CLTI_S_D, + MIPS_INS_CLTI_S_H, + MIPS_INS_CLTI_S_W, + MIPS_INS_CLTI_U_B, + MIPS_INS_CLTI_U_D, + MIPS_INS_CLTI_U_H, + MIPS_INS_CLTI_U_W, + MIPS_INS_CLT_S_B, + MIPS_INS_CLT_S_D, + MIPS_INS_CLT_S_H, + MIPS_INS_CLT_S_W, + MIPS_INS_CLT_U_B, + MIPS_INS_CLT_U_D, + MIPS_INS_CLT_U_H, + MIPS_INS_CLT_U_W, + MIPS_INS_CLZ, + MIPS_INS_CMPGDU_EQ_QB, + MIPS_INS_CMPGDU_LE_QB, + MIPS_INS_CMPGDU_LT_QB, + MIPS_INS_CMPGU_EQ_QB, + MIPS_INS_CMPGU_LE_QB, + MIPS_INS_CMPGU_LT_QB, + MIPS_INS_CMPU_EQ_QB, + MIPS_INS_CMPU_LE_QB, + MIPS_INS_CMPU_LT_QB, + MIPS_INS_CMP_AF_D, + MIPS_INS_CMP_AF_S, + MIPS_INS_CMP_EQ_D, + MIPS_INS_CMP_EQ_PH, + MIPS_INS_CMP_EQ_S, + MIPS_INS_CMP_LE_D, + MIPS_INS_CMP_LE_PH, + MIPS_INS_CMP_LE_S, + MIPS_INS_CMP_LT_D, + MIPS_INS_CMP_LT_PH, + MIPS_INS_CMP_LT_S, + MIPS_INS_CMP_SAF_D, + MIPS_INS_CMP_SAF_S, + MIPS_INS_CMP_SEQ_D, + MIPS_INS_CMP_SEQ_S, + MIPS_INS_CMP_SLE_D, + MIPS_INS_CMP_SLE_S, + MIPS_INS_CMP_SLT_D, + MIPS_INS_CMP_SLT_S, + MIPS_INS_CMP_SUEQ_D, + MIPS_INS_CMP_SUEQ_S, + MIPS_INS_CMP_SULE_D, + MIPS_INS_CMP_SULE_S, + MIPS_INS_CMP_SULT_D, + MIPS_INS_CMP_SULT_S, + MIPS_INS_CMP_SUN_D, + MIPS_INS_CMP_SUN_S, + MIPS_INS_CMP_UEQ_D, + MIPS_INS_CMP_UEQ_S, + MIPS_INS_CMP_ULE_D, + MIPS_INS_CMP_ULE_S, + MIPS_INS_CMP_ULT_D, + MIPS_INS_CMP_ULT_S, + MIPS_INS_CMP_UN_D, + MIPS_INS_CMP_UN_S, + MIPS_INS_COPY_S_B, + MIPS_INS_COPY_S_D, + MIPS_INS_COPY_S_H, + MIPS_INS_COPY_S_W, + MIPS_INS_COPY_U_B, + MIPS_INS_COPY_U_H, + MIPS_INS_COPY_U_W, + MIPS_INS_CRC32B, + MIPS_INS_CRC32CB, + MIPS_INS_CRC32CD, + MIPS_INS_CRC32CH, + MIPS_INS_CRC32CW, + MIPS_INS_CRC32D, + MIPS_INS_CRC32H, + MIPS_INS_CRC32W, + MIPS_INS_CTC1, + MIPS_INS_CTC2, + MIPS_INS_CTCMSA, + MIPS_INS_CVT_D_S, + MIPS_INS_CVT_D_W, + MIPS_INS_CVT_D_L, + MIPS_INS_CVT_L_D, + MIPS_INS_CVT_L_S, + MIPS_INS_CVT_PS_PW, + MIPS_INS_CVT_PS_S, + MIPS_INS_CVT_PW_PS, + MIPS_INS_CVT_S_D, + MIPS_INS_CVT_S_L, + MIPS_INS_CVT_S_PL, + MIPS_INS_CVT_S_PU, + MIPS_INS_CVT_S_W, + MIPS_INS_CVT_W_D, + MIPS_INS_CVT_W_S, + MIPS_INS_C_EQ_D, + MIPS_INS_C_EQ_S, + MIPS_INS_C_F_D, + MIPS_INS_C_F_S, + MIPS_INS_C_LE_D, + MIPS_INS_C_LE_S, + MIPS_INS_C_LT_D, + MIPS_INS_C_LT_S, + MIPS_INS_C_NGE_D, + MIPS_INS_C_NGE_S, + MIPS_INS_C_NGLE_D, + MIPS_INS_C_NGLE_S, + MIPS_INS_C_NGL_D, + MIPS_INS_C_NGL_S, + MIPS_INS_C_NGT_D, + MIPS_INS_C_NGT_S, + MIPS_INS_C_OLE_D, + MIPS_INS_C_OLE_S, + MIPS_INS_C_OLT_D, + MIPS_INS_C_OLT_S, + MIPS_INS_C_SEQ_D, + MIPS_INS_C_SEQ_S, + MIPS_INS_C_SF_D, + MIPS_INS_C_SF_S, + MIPS_INS_C_UEQ_D, + MIPS_INS_C_UEQ_S, + MIPS_INS_C_ULE_D, + MIPS_INS_C_ULE_S, + MIPS_INS_C_ULT_D, + MIPS_INS_C_ULT_S, + MIPS_INS_C_UN_D, + MIPS_INS_C_UN_S, + MIPS_INS_CMP, + MIPS_INS_CMPI, + MIPS_INS_DADD, + MIPS_INS_DADDI, + MIPS_INS_DADDIU, + MIPS_INS_DADDU, + MIPS_INS_DAHI, + MIPS_INS_DALIGN, + MIPS_INS_DATI, + MIPS_INS_DAUI, + MIPS_INS_DBITSWAP, + MIPS_INS_DCLO, + MIPS_INS_DCLZ, + MIPS_INS_DERET, + MIPS_INS_DEXT, + MIPS_INS_DEXTM, + MIPS_INS_DEXTU, + MIPS_INS_DI, + MIPS_INS_DINS, + MIPS_INS_DINSM, + MIPS_INS_DINSU, + MIPS_INS_DIV_S_B, + MIPS_INS_DIV_S_D, + MIPS_INS_DIV_S_H, + MIPS_INS_DIV_S_W, + MIPS_INS_DIV_U_B, + MIPS_INS_DIV_U_D, + MIPS_INS_DIV_U_H, + MIPS_INS_DIV_U_W, + MIPS_INS_DLSA, + MIPS_INS_DMFC0, + MIPS_INS_DMFC1, + MIPS_INS_DMFC2, + MIPS_INS_DMFGC0, + MIPS_INS_DMOD, + MIPS_INS_DMODU, + MIPS_INS_DMT, + MIPS_INS_DMTC0, + MIPS_INS_DMTC1, + MIPS_INS_DMTC2, + MIPS_INS_DMTGC0, + MIPS_INS_DMUH, + MIPS_INS_DMUHU, + MIPS_INS_DMULT, + MIPS_INS_DMULTU, + MIPS_INS_DMULU, + MIPS_INS_DOTP_S_D, + MIPS_INS_DOTP_S_H, + MIPS_INS_DOTP_S_W, + MIPS_INS_DOTP_U_D, + MIPS_INS_DOTP_U_H, + MIPS_INS_DOTP_U_W, + MIPS_INS_DPADD_S_D, + MIPS_INS_DPADD_S_H, + MIPS_INS_DPADD_S_W, + MIPS_INS_DPADD_U_D, + MIPS_INS_DPADD_U_H, + MIPS_INS_DPADD_U_W, + MIPS_INS_DPAQX_SA_W_PH, + MIPS_INS_DPAQX_S_W_PH, + MIPS_INS_DPAQ_SA_L_W, + MIPS_INS_DPAQ_S_W_PH, + MIPS_INS_DPAU_H_QBL, + MIPS_INS_DPAU_H_QBR, + MIPS_INS_DPAX_W_PH, + MIPS_INS_DPA_W_PH, + MIPS_INS_DPOP, + MIPS_INS_DPSQX_SA_W_PH, + MIPS_INS_DPSQX_S_W_PH, + MIPS_INS_DPSQ_SA_L_W, + MIPS_INS_DPSQ_S_W_PH, + MIPS_INS_DPSUB_S_D, + MIPS_INS_DPSUB_S_H, + MIPS_INS_DPSUB_S_W, + MIPS_INS_DPSUB_U_D, + MIPS_INS_DPSUB_U_H, + MIPS_INS_DPSUB_U_W, + MIPS_INS_DPSU_H_QBL, + MIPS_INS_DPSU_H_QBR, + MIPS_INS_DPSX_W_PH, + MIPS_INS_DPS_W_PH, + MIPS_INS_DROTR, + MIPS_INS_DROTR32, + MIPS_INS_DROTRV, + MIPS_INS_DSBH, + MIPS_INS_DSHD, + MIPS_INS_DSLL, + MIPS_INS_DSLL32, + MIPS_INS_DSLLV, + MIPS_INS_DSRA, + MIPS_INS_DSRA32, + MIPS_INS_DSRAV, + MIPS_INS_DSRL, + MIPS_INS_DSRL32, + MIPS_INS_DSRLV, + MIPS_INS_DSUB, + MIPS_INS_DSUBU, + MIPS_INS_DVP, + MIPS_INS_DVPE, + MIPS_INS_EHB, + MIPS_INS_EI, + MIPS_INS_EMT, + MIPS_INS_ERET, + MIPS_INS_ERETNC, + MIPS_INS_EVP, + MIPS_INS_EVPE, + MIPS_INS_EXT, + MIPS_INS_EXTP, + MIPS_INS_EXTPDP, + MIPS_INS_EXTPDPV, + MIPS_INS_EXTPV, + MIPS_INS_EXTRV_RS_W, + MIPS_INS_EXTRV_R_W, + MIPS_INS_EXTRV_S_H, + MIPS_INS_EXTRV_W, + MIPS_INS_EXTR_RS_W, + MIPS_INS_EXTR_R_W, + MIPS_INS_EXTR_S_H, + MIPS_INS_EXTR_W, + MIPS_INS_EXTS, + MIPS_INS_EXTS32, + MIPS_INS_EXTW, + MIPS_INS_ABS_D, + MIPS_INS_ABS_S, + MIPS_INS_FADD_D, + MIPS_INS_ADD_D, + MIPS_INS_ADD_PS, + MIPS_INS_ADD_S, + MIPS_INS_FADD_W, + MIPS_INS_FCAF_D, + MIPS_INS_FCAF_W, + MIPS_INS_FCEQ_D, + MIPS_INS_FCEQ_W, + MIPS_INS_FCLASS_D, + MIPS_INS_FCLASS_W, + MIPS_INS_FCLE_D, + MIPS_INS_FCLE_W, + MIPS_INS_FCLT_D, + MIPS_INS_FCLT_W, + MIPS_INS_FCNE_D, + MIPS_INS_FCNE_W, + MIPS_INS_FCOR_D, + MIPS_INS_FCOR_W, + MIPS_INS_FCUEQ_D, + MIPS_INS_FCUEQ_W, + MIPS_INS_FCULE_D, + MIPS_INS_FCULE_W, + MIPS_INS_FCULT_D, + MIPS_INS_FCULT_W, + MIPS_INS_FCUNE_D, + MIPS_INS_FCUNE_W, + MIPS_INS_FCUN_D, + MIPS_INS_FCUN_W, + MIPS_INS_FDIV_D, + MIPS_INS_DIV_D, + MIPS_INS_DIV_S, + MIPS_INS_FDIV_W, + MIPS_INS_FEXDO_H, + MIPS_INS_FEXDO_W, + MIPS_INS_FEXP2_D, + MIPS_INS_FEXP2_W, + MIPS_INS_FEXUPL_D, + MIPS_INS_FEXUPL_W, + MIPS_INS_FEXUPR_D, + MIPS_INS_FEXUPR_W, + MIPS_INS_FFINT_S_D, + MIPS_INS_FFINT_S_W, + MIPS_INS_FFINT_U_D, + MIPS_INS_FFINT_U_W, + MIPS_INS_FFQL_D, + MIPS_INS_FFQL_W, + MIPS_INS_FFQR_D, + MIPS_INS_FFQR_W, + MIPS_INS_FILL_B, + MIPS_INS_FILL_D, + MIPS_INS_FILL_H, + MIPS_INS_FILL_W, + MIPS_INS_FLOG2_D, + MIPS_INS_FLOG2_W, + MIPS_INS_FLOOR_L_D, + MIPS_INS_FLOOR_L_S, + MIPS_INS_FLOOR_W_D, + MIPS_INS_FLOOR_W_S, + MIPS_INS_FMADD_D, + MIPS_INS_FMADD_W, + MIPS_INS_FMAX_A_D, + MIPS_INS_FMAX_A_W, + MIPS_INS_FMAX_D, + MIPS_INS_FMAX_W, + MIPS_INS_FMIN_A_D, + MIPS_INS_FMIN_A_W, + MIPS_INS_FMIN_D, + MIPS_INS_FMIN_W, + MIPS_INS_MOV_D, + MIPS_INS_MOV_S, + MIPS_INS_FMSUB_D, + MIPS_INS_FMSUB_W, + MIPS_INS_FMUL_D, + MIPS_INS_MUL_D, + MIPS_INS_MUL_PS, + MIPS_INS_MUL_S, + MIPS_INS_FMUL_W, + MIPS_INS_NEG_D, + MIPS_INS_NEG_S, + MIPS_INS_FORK, + MIPS_INS_FRCP_D, + MIPS_INS_FRCP_W, + MIPS_INS_FRINT_D, + MIPS_INS_FRINT_W, + MIPS_INS_FRSQRT_D, + MIPS_INS_FRSQRT_W, + MIPS_INS_FSAF_D, + MIPS_INS_FSAF_W, + MIPS_INS_FSEQ_D, + MIPS_INS_FSEQ_W, + MIPS_INS_FSLE_D, + MIPS_INS_FSLE_W, + MIPS_INS_FSLT_D, + MIPS_INS_FSLT_W, + MIPS_INS_FSNE_D, + MIPS_INS_FSNE_W, + MIPS_INS_FSOR_D, + MIPS_INS_FSOR_W, + MIPS_INS_FSQRT_D, + MIPS_INS_SQRT_D, + MIPS_INS_SQRT_S, + MIPS_INS_FSQRT_W, + MIPS_INS_FSUB_D, + MIPS_INS_SUB_D, + MIPS_INS_SUB_PS, + MIPS_INS_SUB_S, + MIPS_INS_FSUB_W, + MIPS_INS_FSUEQ_D, + MIPS_INS_FSUEQ_W, + MIPS_INS_FSULE_D, + MIPS_INS_FSULE_W, + MIPS_INS_FSULT_D, + MIPS_INS_FSULT_W, + MIPS_INS_FSUNE_D, + MIPS_INS_FSUNE_W, + MIPS_INS_FSUN_D, + MIPS_INS_FSUN_W, + MIPS_INS_FTINT_S_D, + MIPS_INS_FTINT_S_W, + MIPS_INS_FTINT_U_D, + MIPS_INS_FTINT_U_W, + MIPS_INS_FTQ_H, + MIPS_INS_FTQ_W, + MIPS_INS_FTRUNC_S_D, + MIPS_INS_FTRUNC_S_W, + MIPS_INS_FTRUNC_U_D, + MIPS_INS_FTRUNC_U_W, + MIPS_INS_GINVI, + MIPS_INS_GINVT, + MIPS_INS_HADD_S_D, + MIPS_INS_HADD_S_H, + MIPS_INS_HADD_S_W, + MIPS_INS_HADD_U_D, + MIPS_INS_HADD_U_H, + MIPS_INS_HADD_U_W, + MIPS_INS_HSUB_S_D, + MIPS_INS_HSUB_S_H, + MIPS_INS_HSUB_S_W, + MIPS_INS_HSUB_U_D, + MIPS_INS_HSUB_U_H, + MIPS_INS_HSUB_U_W, + MIPS_INS_HYPCALL, + MIPS_INS_ILVEV_B, + MIPS_INS_ILVEV_D, + MIPS_INS_ILVEV_H, + MIPS_INS_ILVEV_W, + MIPS_INS_ILVL_B, + MIPS_INS_ILVL_D, + MIPS_INS_ILVL_H, + MIPS_INS_ILVL_W, + MIPS_INS_ILVOD_B, + MIPS_INS_ILVOD_D, + MIPS_INS_ILVOD_H, + MIPS_INS_ILVOD_W, + MIPS_INS_ILVR_B, + MIPS_INS_ILVR_D, + MIPS_INS_ILVR_H, + MIPS_INS_ILVR_W, + MIPS_INS_INS, + MIPS_INS_INSERT_B, + MIPS_INS_INSERT_D, + MIPS_INS_INSERT_H, + MIPS_INS_INSERT_W, + MIPS_INS_INSV, + MIPS_INS_INSVE_B, + MIPS_INS_INSVE_D, + MIPS_INS_INSVE_H, + MIPS_INS_INSVE_W, + MIPS_INS_J, + MIPS_INS_JALR, + MIPS_INS_JALRC, + MIPS_INS_JALRC_HB, + MIPS_INS_JALRS16, + MIPS_INS_JALRS, + MIPS_INS_JALR_HB, + MIPS_INS_JALS, + MIPS_INS_JALX, + MIPS_INS_JIALC, + MIPS_INS_JIC, + MIPS_INS_JR, + MIPS_INS_JR16, + MIPS_INS_JRADDIUSP, + MIPS_INS_JRC, + MIPS_INS_JRC16, + MIPS_INS_JRCADDIUSP, + MIPS_INS_JR_HB, + MIPS_INS_LAPC_H, + MIPS_INS_LAPC_B, + MIPS_INS_LB, + MIPS_INS_LBE, + MIPS_INS_LBU16, + MIPS_INS_LBU, + MIPS_INS_LBUX, + MIPS_INS_LBX, + MIPS_INS_LBUE, + MIPS_INS_LDC1, + MIPS_INS_LDC2, + MIPS_INS_LDC3, + MIPS_INS_LDI_B, + MIPS_INS_LDI_D, + MIPS_INS_LDI_H, + MIPS_INS_LDI_W, + MIPS_INS_LDL, + MIPS_INS_LDPC, + MIPS_INS_LDR, + MIPS_INS_LDXC1, + MIPS_INS_LD_B, + MIPS_INS_LD_D, + MIPS_INS_LD_H, + MIPS_INS_LD_W, + MIPS_INS_LH, + MIPS_INS_LHE, + MIPS_INS_LHU16, + MIPS_INS_LHU, + MIPS_INS_LHUXS, + MIPS_INS_LHUX, + MIPS_INS_LHX, + MIPS_INS_LHXS, + MIPS_INS_LHUE, + MIPS_INS_LI16, + MIPS_INS_LL, + MIPS_INS_LLD, + MIPS_INS_LLE, + MIPS_INS_LLWP, + MIPS_INS_LSA, + MIPS_INS_LUI, + MIPS_INS_LUXC1, + MIPS_INS_LW, + MIPS_INS_LW16, + MIPS_INS_LWC1, + MIPS_INS_LWC2, + MIPS_INS_LWC3, + MIPS_INS_LWE, + MIPS_INS_LWL, + MIPS_INS_LWLE, + MIPS_INS_LWM16, + MIPS_INS_LWM32, + MIPS_INS_LWPC, + MIPS_INS_LWP, + MIPS_INS_LWR, + MIPS_INS_LWRE, + MIPS_INS_LWUPC, + MIPS_INS_LWU, + MIPS_INS_LWX, + MIPS_INS_LWXC1, + MIPS_INS_LWXS, + MIPS_INS_MADD, + MIPS_INS_MADDF_D, + MIPS_INS_MADDF_S, + MIPS_INS_MADDR_Q_H, + MIPS_INS_MADDR_Q_W, + MIPS_INS_MADDU, + MIPS_INS_MADDV_B, + MIPS_INS_MADDV_D, + MIPS_INS_MADDV_H, + MIPS_INS_MADDV_W, + MIPS_INS_MADD_D, + MIPS_INS_MADD_Q_H, + MIPS_INS_MADD_Q_W, + MIPS_INS_MADD_S, + MIPS_INS_MAQ_SA_W_PHL, + MIPS_INS_MAQ_SA_W_PHR, + MIPS_INS_MAQ_S_W_PHL, + MIPS_INS_MAQ_S_W_PHR, + MIPS_INS_MAXA_D, + MIPS_INS_MAXA_S, + MIPS_INS_MAXI_S_B, + MIPS_INS_MAXI_S_D, + MIPS_INS_MAXI_S_H, + MIPS_INS_MAXI_S_W, + MIPS_INS_MAXI_U_B, + MIPS_INS_MAXI_U_D, + MIPS_INS_MAXI_U_H, + MIPS_INS_MAXI_U_W, + MIPS_INS_MAX_A_B, + MIPS_INS_MAX_A_D, + MIPS_INS_MAX_A_H, + MIPS_INS_MAX_A_W, + MIPS_INS_MAX_D, + MIPS_INS_MAX_S, + MIPS_INS_MAX_S_B, + MIPS_INS_MAX_S_D, + MIPS_INS_MAX_S_H, + MIPS_INS_MAX_S_W, + MIPS_INS_MAX_U_B, + MIPS_INS_MAX_U_D, + MIPS_INS_MAX_U_H, + MIPS_INS_MAX_U_W, + MIPS_INS_MFC0, + MIPS_INS_MFC1, + MIPS_INS_MFC2, + MIPS_INS_MFGC0, + MIPS_INS_MFHC0, + MIPS_INS_MFHC1, + MIPS_INS_MFHC2, + MIPS_INS_MFHGC0, + MIPS_INS_MFHI, + MIPS_INS_MFHI16, + MIPS_INS_MFLO, + MIPS_INS_MFLO16, + MIPS_INS_MFTR, + MIPS_INS_MINA_D, + MIPS_INS_MINA_S, + MIPS_INS_MINI_S_B, + MIPS_INS_MINI_S_D, + MIPS_INS_MINI_S_H, + MIPS_INS_MINI_S_W, + MIPS_INS_MINI_U_B, + MIPS_INS_MINI_U_D, + MIPS_INS_MINI_U_H, + MIPS_INS_MINI_U_W, + MIPS_INS_MIN_A_B, + MIPS_INS_MIN_A_D, + MIPS_INS_MIN_A_H, + MIPS_INS_MIN_A_W, + MIPS_INS_MIN_D, + MIPS_INS_MIN_S, + MIPS_INS_MIN_S_B, + MIPS_INS_MIN_S_D, + MIPS_INS_MIN_S_H, + MIPS_INS_MIN_S_W, + MIPS_INS_MIN_U_B, + MIPS_INS_MIN_U_D, + MIPS_INS_MIN_U_H, + MIPS_INS_MIN_U_W, + MIPS_INS_MOD, + MIPS_INS_MODSUB, + MIPS_INS_MODU, + MIPS_INS_MOD_S_B, + MIPS_INS_MOD_S_D, + MIPS_INS_MOD_S_H, + MIPS_INS_MOD_S_W, + MIPS_INS_MOD_U_B, + MIPS_INS_MOD_U_D, + MIPS_INS_MOD_U_H, + MIPS_INS_MOD_U_W, + MIPS_INS_MOVE, + MIPS_INS_MOVE16, + MIPS_INS_MOVE_BALC, + MIPS_INS_MOVEP, + MIPS_INS_MOVE_V, + MIPS_INS_MOVF_D, + MIPS_INS_MOVF, + MIPS_INS_MOVF_S, + MIPS_INS_MOVN_D, + MIPS_INS_MOVN, + MIPS_INS_MOVN_S, + MIPS_INS_MOVT_D, + MIPS_INS_MOVT, + MIPS_INS_MOVT_S, + MIPS_INS_MOVZ_D, + MIPS_INS_MOVZ, + MIPS_INS_MOVZ_S, + MIPS_INS_MSUB, + MIPS_INS_MSUBF_D, + MIPS_INS_MSUBF_S, + MIPS_INS_MSUBR_Q_H, + MIPS_INS_MSUBR_Q_W, + MIPS_INS_MSUBU, + MIPS_INS_MSUBV_B, + MIPS_INS_MSUBV_D, + MIPS_INS_MSUBV_H, + MIPS_INS_MSUBV_W, + MIPS_INS_MSUB_D, + MIPS_INS_MSUB_Q_H, + MIPS_INS_MSUB_Q_W, + MIPS_INS_MSUB_S, + MIPS_INS_MTC0, + MIPS_INS_MTC1, + MIPS_INS_MTC2, + MIPS_INS_MTGC0, + MIPS_INS_MTHC0, + MIPS_INS_MTHC1, + MIPS_INS_MTHC2, + MIPS_INS_MTHGC0, + MIPS_INS_MTHI, + MIPS_INS_MTHLIP, + MIPS_INS_MTLO, + MIPS_INS_MTM0, + MIPS_INS_MTM1, + MIPS_INS_MTM2, + MIPS_INS_MTP0, + MIPS_INS_MTP1, + MIPS_INS_MTP2, + MIPS_INS_MTTR, + MIPS_INS_MUH, + MIPS_INS_MUHU, + MIPS_INS_MULEQ_S_W_PHL, + MIPS_INS_MULEQ_S_W_PHR, + MIPS_INS_MULEU_S_PH_QBL, + MIPS_INS_MULEU_S_PH_QBR, + MIPS_INS_MULQ_RS_PH, + MIPS_INS_MULQ_RS_W, + MIPS_INS_MULQ_S_PH, + MIPS_INS_MULQ_S_W, + MIPS_INS_MULR_PS, + MIPS_INS_MULR_Q_H, + MIPS_INS_MULR_Q_W, + MIPS_INS_MULSAQ_S_W_PH, + MIPS_INS_MULSA_W_PH, + MIPS_INS_MULT, + MIPS_INS_MULTU, + MIPS_INS_MULU, + MIPS_INS_MULV_B, + MIPS_INS_MULV_D, + MIPS_INS_MULV_H, + MIPS_INS_MULV_W, + MIPS_INS_MUL_PH, + MIPS_INS_MUL_Q_H, + MIPS_INS_MUL_Q_W, + MIPS_INS_MUL_S_PH, + MIPS_INS_NLOC_B, + MIPS_INS_NLOC_D, + MIPS_INS_NLOC_H, + MIPS_INS_NLOC_W, + MIPS_INS_NLZC_B, + MIPS_INS_NLZC_D, + MIPS_INS_NLZC_H, + MIPS_INS_NLZC_W, + MIPS_INS_NMADD_D, + MIPS_INS_NMADD_S, + MIPS_INS_NMSUB_D, + MIPS_INS_NMSUB_S, + MIPS_INS_NOP32, + MIPS_INS_NOP, + MIPS_INS_NORI_B, + MIPS_INS_NOR_V, + MIPS_INS_NOT16, + MIPS_INS_NOT, + MIPS_INS_NEG, + MIPS_INS_OR, + MIPS_INS_OR16, + MIPS_INS_ORI_B, + MIPS_INS_ORI, + MIPS_INS_OR_V, + MIPS_INS_PACKRL_PH, + MIPS_INS_PAUSE, + MIPS_INS_PCKEV_B, + MIPS_INS_PCKEV_D, + MIPS_INS_PCKEV_H, + MIPS_INS_PCKEV_W, + MIPS_INS_PCKOD_B, + MIPS_INS_PCKOD_D, + MIPS_INS_PCKOD_H, + MIPS_INS_PCKOD_W, + MIPS_INS_PCNT_B, + MIPS_INS_PCNT_D, + MIPS_INS_PCNT_H, + MIPS_INS_PCNT_W, + MIPS_INS_PICK_PH, + MIPS_INS_PICK_QB, + MIPS_INS_PLL_PS, + MIPS_INS_PLU_PS, + MIPS_INS_POP, + MIPS_INS_PRECEQU_PH_QBL, + MIPS_INS_PRECEQU_PH_QBLA, + MIPS_INS_PRECEQU_PH_QBR, + MIPS_INS_PRECEQU_PH_QBRA, + MIPS_INS_PRECEQ_W_PHL, + MIPS_INS_PRECEQ_W_PHR, + MIPS_INS_PRECEU_PH_QBL, + MIPS_INS_PRECEU_PH_QBLA, + MIPS_INS_PRECEU_PH_QBR, + MIPS_INS_PRECEU_PH_QBRA, + MIPS_INS_PRECRQU_S_QB_PH, + MIPS_INS_PRECRQ_PH_W, + MIPS_INS_PRECRQ_QB_PH, + MIPS_INS_PRECRQ_RS_PH_W, + MIPS_INS_PRECR_QB_PH, + MIPS_INS_PRECR_SRA_PH_W, + MIPS_INS_PRECR_SRA_R_PH_W, + MIPS_INS_PREF, + MIPS_INS_PREFE, + MIPS_INS_PREFX, + MIPS_INS_PREPEND, + MIPS_INS_PUL_PS, + MIPS_INS_PUU_PS, + MIPS_INS_RADDU_W_QB, + MIPS_INS_RDDSP, + MIPS_INS_RDHWR, + MIPS_INS_RDPGPR, + MIPS_INS_RECIP_D, + MIPS_INS_RECIP_S, + MIPS_INS_REPLV_PH, + MIPS_INS_REPLV_QB, + MIPS_INS_REPL_PH, + MIPS_INS_REPL_QB, + MIPS_INS_RESTORE_JRC, + MIPS_INS_RESTORE, + MIPS_INS_RINT_D, + MIPS_INS_RINT_S, + MIPS_INS_ROTR, + MIPS_INS_ROTRV, + MIPS_INS_ROTX, + MIPS_INS_ROUND_L_D, + MIPS_INS_ROUND_L_S, + MIPS_INS_ROUND_W_D, + MIPS_INS_ROUND_W_S, + MIPS_INS_RSQRT_D, + MIPS_INS_RSQRT_S, + MIPS_INS_SAT_S_B, + MIPS_INS_SAT_S_D, + MIPS_INS_SAT_S_H, + MIPS_INS_SAT_S_W, + MIPS_INS_SAT_U_B, + MIPS_INS_SAT_U_D, + MIPS_INS_SAT_U_H, + MIPS_INS_SAT_U_W, + MIPS_INS_SAVE, + MIPS_INS_SB, + MIPS_INS_SB16, + MIPS_INS_SBE, + MIPS_INS_SBX, + MIPS_INS_SC, + MIPS_INS_SCD, + MIPS_INS_SCE, + MIPS_INS_SCWP, + MIPS_INS_SDBBP, + MIPS_INS_SDBBP16, + MIPS_INS_SDC1, + MIPS_INS_SDC2, + MIPS_INS_SDC3, + MIPS_INS_SDL, + MIPS_INS_SDR, + MIPS_INS_SDXC1, + MIPS_INS_SEB, + MIPS_INS_SEH, + MIPS_INS_SELEQZ, + MIPS_INS_SELEQZ_D, + MIPS_INS_SELEQZ_S, + MIPS_INS_SELNEZ, + MIPS_INS_SELNEZ_D, + MIPS_INS_SELNEZ_S, + MIPS_INS_SEL_D, + MIPS_INS_SEL_S, + MIPS_INS_SEQI, + MIPS_INS_SH, + MIPS_INS_SH16, + MIPS_INS_SHE, + MIPS_INS_SHF_B, + MIPS_INS_SHF_H, + MIPS_INS_SHF_W, + MIPS_INS_SHILO, + MIPS_INS_SHILOV, + MIPS_INS_SHLLV_PH, + MIPS_INS_SHLLV_QB, + MIPS_INS_SHLLV_S_PH, + MIPS_INS_SHLLV_S_W, + MIPS_INS_SHLL_PH, + MIPS_INS_SHLL_QB, + MIPS_INS_SHLL_S_PH, + MIPS_INS_SHLL_S_W, + MIPS_INS_SHRAV_PH, + MIPS_INS_SHRAV_QB, + MIPS_INS_SHRAV_R_PH, + MIPS_INS_SHRAV_R_QB, + MIPS_INS_SHRAV_R_W, + MIPS_INS_SHRA_PH, + MIPS_INS_SHRA_QB, + MIPS_INS_SHRA_R_PH, + MIPS_INS_SHRA_R_QB, + MIPS_INS_SHRA_R_W, + MIPS_INS_SHRLV_PH, + MIPS_INS_SHRLV_QB, + MIPS_INS_SHRL_PH, + MIPS_INS_SHRL_QB, + MIPS_INS_SHXS, + MIPS_INS_SHX, + MIPS_INS_SIGRIE, + MIPS_INS_SLDI_B, + MIPS_INS_SLDI_D, + MIPS_INS_SLDI_H, + MIPS_INS_SLDI_W, + MIPS_INS_SLD_B, + MIPS_INS_SLD_D, + MIPS_INS_SLD_H, + MIPS_INS_SLD_W, + MIPS_INS_SLL, + MIPS_INS_SLL16, + MIPS_INS_SLLI_B, + MIPS_INS_SLLI_D, + MIPS_INS_SLLI_H, + MIPS_INS_SLLI_W, + MIPS_INS_SLLV, + MIPS_INS_SLL_B, + MIPS_INS_SLL_D, + MIPS_INS_SLL_H, + MIPS_INS_SLL_W, + MIPS_INS_SLTIU, + MIPS_INS_SLTI, + MIPS_INS_SNEI, + MIPS_INS_SOV, + MIPS_INS_SPLATI_B, + MIPS_INS_SPLATI_D, + MIPS_INS_SPLATI_H, + MIPS_INS_SPLATI_W, + MIPS_INS_SPLAT_B, + MIPS_INS_SPLAT_D, + MIPS_INS_SPLAT_H, + MIPS_INS_SPLAT_W, + MIPS_INS_SRA, + MIPS_INS_SRAI_B, + MIPS_INS_SRAI_D, + MIPS_INS_SRAI_H, + MIPS_INS_SRAI_W, + MIPS_INS_SRARI_B, + MIPS_INS_SRARI_D, + MIPS_INS_SRARI_H, + MIPS_INS_SRARI_W, + MIPS_INS_SRAR_B, + MIPS_INS_SRAR_D, + MIPS_INS_SRAR_H, + MIPS_INS_SRAR_W, + MIPS_INS_SRAV, + MIPS_INS_SRA_B, + MIPS_INS_SRA_D, + MIPS_INS_SRA_H, + MIPS_INS_SRA_W, + MIPS_INS_SRL, + MIPS_INS_SRL16, + MIPS_INS_SRLI_B, + MIPS_INS_SRLI_D, + MIPS_INS_SRLI_H, + MIPS_INS_SRLI_W, + MIPS_INS_SRLRI_B, + MIPS_INS_SRLRI_D, + MIPS_INS_SRLRI_H, + MIPS_INS_SRLRI_W, + MIPS_INS_SRLR_B, + MIPS_INS_SRLR_D, + MIPS_INS_SRLR_H, + MIPS_INS_SRLR_W, + MIPS_INS_SRLV, + MIPS_INS_SRL_B, + MIPS_INS_SRL_D, + MIPS_INS_SRL_H, + MIPS_INS_SRL_W, + MIPS_INS_SSNOP, + MIPS_INS_ST_B, + MIPS_INS_ST_D, + MIPS_INS_ST_H, + MIPS_INS_ST_W, + MIPS_INS_SUB, + MIPS_INS_SUBQH_PH, + MIPS_INS_SUBQH_R_PH, + MIPS_INS_SUBQH_R_W, + MIPS_INS_SUBQH_W, + MIPS_INS_SUBQ_PH, + MIPS_INS_SUBQ_S_PH, + MIPS_INS_SUBQ_S_W, + MIPS_INS_SUBSUS_U_B, + MIPS_INS_SUBSUS_U_D, + MIPS_INS_SUBSUS_U_H, + MIPS_INS_SUBSUS_U_W, + MIPS_INS_SUBSUU_S_B, + MIPS_INS_SUBSUU_S_D, + MIPS_INS_SUBSUU_S_H, + MIPS_INS_SUBSUU_S_W, + MIPS_INS_SUBS_S_B, + MIPS_INS_SUBS_S_D, + MIPS_INS_SUBS_S_H, + MIPS_INS_SUBS_S_W, + MIPS_INS_SUBS_U_B, + MIPS_INS_SUBS_U_D, + MIPS_INS_SUBS_U_H, + MIPS_INS_SUBS_U_W, + MIPS_INS_SUBU16, + MIPS_INS_SUBUH_QB, + MIPS_INS_SUBUH_R_QB, + MIPS_INS_SUBU_PH, + MIPS_INS_SUBU_QB, + MIPS_INS_SUBU_S_PH, + MIPS_INS_SUBU_S_QB, + MIPS_INS_SUBVI_B, + MIPS_INS_SUBVI_D, + MIPS_INS_SUBVI_H, + MIPS_INS_SUBVI_W, + MIPS_INS_SUBV_B, + MIPS_INS_SUBV_D, + MIPS_INS_SUBV_H, + MIPS_INS_SUBV_W, + MIPS_INS_SUXC1, + MIPS_INS_SW, + MIPS_INS_SW16, + MIPS_INS_SWC1, + MIPS_INS_SWC2, + MIPS_INS_SWC3, + MIPS_INS_SWE, + MIPS_INS_SWL, + MIPS_INS_SWLE, + MIPS_INS_SWM16, + MIPS_INS_SWM32, + MIPS_INS_SWPC, + MIPS_INS_SWP, + MIPS_INS_SWR, + MIPS_INS_SWRE, + MIPS_INS_SWSP, + MIPS_INS_SWXC1, + MIPS_INS_SWXS, + MIPS_INS_SWX, + MIPS_INS_SYNC, + MIPS_INS_SYNCI, + MIPS_INS_SYSCALL, + MIPS_INS_TEQ, + MIPS_INS_TEQI, + MIPS_INS_TGE, + MIPS_INS_TGEI, + MIPS_INS_TGEIU, + MIPS_INS_TGEU, + MIPS_INS_TLBGINV, + MIPS_INS_TLBGINVF, + MIPS_INS_TLBGP, + MIPS_INS_TLBGR, + MIPS_INS_TLBGWI, + MIPS_INS_TLBGWR, + MIPS_INS_TLBINV, + MIPS_INS_TLBINVF, + MIPS_INS_TLBP, + MIPS_INS_TLBR, + MIPS_INS_TLBWI, + MIPS_INS_TLBWR, + MIPS_INS_TLT, + MIPS_INS_TLTI, + MIPS_INS_TLTIU, + MIPS_INS_TLTU, + MIPS_INS_TNE, + MIPS_INS_TNEI, + MIPS_INS_TRUNC_L_D, + MIPS_INS_TRUNC_L_S, + MIPS_INS_UALH, + MIPS_INS_UALWM, + MIPS_INS_UALW, + MIPS_INS_UASH, + MIPS_INS_UASWM, + MIPS_INS_UASW, + MIPS_INS_V3MULU, + MIPS_INS_VMM0, + MIPS_INS_VMULU, + MIPS_INS_VSHF_B, + MIPS_INS_VSHF_D, + MIPS_INS_VSHF_H, + MIPS_INS_VSHF_W, + MIPS_INS_WAIT, + MIPS_INS_WRDSP, + MIPS_INS_WRPGPR, + MIPS_INS_WSBH, + MIPS_INS_XOR, + MIPS_INS_XOR16, + MIPS_INS_XORI_B, + MIPS_INS_XORI, + MIPS_INS_XOR_V, + MIPS_INS_YIELD, diff --git a/arch/Mips/MipsGenCSMappingInsn.inc b/arch/Mips/MipsGenCSMappingInsn.inc new file mode 100644 index 000000000..5e399ea74 --- /dev/null +++ b/arch/Mips/MipsGenCSMappingInsn.inc @@ -0,0 +1,24465 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{ + /* PHINODE */ + Mips_PHI /* 0 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INLINEASM /* 1 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INLINEASM_BR /* 2 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_CFI_INSTRUCTION /* 3 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_EH_LABEL /* 4 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_GC_LABEL /* 5 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ANNOTATION_LABEL /* 6 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_KILL /* 7 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_EXTRACT_SUBREG /* 8 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_SUBREG /* 9 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_IMPLICIT_DEF /* 10 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SUBREG_TO_REG /* 11 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_COPY_TO_REGCLASS /* 12 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_VALUE */ + Mips_DBG_VALUE /* 13 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_VALUE_LIST */ + Mips_DBG_VALUE_LIST /* 14 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_INSTR_REF */ + Mips_DBG_INSTR_REF /* 15 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_PHI */ + Mips_DBG_PHI /* 16 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_LABEL */ + Mips_DBG_LABEL /* 17 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_REG_SEQUENCE /* 18 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_COPY /* 19 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* BUNDLE */ + Mips_BUNDLE /* 20 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* LIFETIME_START */ + Mips_LIFETIME_START /* 21 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* LIFETIME_END */ + Mips_LIFETIME_END /* 22 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* PSEUDO_PROBE */ + Mips_PSEUDO_PROBE /* 23 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ARITH_FENCE /* 24 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_STACKMAP /* 25 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # FEntry call */ + Mips_FENTRY_CALL /* 26 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PATCHPOINT /* 27 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LOAD_STACK_GUARD /* 28 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PREALLOCATED_SETUP /* 29 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PREALLOCATED_ARG /* 30 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_STATEPOINT /* 31 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LOCAL_ESCAPE /* 32 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FAULTING_OP /* 33 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PATCHABLE_OP /* 34 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Function Enter. */ + Mips_PATCHABLE_FUNCTION_ENTER /* 35 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Function Patchable RET. */ + Mips_PATCHABLE_RET /* 36 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Function Exit. */ + Mips_PATCHABLE_FUNCTION_EXIT /* 37 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Tail Call Exit. */ + Mips_PATCHABLE_TAIL_CALL /* 38 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Custom Event Log. */ + Mips_PATCHABLE_EVENT_CALL /* 39 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Typed Event Log. */ + Mips_PATCHABLE_TYPED_EVENT_CALL /* 40 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ICALL_BRANCH_FUNNEL /* 41 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MEMBARRIER /* 42 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JUMP_TABLE_DEBUG_INFO /* 43 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ASSERT_SEXT /* 44 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ASSERT_ZEXT /* 45 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ASSERT_ALIGN /* 46 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ADD /* 47 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SUB /* 48 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_MUL /* 49 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SDIV /* 50 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UDIV /* 51 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SREM /* 52 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UREM /* 53 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SDIVREM /* 54 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UDIVREM /* 55 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_AND /* 56 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_OR /* 57 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_XOR /* 58 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_IMPLICIT_DEF /* 59 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_PHI /* 60 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FRAME_INDEX /* 61 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_GLOBAL_VALUE /* 62 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CONSTANT_POOL /* 63 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_EXTRACT /* 64 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UNMERGE_VALUES /* 65 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INSERT /* 66 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_MERGE_VALUES /* 67 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BUILD_VECTOR /* 68 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BUILD_VECTOR_TRUNC /* 69 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CONCAT_VECTORS /* 70 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_PTRTOINT /* 71 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTTOPTR /* 72 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BITCAST /* 73 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FREEZE /* 74 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CONSTANT_FOLD_BARRIER /* 75 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_FPTRUNC_ROUND /* 76 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_TRUNC /* 77 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_ROUND /* 78 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_LRINT /* 79 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_ROUNDEVEN /* 80 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_READCYCLECOUNTER /* 81 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_LOAD /* 82 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SEXTLOAD /* 83 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ZEXTLOAD /* 84 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INDEXED_LOAD /* 85 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INDEXED_SEXTLOAD /* 86 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INDEXED_ZEXTLOAD /* 87 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STORE /* 88 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INDEXED_STORE /* 89 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMIC_CMPXCHG_WITH_SUCCESS /* 90 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMIC_CMPXCHG /* 91 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_XCHG /* 92 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_ADD /* 93 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_SUB /* 94 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_AND /* 95 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_NAND /* 96 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_OR /* 97 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_XOR /* 98 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_MAX /* 99 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_MIN /* 100 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_UMAX /* 101 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_UMIN /* 102 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_FADD /* 103 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_FSUB /* 104 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_FMAX /* 105 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_FMIN /* 106 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_UINC_WRAP /* 107 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_UDEC_WRAP /* 108 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FENCE /* 109 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_PREFETCH /* 110 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BRCOND /* 111 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BRINDIRECT /* 112 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INVOKE_REGION_START /* 113 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC /* 114 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_W_SIDE_EFFECTS /* 115 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_CONVERGENT /* 116 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS /* 117 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ANYEXT /* 118 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_TRUNC /* 119 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CONSTANT /* 120 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FCONSTANT /* 121 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VASTART /* 122 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VAARG /* 123 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SEXT /* 124 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SEXT_INREG /* 125 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ZEXT /* 126 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SHL /* 127 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_LSHR /* 128 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ASHR /* 129 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FSHL /* 130 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FSHR /* 131 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ROTR /* 132 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ROTL /* 133 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ICMP /* 134 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FCMP /* 135 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SELECT /* 136 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UADDO /* 137 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UADDE /* 138 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_USUBO /* 139 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_USUBE /* 140 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SADDO /* 141 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SADDE /* 142 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SSUBO /* 143 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SSUBE /* 144 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UMULO /* 145 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SMULO /* 146 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UMULH /* 147 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SMULH /* 148 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UADDSAT /* 149 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SADDSAT /* 150 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_USUBSAT /* 151 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SSUBSAT /* 152 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_USHLSAT /* 153 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SSHLSAT /* 154 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SMULFIX /* 155 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UMULFIX /* 156 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SMULFIXSAT /* 157 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UMULFIXSAT /* 158 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SDIVFIX /* 159 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UDIVFIX /* 160 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SDIVFIXSAT /* 161 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UDIVFIXSAT /* 162 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FADD /* 163 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FSUB /* 164 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMUL /* 165 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMA /* 166 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMAD /* 167 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FDIV /* 168 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FREM /* 169 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FPOW /* 170 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FPOWI /* 171 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FEXP /* 172 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FEXP2 /* 173 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FEXP10 /* 174 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FLOG /* 175 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FLOG2 /* 176 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FLOG10 /* 177 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FLDEXP /* 178 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FFREXP /* 179 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FNEG /* 180 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FPEXT /* 181 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FPTRUNC /* 182 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FPTOSI /* 183 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FPTOUI /* 184 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SITOFP /* 185 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UITOFP /* 186 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FABS /* 187 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FCOPYSIGN /* 188 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_IS_FPCLASS /* 189 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FCANONICALIZE /* 190 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMINNUM /* 191 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMAXNUM /* 192 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMINNUM_IEEE /* 193 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMAXNUM_IEEE /* 194 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMINIMUM /* 195 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMAXIMUM /* 196 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_GET_FPENV /* 197 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SET_FPENV /* 198 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_RESET_FPENV /* 199 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_GET_FPMODE /* 200 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SET_FPMODE /* 201 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_RESET_FPMODE /* 202 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_PTR_ADD /* 203 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_PTRMASK /* 204 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SMIN /* 205 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SMAX /* 206 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UMIN /* 207 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UMAX /* 208 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ABS /* 209 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_LROUND /* 210 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_LLROUND /* 211 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BR /* 212 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BRJT /* 213 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INSERT_VECTOR_ELT /* 214 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_EXTRACT_VECTOR_ELT /* 215 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SHUFFLE_VECTOR /* 216 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CTTZ /* 217 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CTTZ_ZERO_UNDEF /* 218 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CTLZ /* 219 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CTLZ_ZERO_UNDEF /* 220 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CTPOP /* 221 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BSWAP /* 222 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BITREVERSE /* 223 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FCEIL /* 224 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FCOS /* 225 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FSIN /* 226 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FSQRT /* 227 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FFLOOR /* 228 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FRINT /* 229 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FNEARBYINT /* 230 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ADDRSPACE_CAST /* 231 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BLOCK_ADDR /* 232 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_JUMP_TABLE /* 233 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_DYN_STACKALLOC /* 234 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STACKSAVE /* 235 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STACKRESTORE /* 236 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FADD /* 237 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FSUB /* 238 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FMUL /* 239 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FDIV /* 240 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FREM /* 241 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FMA /* 242 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FSQRT /* 243 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FLDEXP /* 244 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_READ_REGISTER /* 245 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_WRITE_REGISTER /* 246 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_MEMCPY /* 247 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_MEMCPY_INLINE /* 248 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_MEMMOVE /* 249 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_MEMSET /* 250 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BZERO /* 251 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_SEQ_FADD /* 252 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_SEQ_FMUL /* 253 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_FADD /* 254 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_FMUL /* 255 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_FMAX /* 256 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_FMIN /* 257 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_FMAXIMUM /* 258 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_FMINIMUM /* 259 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_ADD /* 260 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_MUL /* 261 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_AND /* 262 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_OR /* 263 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_XOR /* 264 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_SMAX /* 265 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_SMIN /* 266 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_UMAX /* 267 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_UMIN /* 268 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SBFX /* 269 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UBFX /* 270 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* abs $rd, $rs */ + Mips_ABSMacro /* 271 */, MIPS_INS_ABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_ADJCALLSTACKDOWN /* 272 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ADJCALLSTACKDOWN_NM /* 273 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ADJCALLSTACKUP /* 274 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ADJCALLSTACKUP_NM /* 275 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* align $rd, $rs, $rt, $bp */ + Mips_ALIGN_NM /* 276 */, MIPS_INS_ALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_AND_V_D_PSEUDO /* 277 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_AND_V_H_PSEUDO /* 278 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_AND_V_W_PSEUDO /* 279 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I16 /* 280 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I16_POSTRA /* 281 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I32 /* 282 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I32_POSTRA /* 283 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I64 /* 284 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I64_POSTRA /* 285 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I8 /* 286 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I8_POSTRA /* 287 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I16 /* 288 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I16_POSTRA /* 289 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I32 /* 290 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I32_POSTRA /* 291 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I64 /* 292 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I64_POSTRA /* 293 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I8 /* 294 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I8_POSTRA /* 295 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I16 /* 296 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I16_POSTRA /* 297 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I32 /* 298 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I32_POSTRA /* 299 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I64 /* 300 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I64_POSTRA /* 301 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I8 /* 302 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I8_POSTRA /* 303 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I16 /* 304 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I16_POSTRA /* 305 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I32 /* 306 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I32_POSTRA /* 307 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I64 /* 308 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I64_POSTRA /* 309 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I8 /* 310 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I8_POSTRA /* 311 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I16 /* 312 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I16_POSTRA /* 313 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I32 /* 314 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I32_POSTRA /* 315 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I64 /* 316 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I64_POSTRA /* 317 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I8 /* 318 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I8_POSTRA /* 319 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I16 /* 320 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I16_POSTRA /* 321 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I32 /* 322 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I32_POSTRA /* 323 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I64 /* 324 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I64_POSTRA /* 325 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I8 /* 326 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I8_POSTRA /* 327 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I16 /* 328 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I16_POSTRA /* 329 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I32 /* 330 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I32_POSTRA /* 331 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I64 /* 332 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I64_POSTRA /* 333 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I8 /* 334 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I8_POSTRA /* 335 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I16 /* 336 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I16_POSTRA /* 337 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I32 /* 338 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I32_POSTRA /* 339 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I64 /* 340 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I64_POSTRA /* 341 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I8 /* 342 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I8_POSTRA /* 343 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I16 /* 344 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I16_POSTRA /* 345 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I32 /* 346 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I32_POSTRA /* 347 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I64 /* 348 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I64_POSTRA /* 349 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I8 /* 350 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I8_POSTRA /* 351 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I16 /* 352 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I16_POSTRA /* 353 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I32 /* 354 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I32_POSTRA /* 355 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I64 /* 356 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I64_POSTRA /* 357 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I8 /* 358 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I8_POSTRA /* 359 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I16 /* 360 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I16_POSTRA /* 361 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I32 /* 362 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I32_POSTRA /* 363 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I64 /* 364 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I64_POSTRA /* 365 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I8 /* 366 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I8_POSTRA /* 367 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I16 /* 368 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I16_POSTRA /* 369 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I32 /* 370 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I32_POSTRA /* 371 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I64 /* 372 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I64_POSTRA /* 373 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I8 /* 374 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I8_POSTRA /* 375 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_B /* 376 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BAL_BR /* 377 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BAL_BR_MM /* 378 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* beql $rs, $imm, $offset */ + Mips_BEQLImmMacro /* 379 */, MIPS_INS_BEQL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bge $rs, $rt, $offset */ + Mips_BGE /* 380 */, MIPS_INS_BGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bge $rs, $imm, $offset */ + Mips_BGEImmMacro /* 381 */, MIPS_INS_BGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgel $rs, $rt, $offset */ + Mips_BGEL /* 382 */, MIPS_INS_BGEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgel $rs, $imm, $offset */ + Mips_BGELImmMacro /* 383 */, MIPS_INS_BGEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgeu $rs, $rt, $offset */ + Mips_BGEU /* 384 */, MIPS_INS_BGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgeu $rs, $imm, $offset */ + Mips_BGEUImmMacro /* 385 */, MIPS_INS_BGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgeul $rs, $rt, $offset */ + Mips_BGEUL /* 386 */, MIPS_INS_BGEUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgeul $rs, $imm, $offset */ + Mips_BGEULImmMacro /* 387 */, MIPS_INS_BGEUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgt $rs, $rt, $offset */ + Mips_BGT /* 388 */, MIPS_INS_BGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgt $rs, $imm, $offset */ + Mips_BGTImmMacro /* 389 */, MIPS_INS_BGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgtl $rs, $rt, $offset */ + Mips_BGTL /* 390 */, MIPS_INS_BGTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgtl $rs, $imm, $offset */ + Mips_BGTLImmMacro /* 391 */, MIPS_INS_BGTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgtu $rs, $rt, $offset */ + Mips_BGTU /* 392 */, MIPS_INS_BGTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgtu $rs, $imm, $offset */ + Mips_BGTUImmMacro /* 393 */, MIPS_INS_BGTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgtul $rs, $rt, $offset */ + Mips_BGTUL /* 394 */, MIPS_INS_BGTUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgtul $rs, $imm, $offset */ + Mips_BGTULImmMacro /* 395 */, MIPS_INS_BGTUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ble $rs, $rt, $offset */ + Mips_BLE /* 396 */, MIPS_INS_BLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ble $rs, $imm, $offset */ + Mips_BLEImmMacro /* 397 */, MIPS_INS_BLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* blel $rs, $rt, $offset */ + Mips_BLEL /* 398 */, MIPS_INS_BLEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* blel $rs, $imm, $offset */ + Mips_BLELImmMacro /* 399 */, MIPS_INS_BLEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bleu $rs, $rt, $offset */ + Mips_BLEU /* 400 */, MIPS_INS_BLEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bleu $rs, $imm, $offset */ + Mips_BLEUImmMacro /* 401 */, MIPS_INS_BLEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bleul $rs, $rt, $offset */ + Mips_BLEUL /* 402 */, MIPS_INS_BLEUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bleul $rs, $imm, $offset */ + Mips_BLEULImmMacro /* 403 */, MIPS_INS_BLEUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* blt $rs, $rt, $offset */ + Mips_BLT /* 404 */, MIPS_INS_BLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* blt $rs, $imm, $offset */ + Mips_BLTImmMacro /* 405 */, MIPS_INS_BLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltl $rs, $rt, $offset */ + Mips_BLTL /* 406 */, MIPS_INS_BLTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltl $rs, $imm, $offset */ + Mips_BLTLImmMacro /* 407 */, MIPS_INS_BLTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltu $rs, $rt, $offset */ + Mips_BLTU /* 408 */, MIPS_INS_BLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltu $rs, $imm, $offset */ + Mips_BLTUImmMacro /* 409 */, MIPS_INS_BLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltul $rs, $rt, $offset */ + Mips_BLTUL /* 410 */, MIPS_INS_BLTUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltul $rs, $imm, $offset */ + Mips_BLTULImmMacro /* 411 */, MIPS_INS_BLTUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bnel $rs, $imm, $offset */ + Mips_BNELImmMacro /* 412 */, MIPS_INS_BNEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_BPOSGE32_PSEUDO /* 413 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BSEL_D_PSEUDO /* 414 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BSEL_FD_PSEUDO /* 415 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BSEL_FW_PSEUDO /* 416 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BSEL_H_PSEUDO /* 417 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BSEL_W_PSEUDO /* 418 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_B_MM /* 419 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* b $offset */ + Mips_B_MMR6_Pseudo /* 420 */, MIPS_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* b $offset */ + Mips_B_MM_Pseudo /* 421 */, MIPS_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* beq $rt, $imm64, $offset */ + Mips_BeqImm /* 422 */, MIPS_INS_BEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bne $rt, $imm64, $offset */ + Mips_BneImm /* 423 */, MIPS_INS_BNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp $rx, $ry + bteqz $imm */ + Mips_BteqzT8CmpX16 /* 424 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmpi $rx, $imm + bteqz $targ */ + Mips_BteqzT8CmpiX16 /* 425 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slt $rx, $ry + bteqz $imm */ + Mips_BteqzT8SltX16 /* 426 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slti $rx, $imm + bteqz $targ */ + Mips_BteqzT8SltiX16 /* 427 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rx, $imm + bteqz $targ */ + Mips_BteqzT8SltiuX16 /* 428 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rx, $ry + bteqz $imm */ + Mips_BteqzT8SltuX16 /* 429 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmp $rx, $ry + btnez $imm */ + Mips_BtnezT8CmpX16 /* 430 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmpi $rx, $imm + btnez $targ */ + Mips_BtnezT8CmpiX16 /* 431 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slt $rx, $ry + btnez $imm */ + Mips_BtnezT8SltX16 /* 432 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slti $rx, $imm + btnez $targ */ + Mips_BtnezT8SltiX16 /* 433 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rx, $imm + btnez $targ */ + Mips_BtnezT8SltiuX16 /* 434 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rx, $ry + btnez $imm */ + Mips_BtnezT8SltuX16 /* 435 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BuildPairF64 /* 436 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BuildPairF64_64 /* 437 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cftc1 $rt, $ft */ + Mips_CFTC1 /* 438 */, MIPS_INS_CFTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* foo */ + Mips_CONSTPOOL_ENTRY /* 439 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_COPY_FD_PSEUDO /* 440 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_COPY_FW_PSEUDO /* 441 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cttc1 $rt, $ft */ + Mips_CTTC1 /* 442 */, MIPS_INS_CTTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* .word $imm */ + Mips_Constant32 /* 443 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* dmul $rs, $rt, $imm */ + Mips_DMULImmMacro /* 444 */, MIPS_INS_DMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmul $rs, $rt, $rd */ + Mips_DMULMacro /* 445 */, MIPS_INS_DMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmulo $rs, $rt, $rd */ + Mips_DMULOMacro /* 446 */, MIPS_INS_DMULO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmulou $rs, $rt, $rd */ + Mips_DMULOUMacro /* 447 */, MIPS_INS_DMULOU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drol $rs, $rt, $rd */ + Mips_DROL /* 448 */, MIPS_INS_DROL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drol $rs, $rt, $imm */ + Mips_DROLImm /* 449 */, MIPS_INS_DROL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dror $rs, $rt, $rd */ + Mips_DROR /* 450 */, MIPS_INS_DROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dror $rs, $rt, $imm */ + Mips_DRORImm /* 451 */, MIPS_INS_DROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddiv $rd, $rs, $imm */ + Mips_DSDivIMacro /* 452 */, MIPS_INS_DDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddiv $rd, $rs, $rt */ + Mips_DSDivMacro /* 453 */, MIPS_INS_DDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drem $rd, $rs, $imm */ + Mips_DSRemIMacro /* 454 */, MIPS_INS_DREM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drem $rd, $rs, $rt */ + Mips_DSRemMacro /* 455 */, MIPS_INS_DREM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddivu $rd, $rs, $imm */ + Mips_DUDivIMacro /* 456 */, MIPS_INS_DDIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddivu $rd, $rs, $rt */ + Mips_DUDivMacro /* 457 */, MIPS_INS_DDIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dremu $rd, $rs, $imm */ + Mips_DURemIMacro /* 458 */, MIPS_INS_DREMU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dremu $rd, $rs, $rt */ + Mips_DURemMacro /* 459 */, MIPS_INS_DREMU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_ERet /* 460 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ExtractElementF64 /* 461 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ExtractElementF64_64 /* 462 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FABS_D /* 463 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FABS_W /* 464 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FEXP2_D_1_PSEUDO /* 465 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FEXP2_W_1_PSEUDO /* 466 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FILL_FD_PSEUDO /* 467 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FILL_FW_PSEUDO /* 468 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* li $rh, $immHi + addiu $rl, $$pc, $immLo + */ + Mips_GotPrologue16 /* 469 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_B_VIDX64_PSEUDO /* 470 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_B_VIDX_PSEUDO /* 471 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_D_VIDX64_PSEUDO /* 472 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_D_VIDX_PSEUDO /* 473 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_FD_PSEUDO /* 474 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_FD_VIDX64_PSEUDO /* 475 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_FD_VIDX_PSEUDO /* 476 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_FW_PSEUDO /* 477 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_FW_VIDX64_PSEUDO /* 478 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_FW_VIDX_PSEUDO /* 479 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_H_VIDX64_PSEUDO /* 480 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_H_VIDX_PSEUDO /* 481 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_W_VIDX64_PSEUDO /* 482 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_W_VIDX_PSEUDO /* 483 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JALR64Pseudo /* 484 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JALRCPseudo /* 485 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JALRHB64Pseudo /* 486 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JALRHBPseudo /* 487 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JALRPseudo /* 488 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JAL_MMR6 /* 489 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* jal $rs */ + Mips_JalOneReg /* 490 */, MIPS_INS_JAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jal $rd, $rs */ + Mips_JalTwoReg /* 491 */, MIPS_INS_JAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ld $rt, $addr */ + Mips_LDMacro /* 492 */, MIPS_INS_LD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_LDR_D /* 493 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LDR_W /* 494 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LD_F16 /* 495 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $rt, $addr */ + Mips_LOAD_ACC128 /* 496 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $rt, $addr */ + Mips_LOAD_ACC64 /* 497 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $rt, $addr */ + Mips_LOAD_ACC64DSP /* 498 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* load_ccond_dsp $rt, $addr */ + Mips_LOAD_CCOND_DSP /* 499 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_ADDiu /* 500 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_ADDiu2Op /* 501 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_DADDiu /* 502 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_DADDiu2Op /* 503 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_LUi /* 504 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_LUi2Op /* 505 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_LUi2Op_64 /* 506 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lwm $rt, $addr */ + Mips_LWM_MM /* 507 */, MIPS_INS_LWM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* la $rt, $imm32 */ + Mips_LoadAddrImm32 /* 508 */, MIPS_INS_LA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dla $rt, $imm64 */ + Mips_LoadAddrImm64 /* 509 */, MIPS_INS_DLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* la $rt, $addr */ + Mips_LoadAddrReg32 /* 510 */, MIPS_INS_LA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dla $rt, $addr */ + Mips_LoadAddrReg64 /* 511 */, MIPS_INS_DLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li $rt, $imm32 */ + Mips_LoadImm32 /* 512 */, MIPS_INS_LI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dli $rt, $imm64 */ + Mips_LoadImm64 /* 513 */, MIPS_INS_DLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li.d $rd, $fpimm */ + Mips_LoadImmDoubleFGR /* 514 */, MIPS_INS_LI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li.d $rd, $fpimm */ + Mips_LoadImmDoubleFGR_32 /* 515 */, MIPS_INS_LI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li.d $rd, $fpimm */ + Mips_LoadImmDoubleGPR /* 516 */, MIPS_INS_LI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li.s $rd, $fpimm */ + Mips_LoadImmSingleFGR /* 517 */, MIPS_INS_LI_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li.s $rd, $fpimm */ + Mips_LoadImmSingleGPR /* 518 */, MIPS_INS_LI_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_LoadJumpTableOffset /* 519 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lw $rx, 1f + b 2f + .align 2 +1: .word $imm +2: */ + Mips_LwConstant32 /* 520 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mftacx $rt, $ac */ + Mips_MFTACX /* 521 */, MIPS_INS_MFTACX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftacx $rt, $ac */ + Mips_MFTACX_NM /* 522 */, MIPS_INS_MFTACX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftc0 $rd, $rt, $sel */ + Mips_MFTC0 /* 523 */, MIPS_INS_MFTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftc0 $rd, $rt, $sel */ + Mips_MFTC0_NM /* 524 */, MIPS_INS_MFTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftc1 $rt, $ft */ + Mips_MFTC1 /* 525 */, MIPS_INS_MFTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftdsp $rt */ + Mips_MFTDSP /* 526 */, MIPS_INS_MFTDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftdsp $rt */ + Mips_MFTDSP_NM /* 527 */, MIPS_INS_MFTDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftgpr $rd, $rt */ + Mips_MFTGPR /* 528 */, MIPS_INS_MFTGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftgpr $rd, $rt */ + Mips_MFTGPR_NM /* 529 */, MIPS_INS_MFTGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfthc1 $rt, $ft */ + Mips_MFTHC1 /* 530 */, MIPS_INS_MFTHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfthi $rt, $ac */ + Mips_MFTHI /* 531 */, MIPS_INS_MFTHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfthi $rt, $ac */ + Mips_MFTHI_NM /* 532 */, MIPS_INS_MFTHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftlo $rt, $ac */ + Mips_MFTLO /* 533 */, MIPS_INS_MFTLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftlo $rt, $ac */ + Mips_MFTLO_NM /* 534 */, MIPS_INS_MFTLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_MIPSeh_return32 /* 535 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MIPSeh_return64 /* 536 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MSA_FP_EXTEND_D_PSEUDO /* 537 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MSA_FP_EXTEND_W_PSEUDO /* 538 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MSA_FP_ROUND_D_PSEUDO /* 539 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MSA_FP_ROUND_W_PSEUDO /* 540 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mttacx $rt, $ac */ + Mips_MTTACX /* 541 */, MIPS_INS_MTTACX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttacx $rt, $ac */ + Mips_MTTACX_NM /* 542 */, MIPS_INS_MTTACX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttc0 $rt, $rd, $sel */ + Mips_MTTC0 /* 543 */, MIPS_INS_MTTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttc0 $rt, $rd, $sel */ + Mips_MTTC0_NM /* 544 */, MIPS_INS_MTTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttc1 $rt, $ft */ + Mips_MTTC1 /* 545 */, MIPS_INS_MTTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttdsp $rt */ + Mips_MTTDSP /* 546 */, MIPS_INS_MTTDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttdsp $rt */ + Mips_MTTDSP_NM /* 547 */, MIPS_INS_MTTDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttgpr $rd, $rt */ + Mips_MTTGPR /* 548 */, MIPS_INS_MTTGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttgpr $rd, $rt */ + Mips_MTTGPR_NM /* 549 */, MIPS_INS_MTTGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtthc1 $rt, $ft */ + Mips_MTTHC1 /* 550 */, MIPS_INS_MTTHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtthi $rt, $ac */ + Mips_MTTHI /* 551 */, MIPS_INS_MTTHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtthi $rt, $ac */ + Mips_MTTHI_NM /* 552 */, MIPS_INS_MTTHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttlo $rt, $ac */ + Mips_MTTLO /* 553 */, MIPS_INS_MTTLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttlo $rt, $ac */ + Mips_MTTLO_NM /* 554 */, MIPS_INS_MTTLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $rd, $rs, $imm */ + Mips_MULImmMacro /* 555 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulo $rd, $rs, $rt */ + Mips_MULOMacro /* 556 */, MIPS_INS_MULO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulou $rd, $rs, $rt */ + Mips_MULOUMacro /* 557 */, MIPS_INS_MULOU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_MUSTTAILCALLREG_NM /* 558 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MUSTTAILCALL_NM /* 559 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mult $rx, $ry */ + Mips_MultRxRy16 /* 560 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mult $rx, $ry + mflo $rz */ + Mips_MultRxRyRz16 /* 561 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* multu $rx, $ry */ + Mips_MultuRxRy16 /* 562 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* multu $rx, $ry + mflo $rz */ + Mips_MultuRxRyRz16 /* 563 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_NOP /* 564 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* nor $rs, $rt, $imm */ + Mips_NORImm /* 565 */, MIPS_INS_NOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor $rs, $rt, $imm */ + Mips_NORImm64 /* 566 */, MIPS_INS_NOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_NOR_V_D_PSEUDO /* 567 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_NOR_V_H_PSEUDO /* 568 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_NOR_V_W_PSEUDO /* 569 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_OR_V_D_PSEUDO /* 570 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_OR_V_H_PSEUDO /* 571 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_OR_V_W_PSEUDO /* 572 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* addiu $rt, $rs, $imm */ + Mips_PseudoADDIU_NM /* 573 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi $rt, $rs, $mask */ + Mips_PseudoANDI_NM /* 574 */, MIPS_INS_ANDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_PseudoCMPU_EQ_QB /* 575 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoCMPU_LE_QB /* 576 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoCMPU_LT_QB /* 577 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoCMP_EQ_PH /* 578 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoCMP_LE_PH /* 579 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoCMP_LT_PH /* 580 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $fd, $fs */ + Mips_PseudoCVT_D32_W /* 581 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $fd, $fs */ + Mips_PseudoCVT_D64_L /* 582 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $fd, $fs */ + Mips_PseudoCVT_D64_W /* 583 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $fd, $fs */ + Mips_PseudoCVT_S_L /* 584 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $fd, $fs */ + Mips_PseudoCVT_S_W /* 585 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoDMULT /* 586 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoDMULTu /* 587 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoDSDIV /* 588 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoDUDIV /* 589 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoD_SELECT_I /* 590 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoD_SELECT_I64 /* 591 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranch /* 592 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranch64 /* 593 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranch64R6 /* 594 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranchNM /* 595 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranchR6 /* 596 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranch_MM /* 597 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranch_MMR6 /* 598 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectHazardBranch /* 599 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectHazardBranch64 /* 600 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndrectHazardBranch64R6 /* 601 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndrectHazardBranchR6 /* 602 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* la $rt, $addr */ + Mips_PseudoLA_NM /* 603 */, MIPS_INS_LA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li $rt, $imm */ + Mips_PseudoLI_NM /* 604 */, MIPS_INS_LI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_PseudoMADD /* 605 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMADDU /* 606 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMADDU_MM /* 607 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMADD_MM /* 608 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMFHI /* 609 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMFHI64 /* 610 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMFHI_MM /* 611 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMFLO /* 612 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMFLO64 /* 613 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMFLO_MM /* 614 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMSUB /* 615 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMSUBU /* 616 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMSUBU_MM /* 617 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMSUB_MM /* 618 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMTLOHI /* 619 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMTLOHI64 /* 620 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMTLOHI_DSP /* 621 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMTLOHI_MM /* 622 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMULT /* 623 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMULT_MM /* 624 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMULTu /* 625 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMULTu_MM /* 626 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoPICK_PH /* 627 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoPICK_QB /* 628 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoReturn /* 629 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoReturn64 /* 630 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoReturnNM /* 631 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSDIV /* 632 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_F_D32 /* 633 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_F_D64 /* 634 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_F_I /* 635 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_F_I64 /* 636 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_F_S /* 637 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_T_D32 /* 638 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_T_D64 /* 639 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_T_I /* 640 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_T_I64 /* 641 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_T_S /* 642 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECT_D32 /* 643 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECT_D64 /* 644 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECT_I /* 645 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECT_I64 /* 646 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECT_S /* 647 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* subu $rt, $rs, $imm */ + Mips_PseudoSUBU_NM /* 648 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.d $fd, $fs, $rs */ + Mips_PseudoTRUNC_W_D /* 649 */, MIPS_INS_TRUNC_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.d $fd, $fs, $rs */ + Mips_PseudoTRUNC_W_D32 /* 650 */, MIPS_INS_TRUNC_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.s $fd, $fs, $rs */ + Mips_PseudoTRUNC_W_S /* 651 */, MIPS_INS_TRUNC_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_PseudoUDIV /* 652 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* rol $rs, $rt, $rd */ + Mips_ROL /* 653 */, MIPS_INS_ROL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rol $rs, $rt, $imm */ + Mips_ROLImm /* 654 */, MIPS_INS_ROL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ror $rs, $rt, $rd */ + Mips_ROR /* 655 */, MIPS_INS_ROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ror $rs, $rt, $imm */ + Mips_RORImm /* 656 */, MIPS_INS_ROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_RetRA /* 657 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_RetRA16 /* 658 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* s.d $fd, $addr */ + Mips_SDC1_M1 /* 659 */, MIPS_INS_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_SDIV_MM_Pseudo /* 660 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sd $rt, $addr */ + Mips_SDMacro /* 661 */, MIPS_INS_SD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $rd, $rs, $imm */ + Mips_SDivIMacro /* 662 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $rd, $rs, $rt */ + Mips_SDivMacro /* 663 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seq $rd, $rs, $imm */ + Mips_SEQIMacro /* 664 */, MIPS_INS_SEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seq $rd, $rs, $rt */ + Mips_SEQMacro /* 665 */, MIPS_INS_SEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sge $rd, $rs, $rt */ + Mips_SGE /* 666 */, MIPS_INS_SGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sge $rd, $rs, $imm */ + Mips_SGEImm /* 667 */, MIPS_INS_SGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sge $rd, $rs, $imm */ + Mips_SGEImm64 /* 668 */, MIPS_INS_SGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgeu $rd, $rs, $rt */ + Mips_SGEU /* 669 */, MIPS_INS_SGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgeu $rd, $rs, $imm */ + Mips_SGEUImm /* 670 */, MIPS_INS_SGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgeu $rd, $rs, $imm */ + Mips_SGEUImm64 /* 671 */, MIPS_INS_SGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgt $rd, $rs, $imm */ + Mips_SGTImm /* 672 */, MIPS_INS_SGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgt $rd, $rs, $imm */ + Mips_SGTImm64 /* 673 */, MIPS_INS_SGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgtu $rd, $rs, $imm */ + Mips_SGTUImm /* 674 */, MIPS_INS_SGTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgtu $rd, $rs, $imm */ + Mips_SGTUImm64 /* 675 */, MIPS_INS_SGTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sle $rd, $rs, $rt */ + Mips_SLE /* 676 */, MIPS_INS_SLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sle $rd, $rs, $imm */ + Mips_SLEImm /* 677 */, MIPS_INS_SLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sle $rd, $rs, $imm */ + Mips_SLEImm64 /* 678 */, MIPS_INS_SLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sleu $rd, $rs, $rt */ + Mips_SLEU /* 679 */, MIPS_INS_SLEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sleu $rd, $rs, $imm */ + Mips_SLEUImm /* 680 */, MIPS_INS_SLEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sleu $rd, $rs, $imm */ + Mips_SLEUImm64 /* 681 */, MIPS_INS_SLEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slt $rs, $rt, $imm */ + Mips_SLTImm64 /* 682 */, MIPS_INS_SLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltu $rs, $rt, $imm */ + Mips_SLTUImm64 /* 683 */, MIPS_INS_SLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sne $rd, $rs, $imm */ + Mips_SNEIMacro /* 684 */, MIPS_INS_SNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sne $rd, $rs, $rt */ + Mips_SNEMacro /* 685 */, MIPS_INS_SNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_SNZ_B_PSEUDO /* 686 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SNZ_D_PSEUDO /* 687 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SNZ_H_PSEUDO /* 688 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SNZ_V_PSEUDO /* 689 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SNZ_W_PSEUDO /* 690 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* rem $rd, $rs, $imm */ + Mips_SRemIMacro /* 691 */, MIPS_INS_REM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rem $rd, $rs, $rt */ + Mips_SRemMacro /* 692 */, MIPS_INS_REM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* $rt, $addr */ + Mips_STORE_ACC128 /* 693 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $rt, $addr */ + Mips_STORE_ACC64 /* 694 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $rt, $addr */ + Mips_STORE_ACC64DSP /* 695 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* store_ccond_dsp $rt, $addr */ + Mips_STORE_CCOND_DSP /* 696 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_STR_D /* 697 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_STR_W /* 698 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ST_F16 /* 699 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* swm $rt, $addr */ + Mips_SWM_MM /* 700 */, MIPS_INS_SWM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_SZ_B_PSEUDO /* 701 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SZ_D_PSEUDO /* 702 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SZ_H_PSEUDO /* 703 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SZ_V_PSEUDO /* 704 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SZ_W_PSEUDO /* 705 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* saa $rt, $addr */ + Mips_SaaAddr /* 706 */, MIPS_INS_SAA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* saad $rt, $addr */ + Mips_SaadAddr /* 707 */, MIPS_INS_SAAD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* beqz $rt, .+4 + + move $rd, $rs */ + Mips_SelBeqZ /* 708 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bnez $rt, .+4 + + move $rd, $rs */ + Mips_SelBneZ /* 709 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmp $rl, $rr + bteqz .+4 + move $rd, $rs */ + Mips_SelTBteqZCmp /* 710 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmpi $rl, $imm + bteqz .+4 + move $rd, $rs */ + Mips_SelTBteqZCmpi /* 711 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slt $rl, $rr + bteqz .+4 + move $rd, $rs */ + Mips_SelTBteqZSlt /* 712 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slti $rl, $imm + bteqz .+4 + move $rd, $rs */ + Mips_SelTBteqZSlti /* 713 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rl, $imm + bteqz .+4 + move $rd, $rs */ + Mips_SelTBteqZSltiu /* 714 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rl, $rr + bteqz .+4 + move $rd, $rs */ + Mips_SelTBteqZSltu /* 715 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmp $rl, $rr + btnez .+4 + move $rd, $rs */ + Mips_SelTBtneZCmp /* 716 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmpi $rl, $imm + btnez .+4 + move $rd, $rs */ + Mips_SelTBtneZCmpi /* 717 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slt $rl, $rr + btnez .+4 + move $rd, $rs */ + Mips_SelTBtneZSlt /* 718 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slti $rl, $imm + btnez .+4 + move $rd, $rs */ + Mips_SelTBtneZSlti /* 719 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rl, $imm + btnez .+4 + move $rd, $rs */ + Mips_SelTBtneZSltiu /* 720 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rl, $rr + btnez .+4 + move $rd, $rs */ + Mips_SelTBtneZSltu /* 721 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slt $rx, $ry + move $cc, $$t8 */ + Mips_SltCCRxRy16 /* 722 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slti $rx, $imm + move $cc, $$t8 */ + Mips_SltiCCRxImmX16 /* 723 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rx, $imm + move $cc, $$t8 */ + Mips_SltiuCCRxImmX16 /* 724 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rx, $ry + move $cc, $$t8 */ + Mips_SltuCCRxRy16 /* 725 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rx, $ry + move $rz, $$t8 */ + Mips_SltuRxRyRz16 /* 726 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALL /* 727 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALL64R6REG /* 728 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLHB64R6REG /* 729 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLHBR6REG /* 730 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLR6REG /* 731 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREG /* 732 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREG64 /* 733 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREGHB /* 734 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREGHB64 /* 735 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREG_MM /* 736 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREG_MMR6 /* 737 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREG_NM /* 738 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALL_MM /* 739 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALL_MMR6 /* 740 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALL_NM /* 741 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TRAP /* 742 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TRAP_MM /* 743 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_UDIV_MM_Pseudo /* 744 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* divu $rd, $rs, $imm */ + Mips_UDivIMacro /* 745 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $rd, $rs, $rt */ + Mips_UDivMacro /* 746 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* remu $rd, $rs, $imm */ + Mips_URemIMacro /* 747 */, MIPS_INS_REMU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* remu $rd, $rs, $rt */ + Mips_URemMacro /* 748 */, MIPS_INS_REMU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ulh $rt, $addr */ + Mips_Ulh /* 749 */, MIPS_INS_ULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ulhu $rt, $addr */ + Mips_Ulhu /* 750 */, MIPS_INS_ULHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ulw $rt, $addr */ + Mips_Ulw /* 751 */, MIPS_INS_ULW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ush $rt, $addr */ + Mips_Ush /* 752 */, MIPS_INS_USH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* usw $rt, $addr */ + Mips_Usw /* 753 */, MIPS_INS_USW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_XOR_V_D_PSEUDO /* 754 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_XOR_V_H_PSEUDO /* 755 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_XOR_V_W_PSEUDO /* 756 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* absq_s.ph $rd, $rt */ + Mips_ABSQ_S_PH /* 757 */, MIPS_INS_ABSQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* absq_s.ph $rt, $rs */ + Mips_ABSQ_S_PH_MM /* 758 */, MIPS_INS_ABSQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* absq_s.qb $rd, $rt */ + Mips_ABSQ_S_QB /* 759 */, MIPS_INS_ABSQ_S_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* absq_s.qb $rt, $rs */ + Mips_ABSQ_S_QB_MMR2 /* 760 */, MIPS_INS_ABSQ_S_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* absq_s.w $rd, $rt */ + Mips_ABSQ_S_W /* 761 */, MIPS_INS_ABSQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* absq_s.w $rt, $rs */ + Mips_ABSQ_S_W_MM /* 762 */, MIPS_INS_ABSQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add $rd, $rs, $rt */ + Mips_ADD /* 763 */, MIPS_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[48] $rt, $rs, $imm */ + Mips_ADDIU48_NM /* 764 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[gp48] $rt, $rs, $addr */ + Mips_ADDIUGP48_NM /* 765 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[gp.b] $rt, $rs, $offset */ + Mips_ADDIUGPB_NM /* 766 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[gp.w] $rt, $rs, $offset */ + Mips_ADDIUGPW_NM /* 767 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[neg] $rt, $rs, $imm */ + Mips_ADDIUNEG_NM /* 768 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiupc $rs, $imm */ + Mips_ADDIUPC /* 769 */, MIPS_INS_ADDIUPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiupc $rs, $imm */ + Mips_ADDIUPC_MM /* 770 */, MIPS_INS_ADDIUPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiupc $rt, $imm */ + Mips_ADDIUPC_MMR6 /* 771 */, MIPS_INS_ADDIUPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiur1sp $rd, $imm */ + Mips_ADDIUR1SP_MM /* 772 */, MIPS_INS_ADDIUR1SP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[r1.sp] $rt, $rs, $imm */ + Mips_ADDIUR1SP_NM /* 773 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiur2 $rd, $rs, $imm */ + Mips_ADDIUR2_MM /* 774 */, MIPS_INS_ADDIUR2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[r2] $rt, $rs, $imm */ + Mips_ADDIUR2_NM /* 775 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[rs5] $rt, $rs, $imm */ + Mips_ADDIURS5_NM /* 776 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addius5 $rd, $imm */ + Mips_ADDIUS5_MM /* 777 */, MIPS_INS_ADDIUS5, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiusp $imm */ + Mips_ADDIUSP_MM /* 778 */, MIPS_INS_ADDIUSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rt, $rs, $imm16 */ + Mips_ADDIU_MMR6 /* 779 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[32] $rt, $rs, $imm */ + Mips_ADDIU_NM /* 780 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh.ph $rd, $rs, $rt */ + Mips_ADDQH_PH /* 781 */, MIPS_INS_ADDQH_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh.ph $rd, $rs, $rt */ + Mips_ADDQH_PH_MMR2 /* 782 */, MIPS_INS_ADDQH_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh_r.ph $rd, $rs, $rt */ + Mips_ADDQH_R_PH /* 783 */, MIPS_INS_ADDQH_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh_r.ph $rd, $rs, $rt */ + Mips_ADDQH_R_PH_MMR2 /* 784 */, MIPS_INS_ADDQH_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh_r.w $rd, $rs, $rt */ + Mips_ADDQH_R_W /* 785 */, MIPS_INS_ADDQH_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh_r.w $rd, $rs, $rt */ + Mips_ADDQH_R_W_MMR2 /* 786 */, MIPS_INS_ADDQH_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh.w $rd, $rs, $rt */ + Mips_ADDQH_W /* 787 */, MIPS_INS_ADDQH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh.w $rd, $rs, $rt */ + Mips_ADDQH_W_MMR2 /* 788 */, MIPS_INS_ADDQH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addq.ph $rd, $rs, $rt */ + Mips_ADDQ_PH /* 789 */, MIPS_INS_ADDQ_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addq.ph $rd, $rs, $rt */ + Mips_ADDQ_PH_MM /* 790 */, MIPS_INS_ADDQ_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addq_s.ph $rd, $rs, $rt */ + Mips_ADDQ_S_PH /* 791 */, MIPS_INS_ADDQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addq_s.ph $rd, $rs, $rt */ + Mips_ADDQ_S_PH_MM /* 792 */, MIPS_INS_ADDQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addq_s.w $rd, $rs, $rt */ + Mips_ADDQ_S_W /* 793 */, MIPS_INS_ADDQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addq_s.w $rd, $rs, $rt */ + Mips_ADDQ_S_W_MM /* 794 */, MIPS_INS_ADDQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addr.ps $fd, $fs, $ft */ + Mips_ADDR_PS64 /* 795 */, MIPS_INS_ADDR_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMIPS3D, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addsc $rd, $rs, $rt */ + Mips_ADDSC /* 796 */, MIPS_INS_ADDSC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addsc $rd, $rs, $rt */ + Mips_ADDSC_MM /* 797 */, MIPS_INS_ADDSC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_a.b $wd, $ws, $wt */ + Mips_ADDS_A_B /* 798 */, MIPS_INS_ADDS_A_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_a.d $wd, $ws, $wt */ + Mips_ADDS_A_D /* 799 */, MIPS_INS_ADDS_A_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_a.h $wd, $ws, $wt */ + Mips_ADDS_A_H /* 800 */, MIPS_INS_ADDS_A_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_a.w $wd, $ws, $wt */ + Mips_ADDS_A_W /* 801 */, MIPS_INS_ADDS_A_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_s.b $wd, $ws, $wt */ + Mips_ADDS_S_B /* 802 */, MIPS_INS_ADDS_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_s.d $wd, $ws, $wt */ + Mips_ADDS_S_D /* 803 */, MIPS_INS_ADDS_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_s.h $wd, $ws, $wt */ + Mips_ADDS_S_H /* 804 */, MIPS_INS_ADDS_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_s.w $wd, $ws, $wt */ + Mips_ADDS_S_W /* 805 */, MIPS_INS_ADDS_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_u.b $wd, $ws, $wt */ + Mips_ADDS_U_B /* 806 */, MIPS_INS_ADDS_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_u.d $wd, $ws, $wt */ + Mips_ADDS_U_D /* 807 */, MIPS_INS_ADDS_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_u.h $wd, $ws, $wt */ + Mips_ADDS_U_H /* 808 */, MIPS_INS_ADDS_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_u.w $wd, $ws, $wt */ + Mips_ADDS_U_W /* 809 */, MIPS_INS_ADDS_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu16 $rd, $rs, $rt */ + Mips_ADDU16_MM /* 810 */, MIPS_INS_ADDU16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu16 $rd, $rs, $rt */ + Mips_ADDU16_MMR6 /* 811 */, MIPS_INS_ADDU16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adduh.qb $rd, $rs, $rt */ + Mips_ADDUH_QB /* 812 */, MIPS_INS_ADDUH_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adduh.qb $rd, $rs, $rt */ + Mips_ADDUH_QB_MMR2 /* 813 */, MIPS_INS_ADDUH_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adduh_r.qb $rd, $rs, $rt */ + Mips_ADDUH_R_QB /* 814 */, MIPS_INS_ADDUH_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adduh_r.qb $rd, $rs, $rt */ + Mips_ADDUH_R_QB_MMR2 /* 815 */, MIPS_INS_ADDUH_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $rd, $rs, $rt */ + Mips_ADDU_MMR6 /* 816 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu.ph $rd, $rs, $rt */ + Mips_ADDU_PH /* 817 */, MIPS_INS_ADDU_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu.ph $rd, $rs, $rt */ + Mips_ADDU_PH_MMR2 /* 818 */, MIPS_INS_ADDU_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu.qb $rd, $rs, $rt */ + Mips_ADDU_QB /* 819 */, MIPS_INS_ADDU_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu.qb $rd, $rs, $rt */ + Mips_ADDU_QB_MM /* 820 */, MIPS_INS_ADDU_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu_s.ph $rd, $rs, $rt */ + Mips_ADDU_S_PH /* 821 */, MIPS_INS_ADDU_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu_s.ph $rd, $rs, $rt */ + Mips_ADDU_S_PH_MMR2 /* 822 */, MIPS_INS_ADDU_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu_s.qb $rd, $rs, $rt */ + Mips_ADDU_S_QB /* 823 */, MIPS_INS_ADDU_S_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu_s.qb $rd, $rs, $rt */ + Mips_ADDU_S_QB_MM /* 824 */, MIPS_INS_ADDU_S_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addvi.b $wd, $ws, $imm */ + Mips_ADDVI_B /* 825 */, MIPS_INS_ADDVI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addvi.d $wd, $ws, $imm */ + Mips_ADDVI_D /* 826 */, MIPS_INS_ADDVI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addvi.h $wd, $ws, $imm */ + Mips_ADDVI_H /* 827 */, MIPS_INS_ADDVI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addvi.w $wd, $ws, $imm */ + Mips_ADDVI_W /* 828 */, MIPS_INS_ADDVI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addv.b $wd, $ws, $wt */ + Mips_ADDV_B /* 829 */, MIPS_INS_ADDV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addv.d $wd, $ws, $wt */ + Mips_ADDV_D /* 830 */, MIPS_INS_ADDV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addv.h $wd, $ws, $wt */ + Mips_ADDV_H /* 831 */, MIPS_INS_ADDV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addv.w $wd, $ws, $wt */ + Mips_ADDV_W /* 832 */, MIPS_INS_ADDV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addwc $rd, $rs, $rt */ + Mips_ADDWC /* 833 */, MIPS_INS_ADDWC, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addwc $rd, $rs, $rt */ + Mips_ADDWC_MM /* 834 */, MIPS_INS_ADDWC, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add_a.b $wd, $ws, $wt */ + Mips_ADD_A_B /* 835 */, MIPS_INS_ADD_A_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add_a.d $wd, $ws, $wt */ + Mips_ADD_A_D /* 836 */, MIPS_INS_ADD_A_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add_a.h $wd, $ws, $wt */ + Mips_ADD_A_H /* 837 */, MIPS_INS_ADD_A_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add_a.w $wd, $ws, $wt */ + Mips_ADD_A_W /* 838 */, MIPS_INS_ADD_A_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add $rd, $rs, $rt */ + Mips_ADD_MM /* 839 */, MIPS_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add $rd, $rs, $rt */ + Mips_ADD_MMR6 /* 840 */, MIPS_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add $rd, $rs, $rt */ + Mips_ADD_NM /* 841 */, MIPS_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addi $rt, $rs, $imm16 */ + Mips_ADDi /* 842 */, MIPS_INS_ADDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addi $rt, $rs, $imm16 */ + Mips_ADDi_MM /* 843 */, MIPS_INS_ADDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rt, $rs, $imm16 */ + Mips_ADDiu /* 844 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rt, $rs, $imm16 */ + Mips_ADDiu_MM /* 845 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $rd, $rs, $rt */ + Mips_ADDu /* 846 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $rd, $rs, $rt */ + Mips_ADDu16_NM /* 847 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $dst, $rt, $rs */ + Mips_ADDu4x4_NM /* 848 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $rd, $rs, $rt */ + Mips_ADDu_MM /* 849 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $rd, $rs, $rt */ + Mips_ADDu_NM /* 850 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* align $rd, $rs, $rt, $bp */ + Mips_ALIGN /* 851 */, MIPS_INS_ALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* align $rd, $rs, $rt, $bp */ + Mips_ALIGN_MMR6 /* 852 */, MIPS_INS_ALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aluipc $rs, $imm */ + Mips_ALUIPC /* 853 */, MIPS_INS_ALUIPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aluipc $rt, $imm */ + Mips_ALUIPC_MMR6 /* 854 */, MIPS_INS_ALUIPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aluipc $rt, $imm */ + Mips_ALUIPC_NM /* 855 */, MIPS_INS_ALUIPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $rd, $rs, $rt */ + Mips_AND /* 856 */, MIPS_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and16 $rt, $rs */ + Mips_AND16_MM /* 857 */, MIPS_INS_AND16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and16 $rt, $rs */ + Mips_AND16_MMR6 /* 858 */, MIPS_INS_AND16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $dst, $rs, $rt */ + Mips_AND16_NM /* 859 */, MIPS_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $rd, $rs, $rt */ + Mips_AND64 /* 860 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* andi16 $rd, $rs, $imm */ + Mips_ANDI16_MM /* 861 */, MIPS_INS_ANDI16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi16 $rd, $rs, $imm */ + Mips_ANDI16_MMR6 /* 862 */, MIPS_INS_ANDI16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi[16] $rt, $rs, $imm */ + Mips_ANDI16_NM /* 863 */, MIPS_INS_ANDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi.b $wd, $ws, $u8 */ + Mips_ANDI_B /* 864 */, MIPS_INS_ANDI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi $rt, $rs, $imm16 */ + Mips_ANDI_MMR6 /* 865 */, MIPS_INS_ANDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi[32] $rt, $rs, $imm */ + Mips_ANDI_NM /* 866 */, MIPS_INS_ANDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $rd, $rs, $rt */ + Mips_AND_MM /* 867 */, MIPS_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $rd, $rs, $rt */ + Mips_AND_MMR6 /* 868 */, MIPS_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $rd, $rs, $rt */ + Mips_AND_NM /* 869 */, MIPS_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and.v $wd, $ws, $wt */ + Mips_AND_V /* 870 */, MIPS_INS_AND_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi $rt, $rs, $imm16 */ + Mips_ANDi /* 871 */, MIPS_INS_ANDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi $rt, $rs, $imm16 */ + Mips_ANDi64 /* 872 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* andi $rt, $rs, $imm16 */ + Mips_ANDi_MM /* 873 */, MIPS_INS_ANDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* append $rt, $rs, $sa */ + Mips_APPEND /* 874 */, MIPS_INS_APPEND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* append $rt, $rs, $sa */ + Mips_APPEND_MMR2 /* 875 */, MIPS_INS_APPEND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_s.b $wd, $ws, $wt */ + Mips_ASUB_S_B /* 876 */, MIPS_INS_ASUB_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_s.d $wd, $ws, $wt */ + Mips_ASUB_S_D /* 877 */, MIPS_INS_ASUB_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_s.h $wd, $ws, $wt */ + Mips_ASUB_S_H /* 878 */, MIPS_INS_ASUB_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_s.w $wd, $ws, $wt */ + Mips_ASUB_S_W /* 879 */, MIPS_INS_ASUB_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_u.b $wd, $ws, $wt */ + Mips_ASUB_U_B /* 880 */, MIPS_INS_ASUB_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_u.d $wd, $ws, $wt */ + Mips_ASUB_U_D /* 881 */, MIPS_INS_ASUB_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_u.h $wd, $ws, $wt */ + Mips_ASUB_U_H /* 882 */, MIPS_INS_ASUB_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_u.w $wd, $ws, $wt */ + Mips_ASUB_U_W /* 883 */, MIPS_INS_ASUB_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aui $rt, $rs, $imm */ + Mips_AUI /* 884 */, MIPS_INS_AUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* auipc $rs, $imm */ + Mips_AUIPC /* 885 */, MIPS_INS_AUIPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* auipc $rt, $imm */ + Mips_AUIPC_MMR6 /* 886 */, MIPS_INS_AUIPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aui $rt, $rs, $imm */ + Mips_AUI_MMR6 /* 887 */, MIPS_INS_AUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_s.b $wd, $ws, $wt */ + Mips_AVER_S_B /* 888 */, MIPS_INS_AVER_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_s.d $wd, $ws, $wt */ + Mips_AVER_S_D /* 889 */, MIPS_INS_AVER_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_s.h $wd, $ws, $wt */ + Mips_AVER_S_H /* 890 */, MIPS_INS_AVER_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_s.w $wd, $ws, $wt */ + Mips_AVER_S_W /* 891 */, MIPS_INS_AVER_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_u.b $wd, $ws, $wt */ + Mips_AVER_U_B /* 892 */, MIPS_INS_AVER_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_u.d $wd, $ws, $wt */ + Mips_AVER_U_D /* 893 */, MIPS_INS_AVER_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_u.h $wd, $ws, $wt */ + Mips_AVER_U_H /* 894 */, MIPS_INS_AVER_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_u.w $wd, $ws, $wt */ + Mips_AVER_U_W /* 895 */, MIPS_INS_AVER_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_s.b $wd, $ws, $wt */ + Mips_AVE_S_B /* 896 */, MIPS_INS_AVE_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_s.d $wd, $ws, $wt */ + Mips_AVE_S_D /* 897 */, MIPS_INS_AVE_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_s.h $wd, $ws, $wt */ + Mips_AVE_S_H /* 898 */, MIPS_INS_AVE_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_s.w $wd, $ws, $wt */ + Mips_AVE_S_W /* 899 */, MIPS_INS_AVE_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_u.b $wd, $ws, $wt */ + Mips_AVE_U_B /* 900 */, MIPS_INS_AVE_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_u.d $wd, $ws, $wt */ + Mips_AVE_U_D /* 901 */, MIPS_INS_AVE_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_u.h $wd, $ws, $wt */ + Mips_AVE_U_H /* 902 */, MIPS_INS_AVE_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_u.w $wd, $ws, $wt */ + Mips_AVE_U_W /* 903 */, MIPS_INS_AVE_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rx, $imm16 */ + Mips_AddiuRxImmX16 /* 904 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rx, $$pc, $imm16 */ + Mips_AddiuRxPcImmX16 /* 905 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rx, $imm8 # 16 bit inst */ + Mips_AddiuRxRxImm16 /* 906 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rx, $imm16 */ + Mips_AddiuRxRxImmX16 /* 907 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* addiu $ry, $addr */ + Mips_AddiuRxRyOffMemX16 /* 908 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $$sp, $imm8 # 16 bit inst */ + Mips_AddiuSpImm16 /* 909 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $$sp, $imm16 */ + Mips_AddiuSpImmX16 /* 910 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $rz, $rx, $ry */ + Mips_AdduRxRyRz16 /* 911 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $rz, $ry */ + Mips_AndRxRxRy16 /* 912 */, MIPS_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* b16 $offset */ + Mips_B16_MM /* 913 */, MIPS_INS_B16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* baddu $rd, $rs, $rt */ + Mips_BADDu /* 914 */, MIPS_INS_BADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bal $offset */ + Mips_BAL /* 915 */, MIPS_INS_BAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* balc $offset */ + Mips_BALC /* 916 */, MIPS_INS_BALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* balc[16] $addr */ + Mips_BALC16_NM /* 917 */, MIPS_INS_BALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA_NM, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* balc $offset */ + Mips_BALC_MMR6 /* 918 */, MIPS_INS_BALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* balc $addr */ + Mips_BALC_NM /* 919 */, MIPS_INS_BALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA_NM, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* balign $rt, $rs, $sa */ + Mips_BALIGN /* 920 */, MIPS_INS_BALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* balign $rt, $rs, $bp */ + Mips_BALIGN_MMR2 /* 921 */, MIPS_INS_BALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* balrsc $rt, $rs */ + Mips_BALRSC_NM /* 922 */, MIPS_INS_BALRSC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bbeqzc $rt, $u, $offset */ + Mips_BBEQZC_NM /* 923 */, MIPS_INS_BBEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bbit0 $rs, $p, $offset */ + Mips_BBIT0 /* 924 */, MIPS_INS_BBIT0, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASCNMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bbit032 $rs, $p, $offset */ + Mips_BBIT032 /* 925 */, MIPS_INS_BBIT032, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASCNMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bbit1 $rs, $p, $offset */ + Mips_BBIT1 /* 926 */, MIPS_INS_BBIT1, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASCNMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bbit132 $rs, $p, $offset */ + Mips_BBIT132 /* 927 */, MIPS_INS_BBIT132, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASCNMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bbnezc $rt, $u, $offset */ + Mips_BBNEZC_NM /* 928 */, MIPS_INS_BBNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc $offset */ + Mips_BC /* 929 */, MIPS_INS_BC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc16 $offset */ + Mips_BC16_MMR6 /* 930 */, MIPS_INS_BC16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc $addr */ + Mips_BC16_NM /* 931 */, MIPS_INS_BC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1eqz $ft, $offset */ + Mips_BC1EQZ /* 932 */, MIPS_INS_BC1EQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1eqzc $rt, $offset */ + Mips_BC1EQZC_MMR6 /* 933 */, MIPS_INS_BC1EQZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1f $fcc, $offset */ + Mips_BC1F /* 934 */, MIPS_INS_BC1F, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1fl $fcc, $offset */ + Mips_BC1FL /* 935 */, MIPS_INS_BC1FL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1f $fcc, $offset */ + Mips_BC1F_MM /* 936 */, MIPS_INS_BC1F, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1nez $ft, $offset */ + Mips_BC1NEZ /* 937 */, MIPS_INS_BC1NEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1nezc $rt, $offset */ + Mips_BC1NEZC_MMR6 /* 938 */, MIPS_INS_BC1NEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1t $fcc, $offset */ + Mips_BC1T /* 939 */, MIPS_INS_BC1T, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1tl $fcc, $offset */ + Mips_BC1TL /* 940 */, MIPS_INS_BC1TL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1t $fcc, $offset */ + Mips_BC1T_MM /* 941 */, MIPS_INS_BC1T, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc2eqz $ct, $offset */ + Mips_BC2EQZ /* 942 */, MIPS_INS_BC2EQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc2eqzc $rt, $offset */ + Mips_BC2EQZC_MMR6 /* 943 */, MIPS_INS_BC2EQZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc2nez $ct, $offset */ + Mips_BC2NEZ /* 944 */, MIPS_INS_BC2NEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc2nezc $rt, $offset */ + Mips_BC2NEZC_MMR6 /* 945 */, MIPS_INS_BC2NEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bclri.b $wd, $ws, $m */ + Mips_BCLRI_B /* 946 */, MIPS_INS_BCLRI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclri.d $wd, $ws, $m */ + Mips_BCLRI_D /* 947 */, MIPS_INS_BCLRI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclri.h $wd, $ws, $m */ + Mips_BCLRI_H /* 948 */, MIPS_INS_BCLRI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclri.w $wd, $ws, $m */ + Mips_BCLRI_W /* 949 */, MIPS_INS_BCLRI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclr.b $wd, $ws, $wt */ + Mips_BCLR_B /* 950 */, MIPS_INS_BCLR_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclr.d $wd, $ws, $wt */ + Mips_BCLR_D /* 951 */, MIPS_INS_BCLR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclr.h $wd, $ws, $wt */ + Mips_BCLR_H /* 952 */, MIPS_INS_BCLR_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclr.w $wd, $ws, $wt */ + Mips_BCLR_W /* 953 */, MIPS_INS_BCLR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bc $offset */ + Mips_BC_MMR6 /* 954 */, MIPS_INS_BC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc $addr */ + Mips_BC_NM /* 955 */, MIPS_INS_BC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beq $rs, $rt, $offset */ + Mips_BEQ /* 956 */, MIPS_INS_BEQ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beq $rs, $rt, $offset */ + Mips_BEQ64 /* 957 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* beqc $rs, $rt, $offset */ + Mips_BEQC /* 958 */, MIPS_INS_BEQC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqc $rs, $rt, $offset */ + Mips_BEQC16_NM /* 959 */, MIPS_INS_BEQC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqc $rs, $rt, $offset */ + Mips_BEQC64 /* 960 */, MIPS_INS_BEQC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqc $rs, $rt, $offset */ + Mips_BEQC_MMR6 /* 961 */, MIPS_INS_BEQC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqc $rs, $rt, $offset */ + Mips_BEQC_NM /* 962 */, MIPS_INS_BEQC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqc $rs, $rt, $offset */ + Mips_BEQCzero_NM /* 963 */, MIPS_INS_BEQC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqic $rt, $u, $offset */ + Mips_BEQIC_NM /* 964 */, MIPS_INS_BEQIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beql $rs, $rt, $offset */ + Mips_BEQL /* 965 */, MIPS_INS_BEQL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqz16 $rs, $offset */ + Mips_BEQZ16_MM /* 966 */, MIPS_INS_BEQZ16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzalc $rt, $offset */ + Mips_BEQZALC /* 967 */, MIPS_INS_BEQZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzalc $rt, $offset */ + Mips_BEQZALC_MMR6 /* 968 */, MIPS_INS_BEQZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc $rs, $offset */ + Mips_BEQZC /* 969 */, MIPS_INS_BEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc16 $rs, $offset */ + Mips_BEQZC16_MMR6 /* 970 */, MIPS_INS_BEQZC16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc $rs, $offset */ + Mips_BEQZC16_NM /* 971 */, MIPS_INS_BEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc $rs, $offset */ + Mips_BEQZC64 /* 972 */, MIPS_INS_BEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc $rs, $offset */ + Mips_BEQZC_MM /* 973 */, MIPS_INS_BEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc $rs, $offset */ + Mips_BEQZC_MMR6 /* 974 */, MIPS_INS_BEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc $rs, $offset */ + Mips_BEQZC_NM /* 975 */, MIPS_INS_BEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beq $rs, $rt, $offset */ + Mips_BEQ_MM /* 976 */, MIPS_INS_BEQ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgec $rs, $rt, $offset */ + Mips_BGEC /* 977 */, MIPS_INS_BGEC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgec $rs, $rt, $offset */ + Mips_BGEC64 /* 978 */, MIPS_INS_BGEC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgec $rs, $rt, $offset */ + Mips_BGEC_MMR6 /* 979 */, MIPS_INS_BGEC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgec $rs, $rt, $offset */ + Mips_BGEC_NM /* 980 */, MIPS_INS_BGEC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgeic $rt, $u, $offset */ + Mips_BGEIC_NM /* 981 */, MIPS_INS_BGEIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgeiuc $rt, $u, $offset */ + Mips_BGEIUC_NM /* 982 */, MIPS_INS_BGEIUC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgeuc $rs, $rt, $offset */ + Mips_BGEUC /* 983 */, MIPS_INS_BGEUC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgeuc $rs, $rt, $offset */ + Mips_BGEUC64 /* 984 */, MIPS_INS_BGEUC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgeuc $rs, $rt, $offset */ + Mips_BGEUC_MMR6 /* 985 */, MIPS_INS_BGEUC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgeuc $rs, $rt, $offset */ + Mips_BGEUC_NM /* 986 */, MIPS_INS_BGEUC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgez $rs, $offset */ + Mips_BGEZ /* 987 */, MIPS_INS_BGEZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgez $rs, $offset */ + Mips_BGEZ64 /* 988 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bgezal $rs, $offset */ + Mips_BGEZAL /* 989 */, MIPS_INS_BGEZAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgezalc $rt, $offset */ + Mips_BGEZALC /* 990 */, MIPS_INS_BGEZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgezalc $rt, $offset */ + Mips_BGEZALC_MMR6 /* 991 */, MIPS_INS_BGEZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgezall $rs, $offset */ + Mips_BGEZALL /* 992 */, MIPS_INS_BGEZALL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgezals $rs, $offset */ + Mips_BGEZALS_MM /* 993 */, MIPS_INS_BGEZALS, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgezal $rs, $offset */ + Mips_BGEZAL_MM /* 994 */, MIPS_INS_BGEZAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgezc $rt, $offset */ + Mips_BGEZC /* 995 */, MIPS_INS_BGEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgezc $rt, $offset */ + Mips_BGEZC64 /* 996 */, MIPS_INS_BGEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgezc $rt, $offset */ + Mips_BGEZC_MMR6 /* 997 */, MIPS_INS_BGEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgezl $rs, $offset */ + Mips_BGEZL /* 998 */, MIPS_INS_BGEZL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgez $rs, $offset */ + Mips_BGEZ_MM /* 999 */, MIPS_INS_BGEZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtz $rs, $offset */ + Mips_BGTZ /* 1000 */, MIPS_INS_BGTZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtz $rs, $offset */ + Mips_BGTZ64 /* 1001 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bgtzalc $rt, $offset */ + Mips_BGTZALC /* 1002 */, MIPS_INS_BGTZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtzalc $rt, $offset */ + Mips_BGTZALC_MMR6 /* 1003 */, MIPS_INS_BGTZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtzc $rt, $offset */ + Mips_BGTZC /* 1004 */, MIPS_INS_BGTZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtzc $rt, $offset */ + Mips_BGTZC64 /* 1005 */, MIPS_INS_BGTZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtzc $rt, $offset */ + Mips_BGTZC_MMR6 /* 1006 */, MIPS_INS_BGTZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtzl $rs, $offset */ + Mips_BGTZL /* 1007 */, MIPS_INS_BGTZL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtz $rs, $offset */ + Mips_BGTZ_MM /* 1008 */, MIPS_INS_BGTZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* binsli.b $wd, $ws, $m */ + Mips_BINSLI_B /* 1009 */, MIPS_INS_BINSLI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsli.d $wd, $ws, $m */ + Mips_BINSLI_D /* 1010 */, MIPS_INS_BINSLI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsli.h $wd, $ws, $m */ + Mips_BINSLI_H /* 1011 */, MIPS_INS_BINSLI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsli.w $wd, $ws, $m */ + Mips_BINSLI_W /* 1012 */, MIPS_INS_BINSLI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsl.b $wd, $ws, $wt */ + Mips_BINSL_B /* 1013 */, MIPS_INS_BINSL_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsl.d $wd, $ws, $wt */ + Mips_BINSL_D /* 1014 */, MIPS_INS_BINSL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsl.h $wd, $ws, $wt */ + Mips_BINSL_H /* 1015 */, MIPS_INS_BINSL_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsl.w $wd, $ws, $wt */ + Mips_BINSL_W /* 1016 */, MIPS_INS_BINSL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsri.b $wd, $ws, $m */ + Mips_BINSRI_B /* 1017 */, MIPS_INS_BINSRI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsri.d $wd, $ws, $m */ + Mips_BINSRI_D /* 1018 */, MIPS_INS_BINSRI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsri.h $wd, $ws, $m */ + Mips_BINSRI_H /* 1019 */, MIPS_INS_BINSRI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsri.w $wd, $ws, $m */ + Mips_BINSRI_W /* 1020 */, MIPS_INS_BINSRI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsr.b $wd, $ws, $wt */ + Mips_BINSR_B /* 1021 */, MIPS_INS_BINSR_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsr.d $wd, $ws, $wt */ + Mips_BINSR_D /* 1022 */, MIPS_INS_BINSR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsr.h $wd, $ws, $wt */ + Mips_BINSR_H /* 1023 */, MIPS_INS_BINSR_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsr.w $wd, $ws, $wt */ + Mips_BINSR_W /* 1024 */, MIPS_INS_BINSR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bitrev $rd, $rt */ + Mips_BITREV /* 1025 */, MIPS_INS_BITREV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bitrevw $rt, $rs */ + Mips_BITREVW_NM /* 1026 */, MIPS_INS_BITREVW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bitrev $rt, $rs */ + Mips_BITREV_MM /* 1027 */, MIPS_INS_BITREV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bitswap $rd, $rt */ + Mips_BITSWAP /* 1028 */, MIPS_INS_BITSWAP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bitswap $rd, $rt */ + Mips_BITSWAP_MMR6 /* 1029 */, MIPS_INS_BITSWAP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* blez $rs, $offset */ + Mips_BLEZ /* 1030 */, MIPS_INS_BLEZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blez $rs, $offset */ + Mips_BLEZ64 /* 1031 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* blezalc $rt, $offset */ + Mips_BLEZALC /* 1032 */, MIPS_INS_BLEZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blezalc $rt, $offset */ + Mips_BLEZALC_MMR6 /* 1033 */, MIPS_INS_BLEZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blezc $rt, $offset */ + Mips_BLEZC /* 1034 */, MIPS_INS_BLEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blezc $rt, $offset */ + Mips_BLEZC64 /* 1035 */, MIPS_INS_BLEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blezc $rt, $offset */ + Mips_BLEZC_MMR6 /* 1036 */, MIPS_INS_BLEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blezl $rs, $offset */ + Mips_BLEZL /* 1037 */, MIPS_INS_BLEZL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blez $rs, $offset */ + Mips_BLEZ_MM /* 1038 */, MIPS_INS_BLEZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltc $rs, $rt, $offset */ + Mips_BLTC /* 1039 */, MIPS_INS_BLTC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltc $rs, $rt, $offset */ + Mips_BLTC64 /* 1040 */, MIPS_INS_BLTC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltc $rs, $rt, $offset */ + Mips_BLTC_MMR6 /* 1041 */, MIPS_INS_BLTC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltc $rs, $rt, $offset */ + Mips_BLTC_NM /* 1042 */, MIPS_INS_BLTC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltic $rt, $u, $offset */ + Mips_BLTIC_NM /* 1043 */, MIPS_INS_BLTIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltiuc $rt, $u, $offset */ + Mips_BLTIUC_NM /* 1044 */, MIPS_INS_BLTIUC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltuc $rs, $rt, $offset */ + Mips_BLTUC /* 1045 */, MIPS_INS_BLTUC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltuc $rs, $rt, $offset */ + Mips_BLTUC64 /* 1046 */, MIPS_INS_BLTUC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltuc $rs, $rt, $offset */ + Mips_BLTUC_MMR6 /* 1047 */, MIPS_INS_BLTUC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltuc $rs, $rt, $offset */ + Mips_BLTUC_NM /* 1048 */, MIPS_INS_BLTUC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltz $rs, $offset */ + Mips_BLTZ /* 1049 */, MIPS_INS_BLTZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltz $rs, $offset */ + Mips_BLTZ64 /* 1050 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bltzal $rs, $offset */ + Mips_BLTZAL /* 1051 */, MIPS_INS_BLTZAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltzalc $rt, $offset */ + Mips_BLTZALC /* 1052 */, MIPS_INS_BLTZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltzalc $rt, $offset */ + Mips_BLTZALC_MMR6 /* 1053 */, MIPS_INS_BLTZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltzall $rs, $offset */ + Mips_BLTZALL /* 1054 */, MIPS_INS_BLTZALL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltzals $rs, $offset */ + Mips_BLTZALS_MM /* 1055 */, MIPS_INS_BLTZALS, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltzal $rs, $offset */ + Mips_BLTZAL_MM /* 1056 */, MIPS_INS_BLTZAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltzc $rt, $offset */ + Mips_BLTZC /* 1057 */, MIPS_INS_BLTZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltzc $rt, $offset */ + Mips_BLTZC64 /* 1058 */, MIPS_INS_BLTZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltzc $rt, $offset */ + Mips_BLTZC_MMR6 /* 1059 */, MIPS_INS_BLTZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltzl $rs, $offset */ + Mips_BLTZL /* 1060 */, MIPS_INS_BLTZL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltz $rs, $offset */ + Mips_BLTZ_MM /* 1061 */, MIPS_INS_BLTZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bmnzi.b $wd, $ws, $u8 */ + Mips_BMNZI_B /* 1062 */, MIPS_INS_BMNZI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bmnz.v $wd, $ws, $wt */ + Mips_BMNZ_V /* 1063 */, MIPS_INS_BMNZ_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bmzi.b $wd, $ws, $u8 */ + Mips_BMZI_B /* 1064 */, MIPS_INS_BMZI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bmz.v $wd, $ws, $wt */ + Mips_BMZ_V /* 1065 */, MIPS_INS_BMZ_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bne $rs, $rt, $offset */ + Mips_BNE /* 1066 */, MIPS_INS_BNE, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bne $rs, $rt, $offset */ + Mips_BNE64 /* 1067 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bnec $rs, $rt, $offset */ + Mips_BNEC /* 1068 */, MIPS_INS_BNEC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnec $rs, $rt, $offset */ + Mips_BNEC16_NM /* 1069 */, MIPS_INS_BNEC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnec $rs, $rt, $offset */ + Mips_BNEC64 /* 1070 */, MIPS_INS_BNEC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnec $rs, $rt, $offset */ + Mips_BNEC_MMR6 /* 1071 */, MIPS_INS_BNEC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnec $rs, $rt, $offset */ + Mips_BNEC_NM /* 1072 */, MIPS_INS_BNEC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnec $rs, $rt, $offset */ + Mips_BNECzero_NM /* 1073 */, MIPS_INS_BNEC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnegi.b $wd, $ws, $m */ + Mips_BNEGI_B /* 1074 */, MIPS_INS_BNEGI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bnegi.d $wd, $ws, $m */ + Mips_BNEGI_D /* 1075 */, MIPS_INS_BNEGI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bnegi.h $wd, $ws, $m */ + Mips_BNEGI_H /* 1076 */, MIPS_INS_BNEGI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bnegi.w $wd, $ws, $m */ + Mips_BNEGI_W /* 1077 */, MIPS_INS_BNEGI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bneg.b $wd, $ws, $wt */ + Mips_BNEG_B /* 1078 */, MIPS_INS_BNEG_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bneg.d $wd, $ws, $wt */ + Mips_BNEG_D /* 1079 */, MIPS_INS_BNEG_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bneg.h $wd, $ws, $wt */ + Mips_BNEG_H /* 1080 */, MIPS_INS_BNEG_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bneg.w $wd, $ws, $wt */ + Mips_BNEG_W /* 1081 */, MIPS_INS_BNEG_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bneic $rt, $u, $offset */ + Mips_BNEIC_NM /* 1082 */, MIPS_INS_BNEIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnel $rs, $rt, $offset */ + Mips_BNEL /* 1083 */, MIPS_INS_BNEL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnez16 $rs, $offset */ + Mips_BNEZ16_MM /* 1084 */, MIPS_INS_BNEZ16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezalc $rt, $offset */ + Mips_BNEZALC /* 1085 */, MIPS_INS_BNEZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezalc $rt, $offset */ + Mips_BNEZALC_MMR6 /* 1086 */, MIPS_INS_BNEZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc $rs, $offset */ + Mips_BNEZC /* 1087 */, MIPS_INS_BNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc16 $rs, $offset */ + Mips_BNEZC16_MMR6 /* 1088 */, MIPS_INS_BNEZC16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc $rs, $offset */ + Mips_BNEZC16_NM /* 1089 */, MIPS_INS_BNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc $rs, $offset */ + Mips_BNEZC64 /* 1090 */, MIPS_INS_BNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc $rs, $offset */ + Mips_BNEZC_MM /* 1091 */, MIPS_INS_BNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc $rs, $offset */ + Mips_BNEZC_MMR6 /* 1092 */, MIPS_INS_BNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc $rs, $offset */ + Mips_BNEZC_NM /* 1093 */, MIPS_INS_BNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bne $rs, $rt, $offset */ + Mips_BNE_MM /* 1094 */, MIPS_INS_BNE, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnvc $rs, $rt, $offset */ + Mips_BNVC /* 1095 */, MIPS_INS_BNVC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnvc $rt, $rs, $offset */ + Mips_BNVC_MMR6 /* 1096 */, MIPS_INS_BNVC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnz.b $wt, $offset */ + Mips_BNZ_B /* 1097 */, MIPS_INS_BNZ_B, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnz.d $wt, $offset */ + Mips_BNZ_D /* 1098 */, MIPS_INS_BNZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnz.h $wt, $offset */ + Mips_BNZ_H /* 1099 */, MIPS_INS_BNZ_H, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnz.v $wt, $offset */ + Mips_BNZ_V /* 1100 */, MIPS_INS_BNZ_V, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnz.w $wt, $offset */ + Mips_BNZ_W /* 1101 */, MIPS_INS_BNZ_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bovc $rs, $rt, $offset */ + Mips_BOVC /* 1102 */, MIPS_INS_BOVC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bovc $rt, $rs, $offset */ + Mips_BOVC_MMR6 /* 1103 */, MIPS_INS_BOVC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bposge32 $offset */ + Mips_BPOSGE32 /* 1104 */, MIPS_INS_BPOSGE32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASDSP, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bposge32c $offset */ + Mips_BPOSGE32C_MMR3 /* 1105 */, MIPS_INS_BPOSGE32C, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR3, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bposge32 $offset */ + Mips_BPOSGE32_MM /* 1106 */, MIPS_INS_BPOSGE32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_HASDSP, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* break $code_1, $code_2 */ + Mips_BREAK /* 1107 */, MIPS_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* break16 $code_ */ + Mips_BREAK16_MM /* 1108 */, MIPS_INS_BREAK16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* break16 $code_ */ + Mips_BREAK16_MMR6 /* 1109 */, MIPS_INS_BREAK16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* break $imm */ + Mips_BREAK16_NM /* 1110 */, MIPS_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* break $code_1, $code_2 */ + Mips_BREAK_MM /* 1111 */, MIPS_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* break $code_1, $code_2 */ + Mips_BREAK_MMR6 /* 1112 */, MIPS_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* break $imm */ + Mips_BREAK_NM /* 1113 */, MIPS_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* brsc $rs */ + Mips_BRSC_NM /* 1114 */, MIPS_INS_BRSC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bseli.b $wd, $ws, $u8 */ + Mips_BSELI_B /* 1115 */, MIPS_INS_BSELI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bsel.v $wd, $ws, $wt */ + Mips_BSEL_V /* 1116 */, MIPS_INS_BSEL_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bseti.b $wd, $ws, $m */ + Mips_BSETI_B /* 1117 */, MIPS_INS_BSETI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bseti.d $wd, $ws, $m */ + Mips_BSETI_D /* 1118 */, MIPS_INS_BSETI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bseti.h $wd, $ws, $m */ + Mips_BSETI_H /* 1119 */, MIPS_INS_BSETI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bseti.w $wd, $ws, $m */ + Mips_BSETI_W /* 1120 */, MIPS_INS_BSETI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bset.b $wd, $ws, $wt */ + Mips_BSET_B /* 1121 */, MIPS_INS_BSET_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bset.d $wd, $ws, $wt */ + Mips_BSET_D /* 1122 */, MIPS_INS_BSET_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bset.h $wd, $ws, $wt */ + Mips_BSET_H /* 1123 */, MIPS_INS_BSET_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bset.w $wd, $ws, $wt */ + Mips_BSET_W /* 1124 */, MIPS_INS_BSET_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* byterevw $rt, $rs */ + Mips_BYTEREVW_NM /* 1125 */, MIPS_INS_BYTEREVW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bz.b $wt, $offset */ + Mips_BZ_B /* 1126 */, MIPS_INS_BZ_B, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bz.d $wt, $offset */ + Mips_BZ_D /* 1127 */, MIPS_INS_BZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bz.h $wt, $offset */ + Mips_BZ_H /* 1128 */, MIPS_INS_BZ_H, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bz.v $wt, $offset */ + Mips_BZ_V /* 1129 */, MIPS_INS_BZ_V, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bz.w $wt, $offset */ + Mips_BZ_W /* 1130 */, MIPS_INS_BZ_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqz $rx, $imm8 # 16 bit inst */ + Mips_BeqzRxImm16 /* 1131 */, MIPS_INS_BEQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqz $rx, $imm16 */ + Mips_BeqzRxImmX16 /* 1132 */, MIPS_INS_BEQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* b $imm11 # 16 bit inst */ + Mips_Bimm16 /* 1133 */, MIPS_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* b $imm16 */ + Mips_BimmX16 /* 1134 */, MIPS_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnez $rx, $imm8 # 16 bit inst */ + Mips_BnezRxImm16 /* 1135 */, MIPS_INS_BNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnez $rx, $imm16 */ + Mips_BnezRxImmX16 /* 1136 */, MIPS_INS_BNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* break 0 */ + Mips_Break16 /* 1137 */, MIPS_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bteqz $imm8 # 16 bit inst */ + Mips_Bteqz16 /* 1138 */, MIPS_INS_BTEQZ, + #ifndef CAPSTONE_DIET + { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bteqz $imm16 */ + Mips_BteqzX16 /* 1139 */, MIPS_INS_BTEQZ, + #ifndef CAPSTONE_DIET + { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* btnez $imm8 # 16 bit inst */ + Mips_Btnez16 /* 1140 */, MIPS_INS_BTNEZ, + #ifndef CAPSTONE_DIET + { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* btnez $imm16 */ + Mips_BtnezX16 /* 1141 */, MIPS_INS_BTNEZ, + #ifndef CAPSTONE_DIET + { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* cache $hint, $addr */ + Mips_CACHE /* 1142 */, MIPS_INS_CACHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cachee $hint, $addr */ + Mips_CACHEE /* 1143 */, MIPS_INS_CACHEE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cachee $hint, $addr */ + Mips_CACHEE_MM /* 1144 */, MIPS_INS_CACHEE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cache $hint, $addr */ + Mips_CACHE_MM /* 1145 */, MIPS_INS_CACHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cache $hint, $addr */ + Mips_CACHE_MMR6 /* 1146 */, MIPS_INS_CACHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cache $op, $addr */ + Mips_CACHE_NM /* 1147 */, MIPS_INS_CACHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cache $hint, $addr */ + Mips_CACHE_R6 /* 1148 */, MIPS_INS_CACHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.l.d $fd, $fs */ + Mips_CEIL_L_D64 /* 1149 */, MIPS_INS_CEIL_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.l.d $ft, $fs */ + Mips_CEIL_L_D_MMR6 /* 1150 */, MIPS_INS_CEIL_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.l.s $fd, $fs */ + Mips_CEIL_L_S /* 1151 */, MIPS_INS_CEIL_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.l.s $ft, $fs */ + Mips_CEIL_L_S_MMR6 /* 1152 */, MIPS_INS_CEIL_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.d $fd, $fs */ + Mips_CEIL_W_D32 /* 1153 */, MIPS_INS_CEIL_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.d $fd, $fs */ + Mips_CEIL_W_D64 /* 1154 */, MIPS_INS_CEIL_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.d $ft, $fs */ + Mips_CEIL_W_D_MMR6 /* 1155 */, MIPS_INS_CEIL_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.d $fd, $fs */ + Mips_CEIL_W_MM /* 1156 */, MIPS_INS_CEIL_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.s $fd, $fs */ + Mips_CEIL_W_S /* 1157 */, MIPS_INS_CEIL_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.s $fd, $fs */ + Mips_CEIL_W_S_MM /* 1158 */, MIPS_INS_CEIL_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.s $ft, $fs */ + Mips_CEIL_W_S_MMR6 /* 1159 */, MIPS_INS_CEIL_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceqi.b $wd, $ws, $imm */ + Mips_CEQI_B /* 1160 */, MIPS_INS_CEQI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceqi.d $wd, $ws, $imm */ + Mips_CEQI_D /* 1161 */, MIPS_INS_CEQI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceqi.h $wd, $ws, $imm */ + Mips_CEQI_H /* 1162 */, MIPS_INS_CEQI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceqi.w $wd, $ws, $imm */ + Mips_CEQI_W /* 1163 */, MIPS_INS_CEQI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceq.b $wd, $ws, $wt */ + Mips_CEQ_B /* 1164 */, MIPS_INS_CEQ_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceq.d $wd, $ws, $wt */ + Mips_CEQ_D /* 1165 */, MIPS_INS_CEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceq.h $wd, $ws, $wt */ + Mips_CEQ_H /* 1166 */, MIPS_INS_CEQ_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceq.w $wd, $ws, $wt */ + Mips_CEQ_W /* 1167 */, MIPS_INS_CEQ_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cfc1 $rt, $fs */ + Mips_CFC1 /* 1168 */, MIPS_INS_CFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cfc1 $rt, $fs */ + Mips_CFC1_MM /* 1169 */, MIPS_INS_CFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cfc2 $rt, $impl */ + Mips_CFC2_MM /* 1170 */, MIPS_INS_CFC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cfcmsa $rd, $cs */ + Mips_CFCMSA /* 1171 */, MIPS_INS_CFCMSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cins $rt, $rs, $pos, $lenm1 */ + Mips_CINS /* 1172 */, MIPS_INS_CINS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_HASCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cins32 $rt, $rs, $pos, $lenm1 */ + Mips_CINS32 /* 1173 */, MIPS_INS_CINS32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_HASCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cins $rt, $rs, $pos, $lenm1 */ + Mips_CINS64_32 /* 1174 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cins $rt, $rs, $pos, $lenm1 */ + Mips_CINS_i32 /* 1175 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* class.d $fd, $fs */ + Mips_CLASS_D /* 1176 */, MIPS_INS_CLASS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* class.d $fd, $fs */ + Mips_CLASS_D_MMR6 /* 1177 */, MIPS_INS_CLASS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* class.s $fd, $fs */ + Mips_CLASS_S /* 1178 */, MIPS_INS_CLASS_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* class.s $fd, $fs */ + Mips_CLASS_S_MMR6 /* 1179 */, MIPS_INS_CLASS_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_s.b $wd, $ws, $imm */ + Mips_CLEI_S_B /* 1180 */, MIPS_INS_CLEI_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_s.d $wd, $ws, $imm */ + Mips_CLEI_S_D /* 1181 */, MIPS_INS_CLEI_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_s.h $wd, $ws, $imm */ + Mips_CLEI_S_H /* 1182 */, MIPS_INS_CLEI_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_s.w $wd, $ws, $imm */ + Mips_CLEI_S_W /* 1183 */, MIPS_INS_CLEI_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_u.b $wd, $ws, $imm */ + Mips_CLEI_U_B /* 1184 */, MIPS_INS_CLEI_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_u.d $wd, $ws, $imm */ + Mips_CLEI_U_D /* 1185 */, MIPS_INS_CLEI_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_u.h $wd, $ws, $imm */ + Mips_CLEI_U_H /* 1186 */, MIPS_INS_CLEI_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_u.w $wd, $ws, $imm */ + Mips_CLEI_U_W /* 1187 */, MIPS_INS_CLEI_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_s.b $wd, $ws, $wt */ + Mips_CLE_S_B /* 1188 */, MIPS_INS_CLE_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_s.d $wd, $ws, $wt */ + Mips_CLE_S_D /* 1189 */, MIPS_INS_CLE_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_s.h $wd, $ws, $wt */ + Mips_CLE_S_H /* 1190 */, MIPS_INS_CLE_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_s.w $wd, $ws, $wt */ + Mips_CLE_S_W /* 1191 */, MIPS_INS_CLE_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_u.b $wd, $ws, $wt */ + Mips_CLE_U_B /* 1192 */, MIPS_INS_CLE_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_u.d $wd, $ws, $wt */ + Mips_CLE_U_D /* 1193 */, MIPS_INS_CLE_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_u.h $wd, $ws, $wt */ + Mips_CLE_U_H /* 1194 */, MIPS_INS_CLE_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_u.w $wd, $ws, $wt */ + Mips_CLE_U_W /* 1195 */, MIPS_INS_CLE_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clo $rd, $rs */ + Mips_CLO /* 1196 */, MIPS_INS_CLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clo $rd, $rs */ + Mips_CLO_MM /* 1197 */, MIPS_INS_CLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clo $rt, $rs */ + Mips_CLO_MMR6 /* 1198 */, MIPS_INS_CLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clo $rt, $rs */ + Mips_CLO_NM /* 1199 */, MIPS_INS_CLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clo $rd, $rs */ + Mips_CLO_R6 /* 1200 */, MIPS_INS_CLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_s.b $wd, $ws, $imm */ + Mips_CLTI_S_B /* 1201 */, MIPS_INS_CLTI_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_s.d $wd, $ws, $imm */ + Mips_CLTI_S_D /* 1202 */, MIPS_INS_CLTI_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_s.h $wd, $ws, $imm */ + Mips_CLTI_S_H /* 1203 */, MIPS_INS_CLTI_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_s.w $wd, $ws, $imm */ + Mips_CLTI_S_W /* 1204 */, MIPS_INS_CLTI_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_u.b $wd, $ws, $imm */ + Mips_CLTI_U_B /* 1205 */, MIPS_INS_CLTI_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_u.d $wd, $ws, $imm */ + Mips_CLTI_U_D /* 1206 */, MIPS_INS_CLTI_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_u.h $wd, $ws, $imm */ + Mips_CLTI_U_H /* 1207 */, MIPS_INS_CLTI_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_u.w $wd, $ws, $imm */ + Mips_CLTI_U_W /* 1208 */, MIPS_INS_CLTI_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_s.b $wd, $ws, $wt */ + Mips_CLT_S_B /* 1209 */, MIPS_INS_CLT_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_s.d $wd, $ws, $wt */ + Mips_CLT_S_D /* 1210 */, MIPS_INS_CLT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_s.h $wd, $ws, $wt */ + Mips_CLT_S_H /* 1211 */, MIPS_INS_CLT_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_s.w $wd, $ws, $wt */ + Mips_CLT_S_W /* 1212 */, MIPS_INS_CLT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_u.b $wd, $ws, $wt */ + Mips_CLT_U_B /* 1213 */, MIPS_INS_CLT_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_u.d $wd, $ws, $wt */ + Mips_CLT_U_D /* 1214 */, MIPS_INS_CLT_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_u.h $wd, $ws, $wt */ + Mips_CLT_U_H /* 1215 */, MIPS_INS_CLT_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_u.w $wd, $ws, $wt */ + Mips_CLT_U_W /* 1216 */, MIPS_INS_CLT_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clz $rd, $rs */ + Mips_CLZ /* 1217 */, MIPS_INS_CLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clz $rd, $rs */ + Mips_CLZ_MM /* 1218 */, MIPS_INS_CLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clz $rt, $rs */ + Mips_CLZ_MMR6 /* 1219 */, MIPS_INS_CLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clz $rt, $rs */ + Mips_CLZ_NM /* 1220 */, MIPS_INS_CLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clz $rd, $rs */ + Mips_CLZ_R6 /* 1221 */, MIPS_INS_CLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgdu.eq.qb $rd, $rs, $rt */ + Mips_CMPGDU_EQ_QB /* 1222 */, MIPS_INS_CMPGDU_EQ_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgdu.eq.qb $rd, $rs, $rt */ + Mips_CMPGDU_EQ_QB_MMR2 /* 1223 */, MIPS_INS_CMPGDU_EQ_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgdu.le.qb $rd, $rs, $rt */ + Mips_CMPGDU_LE_QB /* 1224 */, MIPS_INS_CMPGDU_LE_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgdu.le.qb $rd, $rs, $rt */ + Mips_CMPGDU_LE_QB_MMR2 /* 1225 */, MIPS_INS_CMPGDU_LE_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgdu.lt.qb $rd, $rs, $rt */ + Mips_CMPGDU_LT_QB /* 1226 */, MIPS_INS_CMPGDU_LT_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgdu.lt.qb $rd, $rs, $rt */ + Mips_CMPGDU_LT_QB_MMR2 /* 1227 */, MIPS_INS_CMPGDU_LT_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgu.eq.qb $rd, $rs, $rt */ + Mips_CMPGU_EQ_QB /* 1228 */, MIPS_INS_CMPGU_EQ_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgu.eq.qb $rd, $rs, $rt */ + Mips_CMPGU_EQ_QB_MM /* 1229 */, MIPS_INS_CMPGU_EQ_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgu.le.qb $rd, $rs, $rt */ + Mips_CMPGU_LE_QB /* 1230 */, MIPS_INS_CMPGU_LE_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgu.le.qb $rd, $rs, $rt */ + Mips_CMPGU_LE_QB_MM /* 1231 */, MIPS_INS_CMPGU_LE_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgu.lt.qb $rd, $rs, $rt */ + Mips_CMPGU_LT_QB /* 1232 */, MIPS_INS_CMPGU_LT_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgu.lt.qb $rd, $rs, $rt */ + Mips_CMPGU_LT_QB_MM /* 1233 */, MIPS_INS_CMPGU_LT_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpu.eq.qb $rs, $rt */ + Mips_CMPU_EQ_QB /* 1234 */, MIPS_INS_CMPU_EQ_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpu.eq.qb $rs, $rt */ + Mips_CMPU_EQ_QB_MM /* 1235 */, MIPS_INS_CMPU_EQ_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpu.le.qb $rs, $rt */ + Mips_CMPU_LE_QB /* 1236 */, MIPS_INS_CMPU_LE_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpu.le.qb $rs, $rt */ + Mips_CMPU_LE_QB_MM /* 1237 */, MIPS_INS_CMPU_LE_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpu.lt.qb $rs, $rt */ + Mips_CMPU_LT_QB /* 1238 */, MIPS_INS_CMPU_LT_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpu.lt.qb $rs, $rt */ + Mips_CMPU_LT_QB_MM /* 1239 */, MIPS_INS_CMPU_LT_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.af.d $fd, $fs, $ft */ + Mips_CMP_AF_D_MMR6 /* 1240 */, MIPS_INS_CMP_AF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.af.s $fd, $fs, $ft */ + Mips_CMP_AF_S_MMR6 /* 1241 */, MIPS_INS_CMP_AF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.eq.d $fd, $fs, $ft */ + Mips_CMP_EQ_D /* 1242 */, MIPS_INS_CMP_EQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.eq.d $fd, $fs, $ft */ + Mips_CMP_EQ_D_MMR6 /* 1243 */, MIPS_INS_CMP_EQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.eq.ph $rs, $rt */ + Mips_CMP_EQ_PH /* 1244 */, MIPS_INS_CMP_EQ_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.eq.ph $rs, $rt */ + Mips_CMP_EQ_PH_MM /* 1245 */, MIPS_INS_CMP_EQ_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.eq.s $fd, $fs, $ft */ + Mips_CMP_EQ_S /* 1246 */, MIPS_INS_CMP_EQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.eq.s $fd, $fs, $ft */ + Mips_CMP_EQ_S_MMR6 /* 1247 */, MIPS_INS_CMP_EQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.af.d $fd, $fs, $ft */ + Mips_CMP_F_D /* 1248 */, MIPS_INS_CMP_AF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.af.s $fd, $fs, $ft */ + Mips_CMP_F_S /* 1249 */, MIPS_INS_CMP_AF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.le.d $fd, $fs, $ft */ + Mips_CMP_LE_D /* 1250 */, MIPS_INS_CMP_LE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.le.d $fd, $fs, $ft */ + Mips_CMP_LE_D_MMR6 /* 1251 */, MIPS_INS_CMP_LE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.le.ph $rs, $rt */ + Mips_CMP_LE_PH /* 1252 */, MIPS_INS_CMP_LE_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.le.ph $rs, $rt */ + Mips_CMP_LE_PH_MM /* 1253 */, MIPS_INS_CMP_LE_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.le.s $fd, $fs, $ft */ + Mips_CMP_LE_S /* 1254 */, MIPS_INS_CMP_LE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.le.s $fd, $fs, $ft */ + Mips_CMP_LE_S_MMR6 /* 1255 */, MIPS_INS_CMP_LE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.lt.d $fd, $fs, $ft */ + Mips_CMP_LT_D /* 1256 */, MIPS_INS_CMP_LT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.lt.d $fd, $fs, $ft */ + Mips_CMP_LT_D_MMR6 /* 1257 */, MIPS_INS_CMP_LT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.lt.ph $rs, $rt */ + Mips_CMP_LT_PH /* 1258 */, MIPS_INS_CMP_LT_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.lt.ph $rs, $rt */ + Mips_CMP_LT_PH_MM /* 1259 */, MIPS_INS_CMP_LT_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.lt.s $fd, $fs, $ft */ + Mips_CMP_LT_S /* 1260 */, MIPS_INS_CMP_LT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.lt.s $fd, $fs, $ft */ + Mips_CMP_LT_S_MMR6 /* 1261 */, MIPS_INS_CMP_LT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.saf.d $fd, $fs, $ft */ + Mips_CMP_SAF_D /* 1262 */, MIPS_INS_CMP_SAF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.saf.d $fd, $fs, $ft */ + Mips_CMP_SAF_D_MMR6 /* 1263 */, MIPS_INS_CMP_SAF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.saf.s $fd, $fs, $ft */ + Mips_CMP_SAF_S /* 1264 */, MIPS_INS_CMP_SAF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.saf.s $fd, $fs, $ft */ + Mips_CMP_SAF_S_MMR6 /* 1265 */, MIPS_INS_CMP_SAF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.seq.d $fd, $fs, $ft */ + Mips_CMP_SEQ_D /* 1266 */, MIPS_INS_CMP_SEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.seq.d $fd, $fs, $ft */ + Mips_CMP_SEQ_D_MMR6 /* 1267 */, MIPS_INS_CMP_SEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.seq.s $fd, $fs, $ft */ + Mips_CMP_SEQ_S /* 1268 */, MIPS_INS_CMP_SEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.seq.s $fd, $fs, $ft */ + Mips_CMP_SEQ_S_MMR6 /* 1269 */, MIPS_INS_CMP_SEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sle.d $fd, $fs, $ft */ + Mips_CMP_SLE_D /* 1270 */, MIPS_INS_CMP_SLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sle.d $fd, $fs, $ft */ + Mips_CMP_SLE_D_MMR6 /* 1271 */, MIPS_INS_CMP_SLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sle.s $fd, $fs, $ft */ + Mips_CMP_SLE_S /* 1272 */, MIPS_INS_CMP_SLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sle.s $fd, $fs, $ft */ + Mips_CMP_SLE_S_MMR6 /* 1273 */, MIPS_INS_CMP_SLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.slt.d $fd, $fs, $ft */ + Mips_CMP_SLT_D /* 1274 */, MIPS_INS_CMP_SLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.slt.d $fd, $fs, $ft */ + Mips_CMP_SLT_D_MMR6 /* 1275 */, MIPS_INS_CMP_SLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.slt.s $fd, $fs, $ft */ + Mips_CMP_SLT_S /* 1276 */, MIPS_INS_CMP_SLT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.slt.s $fd, $fs, $ft */ + Mips_CMP_SLT_S_MMR6 /* 1277 */, MIPS_INS_CMP_SLT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sueq.d $fd, $fs, $ft */ + Mips_CMP_SUEQ_D /* 1278 */, MIPS_INS_CMP_SUEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sueq.d $fd, $fs, $ft */ + Mips_CMP_SUEQ_D_MMR6 /* 1279 */, MIPS_INS_CMP_SUEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sueq.s $fd, $fs, $ft */ + Mips_CMP_SUEQ_S /* 1280 */, MIPS_INS_CMP_SUEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sueq.s $fd, $fs, $ft */ + Mips_CMP_SUEQ_S_MMR6 /* 1281 */, MIPS_INS_CMP_SUEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sule.d $fd, $fs, $ft */ + Mips_CMP_SULE_D /* 1282 */, MIPS_INS_CMP_SULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sule.d $fd, $fs, $ft */ + Mips_CMP_SULE_D_MMR6 /* 1283 */, MIPS_INS_CMP_SULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sule.s $fd, $fs, $ft */ + Mips_CMP_SULE_S /* 1284 */, MIPS_INS_CMP_SULE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sule.s $fd, $fs, $ft */ + Mips_CMP_SULE_S_MMR6 /* 1285 */, MIPS_INS_CMP_SULE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sult.d $fd, $fs, $ft */ + Mips_CMP_SULT_D /* 1286 */, MIPS_INS_CMP_SULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sult.d $fd, $fs, $ft */ + Mips_CMP_SULT_D_MMR6 /* 1287 */, MIPS_INS_CMP_SULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sult.s $fd, $fs, $ft */ + Mips_CMP_SULT_S /* 1288 */, MIPS_INS_CMP_SULT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sult.s $fd, $fs, $ft */ + Mips_CMP_SULT_S_MMR6 /* 1289 */, MIPS_INS_CMP_SULT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sun.d $fd, $fs, $ft */ + Mips_CMP_SUN_D /* 1290 */, MIPS_INS_CMP_SUN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sun.d $fd, $fs, $ft */ + Mips_CMP_SUN_D_MMR6 /* 1291 */, MIPS_INS_CMP_SUN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sun.s $fd, $fs, $ft */ + Mips_CMP_SUN_S /* 1292 */, MIPS_INS_CMP_SUN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sun.s $fd, $fs, $ft */ + Mips_CMP_SUN_S_MMR6 /* 1293 */, MIPS_INS_CMP_SUN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ueq.d $fd, $fs, $ft */ + Mips_CMP_UEQ_D /* 1294 */, MIPS_INS_CMP_UEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ueq.d $fd, $fs, $ft */ + Mips_CMP_UEQ_D_MMR6 /* 1295 */, MIPS_INS_CMP_UEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ueq.s $fd, $fs, $ft */ + Mips_CMP_UEQ_S /* 1296 */, MIPS_INS_CMP_UEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ueq.s $fd, $fs, $ft */ + Mips_CMP_UEQ_S_MMR6 /* 1297 */, MIPS_INS_CMP_UEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ule.d $fd, $fs, $ft */ + Mips_CMP_ULE_D /* 1298 */, MIPS_INS_CMP_ULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ule.d $fd, $fs, $ft */ + Mips_CMP_ULE_D_MMR6 /* 1299 */, MIPS_INS_CMP_ULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ule.s $fd, $fs, $ft */ + Mips_CMP_ULE_S /* 1300 */, MIPS_INS_CMP_ULE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ule.s $fd, $fs, $ft */ + Mips_CMP_ULE_S_MMR6 /* 1301 */, MIPS_INS_CMP_ULE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ult.d $fd, $fs, $ft */ + Mips_CMP_ULT_D /* 1302 */, MIPS_INS_CMP_ULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ult.d $fd, $fs, $ft */ + Mips_CMP_ULT_D_MMR6 /* 1303 */, MIPS_INS_CMP_ULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ult.s $fd, $fs, $ft */ + Mips_CMP_ULT_S /* 1304 */, MIPS_INS_CMP_ULT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ult.s $fd, $fs, $ft */ + Mips_CMP_ULT_S_MMR6 /* 1305 */, MIPS_INS_CMP_ULT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.un.d $fd, $fs, $ft */ + Mips_CMP_UN_D /* 1306 */, MIPS_INS_CMP_UN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.un.d $fd, $fs, $ft */ + Mips_CMP_UN_D_MMR6 /* 1307 */, MIPS_INS_CMP_UN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.un.s $fd, $fs, $ft */ + Mips_CMP_UN_S /* 1308 */, MIPS_INS_CMP_UN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.un.s $fd, $fs, $ft */ + Mips_CMP_UN_S_MMR6 /* 1309 */, MIPS_INS_CMP_UN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_s.b $rd, $ws[$n] */ + Mips_COPY_S_B /* 1310 */, MIPS_INS_COPY_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_s.d $rd, $ws[$n] */ + Mips_COPY_S_D /* 1311 */, MIPS_INS_COPY_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_s.h $rd, $ws[$n] */ + Mips_COPY_S_H /* 1312 */, MIPS_INS_COPY_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_s.w $rd, $ws[$n] */ + Mips_COPY_S_W /* 1313 */, MIPS_INS_COPY_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_u.b $rd, $ws[$n] */ + Mips_COPY_U_B /* 1314 */, MIPS_INS_COPY_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_u.h $rd, $ws[$n] */ + Mips_COPY_U_H /* 1315 */, MIPS_INS_COPY_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_u.w $rd, $ws[$n] */ + Mips_COPY_U_W /* 1316 */, MIPS_INS_COPY_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32b $rd, $rs, $rt */ + Mips_CRC32B /* 1317 */, MIPS_INS_CRC32B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32b $rt, $rs */ + Mips_CRC32B_NM /* 1318 */, MIPS_INS_CRC32B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASCRC, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32cb $rd, $rs, $rt */ + Mips_CRC32CB /* 1319 */, MIPS_INS_CRC32CB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32cb $rt, $rs */ + Mips_CRC32CB_NM /* 1320 */, MIPS_INS_CRC32CB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASCRC, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32cd $rd, $rs, $rt */ + Mips_CRC32CD /* 1321 */, MIPS_INS_CRC32CD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32ch $rd, $rs, $rt */ + Mips_CRC32CH /* 1322 */, MIPS_INS_CRC32CH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32ch $rt, $rs */ + Mips_CRC32CH_NM /* 1323 */, MIPS_INS_CRC32CH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASCRC, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32cw $rd, $rs, $rt */ + Mips_CRC32CW /* 1324 */, MIPS_INS_CRC32CW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32cw $rt, $rs */ + Mips_CRC32CW_NM /* 1325 */, MIPS_INS_CRC32CW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASCRC, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32d $rd, $rs, $rt */ + Mips_CRC32D /* 1326 */, MIPS_INS_CRC32D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32h $rd, $rs, $rt */ + Mips_CRC32H /* 1327 */, MIPS_INS_CRC32H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32h $rt, $rs */ + Mips_CRC32H_NM /* 1328 */, MIPS_INS_CRC32H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASCRC, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32w $rd, $rs, $rt */ + Mips_CRC32W /* 1329 */, MIPS_INS_CRC32W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32w $rt, $rs */ + Mips_CRC32W_NM /* 1330 */, MIPS_INS_CRC32W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASCRC, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ctc1 $rt, $fs */ + Mips_CTC1 /* 1331 */, MIPS_INS_CTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ctc1 $rt, $fs */ + Mips_CTC1_MM /* 1332 */, MIPS_INS_CTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ctc2 $rt, $impl */ + Mips_CTC2_MM /* 1333 */, MIPS_INS_CTC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ctcmsa $cd, $rs */ + Mips_CTCMSA /* 1334 */, MIPS_INS_CTCMSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.s $fd, $fs */ + Mips_CVT_D32_S /* 1335 */, MIPS_INS_CVT_D_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.s $fd, $fs */ + Mips_CVT_D32_S_MM /* 1336 */, MIPS_INS_CVT_D_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.w $fd, $fs */ + Mips_CVT_D32_W /* 1337 */, MIPS_INS_CVT_D_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.w $fd, $fs */ + Mips_CVT_D32_W_MM /* 1338 */, MIPS_INS_CVT_D_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.l $fd, $fs */ + Mips_CVT_D64_L /* 1339 */, MIPS_INS_CVT_D_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS3_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.s $fd, $fs */ + Mips_CVT_D64_S /* 1340 */, MIPS_INS_CVT_D_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.s $fd, $fs */ + Mips_CVT_D64_S_MM /* 1341 */, MIPS_INS_CVT_D_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.w $fd, $fs */ + Mips_CVT_D64_W /* 1342 */, MIPS_INS_CVT_D_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.w $fd, $fs */ + Mips_CVT_D64_W_MM /* 1343 */, MIPS_INS_CVT_D_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.l $ft, $fs */ + Mips_CVT_D_L_MMR6 /* 1344 */, MIPS_INS_CVT_D_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.l.d $fd, $fs */ + Mips_CVT_L_D64 /* 1345 */, MIPS_INS_CVT_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.l.d $fd, $fs */ + Mips_CVT_L_D64_MM /* 1346 */, MIPS_INS_CVT_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.l.d $ft, $fs */ + Mips_CVT_L_D_MMR6 /* 1347 */, MIPS_INS_CVT_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.l.s $fd, $fs */ + Mips_CVT_L_S /* 1348 */, MIPS_INS_CVT_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.l.s $fd, $fs */ + Mips_CVT_L_S_MM /* 1349 */, MIPS_INS_CVT_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.l.s $ft, $fs */ + Mips_CVT_L_S_MMR6 /* 1350 */, MIPS_INS_CVT_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.ps.pw $fd, $fs */ + Mips_CVT_PS_PW64 /* 1351 */, MIPS_INS_CVT_PS_PW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMIPS3D, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.ps.s $fd, $fs, $ft */ + Mips_CVT_PS_S64 /* 1352 */, MIPS_INS_CVT_PS_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.pw.ps $fd, $fs */ + Mips_CVT_PW_PS64 /* 1353 */, MIPS_INS_CVT_PW_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMIPS3D, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.d $fd, $fs */ + Mips_CVT_S_D32 /* 1354 */, MIPS_INS_CVT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.d $fd, $fs */ + Mips_CVT_S_D32_MM /* 1355 */, MIPS_INS_CVT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.d $fd, $fs */ + Mips_CVT_S_D64 /* 1356 */, MIPS_INS_CVT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.d $fd, $fs */ + Mips_CVT_S_D64_MM /* 1357 */, MIPS_INS_CVT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.l $fd, $fs */ + Mips_CVT_S_L /* 1358 */, MIPS_INS_CVT_S_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS3_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.l $ft, $fs */ + Mips_CVT_S_L_MMR6 /* 1359 */, MIPS_INS_CVT_S_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.pl $fd, $fs */ + Mips_CVT_S_PL64 /* 1360 */, MIPS_INS_CVT_S_PL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.pu $fd, $fs */ + Mips_CVT_S_PU64 /* 1361 */, MIPS_INS_CVT_S_PU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.w $fd, $fs */ + Mips_CVT_S_W /* 1362 */, MIPS_INS_CVT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.w $fd, $fs */ + Mips_CVT_S_W_MM /* 1363 */, MIPS_INS_CVT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.w $ft, $fs */ + Mips_CVT_S_W_MMR6 /* 1364 */, MIPS_INS_CVT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.d $fd, $fs */ + Mips_CVT_W_D32 /* 1365 */, MIPS_INS_CVT_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.d $fd, $fs */ + Mips_CVT_W_D32_MM /* 1366 */, MIPS_INS_CVT_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.d $fd, $fs */ + Mips_CVT_W_D64 /* 1367 */, MIPS_INS_CVT_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.d $fd, $fs */ + Mips_CVT_W_D64_MM /* 1368 */, MIPS_INS_CVT_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.s $fd, $fs */ + Mips_CVT_W_S /* 1369 */, MIPS_INS_CVT_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.s $fd, $fs */ + Mips_CVT_W_S_MM /* 1370 */, MIPS_INS_CVT_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.s $ft, $fs */ + Mips_CVT_W_S_MMR6 /* 1371 */, MIPS_INS_CVT_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.eq.d $fcc, $fs, $ft */ + Mips_C_EQ_D32 /* 1372 */, MIPS_INS_C_EQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.eq.d $fcc, $fs, $ft */ + Mips_C_EQ_D32_MM /* 1373 */, MIPS_INS_C_EQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.eq.d $fcc, $fs, $ft */ + Mips_C_EQ_D64 /* 1374 */, MIPS_INS_C_EQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.eq.d $fcc, $fs, $ft */ + Mips_C_EQ_D64_MM /* 1375 */, MIPS_INS_C_EQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.eq.s $fcc, $fs, $ft */ + Mips_C_EQ_S /* 1376 */, MIPS_INS_C_EQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.eq.s $fcc, $fs, $ft */ + Mips_C_EQ_S_MM /* 1377 */, MIPS_INS_C_EQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.f.d $fcc, $fs, $ft */ + Mips_C_F_D32 /* 1378 */, MIPS_INS_C_F_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.f.d $fcc, $fs, $ft */ + Mips_C_F_D32_MM /* 1379 */, MIPS_INS_C_F_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.f.d $fcc, $fs, $ft */ + Mips_C_F_D64 /* 1380 */, MIPS_INS_C_F_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.f.d $fcc, $fs, $ft */ + Mips_C_F_D64_MM /* 1381 */, MIPS_INS_C_F_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.f.s $fcc, $fs, $ft */ + Mips_C_F_S /* 1382 */, MIPS_INS_C_F_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.f.s $fcc, $fs, $ft */ + Mips_C_F_S_MM /* 1383 */, MIPS_INS_C_F_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.le.d $fcc, $fs, $ft */ + Mips_C_LE_D32 /* 1384 */, MIPS_INS_C_LE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.le.d $fcc, $fs, $ft */ + Mips_C_LE_D32_MM /* 1385 */, MIPS_INS_C_LE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.le.d $fcc, $fs, $ft */ + Mips_C_LE_D64 /* 1386 */, MIPS_INS_C_LE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.le.d $fcc, $fs, $ft */ + Mips_C_LE_D64_MM /* 1387 */, MIPS_INS_C_LE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.le.s $fcc, $fs, $ft */ + Mips_C_LE_S /* 1388 */, MIPS_INS_C_LE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.le.s $fcc, $fs, $ft */ + Mips_C_LE_S_MM /* 1389 */, MIPS_INS_C_LE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.lt.d $fcc, $fs, $ft */ + Mips_C_LT_D32 /* 1390 */, MIPS_INS_C_LT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.lt.d $fcc, $fs, $ft */ + Mips_C_LT_D32_MM /* 1391 */, MIPS_INS_C_LT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.lt.d $fcc, $fs, $ft */ + Mips_C_LT_D64 /* 1392 */, MIPS_INS_C_LT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.lt.d $fcc, $fs, $ft */ + Mips_C_LT_D64_MM /* 1393 */, MIPS_INS_C_LT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.lt.s $fcc, $fs, $ft */ + Mips_C_LT_S /* 1394 */, MIPS_INS_C_LT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.lt.s $fcc, $fs, $ft */ + Mips_C_LT_S_MM /* 1395 */, MIPS_INS_C_LT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.nge.d $fcc, $fs, $ft */ + Mips_C_NGE_D32 /* 1396 */, MIPS_INS_C_NGE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.nge.d $fcc, $fs, $ft */ + Mips_C_NGE_D32_MM /* 1397 */, MIPS_INS_C_NGE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.nge.d $fcc, $fs, $ft */ + Mips_C_NGE_D64 /* 1398 */, MIPS_INS_C_NGE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.nge.d $fcc, $fs, $ft */ + Mips_C_NGE_D64_MM /* 1399 */, MIPS_INS_C_NGE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.nge.s $fcc, $fs, $ft */ + Mips_C_NGE_S /* 1400 */, MIPS_INS_C_NGE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.nge.s $fcc, $fs, $ft */ + Mips_C_NGE_S_MM /* 1401 */, MIPS_INS_C_NGE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngle.d $fcc, $fs, $ft */ + Mips_C_NGLE_D32 /* 1402 */, MIPS_INS_C_NGLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngle.d $fcc, $fs, $ft */ + Mips_C_NGLE_D32_MM /* 1403 */, MIPS_INS_C_NGLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngle.d $fcc, $fs, $ft */ + Mips_C_NGLE_D64 /* 1404 */, MIPS_INS_C_NGLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngle.d $fcc, $fs, $ft */ + Mips_C_NGLE_D64_MM /* 1405 */, MIPS_INS_C_NGLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngle.s $fcc, $fs, $ft */ + Mips_C_NGLE_S /* 1406 */, MIPS_INS_C_NGLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngle.s $fcc, $fs, $ft */ + Mips_C_NGLE_S_MM /* 1407 */, MIPS_INS_C_NGLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngl.d $fcc, $fs, $ft */ + Mips_C_NGL_D32 /* 1408 */, MIPS_INS_C_NGL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngl.d $fcc, $fs, $ft */ + Mips_C_NGL_D32_MM /* 1409 */, MIPS_INS_C_NGL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngl.d $fcc, $fs, $ft */ + Mips_C_NGL_D64 /* 1410 */, MIPS_INS_C_NGL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngl.d $fcc, $fs, $ft */ + Mips_C_NGL_D64_MM /* 1411 */, MIPS_INS_C_NGL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngl.s $fcc, $fs, $ft */ + Mips_C_NGL_S /* 1412 */, MIPS_INS_C_NGL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngl.s $fcc, $fs, $ft */ + Mips_C_NGL_S_MM /* 1413 */, MIPS_INS_C_NGL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngt.d $fcc, $fs, $ft */ + Mips_C_NGT_D32 /* 1414 */, MIPS_INS_C_NGT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngt.d $fcc, $fs, $ft */ + Mips_C_NGT_D32_MM /* 1415 */, MIPS_INS_C_NGT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngt.d $fcc, $fs, $ft */ + Mips_C_NGT_D64 /* 1416 */, MIPS_INS_C_NGT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngt.d $fcc, $fs, $ft */ + Mips_C_NGT_D64_MM /* 1417 */, MIPS_INS_C_NGT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngt.s $fcc, $fs, $ft */ + Mips_C_NGT_S /* 1418 */, MIPS_INS_C_NGT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngt.s $fcc, $fs, $ft */ + Mips_C_NGT_S_MM /* 1419 */, MIPS_INS_C_NGT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ole.d $fcc, $fs, $ft */ + Mips_C_OLE_D32 /* 1420 */, MIPS_INS_C_OLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ole.d $fcc, $fs, $ft */ + Mips_C_OLE_D32_MM /* 1421 */, MIPS_INS_C_OLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ole.d $fcc, $fs, $ft */ + Mips_C_OLE_D64 /* 1422 */, MIPS_INS_C_OLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ole.d $fcc, $fs, $ft */ + Mips_C_OLE_D64_MM /* 1423 */, MIPS_INS_C_OLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ole.s $fcc, $fs, $ft */ + Mips_C_OLE_S /* 1424 */, MIPS_INS_C_OLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ole.s $fcc, $fs, $ft */ + Mips_C_OLE_S_MM /* 1425 */, MIPS_INS_C_OLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.olt.d $fcc, $fs, $ft */ + Mips_C_OLT_D32 /* 1426 */, MIPS_INS_C_OLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.olt.d $fcc, $fs, $ft */ + Mips_C_OLT_D32_MM /* 1427 */, MIPS_INS_C_OLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.olt.d $fcc, $fs, $ft */ + Mips_C_OLT_D64 /* 1428 */, MIPS_INS_C_OLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.olt.d $fcc, $fs, $ft */ + Mips_C_OLT_D64_MM /* 1429 */, MIPS_INS_C_OLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.olt.s $fcc, $fs, $ft */ + Mips_C_OLT_S /* 1430 */, MIPS_INS_C_OLT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.olt.s $fcc, $fs, $ft */ + Mips_C_OLT_S_MM /* 1431 */, MIPS_INS_C_OLT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.seq.d $fcc, $fs, $ft */ + Mips_C_SEQ_D32 /* 1432 */, MIPS_INS_C_SEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.seq.d $fcc, $fs, $ft */ + Mips_C_SEQ_D32_MM /* 1433 */, MIPS_INS_C_SEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.seq.d $fcc, $fs, $ft */ + Mips_C_SEQ_D64 /* 1434 */, MIPS_INS_C_SEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.seq.d $fcc, $fs, $ft */ + Mips_C_SEQ_D64_MM /* 1435 */, MIPS_INS_C_SEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.seq.s $fcc, $fs, $ft */ + Mips_C_SEQ_S /* 1436 */, MIPS_INS_C_SEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.seq.s $fcc, $fs, $ft */ + Mips_C_SEQ_S_MM /* 1437 */, MIPS_INS_C_SEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.sf.d $fcc, $fs, $ft */ + Mips_C_SF_D32 /* 1438 */, MIPS_INS_C_SF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.sf.d $fcc, $fs, $ft */ + Mips_C_SF_D32_MM /* 1439 */, MIPS_INS_C_SF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.sf.d $fcc, $fs, $ft */ + Mips_C_SF_D64 /* 1440 */, MIPS_INS_C_SF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.sf.d $fcc, $fs, $ft */ + Mips_C_SF_D64_MM /* 1441 */, MIPS_INS_C_SF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.sf.s $fcc, $fs, $ft */ + Mips_C_SF_S /* 1442 */, MIPS_INS_C_SF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.sf.s $fcc, $fs, $ft */ + Mips_C_SF_S_MM /* 1443 */, MIPS_INS_C_SF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ueq.d $fcc, $fs, $ft */ + Mips_C_UEQ_D32 /* 1444 */, MIPS_INS_C_UEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ueq.d $fcc, $fs, $ft */ + Mips_C_UEQ_D32_MM /* 1445 */, MIPS_INS_C_UEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ueq.d $fcc, $fs, $ft */ + Mips_C_UEQ_D64 /* 1446 */, MIPS_INS_C_UEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ueq.d $fcc, $fs, $ft */ + Mips_C_UEQ_D64_MM /* 1447 */, MIPS_INS_C_UEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ueq.s $fcc, $fs, $ft */ + Mips_C_UEQ_S /* 1448 */, MIPS_INS_C_UEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ueq.s $fcc, $fs, $ft */ + Mips_C_UEQ_S_MM /* 1449 */, MIPS_INS_C_UEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ule.d $fcc, $fs, $ft */ + Mips_C_ULE_D32 /* 1450 */, MIPS_INS_C_ULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ule.d $fcc, $fs, $ft */ + Mips_C_ULE_D32_MM /* 1451 */, MIPS_INS_C_ULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ule.d $fcc, $fs, $ft */ + Mips_C_ULE_D64 /* 1452 */, MIPS_INS_C_ULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ule.d $fcc, $fs, $ft */ + Mips_C_ULE_D64_MM /* 1453 */, MIPS_INS_C_ULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ule.s $fcc, $fs, $ft */ + Mips_C_ULE_S /* 1454 */, MIPS_INS_C_ULE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ule.s $fcc, $fs, $ft */ + Mips_C_ULE_S_MM /* 1455 */, MIPS_INS_C_ULE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ult.d $fcc, $fs, $ft */ + Mips_C_ULT_D32 /* 1456 */, MIPS_INS_C_ULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ult.d $fcc, $fs, $ft */ + Mips_C_ULT_D32_MM /* 1457 */, MIPS_INS_C_ULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ult.d $fcc, $fs, $ft */ + Mips_C_ULT_D64 /* 1458 */, MIPS_INS_C_ULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ult.d $fcc, $fs, $ft */ + Mips_C_ULT_D64_MM /* 1459 */, MIPS_INS_C_ULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ult.s $fcc, $fs, $ft */ + Mips_C_ULT_S /* 1460 */, MIPS_INS_C_ULT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ult.s $fcc, $fs, $ft */ + Mips_C_ULT_S_MM /* 1461 */, MIPS_INS_C_ULT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.un.d $fcc, $fs, $ft */ + Mips_C_UN_D32 /* 1462 */, MIPS_INS_C_UN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.un.d $fcc, $fs, $ft */ + Mips_C_UN_D32_MM /* 1463 */, MIPS_INS_C_UN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.un.d $fcc, $fs, $ft */ + Mips_C_UN_D64 /* 1464 */, MIPS_INS_C_UN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.un.d $fcc, $fs, $ft */ + Mips_C_UN_D64_MM /* 1465 */, MIPS_INS_C_UN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.un.s $fcc, $fs, $ft */ + Mips_C_UN_S /* 1466 */, MIPS_INS_C_UN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.un.s $fcc, $fs, $ft */ + Mips_C_UN_S_MM /* 1467 */, MIPS_INS_C_UN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp $rx, $ry */ + Mips_CmpRxRy16 /* 1468 */, MIPS_INS_CMP, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpi $rx, $imm8 # 16 bit inst */ + Mips_CmpiRxImm16 /* 1469 */, MIPS_INS_CMPI, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpi $rx, $imm16 */ + Mips_CmpiRxImmX16 /* 1470 */, MIPS_INS_CMPI, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dadd $rd, $rs, $rt */ + Mips_DADD /* 1471 */, MIPS_INS_DADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* daddi $rt, $rs, $imm16 */ + Mips_DADDi /* 1472 */, MIPS_INS_DADDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* daddiu $rt, $rs, $imm16 */ + Mips_DADDiu /* 1473 */, MIPS_INS_DADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* daddu $rd, $rs, $rt */ + Mips_DADDu /* 1474 */, MIPS_INS_DADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dahi $rs, $rt, $imm */ + Mips_DAHI /* 1475 */, MIPS_INS_DAHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dalign $rd, $rs, $rt, $bp */ + Mips_DALIGN /* 1476 */, MIPS_INS_DALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dati $rs, $rt, $imm */ + Mips_DATI /* 1477 */, MIPS_INS_DATI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* daui $rt, $rs, $imm */ + Mips_DAUI /* 1478 */, MIPS_INS_DAUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dbitswap $rd, $rt */ + Mips_DBITSWAP /* 1479 */, MIPS_INS_DBITSWAP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dclo $rd, $rs */ + Mips_DCLO /* 1480 */, MIPS_INS_DCLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dclo $rd, $rs */ + Mips_DCLO_R6 /* 1481 */, MIPS_INS_DCLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dclz $rd, $rs */ + Mips_DCLZ /* 1482 */, MIPS_INS_DCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dclz $rd, $rs */ + Mips_DCLZ_R6 /* 1483 */, MIPS_INS_DCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddiv $rd, $rs, $rt */ + Mips_DDIV /* 1484 */, MIPS_INS_DDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddivu $rd, $rs, $rt */ + Mips_DDIVU /* 1485 */, MIPS_INS_DDIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* deret */ + Mips_DERET /* 1486 */, MIPS_INS_DERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* deret */ + Mips_DERET_MM /* 1487 */, MIPS_INS_DERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* deret */ + Mips_DERET_MMR6 /* 1488 */, MIPS_INS_DERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* deret */ + Mips_DERET_NM /* 1489 */, MIPS_INS_DERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dext $rt, $rs, $pos, $size */ + Mips_DEXT /* 1490 */, MIPS_INS_DEXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dext $rt, $rs, $pos, $size */ + Mips_DEXT64_32 /* 1491 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* dextm $rt, $rs, $pos, $size */ + Mips_DEXTM /* 1492 */, MIPS_INS_DEXTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dextu $rt, $rs, $pos, $size */ + Mips_DEXTU /* 1493 */, MIPS_INS_DEXTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* di $rt */ + Mips_DI /* 1494 */, MIPS_INS_DI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dins $rt, $rs, $pos, $size */ + Mips_DINS /* 1495 */, MIPS_INS_DINS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dinsm $rt, $rs, $pos, $size */ + Mips_DINSM /* 1496 */, MIPS_INS_DINSM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dinsu $rt, $rs, $pos, $size */ + Mips_DINSU /* 1497 */, MIPS_INS_DINSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $rd, $rs, $rt */ + Mips_DIV /* 1498 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $rd, $rs, $rt */ + Mips_DIVU /* 1499 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $rd, $rs, $rt */ + Mips_DIVU_MMR6 /* 1500 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $rd, $rs, $rt */ + Mips_DIVU_NM /* 1501 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $rd, $rs, $rt */ + Mips_DIV_MMR6 /* 1502 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $rd, $rs, $rt */ + Mips_DIV_NM /* 1503 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_s.b $wd, $ws, $wt */ + Mips_DIV_S_B /* 1504 */, MIPS_INS_DIV_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_s.d $wd, $ws, $wt */ + Mips_DIV_S_D /* 1505 */, MIPS_INS_DIV_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_s.h $wd, $ws, $wt */ + Mips_DIV_S_H /* 1506 */, MIPS_INS_DIV_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_s.w $wd, $ws, $wt */ + Mips_DIV_S_W /* 1507 */, MIPS_INS_DIV_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_u.b $wd, $ws, $wt */ + Mips_DIV_U_B /* 1508 */, MIPS_INS_DIV_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_u.d $wd, $ws, $wt */ + Mips_DIV_U_D /* 1509 */, MIPS_INS_DIV_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_u.h $wd, $ws, $wt */ + Mips_DIV_U_H /* 1510 */, MIPS_INS_DIV_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_u.w $wd, $ws, $wt */ + Mips_DIV_U_W /* 1511 */, MIPS_INS_DIV_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* di $rt */ + Mips_DI_MM /* 1512 */, MIPS_INS_DI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* di $rt */ + Mips_DI_MMR6 /* 1513 */, MIPS_INS_DI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* di $rt */ + Mips_DI_NM /* 1514 */, MIPS_INS_DI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dlsa $rd, $rs, $rt, $sa */ + Mips_DLSA /* 1515 */, MIPS_INS_DLSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dlsa $rd, $rs, $rt, $imm2 */ + Mips_DLSA_R6 /* 1516 */, MIPS_INS_DLSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmfc0 $rt, $rd, $sel */ + Mips_DMFC0 /* 1517 */, MIPS_INS_DMFC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmfc1 $rt, $fs */ + Mips_DMFC1 /* 1518 */, MIPS_INS_DMFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmfc2 $rt, $rd, $sel */ + Mips_DMFC2 /* 1519 */, MIPS_INS_DMFC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmfc2 $rt, $imm16 */ + Mips_DMFC2_OCTEON /* 1520 */, MIPS_INS_DMFC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmfgc0 $rt, $rd, $sel */ + Mips_DMFGC0 /* 1521 */, MIPS_INS_DMFGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmod $rd, $rs, $rt */ + Mips_DMOD /* 1522 */, MIPS_INS_DMOD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmodu $rd, $rs, $rt */ + Mips_DMODU /* 1523 */, MIPS_INS_DMODU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmt $rt */ + Mips_DMT /* 1524 */, MIPS_INS_DMT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmtc0 $rt, $rd, $sel */ + Mips_DMTC0 /* 1525 */, MIPS_INS_DMTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmtc1 $rt, $fs */ + Mips_DMTC1 /* 1526 */, MIPS_INS_DMTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmtc2 $rt, $rd, $sel */ + Mips_DMTC2 /* 1527 */, MIPS_INS_DMTC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmtc2 $rt, $imm16 */ + Mips_DMTC2_OCTEON /* 1528 */, MIPS_INS_DMTC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmtgc0 $rt, $rd, $sel */ + Mips_DMTGC0 /* 1529 */, MIPS_INS_DMTGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmt $rt */ + Mips_DMT_NM /* 1530 */, MIPS_INS_DMT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmuh $rd, $rs, $rt */ + Mips_DMUH /* 1531 */, MIPS_INS_DMUH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmuhu $rd, $rs, $rt */ + Mips_DMUHU /* 1532 */, MIPS_INS_DMUHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmul $rd, $rs, $rt */ + Mips_DMUL /* 1533 */, MIPS_INS_DMUL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmult $rs, $rt */ + Mips_DMULT /* 1534 */, MIPS_INS_DMULT, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0_64, MIPS_REG_LO0_64, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmultu $rs, $rt */ + Mips_DMULTu /* 1535 */, MIPS_INS_DMULTU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0_64, MIPS_REG_LO0_64, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmulu $rd, $rs, $rt */ + Mips_DMULU /* 1536 */, MIPS_INS_DMULU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmul $rd, $rs, $rt */ + Mips_DMUL_R6 /* 1537 */, MIPS_INS_DMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dotp_s.d $wd, $ws, $wt */ + Mips_DOTP_S_D /* 1538 */, MIPS_INS_DOTP_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dotp_s.h $wd, $ws, $wt */ + Mips_DOTP_S_H /* 1539 */, MIPS_INS_DOTP_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dotp_s.w $wd, $ws, $wt */ + Mips_DOTP_S_W /* 1540 */, MIPS_INS_DOTP_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dotp_u.d $wd, $ws, $wt */ + Mips_DOTP_U_D /* 1541 */, MIPS_INS_DOTP_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dotp_u.h $wd, $ws, $wt */ + Mips_DOTP_U_H /* 1542 */, MIPS_INS_DOTP_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dotp_u.w $wd, $ws, $wt */ + Mips_DOTP_U_W /* 1543 */, MIPS_INS_DOTP_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpadd_s.d $wd, $ws, $wt */ + Mips_DPADD_S_D /* 1544 */, MIPS_INS_DPADD_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpadd_s.h $wd, $ws, $wt */ + Mips_DPADD_S_H /* 1545 */, MIPS_INS_DPADD_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpadd_s.w $wd, $ws, $wt */ + Mips_DPADD_S_W /* 1546 */, MIPS_INS_DPADD_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpadd_u.d $wd, $ws, $wt */ + Mips_DPADD_U_D /* 1547 */, MIPS_INS_DPADD_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpadd_u.h $wd, $ws, $wt */ + Mips_DPADD_U_H /* 1548 */, MIPS_INS_DPADD_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpadd_u.w $wd, $ws, $wt */ + Mips_DPADD_U_W /* 1549 */, MIPS_INS_DPADD_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaqx_sa.w.ph $ac, $rs, $rt */ + Mips_DPAQX_SA_W_PH /* 1550 */, MIPS_INS_DPAQX_SA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaqx_sa.w.ph $ac, $rs, $rt */ + Mips_DPAQX_SA_W_PH_MMR2 /* 1551 */, MIPS_INS_DPAQX_SA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaqx_s.w.ph $ac, $rs, $rt */ + Mips_DPAQX_S_W_PH /* 1552 */, MIPS_INS_DPAQX_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaqx_s.w.ph $ac, $rs, $rt */ + Mips_DPAQX_S_W_PH_MMR2 /* 1553 */, MIPS_INS_DPAQX_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaq_sa.l.w $ac, $rs, $rt */ + Mips_DPAQ_SA_L_W /* 1554 */, MIPS_INS_DPAQ_SA_L_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaq_sa.l.w $ac, $rs, $rt */ + Mips_DPAQ_SA_L_W_MM /* 1555 */, MIPS_INS_DPAQ_SA_L_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaq_s.w.ph $ac, $rs, $rt */ + Mips_DPAQ_S_W_PH /* 1556 */, MIPS_INS_DPAQ_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaq_s.w.ph $ac, $rs, $rt */ + Mips_DPAQ_S_W_PH_MM /* 1557 */, MIPS_INS_DPAQ_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpau.h.qbl $ac, $rs, $rt */ + Mips_DPAU_H_QBL /* 1558 */, MIPS_INS_DPAU_H_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpau.h.qbl $ac, $rs, $rt */ + Mips_DPAU_H_QBL_MM /* 1559 */, MIPS_INS_DPAU_H_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpau.h.qbr $ac, $rs, $rt */ + Mips_DPAU_H_QBR /* 1560 */, MIPS_INS_DPAU_H_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpau.h.qbr $ac, $rs, $rt */ + Mips_DPAU_H_QBR_MM /* 1561 */, MIPS_INS_DPAU_H_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpax.w.ph $ac, $rs, $rt */ + Mips_DPAX_W_PH /* 1562 */, MIPS_INS_DPAX_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpax.w.ph $ac, $rs, $rt */ + Mips_DPAX_W_PH_MMR2 /* 1563 */, MIPS_INS_DPAX_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpa.w.ph $ac, $rs, $rt */ + Mips_DPA_W_PH /* 1564 */, MIPS_INS_DPA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpa.w.ph $ac, $rs, $rt */ + Mips_DPA_W_PH_MMR2 /* 1565 */, MIPS_INS_DPA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpop $rd, $rs */ + Mips_DPOP /* 1566 */, MIPS_INS_DPOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsqx_sa.w.ph $ac, $rs, $rt */ + Mips_DPSQX_SA_W_PH /* 1567 */, MIPS_INS_DPSQX_SA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsqx_sa.w.ph $ac, $rs, $rt */ + Mips_DPSQX_SA_W_PH_MMR2 /* 1568 */, MIPS_INS_DPSQX_SA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsqx_s.w.ph $ac, $rs, $rt */ + Mips_DPSQX_S_W_PH /* 1569 */, MIPS_INS_DPSQX_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsqx_s.w.ph $ac, $rs, $rt */ + Mips_DPSQX_S_W_PH_MMR2 /* 1570 */, MIPS_INS_DPSQX_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsq_sa.l.w $ac, $rs, $rt */ + Mips_DPSQ_SA_L_W /* 1571 */, MIPS_INS_DPSQ_SA_L_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsq_sa.l.w $ac, $rs, $rt */ + Mips_DPSQ_SA_L_W_MM /* 1572 */, MIPS_INS_DPSQ_SA_L_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsq_s.w.ph $ac, $rs, $rt */ + Mips_DPSQ_S_W_PH /* 1573 */, MIPS_INS_DPSQ_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsq_s.w.ph $ac, $rs, $rt */ + Mips_DPSQ_S_W_PH_MM /* 1574 */, MIPS_INS_DPSQ_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsub_s.d $wd, $ws, $wt */ + Mips_DPSUB_S_D /* 1575 */, MIPS_INS_DPSUB_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsub_s.h $wd, $ws, $wt */ + Mips_DPSUB_S_H /* 1576 */, MIPS_INS_DPSUB_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsub_s.w $wd, $ws, $wt */ + Mips_DPSUB_S_W /* 1577 */, MIPS_INS_DPSUB_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsub_u.d $wd, $ws, $wt */ + Mips_DPSUB_U_D /* 1578 */, MIPS_INS_DPSUB_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsub_u.h $wd, $ws, $wt */ + Mips_DPSUB_U_H /* 1579 */, MIPS_INS_DPSUB_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsub_u.w $wd, $ws, $wt */ + Mips_DPSUB_U_W /* 1580 */, MIPS_INS_DPSUB_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsu.h.qbl $ac, $rs, $rt */ + Mips_DPSU_H_QBL /* 1581 */, MIPS_INS_DPSU_H_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsu.h.qbl $ac, $rs, $rt */ + Mips_DPSU_H_QBL_MM /* 1582 */, MIPS_INS_DPSU_H_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsu.h.qbr $ac, $rs, $rt */ + Mips_DPSU_H_QBR /* 1583 */, MIPS_INS_DPSU_H_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsu.h.qbr $ac, $rs, $rt */ + Mips_DPSU_H_QBR_MM /* 1584 */, MIPS_INS_DPSU_H_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsx.w.ph $ac, $rs, $rt */ + Mips_DPSX_W_PH /* 1585 */, MIPS_INS_DPSX_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsx.w.ph $ac, $rs, $rt */ + Mips_DPSX_W_PH_MMR2 /* 1586 */, MIPS_INS_DPSX_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dps.w.ph $ac, $rs, $rt */ + Mips_DPS_W_PH /* 1587 */, MIPS_INS_DPS_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dps.w.ph $ac, $rs, $rt */ + Mips_DPS_W_PH_MMR2 /* 1588 */, MIPS_INS_DPS_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drotr $rd, $rt, $shamt */ + Mips_DROTR /* 1589 */, MIPS_INS_DROTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drotr32 $rd, $rt, $shamt */ + Mips_DROTR32 /* 1590 */, MIPS_INS_DROTR32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drotrv $rd, $rt, $rs */ + Mips_DROTRV /* 1591 */, MIPS_INS_DROTRV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsbh $rd, $rt */ + Mips_DSBH /* 1592 */, MIPS_INS_DSBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddiv $$zero, $rs, $rt */ + Mips_DSDIV /* 1593 */, MIPS_INS_DDIV, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0_64, MIPS_REG_LO0_64, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dshd $rd, $rt */ + Mips_DSHD /* 1594 */, MIPS_INS_DSHD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsll $rd, $rt, $shamt */ + Mips_DSLL /* 1595 */, MIPS_INS_DSLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsll32 $rd, $rt, $shamt */ + Mips_DSLL32 /* 1596 */, MIPS_INS_DSLL32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsll $rd, $rt, 32 */ + Mips_DSLL64_32 /* 1597 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* dsllv $rd, $rt, $rs */ + Mips_DSLLV /* 1598 */, MIPS_INS_DSLLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsra $rd, $rt, $shamt */ + Mips_DSRA /* 1599 */, MIPS_INS_DSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsra32 $rd, $rt, $shamt */ + Mips_DSRA32 /* 1600 */, MIPS_INS_DSRA32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsrav $rd, $rt, $rs */ + Mips_DSRAV /* 1601 */, MIPS_INS_DSRAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsrl $rd, $rt, $shamt */ + Mips_DSRL /* 1602 */, MIPS_INS_DSRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsrl32 $rd, $rt, $shamt */ + Mips_DSRL32 /* 1603 */, MIPS_INS_DSRL32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsrlv $rd, $rt, $rs */ + Mips_DSRLV /* 1604 */, MIPS_INS_DSRLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsub $rd, $rs, $rt */ + Mips_DSUB /* 1605 */, MIPS_INS_DSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsubu $rd, $rs, $rt */ + Mips_DSUBu /* 1606 */, MIPS_INS_DSUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddivu $$zero, $rs, $rt */ + Mips_DUDIV /* 1607 */, MIPS_INS_DDIVU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0_64, MIPS_REG_LO0_64, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dvp $rt */ + Mips_DVP /* 1608 */, MIPS_INS_DVP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dvpe $rt */ + Mips_DVPE /* 1609 */, MIPS_INS_DVPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dvpe $rt */ + Mips_DVPE_NM /* 1610 */, MIPS_INS_DVPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dvp $rs */ + Mips_DVP_MMR6 /* 1611 */, MIPS_INS_DVP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $$zero, $rx, $ry */ + Mips_DivRxRy16 /* 1612 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $$zero, $rx, $ry */ + Mips_DivuRxRy16 /* 1613 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ehb */ + Mips_EHB /* 1614 */, MIPS_INS_EHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ehb */ + Mips_EHB_MM /* 1615 */, MIPS_INS_EHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ehb */ + Mips_EHB_MMR6 /* 1616 */, MIPS_INS_EHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ehb */ + Mips_EHB_NM /* 1617 */, MIPS_INS_EHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ei $rt */ + Mips_EI /* 1618 */, MIPS_INS_EI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ei $rt */ + Mips_EI_MM /* 1619 */, MIPS_INS_EI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ei $rt */ + Mips_EI_MMR6 /* 1620 */, MIPS_INS_EI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ei $rt */ + Mips_EI_NM /* 1621 */, MIPS_INS_EI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* emt $rt */ + Mips_EMT /* 1622 */, MIPS_INS_EMT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* emt $rt */ + Mips_EMT_NM /* 1623 */, MIPS_INS_EMT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eret */ + Mips_ERET /* 1624 */, MIPS_INS_ERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eretnc */ + Mips_ERETNC /* 1625 */, MIPS_INS_ERETNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eretnc */ + Mips_ERETNC_MMR6 /* 1626 */, MIPS_INS_ERETNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eretnc */ + Mips_ERETNC_NM /* 1627 */, MIPS_INS_ERETNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eret */ + Mips_ERET_MM /* 1628 */, MIPS_INS_ERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eret */ + Mips_ERET_MMR6 /* 1629 */, MIPS_INS_ERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eret */ + Mips_ERET_NM /* 1630 */, MIPS_INS_ERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* evp $rt */ + Mips_EVP /* 1631 */, MIPS_INS_EVP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* evpe $rt */ + Mips_EVPE /* 1632 */, MIPS_INS_EVPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* evpe $rt */ + Mips_EVPE_NM /* 1633 */, MIPS_INS_EVPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* evp $rs */ + Mips_EVP_MMR6 /* 1634 */, MIPS_INS_EVP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ext $rt, $rs, $pos, $size */ + Mips_EXT /* 1635 */, MIPS_INS_EXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extp $rt, $ac, $shift_rs */ + Mips_EXTP /* 1636 */, MIPS_INS_EXTP, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extpdp $rt, $ac, $shift_rs */ + Mips_EXTPDP /* 1637 */, MIPS_INS_EXTPDP, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extpdpv $rt, $ac, $shift_rs */ + Mips_EXTPDPV /* 1638 */, MIPS_INS_EXTPDPV, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extpdpv $rt, $ac, $rs */ + Mips_EXTPDPV_MM /* 1639 */, MIPS_INS_EXTPDPV, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extpdp $rt, $ac, $imm */ + Mips_EXTPDP_MM /* 1640 */, MIPS_INS_EXTPDP, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extpv $rt, $ac, $shift_rs */ + Mips_EXTPV /* 1641 */, MIPS_INS_EXTPV, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extpv $rt, $ac, $rs */ + Mips_EXTPV_MM /* 1642 */, MIPS_INS_EXTPV, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extp $rt, $ac, $imm */ + Mips_EXTP_MM /* 1643 */, MIPS_INS_EXTP, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv_rs.w $rt, $ac, $shift_rs */ + Mips_EXTRV_RS_W /* 1644 */, MIPS_INS_EXTRV_RS_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv_rs.w $rt, $ac, $rs */ + Mips_EXTRV_RS_W_MM /* 1645 */, MIPS_INS_EXTRV_RS_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv_r.w $rt, $ac, $shift_rs */ + Mips_EXTRV_R_W /* 1646 */, MIPS_INS_EXTRV_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv_r.w $rt, $ac, $rs */ + Mips_EXTRV_R_W_MM /* 1647 */, MIPS_INS_EXTRV_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv_s.h $rt, $ac, $shift_rs */ + Mips_EXTRV_S_H /* 1648 */, MIPS_INS_EXTRV_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv_s.h $rt, $ac, $rs */ + Mips_EXTRV_S_H_MM /* 1649 */, MIPS_INS_EXTRV_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv.w $rt, $ac, $shift_rs */ + Mips_EXTRV_W /* 1650 */, MIPS_INS_EXTRV_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv.w $rt, $ac, $rs */ + Mips_EXTRV_W_MM /* 1651 */, MIPS_INS_EXTRV_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr_rs.w $rt, $ac, $shift_rs */ + Mips_EXTR_RS_W /* 1652 */, MIPS_INS_EXTR_RS_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr_rs.w $rt, $ac, $imm */ + Mips_EXTR_RS_W_MM /* 1653 */, MIPS_INS_EXTR_RS_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr_r.w $rt, $ac, $shift_rs */ + Mips_EXTR_R_W /* 1654 */, MIPS_INS_EXTR_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr_r.w $rt, $ac, $imm */ + Mips_EXTR_R_W_MM /* 1655 */, MIPS_INS_EXTR_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr_s.h $rt, $ac, $shift_rs */ + Mips_EXTR_S_H /* 1656 */, MIPS_INS_EXTR_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr_s.h $rt, $ac, $imm */ + Mips_EXTR_S_H_MM /* 1657 */, MIPS_INS_EXTR_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr.w $rt, $ac, $shift_rs */ + Mips_EXTR_W /* 1658 */, MIPS_INS_EXTR_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr.w $rt, $ac, $imm */ + Mips_EXTR_W_MM /* 1659 */, MIPS_INS_EXTR_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* exts $rt, $rs, $pos, $lenm1 */ + Mips_EXTS /* 1660 */, MIPS_INS_EXTS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_HASCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* exts32 $rt, $rs, $pos, $lenm1 */ + Mips_EXTS32 /* 1661 */, MIPS_INS_EXTS32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_HASCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extw $rd, $rs, $rt, $shift */ + Mips_EXTW_NM /* 1662 */, MIPS_INS_EXTW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ext $rt, $rs, $pos, $size */ + Mips_EXT_MM /* 1663 */, MIPS_INS_EXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ext $rt, $rs, $pos, $size */ + Mips_EXT_MMR6 /* 1664 */, MIPS_INS_EXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ext $rt, $rs, $pos, $size */ + Mips_EXT_NM /* 1665 */, MIPS_INS_EXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* abs.d $fd, $fs */ + Mips_FABS_D32 /* 1666 */, MIPS_INS_ABS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* abs.d $fd, $fs */ + Mips_FABS_D32_MM /* 1667 */, MIPS_INS_ABS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* abs.d $fd, $fs */ + Mips_FABS_D64 /* 1668 */, MIPS_INS_ABS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* abs.d $fd, $fs */ + Mips_FABS_D64_MM /* 1669 */, MIPS_INS_ABS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* abs.s $fd, $fs */ + Mips_FABS_S /* 1670 */, MIPS_INS_ABS_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* abs.s $fd, $fs */ + Mips_FABS_S_MM /* 1671 */, MIPS_INS_ABS_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fadd.d $wd, $ws, $wt */ + Mips_FADD_D /* 1672 */, MIPS_INS_FADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.d $fd, $fs, $ft */ + Mips_FADD_D32 /* 1673 */, MIPS_INS_ADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.d $fd, $fs, $ft */ + Mips_FADD_D32_MM /* 1674 */, MIPS_INS_ADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.d $fd, $fs, $ft */ + Mips_FADD_D64 /* 1675 */, MIPS_INS_ADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.d $fd, $fs, $ft */ + Mips_FADD_D64_MM /* 1676 */, MIPS_INS_ADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.ps $fd, $fs, $ft */ + Mips_FADD_PS64 /* 1677 */, MIPS_INS_ADD_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.s $fd, $fs, $ft */ + Mips_FADD_S /* 1678 */, MIPS_INS_ADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.s $fd, $fs, $ft */ + Mips_FADD_S_MM /* 1679 */, MIPS_INS_ADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.s $fd, $fs, $ft */ + Mips_FADD_S_MMR6 /* 1680 */, MIPS_INS_ADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fadd.w $wd, $ws, $wt */ + Mips_FADD_W /* 1681 */, MIPS_INS_FADD_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcaf.d $wd, $ws, $wt */ + Mips_FCAF_D /* 1682 */, MIPS_INS_FCAF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcaf.w $wd, $ws, $wt */ + Mips_FCAF_W /* 1683 */, MIPS_INS_FCAF_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fceq.d $wd, $ws, $wt */ + Mips_FCEQ_D /* 1684 */, MIPS_INS_FCEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fceq.w $wd, $ws, $wt */ + Mips_FCEQ_W /* 1685 */, MIPS_INS_FCEQ_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fclass.d $wd, $ws */ + Mips_FCLASS_D /* 1686 */, MIPS_INS_FCLASS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fclass.w $wd, $ws */ + Mips_FCLASS_W /* 1687 */, MIPS_INS_FCLASS_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcle.d $wd, $ws, $wt */ + Mips_FCLE_D /* 1688 */, MIPS_INS_FCLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcle.w $wd, $ws, $wt */ + Mips_FCLE_W /* 1689 */, MIPS_INS_FCLE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fclt.d $wd, $ws, $wt */ + Mips_FCLT_D /* 1690 */, MIPS_INS_FCLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fclt.w $wd, $ws, $wt */ + Mips_FCLT_W /* 1691 */, MIPS_INS_FCLT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.$cond.d $fs, $ft */ + Mips_FCMP_D32 /* 1692 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* c.$cond.d $fs, $ft */ + Mips_FCMP_D32_MM /* 1693 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* c.$cond.d $fs, $ft */ + Mips_FCMP_D64 /* 1694 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* c.$cond.s $fs, $ft */ + Mips_FCMP_S32 /* 1695 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* c.$cond.s $fs, $ft */ + Mips_FCMP_S32_MM /* 1696 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* fcne.d $wd, $ws, $wt */ + Mips_FCNE_D /* 1697 */, MIPS_INS_FCNE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcne.w $wd, $ws, $wt */ + Mips_FCNE_W /* 1698 */, MIPS_INS_FCNE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcor.d $wd, $ws, $wt */ + Mips_FCOR_D /* 1699 */, MIPS_INS_FCOR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcor.w $wd, $ws, $wt */ + Mips_FCOR_W /* 1700 */, MIPS_INS_FCOR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcueq.d $wd, $ws, $wt */ + Mips_FCUEQ_D /* 1701 */, MIPS_INS_FCUEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcueq.w $wd, $ws, $wt */ + Mips_FCUEQ_W /* 1702 */, MIPS_INS_FCUEQ_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcule.d $wd, $ws, $wt */ + Mips_FCULE_D /* 1703 */, MIPS_INS_FCULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcule.w $wd, $ws, $wt */ + Mips_FCULE_W /* 1704 */, MIPS_INS_FCULE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcult.d $wd, $ws, $wt */ + Mips_FCULT_D /* 1705 */, MIPS_INS_FCULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcult.w $wd, $ws, $wt */ + Mips_FCULT_W /* 1706 */, MIPS_INS_FCULT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcune.d $wd, $ws, $wt */ + Mips_FCUNE_D /* 1707 */, MIPS_INS_FCUNE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcune.w $wd, $ws, $wt */ + Mips_FCUNE_W /* 1708 */, MIPS_INS_FCUNE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcun.d $wd, $ws, $wt */ + Mips_FCUN_D /* 1709 */, MIPS_INS_FCUN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcun.w $wd, $ws, $wt */ + Mips_FCUN_W /* 1710 */, MIPS_INS_FCUN_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fdiv.d $wd, $ws, $wt */ + Mips_FDIV_D /* 1711 */, MIPS_INS_FDIV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.d $fd, $fs, $ft */ + Mips_FDIV_D32 /* 1712 */, MIPS_INS_DIV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.d $fd, $fs, $ft */ + Mips_FDIV_D32_MM /* 1713 */, MIPS_INS_DIV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.d $fd, $fs, $ft */ + Mips_FDIV_D64 /* 1714 */, MIPS_INS_DIV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.d $fd, $fs, $ft */ + Mips_FDIV_D64_MM /* 1715 */, MIPS_INS_DIV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.s $fd, $fs, $ft */ + Mips_FDIV_S /* 1716 */, MIPS_INS_DIV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.s $fd, $fs, $ft */ + Mips_FDIV_S_MM /* 1717 */, MIPS_INS_DIV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.s $fd, $fs, $ft */ + Mips_FDIV_S_MMR6 /* 1718 */, MIPS_INS_DIV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fdiv.w $wd, $ws, $wt */ + Mips_FDIV_W /* 1719 */, MIPS_INS_FDIV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexdo.h $wd, $ws, $wt */ + Mips_FEXDO_H /* 1720 */, MIPS_INS_FEXDO_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexdo.w $wd, $ws, $wt */ + Mips_FEXDO_W /* 1721 */, MIPS_INS_FEXDO_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexp2.d $wd, $ws, $wt */ + Mips_FEXP2_D /* 1722 */, MIPS_INS_FEXP2_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexp2.w $wd, $ws, $wt */ + Mips_FEXP2_W /* 1723 */, MIPS_INS_FEXP2_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexupl.d $wd, $ws */ + Mips_FEXUPL_D /* 1724 */, MIPS_INS_FEXUPL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexupl.w $wd, $ws */ + Mips_FEXUPL_W /* 1725 */, MIPS_INS_FEXUPL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexupr.d $wd, $ws */ + Mips_FEXUPR_D /* 1726 */, MIPS_INS_FEXUPR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexupr.w $wd, $ws */ + Mips_FEXUPR_W /* 1727 */, MIPS_INS_FEXUPR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffint_s.d $wd, $ws */ + Mips_FFINT_S_D /* 1728 */, MIPS_INS_FFINT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffint_s.w $wd, $ws */ + Mips_FFINT_S_W /* 1729 */, MIPS_INS_FFINT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffint_u.d $wd, $ws */ + Mips_FFINT_U_D /* 1730 */, MIPS_INS_FFINT_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffint_u.w $wd, $ws */ + Mips_FFINT_U_W /* 1731 */, MIPS_INS_FFINT_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffql.d $wd, $ws */ + Mips_FFQL_D /* 1732 */, MIPS_INS_FFQL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffql.w $wd, $ws */ + Mips_FFQL_W /* 1733 */, MIPS_INS_FFQL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffqr.d $wd, $ws */ + Mips_FFQR_D /* 1734 */, MIPS_INS_FFQR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffqr.w $wd, $ws */ + Mips_FFQR_W /* 1735 */, MIPS_INS_FFQR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fill.b $wd, $rs */ + Mips_FILL_B /* 1736 */, MIPS_INS_FILL_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fill.d $wd, $rs */ + Mips_FILL_D /* 1737 */, MIPS_INS_FILL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fill.h $wd, $rs */ + Mips_FILL_H /* 1738 */, MIPS_INS_FILL_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fill.w $wd, $rs */ + Mips_FILL_W /* 1739 */, MIPS_INS_FILL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* flog2.d $wd, $ws */ + Mips_FLOG2_D /* 1740 */, MIPS_INS_FLOG2_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* flog2.w $wd, $ws */ + Mips_FLOG2_W /* 1741 */, MIPS_INS_FLOG2_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.l.d $fd, $fs */ + Mips_FLOOR_L_D64 /* 1742 */, MIPS_INS_FLOOR_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.l.d $ft, $fs */ + Mips_FLOOR_L_D_MMR6 /* 1743 */, MIPS_INS_FLOOR_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.l.s $fd, $fs */ + Mips_FLOOR_L_S /* 1744 */, MIPS_INS_FLOOR_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.l.s $ft, $fs */ + Mips_FLOOR_L_S_MMR6 /* 1745 */, MIPS_INS_FLOOR_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.d $fd, $fs */ + Mips_FLOOR_W_D32 /* 1746 */, MIPS_INS_FLOOR_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.d $fd, $fs */ + Mips_FLOOR_W_D64 /* 1747 */, MIPS_INS_FLOOR_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.d $ft, $fs */ + Mips_FLOOR_W_D_MMR6 /* 1748 */, MIPS_INS_FLOOR_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.d $fd, $fs */ + Mips_FLOOR_W_MM /* 1749 */, MIPS_INS_FLOOR_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.s $fd, $fs */ + Mips_FLOOR_W_S /* 1750 */, MIPS_INS_FLOOR_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.s $fd, $fs */ + Mips_FLOOR_W_S_MM /* 1751 */, MIPS_INS_FLOOR_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.s $ft, $fs */ + Mips_FLOOR_W_S_MMR6 /* 1752 */, MIPS_INS_FLOOR_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmadd.d $wd, $ws, $wt */ + Mips_FMADD_D /* 1753 */, MIPS_INS_FMADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmadd.w $wd, $ws, $wt */ + Mips_FMADD_W /* 1754 */, MIPS_INS_FMADD_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmax_a.d $wd, $ws, $wt */ + Mips_FMAX_A_D /* 1755 */, MIPS_INS_FMAX_A_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmax_a.w $wd, $ws, $wt */ + Mips_FMAX_A_W /* 1756 */, MIPS_INS_FMAX_A_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmax.d $wd, $ws, $wt */ + Mips_FMAX_D /* 1757 */, MIPS_INS_FMAX_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmax.w $wd, $ws, $wt */ + Mips_FMAX_W /* 1758 */, MIPS_INS_FMAX_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmin_a.d $wd, $ws, $wt */ + Mips_FMIN_A_D /* 1759 */, MIPS_INS_FMIN_A_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmin_a.w $wd, $ws, $wt */ + Mips_FMIN_A_W /* 1760 */, MIPS_INS_FMIN_A_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmin.d $wd, $ws, $wt */ + Mips_FMIN_D /* 1761 */, MIPS_INS_FMIN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmin.w $wd, $ws, $wt */ + Mips_FMIN_W /* 1762 */, MIPS_INS_FMIN_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.d $fd, $fs */ + Mips_FMOV_D32 /* 1763 */, MIPS_INS_MOV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.d $fd, $fs */ + Mips_FMOV_D32_MM /* 1764 */, MIPS_INS_MOV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.d $fd, $fs */ + Mips_FMOV_D64 /* 1765 */, MIPS_INS_MOV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.d $fd, $fs */ + Mips_FMOV_D64_MM /* 1766 */, MIPS_INS_MOV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.d $ft, $fs */ + Mips_FMOV_D_MMR6 /* 1767 */, MIPS_INS_MOV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.s $fd, $fs */ + Mips_FMOV_S /* 1768 */, MIPS_INS_MOV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.s $fd, $fs */ + Mips_FMOV_S_MM /* 1769 */, MIPS_INS_MOV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.s $ft, $fs */ + Mips_FMOV_S_MMR6 /* 1770 */, MIPS_INS_MOV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmsub.d $wd, $ws, $wt */ + Mips_FMSUB_D /* 1771 */, MIPS_INS_FMSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmsub.w $wd, $ws, $wt */ + Mips_FMSUB_W /* 1772 */, MIPS_INS_FMSUB_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmul.d $wd, $ws, $wt */ + Mips_FMUL_D /* 1773 */, MIPS_INS_FMUL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.d $fd, $fs, $ft */ + Mips_FMUL_D32 /* 1774 */, MIPS_INS_MUL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.d $fd, $fs, $ft */ + Mips_FMUL_D32_MM /* 1775 */, MIPS_INS_MUL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.d $fd, $fs, $ft */ + Mips_FMUL_D64 /* 1776 */, MIPS_INS_MUL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.d $fd, $fs, $ft */ + Mips_FMUL_D64_MM /* 1777 */, MIPS_INS_MUL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.ps $fd, $fs, $ft */ + Mips_FMUL_PS64 /* 1778 */, MIPS_INS_MUL_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.s $fd, $fs, $ft */ + Mips_FMUL_S /* 1779 */, MIPS_INS_MUL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.s $fd, $fs, $ft */ + Mips_FMUL_S_MM /* 1780 */, MIPS_INS_MUL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.s $fd, $fs, $ft */ + Mips_FMUL_S_MMR6 /* 1781 */, MIPS_INS_MUL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmul.w $wd, $ws, $wt */ + Mips_FMUL_W /* 1782 */, MIPS_INS_FMUL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.d $fd, $fs */ + Mips_FNEG_D32 /* 1783 */, MIPS_INS_NEG_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.d $fd, $fs */ + Mips_FNEG_D32_MM /* 1784 */, MIPS_INS_NEG_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.d $fd, $fs */ + Mips_FNEG_D64 /* 1785 */, MIPS_INS_NEG_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.d $fd, $fs */ + Mips_FNEG_D64_MM /* 1786 */, MIPS_INS_NEG_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.s $fd, $fs */ + Mips_FNEG_S /* 1787 */, MIPS_INS_NEG_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.s $fd, $fs */ + Mips_FNEG_S_MM /* 1788 */, MIPS_INS_NEG_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.s $ft, $fs */ + Mips_FNEG_S_MMR6 /* 1789 */, MIPS_INS_NEG_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fork $rd, $rs, $rt */ + Mips_FORK /* 1790 */, MIPS_INS_FORK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fork $rd, $rs, $rt */ + Mips_FORK_NM /* 1791 */, MIPS_INS_FORK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* frcp.d $wd, $ws */ + Mips_FRCP_D /* 1792 */, MIPS_INS_FRCP_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* frcp.w $wd, $ws */ + Mips_FRCP_W /* 1793 */, MIPS_INS_FRCP_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* frint.d $wd, $ws */ + Mips_FRINT_D /* 1794 */, MIPS_INS_FRINT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* frint.w $wd, $ws */ + Mips_FRINT_W /* 1795 */, MIPS_INS_FRINT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* frsqrt.d $wd, $ws */ + Mips_FRSQRT_D /* 1796 */, MIPS_INS_FRSQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* frsqrt.w $wd, $ws */ + Mips_FRSQRT_W /* 1797 */, MIPS_INS_FRSQRT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsaf.d $wd, $ws, $wt */ + Mips_FSAF_D /* 1798 */, MIPS_INS_FSAF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsaf.w $wd, $ws, $wt */ + Mips_FSAF_W /* 1799 */, MIPS_INS_FSAF_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fseq.d $wd, $ws, $wt */ + Mips_FSEQ_D /* 1800 */, MIPS_INS_FSEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fseq.w $wd, $ws, $wt */ + Mips_FSEQ_W /* 1801 */, MIPS_INS_FSEQ_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsle.d $wd, $ws, $wt */ + Mips_FSLE_D /* 1802 */, MIPS_INS_FSLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsle.w $wd, $ws, $wt */ + Mips_FSLE_W /* 1803 */, MIPS_INS_FSLE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fslt.d $wd, $ws, $wt */ + Mips_FSLT_D /* 1804 */, MIPS_INS_FSLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fslt.w $wd, $ws, $wt */ + Mips_FSLT_W /* 1805 */, MIPS_INS_FSLT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsne.d $wd, $ws, $wt */ + Mips_FSNE_D /* 1806 */, MIPS_INS_FSNE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsne.w $wd, $ws, $wt */ + Mips_FSNE_W /* 1807 */, MIPS_INS_FSNE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsor.d $wd, $ws, $wt */ + Mips_FSOR_D /* 1808 */, MIPS_INS_FSOR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsor.w $wd, $ws, $wt */ + Mips_FSOR_W /* 1809 */, MIPS_INS_FSOR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsqrt.d $wd, $ws */ + Mips_FSQRT_D /* 1810 */, MIPS_INS_FSQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sqrt.d $fd, $fs */ + Mips_FSQRT_D32 /* 1811 */, MIPS_INS_SQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sqrt.d $fd, $fs */ + Mips_FSQRT_D32_MM /* 1812 */, MIPS_INS_SQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sqrt.d $fd, $fs */ + Mips_FSQRT_D64 /* 1813 */, MIPS_INS_SQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sqrt.d $fd, $fs */ + Mips_FSQRT_D64_MM /* 1814 */, MIPS_INS_SQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sqrt.s $fd, $fs */ + Mips_FSQRT_S /* 1815 */, MIPS_INS_SQRT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sqrt.s $fd, $fs */ + Mips_FSQRT_S_MM /* 1816 */, MIPS_INS_SQRT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsqrt.w $wd, $ws */ + Mips_FSQRT_W /* 1817 */, MIPS_INS_FSQRT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsub.d $wd, $ws, $wt */ + Mips_FSUB_D /* 1818 */, MIPS_INS_FSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.d $fd, $fs, $ft */ + Mips_FSUB_D32 /* 1819 */, MIPS_INS_SUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.d $fd, $fs, $ft */ + Mips_FSUB_D32_MM /* 1820 */, MIPS_INS_SUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.d $fd, $fs, $ft */ + Mips_FSUB_D64 /* 1821 */, MIPS_INS_SUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.d $fd, $fs, $ft */ + Mips_FSUB_D64_MM /* 1822 */, MIPS_INS_SUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.ps $fd, $fs, $ft */ + Mips_FSUB_PS64 /* 1823 */, MIPS_INS_SUB_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.s $fd, $fs, $ft */ + Mips_FSUB_S /* 1824 */, MIPS_INS_SUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.s $fd, $fs, $ft */ + Mips_FSUB_S_MM /* 1825 */, MIPS_INS_SUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.s $fd, $fs, $ft */ + Mips_FSUB_S_MMR6 /* 1826 */, MIPS_INS_SUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsub.w $wd, $ws, $wt */ + Mips_FSUB_W /* 1827 */, MIPS_INS_FSUB_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsueq.d $wd, $ws, $wt */ + Mips_FSUEQ_D /* 1828 */, MIPS_INS_FSUEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsueq.w $wd, $ws, $wt */ + Mips_FSUEQ_W /* 1829 */, MIPS_INS_FSUEQ_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsule.d $wd, $ws, $wt */ + Mips_FSULE_D /* 1830 */, MIPS_INS_FSULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsule.w $wd, $ws, $wt */ + Mips_FSULE_W /* 1831 */, MIPS_INS_FSULE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsult.d $wd, $ws, $wt */ + Mips_FSULT_D /* 1832 */, MIPS_INS_FSULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsult.w $wd, $ws, $wt */ + Mips_FSULT_W /* 1833 */, MIPS_INS_FSULT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsune.d $wd, $ws, $wt */ + Mips_FSUNE_D /* 1834 */, MIPS_INS_FSUNE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsune.w $wd, $ws, $wt */ + Mips_FSUNE_W /* 1835 */, MIPS_INS_FSUNE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsun.d $wd, $ws, $wt */ + Mips_FSUN_D /* 1836 */, MIPS_INS_FSUN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsun.w $wd, $ws, $wt */ + Mips_FSUN_W /* 1837 */, MIPS_INS_FSUN_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftint_s.d $wd, $ws */ + Mips_FTINT_S_D /* 1838 */, MIPS_INS_FTINT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftint_s.w $wd, $ws */ + Mips_FTINT_S_W /* 1839 */, MIPS_INS_FTINT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftint_u.d $wd, $ws */ + Mips_FTINT_U_D /* 1840 */, MIPS_INS_FTINT_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftint_u.w $wd, $ws */ + Mips_FTINT_U_W /* 1841 */, MIPS_INS_FTINT_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftq.h $wd, $ws, $wt */ + Mips_FTQ_H /* 1842 */, MIPS_INS_FTQ_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftq.w $wd, $ws, $wt */ + Mips_FTQ_W /* 1843 */, MIPS_INS_FTQ_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftrunc_s.d $wd, $ws */ + Mips_FTRUNC_S_D /* 1844 */, MIPS_INS_FTRUNC_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftrunc_s.w $wd, $ws */ + Mips_FTRUNC_S_W /* 1845 */, MIPS_INS_FTRUNC_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftrunc_u.d $wd, $ws */ + Mips_FTRUNC_U_D /* 1846 */, MIPS_INS_FTRUNC_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftrunc_u.w $wd, $ws */ + Mips_FTRUNC_U_W /* 1847 */, MIPS_INS_FTRUNC_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ginvi $rs */ + Mips_GINVI /* 1848 */, MIPS_INS_GINVI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASGINV, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ginvi $rs */ + Mips_GINVI_MMR6 /* 1849 */, MIPS_INS_GINVI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASGINV, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ginvi $rs */ + Mips_GINVI_NM /* 1850 */, MIPS_INS_GINVI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASGINV, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ginvt $rs, $type_ */ + Mips_GINVT /* 1851 */, MIPS_INS_GINVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASGINV, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ginvt $rs, $type */ + Mips_GINVT_MMR6 /* 1852 */, MIPS_INS_GINVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASGINV, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ginvt $rs, $type */ + Mips_GINVT_NM /* 1853 */, MIPS_INS_GINVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASGINV, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hadd_s.d $wd, $ws, $wt */ + Mips_HADD_S_D /* 1854 */, MIPS_INS_HADD_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hadd_s.h $wd, $ws, $wt */ + Mips_HADD_S_H /* 1855 */, MIPS_INS_HADD_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hadd_s.w $wd, $ws, $wt */ + Mips_HADD_S_W /* 1856 */, MIPS_INS_HADD_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hadd_u.d $wd, $ws, $wt */ + Mips_HADD_U_D /* 1857 */, MIPS_INS_HADD_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hadd_u.h $wd, $ws, $wt */ + Mips_HADD_U_H /* 1858 */, MIPS_INS_HADD_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hadd_u.w $wd, $ws, $wt */ + Mips_HADD_U_W /* 1859 */, MIPS_INS_HADD_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hsub_s.d $wd, $ws, $wt */ + Mips_HSUB_S_D /* 1860 */, MIPS_INS_HSUB_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hsub_s.h $wd, $ws, $wt */ + Mips_HSUB_S_H /* 1861 */, MIPS_INS_HSUB_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hsub_s.w $wd, $ws, $wt */ + Mips_HSUB_S_W /* 1862 */, MIPS_INS_HSUB_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hsub_u.d $wd, $ws, $wt */ + Mips_HSUB_U_D /* 1863 */, MIPS_INS_HSUB_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hsub_u.h $wd, $ws, $wt */ + Mips_HSUB_U_H /* 1864 */, MIPS_INS_HSUB_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hsub_u.w $wd, $ws, $wt */ + Mips_HSUB_U_W /* 1865 */, MIPS_INS_HSUB_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hypcall $code_ */ + Mips_HYPCALL /* 1866 */, MIPS_INS_HYPCALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hypcall $code_ */ + Mips_HYPCALL_MM /* 1867 */, MIPS_INS_HYPCALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvev.b $wd, $ws, $wt */ + Mips_ILVEV_B /* 1868 */, MIPS_INS_ILVEV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvev.d $wd, $ws, $wt */ + Mips_ILVEV_D /* 1869 */, MIPS_INS_ILVEV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvev.h $wd, $ws, $wt */ + Mips_ILVEV_H /* 1870 */, MIPS_INS_ILVEV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvev.w $wd, $ws, $wt */ + Mips_ILVEV_W /* 1871 */, MIPS_INS_ILVEV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvl.b $wd, $ws, $wt */ + Mips_ILVL_B /* 1872 */, MIPS_INS_ILVL_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvl.d $wd, $ws, $wt */ + Mips_ILVL_D /* 1873 */, MIPS_INS_ILVL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvl.h $wd, $ws, $wt */ + Mips_ILVL_H /* 1874 */, MIPS_INS_ILVL_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvl.w $wd, $ws, $wt */ + Mips_ILVL_W /* 1875 */, MIPS_INS_ILVL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvod.b $wd, $ws, $wt */ + Mips_ILVOD_B /* 1876 */, MIPS_INS_ILVOD_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvod.d $wd, $ws, $wt */ + Mips_ILVOD_D /* 1877 */, MIPS_INS_ILVOD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvod.h $wd, $ws, $wt */ + Mips_ILVOD_H /* 1878 */, MIPS_INS_ILVOD_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvod.w $wd, $ws, $wt */ + Mips_ILVOD_W /* 1879 */, MIPS_INS_ILVOD_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvr.b $wd, $ws, $wt */ + Mips_ILVR_B /* 1880 */, MIPS_INS_ILVR_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvr.d $wd, $ws, $wt */ + Mips_ILVR_D /* 1881 */, MIPS_INS_ILVR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvr.h $wd, $ws, $wt */ + Mips_ILVR_H /* 1882 */, MIPS_INS_ILVR_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvr.w $wd, $ws, $wt */ + Mips_ILVR_W /* 1883 */, MIPS_INS_ILVR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ins $rt, $rs, $pos, $size */ + Mips_INS /* 1884 */, MIPS_INS_INS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insert.b $wd[$n], $rs */ + Mips_INSERT_B /* 1885 */, MIPS_INS_INSERT_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insert.d $wd[$n], $rs */ + Mips_INSERT_D /* 1886 */, MIPS_INS_INSERT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insert.h $wd[$n], $rs */ + Mips_INSERT_H /* 1887 */, MIPS_INS_INSERT_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insert.w $wd[$n], $rs */ + Mips_INSERT_W /* 1888 */, MIPS_INS_INSERT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insv $rt, $rs */ + Mips_INSV /* 1889 */, MIPS_INS_INSV, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insve.b $wd[$n], $ws[$n2] */ + Mips_INSVE_B /* 1890 */, MIPS_INS_INSVE_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insve.d $wd[$n], $ws[$n2] */ + Mips_INSVE_D /* 1891 */, MIPS_INS_INSVE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insve.h $wd[$n], $ws[$n2] */ + Mips_INSVE_H /* 1892 */, MIPS_INS_INSVE_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insve.w $wd[$n], $ws[$n2] */ + Mips_INSVE_W /* 1893 */, MIPS_INS_INSVE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insv $rt, $rs */ + Mips_INSV_MM /* 1894 */, MIPS_INS_INSV, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ins $rt, $rs, $pos, $size */ + Mips_INS_MM /* 1895 */, MIPS_INS_INS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ins $rt, $rs, $pos, $size */ + Mips_INS_MMR6 /* 1896 */, MIPS_INS_INS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ins $rt, $rs, $pos, $size */ + Mips_INS_NM /* 1897 */, MIPS_INS_INS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* j $target */ + Mips_J /* 1898 */, MIPS_INS_J, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* jal $target */ + Mips_JAL /* 1899 */, MIPS_INS_JAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalr $rd, $rs */ + Mips_JALR /* 1900 */, MIPS_INS_JALR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOINDIRECTJUMPGUARDS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalr $rs */ + Mips_JALR16_MM /* 1901 */, MIPS_INS_JALR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalr $rd, $rs */ + Mips_JALR64 /* 1902 */, MIPS_INS_JALR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_NOTINMIPS16MODE, MIPS_FEATURE_ISPTR64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalr $rs */ + Mips_JALRC16_MMR6 /* 1903 */, MIPS_INS_JALR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalrc $rt, $rs */ + Mips_JALRC16_NM /* 1904 */, MIPS_INS_JALRC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA_NM, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalrc.hb $rt, $rs */ + Mips_JALRCHB_NM /* 1905 */, MIPS_INS_JALRC_HB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA_NM, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalrc.hb $rt, $rs */ + Mips_JALRC_HB_MMR6 /* 1906 */, MIPS_INS_JALRC_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 1, {{ 0 }} + + #endif +}, +{ + /* jalrc $rt, $rs */ + Mips_JALRC_MMR6 /* 1907 */, MIPS_INS_JALRC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalrc $rt, $rs */ + Mips_JALRC_NM /* 1908 */, MIPS_INS_JALRC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA_NM, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalrs16 $rs */ + Mips_JALRS16_MM /* 1909 */, MIPS_INS_JALRS16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalrs $rd, $rs */ + Mips_JALRS_MM /* 1910 */, MIPS_INS_JALRS, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalr.hb $rd, $rs */ + Mips_JALR_HB /* 1911 */, MIPS_INS_JALR_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, 0 }, 0, 1, {{ 0 }} + + #endif +}, +{ + /* jalr.hb $rd, $rs */ + Mips_JALR_HB64 /* 1912 */, MIPS_INS_JALR_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 1, {{ 0 }} + + #endif +}, +{ + /* jalr $rd, $rs */ + Mips_JALR_MM /* 1913 */, MIPS_INS_JALR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jals $target */ + Mips_JALS_MM /* 1914 */, MIPS_INS_JALS, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalx $target */ + Mips_JALX /* 1915 */, MIPS_INS_JALX, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalx $target */ + Mips_JALX_MM /* 1916 */, MIPS_INS_JALX, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jal $target */ + Mips_JAL_MM /* 1917 */, MIPS_INS_JAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jialc $rt, $offset */ + Mips_JIALC /* 1918 */, MIPS_INS_JIALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jialc $rt, $offset */ + Mips_JIALC64 /* 1919 */, MIPS_INS_JIALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jialc $rt, $offset */ + Mips_JIALC_MMR6 /* 1920 */, MIPS_INS_JIALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jic $rt, $offset */ + Mips_JIC /* 1921 */, MIPS_INS_JIC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jic $rt, $offset */ + Mips_JIC64 /* 1922 */, MIPS_INS_JIC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jic $rt, $offset */ + Mips_JIC_MMR6 /* 1923 */, MIPS_INS_JIC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jr $rs */ + Mips_JR /* 1924 */, MIPS_INS_JR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr16 $rs */ + Mips_JR16_MM /* 1925 */, MIPS_INS_JR16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr $rs */ + Mips_JR64 /* 1926 */, MIPS_INS_JR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_NOTINMIPS16MODE, MIPS_FEATURE_ISPTR64BIT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jraddiusp $imm */ + Mips_JRADDIUSP /* 1927 */, MIPS_INS_JRADDIUSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jrc $rs */ + Mips_JRC16_MM /* 1928 */, MIPS_INS_JRC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jrc16 $rs */ + Mips_JRC16_MMR6 /* 1929 */, MIPS_INS_JRC16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jrcaddiusp $imm */ + Mips_JRCADDIUSP_MMR6 /* 1930 */, MIPS_INS_JRCADDIUSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jrc $rs */ + Mips_JRC_NM /* 1931 */, MIPS_INS_JRC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr.hb $rs */ + Mips_JR_HB /* 1932 */, MIPS_INS_JR_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr.hb $rs */ + Mips_JR_HB64 /* 1933 */, MIPS_INS_JR_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr.hb $rs */ + Mips_JR_HB64_R6 /* 1934 */, MIPS_INS_JR_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr.hb $rs */ + Mips_JR_HB_R6 /* 1935 */, MIPS_INS_JR_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr $rs */ + Mips_JR_MM /* 1936 */, MIPS_INS_JR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* j $target */ + Mips_J_MM /* 1937 */, MIPS_INS_J, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* jal $imm26 + nop */ + Mips_Jal16 /* 1938 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* jal $imm26 # branch + nop */ + Mips_JalB16 /* 1939 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* jr $$ra */ + Mips_JrRa16 /* 1940 */, MIPS_INS_JR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_RET, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jrc $$ra */ + Mips_JrcRa16 /* 1941 */, MIPS_INS_JRC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_RET, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jrc $rs */ + Mips_JrcRx16 /* 1942 */, MIPS_INS_JRC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jalrc $rx */ + Mips_JumpLinkReg16 /* 1943 */, MIPS_INS_JALRC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lapc.h $rt, $addr */ + Mips_LAPC32_NM /* 1944 */, MIPS_INS_LAPC_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lapc.b $rt, $addr */ + Mips_LAPC48_NM /* 1945 */, MIPS_INS_LAPC_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LB /* 1946 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LB16_NM /* 1947 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LB64 /* 1948 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lbe $rt, $addr */ + Mips_LBE /* 1949 */, MIPS_INS_LBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbe $rt, $addr */ + Mips_LBE_MM /* 1950 */, MIPS_INS_LBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LBGP_NM /* 1951 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu16 $rt, $addr */ + Mips_LBU16_MM /* 1952 */, MIPS_INS_LBU16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBU16_NM /* 1953 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBUGP_NM /* 1954 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbux $rd, ${index}(${base}) */ + Mips_LBUX /* 1955 */, MIPS_INS_LBUX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbux $rd, ${index}(${base}) */ + Mips_LBUX_MM /* 1956 */, MIPS_INS_LBUX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbux $rt, $addr */ + Mips_LBUX_NM /* 1957 */, MIPS_INS_LBUX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBU_MMR6 /* 1958 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBU_NM /* 1959 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBUs9_NM /* 1960 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbx $rt, $addr */ + Mips_LBX_NM /* 1961 */, MIPS_INS_LBX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LB_MM /* 1962 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LB_MMR6 /* 1963 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LB_NM /* 1964 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LBs9_NM /* 1965 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBu /* 1966 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBu64 /* 1967 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lbue $rt, $addr */ + Mips_LBuE /* 1968 */, MIPS_INS_LBUE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbue $rt, $addr */ + Mips_LBuE_MM /* 1969 */, MIPS_INS_LBUE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBu_MM /* 1970 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ld $rt, $addr */ + Mips_LD /* 1971 */, MIPS_INS_LD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc1 $rt, $addr */ + Mips_LDC1 /* 1972 */, MIPS_INS_LDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc1 $rt, $addr */ + Mips_LDC164 /* 1973 */, MIPS_INS_LDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc1 $ft, $addr */ + Mips_LDC1_D64_MMR6 /* 1974 */, MIPS_INS_LDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc1 $rt, $addr */ + Mips_LDC1_MM_D32 /* 1975 */, MIPS_INS_LDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc1 $rt, $addr */ + Mips_LDC1_MM_D64 /* 1976 */, MIPS_INS_LDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc2 $rt, $addr */ + Mips_LDC2 /* 1977 */, MIPS_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc2 $rt, $addr */ + Mips_LDC2_MMR6 /* 1978 */, MIPS_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc2 $rt, $addr */ + Mips_LDC2_R6 /* 1979 */, MIPS_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc3 $rt, $addr */ + Mips_LDC3 /* 1980 */, MIPS_INS_LDC3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldi.b $wd, $s10 */ + Mips_LDI_B /* 1981 */, MIPS_INS_LDI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldi.d $wd, $s10 */ + Mips_LDI_D /* 1982 */, MIPS_INS_LDI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldi.h $wd, $s10 */ + Mips_LDI_H /* 1983 */, MIPS_INS_LDI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldi.w $wd, $s10 */ + Mips_LDI_W /* 1984 */, MIPS_INS_LDI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldl $rt, $addr */ + Mips_LDL /* 1985 */, MIPS_INS_LDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldpc $rs, $imm */ + Mips_LDPC /* 1986 */, MIPS_INS_LDPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldr $rt, $addr */ + Mips_LDR /* 1987 */, MIPS_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldxc1 $fd, ${index}(${base}) */ + Mips_LDXC1 /* 1988 */, MIPS_INS_LDXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldxc1 $fd, ${index}(${base}) */ + Mips_LDXC164 /* 1989 */, MIPS_INS_LDXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ld.b $wd, $addr */ + Mips_LD_B /* 1990 */, MIPS_INS_LD_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ld.d $wd, $addr */ + Mips_LD_D /* 1991 */, MIPS_INS_LD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ld.h $wd, $addr */ + Mips_LD_H /* 1992 */, MIPS_INS_LD_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ld.w $wd, $addr */ + Mips_LD_W /* 1993 */, MIPS_INS_LD_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rt, $addr */ + Mips_LEA_ADDIU_NM /* 1994 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* addiu $rt, $addr */ + Mips_LEA_ADDiu /* 1995 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* daddiu $rt, $addr */ + Mips_LEA_ADDiu64 /* 1996 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* addiu $rt, $addr */ + Mips_LEA_ADDiu_MM /* 1997 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LH /* 1998 */, MIPS_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LH16_NM /* 1999 */, MIPS_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LH64 /* 2000 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lhe $rt, $addr */ + Mips_LHE /* 2001 */, MIPS_INS_LHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhe $rt, $addr */ + Mips_LHE_MM /* 2002 */, MIPS_INS_LHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LHGP_NM /* 2003 */, MIPS_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu16 $rt, $addr */ + Mips_LHU16_MM /* 2004 */, MIPS_INS_LHU16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHU16_NM /* 2005 */, MIPS_INS_LHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHUGP_NM /* 2006 */, MIPS_INS_LHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhuxs $rt, $addr */ + Mips_LHUXS_NM /* 2007 */, MIPS_INS_LHUXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhux $rt, $addr */ + Mips_LHUX_NM /* 2008 */, MIPS_INS_LHUX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHU_NM /* 2009 */, MIPS_INS_LHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHUs9_NM /* 2010 */, MIPS_INS_LHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhx $rd, ${index}(${base}) */ + Mips_LHX /* 2011 */, MIPS_INS_LHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhxs $rt, $addr */ + Mips_LHXS_NM /* 2012 */, MIPS_INS_LHXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhx $rd, ${index}(${base}) */ + Mips_LHX_MM /* 2013 */, MIPS_INS_LHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhx $rt, $addr */ + Mips_LHX_NM /* 2014 */, MIPS_INS_LHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LH_MM /* 2015 */, MIPS_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LH_NM /* 2016 */, MIPS_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LHs9_NM /* 2017 */, MIPS_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHu /* 2018 */, MIPS_INS_LHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHu64 /* 2019 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lhue $rt, $addr */ + Mips_LHuE /* 2020 */, MIPS_INS_LHUE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhue $rt, $addr */ + Mips_LHuE_MM /* 2021 */, MIPS_INS_LHUE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHu_MM /* 2022 */, MIPS_INS_LHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li16 $rd, $imm */ + Mips_LI16_MM /* 2023 */, MIPS_INS_LI16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li16 $rd, $imm */ + Mips_LI16_MMR6 /* 2024 */, MIPS_INS_LI16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li $rt, $eu */ + Mips_LI16_NM /* 2025 */, MIPS_INS_LI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li[48] $rt, $imm */ + Mips_LI48_NM /* 2026 */, MIPS_INS_LI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL /* 2027 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR32BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL64 /* 2028 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL64_R6 /* 2029 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR64BIT, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lld $rt, $addr */ + Mips_LLD /* 2030 */, MIPS_INS_LLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lld $rt, $addr */ + Mips_LLD_R6 /* 2031 */, MIPS_INS_LLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lle $rt, $addr */ + Mips_LLE /* 2032 */, MIPS_INS_LLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lle $rt, $addr */ + Mips_LLE_MM /* 2033 */, MIPS_INS_LLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* llwp $rt, $ru, $addr */ + Mips_LLWP_NM /* 2034 */, MIPS_INS_LLWP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL_MM /* 2035 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL_MMR6 /* 2036 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL_NM /* 2037 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL_R6 /* 2038 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR32BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lsa $rd, $rs, $rt, $sa */ + Mips_LSA /* 2039 */, MIPS_INS_LSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lsa $rt, $rs, $rd, $imm2 */ + Mips_LSA_MMR6 /* 2040 */, MIPS_INS_LSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lsa $rd, $rs, $rt, $shift */ + Mips_LSA_NM /* 2041 */, MIPS_INS_LSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lsa $rd, $rs, $rt, $imm2 */ + Mips_LSA_R6 /* 2042 */, MIPS_INS_LSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lui $rt, $imm16 */ + Mips_LUI_MMR6 /* 2043 */, MIPS_INS_LUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lui $rt, $imm */ + Mips_LUI_NM /* 2044 */, MIPS_INS_LUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* luxc1 $fd, ${index}(${base}) */ + Mips_LUXC1 /* 2045 */, MIPS_INS_LUXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS5_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* luxc1 $fd, ${index}(${base}) */ + Mips_LUXC164 /* 2046 */, MIPS_INS_LUXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS5_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* luxc1 $fd, ${index}(${base}) */ + Mips_LUXC1_MM /* 2047 */, MIPS_INS_LUXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lui $rt, $imm16 */ + Mips_LUi /* 2048 */, MIPS_INS_LUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lui $rt, $imm16 */ + Mips_LUi64 /* 2049 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lui $rt, $imm16 */ + Mips_LUi_MM /* 2050 */, MIPS_INS_LUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW /* 2051 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw16 $rt, $addr */ + Mips_LW16_MM /* 2052 */, MIPS_INS_LW16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW16_NM /* 2053 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW4x4_NM /* 2054 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW64 /* 2055 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lwc1 $rt, $addr */ + Mips_LWC1 /* 2056 */, MIPS_INS_LWC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwc1 $rt, $addr */ + Mips_LWC1_MM /* 2057 */, MIPS_INS_LWC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwc2 $rt, $addr */ + Mips_LWC2 /* 2058 */, MIPS_INS_LWC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwc2 $rt, $addr */ + Mips_LWC2_MMR6 /* 2059 */, MIPS_INS_LWC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwc2 $rt, $addr */ + Mips_LWC2_R6 /* 2060 */, MIPS_INS_LWC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwc3 $rt, $addr */ + Mips_LWC3 /* 2061 */, MIPS_INS_LWC3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LWDSP /* 2062 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTINMIPS16MODE, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LWDSP_MM /* 2063 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwe $rt, $addr */ + Mips_LWE /* 2064 */, MIPS_INS_LWE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwe $rt, $addr */ + Mips_LWE_MM /* 2065 */, MIPS_INS_LWE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LWGP16_NM /* 2066 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $offset */ + Mips_LWGP_MM /* 2067 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LWGP_NM /* 2068 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwl $rt, $addr */ + Mips_LWL /* 2069 */, MIPS_INS_LWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwl $rt, $addr */ + Mips_LWL64 /* 2070 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lwle $rt, $addr */ + Mips_LWLE /* 2071 */, MIPS_INS_LWLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwle $rt, $addr */ + Mips_LWLE_MM /* 2072 */, MIPS_INS_LWLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwl $rt, $addr */ + Mips_LWL_MM /* 2073 */, MIPS_INS_LWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwm16 $rt, $addr */ + Mips_LWM16_MM /* 2074 */, MIPS_INS_LWM16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwm16 $rt, $addr */ + Mips_LWM16_MMR6 /* 2075 */, MIPS_INS_LWM16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwm32 $rt, $addr */ + Mips_LWM32_MM /* 2076 */, MIPS_INS_LWM32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwm $rt, $addr, $rcount */ + Mips_LWM_NM /* 2077 */, MIPS_INS_LWM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwpc $rs, $imm */ + Mips_LWPC /* 2078 */, MIPS_INS_LWPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwpc $rt, $imm */ + Mips_LWPC_MMR6 /* 2079 */, MIPS_INS_LWPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwpc $rt, $addr */ + Mips_LWPC_NM /* 2080 */, MIPS_INS_LWPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwp $rt, $addr */ + Mips_LWP_MM /* 2081 */, MIPS_INS_LWP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwr $rt, $addr */ + Mips_LWR /* 2082 */, MIPS_INS_LWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwr $rt, $addr */ + Mips_LWR64 /* 2083 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lwre $rt, $addr */ + Mips_LWRE /* 2084 */, MIPS_INS_LWRE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwre $rt, $addr */ + Mips_LWRE_MM /* 2085 */, MIPS_INS_LWRE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwr $rt, $addr */ + Mips_LWR_MM /* 2086 */, MIPS_INS_LWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LWSP16_NM /* 2087 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $offset */ + Mips_LWSP_MM /* 2088 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwupc $rs, $imm */ + Mips_LWUPC /* 2089 */, MIPS_INS_LWUPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwu $rt, $addr */ + Mips_LWU_MM /* 2090 */, MIPS_INS_LWU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwx $rd, ${index}(${base}) */ + Mips_LWX /* 2091 */, MIPS_INS_LWX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwxc1 $fd, ${index}(${base}) */ + Mips_LWXC1 /* 2092 */, MIPS_INS_LWXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwxc1 $fd, ${index}(${base}) */ + Mips_LWXC1_MM /* 2093 */, MIPS_INS_LWXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwxs $rt, $addr */ + Mips_LWXS16_NM /* 2094 */, MIPS_INS_LWXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwxs $rd, ${index}(${base}) */ + Mips_LWXS_MM /* 2095 */, MIPS_INS_LWXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwxs $rt, $addr */ + Mips_LWXS_NM /* 2096 */, MIPS_INS_LWXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwx $rd, ${index}(${base}) */ + Mips_LWX_MM /* 2097 */, MIPS_INS_LWX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwx $rt, $addr */ + Mips_LWX_NM /* 2098 */, MIPS_INS_LWX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW_MM /* 2099 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW_MMR6 /* 2100 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW_NM /* 2101 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LWs9_NM /* 2102 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwu $rt, $addr */ + Mips_LWu /* 2103 */, MIPS_INS_LWU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $ry, $addr */ + Mips_LbRxRyOffMemX16 /* 2104 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lbu $ry, $addr */ + Mips_LbuRxRyOffMemX16 /* 2105 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lh $ry, $addr */ + Mips_LhRxRyOffMemX16 /* 2106 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lhu $ry, $addr */ + Mips_LhuRxRyOffMemX16 /* 2107 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* li $rx, $imm8 # 16 bit inst */ + Mips_LiRxImm16 /* 2108 */, MIPS_INS_LI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* .align 2 + li $rx, $imm16 */ + Mips_LiRxImmAlignX16 /* 2109 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* li $rx, $imm16 */ + Mips_LiRxImmX16 /* 2110 */, MIPS_INS_LI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rx, $imm8 # 16 bit inst */ + Mips_LwRxPcTcp16 /* 2111 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rx, $imm16 */ + Mips_LwRxPcTcpX16 /* 2112 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $ry, $addr */ + Mips_LwRxRyOffMemX16 /* 2113 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lw $ry, $addr */ + Mips_LwRxSpImmX16 /* 2114 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd $rs, $rt */ + Mips_MADD /* 2115 */, MIPS_INS_MADD, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddf.d $fd, $fs, $ft */ + Mips_MADDF_D /* 2116 */, MIPS_INS_MADDF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddf.d $fd, $fs, $ft */ + Mips_MADDF_D_MMR6 /* 2117 */, MIPS_INS_MADDF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddf.s $fd, $fs, $ft */ + Mips_MADDF_S /* 2118 */, MIPS_INS_MADDF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddf.s $fd, $fs, $ft */ + Mips_MADDF_S_MMR6 /* 2119 */, MIPS_INS_MADDF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddr_q.h $wd, $ws, $wt */ + Mips_MADDR_Q_H /* 2120 */, MIPS_INS_MADDR_Q_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddr_q.w $wd, $ws, $wt */ + Mips_MADDR_Q_W /* 2121 */, MIPS_INS_MADDR_Q_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddu $rs, $rt */ + Mips_MADDU /* 2122 */, MIPS_INS_MADDU, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddu $ac, $rs, $rt */ + Mips_MADDU_DSP /* 2123 */, MIPS_INS_MADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddu $ac, $rs, $rt */ + Mips_MADDU_DSP_MM /* 2124 */, MIPS_INS_MADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddu $rs, $rt */ + Mips_MADDU_MM /* 2125 */, MIPS_INS_MADDU, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddv.b $wd, $ws, $wt */ + Mips_MADDV_B /* 2126 */, MIPS_INS_MADDV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddv.d $wd, $ws, $wt */ + Mips_MADDV_D /* 2127 */, MIPS_INS_MADDV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddv.h $wd, $ws, $wt */ + Mips_MADDV_H /* 2128 */, MIPS_INS_MADDV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddv.w $wd, $ws, $wt */ + Mips_MADDV_W /* 2129 */, MIPS_INS_MADDV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd.d $fd, $fr, $fs, $ft */ + Mips_MADD_D32 /* 2130 */, MIPS_INS_MADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_HASMADD4 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd.d $fd, $fr, $fs, $ft */ + Mips_MADD_D32_MM /* 2131 */, MIPS_INS_MADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd.d $fd, $fr, $fs, $ft */ + Mips_MADD_D64 /* 2132 */, MIPS_INS_MADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_HASMADD4 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd $ac, $rs, $rt */ + Mips_MADD_DSP /* 2133 */, MIPS_INS_MADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd $ac, $rs, $rt */ + Mips_MADD_DSP_MM /* 2134 */, MIPS_INS_MADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd $rs, $rt */ + Mips_MADD_MM /* 2135 */, MIPS_INS_MADD, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd_q.h $wd, $ws, $wt */ + Mips_MADD_Q_H /* 2136 */, MIPS_INS_MADD_Q_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd_q.w $wd, $ws, $wt */ + Mips_MADD_Q_W /* 2137 */, MIPS_INS_MADD_Q_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd.s $fd, $fr, $fs, $ft */ + Mips_MADD_S /* 2138 */, MIPS_INS_MADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd.s $fd, $fr, $fs, $ft */ + Mips_MADD_S_MM /* 2139 */, MIPS_INS_MADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_sa.w.phl $ac, $rs, $rt */ + Mips_MAQ_SA_W_PHL /* 2140 */, MIPS_INS_MAQ_SA_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_sa.w.phl $ac, $rs, $rt */ + Mips_MAQ_SA_W_PHL_MM /* 2141 */, MIPS_INS_MAQ_SA_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_sa.w.phr $ac, $rs, $rt */ + Mips_MAQ_SA_W_PHR /* 2142 */, MIPS_INS_MAQ_SA_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_sa.w.phr $ac, $rs, $rt */ + Mips_MAQ_SA_W_PHR_MM /* 2143 */, MIPS_INS_MAQ_SA_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_s.w.phl $ac, $rs, $rt */ + Mips_MAQ_S_W_PHL /* 2144 */, MIPS_INS_MAQ_S_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_s.w.phl $ac, $rs, $rt */ + Mips_MAQ_S_W_PHL_MM /* 2145 */, MIPS_INS_MAQ_S_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_s.w.phr $ac, $rs, $rt */ + Mips_MAQ_S_W_PHR /* 2146 */, MIPS_INS_MAQ_S_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_s.w.phr $ac, $rs, $rt */ + Mips_MAQ_S_W_PHR_MM /* 2147 */, MIPS_INS_MAQ_S_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxa.d $fd, $fs, $ft */ + Mips_MAXA_D /* 2148 */, MIPS_INS_MAXA_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxa.d $fd, $fs, $ft */ + Mips_MAXA_D_MMR6 /* 2149 */, MIPS_INS_MAXA_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxa.s $fd, $fs, $ft */ + Mips_MAXA_S /* 2150 */, MIPS_INS_MAXA_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxa.s $fd, $fs, $ft */ + Mips_MAXA_S_MMR6 /* 2151 */, MIPS_INS_MAXA_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_s.b $wd, $ws, $imm */ + Mips_MAXI_S_B /* 2152 */, MIPS_INS_MAXI_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_s.d $wd, $ws, $imm */ + Mips_MAXI_S_D /* 2153 */, MIPS_INS_MAXI_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_s.h $wd, $ws, $imm */ + Mips_MAXI_S_H /* 2154 */, MIPS_INS_MAXI_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_s.w $wd, $ws, $imm */ + Mips_MAXI_S_W /* 2155 */, MIPS_INS_MAXI_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_u.b $wd, $ws, $imm */ + Mips_MAXI_U_B /* 2156 */, MIPS_INS_MAXI_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_u.d $wd, $ws, $imm */ + Mips_MAXI_U_D /* 2157 */, MIPS_INS_MAXI_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_u.h $wd, $ws, $imm */ + Mips_MAXI_U_H /* 2158 */, MIPS_INS_MAXI_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_u.w $wd, $ws, $imm */ + Mips_MAXI_U_W /* 2159 */, MIPS_INS_MAXI_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_a.b $wd, $ws, $wt */ + Mips_MAX_A_B /* 2160 */, MIPS_INS_MAX_A_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_a.d $wd, $ws, $wt */ + Mips_MAX_A_D /* 2161 */, MIPS_INS_MAX_A_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_a.h $wd, $ws, $wt */ + Mips_MAX_A_H /* 2162 */, MIPS_INS_MAX_A_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_a.w $wd, $ws, $wt */ + Mips_MAX_A_W /* 2163 */, MIPS_INS_MAX_A_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max.d $fd, $fs, $ft */ + Mips_MAX_D /* 2164 */, MIPS_INS_MAX_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max.d $fd, $fs, $ft */ + Mips_MAX_D_MMR6 /* 2165 */, MIPS_INS_MAX_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max.s $fd, $fs, $ft */ + Mips_MAX_S /* 2166 */, MIPS_INS_MAX_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_s.b $wd, $ws, $wt */ + Mips_MAX_S_B /* 2167 */, MIPS_INS_MAX_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_s.d $wd, $ws, $wt */ + Mips_MAX_S_D /* 2168 */, MIPS_INS_MAX_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_s.h $wd, $ws, $wt */ + Mips_MAX_S_H /* 2169 */, MIPS_INS_MAX_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max.s $fd, $fs, $ft */ + Mips_MAX_S_MMR6 /* 2170 */, MIPS_INS_MAX_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_s.w $wd, $ws, $wt */ + Mips_MAX_S_W /* 2171 */, MIPS_INS_MAX_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_u.b $wd, $ws, $wt */ + Mips_MAX_U_B /* 2172 */, MIPS_INS_MAX_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_u.d $wd, $ws, $wt */ + Mips_MAX_U_D /* 2173 */, MIPS_INS_MAX_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_u.h $wd, $ws, $wt */ + Mips_MAX_U_H /* 2174 */, MIPS_INS_MAX_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_u.w $wd, $ws, $wt */ + Mips_MAX_U_W /* 2175 */, MIPS_INS_MAX_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc0 $rt, $rd, $sel */ + Mips_MFC0 /* 2176 */, MIPS_INS_MFC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc0 $rt, $c0s */ + Mips_MFC0Sel_NM /* 2177 */, MIPS_INS_MFC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc0 $rt, $rs, $sel */ + Mips_MFC0_MMR6 /* 2178 */, MIPS_INS_MFC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc0 $rt, $c0s, $sel */ + Mips_MFC0_NM /* 2179 */, MIPS_INS_MFC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc1 $rt, $fs */ + Mips_MFC1 /* 2180 */, MIPS_INS_MFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc1 $rt, $fs */ + Mips_MFC1_D64 /* 2181 */, MIPS_INS_MFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc1 $rt, $fs */ + Mips_MFC1_MM /* 2182 */, MIPS_INS_MFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc1 $rt, $fs */ + Mips_MFC1_MMR6 /* 2183 */, MIPS_INS_MFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc2 $rt, $rd, $sel */ + Mips_MFC2 /* 2184 */, MIPS_INS_MFC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc2 $rt, $impl */ + Mips_MFC2_MMR6 /* 2185 */, MIPS_INS_MFC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfgc0 $rt, $rd, $sel */ + Mips_MFGC0 /* 2186 */, MIPS_INS_MFGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfgc0 $rt, $rs, $sel */ + Mips_MFGC0_MM /* 2187 */, MIPS_INS_MFGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc0 $rt, $c0s */ + Mips_MFHC0Sel_NM /* 2188 */, MIPS_INS_MFHC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc0 $rt, $rs, $sel */ + Mips_MFHC0_MMR6 /* 2189 */, MIPS_INS_MFHC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc0 $rt, $c0s, $sel */ + Mips_MFHC0_NM /* 2190 */, MIPS_INS_MFHC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc1 $rt, $fs */ + Mips_MFHC1_D32 /* 2191 */, MIPS_INS_MFHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc1 $rt, $fs */ + Mips_MFHC1_D32_MM /* 2192 */, MIPS_INS_MFHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc1 $rt, $fs */ + Mips_MFHC1_D64 /* 2193 */, MIPS_INS_MFHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc1 $rt, $fs */ + Mips_MFHC1_D64_MM /* 2194 */, MIPS_INS_MFHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc2 $rt, $impl */ + Mips_MFHC2_MMR6 /* 2195 */, MIPS_INS_MFHC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhgc0 $rt, $rd, $sel */ + Mips_MFHGC0 /* 2196 */, MIPS_INS_MFHGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhgc0 $rt, $rs, $sel */ + Mips_MFHGC0_MM /* 2197 */, MIPS_INS_MFHGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhi $rd */ + Mips_MFHI /* 2198 */, MIPS_INS_MFHI, + #ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhi16 $rd */ + Mips_MFHI16_MM /* 2199 */, MIPS_INS_MFHI16, + #ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhi $rd */ + Mips_MFHI64 /* 2200 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mfhi $rd, $ac */ + Mips_MFHI_DSP /* 2201 */, MIPS_INS_MFHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhi $rs, $ac */ + Mips_MFHI_DSP_MM /* 2202 */, MIPS_INS_MFHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhi $rd */ + Mips_MFHI_MM /* 2203 */, MIPS_INS_MFHI, + #ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mflo $rd */ + Mips_MFLO /* 2204 */, MIPS_INS_MFLO, + #ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mflo16 $rd */ + Mips_MFLO16_MM /* 2205 */, MIPS_INS_MFLO16, + #ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mflo $rd */ + Mips_MFLO64 /* 2206 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mflo $rd, $ac */ + Mips_MFLO_DSP /* 2207 */, MIPS_INS_MFLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mflo $rs, $ac */ + Mips_MFLO_DSP_MM /* 2208 */, MIPS_INS_MFLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mflo $rd */ + Mips_MFLO_MM /* 2209 */, MIPS_INS_MFLO, + #ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftr $rd, $rt, $u, $sel, $h */ + Mips_MFTR /* 2210 */, MIPS_INS_MFTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftr $rd, $rt, $u, $sel, $h */ + Mips_MFTR_NM /* 2211 */, MIPS_INS_MFTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mina.d $fd, $fs, $ft */ + Mips_MINA_D /* 2212 */, MIPS_INS_MINA_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mina.d $fd, $fs, $ft */ + Mips_MINA_D_MMR6 /* 2213 */, MIPS_INS_MINA_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mina.s $fd, $fs, $ft */ + Mips_MINA_S /* 2214 */, MIPS_INS_MINA_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mina.s $fd, $fs, $ft */ + Mips_MINA_S_MMR6 /* 2215 */, MIPS_INS_MINA_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_s.b $wd, $ws, $imm */ + Mips_MINI_S_B /* 2216 */, MIPS_INS_MINI_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_s.d $wd, $ws, $imm */ + Mips_MINI_S_D /* 2217 */, MIPS_INS_MINI_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_s.h $wd, $ws, $imm */ + Mips_MINI_S_H /* 2218 */, MIPS_INS_MINI_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_s.w $wd, $ws, $imm */ + Mips_MINI_S_W /* 2219 */, MIPS_INS_MINI_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_u.b $wd, $ws, $imm */ + Mips_MINI_U_B /* 2220 */, MIPS_INS_MINI_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_u.d $wd, $ws, $imm */ + Mips_MINI_U_D /* 2221 */, MIPS_INS_MINI_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_u.h $wd, $ws, $imm */ + Mips_MINI_U_H /* 2222 */, MIPS_INS_MINI_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_u.w $wd, $ws, $imm */ + Mips_MINI_U_W /* 2223 */, MIPS_INS_MINI_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_a.b $wd, $ws, $wt */ + Mips_MIN_A_B /* 2224 */, MIPS_INS_MIN_A_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_a.d $wd, $ws, $wt */ + Mips_MIN_A_D /* 2225 */, MIPS_INS_MIN_A_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_a.h $wd, $ws, $wt */ + Mips_MIN_A_H /* 2226 */, MIPS_INS_MIN_A_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_a.w $wd, $ws, $wt */ + Mips_MIN_A_W /* 2227 */, MIPS_INS_MIN_A_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min.d $fd, $fs, $ft */ + Mips_MIN_D /* 2228 */, MIPS_INS_MIN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min.d $fd, $fs, $ft */ + Mips_MIN_D_MMR6 /* 2229 */, MIPS_INS_MIN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min.s $fd, $fs, $ft */ + Mips_MIN_S /* 2230 */, MIPS_INS_MIN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_s.b $wd, $ws, $wt */ + Mips_MIN_S_B /* 2231 */, MIPS_INS_MIN_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_s.d $wd, $ws, $wt */ + Mips_MIN_S_D /* 2232 */, MIPS_INS_MIN_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_s.h $wd, $ws, $wt */ + Mips_MIN_S_H /* 2233 */, MIPS_INS_MIN_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min.s $fd, $fs, $ft */ + Mips_MIN_S_MMR6 /* 2234 */, MIPS_INS_MIN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_s.w $wd, $ws, $wt */ + Mips_MIN_S_W /* 2235 */, MIPS_INS_MIN_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_u.b $wd, $ws, $wt */ + Mips_MIN_U_B /* 2236 */, MIPS_INS_MIN_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_u.d $wd, $ws, $wt */ + Mips_MIN_U_D /* 2237 */, MIPS_INS_MIN_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_u.h $wd, $ws, $wt */ + Mips_MIN_U_H /* 2238 */, MIPS_INS_MIN_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_u.w $wd, $ws, $wt */ + Mips_MIN_U_W /* 2239 */, MIPS_INS_MIN_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod $rd, $rs, $rt */ + Mips_MOD /* 2240 */, MIPS_INS_MOD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* modsub $rd, $rs, $rt */ + Mips_MODSUB /* 2241 */, MIPS_INS_MODSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* modsub $rd, $rs, $rt */ + Mips_MODSUB_MM /* 2242 */, MIPS_INS_MODSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* modu $rd, $rs, $rt */ + Mips_MODU /* 2243 */, MIPS_INS_MODU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* modu $rd, $rs, $rt */ + Mips_MODU_MMR6 /* 2244 */, MIPS_INS_MODU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* modu $rd, $rs, $rt */ + Mips_MODU_NM /* 2245 */, MIPS_INS_MODU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod $rd, $rs, $rt */ + Mips_MOD_MMR6 /* 2246 */, MIPS_INS_MOD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod $rd, $rs, $rt */ + Mips_MOD_NM /* 2247 */, MIPS_INS_MOD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_s.b $wd, $ws, $wt */ + Mips_MOD_S_B /* 2248 */, MIPS_INS_MOD_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_s.d $wd, $ws, $wt */ + Mips_MOD_S_D /* 2249 */, MIPS_INS_MOD_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_s.h $wd, $ws, $wt */ + Mips_MOD_S_H /* 2250 */, MIPS_INS_MOD_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_s.w $wd, $ws, $wt */ + Mips_MOD_S_W /* 2251 */, MIPS_INS_MOD_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_u.b $wd, $ws, $wt */ + Mips_MOD_U_B /* 2252 */, MIPS_INS_MOD_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_u.d $wd, $ws, $wt */ + Mips_MOD_U_D /* 2253 */, MIPS_INS_MOD_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_u.h $wd, $ws, $wt */ + Mips_MOD_U_H /* 2254 */, MIPS_INS_MOD_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_u.w $wd, $ws, $wt */ + Mips_MOD_U_W /* 2255 */, MIPS_INS_MOD_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move $rd, $rs */ + Mips_MOVE16_MM /* 2256 */, MIPS_INS_MOVE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move16 $rd, $rs */ + Mips_MOVE16_MMR6 /* 2257 */, MIPS_INS_MOVE16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move.balc $rd, $rt, $addr */ + Mips_MOVEBALC_NM /* 2258 */, MIPS_INS_MOVE_BALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA_NM, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movep $dst1, $dst2, $src1, $src2 */ + Mips_MOVEPREV_NM /* 2259 */, MIPS_INS_MOVEP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movep $rd1, $rd2, $rs, $rt */ + Mips_MOVEP_MM /* 2260 */, MIPS_INS_MOVEP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movep $rd1, $rd2, $rs, $rt */ + Mips_MOVEP_MMR6 /* 2261 */, MIPS_INS_MOVEP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movep $dst1, $dst2, $src1, $src2 */ + Mips_MOVEP_NM /* 2262 */, MIPS_INS_MOVEP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move $rt, $rs */ + Mips_MOVE_NM /* 2263 */, MIPS_INS_MOVE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move.v $wd, $ws */ + Mips_MOVE_V /* 2264 */, MIPS_INS_MOVE_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf.d $fd, $fs, $fcc */ + Mips_MOVF_D32 /* 2265 */, MIPS_INS_MOVF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf.d $fd, $fs, $fcc */ + Mips_MOVF_D32_MM /* 2266 */, MIPS_INS_MOVF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf.d $fd, $fs, $fcc */ + Mips_MOVF_D64 /* 2267 */, MIPS_INS_MOVF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf $rd, $rs, $fcc */ + Mips_MOVF_I /* 2268 */, MIPS_INS_MOVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf $rd, $rs, $fcc */ + Mips_MOVF_I64 /* 2269 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movf $rd, $rs, $fcc */ + Mips_MOVF_I_MM /* 2270 */, MIPS_INS_MOVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf.s $fd, $fs, $fcc */ + Mips_MOVF_S /* 2271 */, MIPS_INS_MOVF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf.s $fd, $fs, $fcc */ + Mips_MOVF_S_MM /* 2272 */, MIPS_INS_MOVF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn.d $fd, $fs, $rt */ + Mips_MOVN_I64_D64 /* 2273 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movn $rd, $rs, $rt */ + Mips_MOVN_I64_I /* 2274 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movn $rd, $rs, $rt */ + Mips_MOVN_I64_I64 /* 2275 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movn.s $fd, $fs, $rt */ + Mips_MOVN_I64_S /* 2276 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movn.d $fd, $fs, $rt */ + Mips_MOVN_I_D32 /* 2277 */, MIPS_INS_MOVN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn.d $fd, $fs, $rt */ + Mips_MOVN_I_D32_MM /* 2278 */, MIPS_INS_MOVN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn.d $fd, $fs, $rt */ + Mips_MOVN_I_D64 /* 2279 */, MIPS_INS_MOVN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn $rd, $rs, $rt */ + Mips_MOVN_I_I /* 2280 */, MIPS_INS_MOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn $rd, $rs, $rt */ + Mips_MOVN_I_I64 /* 2281 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movn $rd, $rs, $rt */ + Mips_MOVN_I_MM /* 2282 */, MIPS_INS_MOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn.s $fd, $fs, $rt */ + Mips_MOVN_I_S /* 2283 */, MIPS_INS_MOVN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn.s $fd, $fs, $rt */ + Mips_MOVN_I_S_MM /* 2284 */, MIPS_INS_MOVN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn $rd, $rs, $rt */ + Mips_MOVN_NM /* 2285 */, MIPS_INS_MOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt.d $fd, $fs, $fcc */ + Mips_MOVT_D32 /* 2286 */, MIPS_INS_MOVT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt.d $fd, $fs, $fcc */ + Mips_MOVT_D32_MM /* 2287 */, MIPS_INS_MOVT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt.d $fd, $fs, $fcc */ + Mips_MOVT_D64 /* 2288 */, MIPS_INS_MOVT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt $rd, $rs, $fcc */ + Mips_MOVT_I /* 2289 */, MIPS_INS_MOVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt $rd, $rs, $fcc */ + Mips_MOVT_I64 /* 2290 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movt $rd, $rs, $fcc */ + Mips_MOVT_I_MM /* 2291 */, MIPS_INS_MOVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt.s $fd, $fs, $fcc */ + Mips_MOVT_S /* 2292 */, MIPS_INS_MOVT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt.s $fd, $fs, $fcc */ + Mips_MOVT_S_MM /* 2293 */, MIPS_INS_MOVT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz.d $fd, $fs, $rt */ + Mips_MOVZ_I64_D64 /* 2294 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movz $rd, $rs, $rt */ + Mips_MOVZ_I64_I /* 2295 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movz $rd, $rs, $rt */ + Mips_MOVZ_I64_I64 /* 2296 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movz.s $fd, $fs, $rt */ + Mips_MOVZ_I64_S /* 2297 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movz.d $fd, $fs, $rt */ + Mips_MOVZ_I_D32 /* 2298 */, MIPS_INS_MOVZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz.d $fd, $fs, $rt */ + Mips_MOVZ_I_D32_MM /* 2299 */, MIPS_INS_MOVZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz.d $fd, $fs, $rt */ + Mips_MOVZ_I_D64 /* 2300 */, MIPS_INS_MOVZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz $rd, $rs, $rt */ + Mips_MOVZ_I_I /* 2301 */, MIPS_INS_MOVZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz $rd, $rs, $rt */ + Mips_MOVZ_I_I64 /* 2302 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movz $rd, $rs, $rt */ + Mips_MOVZ_I_MM /* 2303 */, MIPS_INS_MOVZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz.s $fd, $fs, $rt */ + Mips_MOVZ_I_S /* 2304 */, MIPS_INS_MOVZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz.s $fd, $fs, $rt */ + Mips_MOVZ_I_S_MM /* 2305 */, MIPS_INS_MOVZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz $rd, $rs, $rt */ + Mips_MOVZ_NM /* 2306 */, MIPS_INS_MOVZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub $rs, $rt */ + Mips_MSUB /* 2307 */, MIPS_INS_MSUB, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubf.d $fd, $fs, $ft */ + Mips_MSUBF_D /* 2308 */, MIPS_INS_MSUBF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubf.d $fd, $fs, $ft */ + Mips_MSUBF_D_MMR6 /* 2309 */, MIPS_INS_MSUBF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubf.s $fd, $fs, $ft */ + Mips_MSUBF_S /* 2310 */, MIPS_INS_MSUBF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubf.s $fd, $fs, $ft */ + Mips_MSUBF_S_MMR6 /* 2311 */, MIPS_INS_MSUBF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubr_q.h $wd, $ws, $wt */ + Mips_MSUBR_Q_H /* 2312 */, MIPS_INS_MSUBR_Q_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubr_q.w $wd, $ws, $wt */ + Mips_MSUBR_Q_W /* 2313 */, MIPS_INS_MSUBR_Q_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubu $rs, $rt */ + Mips_MSUBU /* 2314 */, MIPS_INS_MSUBU, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubu $ac, $rs, $rt */ + Mips_MSUBU_DSP /* 2315 */, MIPS_INS_MSUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubu $ac, $rs, $rt */ + Mips_MSUBU_DSP_MM /* 2316 */, MIPS_INS_MSUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubu $rs, $rt */ + Mips_MSUBU_MM /* 2317 */, MIPS_INS_MSUBU, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubv.b $wd, $ws, $wt */ + Mips_MSUBV_B /* 2318 */, MIPS_INS_MSUBV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubv.d $wd, $ws, $wt */ + Mips_MSUBV_D /* 2319 */, MIPS_INS_MSUBV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubv.h $wd, $ws, $wt */ + Mips_MSUBV_H /* 2320 */, MIPS_INS_MSUBV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubv.w $wd, $ws, $wt */ + Mips_MSUBV_W /* 2321 */, MIPS_INS_MSUBV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub.d $fd, $fr, $fs, $ft */ + Mips_MSUB_D32 /* 2322 */, MIPS_INS_MSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_HASMADD4 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub.d $fd, $fr, $fs, $ft */ + Mips_MSUB_D32_MM /* 2323 */, MIPS_INS_MSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub.d $fd, $fr, $fs, $ft */ + Mips_MSUB_D64 /* 2324 */, MIPS_INS_MSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_HASMADD4 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub $ac, $rs, $rt */ + Mips_MSUB_DSP /* 2325 */, MIPS_INS_MSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub $ac, $rs, $rt */ + Mips_MSUB_DSP_MM /* 2326 */, MIPS_INS_MSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub $rs, $rt */ + Mips_MSUB_MM /* 2327 */, MIPS_INS_MSUB, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub_q.h $wd, $ws, $wt */ + Mips_MSUB_Q_H /* 2328 */, MIPS_INS_MSUB_Q_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub_q.w $wd, $ws, $wt */ + Mips_MSUB_Q_W /* 2329 */, MIPS_INS_MSUB_Q_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub.s $fd, $fr, $fs, $ft */ + Mips_MSUB_S /* 2330 */, MIPS_INS_MSUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub.s $fd, $fr, $fs, $ft */ + Mips_MSUB_S_MM /* 2331 */, MIPS_INS_MSUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc0 $rt, $rd, $sel */ + Mips_MTC0 /* 2332 */, MIPS_INS_MTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc0 $rt, $c0s */ + Mips_MTC0Sel_NM /* 2333 */, MIPS_INS_MTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc0 $rt, $rs, $sel */ + Mips_MTC0_MMR6 /* 2334 */, MIPS_INS_MTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc0 $rt, $c0s, $sel */ + Mips_MTC0_NM /* 2335 */, MIPS_INS_MTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc1 $rt, $fs */ + Mips_MTC1 /* 2336 */, MIPS_INS_MTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc1 $rt, $fs */ + Mips_MTC1_D64 /* 2337 */, MIPS_INS_MTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc1 $rt, $fs */ + Mips_MTC1_D64_MM /* 2338 */, MIPS_INS_MTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc1 $rt, $fs */ + Mips_MTC1_MM /* 2339 */, MIPS_INS_MTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc1 $rt, $fs */ + Mips_MTC1_MMR6 /* 2340 */, MIPS_INS_MTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc2 $rt, $rd, $sel */ + Mips_MTC2 /* 2341 */, MIPS_INS_MTC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc2 $rt, $impl */ + Mips_MTC2_MMR6 /* 2342 */, MIPS_INS_MTC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtgc0 $rt, $rd, $sel */ + Mips_MTGC0 /* 2343 */, MIPS_INS_MTGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtgc0 $rt, $rs, $sel */ + Mips_MTGC0_MM /* 2344 */, MIPS_INS_MTGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc0 $rt, $c0s */ + Mips_MTHC0Sel_NM /* 2345 */, MIPS_INS_MTHC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc0 $rt, $rs, $sel */ + Mips_MTHC0_MMR6 /* 2346 */, MIPS_INS_MTHC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc0 $rt, $c0s, $sel */ + Mips_MTHC0_NM /* 2347 */, MIPS_INS_MTHC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc1 $rt, $fs */ + Mips_MTHC1_D32 /* 2348 */, MIPS_INS_MTHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc1 $rt, $fs */ + Mips_MTHC1_D32_MM /* 2349 */, MIPS_INS_MTHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc1 $rt, $fs */ + Mips_MTHC1_D64 /* 2350 */, MIPS_INS_MTHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc1 $rt, $fs */ + Mips_MTHC1_D64_MM /* 2351 */, MIPS_INS_MTHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc2 $rt, $impl */ + Mips_MTHC2_MMR6 /* 2352 */, MIPS_INS_MTHC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthgc0 $rt, $rd, $sel */ + Mips_MTHGC0 /* 2353 */, MIPS_INS_MTHGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthgc0 $rt, $rs, $sel */ + Mips_MTHGC0_MM /* 2354 */, MIPS_INS_MTHGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthi $rs */ + Mips_MTHI /* 2355 */, MIPS_INS_MTHI, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthi $rs */ + Mips_MTHI64 /* 2356 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mthi $rs, $ac */ + Mips_MTHI_DSP /* 2357 */, MIPS_INS_MTHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthi $rs, $ac */ + Mips_MTHI_DSP_MM /* 2358 */, MIPS_INS_MTHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthi $rs */ + Mips_MTHI_MM /* 2359 */, MIPS_INS_MTHI, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthlip $rs, $ac */ + Mips_MTHLIP /* 2360 */, MIPS_INS_MTHLIP, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthlip $rs, $ac */ + Mips_MTHLIP_MM /* 2361 */, MIPS_INS_MTHLIP, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtlo $rs */ + Mips_MTLO /* 2362 */, MIPS_INS_MTLO, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtlo $rs */ + Mips_MTLO64 /* 2363 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mtlo $rs, $ac */ + Mips_MTLO_DSP /* 2364 */, MIPS_INS_MTLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtlo $rs, $ac */ + Mips_MTLO_DSP_MM /* 2365 */, MIPS_INS_MTLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtlo $rs */ + Mips_MTLO_MM /* 2366 */, MIPS_INS_MTLO, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtm0 $rs */ + Mips_MTM0 /* 2367 */, MIPS_INS_MTM0, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtm1 $rs */ + Mips_MTM1 /* 2368 */, MIPS_INS_MTM1, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL1, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtm2 $rs */ + Mips_MTM2 /* 2369 */, MIPS_INS_MTM2, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtp0 $rs */ + Mips_MTP0 /* 2370 */, MIPS_INS_MTP0, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_P0, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtp1 $rs */ + Mips_MTP1 /* 2371 */, MIPS_INS_MTP1, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_P1, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtp2 $rs */ + Mips_MTP2 /* 2372 */, MIPS_INS_MTP2, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttr $rt, $rd, $u, $sel, $h */ + Mips_MTTR /* 2373 */, MIPS_INS_MTTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttr $rt, $rd, $u, $sel, $h */ + Mips_MTTR_NM /* 2374 */, MIPS_INS_MTTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muh $rd, $rs, $rt */ + Mips_MUH /* 2375 */, MIPS_INS_MUH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muhu $rd, $rs, $rt */ + Mips_MUHU /* 2376 */, MIPS_INS_MUHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muhu $rd, $rs, $rt */ + Mips_MUHU_MMR6 /* 2377 */, MIPS_INS_MUHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muhu $rd, $rs, $rt */ + Mips_MUHU_NM /* 2378 */, MIPS_INS_MUHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muh $rd, $rs, $rt */ + Mips_MUH_MMR6 /* 2379 */, MIPS_INS_MUH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muh $rd, $rs, $rt */ + Mips_MUH_NM /* 2380 */, MIPS_INS_MUH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $rd, $rs, $rt */ + Mips_MUL /* 2381 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $dst, $rt, $rs */ + Mips_MUL4x4_NM /* 2382 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleq_s.w.phl $rd, $rs, $rt */ + Mips_MULEQ_S_W_PHL /* 2383 */, MIPS_INS_MULEQ_S_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleq_s.w.phl $rd, $rs, $rt */ + Mips_MULEQ_S_W_PHL_MM /* 2384 */, MIPS_INS_MULEQ_S_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleq_s.w.phr $rd, $rs, $rt */ + Mips_MULEQ_S_W_PHR /* 2385 */, MIPS_INS_MULEQ_S_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleq_s.w.phr $rd, $rs, $rt */ + Mips_MULEQ_S_W_PHR_MM /* 2386 */, MIPS_INS_MULEQ_S_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleu_s.ph.qbl $rd, $rs, $rt */ + Mips_MULEU_S_PH_QBL /* 2387 */, MIPS_INS_MULEU_S_PH_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleu_s.ph.qbl $rd, $rs, $rt */ + Mips_MULEU_S_PH_QBL_MM /* 2388 */, MIPS_INS_MULEU_S_PH_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleu_s.ph.qbr $rd, $rs, $rt */ + Mips_MULEU_S_PH_QBR /* 2389 */, MIPS_INS_MULEU_S_PH_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleu_s.ph.qbr $rd, $rs, $rt */ + Mips_MULEU_S_PH_QBR_MM /* 2390 */, MIPS_INS_MULEU_S_PH_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_rs.ph $rd, $rs, $rt */ + Mips_MULQ_RS_PH /* 2391 */, MIPS_INS_MULQ_RS_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_rs.ph $rd, $rs, $rt */ + Mips_MULQ_RS_PH_MM /* 2392 */, MIPS_INS_MULQ_RS_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_rs.w $rd, $rs, $rt */ + Mips_MULQ_RS_W /* 2393 */, MIPS_INS_MULQ_RS_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_rs.w $rd, $rs, $rt */ + Mips_MULQ_RS_W_MMR2 /* 2394 */, MIPS_INS_MULQ_RS_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_s.ph $rd, $rs, $rt */ + Mips_MULQ_S_PH /* 2395 */, MIPS_INS_MULQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_s.ph $rd, $rs, $rt */ + Mips_MULQ_S_PH_MMR2 /* 2396 */, MIPS_INS_MULQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_s.w $rd, $rs, $rt */ + Mips_MULQ_S_W /* 2397 */, MIPS_INS_MULQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_s.w $rd, $rs, $rt */ + Mips_MULQ_S_W_MMR2 /* 2398 */, MIPS_INS_MULQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulr.ps $fd, $fs, $ft */ + Mips_MULR_PS64 /* 2399 */, MIPS_INS_MULR_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMIPS3D, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulr_q.h $wd, $ws, $wt */ + Mips_MULR_Q_H /* 2400 */, MIPS_INS_MULR_Q_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulr_q.w $wd, $ws, $wt */ + Mips_MULR_Q_W /* 2401 */, MIPS_INS_MULR_Q_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulsaq_s.w.ph $ac, $rs, $rt */ + Mips_MULSAQ_S_W_PH /* 2402 */, MIPS_INS_MULSAQ_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulsaq_s.w.ph $ac, $rs, $rt */ + Mips_MULSAQ_S_W_PH_MM /* 2403 */, MIPS_INS_MULSAQ_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulsa.w.ph $ac, $rs, $rt */ + Mips_MULSA_W_PH /* 2404 */, MIPS_INS_MULSA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulsa.w.ph $ac, $rs, $rt */ + Mips_MULSA_W_PH_MMR2 /* 2405 */, MIPS_INS_MULSA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mult $rs, $rt */ + Mips_MULT /* 2406 */, MIPS_INS_MULT, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* multu $ac, $rs, $rt */ + Mips_MULTU_DSP /* 2407 */, MIPS_INS_MULTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* multu $ac, $rs, $rt */ + Mips_MULTU_DSP_MM /* 2408 */, MIPS_INS_MULTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mult $ac, $rs, $rt */ + Mips_MULT_DSP /* 2409 */, MIPS_INS_MULT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mult $ac, $rs, $rt */ + Mips_MULT_DSP_MM /* 2410 */, MIPS_INS_MULT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mult $rs, $rt */ + Mips_MULT_MM /* 2411 */, MIPS_INS_MULT, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* multu $rs, $rt */ + Mips_MULTu /* 2412 */, MIPS_INS_MULTU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* multu $rs, $rt */ + Mips_MULTu_MM /* 2413 */, MIPS_INS_MULTU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulu $rd, $rs, $rt */ + Mips_MULU /* 2414 */, MIPS_INS_MULU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulu $rd, $rs, $rt */ + Mips_MULU_MMR6 /* 2415 */, MIPS_INS_MULU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulu $rd, $rs, $rt */ + Mips_MULU_NM /* 2416 */, MIPS_INS_MULU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulv.b $wd, $ws, $wt */ + Mips_MULV_B /* 2417 */, MIPS_INS_MULV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulv.d $wd, $ws, $wt */ + Mips_MULV_D /* 2418 */, MIPS_INS_MULV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulv.h $wd, $ws, $wt */ + Mips_MULV_H /* 2419 */, MIPS_INS_MULV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulv.w $wd, $ws, $wt */ + Mips_MULV_W /* 2420 */, MIPS_INS_MULV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $rd, $rs, $rt */ + Mips_MUL_MM /* 2421 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $rd, $rs, $rt */ + Mips_MUL_MMR6 /* 2422 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $rd, $rs, $rt */ + Mips_MUL_NM /* 2423 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.ph $rd, $rs, $rt */ + Mips_MUL_PH /* 2424 */, MIPS_INS_MUL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.ph $rd, $rs, $rt */ + Mips_MUL_PH_MMR2 /* 2425 */, MIPS_INS_MUL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul_q.h $wd, $ws, $wt */ + Mips_MUL_Q_H /* 2426 */, MIPS_INS_MUL_Q_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul_q.w $wd, $ws, $wt */ + Mips_MUL_Q_W /* 2427 */, MIPS_INS_MUL_Q_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $rd, $rs, $rt */ + Mips_MUL_R6 /* 2428 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul_s.ph $rd, $rs, $rt */ + Mips_MUL_S_PH /* 2429 */, MIPS_INS_MUL_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul_s.ph $rd, $rs, $rt */ + Mips_MUL_S_PH_MMR2 /* 2430 */, MIPS_INS_MUL_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhi $rx */ + Mips_Mfhi16 /* 2431 */, MIPS_INS_MFHI, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mflo $rx */ + Mips_Mflo16 /* 2432 */, MIPS_INS_MFLO, + #ifndef CAPSTONE_DIET + { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move $r32, $rz */ + Mips_Move32R16 /* 2433 */, MIPS_INS_MOVE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move $ry, $r32 */ + Mips_MoveR3216 /* 2434 */, MIPS_INS_MOVE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nloc.b $wd, $ws */ + Mips_NLOC_B /* 2435 */, MIPS_INS_NLOC_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nloc.d $wd, $ws */ + Mips_NLOC_D /* 2436 */, MIPS_INS_NLOC_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nloc.h $wd, $ws */ + Mips_NLOC_H /* 2437 */, MIPS_INS_NLOC_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nloc.w $wd, $ws */ + Mips_NLOC_W /* 2438 */, MIPS_INS_NLOC_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nlzc.b $wd, $ws */ + Mips_NLZC_B /* 2439 */, MIPS_INS_NLZC_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nlzc.d $wd, $ws */ + Mips_NLZC_D /* 2440 */, MIPS_INS_NLZC_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nlzc.h $wd, $ws */ + Mips_NLZC_H /* 2441 */, MIPS_INS_NLZC_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nlzc.w $wd, $ws */ + Mips_NLZC_W /* 2442 */, MIPS_INS_NLZC_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmadd.d $fd, $fr, $fs, $ft */ + Mips_NMADD_D32 /* 2443 */, MIPS_INS_NMADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, MIPS_FEATURE_NOTINMICROMIPS }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmadd.d $fd, $fr, $fs, $ft */ + Mips_NMADD_D32_MM /* 2444 */, MIPS_INS_NMADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmadd.d $fd, $fr, $fs, $ft */ + Mips_NMADD_D64 /* 2445 */, MIPS_INS_NMADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, MIPS_FEATURE_NOTINMICROMIPS }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmadd.s $fd, $fr, $fs, $ft */ + Mips_NMADD_S /* 2446 */, MIPS_INS_NMADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmadd.s $fd, $fr, $fs, $ft */ + Mips_NMADD_S_MM /* 2447 */, MIPS_INS_NMADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmsub.d $fd, $fr, $fs, $ft */ + Mips_NMSUB_D32 /* 2448 */, MIPS_INS_NMSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, MIPS_FEATURE_NOTINMICROMIPS }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmsub.d $fd, $fr, $fs, $ft */ + Mips_NMSUB_D32_MM /* 2449 */, MIPS_INS_NMSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmsub.d $fd, $fr, $fs, $ft */ + Mips_NMSUB_D64 /* 2450 */, MIPS_INS_NMSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, MIPS_FEATURE_NOTINMICROMIPS }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmsub.s $fd, $fr, $fs, $ft */ + Mips_NMSUB_S /* 2451 */, MIPS_INS_NMSUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmsub.s $fd, $fr, $fs, $ft */ + Mips_NMSUB_S_MM /* 2452 */, MIPS_INS_NMSUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nop32 */ + Mips_NOP32_NM /* 2453 */, MIPS_INS_NOP32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nop */ + Mips_NOP_NM /* 2454 */, MIPS_INS_NOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor $rd, $rs, $rt */ + Mips_NOR /* 2455 */, MIPS_INS_NOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor $rd, $rs, $rt */ + Mips_NOR64 /* 2456 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* nori.b $wd, $ws, $u8 */ + Mips_NORI_B /* 2457 */, MIPS_INS_NORI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor $rd, $rs, $rt */ + Mips_NOR_MM /* 2458 */, MIPS_INS_NOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor $rd, $rs, $rt */ + Mips_NOR_MMR6 /* 2459 */, MIPS_INS_NOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor $rd, $rs, $rt */ + Mips_NOR_NM /* 2460 */, MIPS_INS_NOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor.v $wd, $ws, $wt */ + Mips_NOR_V /* 2461 */, MIPS_INS_NOR_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* not16 $rt, $rs */ + Mips_NOT16_MM /* 2462 */, MIPS_INS_NOT16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* not16 $rt, $rs */ + Mips_NOT16_MMR6 /* 2463 */, MIPS_INS_NOT16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* not $rt, $rs */ + Mips_NOT16_NM /* 2464 */, MIPS_INS_NOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg $rx, $ry */ + Mips_NegRxRy16 /* 2465 */, MIPS_INS_NEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* not $rx, $ry */ + Mips_NotRxRy16 /* 2466 */, MIPS_INS_NOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $rd, $rs, $rt */ + Mips_OR /* 2467 */, MIPS_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or16 $rt, $rs */ + Mips_OR16_MM /* 2468 */, MIPS_INS_OR16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or16 $rt, $rs */ + Mips_OR16_MMR6 /* 2469 */, MIPS_INS_OR16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $dst, $rs, $rt */ + Mips_OR16_NM /* 2470 */, MIPS_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $rd, $rs, $rt */ + Mips_OR64 /* 2471 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* ori.b $wd, $ws, $u8 */ + Mips_ORI_B /* 2472 */, MIPS_INS_ORI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ori $rt, $rs, $imm16 */ + Mips_ORI_MMR6 /* 2473 */, MIPS_INS_ORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ori $rt, $rs, $imm */ + Mips_ORI_NM /* 2474 */, MIPS_INS_ORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $rd, $rs, $rt */ + Mips_OR_MM /* 2475 */, MIPS_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $rd, $rs, $rt */ + Mips_OR_MMR6 /* 2476 */, MIPS_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $rd, $rs, $rt */ + Mips_OR_NM /* 2477 */, MIPS_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or.v $wd, $ws, $wt */ + Mips_OR_V /* 2478 */, MIPS_INS_OR_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ori $rt, $rs, $imm16 */ + Mips_ORi /* 2479 */, MIPS_INS_ORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ori $rt, $rs, $imm16 */ + Mips_ORi64 /* 2480 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* ori $rt, $rs, $imm16 */ + Mips_ORi_MM /* 2481 */, MIPS_INS_ORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $rz, $ry */ + Mips_OrRxRxRy16 /* 2482 */, MIPS_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* packrl.ph $rd, $rs, $rt */ + Mips_PACKRL_PH /* 2483 */, MIPS_INS_PACKRL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* packrl.ph $rd, $rs, $rt */ + Mips_PACKRL_PH_MM /* 2484 */, MIPS_INS_PACKRL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pause */ + Mips_PAUSE /* 2485 */, MIPS_INS_PAUSE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pause */ + Mips_PAUSE_MM /* 2486 */, MIPS_INS_PAUSE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pause */ + Mips_PAUSE_MMR6 /* 2487 */, MIPS_INS_PAUSE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pause */ + Mips_PAUSE_NM /* 2488 */, MIPS_INS_PAUSE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckev.b $wd, $ws, $wt */ + Mips_PCKEV_B /* 2489 */, MIPS_INS_PCKEV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckev.d $wd, $ws, $wt */ + Mips_PCKEV_D /* 2490 */, MIPS_INS_PCKEV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckev.h $wd, $ws, $wt */ + Mips_PCKEV_H /* 2491 */, MIPS_INS_PCKEV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckev.w $wd, $ws, $wt */ + Mips_PCKEV_W /* 2492 */, MIPS_INS_PCKEV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckod.b $wd, $ws, $wt */ + Mips_PCKOD_B /* 2493 */, MIPS_INS_PCKOD_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckod.d $wd, $ws, $wt */ + Mips_PCKOD_D /* 2494 */, MIPS_INS_PCKOD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckod.h $wd, $ws, $wt */ + Mips_PCKOD_H /* 2495 */, MIPS_INS_PCKOD_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckod.w $wd, $ws, $wt */ + Mips_PCKOD_W /* 2496 */, MIPS_INS_PCKOD_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pcnt.b $wd, $ws */ + Mips_PCNT_B /* 2497 */, MIPS_INS_PCNT_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pcnt.d $wd, $ws */ + Mips_PCNT_D /* 2498 */, MIPS_INS_PCNT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pcnt.h $wd, $ws */ + Mips_PCNT_H /* 2499 */, MIPS_INS_PCNT_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pcnt.w $wd, $ws */ + Mips_PCNT_W /* 2500 */, MIPS_INS_PCNT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pick.ph $rd, $rs, $rt */ + Mips_PICK_PH /* 2501 */, MIPS_INS_PICK_PH, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pick.ph $rd, $rs, $rt */ + Mips_PICK_PH_MM /* 2502 */, MIPS_INS_PICK_PH, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pick.qb $rd, $rs, $rt */ + Mips_PICK_QB /* 2503 */, MIPS_INS_PICK_QB, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pick.qb $rd, $rs, $rt */ + Mips_PICK_QB_MM /* 2504 */, MIPS_INS_PICK_QB, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pll.ps $fd, $fs, $ft */ + Mips_PLL_PS64 /* 2505 */, MIPS_INS_PLL_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* plu.ps $fd, $fs, $ft */ + Mips_PLU_PS64 /* 2506 */, MIPS_INS_PLU_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pop $rd, $rs */ + Mips_POP /* 2507 */, MIPS_INS_POP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbl $rd, $rt */ + Mips_PRECEQU_PH_QBL /* 2508 */, MIPS_INS_PRECEQU_PH_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbla $rd, $rt */ + Mips_PRECEQU_PH_QBLA /* 2509 */, MIPS_INS_PRECEQU_PH_QBLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbla $rt, $rs */ + Mips_PRECEQU_PH_QBLA_MM /* 2510 */, MIPS_INS_PRECEQU_PH_QBLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbl $rt, $rs */ + Mips_PRECEQU_PH_QBL_MM /* 2511 */, MIPS_INS_PRECEQU_PH_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbr $rd, $rt */ + Mips_PRECEQU_PH_QBR /* 2512 */, MIPS_INS_PRECEQU_PH_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbra $rd, $rt */ + Mips_PRECEQU_PH_QBRA /* 2513 */, MIPS_INS_PRECEQU_PH_QBRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbra $rt, $rs */ + Mips_PRECEQU_PH_QBRA_MM /* 2514 */, MIPS_INS_PRECEQU_PH_QBRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbr $rt, $rs */ + Mips_PRECEQU_PH_QBR_MM /* 2515 */, MIPS_INS_PRECEQU_PH_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceq.w.phl $rd, $rt */ + Mips_PRECEQ_W_PHL /* 2516 */, MIPS_INS_PRECEQ_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceq.w.phl $rt, $rs */ + Mips_PRECEQ_W_PHL_MM /* 2517 */, MIPS_INS_PRECEQ_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceq.w.phr $rd, $rt */ + Mips_PRECEQ_W_PHR /* 2518 */, MIPS_INS_PRECEQ_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceq.w.phr $rt, $rs */ + Mips_PRECEQ_W_PHR_MM /* 2519 */, MIPS_INS_PRECEQ_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbl $rd, $rt */ + Mips_PRECEU_PH_QBL /* 2520 */, MIPS_INS_PRECEU_PH_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbla $rd, $rt */ + Mips_PRECEU_PH_QBLA /* 2521 */, MIPS_INS_PRECEU_PH_QBLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbla $rt, $rs */ + Mips_PRECEU_PH_QBLA_MM /* 2522 */, MIPS_INS_PRECEU_PH_QBLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbl $rt, $rs */ + Mips_PRECEU_PH_QBL_MM /* 2523 */, MIPS_INS_PRECEU_PH_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbr $rd, $rt */ + Mips_PRECEU_PH_QBR /* 2524 */, MIPS_INS_PRECEU_PH_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbra $rd, $rt */ + Mips_PRECEU_PH_QBRA /* 2525 */, MIPS_INS_PRECEU_PH_QBRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbra $rt, $rs */ + Mips_PRECEU_PH_QBRA_MM /* 2526 */, MIPS_INS_PRECEU_PH_QBRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbr $rt, $rs */ + Mips_PRECEU_PH_QBR_MM /* 2527 */, MIPS_INS_PRECEU_PH_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrqu_s.qb.ph $rd, $rs, $rt */ + Mips_PRECRQU_S_QB_PH /* 2528 */, MIPS_INS_PRECRQU_S_QB_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrqu_s.qb.ph $rd, $rs, $rt */ + Mips_PRECRQU_S_QB_PH_MM /* 2529 */, MIPS_INS_PRECRQU_S_QB_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrq.ph.w $rd, $rs, $rt */ + Mips_PRECRQ_PH_W /* 2530 */, MIPS_INS_PRECRQ_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrq.ph.w $rd, $rs, $rt */ + Mips_PRECRQ_PH_W_MM /* 2531 */, MIPS_INS_PRECRQ_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrq.qb.ph $rd, $rs, $rt */ + Mips_PRECRQ_QB_PH /* 2532 */, MIPS_INS_PRECRQ_QB_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrq.qb.ph $rd, $rs, $rt */ + Mips_PRECRQ_QB_PH_MM /* 2533 */, MIPS_INS_PRECRQ_QB_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrq_rs.ph.w $rd, $rs, $rt */ + Mips_PRECRQ_RS_PH_W /* 2534 */, MIPS_INS_PRECRQ_RS_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrq_rs.ph.w $rd, $rs, $rt */ + Mips_PRECRQ_RS_PH_W_MM /* 2535 */, MIPS_INS_PRECRQ_RS_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precr.qb.ph $rd, $rs, $rt */ + Mips_PRECR_QB_PH /* 2536 */, MIPS_INS_PRECR_QB_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precr.qb.ph $rd, $rs, $rt */ + Mips_PRECR_QB_PH_MMR2 /* 2537 */, MIPS_INS_PRECR_QB_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precr_sra.ph.w $rt, $rs, $sa */ + Mips_PRECR_SRA_PH_W /* 2538 */, MIPS_INS_PRECR_SRA_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precr_sra.ph.w $rt, $rs, $sa */ + Mips_PRECR_SRA_PH_W_MMR2 /* 2539 */, MIPS_INS_PRECR_SRA_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precr_sra_r.ph.w $rt, $rs, $sa */ + Mips_PRECR_SRA_R_PH_W /* 2540 */, MIPS_INS_PRECR_SRA_R_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precr_sra_r.ph.w $rt, $rs, $sa */ + Mips_PRECR_SRA_R_PH_W_MMR2 /* 2541 */, MIPS_INS_PRECR_SRA_R_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pref $hint, $addr */ + Mips_PREF /* 2542 */, MIPS_INS_PREF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* prefe $hint, $addr */ + Mips_PREFE /* 2543 */, MIPS_INS_PREFE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* prefe $hint, $addr */ + Mips_PREFE_MM /* 2544 */, MIPS_INS_PREFE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* prefx $hint, ${index}(${base}) */ + Mips_PREFX_MM /* 2545 */, MIPS_INS_PREFX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pref $hint, $addr */ + Mips_PREF_MM /* 2546 */, MIPS_INS_PREF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pref $hint, $addr */ + Mips_PREF_MMR6 /* 2547 */, MIPS_INS_PREF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pref $op, $addr */ + Mips_PREF_NM /* 2548 */, MIPS_INS_PREF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pref $hint, $addr */ + Mips_PREF_R6 /* 2549 */, MIPS_INS_PREF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pref $op, $addr */ + Mips_PREFs9_NM /* 2550 */, MIPS_INS_PREF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* prepend $rt, $rs, $sa */ + Mips_PREPEND /* 2551 */, MIPS_INS_PREPEND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* prepend $rt, $rs, $sa */ + Mips_PREPEND_MMR2 /* 2552 */, MIPS_INS_PREPEND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pul.ps $fd, $fs, $ft */ + Mips_PUL_PS64 /* 2553 */, MIPS_INS_PUL_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* puu.ps $fd, $fs, $ft */ + Mips_PUU_PS64 /* 2554 */, MIPS_INS_PUU_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* raddu.w.qb $rd, $rs */ + Mips_RADDU_W_QB /* 2555 */, MIPS_INS_RADDU_W_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* raddu.w.qb $rt, $rs */ + Mips_RADDU_W_QB_MM /* 2556 */, MIPS_INS_RADDU_W_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rddsp $rd, $mask */ + Mips_RDDSP /* 2557 */, MIPS_INS_RDDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rddsp $rt, $mask */ + Mips_RDDSP_MM /* 2558 */, MIPS_INS_RDDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rdhwr $rt, $rd, $sel */ + Mips_RDHWR /* 2559 */, MIPS_INS_RDHWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rdhwr $rt, $rd, $sel */ + Mips_RDHWR64 /* 2560 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* rdhwr $rt, $rd, $sel */ + Mips_RDHWR_MM /* 2561 */, MIPS_INS_RDHWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rdhwr $rt, $rs, $sel */ + Mips_RDHWR_MMR6 /* 2562 */, MIPS_INS_RDHWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rdhwr $rt, $hs, $sel */ + Mips_RDHWR_NM /* 2563 */, MIPS_INS_RDHWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rdpgpr $rt, $rd */ + Mips_RDPGPR_MMR6 /* 2564 */, MIPS_INS_RDPGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rdpgpr $rt, $rs */ + Mips_RDPGPR_NM /* 2565 */, MIPS_INS_RDPGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* recip.d $fd, $fs */ + Mips_RECIP_D32 /* 2566 */, MIPS_INS_RECIP_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* recip.d $fd, $fs */ + Mips_RECIP_D32_MM /* 2567 */, MIPS_INS_RECIP_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* recip.d $fd, $fs */ + Mips_RECIP_D64 /* 2568 */, MIPS_INS_RECIP_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* recip.d $fd, $fs */ + Mips_RECIP_D64_MM /* 2569 */, MIPS_INS_RECIP_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* recip.s $fd, $fs */ + Mips_RECIP_S /* 2570 */, MIPS_INS_RECIP_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* recip.s $fd, $fs */ + Mips_RECIP_S_MM /* 2571 */, MIPS_INS_RECIP_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* replv.ph $rd, $rt */ + Mips_REPLV_PH /* 2572 */, MIPS_INS_REPLV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* replv.ph $rt, $rs */ + Mips_REPLV_PH_MM /* 2573 */, MIPS_INS_REPLV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* replv.qb $rd, $rt */ + Mips_REPLV_QB /* 2574 */, MIPS_INS_REPLV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* replv.qb $rt, $rs */ + Mips_REPLV_QB_MM /* 2575 */, MIPS_INS_REPLV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* repl.ph $rd, $imm */ + Mips_REPL_PH /* 2576 */, MIPS_INS_REPL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* repl.ph $rd, $imm */ + Mips_REPL_PH_MM /* 2577 */, MIPS_INS_REPL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* repl.qb $rd, $imm */ + Mips_REPL_QB /* 2578 */, MIPS_INS_REPL_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* repl.qb $rt, $imm */ + Mips_REPL_QB_MM /* 2579 */, MIPS_INS_REPL_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* restore.jrc $adj$regs */ + Mips_RESTOREJRC16_NM /* 2580 */, MIPS_INS_RESTORE_JRC, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP_NM, 0 }, { MIPS_REG_SP_NM, 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* restore.jrc $adj$regs */ + Mips_RESTOREJRC_NM /* 2581 */, MIPS_INS_RESTORE_JRC, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP_NM, 0 }, { MIPS_REG_SP_NM, 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* restore $adj$regs */ + Mips_RESTORE_NM /* 2582 */, MIPS_INS_RESTORE, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP_NM, 0 }, { MIPS_REG_SP_NM, 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rint.d $fd, $fs */ + Mips_RINT_D /* 2583 */, MIPS_INS_RINT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rint.d $fd, $fs */ + Mips_RINT_D_MMR6 /* 2584 */, MIPS_INS_RINT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rint.s $fd, $fs */ + Mips_RINT_S /* 2585 */, MIPS_INS_RINT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rint.s $fd, $fs */ + Mips_RINT_S_MMR6 /* 2586 */, MIPS_INS_RINT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotr $rd, $rt, $shamt */ + Mips_ROTR /* 2587 */, MIPS_INS_ROTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotrv $rd, $rt, $rs */ + Mips_ROTRV /* 2588 */, MIPS_INS_ROTRV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotrv $rd, $rt, $rs */ + Mips_ROTRV_MM /* 2589 */, MIPS_INS_ROTRV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotrv $rd, $rs, $rt */ + Mips_ROTRV_NM /* 2590 */, MIPS_INS_ROTRV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotr $rd, $rt, $shamt */ + Mips_ROTR_MM /* 2591 */, MIPS_INS_ROTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotr $rt, $rs, $imm */ + Mips_ROTR_NM /* 2592 */, MIPS_INS_ROTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotx $rt, $rs, $shift, $shiftx, $stripe */ + Mips_ROTX_NM /* 2593 */, MIPS_INS_ROTX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.l.d $fd, $fs */ + Mips_ROUND_L_D64 /* 2594 */, MIPS_INS_ROUND_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.l.d $ft, $fs */ + Mips_ROUND_L_D_MMR6 /* 2595 */, MIPS_INS_ROUND_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.l.s $fd, $fs */ + Mips_ROUND_L_S /* 2596 */, MIPS_INS_ROUND_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.l.s $ft, $fs */ + Mips_ROUND_L_S_MMR6 /* 2597 */, MIPS_INS_ROUND_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.d $fd, $fs */ + Mips_ROUND_W_D32 /* 2598 */, MIPS_INS_ROUND_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.d $fd, $fs */ + Mips_ROUND_W_D64 /* 2599 */, MIPS_INS_ROUND_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.d $ft, $fs */ + Mips_ROUND_W_D_MMR6 /* 2600 */, MIPS_INS_ROUND_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.d $fd, $fs */ + Mips_ROUND_W_MM /* 2601 */, MIPS_INS_ROUND_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.s $fd, $fs */ + Mips_ROUND_W_S /* 2602 */, MIPS_INS_ROUND_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.s $fd, $fs */ + Mips_ROUND_W_S_MM /* 2603 */, MIPS_INS_ROUND_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.s $ft, $fs */ + Mips_ROUND_W_S_MMR6 /* 2604 */, MIPS_INS_ROUND_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rsqrt.d $fd, $fs */ + Mips_RSQRT_D32 /* 2605 */, MIPS_INS_RSQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rsqrt.d $fd, $fs */ + Mips_RSQRT_D32_MM /* 2606 */, MIPS_INS_RSQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rsqrt.d $fd, $fs */ + Mips_RSQRT_D64 /* 2607 */, MIPS_INS_RSQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rsqrt.d $fd, $fs */ + Mips_RSQRT_D64_MM /* 2608 */, MIPS_INS_RSQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rsqrt.s $fd, $fs */ + Mips_RSQRT_S /* 2609 */, MIPS_INS_RSQRT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rsqrt.s $fd, $fs */ + Mips_RSQRT_S_MM /* 2610 */, MIPS_INS_RSQRT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_Restore16 /* 2611 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_RestoreX16 /* 2612 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* saa $rt, (${rs}) */ + Mips_SAA /* 2613 */, MIPS_INS_SAA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* saad $rt, (${rs}) */ + Mips_SAAD /* 2614 */, MIPS_INS_SAAD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_s.b $wd, $ws, $m */ + Mips_SAT_S_B /* 2615 */, MIPS_INS_SAT_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_s.d $wd, $ws, $m */ + Mips_SAT_S_D /* 2616 */, MIPS_INS_SAT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_s.h $wd, $ws, $m */ + Mips_SAT_S_H /* 2617 */, MIPS_INS_SAT_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_s.w $wd, $ws, $m */ + Mips_SAT_S_W /* 2618 */, MIPS_INS_SAT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_u.b $wd, $ws, $m */ + Mips_SAT_U_B /* 2619 */, MIPS_INS_SAT_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_u.d $wd, $ws, $m */ + Mips_SAT_U_D /* 2620 */, MIPS_INS_SAT_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_u.h $wd, $ws, $m */ + Mips_SAT_U_H /* 2621 */, MIPS_INS_SAT_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_u.w $wd, $ws, $m */ + Mips_SAT_U_W /* 2622 */, MIPS_INS_SAT_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* save $adj$regs */ + Mips_SAVE16_NM /* 2623 */, MIPS_INS_SAVE, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP_NM, 0 }, { MIPS_REG_SP_NM, 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* save $adj$regs */ + Mips_SAVE_NM /* 2624 */, MIPS_INS_SAVE, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP_NM, 0 }, { MIPS_REG_SP_NM, 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SB /* 2625 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb16 $rt, $addr */ + Mips_SB16_MM /* 2626 */, MIPS_INS_SB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb16 $rt, $addr */ + Mips_SB16_MMR6 /* 2627 */, MIPS_INS_SB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SB16_NM /* 2628 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SB64 /* 2629 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sbe $rt, $addr */ + Mips_SBE /* 2630 */, MIPS_INS_SBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sbe $rt, $addr */ + Mips_SBE_MM /* 2631 */, MIPS_INS_SBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SBGP_NM /* 2632 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sbx $rt, $addr */ + Mips_SBX_NM /* 2633 */, MIPS_INS_SBX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SB_MM /* 2634 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SB_MMR6 /* 2635 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SB_NM /* 2636 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SBs9_NM /* 2637 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC /* 2638 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR32BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC64 /* 2639 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC64_R6 /* 2640 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR64BIT, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* scd $rt, $addr */ + Mips_SCD /* 2641 */, MIPS_INS_SCD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* scd $rt, $addr */ + Mips_SCD_R6 /* 2642 */, MIPS_INS_SCD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sce $rt, $addr */ + Mips_SCE /* 2643 */, MIPS_INS_SCE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sce $rt, $addr */ + Mips_SCE_MM /* 2644 */, MIPS_INS_SCE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* scwp $rt, $ru, $addr */ + Mips_SCWP_NM /* 2645 */, MIPS_INS_SCWP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC_MM /* 2646 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC_MMR6 /* 2647 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC_NM /* 2648 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC_R6 /* 2649 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR32BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sd $rt, $addr */ + Mips_SD /* 2650 */, MIPS_INS_SD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp $code_ */ + Mips_SDBBP /* 2651 */, MIPS_INS_SDBBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp16 $code_ */ + Mips_SDBBP16_MM /* 2652 */, MIPS_INS_SDBBP16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp16 $code_ */ + Mips_SDBBP16_MMR6 /* 2653 */, MIPS_INS_SDBBP16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp $imm */ + Mips_SDBBP16_NM /* 2654 */, MIPS_INS_SDBBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp $code_ */ + Mips_SDBBP_MM /* 2655 */, MIPS_INS_SDBBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp $code_ */ + Mips_SDBBP_MMR6 /* 2656 */, MIPS_INS_SDBBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp $imm */ + Mips_SDBBP_NM /* 2657 */, MIPS_INS_SDBBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp $code_ */ + Mips_SDBBP_R6 /* 2658 */, MIPS_INS_SDBBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc1 $rt, $addr */ + Mips_SDC1 /* 2659 */, MIPS_INS_SDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc1 $rt, $addr */ + Mips_SDC164 /* 2660 */, MIPS_INS_SDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc1 $ft, $addr */ + Mips_SDC1_D64_MMR6 /* 2661 */, MIPS_INS_SDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc1 $rt, $addr */ + Mips_SDC1_MM_D32 /* 2662 */, MIPS_INS_SDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc1 $rt, $addr */ + Mips_SDC1_MM_D64 /* 2663 */, MIPS_INS_SDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc2 $rt, $addr */ + Mips_SDC2 /* 2664 */, MIPS_INS_SDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc2 $rt, $addr */ + Mips_SDC2_MMR6 /* 2665 */, MIPS_INS_SDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc2 $rt, $addr */ + Mips_SDC2_R6 /* 2666 */, MIPS_INS_SDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc3 $rt, $addr */ + Mips_SDC3 /* 2667 */, MIPS_INS_SDC3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $$zero, $rs, $rt */ + Mips_SDIV /* 2668 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $$zero, $rs, $rt */ + Mips_SDIV_MM /* 2669 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdl $rt, $addr */ + Mips_SDL /* 2670 */, MIPS_INS_SDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdr $rt, $addr */ + Mips_SDR /* 2671 */, MIPS_INS_SDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdxc1 $fs, ${index}(${base}) */ + Mips_SDXC1 /* 2672 */, MIPS_INS_SDXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdxc1 $fs, ${index}(${base}) */ + Mips_SDXC164 /* 2673 */, MIPS_INS_SDXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seb $rd, $rt */ + Mips_SEB /* 2674 */, MIPS_INS_SEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seb $rd, $rt */ + Mips_SEB64 /* 2675 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* seb $rd, $rt */ + Mips_SEB_MM /* 2676 */, MIPS_INS_SEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seb $rt, $rs */ + Mips_SEB_NM /* 2677 */, MIPS_INS_SEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seh $rd, $rt */ + Mips_SEH /* 2678 */, MIPS_INS_SEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seh $rd, $rt */ + Mips_SEH64 /* 2679 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* seh $rd, $rt */ + Mips_SEH_MM /* 2680 */, MIPS_INS_SEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seh $rt, $rs */ + Mips_SEH_NM /* 2681 */, MIPS_INS_SEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz $rd, $rs, $rt */ + Mips_SELEQZ /* 2682 */, MIPS_INS_SELEQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz $rd, $rs, $rt */ + Mips_SELEQZ64 /* 2683 */, MIPS_INS_SELEQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz.d $fd, $fs, $ft */ + Mips_SELEQZ_D /* 2684 */, MIPS_INS_SELEQZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz.d $fd, $fs, $ft */ + Mips_SELEQZ_D_MMR6 /* 2685 */, MIPS_INS_SELEQZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz $rd, $rs, $rt */ + Mips_SELEQZ_MMR6 /* 2686 */, MIPS_INS_SELEQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz.s $fd, $fs, $ft */ + Mips_SELEQZ_S /* 2687 */, MIPS_INS_SELEQZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz.s $fd, $fs, $ft */ + Mips_SELEQZ_S_MMR6 /* 2688 */, MIPS_INS_SELEQZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez $rd, $rs, $rt */ + Mips_SELNEZ /* 2689 */, MIPS_INS_SELNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez $rd, $rs, $rt */ + Mips_SELNEZ64 /* 2690 */, MIPS_INS_SELNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez.d $fd, $fs, $ft */ + Mips_SELNEZ_D /* 2691 */, MIPS_INS_SELNEZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez.d $fd, $fs, $ft */ + Mips_SELNEZ_D_MMR6 /* 2692 */, MIPS_INS_SELNEZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez $rd, $rs, $rt */ + Mips_SELNEZ_MMR6 /* 2693 */, MIPS_INS_SELNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez.s $fd, $fs, $ft */ + Mips_SELNEZ_S /* 2694 */, MIPS_INS_SELNEZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez.s $fd, $fs, $ft */ + Mips_SELNEZ_S_MMR6 /* 2695 */, MIPS_INS_SELNEZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sel.d $fd, $fs, $ft */ + Mips_SEL_D /* 2696 */, MIPS_INS_SEL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sel.d $fd, $fs, $ft */ + Mips_SEL_D_MMR6 /* 2697 */, MIPS_INS_SEL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sel.s $fd, $fs, $ft */ + Mips_SEL_S /* 2698 */, MIPS_INS_SEL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sel.s $fd, $fs, $ft */ + Mips_SEL_S_MMR6 /* 2699 */, MIPS_INS_SEL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seq $rd, $rs, $rt */ + Mips_SEQ /* 2700 */, MIPS_INS_SEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seqi $rt, $rs, $imm */ + Mips_SEQI_NM /* 2701 */, MIPS_INS_SEQI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seqi $rt, $rs, $imm10 */ + Mips_SEQi /* 2702 */, MIPS_INS_SEQI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SH /* 2703 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh16 $rt, $addr */ + Mips_SH16_MM /* 2704 */, MIPS_INS_SH16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh16 $rt, $addr */ + Mips_SH16_MMR6 /* 2705 */, MIPS_INS_SH16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SH16_NM /* 2706 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SH64 /* 2707 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* she $rt, $addr */ + Mips_SHE /* 2708 */, MIPS_INS_SHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* she $rt, $addr */ + Mips_SHE_MM /* 2709 */, MIPS_INS_SHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shf.b $wd, $ws, $u8 */ + Mips_SHF_B /* 2710 */, MIPS_INS_SHF_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shf.h $wd, $ws, $u8 */ + Mips_SHF_H /* 2711 */, MIPS_INS_SHF_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shf.w $wd, $ws, $u8 */ + Mips_SHF_W /* 2712 */, MIPS_INS_SHF_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SHGP_NM /* 2713 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shilo $ac, $shift */ + Mips_SHILO /* 2714 */, MIPS_INS_SHILO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shilov $ac, $rs */ + Mips_SHILOV /* 2715 */, MIPS_INS_SHILOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shilov $ac, $rs */ + Mips_SHILOV_MM /* 2716 */, MIPS_INS_SHILOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shilo $ac, $shift */ + Mips_SHILO_MM /* 2717 */, MIPS_INS_SHILO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv.ph $rd, $rt, $rs_sa */ + Mips_SHLLV_PH /* 2718 */, MIPS_INS_SHLLV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv.ph $rd, $rt, $rs */ + Mips_SHLLV_PH_MM /* 2719 */, MIPS_INS_SHLLV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv.qb $rd, $rt, $rs_sa */ + Mips_SHLLV_QB /* 2720 */, MIPS_INS_SHLLV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv.qb $rd, $rt, $rs */ + Mips_SHLLV_QB_MM /* 2721 */, MIPS_INS_SHLLV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv_s.ph $rd, $rt, $rs_sa */ + Mips_SHLLV_S_PH /* 2722 */, MIPS_INS_SHLLV_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv_s.ph $rd, $rt, $rs */ + Mips_SHLLV_S_PH_MM /* 2723 */, MIPS_INS_SHLLV_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv_s.w $rd, $rt, $rs_sa */ + Mips_SHLLV_S_W /* 2724 */, MIPS_INS_SHLLV_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv_s.w $rd, $rt, $rs */ + Mips_SHLLV_S_W_MM /* 2725 */, MIPS_INS_SHLLV_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll.ph $rd, $rt, $rs_sa */ + Mips_SHLL_PH /* 2726 */, MIPS_INS_SHLL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll.ph $rt, $rs, $sa */ + Mips_SHLL_PH_MM /* 2727 */, MIPS_INS_SHLL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll.qb $rd, $rt, $rs_sa */ + Mips_SHLL_QB /* 2728 */, MIPS_INS_SHLL_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll.qb $rt, $rs, $sa */ + Mips_SHLL_QB_MM /* 2729 */, MIPS_INS_SHLL_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll_s.ph $rd, $rt, $rs_sa */ + Mips_SHLL_S_PH /* 2730 */, MIPS_INS_SHLL_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll_s.ph $rt, $rs, $sa */ + Mips_SHLL_S_PH_MM /* 2731 */, MIPS_INS_SHLL_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll_s.w $rd, $rt, $rs_sa */ + Mips_SHLL_S_W /* 2732 */, MIPS_INS_SHLL_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll_s.w $rt, $rs, $sa */ + Mips_SHLL_S_W_MM /* 2733 */, MIPS_INS_SHLL_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav.ph $rd, $rt, $rs_sa */ + Mips_SHRAV_PH /* 2734 */, MIPS_INS_SHRAV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav.ph $rd, $rt, $rs */ + Mips_SHRAV_PH_MM /* 2735 */, MIPS_INS_SHRAV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav.qb $rd, $rt, $rs_sa */ + Mips_SHRAV_QB /* 2736 */, MIPS_INS_SHRAV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav.qb $rd, $rt, $rs */ + Mips_SHRAV_QB_MMR2 /* 2737 */, MIPS_INS_SHRAV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav_r.ph $rd, $rt, $rs_sa */ + Mips_SHRAV_R_PH /* 2738 */, MIPS_INS_SHRAV_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav_r.ph $rd, $rt, $rs */ + Mips_SHRAV_R_PH_MM /* 2739 */, MIPS_INS_SHRAV_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav_r.qb $rd, $rt, $rs_sa */ + Mips_SHRAV_R_QB /* 2740 */, MIPS_INS_SHRAV_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav_r.qb $rd, $rt, $rs */ + Mips_SHRAV_R_QB_MMR2 /* 2741 */, MIPS_INS_SHRAV_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav_r.w $rd, $rt, $rs_sa */ + Mips_SHRAV_R_W /* 2742 */, MIPS_INS_SHRAV_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav_r.w $rd, $rt, $rs */ + Mips_SHRAV_R_W_MM /* 2743 */, MIPS_INS_SHRAV_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra.ph $rd, $rt, $rs_sa */ + Mips_SHRA_PH /* 2744 */, MIPS_INS_SHRA_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra.ph $rt, $rs, $sa */ + Mips_SHRA_PH_MM /* 2745 */, MIPS_INS_SHRA_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra.qb $rd, $rt, $rs_sa */ + Mips_SHRA_QB /* 2746 */, MIPS_INS_SHRA_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra.qb $rt, $rs, $sa */ + Mips_SHRA_QB_MMR2 /* 2747 */, MIPS_INS_SHRA_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra_r.ph $rd, $rt, $rs_sa */ + Mips_SHRA_R_PH /* 2748 */, MIPS_INS_SHRA_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra_r.ph $rt, $rs, $sa */ + Mips_SHRA_R_PH_MM /* 2749 */, MIPS_INS_SHRA_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra_r.qb $rd, $rt, $rs_sa */ + Mips_SHRA_R_QB /* 2750 */, MIPS_INS_SHRA_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra_r.qb $rt, $rs, $sa */ + Mips_SHRA_R_QB_MMR2 /* 2751 */, MIPS_INS_SHRA_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra_r.w $rd, $rt, $rs_sa */ + Mips_SHRA_R_W /* 2752 */, MIPS_INS_SHRA_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra_r.w $rt, $rs, $sa */ + Mips_SHRA_R_W_MM /* 2753 */, MIPS_INS_SHRA_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrlv.ph $rd, $rt, $rs_sa */ + Mips_SHRLV_PH /* 2754 */, MIPS_INS_SHRLV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrlv.ph $rd, $rt, $rs */ + Mips_SHRLV_PH_MMR2 /* 2755 */, MIPS_INS_SHRLV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrlv.qb $rd, $rt, $rs_sa */ + Mips_SHRLV_QB /* 2756 */, MIPS_INS_SHRLV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrlv.qb $rd, $rt, $rs */ + Mips_SHRLV_QB_MM /* 2757 */, MIPS_INS_SHRLV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrl.ph $rd, $rt, $rs_sa */ + Mips_SHRL_PH /* 2758 */, MIPS_INS_SHRL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrl.ph $rt, $rs, $sa */ + Mips_SHRL_PH_MMR2 /* 2759 */, MIPS_INS_SHRL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrl.qb $rd, $rt, $rs_sa */ + Mips_SHRL_QB /* 2760 */, MIPS_INS_SHRL_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrl.qb $rt, $rs, $sa */ + Mips_SHRL_QB_MM /* 2761 */, MIPS_INS_SHRL_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shxs $rt, $addr */ + Mips_SHXS_NM /* 2762 */, MIPS_INS_SHXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shx $rt, $addr */ + Mips_SHX_NM /* 2763 */, MIPS_INS_SHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SH_MM /* 2764 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SH_MMR6 /* 2765 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SH_NM /* 2766 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SHs9_NM /* 2767 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sigrie $code_ */ + Mips_SIGRIE /* 2768 */, MIPS_INS_SIGRIE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sigrie $code_ */ + Mips_SIGRIE_MMR6 /* 2769 */, MIPS_INS_SIGRIE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sigrie $imm */ + Mips_SIGRIE_NM /* 2770 */, MIPS_INS_SIGRIE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sldi.b $wd, $ws[$n] */ + Mips_SLDI_B /* 2771 */, MIPS_INS_SLDI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sldi.d $wd, $ws[$n] */ + Mips_SLDI_D /* 2772 */, MIPS_INS_SLDI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sldi.h $wd, $ws[$n] */ + Mips_SLDI_H /* 2773 */, MIPS_INS_SLDI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sldi.w $wd, $ws[$n] */ + Mips_SLDI_W /* 2774 */, MIPS_INS_SLDI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sld.b $wd, $ws[$rt] */ + Mips_SLD_B /* 2775 */, MIPS_INS_SLD_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sld.d $wd, $ws[$rt] */ + Mips_SLD_D /* 2776 */, MIPS_INS_SLD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sld.h $wd, $ws[$rt] */ + Mips_SLD_H /* 2777 */, MIPS_INS_SLD_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sld.w $wd, $ws[$rt] */ + Mips_SLD_W /* 2778 */, MIPS_INS_SLD_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rd, $rt, $shamt */ + Mips_SLL /* 2779 */, MIPS_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll16 $rd, $rt, $shamt */ + Mips_SLL16_MM /* 2780 */, MIPS_INS_SLL16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll16 $rd, $rt, $shamt */ + Mips_SLL16_MMR6 /* 2781 */, MIPS_INS_SLL16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rt, $rs, $imm */ + Mips_SLL16_NM /* 2782 */, MIPS_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rd, $rt, 0 */ + Mips_SLL64_32 /* 2783 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sll $rd, $rt, 0 */ + Mips_SLL64_64 /* 2784 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slli.b $wd, $ws, $m */ + Mips_SLLI_B /* 2785 */, MIPS_INS_SLLI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slli.d $wd, $ws, $m */ + Mips_SLLI_D /* 2786 */, MIPS_INS_SLLI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slli.h $wd, $ws, $m */ + Mips_SLLI_H /* 2787 */, MIPS_INS_SLLI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slli.w $wd, $ws, $m */ + Mips_SLLI_W /* 2788 */, MIPS_INS_SLLI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sllv $rd, $rt, $rs */ + Mips_SLLV /* 2789 */, MIPS_INS_SLLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sllv $rd, $rt, $rs */ + Mips_SLLV_MM /* 2790 */, MIPS_INS_SLLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sllv $rd, $rs, $rt */ + Mips_SLLV_NM /* 2791 */, MIPS_INS_SLLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll.b $wd, $ws, $wt */ + Mips_SLL_B /* 2792 */, MIPS_INS_SLL_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll.d $wd, $ws, $wt */ + Mips_SLL_D /* 2793 */, MIPS_INS_SLL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll.h $wd, $ws, $wt */ + Mips_SLL_H /* 2794 */, MIPS_INS_SLL_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rd, $rt, $shamt */ + Mips_SLL_MM /* 2795 */, MIPS_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rd, $rt, $shamt */ + Mips_SLL_MMR6 /* 2796 */, MIPS_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rt, $rs, $imm */ + Mips_SLL_NM /* 2797 */, MIPS_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll.w $wd, $ws, $wt */ + Mips_SLL_W /* 2798 */, MIPS_INS_SLL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slt $rd, $rs, $rt */ + Mips_SLT /* 2799 */, MIPS_INS_SLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slt $rd, $rs, $rt */ + Mips_SLT64 /* 2800 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rt, $rs, $imm */ + Mips_SLTIU_NM /* 2801 */, MIPS_INS_SLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slti $rt, $rs, $imm */ + Mips_SLTI_NM /* 2802 */, MIPS_INS_SLTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltu $rd, $rs, $rt */ + Mips_SLTU_NM /* 2803 */, MIPS_INS_SLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slt $rd, $rs, $rt */ + Mips_SLT_MM /* 2804 */, MIPS_INS_SLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slt $rd, $rs, $rt */ + Mips_SLT_NM /* 2805 */, MIPS_INS_SLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slti $rt, $rs, $imm16 */ + Mips_SLTi /* 2806 */, MIPS_INS_SLTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slti $rt, $rs, $imm16 */ + Mips_SLTi64 /* 2807 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slti $rt, $rs, $imm16 */ + Mips_SLTi_MM /* 2808 */, MIPS_INS_SLTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltiu $rt, $rs, $imm16 */ + Mips_SLTiu /* 2809 */, MIPS_INS_SLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltiu $rt, $rs, $imm16 */ + Mips_SLTiu64 /* 2810 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rt, $rs, $imm16 */ + Mips_SLTiu_MM /* 2811 */, MIPS_INS_SLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltu $rd, $rs, $rt */ + Mips_SLTu /* 2812 */, MIPS_INS_SLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltu $rd, $rs, $rt */ + Mips_SLTu64 /* 2813 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rd, $rs, $rt */ + Mips_SLTu_MM /* 2814 */, MIPS_INS_SLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sne $rd, $rs, $rt */ + Mips_SNE /* 2815 */, MIPS_INS_SNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* snei $rt, $rs, $imm10 */ + Mips_SNEi /* 2816 */, MIPS_INS_SNEI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sov $rd, $rs, $rt */ + Mips_SOV_NM /* 2817 */, MIPS_INS_SOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splati.b $wd, $ws[$n] */ + Mips_SPLATI_B /* 2818 */, MIPS_INS_SPLATI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splati.d $wd, $ws[$n] */ + Mips_SPLATI_D /* 2819 */, MIPS_INS_SPLATI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splati.h $wd, $ws[$n] */ + Mips_SPLATI_H /* 2820 */, MIPS_INS_SPLATI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splati.w $wd, $ws[$n] */ + Mips_SPLATI_W /* 2821 */, MIPS_INS_SPLATI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splat.b $wd, $ws[$rt] */ + Mips_SPLAT_B /* 2822 */, MIPS_INS_SPLAT_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splat.d $wd, $ws[$rt] */ + Mips_SPLAT_D /* 2823 */, MIPS_INS_SPLAT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splat.h $wd, $ws[$rt] */ + Mips_SPLAT_H /* 2824 */, MIPS_INS_SPLAT_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splat.w $wd, $ws[$rt] */ + Mips_SPLAT_W /* 2825 */, MIPS_INS_SPLAT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra $rd, $rt, $shamt */ + Mips_SRA /* 2826 */, MIPS_INS_SRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srai.b $wd, $ws, $m */ + Mips_SRAI_B /* 2827 */, MIPS_INS_SRAI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srai.d $wd, $ws, $m */ + Mips_SRAI_D /* 2828 */, MIPS_INS_SRAI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srai.h $wd, $ws, $m */ + Mips_SRAI_H /* 2829 */, MIPS_INS_SRAI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srai.w $wd, $ws, $m */ + Mips_SRAI_W /* 2830 */, MIPS_INS_SRAI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srari.b $wd, $ws, $m */ + Mips_SRARI_B /* 2831 */, MIPS_INS_SRARI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srari.d $wd, $ws, $m */ + Mips_SRARI_D /* 2832 */, MIPS_INS_SRARI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srari.h $wd, $ws, $m */ + Mips_SRARI_H /* 2833 */, MIPS_INS_SRARI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srari.w $wd, $ws, $m */ + Mips_SRARI_W /* 2834 */, MIPS_INS_SRARI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srar.b $wd, $ws, $wt */ + Mips_SRAR_B /* 2835 */, MIPS_INS_SRAR_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srar.d $wd, $ws, $wt */ + Mips_SRAR_D /* 2836 */, MIPS_INS_SRAR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srar.h $wd, $ws, $wt */ + Mips_SRAR_H /* 2837 */, MIPS_INS_SRAR_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srar.w $wd, $ws, $wt */ + Mips_SRAR_W /* 2838 */, MIPS_INS_SRAR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srav $rd, $rt, $rs */ + Mips_SRAV /* 2839 */, MIPS_INS_SRAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srav $rd, $rt, $rs */ + Mips_SRAV_MM /* 2840 */, MIPS_INS_SRAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srav $rd, $rs, $rt */ + Mips_SRAV_NM /* 2841 */, MIPS_INS_SRAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra.b $wd, $ws, $wt */ + Mips_SRA_B /* 2842 */, MIPS_INS_SRA_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra.d $wd, $ws, $wt */ + Mips_SRA_D /* 2843 */, MIPS_INS_SRA_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra.h $wd, $ws, $wt */ + Mips_SRA_H /* 2844 */, MIPS_INS_SRA_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra $rd, $rt, $shamt */ + Mips_SRA_MM /* 2845 */, MIPS_INS_SRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra $rt, $rs, $imm */ + Mips_SRA_NM /* 2846 */, MIPS_INS_SRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra.w $wd, $ws, $wt */ + Mips_SRA_W /* 2847 */, MIPS_INS_SRA_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl $rd, $rt, $shamt */ + Mips_SRL /* 2848 */, MIPS_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl16 $rd, $rt, $shamt */ + Mips_SRL16_MM /* 2849 */, MIPS_INS_SRL16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl16 $rd, $rt, $shamt */ + Mips_SRL16_MMR6 /* 2850 */, MIPS_INS_SRL16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl $rt, $rs, $imm */ + Mips_SRL16_NM /* 2851 */, MIPS_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srli.b $wd, $ws, $m */ + Mips_SRLI_B /* 2852 */, MIPS_INS_SRLI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srli.d $wd, $ws, $m */ + Mips_SRLI_D /* 2853 */, MIPS_INS_SRLI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srli.h $wd, $ws, $m */ + Mips_SRLI_H /* 2854 */, MIPS_INS_SRLI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srli.w $wd, $ws, $m */ + Mips_SRLI_W /* 2855 */, MIPS_INS_SRLI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlri.b $wd, $ws, $m */ + Mips_SRLRI_B /* 2856 */, MIPS_INS_SRLRI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlri.d $wd, $ws, $m */ + Mips_SRLRI_D /* 2857 */, MIPS_INS_SRLRI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlri.h $wd, $ws, $m */ + Mips_SRLRI_H /* 2858 */, MIPS_INS_SRLRI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlri.w $wd, $ws, $m */ + Mips_SRLRI_W /* 2859 */, MIPS_INS_SRLRI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlr.b $wd, $ws, $wt */ + Mips_SRLR_B /* 2860 */, MIPS_INS_SRLR_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlr.d $wd, $ws, $wt */ + Mips_SRLR_D /* 2861 */, MIPS_INS_SRLR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlr.h $wd, $ws, $wt */ + Mips_SRLR_H /* 2862 */, MIPS_INS_SRLR_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlr.w $wd, $ws, $wt */ + Mips_SRLR_W /* 2863 */, MIPS_INS_SRLR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlv $rd, $rt, $rs */ + Mips_SRLV /* 2864 */, MIPS_INS_SRLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlv $rd, $rt, $rs */ + Mips_SRLV_MM /* 2865 */, MIPS_INS_SRLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlv $rd, $rs, $rt */ + Mips_SRLV_NM /* 2866 */, MIPS_INS_SRLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl.b $wd, $ws, $wt */ + Mips_SRL_B /* 2867 */, MIPS_INS_SRL_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl.d $wd, $ws, $wt */ + Mips_SRL_D /* 2868 */, MIPS_INS_SRL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl.h $wd, $ws, $wt */ + Mips_SRL_H /* 2869 */, MIPS_INS_SRL_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl $rd, $rt, $shamt */ + Mips_SRL_MM /* 2870 */, MIPS_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl $rt, $rs, $imm */ + Mips_SRL_NM /* 2871 */, MIPS_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl.w $wd, $ws, $wt */ + Mips_SRL_W /* 2872 */, MIPS_INS_SRL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ssnop */ + Mips_SSNOP /* 2873 */, MIPS_INS_SSNOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ssnop */ + Mips_SSNOP_MM /* 2874 */, MIPS_INS_SSNOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ssnop */ + Mips_SSNOP_MMR6 /* 2875 */, MIPS_INS_SSNOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* st.b $wd, $addr */ + Mips_ST_B /* 2876 */, MIPS_INS_ST_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* st.d $wd, $addr */ + Mips_ST_D /* 2877 */, MIPS_INS_ST_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* st.h $wd, $addr */ + Mips_ST_H /* 2878 */, MIPS_INS_ST_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* st.w $wd, $addr */ + Mips_ST_W /* 2879 */, MIPS_INS_ST_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub $rd, $rs, $rt */ + Mips_SUB /* 2880 */, MIPS_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh.ph $rd, $rs, $rt */ + Mips_SUBQH_PH /* 2881 */, MIPS_INS_SUBQH_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh.ph $rd, $rs, $rt */ + Mips_SUBQH_PH_MMR2 /* 2882 */, MIPS_INS_SUBQH_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh_r.ph $rd, $rs, $rt */ + Mips_SUBQH_R_PH /* 2883 */, MIPS_INS_SUBQH_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh_r.ph $rd, $rs, $rt */ + Mips_SUBQH_R_PH_MMR2 /* 2884 */, MIPS_INS_SUBQH_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh_r.w $rd, $rs, $rt */ + Mips_SUBQH_R_W /* 2885 */, MIPS_INS_SUBQH_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh_r.w $rd, $rs, $rt */ + Mips_SUBQH_R_W_MMR2 /* 2886 */, MIPS_INS_SUBQH_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh.w $rd, $rs, $rt */ + Mips_SUBQH_W /* 2887 */, MIPS_INS_SUBQH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh.w $rd, $rs, $rt */ + Mips_SUBQH_W_MMR2 /* 2888 */, MIPS_INS_SUBQH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subq.ph $rd, $rs, $rt */ + Mips_SUBQ_PH /* 2889 */, MIPS_INS_SUBQ_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subq.ph $rd, $rs, $rt */ + Mips_SUBQ_PH_MM /* 2890 */, MIPS_INS_SUBQ_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subq_s.ph $rd, $rs, $rt */ + Mips_SUBQ_S_PH /* 2891 */, MIPS_INS_SUBQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subq_s.ph $rd, $rs, $rt */ + Mips_SUBQ_S_PH_MM /* 2892 */, MIPS_INS_SUBQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subq_s.w $rd, $rs, $rt */ + Mips_SUBQ_S_W /* 2893 */, MIPS_INS_SUBQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subq_s.w $rd, $rs, $rt */ + Mips_SUBQ_S_W_MM /* 2894 */, MIPS_INS_SUBQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsus_u.b $wd, $ws, $wt */ + Mips_SUBSUS_U_B /* 2895 */, MIPS_INS_SUBSUS_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsus_u.d $wd, $ws, $wt */ + Mips_SUBSUS_U_D /* 2896 */, MIPS_INS_SUBSUS_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsus_u.h $wd, $ws, $wt */ + Mips_SUBSUS_U_H /* 2897 */, MIPS_INS_SUBSUS_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsus_u.w $wd, $ws, $wt */ + Mips_SUBSUS_U_W /* 2898 */, MIPS_INS_SUBSUS_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsuu_s.b $wd, $ws, $wt */ + Mips_SUBSUU_S_B /* 2899 */, MIPS_INS_SUBSUU_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsuu_s.d $wd, $ws, $wt */ + Mips_SUBSUU_S_D /* 2900 */, MIPS_INS_SUBSUU_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsuu_s.h $wd, $ws, $wt */ + Mips_SUBSUU_S_H /* 2901 */, MIPS_INS_SUBSUU_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsuu_s.w $wd, $ws, $wt */ + Mips_SUBSUU_S_W /* 2902 */, MIPS_INS_SUBSUU_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_s.b $wd, $ws, $wt */ + Mips_SUBS_S_B /* 2903 */, MIPS_INS_SUBS_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_s.d $wd, $ws, $wt */ + Mips_SUBS_S_D /* 2904 */, MIPS_INS_SUBS_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_s.h $wd, $ws, $wt */ + Mips_SUBS_S_H /* 2905 */, MIPS_INS_SUBS_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_s.w $wd, $ws, $wt */ + Mips_SUBS_S_W /* 2906 */, MIPS_INS_SUBS_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_u.b $wd, $ws, $wt */ + Mips_SUBS_U_B /* 2907 */, MIPS_INS_SUBS_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_u.d $wd, $ws, $wt */ + Mips_SUBS_U_D /* 2908 */, MIPS_INS_SUBS_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_u.h $wd, $ws, $wt */ + Mips_SUBS_U_H /* 2909 */, MIPS_INS_SUBS_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_u.w $wd, $ws, $wt */ + Mips_SUBS_U_W /* 2910 */, MIPS_INS_SUBS_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu16 $rd, $rs, $rt */ + Mips_SUBU16_MM /* 2911 */, MIPS_INS_SUBU16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu16 $rd, $rs, $rt */ + Mips_SUBU16_MMR6 /* 2912 */, MIPS_INS_SUBU16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subuh.qb $rd, $rs, $rt */ + Mips_SUBUH_QB /* 2913 */, MIPS_INS_SUBUH_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subuh.qb $rd, $rs, $rt */ + Mips_SUBUH_QB_MMR2 /* 2914 */, MIPS_INS_SUBUH_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subuh_r.qb $rd, $rs, $rt */ + Mips_SUBUH_R_QB /* 2915 */, MIPS_INS_SUBUH_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subuh_r.qb $rd, $rs, $rt */ + Mips_SUBUH_R_QB_MMR2 /* 2916 */, MIPS_INS_SUBUH_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu $rd, $rs, $rt */ + Mips_SUBU_MMR6 /* 2917 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu.ph $rd, $rs, $rt */ + Mips_SUBU_PH /* 2918 */, MIPS_INS_SUBU_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu.ph $rd, $rs, $rt */ + Mips_SUBU_PH_MMR2 /* 2919 */, MIPS_INS_SUBU_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu.qb $rd, $rs, $rt */ + Mips_SUBU_QB /* 2920 */, MIPS_INS_SUBU_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu.qb $rd, $rs, $rt */ + Mips_SUBU_QB_MM /* 2921 */, MIPS_INS_SUBU_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu_s.ph $rd, $rs, $rt */ + Mips_SUBU_S_PH /* 2922 */, MIPS_INS_SUBU_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu_s.ph $rd, $rs, $rt */ + Mips_SUBU_S_PH_MMR2 /* 2923 */, MIPS_INS_SUBU_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu_s.qb $rd, $rs, $rt */ + Mips_SUBU_S_QB /* 2924 */, MIPS_INS_SUBU_S_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu_s.qb $rd, $rs, $rt */ + Mips_SUBU_S_QB_MM /* 2925 */, MIPS_INS_SUBU_S_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subvi.b $wd, $ws, $imm */ + Mips_SUBVI_B /* 2926 */, MIPS_INS_SUBVI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subvi.d $wd, $ws, $imm */ + Mips_SUBVI_D /* 2927 */, MIPS_INS_SUBVI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subvi.h $wd, $ws, $imm */ + Mips_SUBVI_H /* 2928 */, MIPS_INS_SUBVI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subvi.w $wd, $ws, $imm */ + Mips_SUBVI_W /* 2929 */, MIPS_INS_SUBVI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subv.b $wd, $ws, $wt */ + Mips_SUBV_B /* 2930 */, MIPS_INS_SUBV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subv.d $wd, $ws, $wt */ + Mips_SUBV_D /* 2931 */, MIPS_INS_SUBV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subv.h $wd, $ws, $wt */ + Mips_SUBV_H /* 2932 */, MIPS_INS_SUBV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subv.w $wd, $ws, $wt */ + Mips_SUBV_W /* 2933 */, MIPS_INS_SUBV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub $rd, $rs, $rt */ + Mips_SUB_MM /* 2934 */, MIPS_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub $rd, $rs, $rt */ + Mips_SUB_MMR6 /* 2935 */, MIPS_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub $rd, $rs, $rt */ + Mips_SUB_NM /* 2936 */, MIPS_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu $rd, $rs, $rt */ + Mips_SUBu /* 2937 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu $rd, $rs, $rt */ + Mips_SUBu16_NM /* 2938 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu $rd, $rs, $rt */ + Mips_SUBu_MM /* 2939 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu $rd, $rs, $rt */ + Mips_SUBu_NM /* 2940 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* suxc1 $fs, ${index}(${base}) */ + Mips_SUXC1 /* 2941 */, MIPS_INS_SUXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS5_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* suxc1 $fs, ${index}(${base}) */ + Mips_SUXC164 /* 2942 */, MIPS_INS_SUXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS5_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* suxc1 $fs, ${index}(${base}) */ + Mips_SUXC1_MM /* 2943 */, MIPS_INS_SUXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW /* 2944 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw16 $rt, $addr */ + Mips_SW16_MM /* 2945 */, MIPS_INS_SW16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw16 $rt, $addr */ + Mips_SW16_MMR6 /* 2946 */, MIPS_INS_SW16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW16_NM /* 2947 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW4x4_NM /* 2948 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW64 /* 2949 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* swc1 $rt, $addr */ + Mips_SWC1 /* 2950 */, MIPS_INS_SWC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swc1 $rt, $addr */ + Mips_SWC1_MM /* 2951 */, MIPS_INS_SWC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swc2 $rt, $addr */ + Mips_SWC2 /* 2952 */, MIPS_INS_SWC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swc2 $rt, $addr */ + Mips_SWC2_MMR6 /* 2953 */, MIPS_INS_SWC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swc2 $rt, $addr */ + Mips_SWC2_R6 /* 2954 */, MIPS_INS_SWC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swc3 $rt, $addr */ + Mips_SWC3 /* 2955 */, MIPS_INS_SWC3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SWDSP /* 2956 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTINMIPS16MODE, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SWDSP_MM /* 2957 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swe $rt, $addr */ + Mips_SWE /* 2958 */, MIPS_INS_SWE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swe $rt, $addr */ + Mips_SWE_MM /* 2959 */, MIPS_INS_SWE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SWGP16_NM /* 2960 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SWGP_NM /* 2961 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swl $rt, $addr */ + Mips_SWL /* 2962 */, MIPS_INS_SWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swl $rt, $addr */ + Mips_SWL64 /* 2963 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* swle $rt, $addr */ + Mips_SWLE /* 2964 */, MIPS_INS_SWLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swle $rt, $addr */ + Mips_SWLE_MM /* 2965 */, MIPS_INS_SWLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swl $rt, $addr */ + Mips_SWL_MM /* 2966 */, MIPS_INS_SWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swm16 $rt, $addr */ + Mips_SWM16_MM /* 2967 */, MIPS_INS_SWM16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swm16 $rt, $addr */ + Mips_SWM16_MMR6 /* 2968 */, MIPS_INS_SWM16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swm32 $rt, $addr */ + Mips_SWM32_MM /* 2969 */, MIPS_INS_SWM32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swm $rt, $addr, $rcount */ + Mips_SWM_NM /* 2970 */, MIPS_INS_SWM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swpc $rt, $addr */ + Mips_SWPC_NM /* 2971 */, MIPS_INS_SWPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swp $rt, $addr */ + Mips_SWP_MM /* 2972 */, MIPS_INS_SWP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swr $rt, $addr */ + Mips_SWR /* 2973 */, MIPS_INS_SWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swr $rt, $addr */ + Mips_SWR64 /* 2974 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* swre $rt, $addr */ + Mips_SWRE /* 2975 */, MIPS_INS_SWRE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swre $rt, $addr */ + Mips_SWRE_MM /* 2976 */, MIPS_INS_SWRE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swr $rt, $addr */ + Mips_SWR_MM /* 2977 */, MIPS_INS_SWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SWSP16_NM /* 2978 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swsp $rt, $offset */ + Mips_SWSP_MM /* 2979 */, MIPS_INS_SWSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $offset */ + Mips_SWSP_MMR6 /* 2980 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swxc1 $fs, ${index}(${base}) */ + Mips_SWXC1 /* 2981 */, MIPS_INS_SWXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swxc1 $fs, ${index}(${base}) */ + Mips_SWXC1_MM /* 2982 */, MIPS_INS_SWXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swxs $rt, $addr */ + Mips_SWXS_NM /* 2983 */, MIPS_INS_SWXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swx $rt, $addr */ + Mips_SWX_NM /* 2984 */, MIPS_INS_SWX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW_MM /* 2985 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW_MMR6 /* 2986 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW_NM /* 2987 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SWs9_NM /* 2988 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sync $stype */ + Mips_SYNC /* 2989 */, MIPS_INS_SYNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* synci $addr */ + Mips_SYNCI /* 2990 */, MIPS_INS_SYNCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* synci $addr */ + Mips_SYNCI_MM /* 2991 */, MIPS_INS_SYNCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* synci $addr */ + Mips_SYNCI_MMR6 /* 2992 */, MIPS_INS_SYNCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* synci $addr */ + Mips_SYNCI_NM /* 2993 */, MIPS_INS_SYNCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* synci $addr */ + Mips_SYNCIs9_NM /* 2994 */, MIPS_INS_SYNCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sync $stype */ + Mips_SYNC_MM /* 2995 */, MIPS_INS_SYNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sync $stype */ + Mips_SYNC_MMR6 /* 2996 */, MIPS_INS_SYNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sync $stype */ + Mips_SYNC_NM /* 2997 */, MIPS_INS_SYNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* syscall $code_ */ + Mips_SYSCALL /* 2998 */, MIPS_INS_SYSCALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* syscall $imm */ + Mips_SYSCALL16_NM /* 2999 */, MIPS_INS_SYSCALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* syscall $code_ */ + Mips_SYSCALL_MM /* 3000 */, MIPS_INS_SYSCALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* syscall $imm */ + Mips_SYSCALL_NM /* 3001 */, MIPS_INS_SYSCALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_Save16 /* 3002 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SaveX16 /* 3003 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sb $ry, $addr */ + Mips_SbRxRyOffMemX16 /* 3004 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seb $rx */ + Mips_SebRx16 /* 3005 */, MIPS_INS_SEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seh $rx */ + Mips_SehRx16 /* 3006 */, MIPS_INS_SEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $ry, $addr */ + Mips_ShRxRyOffMemX16 /* 3007 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rx, $ry, $sa6 */ + Mips_SllX16 /* 3008 */, MIPS_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sllv $rz, $ry */ + Mips_SllvRxRy16 /* 3009 */, MIPS_INS_SLLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slt $rx, $ry */ + Mips_SltRxRy16 /* 3010 */, MIPS_INS_SLT, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slti $rx, $imm8 # 16 bit inst */ + Mips_SltiRxImm16 /* 3011 */, MIPS_INS_SLTI, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slti $rx, $imm16 */ + Mips_SltiRxImmX16 /* 3012 */, MIPS_INS_SLTI, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltiu $rx, $imm8 # 16 bit inst */ + Mips_SltiuRxImm16 /* 3013 */, MIPS_INS_SLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltiu $rx, $imm16 */ + Mips_SltiuRxImmX16 /* 3014 */, MIPS_INS_SLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltu $rx, $ry */ + Mips_SltuRxRy16 /* 3015 */, MIPS_INS_SLTU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra $rx, $ry, $sa6 */ + Mips_SraX16 /* 3016 */, MIPS_INS_SRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srav $rz, $ry */ + Mips_SravRxRy16 /* 3017 */, MIPS_INS_SRAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl $rx, $ry, $sa6 */ + Mips_SrlX16 /* 3018 */, MIPS_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlv $rz, $ry */ + Mips_SrlvRxRy16 /* 3019 */, MIPS_INS_SRLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu $rz, $rx, $ry */ + Mips_SubuRxRyRz16 /* 3020 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $ry, $addr */ + Mips_SwRxRyOffMemX16 /* 3021 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $ry, $addr */ + Mips_SwRxSpImmX16 /* 3022 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* teq $rs, $rt, $code_ */ + Mips_TEQ /* 3023 */, MIPS_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* teqi $rs, $imm16 */ + Mips_TEQI /* 3024 */, MIPS_INS_TEQI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* teqi $rs, $imm16 */ + Mips_TEQI_MM /* 3025 */, MIPS_INS_TEQI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* teq $rs, $rt, $code_ */ + Mips_TEQ_MM /* 3026 */, MIPS_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* teq $rs, $rt, $imm */ + Mips_TEQ_NM /* 3027 */, MIPS_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tge $rs, $rt, $code_ */ + Mips_TGE /* 3028 */, MIPS_INS_TGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tgei $rs, $imm16 */ + Mips_TGEI /* 3029 */, MIPS_INS_TGEI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tgeiu $rs, $imm16 */ + Mips_TGEIU /* 3030 */, MIPS_INS_TGEIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tgeiu $rs, $imm16 */ + Mips_TGEIU_MM /* 3031 */, MIPS_INS_TGEIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tgei $rs, $imm16 */ + Mips_TGEI_MM /* 3032 */, MIPS_INS_TGEI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tgeu $rs, $rt, $code_ */ + Mips_TGEU /* 3033 */, MIPS_INS_TGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tgeu $rs, $rt, $code_ */ + Mips_TGEU_MM /* 3034 */, MIPS_INS_TGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tge $rs, $rt, $code_ */ + Mips_TGE_MM /* 3035 */, MIPS_INS_TGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbginv */ + Mips_TLBGINV /* 3036 */, MIPS_INS_TLBGINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbginvf */ + Mips_TLBGINVF /* 3037 */, MIPS_INS_TLBGINVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbginvf */ + Mips_TLBGINVF_MM /* 3038 */, MIPS_INS_TLBGINVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbginv */ + Mips_TLBGINV_MM /* 3039 */, MIPS_INS_TLBGINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgp */ + Mips_TLBGP /* 3040 */, MIPS_INS_TLBGP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgp */ + Mips_TLBGP_MM /* 3041 */, MIPS_INS_TLBGP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgr */ + Mips_TLBGR /* 3042 */, MIPS_INS_TLBGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgr */ + Mips_TLBGR_MM /* 3043 */, MIPS_INS_TLBGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgwi */ + Mips_TLBGWI /* 3044 */, MIPS_INS_TLBGWI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgwi */ + Mips_TLBGWI_MM /* 3045 */, MIPS_INS_TLBGWI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgwr */ + Mips_TLBGWR /* 3046 */, MIPS_INS_TLBGWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgwr */ + Mips_TLBGWR_MM /* 3047 */, MIPS_INS_TLBGWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbinv */ + Mips_TLBINV /* 3048 */, MIPS_INS_TLBINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbinvf */ + Mips_TLBINVF /* 3049 */, MIPS_INS_TLBINVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbinvf */ + Mips_TLBINVF_MMR6 /* 3050 */, MIPS_INS_TLBINVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbinvf */ + Mips_TLBINVF_NM /* 3051 */, MIPS_INS_TLBINVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASTLB, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbinv */ + Mips_TLBINV_MMR6 /* 3052 */, MIPS_INS_TLBINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbinv */ + Mips_TLBINV_NM /* 3053 */, MIPS_INS_TLBINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASTLB, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbp */ + Mips_TLBP /* 3054 */, MIPS_INS_TLBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbp */ + Mips_TLBP_MM /* 3055 */, MIPS_INS_TLBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbp */ + Mips_TLBP_NM /* 3056 */, MIPS_INS_TLBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASTLB, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbr */ + Mips_TLBR /* 3057 */, MIPS_INS_TLBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbr */ + Mips_TLBR_MM /* 3058 */, MIPS_INS_TLBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbr */ + Mips_TLBR_NM /* 3059 */, MIPS_INS_TLBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASTLB, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbwi */ + Mips_TLBWI /* 3060 */, MIPS_INS_TLBWI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbwi */ + Mips_TLBWI_MM /* 3061 */, MIPS_INS_TLBWI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbwi */ + Mips_TLBWI_NM /* 3062 */, MIPS_INS_TLBWI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASTLB, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbwr */ + Mips_TLBWR /* 3063 */, MIPS_INS_TLBWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbwr */ + Mips_TLBWR_MM /* 3064 */, MIPS_INS_TLBWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbwr */ + Mips_TLBWR_NM /* 3065 */, MIPS_INS_TLBWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASTLB, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlt $rs, $rt, $code_ */ + Mips_TLT /* 3066 */, MIPS_INS_TLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlti $rs, $imm16 */ + Mips_TLTI /* 3067 */, MIPS_INS_TLTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tltiu $rs, $imm16 */ + Mips_TLTIU_MM /* 3068 */, MIPS_INS_TLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlti $rs, $imm16 */ + Mips_TLTI_MM /* 3069 */, MIPS_INS_TLTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tltu $rs, $rt, $code_ */ + Mips_TLTU /* 3070 */, MIPS_INS_TLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tltu $rs, $rt, $code_ */ + Mips_TLTU_MM /* 3071 */, MIPS_INS_TLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlt $rs, $rt, $code_ */ + Mips_TLT_MM /* 3072 */, MIPS_INS_TLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tne $rs, $rt, $code_ */ + Mips_TNE /* 3073 */, MIPS_INS_TNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tnei $rs, $imm16 */ + Mips_TNEI /* 3074 */, MIPS_INS_TNEI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tnei $rs, $imm16 */ + Mips_TNEI_MM /* 3075 */, MIPS_INS_TNEI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tne $rs, $rt, $code_ */ + Mips_TNE_MM /* 3076 */, MIPS_INS_TNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tne $rs, $rt, $imm */ + Mips_TNE_NM /* 3077 */, MIPS_INS_TNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.l.d $fd, $fs */ + Mips_TRUNC_L_D64 /* 3078 */, MIPS_INS_TRUNC_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.l.d $ft, $fs */ + Mips_TRUNC_L_D_MMR6 /* 3079 */, MIPS_INS_TRUNC_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.l.s $fd, $fs */ + Mips_TRUNC_L_S /* 3080 */, MIPS_INS_TRUNC_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.l.s $ft, $fs */ + Mips_TRUNC_L_S_MMR6 /* 3081 */, MIPS_INS_TRUNC_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.d $fd, $fs */ + Mips_TRUNC_W_D32 /* 3082 */, MIPS_INS_TRUNC_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.d $fd, $fs */ + Mips_TRUNC_W_D64 /* 3083 */, MIPS_INS_TRUNC_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.d $ft, $fs */ + Mips_TRUNC_W_D_MMR6 /* 3084 */, MIPS_INS_TRUNC_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.d $fd, $fs */ + Mips_TRUNC_W_MM /* 3085 */, MIPS_INS_TRUNC_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.s $fd, $fs */ + Mips_TRUNC_W_S /* 3086 */, MIPS_INS_TRUNC_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.s $fd, $fs */ + Mips_TRUNC_W_S_MM /* 3087 */, MIPS_INS_TRUNC_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.s $ft, $fs */ + Mips_TRUNC_W_S_MMR6 /* 3088 */, MIPS_INS_TRUNC_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tltiu $rs, $imm16 */ + Mips_TTLTIU /* 3089 */, MIPS_INS_TLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ualh $rt, $addr */ + Mips_UALH_NM /* 3090 */, MIPS_INS_UALH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ualwm $rt, $addr, $rcount */ + Mips_UALWM_NM /* 3091 */, MIPS_INS_UALWM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ualw $rt, $addr */ + Mips_UALW_NM /* 3092 */, MIPS_INS_UALW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* uash $rt, $addr */ + Mips_UASH_NM /* 3093 */, MIPS_INS_UASH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* uaswm $rt, $addr, $rcount */ + Mips_UASWM_NM /* 3094 */, MIPS_INS_UASWM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* uasw $rt, $addr */ + Mips_UASW_NM /* 3095 */, MIPS_INS_UASW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $$zero, $rs, $rt */ + Mips_UDIV /* 3096 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $$zero, $rs, $rt */ + Mips_UDIV_MM /* 3097 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* v3mulu $rd, $rs, $rt */ + Mips_V3MULU /* 3098 */, MIPS_INS_V3MULU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* vmm0 $rd, $rs, $rt */ + Mips_VMM0 /* 3099 */, MIPS_INS_VMM0, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* vmulu $rd, $rs, $rt */ + Mips_VMULU /* 3100 */, MIPS_INS_VMULU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* vshf.b $wd, $ws, $wt */ + Mips_VSHF_B /* 3101 */, MIPS_INS_VSHF_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* vshf.d $wd, $ws, $wt */ + Mips_VSHF_D /* 3102 */, MIPS_INS_VSHF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* vshf.h $wd, $ws, $wt */ + Mips_VSHF_H /* 3103 */, MIPS_INS_VSHF_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* vshf.w $wd, $ws, $wt */ + Mips_VSHF_W /* 3104 */, MIPS_INS_VSHF_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wait */ + Mips_WAIT /* 3105 */, MIPS_INS_WAIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wait $code_ */ + Mips_WAIT_MM /* 3106 */, MIPS_INS_WAIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wait $code_ */ + Mips_WAIT_MMR6 /* 3107 */, MIPS_INS_WAIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wait $cd */ + Mips_WAIT_NM /* 3108 */, MIPS_INS_WAIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wrdsp $rs, $mask */ + Mips_WRDSP /* 3109 */, MIPS_INS_WRDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wrdsp $rt, $mask */ + Mips_WRDSP_MM /* 3110 */, MIPS_INS_WRDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wrpgpr $rt, $rs */ + Mips_WRPGPR_MMR6 /* 3111 */, MIPS_INS_WRPGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wrpgpr $rt, $rs */ + Mips_WRPGPR_NM /* 3112 */, MIPS_INS_WRPGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wsbh $rd, $rt */ + Mips_WSBH /* 3113 */, MIPS_INS_WSBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wsbh $rd, $rt */ + Mips_WSBH_MM /* 3114 */, MIPS_INS_WSBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wsbh $rt, $rs */ + Mips_WSBH_MMR6 /* 3115 */, MIPS_INS_WSBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $rd, $rs, $rt */ + Mips_XOR /* 3116 */, MIPS_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor16 $rt, $rs */ + Mips_XOR16_MM /* 3117 */, MIPS_INS_XOR16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor16 $rt, $rs */ + Mips_XOR16_MMR6 /* 3118 */, MIPS_INS_XOR16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $dst, $rs, $rt */ + Mips_XOR16_NM /* 3119 */, MIPS_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $rd, $rs, $rt */ + Mips_XOR64 /* 3120 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* xori.b $wd, $ws, $u8 */ + Mips_XORI_B /* 3121 */, MIPS_INS_XORI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xori $rt, $rs, $imm16 */ + Mips_XORI_MMR6 /* 3122 */, MIPS_INS_XORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xori $rt, $rs, $imm */ + Mips_XORI_NM /* 3123 */, MIPS_INS_XORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $rd, $rs, $rt */ + Mips_XOR_MM /* 3124 */, MIPS_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $rd, $rs, $rt */ + Mips_XOR_MMR6 /* 3125 */, MIPS_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $rd, $rs, $rt */ + Mips_XOR_NM /* 3126 */, MIPS_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor.v $wd, $ws, $wt */ + Mips_XOR_V /* 3127 */, MIPS_INS_XOR_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xori $rt, $rs, $imm16 */ + Mips_XORi /* 3128 */, MIPS_INS_XORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xori $rt, $rs, $imm16 */ + Mips_XORi64 /* 3129 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* xori $rt, $rs, $imm16 */ + Mips_XORi_MM /* 3130 */, MIPS_INS_XORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $rz, $ry */ + Mips_XorRxRxRy16 /* 3131 */, MIPS_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* yield $rd, $rs */ + Mips_YIELD /* 3132 */, MIPS_INS_YIELD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* yield $rd, $rs */ + Mips_YIELD_NM /* 3133 */, MIPS_INS_YIELD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, diff --git a/arch/Mips/MipsGenCSMappingInsnName.inc b/arch/Mips/MipsGenCSMappingInsnName.inc new file mode 100644 index 000000000..112a6aeb6 --- /dev/null +++ b/arch/Mips/MipsGenCSMappingInsnName.inc @@ -0,0 +1,1373 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + "invalid", // MIPS_INS_INVALID + "abs", // MIPS_INS_ABS + "align", // MIPS_INS_ALIGN + "beql", // MIPS_INS_BEQL + "bge", // MIPS_INS_BGE + "bgel", // MIPS_INS_BGEL + "bgeu", // MIPS_INS_BGEU + "bgeul", // MIPS_INS_BGEUL + "bgt", // MIPS_INS_BGT + "bgtl", // MIPS_INS_BGTL + "bgtu", // MIPS_INS_BGTU + "bgtul", // MIPS_INS_BGTUL + "ble", // MIPS_INS_BLE + "blel", // MIPS_INS_BLEL + "bleu", // MIPS_INS_BLEU + "bleul", // MIPS_INS_BLEUL + "blt", // MIPS_INS_BLT + "bltl", // MIPS_INS_BLTL + "bltu", // MIPS_INS_BLTU + "bltul", // MIPS_INS_BLTUL + "bnel", // MIPS_INS_BNEL + "b", // MIPS_INS_B + "beq", // MIPS_INS_BEQ + "bne", // MIPS_INS_BNE + "cftc1", // MIPS_INS_CFTC1 + "cttc1", // MIPS_INS_CTTC1 + "dmul", // MIPS_INS_DMUL + "dmulo", // MIPS_INS_DMULO + "dmulou", // MIPS_INS_DMULOU + "drol", // MIPS_INS_DROL + "dror", // MIPS_INS_DROR + "ddiv", // MIPS_INS_DDIV + "drem", // MIPS_INS_DREM + "ddivu", // MIPS_INS_DDIVU + "dremu", // MIPS_INS_DREMU + "jal", // MIPS_INS_JAL + "ld", // MIPS_INS_LD + "lwm", // MIPS_INS_LWM + "la", // MIPS_INS_LA + "dla", // MIPS_INS_DLA + "li", // MIPS_INS_LI + "dli", // MIPS_INS_DLI + "li_d", // MIPS_INS_LI_D + "li_s", // MIPS_INS_LI_S + "mftacx", // MIPS_INS_MFTACX + "mftc0", // MIPS_INS_MFTC0 + "mftc1", // MIPS_INS_MFTC1 + "mftdsp", // MIPS_INS_MFTDSP + "mftgpr", // MIPS_INS_MFTGPR + "mfthc1", // MIPS_INS_MFTHC1 + "mfthi", // MIPS_INS_MFTHI + "mftlo", // MIPS_INS_MFTLO + "mttacx", // MIPS_INS_MTTACX + "mttc0", // MIPS_INS_MTTC0 + "mttc1", // MIPS_INS_MTTC1 + "mttdsp", // MIPS_INS_MTTDSP + "mttgpr", // MIPS_INS_MTTGPR + "mtthc1", // MIPS_INS_MTTHC1 + "mtthi", // MIPS_INS_MTTHI + "mttlo", // MIPS_INS_MTTLO + "mul", // MIPS_INS_MUL + "mulo", // MIPS_INS_MULO + "mulou", // MIPS_INS_MULOU + "nor", // MIPS_INS_NOR + "addiu", // MIPS_INS_ADDIU + "andi", // MIPS_INS_ANDI + "subu", // MIPS_INS_SUBU + "trunc_w_d", // MIPS_INS_TRUNC_W_D + "trunc_w_s", // MIPS_INS_TRUNC_W_S + "rol", // MIPS_INS_ROL + "ror", // MIPS_INS_ROR + "s_d", // MIPS_INS_S_D + "sd", // MIPS_INS_SD + "div", // MIPS_INS_DIV + "seq", // MIPS_INS_SEQ + "sge", // MIPS_INS_SGE + "sgeu", // MIPS_INS_SGEU + "sgt", // MIPS_INS_SGT + "sgtu", // MIPS_INS_SGTU + "sle", // MIPS_INS_SLE + "sleu", // MIPS_INS_SLEU + "slt", // MIPS_INS_SLT + "sltu", // MIPS_INS_SLTU + "sne", // MIPS_INS_SNE + "rem", // MIPS_INS_REM + "swm", // MIPS_INS_SWM + "saa", // MIPS_INS_SAA + "saad", // MIPS_INS_SAAD + "divu", // MIPS_INS_DIVU + "remu", // MIPS_INS_REMU + "ulh", // MIPS_INS_ULH + "ulhu", // MIPS_INS_ULHU + "ulw", // MIPS_INS_ULW + "ush", // MIPS_INS_USH + "usw", // MIPS_INS_USW + "absq_s_ph", // MIPS_INS_ABSQ_S_PH + "absq_s_qb", // MIPS_INS_ABSQ_S_QB + "absq_s_w", // MIPS_INS_ABSQ_S_W + "add", // MIPS_INS_ADD + "addiupc", // MIPS_INS_ADDIUPC + "addiur1sp", // MIPS_INS_ADDIUR1SP + "addiur2", // MIPS_INS_ADDIUR2 + "addius5", // MIPS_INS_ADDIUS5 + "addiusp", // MIPS_INS_ADDIUSP + "addqh_ph", // MIPS_INS_ADDQH_PH + "addqh_r_ph", // MIPS_INS_ADDQH_R_PH + "addqh_r_w", // MIPS_INS_ADDQH_R_W + "addqh_w", // MIPS_INS_ADDQH_W + "addq_ph", // MIPS_INS_ADDQ_PH + "addq_s_ph", // MIPS_INS_ADDQ_S_PH + "addq_s_w", // MIPS_INS_ADDQ_S_W + "addr_ps", // MIPS_INS_ADDR_PS + "addsc", // MIPS_INS_ADDSC + "adds_a_b", // MIPS_INS_ADDS_A_B + "adds_a_d", // MIPS_INS_ADDS_A_D + "adds_a_h", // MIPS_INS_ADDS_A_H + "adds_a_w", // MIPS_INS_ADDS_A_W + "adds_s_b", // MIPS_INS_ADDS_S_B + "adds_s_d", // MIPS_INS_ADDS_S_D + "adds_s_h", // MIPS_INS_ADDS_S_H + "adds_s_w", // MIPS_INS_ADDS_S_W + "adds_u_b", // MIPS_INS_ADDS_U_B + "adds_u_d", // MIPS_INS_ADDS_U_D + "adds_u_h", // MIPS_INS_ADDS_U_H + "adds_u_w", // MIPS_INS_ADDS_U_W + "addu16", // MIPS_INS_ADDU16 + "adduh_qb", // MIPS_INS_ADDUH_QB + "adduh_r_qb", // MIPS_INS_ADDUH_R_QB + "addu", // MIPS_INS_ADDU + "addu_ph", // MIPS_INS_ADDU_PH + "addu_qb", // MIPS_INS_ADDU_QB + "addu_s_ph", // MIPS_INS_ADDU_S_PH + "addu_s_qb", // MIPS_INS_ADDU_S_QB + "addvi_b", // MIPS_INS_ADDVI_B + "addvi_d", // MIPS_INS_ADDVI_D + "addvi_h", // MIPS_INS_ADDVI_H + "addvi_w", // MIPS_INS_ADDVI_W + "addv_b", // MIPS_INS_ADDV_B + "addv_d", // MIPS_INS_ADDV_D + "addv_h", // MIPS_INS_ADDV_H + "addv_w", // MIPS_INS_ADDV_W + "addwc", // MIPS_INS_ADDWC + "add_a_b", // MIPS_INS_ADD_A_B + "add_a_d", // MIPS_INS_ADD_A_D + "add_a_h", // MIPS_INS_ADD_A_H + "add_a_w", // MIPS_INS_ADD_A_W + "addi", // MIPS_INS_ADDI + "aluipc", // MIPS_INS_ALUIPC + "and", // MIPS_INS_AND + "and16", // MIPS_INS_AND16 + "andi16", // MIPS_INS_ANDI16 + "andi_b", // MIPS_INS_ANDI_B + "and_v", // MIPS_INS_AND_V + "append", // MIPS_INS_APPEND + "asub_s_b", // MIPS_INS_ASUB_S_B + "asub_s_d", // MIPS_INS_ASUB_S_D + "asub_s_h", // MIPS_INS_ASUB_S_H + "asub_s_w", // MIPS_INS_ASUB_S_W + "asub_u_b", // MIPS_INS_ASUB_U_B + "asub_u_d", // MIPS_INS_ASUB_U_D + "asub_u_h", // MIPS_INS_ASUB_U_H + "asub_u_w", // MIPS_INS_ASUB_U_W + "aui", // MIPS_INS_AUI + "auipc", // MIPS_INS_AUIPC + "aver_s_b", // MIPS_INS_AVER_S_B + "aver_s_d", // MIPS_INS_AVER_S_D + "aver_s_h", // MIPS_INS_AVER_S_H + "aver_s_w", // MIPS_INS_AVER_S_W + "aver_u_b", // MIPS_INS_AVER_U_B + "aver_u_d", // MIPS_INS_AVER_U_D + "aver_u_h", // MIPS_INS_AVER_U_H + "aver_u_w", // MIPS_INS_AVER_U_W + "ave_s_b", // MIPS_INS_AVE_S_B + "ave_s_d", // MIPS_INS_AVE_S_D + "ave_s_h", // MIPS_INS_AVE_S_H + "ave_s_w", // MIPS_INS_AVE_S_W + "ave_u_b", // MIPS_INS_AVE_U_B + "ave_u_d", // MIPS_INS_AVE_U_D + "ave_u_h", // MIPS_INS_AVE_U_H + "ave_u_w", // MIPS_INS_AVE_U_W + "b16", // MIPS_INS_B16 + "baddu", // MIPS_INS_BADDU + "bal", // MIPS_INS_BAL + "balc", // MIPS_INS_BALC + "balign", // MIPS_INS_BALIGN + "balrsc", // MIPS_INS_BALRSC + "bbeqzc", // MIPS_INS_BBEQZC + "bbit0", // MIPS_INS_BBIT0 + "bbit032", // MIPS_INS_BBIT032 + "bbit1", // MIPS_INS_BBIT1 + "bbit132", // MIPS_INS_BBIT132 + "bbnezc", // MIPS_INS_BBNEZC + "bc", // MIPS_INS_BC + "bc16", // MIPS_INS_BC16 + "bc1eqz", // MIPS_INS_BC1EQZ + "bc1eqzc", // MIPS_INS_BC1EQZC + "bc1f", // MIPS_INS_BC1F + "bc1fl", // MIPS_INS_BC1FL + "bc1nez", // MIPS_INS_BC1NEZ + "bc1nezc", // MIPS_INS_BC1NEZC + "bc1t", // MIPS_INS_BC1T + "bc1tl", // MIPS_INS_BC1TL + "bc2eqz", // MIPS_INS_BC2EQZ + "bc2eqzc", // MIPS_INS_BC2EQZC + "bc2nez", // MIPS_INS_BC2NEZ + "bc2nezc", // MIPS_INS_BC2NEZC + "bclri_b", // MIPS_INS_BCLRI_B + "bclri_d", // MIPS_INS_BCLRI_D + "bclri_h", // MIPS_INS_BCLRI_H + "bclri_w", // MIPS_INS_BCLRI_W + "bclr_b", // MIPS_INS_BCLR_B + "bclr_d", // MIPS_INS_BCLR_D + "bclr_h", // MIPS_INS_BCLR_H + "bclr_w", // MIPS_INS_BCLR_W + "beqc", // MIPS_INS_BEQC + "beqic", // MIPS_INS_BEQIC + "beqz16", // MIPS_INS_BEQZ16 + "beqzalc", // MIPS_INS_BEQZALC + "beqzc", // MIPS_INS_BEQZC + "beqzc16", // MIPS_INS_BEQZC16 + "bgec", // MIPS_INS_BGEC + "bgeic", // MIPS_INS_BGEIC + "bgeiuc", // MIPS_INS_BGEIUC + "bgeuc", // MIPS_INS_BGEUC + "bgez", // MIPS_INS_BGEZ + "bgezal", // MIPS_INS_BGEZAL + "bgezalc", // MIPS_INS_BGEZALC + "bgezall", // MIPS_INS_BGEZALL + "bgezals", // MIPS_INS_BGEZALS + "bgezc", // MIPS_INS_BGEZC + "bgezl", // MIPS_INS_BGEZL + "bgtz", // MIPS_INS_BGTZ + "bgtzalc", // MIPS_INS_BGTZALC + "bgtzc", // MIPS_INS_BGTZC + "bgtzl", // MIPS_INS_BGTZL + "binsli_b", // MIPS_INS_BINSLI_B + "binsli_d", // MIPS_INS_BINSLI_D + "binsli_h", // MIPS_INS_BINSLI_H + "binsli_w", // MIPS_INS_BINSLI_W + "binsl_b", // MIPS_INS_BINSL_B + "binsl_d", // MIPS_INS_BINSL_D + "binsl_h", // MIPS_INS_BINSL_H + "binsl_w", // MIPS_INS_BINSL_W + "binsri_b", // MIPS_INS_BINSRI_B + "binsri_d", // MIPS_INS_BINSRI_D + "binsri_h", // MIPS_INS_BINSRI_H + "binsri_w", // MIPS_INS_BINSRI_W + "binsr_b", // MIPS_INS_BINSR_B + "binsr_d", // MIPS_INS_BINSR_D + "binsr_h", // MIPS_INS_BINSR_H + "binsr_w", // MIPS_INS_BINSR_W + "bitrev", // MIPS_INS_BITREV + "bitrevw", // MIPS_INS_BITREVW + "bitswap", // MIPS_INS_BITSWAP + "blez", // MIPS_INS_BLEZ + "blezalc", // MIPS_INS_BLEZALC + "blezc", // MIPS_INS_BLEZC + "blezl", // MIPS_INS_BLEZL + "bltc", // MIPS_INS_BLTC + "bltic", // MIPS_INS_BLTIC + "bltiuc", // MIPS_INS_BLTIUC + "bltuc", // MIPS_INS_BLTUC + "bltz", // MIPS_INS_BLTZ + "bltzal", // MIPS_INS_BLTZAL + "bltzalc", // MIPS_INS_BLTZALC + "bltzall", // MIPS_INS_BLTZALL + "bltzals", // MIPS_INS_BLTZALS + "bltzc", // MIPS_INS_BLTZC + "bltzl", // MIPS_INS_BLTZL + "bmnzi_b", // MIPS_INS_BMNZI_B + "bmnz_v", // MIPS_INS_BMNZ_V + "bmzi_b", // MIPS_INS_BMZI_B + "bmz_v", // MIPS_INS_BMZ_V + "bnec", // MIPS_INS_BNEC + "bnegi_b", // MIPS_INS_BNEGI_B + "bnegi_d", // MIPS_INS_BNEGI_D + "bnegi_h", // MIPS_INS_BNEGI_H + "bnegi_w", // MIPS_INS_BNEGI_W + "bneg_b", // MIPS_INS_BNEG_B + "bneg_d", // MIPS_INS_BNEG_D + "bneg_h", // MIPS_INS_BNEG_H + "bneg_w", // MIPS_INS_BNEG_W + "bneic", // MIPS_INS_BNEIC + "bnez16", // MIPS_INS_BNEZ16 + "bnezalc", // MIPS_INS_BNEZALC + "bnezc", // MIPS_INS_BNEZC + "bnezc16", // MIPS_INS_BNEZC16 + "bnvc", // MIPS_INS_BNVC + "bnz_b", // MIPS_INS_BNZ_B + "bnz_d", // MIPS_INS_BNZ_D + "bnz_h", // MIPS_INS_BNZ_H + "bnz_v", // MIPS_INS_BNZ_V + "bnz_w", // MIPS_INS_BNZ_W + "bovc", // MIPS_INS_BOVC + "bposge32", // MIPS_INS_BPOSGE32 + "bposge32c", // MIPS_INS_BPOSGE32C + "break", // MIPS_INS_BREAK + "break16", // MIPS_INS_BREAK16 + "brsc", // MIPS_INS_BRSC + "bseli_b", // MIPS_INS_BSELI_B + "bsel_v", // MIPS_INS_BSEL_V + "bseti_b", // MIPS_INS_BSETI_B + "bseti_d", // MIPS_INS_BSETI_D + "bseti_h", // MIPS_INS_BSETI_H + "bseti_w", // MIPS_INS_BSETI_W + "bset_b", // MIPS_INS_BSET_B + "bset_d", // MIPS_INS_BSET_D + "bset_h", // MIPS_INS_BSET_H + "bset_w", // MIPS_INS_BSET_W + "byterevw", // MIPS_INS_BYTEREVW + "bz_b", // MIPS_INS_BZ_B + "bz_d", // MIPS_INS_BZ_D + "bz_h", // MIPS_INS_BZ_H + "bz_v", // MIPS_INS_BZ_V + "bz_w", // MIPS_INS_BZ_W + "beqz", // MIPS_INS_BEQZ + "bnez", // MIPS_INS_BNEZ + "bteqz", // MIPS_INS_BTEQZ + "btnez", // MIPS_INS_BTNEZ + "cache", // MIPS_INS_CACHE + "cachee", // MIPS_INS_CACHEE + "ceil_l_d", // MIPS_INS_CEIL_L_D + "ceil_l_s", // MIPS_INS_CEIL_L_S + "ceil_w_d", // MIPS_INS_CEIL_W_D + "ceil_w_s", // MIPS_INS_CEIL_W_S + "ceqi_b", // MIPS_INS_CEQI_B + "ceqi_d", // MIPS_INS_CEQI_D + "ceqi_h", // MIPS_INS_CEQI_H + "ceqi_w", // MIPS_INS_CEQI_W + "ceq_b", // MIPS_INS_CEQ_B + "ceq_d", // MIPS_INS_CEQ_D + "ceq_h", // MIPS_INS_CEQ_H + "ceq_w", // MIPS_INS_CEQ_W + "cfc1", // MIPS_INS_CFC1 + "cfc2", // MIPS_INS_CFC2 + "cfcmsa", // MIPS_INS_CFCMSA + "cins", // MIPS_INS_CINS + "cins32", // MIPS_INS_CINS32 + "class_d", // MIPS_INS_CLASS_D + "class_s", // MIPS_INS_CLASS_S + "clei_s_b", // MIPS_INS_CLEI_S_B + "clei_s_d", // MIPS_INS_CLEI_S_D + "clei_s_h", // MIPS_INS_CLEI_S_H + "clei_s_w", // MIPS_INS_CLEI_S_W + "clei_u_b", // MIPS_INS_CLEI_U_B + "clei_u_d", // MIPS_INS_CLEI_U_D + "clei_u_h", // MIPS_INS_CLEI_U_H + "clei_u_w", // MIPS_INS_CLEI_U_W + "cle_s_b", // MIPS_INS_CLE_S_B + "cle_s_d", // MIPS_INS_CLE_S_D + "cle_s_h", // MIPS_INS_CLE_S_H + "cle_s_w", // MIPS_INS_CLE_S_W + "cle_u_b", // MIPS_INS_CLE_U_B + "cle_u_d", // MIPS_INS_CLE_U_D + "cle_u_h", // MIPS_INS_CLE_U_H + "cle_u_w", // MIPS_INS_CLE_U_W + "clo", // MIPS_INS_CLO + "clti_s_b", // MIPS_INS_CLTI_S_B + "clti_s_d", // MIPS_INS_CLTI_S_D + "clti_s_h", // MIPS_INS_CLTI_S_H + "clti_s_w", // MIPS_INS_CLTI_S_W + "clti_u_b", // MIPS_INS_CLTI_U_B + "clti_u_d", // MIPS_INS_CLTI_U_D + "clti_u_h", // MIPS_INS_CLTI_U_H + "clti_u_w", // MIPS_INS_CLTI_U_W + "clt_s_b", // MIPS_INS_CLT_S_B + "clt_s_d", // MIPS_INS_CLT_S_D + "clt_s_h", // MIPS_INS_CLT_S_H + "clt_s_w", // MIPS_INS_CLT_S_W + "clt_u_b", // MIPS_INS_CLT_U_B + "clt_u_d", // MIPS_INS_CLT_U_D + "clt_u_h", // MIPS_INS_CLT_U_H + "clt_u_w", // MIPS_INS_CLT_U_W + "clz", // MIPS_INS_CLZ + "cmpgdu_eq_qb", // MIPS_INS_CMPGDU_EQ_QB + "cmpgdu_le_qb", // MIPS_INS_CMPGDU_LE_QB + "cmpgdu_lt_qb", // MIPS_INS_CMPGDU_LT_QB + "cmpgu_eq_qb", // MIPS_INS_CMPGU_EQ_QB + "cmpgu_le_qb", // MIPS_INS_CMPGU_LE_QB + "cmpgu_lt_qb", // MIPS_INS_CMPGU_LT_QB + "cmpu_eq_qb", // MIPS_INS_CMPU_EQ_QB + "cmpu_le_qb", // MIPS_INS_CMPU_LE_QB + "cmpu_lt_qb", // MIPS_INS_CMPU_LT_QB + "cmp_af_d", // MIPS_INS_CMP_AF_D + "cmp_af_s", // MIPS_INS_CMP_AF_S + "cmp_eq_d", // MIPS_INS_CMP_EQ_D + "cmp_eq_ph", // MIPS_INS_CMP_EQ_PH + "cmp_eq_s", // MIPS_INS_CMP_EQ_S + "cmp_le_d", // MIPS_INS_CMP_LE_D + "cmp_le_ph", // MIPS_INS_CMP_LE_PH + "cmp_le_s", // MIPS_INS_CMP_LE_S + "cmp_lt_d", // MIPS_INS_CMP_LT_D + "cmp_lt_ph", // MIPS_INS_CMP_LT_PH + "cmp_lt_s", // MIPS_INS_CMP_LT_S + "cmp_saf_d", // MIPS_INS_CMP_SAF_D + "cmp_saf_s", // MIPS_INS_CMP_SAF_S + "cmp_seq_d", // MIPS_INS_CMP_SEQ_D + "cmp_seq_s", // MIPS_INS_CMP_SEQ_S + "cmp_sle_d", // MIPS_INS_CMP_SLE_D + "cmp_sle_s", // MIPS_INS_CMP_SLE_S + "cmp_slt_d", // MIPS_INS_CMP_SLT_D + "cmp_slt_s", // MIPS_INS_CMP_SLT_S + "cmp_sueq_d", // MIPS_INS_CMP_SUEQ_D + "cmp_sueq_s", // MIPS_INS_CMP_SUEQ_S + "cmp_sule_d", // MIPS_INS_CMP_SULE_D + "cmp_sule_s", // MIPS_INS_CMP_SULE_S + "cmp_sult_d", // MIPS_INS_CMP_SULT_D + "cmp_sult_s", // MIPS_INS_CMP_SULT_S + "cmp_sun_d", // MIPS_INS_CMP_SUN_D + "cmp_sun_s", // MIPS_INS_CMP_SUN_S + "cmp_ueq_d", // MIPS_INS_CMP_UEQ_D + "cmp_ueq_s", // MIPS_INS_CMP_UEQ_S + "cmp_ule_d", // MIPS_INS_CMP_ULE_D + "cmp_ule_s", // MIPS_INS_CMP_ULE_S + "cmp_ult_d", // MIPS_INS_CMP_ULT_D + "cmp_ult_s", // MIPS_INS_CMP_ULT_S + "cmp_un_d", // MIPS_INS_CMP_UN_D + "cmp_un_s", // MIPS_INS_CMP_UN_S + "copy_s_b", // MIPS_INS_COPY_S_B + "copy_s_d", // MIPS_INS_COPY_S_D + "copy_s_h", // MIPS_INS_COPY_S_H + "copy_s_w", // MIPS_INS_COPY_S_W + "copy_u_b", // MIPS_INS_COPY_U_B + "copy_u_h", // MIPS_INS_COPY_U_H + "copy_u_w", // MIPS_INS_COPY_U_W + "crc32b", // MIPS_INS_CRC32B + "crc32cb", // MIPS_INS_CRC32CB + "crc32cd", // MIPS_INS_CRC32CD + "crc32ch", // MIPS_INS_CRC32CH + "crc32cw", // MIPS_INS_CRC32CW + "crc32d", // MIPS_INS_CRC32D + "crc32h", // MIPS_INS_CRC32H + "crc32w", // MIPS_INS_CRC32W + "ctc1", // MIPS_INS_CTC1 + "ctc2", // MIPS_INS_CTC2 + "ctcmsa", // MIPS_INS_CTCMSA + "cvt_d_s", // MIPS_INS_CVT_D_S + "cvt_d_w", // MIPS_INS_CVT_D_W + "cvt_d_l", // MIPS_INS_CVT_D_L + "cvt_l_d", // MIPS_INS_CVT_L_D + "cvt_l_s", // MIPS_INS_CVT_L_S + "cvt_ps_pw", // MIPS_INS_CVT_PS_PW + "cvt_ps_s", // MIPS_INS_CVT_PS_S + "cvt_pw_ps", // MIPS_INS_CVT_PW_PS + "cvt_s_d", // MIPS_INS_CVT_S_D + "cvt_s_l", // MIPS_INS_CVT_S_L + "cvt_s_pl", // MIPS_INS_CVT_S_PL + "cvt_s_pu", // MIPS_INS_CVT_S_PU + "cvt_s_w", // MIPS_INS_CVT_S_W + "cvt_w_d", // MIPS_INS_CVT_W_D + "cvt_w_s", // MIPS_INS_CVT_W_S + "c_eq_d", // MIPS_INS_C_EQ_D + "c_eq_s", // MIPS_INS_C_EQ_S + "c_f_d", // MIPS_INS_C_F_D + "c_f_s", // MIPS_INS_C_F_S + "c_le_d", // MIPS_INS_C_LE_D + "c_le_s", // MIPS_INS_C_LE_S + "c_lt_d", // MIPS_INS_C_LT_D + "c_lt_s", // MIPS_INS_C_LT_S + "c_nge_d", // MIPS_INS_C_NGE_D + "c_nge_s", // MIPS_INS_C_NGE_S + "c_ngle_d", // MIPS_INS_C_NGLE_D + "c_ngle_s", // MIPS_INS_C_NGLE_S + "c_ngl_d", // MIPS_INS_C_NGL_D + "c_ngl_s", // MIPS_INS_C_NGL_S + "c_ngt_d", // MIPS_INS_C_NGT_D + "c_ngt_s", // MIPS_INS_C_NGT_S + "c_ole_d", // MIPS_INS_C_OLE_D + "c_ole_s", // MIPS_INS_C_OLE_S + "c_olt_d", // MIPS_INS_C_OLT_D + "c_olt_s", // MIPS_INS_C_OLT_S + "c_seq_d", // MIPS_INS_C_SEQ_D + "c_seq_s", // MIPS_INS_C_SEQ_S + "c_sf_d", // MIPS_INS_C_SF_D + "c_sf_s", // MIPS_INS_C_SF_S + "c_ueq_d", // MIPS_INS_C_UEQ_D + "c_ueq_s", // MIPS_INS_C_UEQ_S + "c_ule_d", // MIPS_INS_C_ULE_D + "c_ule_s", // MIPS_INS_C_ULE_S + "c_ult_d", // MIPS_INS_C_ULT_D + "c_ult_s", // MIPS_INS_C_ULT_S + "c_un_d", // MIPS_INS_C_UN_D + "c_un_s", // MIPS_INS_C_UN_S + "cmp", // MIPS_INS_CMP + "cmpi", // MIPS_INS_CMPI + "dadd", // MIPS_INS_DADD + "daddi", // MIPS_INS_DADDI + "daddiu", // MIPS_INS_DADDIU + "daddu", // MIPS_INS_DADDU + "dahi", // MIPS_INS_DAHI + "dalign", // MIPS_INS_DALIGN + "dati", // MIPS_INS_DATI + "daui", // MIPS_INS_DAUI + "dbitswap", // MIPS_INS_DBITSWAP + "dclo", // MIPS_INS_DCLO + "dclz", // MIPS_INS_DCLZ + "deret", // MIPS_INS_DERET + "dext", // MIPS_INS_DEXT + "dextm", // MIPS_INS_DEXTM + "dextu", // MIPS_INS_DEXTU + "di", // MIPS_INS_DI + "dins", // MIPS_INS_DINS + "dinsm", // MIPS_INS_DINSM + "dinsu", // MIPS_INS_DINSU + "div_s_b", // MIPS_INS_DIV_S_B + "div_s_d", // MIPS_INS_DIV_S_D + "div_s_h", // MIPS_INS_DIV_S_H + "div_s_w", // MIPS_INS_DIV_S_W + "div_u_b", // MIPS_INS_DIV_U_B + "div_u_d", // MIPS_INS_DIV_U_D + "div_u_h", // MIPS_INS_DIV_U_H + "div_u_w", // MIPS_INS_DIV_U_W + "dlsa", // MIPS_INS_DLSA + "dmfc0", // MIPS_INS_DMFC0 + "dmfc1", // MIPS_INS_DMFC1 + "dmfc2", // MIPS_INS_DMFC2 + "dmfgc0", // MIPS_INS_DMFGC0 + "dmod", // MIPS_INS_DMOD + "dmodu", // MIPS_INS_DMODU + "dmt", // MIPS_INS_DMT + "dmtc0", // MIPS_INS_DMTC0 + "dmtc1", // MIPS_INS_DMTC1 + "dmtc2", // MIPS_INS_DMTC2 + "dmtgc0", // MIPS_INS_DMTGC0 + "dmuh", // MIPS_INS_DMUH + "dmuhu", // MIPS_INS_DMUHU + "dmult", // MIPS_INS_DMULT + "dmultu", // MIPS_INS_DMULTU + "dmulu", // MIPS_INS_DMULU + "dotp_s_d", // MIPS_INS_DOTP_S_D + "dotp_s_h", // MIPS_INS_DOTP_S_H + "dotp_s_w", // MIPS_INS_DOTP_S_W + "dotp_u_d", // MIPS_INS_DOTP_U_D + "dotp_u_h", // MIPS_INS_DOTP_U_H + "dotp_u_w", // MIPS_INS_DOTP_U_W + "dpadd_s_d", // MIPS_INS_DPADD_S_D + "dpadd_s_h", // MIPS_INS_DPADD_S_H + "dpadd_s_w", // MIPS_INS_DPADD_S_W + "dpadd_u_d", // MIPS_INS_DPADD_U_D + "dpadd_u_h", // MIPS_INS_DPADD_U_H + "dpadd_u_w", // MIPS_INS_DPADD_U_W + "dpaqx_sa_w_ph", // MIPS_INS_DPAQX_SA_W_PH + "dpaqx_s_w_ph", // MIPS_INS_DPAQX_S_W_PH + "dpaq_sa_l_w", // MIPS_INS_DPAQ_SA_L_W + "dpaq_s_w_ph", // MIPS_INS_DPAQ_S_W_PH + "dpau_h_qbl", // MIPS_INS_DPAU_H_QBL + "dpau_h_qbr", // MIPS_INS_DPAU_H_QBR + "dpax_w_ph", // MIPS_INS_DPAX_W_PH + "dpa_w_ph", // MIPS_INS_DPA_W_PH + "dpop", // MIPS_INS_DPOP + "dpsqx_sa_w_ph", // MIPS_INS_DPSQX_SA_W_PH + "dpsqx_s_w_ph", // MIPS_INS_DPSQX_S_W_PH + "dpsq_sa_l_w", // MIPS_INS_DPSQ_SA_L_W + "dpsq_s_w_ph", // MIPS_INS_DPSQ_S_W_PH + "dpsub_s_d", // MIPS_INS_DPSUB_S_D + "dpsub_s_h", // MIPS_INS_DPSUB_S_H + "dpsub_s_w", // MIPS_INS_DPSUB_S_W + "dpsub_u_d", // MIPS_INS_DPSUB_U_D + "dpsub_u_h", // MIPS_INS_DPSUB_U_H + "dpsub_u_w", // MIPS_INS_DPSUB_U_W + "dpsu_h_qbl", // MIPS_INS_DPSU_H_QBL + "dpsu_h_qbr", // MIPS_INS_DPSU_H_QBR + "dpsx_w_ph", // MIPS_INS_DPSX_W_PH + "dps_w_ph", // MIPS_INS_DPS_W_PH + "drotr", // MIPS_INS_DROTR + "drotr32", // MIPS_INS_DROTR32 + "drotrv", // MIPS_INS_DROTRV + "dsbh", // MIPS_INS_DSBH + "dshd", // MIPS_INS_DSHD + "dsll", // MIPS_INS_DSLL + "dsll32", // MIPS_INS_DSLL32 + "dsllv", // MIPS_INS_DSLLV + "dsra", // MIPS_INS_DSRA + "dsra32", // MIPS_INS_DSRA32 + "dsrav", // MIPS_INS_DSRAV + "dsrl", // MIPS_INS_DSRL + "dsrl32", // MIPS_INS_DSRL32 + "dsrlv", // MIPS_INS_DSRLV + "dsub", // MIPS_INS_DSUB + "dsubu", // MIPS_INS_DSUBU + "dvp", // MIPS_INS_DVP + "dvpe", // MIPS_INS_DVPE + "ehb", // MIPS_INS_EHB + "ei", // MIPS_INS_EI + "emt", // MIPS_INS_EMT + "eret", // MIPS_INS_ERET + "eretnc", // MIPS_INS_ERETNC + "evp", // MIPS_INS_EVP + "evpe", // MIPS_INS_EVPE + "ext", // MIPS_INS_EXT + "extp", // MIPS_INS_EXTP + "extpdp", // MIPS_INS_EXTPDP + "extpdpv", // MIPS_INS_EXTPDPV + "extpv", // MIPS_INS_EXTPV + "extrv_rs_w", // MIPS_INS_EXTRV_RS_W + "extrv_r_w", // MIPS_INS_EXTRV_R_W + "extrv_s_h", // MIPS_INS_EXTRV_S_H + "extrv_w", // MIPS_INS_EXTRV_W + "extr_rs_w", // MIPS_INS_EXTR_RS_W + "extr_r_w", // MIPS_INS_EXTR_R_W + "extr_s_h", // MIPS_INS_EXTR_S_H + "extr_w", // MIPS_INS_EXTR_W + "exts", // MIPS_INS_EXTS + "exts32", // MIPS_INS_EXTS32 + "extw", // MIPS_INS_EXTW + "abs_d", // MIPS_INS_ABS_D + "abs_s", // MIPS_INS_ABS_S + "fadd_d", // MIPS_INS_FADD_D + "add_d", // MIPS_INS_ADD_D + "add_ps", // MIPS_INS_ADD_PS + "add_s", // MIPS_INS_ADD_S + "fadd_w", // MIPS_INS_FADD_W + "fcaf_d", // MIPS_INS_FCAF_D + "fcaf_w", // MIPS_INS_FCAF_W + "fceq_d", // MIPS_INS_FCEQ_D + "fceq_w", // MIPS_INS_FCEQ_W + "fclass_d", // MIPS_INS_FCLASS_D + "fclass_w", // MIPS_INS_FCLASS_W + "fcle_d", // MIPS_INS_FCLE_D + "fcle_w", // MIPS_INS_FCLE_W + "fclt_d", // MIPS_INS_FCLT_D + "fclt_w", // MIPS_INS_FCLT_W + "fcne_d", // MIPS_INS_FCNE_D + "fcne_w", // MIPS_INS_FCNE_W + "fcor_d", // MIPS_INS_FCOR_D + "fcor_w", // MIPS_INS_FCOR_W + "fcueq_d", // MIPS_INS_FCUEQ_D + "fcueq_w", // MIPS_INS_FCUEQ_W + "fcule_d", // MIPS_INS_FCULE_D + "fcule_w", // MIPS_INS_FCULE_W + "fcult_d", // MIPS_INS_FCULT_D + "fcult_w", // MIPS_INS_FCULT_W + "fcune_d", // MIPS_INS_FCUNE_D + "fcune_w", // MIPS_INS_FCUNE_W + "fcun_d", // MIPS_INS_FCUN_D + "fcun_w", // MIPS_INS_FCUN_W + "fdiv_d", // MIPS_INS_FDIV_D + "div_d", // MIPS_INS_DIV_D + "div_s", // MIPS_INS_DIV_S + "fdiv_w", // MIPS_INS_FDIV_W + "fexdo_h", // MIPS_INS_FEXDO_H + "fexdo_w", // MIPS_INS_FEXDO_W + "fexp2_d", // MIPS_INS_FEXP2_D + "fexp2_w", // MIPS_INS_FEXP2_W + "fexupl_d", // MIPS_INS_FEXUPL_D + "fexupl_w", // MIPS_INS_FEXUPL_W + "fexupr_d", // MIPS_INS_FEXUPR_D + "fexupr_w", // MIPS_INS_FEXUPR_W + "ffint_s_d", // MIPS_INS_FFINT_S_D + "ffint_s_w", // MIPS_INS_FFINT_S_W + "ffint_u_d", // MIPS_INS_FFINT_U_D + "ffint_u_w", // MIPS_INS_FFINT_U_W + "ffql_d", // MIPS_INS_FFQL_D + "ffql_w", // MIPS_INS_FFQL_W + "ffqr_d", // MIPS_INS_FFQR_D + "ffqr_w", // MIPS_INS_FFQR_W + "fill_b", // MIPS_INS_FILL_B + "fill_d", // MIPS_INS_FILL_D + "fill_h", // MIPS_INS_FILL_H + "fill_w", // MIPS_INS_FILL_W + "flog2_d", // MIPS_INS_FLOG2_D + "flog2_w", // MIPS_INS_FLOG2_W + "floor_l_d", // MIPS_INS_FLOOR_L_D + "floor_l_s", // MIPS_INS_FLOOR_L_S + "floor_w_d", // MIPS_INS_FLOOR_W_D + "floor_w_s", // MIPS_INS_FLOOR_W_S + "fmadd_d", // MIPS_INS_FMADD_D + "fmadd_w", // MIPS_INS_FMADD_W + "fmax_a_d", // MIPS_INS_FMAX_A_D + "fmax_a_w", // MIPS_INS_FMAX_A_W + "fmax_d", // MIPS_INS_FMAX_D + "fmax_w", // MIPS_INS_FMAX_W + "fmin_a_d", // MIPS_INS_FMIN_A_D + "fmin_a_w", // MIPS_INS_FMIN_A_W + "fmin_d", // MIPS_INS_FMIN_D + "fmin_w", // MIPS_INS_FMIN_W + "mov_d", // MIPS_INS_MOV_D + "mov_s", // MIPS_INS_MOV_S + "fmsub_d", // MIPS_INS_FMSUB_D + "fmsub_w", // MIPS_INS_FMSUB_W + "fmul_d", // MIPS_INS_FMUL_D + "mul_d", // MIPS_INS_MUL_D + "mul_ps", // MIPS_INS_MUL_PS + "mul_s", // MIPS_INS_MUL_S + "fmul_w", // MIPS_INS_FMUL_W + "neg_d", // MIPS_INS_NEG_D + "neg_s", // MIPS_INS_NEG_S + "fork", // MIPS_INS_FORK + "frcp_d", // MIPS_INS_FRCP_D + "frcp_w", // MIPS_INS_FRCP_W + "frint_d", // MIPS_INS_FRINT_D + "frint_w", // MIPS_INS_FRINT_W + "frsqrt_d", // MIPS_INS_FRSQRT_D + "frsqrt_w", // MIPS_INS_FRSQRT_W + "fsaf_d", // MIPS_INS_FSAF_D + "fsaf_w", // MIPS_INS_FSAF_W + "fseq_d", // MIPS_INS_FSEQ_D + "fseq_w", // MIPS_INS_FSEQ_W + "fsle_d", // MIPS_INS_FSLE_D + "fsle_w", // MIPS_INS_FSLE_W + "fslt_d", // MIPS_INS_FSLT_D + "fslt_w", // MIPS_INS_FSLT_W + "fsne_d", // MIPS_INS_FSNE_D + "fsne_w", // MIPS_INS_FSNE_W + "fsor_d", // MIPS_INS_FSOR_D + "fsor_w", // MIPS_INS_FSOR_W + "fsqrt_d", // MIPS_INS_FSQRT_D + "sqrt_d", // MIPS_INS_SQRT_D + "sqrt_s", // MIPS_INS_SQRT_S + "fsqrt_w", // MIPS_INS_FSQRT_W + "fsub_d", // MIPS_INS_FSUB_D + "sub_d", // MIPS_INS_SUB_D + "sub_ps", // MIPS_INS_SUB_PS + "sub_s", // MIPS_INS_SUB_S + "fsub_w", // MIPS_INS_FSUB_W + "fsueq_d", // MIPS_INS_FSUEQ_D + "fsueq_w", // MIPS_INS_FSUEQ_W + "fsule_d", // MIPS_INS_FSULE_D + "fsule_w", // MIPS_INS_FSULE_W + "fsult_d", // MIPS_INS_FSULT_D + "fsult_w", // MIPS_INS_FSULT_W + "fsune_d", // MIPS_INS_FSUNE_D + "fsune_w", // MIPS_INS_FSUNE_W + "fsun_d", // MIPS_INS_FSUN_D + "fsun_w", // MIPS_INS_FSUN_W + "ftint_s_d", // MIPS_INS_FTINT_S_D + "ftint_s_w", // MIPS_INS_FTINT_S_W + "ftint_u_d", // MIPS_INS_FTINT_U_D + "ftint_u_w", // MIPS_INS_FTINT_U_W + "ftq_h", // MIPS_INS_FTQ_H + "ftq_w", // MIPS_INS_FTQ_W + "ftrunc_s_d", // MIPS_INS_FTRUNC_S_D + "ftrunc_s_w", // MIPS_INS_FTRUNC_S_W + "ftrunc_u_d", // MIPS_INS_FTRUNC_U_D + "ftrunc_u_w", // MIPS_INS_FTRUNC_U_W + "ginvi", // MIPS_INS_GINVI + "ginvt", // MIPS_INS_GINVT + "hadd_s_d", // MIPS_INS_HADD_S_D + "hadd_s_h", // MIPS_INS_HADD_S_H + "hadd_s_w", // MIPS_INS_HADD_S_W + "hadd_u_d", // MIPS_INS_HADD_U_D + "hadd_u_h", // MIPS_INS_HADD_U_H + "hadd_u_w", // MIPS_INS_HADD_U_W + "hsub_s_d", // MIPS_INS_HSUB_S_D + "hsub_s_h", // MIPS_INS_HSUB_S_H + "hsub_s_w", // MIPS_INS_HSUB_S_W + "hsub_u_d", // MIPS_INS_HSUB_U_D + "hsub_u_h", // MIPS_INS_HSUB_U_H + "hsub_u_w", // MIPS_INS_HSUB_U_W + "hypcall", // MIPS_INS_HYPCALL + "ilvev_b", // MIPS_INS_ILVEV_B + "ilvev_d", // MIPS_INS_ILVEV_D + "ilvev_h", // MIPS_INS_ILVEV_H + "ilvev_w", // MIPS_INS_ILVEV_W + "ilvl_b", // MIPS_INS_ILVL_B + "ilvl_d", // MIPS_INS_ILVL_D + "ilvl_h", // MIPS_INS_ILVL_H + "ilvl_w", // MIPS_INS_ILVL_W + "ilvod_b", // MIPS_INS_ILVOD_B + "ilvod_d", // MIPS_INS_ILVOD_D + "ilvod_h", // MIPS_INS_ILVOD_H + "ilvod_w", // MIPS_INS_ILVOD_W + "ilvr_b", // MIPS_INS_ILVR_B + "ilvr_d", // MIPS_INS_ILVR_D + "ilvr_h", // MIPS_INS_ILVR_H + "ilvr_w", // MIPS_INS_ILVR_W + "ins", // MIPS_INS_INS + "insert_b", // MIPS_INS_INSERT_B + "insert_d", // MIPS_INS_INSERT_D + "insert_h", // MIPS_INS_INSERT_H + "insert_w", // MIPS_INS_INSERT_W + "insv", // MIPS_INS_INSV + "insve_b", // MIPS_INS_INSVE_B + "insve_d", // MIPS_INS_INSVE_D + "insve_h", // MIPS_INS_INSVE_H + "insve_w", // MIPS_INS_INSVE_W + "j", // MIPS_INS_J + "jalr", // MIPS_INS_JALR + "jalrc", // MIPS_INS_JALRC + "jalrc_hb", // MIPS_INS_JALRC_HB + "jalrs16", // MIPS_INS_JALRS16 + "jalrs", // MIPS_INS_JALRS + "jalr_hb", // MIPS_INS_JALR_HB + "jals", // MIPS_INS_JALS + "jalx", // MIPS_INS_JALX + "jialc", // MIPS_INS_JIALC + "jic", // MIPS_INS_JIC + "jr", // MIPS_INS_JR + "jr16", // MIPS_INS_JR16 + "jraddiusp", // MIPS_INS_JRADDIUSP + "jrc", // MIPS_INS_JRC + "jrc16", // MIPS_INS_JRC16 + "jrcaddiusp", // MIPS_INS_JRCADDIUSP + "jr_hb", // MIPS_INS_JR_HB + "lapc_h", // MIPS_INS_LAPC_H + "lapc_b", // MIPS_INS_LAPC_B + "lb", // MIPS_INS_LB + "lbe", // MIPS_INS_LBE + "lbu16", // MIPS_INS_LBU16 + "lbu", // MIPS_INS_LBU + "lbux", // MIPS_INS_LBUX + "lbx", // MIPS_INS_LBX + "lbue", // MIPS_INS_LBUE + "ldc1", // MIPS_INS_LDC1 + "ldc2", // MIPS_INS_LDC2 + "ldc3", // MIPS_INS_LDC3 + "ldi_b", // MIPS_INS_LDI_B + "ldi_d", // MIPS_INS_LDI_D + "ldi_h", // MIPS_INS_LDI_H + "ldi_w", // MIPS_INS_LDI_W + "ldl", // MIPS_INS_LDL + "ldpc", // MIPS_INS_LDPC + "ldr", // MIPS_INS_LDR + "ldxc1", // MIPS_INS_LDXC1 + "ld_b", // MIPS_INS_LD_B + "ld_d", // MIPS_INS_LD_D + "ld_h", // MIPS_INS_LD_H + "ld_w", // MIPS_INS_LD_W + "lh", // MIPS_INS_LH + "lhe", // MIPS_INS_LHE + "lhu16", // MIPS_INS_LHU16 + "lhu", // MIPS_INS_LHU + "lhuxs", // MIPS_INS_LHUXS + "lhux", // MIPS_INS_LHUX + "lhx", // MIPS_INS_LHX + "lhxs", // MIPS_INS_LHXS + "lhue", // MIPS_INS_LHUE + "li16", // MIPS_INS_LI16 + "ll", // MIPS_INS_LL + "lld", // MIPS_INS_LLD + "lle", // MIPS_INS_LLE + "llwp", // MIPS_INS_LLWP + "lsa", // MIPS_INS_LSA + "lui", // MIPS_INS_LUI + "luxc1", // MIPS_INS_LUXC1 + "lw", // MIPS_INS_LW + "lw16", // MIPS_INS_LW16 + "lwc1", // MIPS_INS_LWC1 + "lwc2", // MIPS_INS_LWC2 + "lwc3", // MIPS_INS_LWC3 + "lwe", // MIPS_INS_LWE + "lwl", // MIPS_INS_LWL + "lwle", // MIPS_INS_LWLE + "lwm16", // MIPS_INS_LWM16 + "lwm32", // MIPS_INS_LWM32 + "lwpc", // MIPS_INS_LWPC + "lwp", // MIPS_INS_LWP + "lwr", // MIPS_INS_LWR + "lwre", // MIPS_INS_LWRE + "lwupc", // MIPS_INS_LWUPC + "lwu", // MIPS_INS_LWU + "lwx", // MIPS_INS_LWX + "lwxc1", // MIPS_INS_LWXC1 + "lwxs", // MIPS_INS_LWXS + "madd", // MIPS_INS_MADD + "maddf_d", // MIPS_INS_MADDF_D + "maddf_s", // MIPS_INS_MADDF_S + "maddr_q_h", // MIPS_INS_MADDR_Q_H + "maddr_q_w", // MIPS_INS_MADDR_Q_W + "maddu", // MIPS_INS_MADDU + "maddv_b", // MIPS_INS_MADDV_B + "maddv_d", // MIPS_INS_MADDV_D + "maddv_h", // MIPS_INS_MADDV_H + "maddv_w", // MIPS_INS_MADDV_W + "madd_d", // MIPS_INS_MADD_D + "madd_q_h", // MIPS_INS_MADD_Q_H + "madd_q_w", // MIPS_INS_MADD_Q_W + "madd_s", // MIPS_INS_MADD_S + "maq_sa_w_phl", // MIPS_INS_MAQ_SA_W_PHL + "maq_sa_w_phr", // MIPS_INS_MAQ_SA_W_PHR + "maq_s_w_phl", // MIPS_INS_MAQ_S_W_PHL + "maq_s_w_phr", // MIPS_INS_MAQ_S_W_PHR + "maxa_d", // MIPS_INS_MAXA_D + "maxa_s", // MIPS_INS_MAXA_S + "maxi_s_b", // MIPS_INS_MAXI_S_B + "maxi_s_d", // MIPS_INS_MAXI_S_D + "maxi_s_h", // MIPS_INS_MAXI_S_H + "maxi_s_w", // MIPS_INS_MAXI_S_W + "maxi_u_b", // MIPS_INS_MAXI_U_B + "maxi_u_d", // MIPS_INS_MAXI_U_D + "maxi_u_h", // MIPS_INS_MAXI_U_H + "maxi_u_w", // MIPS_INS_MAXI_U_W + "max_a_b", // MIPS_INS_MAX_A_B + "max_a_d", // MIPS_INS_MAX_A_D + "max_a_h", // MIPS_INS_MAX_A_H + "max_a_w", // MIPS_INS_MAX_A_W + "max_d", // MIPS_INS_MAX_D + "max_s", // MIPS_INS_MAX_S + "max_s_b", // MIPS_INS_MAX_S_B + "max_s_d", // MIPS_INS_MAX_S_D + "max_s_h", // MIPS_INS_MAX_S_H + "max_s_w", // MIPS_INS_MAX_S_W + "max_u_b", // MIPS_INS_MAX_U_B + "max_u_d", // MIPS_INS_MAX_U_D + "max_u_h", // MIPS_INS_MAX_U_H + "max_u_w", // MIPS_INS_MAX_U_W + "mfc0", // MIPS_INS_MFC0 + "mfc1", // MIPS_INS_MFC1 + "mfc2", // MIPS_INS_MFC2 + "mfgc0", // MIPS_INS_MFGC0 + "mfhc0", // MIPS_INS_MFHC0 + "mfhc1", // MIPS_INS_MFHC1 + "mfhc2", // MIPS_INS_MFHC2 + "mfhgc0", // MIPS_INS_MFHGC0 + "mfhi", // MIPS_INS_MFHI + "mfhi16", // MIPS_INS_MFHI16 + "mflo", // MIPS_INS_MFLO + "mflo16", // MIPS_INS_MFLO16 + "mftr", // MIPS_INS_MFTR + "mina_d", // MIPS_INS_MINA_D + "mina_s", // MIPS_INS_MINA_S + "mini_s_b", // MIPS_INS_MINI_S_B + "mini_s_d", // MIPS_INS_MINI_S_D + "mini_s_h", // MIPS_INS_MINI_S_H + "mini_s_w", // MIPS_INS_MINI_S_W + "mini_u_b", // MIPS_INS_MINI_U_B + "mini_u_d", // MIPS_INS_MINI_U_D + "mini_u_h", // MIPS_INS_MINI_U_H + "mini_u_w", // MIPS_INS_MINI_U_W + "min_a_b", // MIPS_INS_MIN_A_B + "min_a_d", // MIPS_INS_MIN_A_D + "min_a_h", // MIPS_INS_MIN_A_H + "min_a_w", // MIPS_INS_MIN_A_W + "min_d", // MIPS_INS_MIN_D + "min_s", // MIPS_INS_MIN_S + "min_s_b", // MIPS_INS_MIN_S_B + "min_s_d", // MIPS_INS_MIN_S_D + "min_s_h", // MIPS_INS_MIN_S_H + "min_s_w", // MIPS_INS_MIN_S_W + "min_u_b", // MIPS_INS_MIN_U_B + "min_u_d", // MIPS_INS_MIN_U_D + "min_u_h", // MIPS_INS_MIN_U_H + "min_u_w", // MIPS_INS_MIN_U_W + "mod", // MIPS_INS_MOD + "modsub", // MIPS_INS_MODSUB + "modu", // MIPS_INS_MODU + "mod_s_b", // MIPS_INS_MOD_S_B + "mod_s_d", // MIPS_INS_MOD_S_D + "mod_s_h", // MIPS_INS_MOD_S_H + "mod_s_w", // MIPS_INS_MOD_S_W + "mod_u_b", // MIPS_INS_MOD_U_B + "mod_u_d", // MIPS_INS_MOD_U_D + "mod_u_h", // MIPS_INS_MOD_U_H + "mod_u_w", // MIPS_INS_MOD_U_W + "move", // MIPS_INS_MOVE + "move16", // MIPS_INS_MOVE16 + "move_balc", // MIPS_INS_MOVE_BALC + "movep", // MIPS_INS_MOVEP + "move_v", // MIPS_INS_MOVE_V + "movf_d", // MIPS_INS_MOVF_D + "movf", // MIPS_INS_MOVF + "movf_s", // MIPS_INS_MOVF_S + "movn_d", // MIPS_INS_MOVN_D + "movn", // MIPS_INS_MOVN + "movn_s", // MIPS_INS_MOVN_S + "movt_d", // MIPS_INS_MOVT_D + "movt", // MIPS_INS_MOVT + "movt_s", // MIPS_INS_MOVT_S + "movz_d", // MIPS_INS_MOVZ_D + "movz", // MIPS_INS_MOVZ + "movz_s", // MIPS_INS_MOVZ_S + "msub", // MIPS_INS_MSUB + "msubf_d", // MIPS_INS_MSUBF_D + "msubf_s", // MIPS_INS_MSUBF_S + "msubr_q_h", // MIPS_INS_MSUBR_Q_H + "msubr_q_w", // MIPS_INS_MSUBR_Q_W + "msubu", // MIPS_INS_MSUBU + "msubv_b", // MIPS_INS_MSUBV_B + "msubv_d", // MIPS_INS_MSUBV_D + "msubv_h", // MIPS_INS_MSUBV_H + "msubv_w", // MIPS_INS_MSUBV_W + "msub_d", // MIPS_INS_MSUB_D + "msub_q_h", // MIPS_INS_MSUB_Q_H + "msub_q_w", // MIPS_INS_MSUB_Q_W + "msub_s", // MIPS_INS_MSUB_S + "mtc0", // MIPS_INS_MTC0 + "mtc1", // MIPS_INS_MTC1 + "mtc2", // MIPS_INS_MTC2 + "mtgc0", // MIPS_INS_MTGC0 + "mthc0", // MIPS_INS_MTHC0 + "mthc1", // MIPS_INS_MTHC1 + "mthc2", // MIPS_INS_MTHC2 + "mthgc0", // MIPS_INS_MTHGC0 + "mthi", // MIPS_INS_MTHI + "mthlip", // MIPS_INS_MTHLIP + "mtlo", // MIPS_INS_MTLO + "mtm0", // MIPS_INS_MTM0 + "mtm1", // MIPS_INS_MTM1 + "mtm2", // MIPS_INS_MTM2 + "mtp0", // MIPS_INS_MTP0 + "mtp1", // MIPS_INS_MTP1 + "mtp2", // MIPS_INS_MTP2 + "mttr", // MIPS_INS_MTTR + "muh", // MIPS_INS_MUH + "muhu", // MIPS_INS_MUHU + "muleq_s_w_phl", // MIPS_INS_MULEQ_S_W_PHL + "muleq_s_w_phr", // MIPS_INS_MULEQ_S_W_PHR + "muleu_s_ph_qbl", // MIPS_INS_MULEU_S_PH_QBL + "muleu_s_ph_qbr", // MIPS_INS_MULEU_S_PH_QBR + "mulq_rs_ph", // MIPS_INS_MULQ_RS_PH + "mulq_rs_w", // MIPS_INS_MULQ_RS_W + "mulq_s_ph", // MIPS_INS_MULQ_S_PH + "mulq_s_w", // MIPS_INS_MULQ_S_W + "mulr_ps", // MIPS_INS_MULR_PS + "mulr_q_h", // MIPS_INS_MULR_Q_H + "mulr_q_w", // MIPS_INS_MULR_Q_W + "mulsaq_s_w_ph", // MIPS_INS_MULSAQ_S_W_PH + "mulsa_w_ph", // MIPS_INS_MULSA_W_PH + "mult", // MIPS_INS_MULT + "multu", // MIPS_INS_MULTU + "mulu", // MIPS_INS_MULU + "mulv_b", // MIPS_INS_MULV_B + "mulv_d", // MIPS_INS_MULV_D + "mulv_h", // MIPS_INS_MULV_H + "mulv_w", // MIPS_INS_MULV_W + "mul_ph", // MIPS_INS_MUL_PH + "mul_q_h", // MIPS_INS_MUL_Q_H + "mul_q_w", // MIPS_INS_MUL_Q_W + "mul_s_ph", // MIPS_INS_MUL_S_PH + "nloc_b", // MIPS_INS_NLOC_B + "nloc_d", // MIPS_INS_NLOC_D + "nloc_h", // MIPS_INS_NLOC_H + "nloc_w", // MIPS_INS_NLOC_W + "nlzc_b", // MIPS_INS_NLZC_B + "nlzc_d", // MIPS_INS_NLZC_D + "nlzc_h", // MIPS_INS_NLZC_H + "nlzc_w", // MIPS_INS_NLZC_W + "nmadd_d", // MIPS_INS_NMADD_D + "nmadd_s", // MIPS_INS_NMADD_S + "nmsub_d", // MIPS_INS_NMSUB_D + "nmsub_s", // MIPS_INS_NMSUB_S + "nop32", // MIPS_INS_NOP32 + "nop", // MIPS_INS_NOP + "nori_b", // MIPS_INS_NORI_B + "nor_v", // MIPS_INS_NOR_V + "not16", // MIPS_INS_NOT16 + "not", // MIPS_INS_NOT + "neg", // MIPS_INS_NEG + "or", // MIPS_INS_OR + "or16", // MIPS_INS_OR16 + "ori_b", // MIPS_INS_ORI_B + "ori", // MIPS_INS_ORI + "or_v", // MIPS_INS_OR_V + "packrl_ph", // MIPS_INS_PACKRL_PH + "pause", // MIPS_INS_PAUSE + "pckev_b", // MIPS_INS_PCKEV_B + "pckev_d", // MIPS_INS_PCKEV_D + "pckev_h", // MIPS_INS_PCKEV_H + "pckev_w", // MIPS_INS_PCKEV_W + "pckod_b", // MIPS_INS_PCKOD_B + "pckod_d", // MIPS_INS_PCKOD_D + "pckod_h", // MIPS_INS_PCKOD_H + "pckod_w", // MIPS_INS_PCKOD_W + "pcnt_b", // MIPS_INS_PCNT_B + "pcnt_d", // MIPS_INS_PCNT_D + "pcnt_h", // MIPS_INS_PCNT_H + "pcnt_w", // MIPS_INS_PCNT_W + "pick_ph", // MIPS_INS_PICK_PH + "pick_qb", // MIPS_INS_PICK_QB + "pll_ps", // MIPS_INS_PLL_PS + "plu_ps", // MIPS_INS_PLU_PS + "pop", // MIPS_INS_POP + "precequ_ph_qbl", // MIPS_INS_PRECEQU_PH_QBL + "precequ_ph_qbla", // MIPS_INS_PRECEQU_PH_QBLA + "precequ_ph_qbr", // MIPS_INS_PRECEQU_PH_QBR + "precequ_ph_qbra", // MIPS_INS_PRECEQU_PH_QBRA + "preceq_w_phl", // MIPS_INS_PRECEQ_W_PHL + "preceq_w_phr", // MIPS_INS_PRECEQ_W_PHR + "preceu_ph_qbl", // MIPS_INS_PRECEU_PH_QBL + "preceu_ph_qbla", // MIPS_INS_PRECEU_PH_QBLA + "preceu_ph_qbr", // MIPS_INS_PRECEU_PH_QBR + "preceu_ph_qbra", // MIPS_INS_PRECEU_PH_QBRA + "precrqu_s_qb_ph", // MIPS_INS_PRECRQU_S_QB_PH + "precrq_ph_w", // MIPS_INS_PRECRQ_PH_W + "precrq_qb_ph", // MIPS_INS_PRECRQ_QB_PH + "precrq_rs_ph_w", // MIPS_INS_PRECRQ_RS_PH_W + "precr_qb_ph", // MIPS_INS_PRECR_QB_PH + "precr_sra_ph_w", // MIPS_INS_PRECR_SRA_PH_W + "precr_sra_r_ph_w", // MIPS_INS_PRECR_SRA_R_PH_W + "pref", // MIPS_INS_PREF + "prefe", // MIPS_INS_PREFE + "prefx", // MIPS_INS_PREFX + "prepend", // MIPS_INS_PREPEND + "pul_ps", // MIPS_INS_PUL_PS + "puu_ps", // MIPS_INS_PUU_PS + "raddu_w_qb", // MIPS_INS_RADDU_W_QB + "rddsp", // MIPS_INS_RDDSP + "rdhwr", // MIPS_INS_RDHWR + "rdpgpr", // MIPS_INS_RDPGPR + "recip_d", // MIPS_INS_RECIP_D + "recip_s", // MIPS_INS_RECIP_S + "replv_ph", // MIPS_INS_REPLV_PH + "replv_qb", // MIPS_INS_REPLV_QB + "repl_ph", // MIPS_INS_REPL_PH + "repl_qb", // MIPS_INS_REPL_QB + "restore_jrc", // MIPS_INS_RESTORE_JRC + "restore", // MIPS_INS_RESTORE + "rint_d", // MIPS_INS_RINT_D + "rint_s", // MIPS_INS_RINT_S + "rotr", // MIPS_INS_ROTR + "rotrv", // MIPS_INS_ROTRV + "rotx", // MIPS_INS_ROTX + "round_l_d", // MIPS_INS_ROUND_L_D + "round_l_s", // MIPS_INS_ROUND_L_S + "round_w_d", // MIPS_INS_ROUND_W_D + "round_w_s", // MIPS_INS_ROUND_W_S + "rsqrt_d", // MIPS_INS_RSQRT_D + "rsqrt_s", // MIPS_INS_RSQRT_S + "sat_s_b", // MIPS_INS_SAT_S_B + "sat_s_d", // MIPS_INS_SAT_S_D + "sat_s_h", // MIPS_INS_SAT_S_H + "sat_s_w", // MIPS_INS_SAT_S_W + "sat_u_b", // MIPS_INS_SAT_U_B + "sat_u_d", // MIPS_INS_SAT_U_D + "sat_u_h", // MIPS_INS_SAT_U_H + "sat_u_w", // MIPS_INS_SAT_U_W + "save", // MIPS_INS_SAVE + "sb", // MIPS_INS_SB + "sb16", // MIPS_INS_SB16 + "sbe", // MIPS_INS_SBE + "sbx", // MIPS_INS_SBX + "sc", // MIPS_INS_SC + "scd", // MIPS_INS_SCD + "sce", // MIPS_INS_SCE + "scwp", // MIPS_INS_SCWP + "sdbbp", // MIPS_INS_SDBBP + "sdbbp16", // MIPS_INS_SDBBP16 + "sdc1", // MIPS_INS_SDC1 + "sdc2", // MIPS_INS_SDC2 + "sdc3", // MIPS_INS_SDC3 + "sdl", // MIPS_INS_SDL + "sdr", // MIPS_INS_SDR + "sdxc1", // MIPS_INS_SDXC1 + "seb", // MIPS_INS_SEB + "seh", // MIPS_INS_SEH + "seleqz", // MIPS_INS_SELEQZ + "seleqz_d", // MIPS_INS_SELEQZ_D + "seleqz_s", // MIPS_INS_SELEQZ_S + "selnez", // MIPS_INS_SELNEZ + "selnez_d", // MIPS_INS_SELNEZ_D + "selnez_s", // MIPS_INS_SELNEZ_S + "sel_d", // MIPS_INS_SEL_D + "sel_s", // MIPS_INS_SEL_S + "seqi", // MIPS_INS_SEQI + "sh", // MIPS_INS_SH + "sh16", // MIPS_INS_SH16 + "she", // MIPS_INS_SHE + "shf_b", // MIPS_INS_SHF_B + "shf_h", // MIPS_INS_SHF_H + "shf_w", // MIPS_INS_SHF_W + "shilo", // MIPS_INS_SHILO + "shilov", // MIPS_INS_SHILOV + "shllv_ph", // MIPS_INS_SHLLV_PH + "shllv_qb", // MIPS_INS_SHLLV_QB + "shllv_s_ph", // MIPS_INS_SHLLV_S_PH + "shllv_s_w", // MIPS_INS_SHLLV_S_W + "shll_ph", // MIPS_INS_SHLL_PH + "shll_qb", // MIPS_INS_SHLL_QB + "shll_s_ph", // MIPS_INS_SHLL_S_PH + "shll_s_w", // MIPS_INS_SHLL_S_W + "shrav_ph", // MIPS_INS_SHRAV_PH + "shrav_qb", // MIPS_INS_SHRAV_QB + "shrav_r_ph", // MIPS_INS_SHRAV_R_PH + "shrav_r_qb", // MIPS_INS_SHRAV_R_QB + "shrav_r_w", // MIPS_INS_SHRAV_R_W + "shra_ph", // MIPS_INS_SHRA_PH + "shra_qb", // MIPS_INS_SHRA_QB + "shra_r_ph", // MIPS_INS_SHRA_R_PH + "shra_r_qb", // MIPS_INS_SHRA_R_QB + "shra_r_w", // MIPS_INS_SHRA_R_W + "shrlv_ph", // MIPS_INS_SHRLV_PH + "shrlv_qb", // MIPS_INS_SHRLV_QB + "shrl_ph", // MIPS_INS_SHRL_PH + "shrl_qb", // MIPS_INS_SHRL_QB + "shxs", // MIPS_INS_SHXS + "shx", // MIPS_INS_SHX + "sigrie", // MIPS_INS_SIGRIE + "sldi_b", // MIPS_INS_SLDI_B + "sldi_d", // MIPS_INS_SLDI_D + "sldi_h", // MIPS_INS_SLDI_H + "sldi_w", // MIPS_INS_SLDI_W + "sld_b", // MIPS_INS_SLD_B + "sld_d", // MIPS_INS_SLD_D + "sld_h", // MIPS_INS_SLD_H + "sld_w", // MIPS_INS_SLD_W + "sll", // MIPS_INS_SLL + "sll16", // MIPS_INS_SLL16 + "slli_b", // MIPS_INS_SLLI_B + "slli_d", // MIPS_INS_SLLI_D + "slli_h", // MIPS_INS_SLLI_H + "slli_w", // MIPS_INS_SLLI_W + "sllv", // MIPS_INS_SLLV + "sll_b", // MIPS_INS_SLL_B + "sll_d", // MIPS_INS_SLL_D + "sll_h", // MIPS_INS_SLL_H + "sll_w", // MIPS_INS_SLL_W + "sltiu", // MIPS_INS_SLTIU + "slti", // MIPS_INS_SLTI + "snei", // MIPS_INS_SNEI + "sov", // MIPS_INS_SOV + "splati_b", // MIPS_INS_SPLATI_B + "splati_d", // MIPS_INS_SPLATI_D + "splati_h", // MIPS_INS_SPLATI_H + "splati_w", // MIPS_INS_SPLATI_W + "splat_b", // MIPS_INS_SPLAT_B + "splat_d", // MIPS_INS_SPLAT_D + "splat_h", // MIPS_INS_SPLAT_H + "splat_w", // MIPS_INS_SPLAT_W + "sra", // MIPS_INS_SRA + "srai_b", // MIPS_INS_SRAI_B + "srai_d", // MIPS_INS_SRAI_D + "srai_h", // MIPS_INS_SRAI_H + "srai_w", // MIPS_INS_SRAI_W + "srari_b", // MIPS_INS_SRARI_B + "srari_d", // MIPS_INS_SRARI_D + "srari_h", // MIPS_INS_SRARI_H + "srari_w", // MIPS_INS_SRARI_W + "srar_b", // MIPS_INS_SRAR_B + "srar_d", // MIPS_INS_SRAR_D + "srar_h", // MIPS_INS_SRAR_H + "srar_w", // MIPS_INS_SRAR_W + "srav", // MIPS_INS_SRAV + "sra_b", // MIPS_INS_SRA_B + "sra_d", // MIPS_INS_SRA_D + "sra_h", // MIPS_INS_SRA_H + "sra_w", // MIPS_INS_SRA_W + "srl", // MIPS_INS_SRL + "srl16", // MIPS_INS_SRL16 + "srli_b", // MIPS_INS_SRLI_B + "srli_d", // MIPS_INS_SRLI_D + "srli_h", // MIPS_INS_SRLI_H + "srli_w", // MIPS_INS_SRLI_W + "srlri_b", // MIPS_INS_SRLRI_B + "srlri_d", // MIPS_INS_SRLRI_D + "srlri_h", // MIPS_INS_SRLRI_H + "srlri_w", // MIPS_INS_SRLRI_W + "srlr_b", // MIPS_INS_SRLR_B + "srlr_d", // MIPS_INS_SRLR_D + "srlr_h", // MIPS_INS_SRLR_H + "srlr_w", // MIPS_INS_SRLR_W + "srlv", // MIPS_INS_SRLV + "srl_b", // MIPS_INS_SRL_B + "srl_d", // MIPS_INS_SRL_D + "srl_h", // MIPS_INS_SRL_H + "srl_w", // MIPS_INS_SRL_W + "ssnop", // MIPS_INS_SSNOP + "st_b", // MIPS_INS_ST_B + "st_d", // MIPS_INS_ST_D + "st_h", // MIPS_INS_ST_H + "st_w", // MIPS_INS_ST_W + "sub", // MIPS_INS_SUB + "subqh_ph", // MIPS_INS_SUBQH_PH + "subqh_r_ph", // MIPS_INS_SUBQH_R_PH + "subqh_r_w", // MIPS_INS_SUBQH_R_W + "subqh_w", // MIPS_INS_SUBQH_W + "subq_ph", // MIPS_INS_SUBQ_PH + "subq_s_ph", // MIPS_INS_SUBQ_S_PH + "subq_s_w", // MIPS_INS_SUBQ_S_W + "subsus_u_b", // MIPS_INS_SUBSUS_U_B + "subsus_u_d", // MIPS_INS_SUBSUS_U_D + "subsus_u_h", // MIPS_INS_SUBSUS_U_H + "subsus_u_w", // MIPS_INS_SUBSUS_U_W + "subsuu_s_b", // MIPS_INS_SUBSUU_S_B + "subsuu_s_d", // MIPS_INS_SUBSUU_S_D + "subsuu_s_h", // MIPS_INS_SUBSUU_S_H + "subsuu_s_w", // MIPS_INS_SUBSUU_S_W + "subs_s_b", // MIPS_INS_SUBS_S_B + "subs_s_d", // MIPS_INS_SUBS_S_D + "subs_s_h", // MIPS_INS_SUBS_S_H + "subs_s_w", // MIPS_INS_SUBS_S_W + "subs_u_b", // MIPS_INS_SUBS_U_B + "subs_u_d", // MIPS_INS_SUBS_U_D + "subs_u_h", // MIPS_INS_SUBS_U_H + "subs_u_w", // MIPS_INS_SUBS_U_W + "subu16", // MIPS_INS_SUBU16 + "subuh_qb", // MIPS_INS_SUBUH_QB + "subuh_r_qb", // MIPS_INS_SUBUH_R_QB + "subu_ph", // MIPS_INS_SUBU_PH + "subu_qb", // MIPS_INS_SUBU_QB + "subu_s_ph", // MIPS_INS_SUBU_S_PH + "subu_s_qb", // MIPS_INS_SUBU_S_QB + "subvi_b", // MIPS_INS_SUBVI_B + "subvi_d", // MIPS_INS_SUBVI_D + "subvi_h", // MIPS_INS_SUBVI_H + "subvi_w", // MIPS_INS_SUBVI_W + "subv_b", // MIPS_INS_SUBV_B + "subv_d", // MIPS_INS_SUBV_D + "subv_h", // MIPS_INS_SUBV_H + "subv_w", // MIPS_INS_SUBV_W + "suxc1", // MIPS_INS_SUXC1 + "sw", // MIPS_INS_SW + "sw16", // MIPS_INS_SW16 + "swc1", // MIPS_INS_SWC1 + "swc2", // MIPS_INS_SWC2 + "swc3", // MIPS_INS_SWC3 + "swe", // MIPS_INS_SWE + "swl", // MIPS_INS_SWL + "swle", // MIPS_INS_SWLE + "swm16", // MIPS_INS_SWM16 + "swm32", // MIPS_INS_SWM32 + "swpc", // MIPS_INS_SWPC + "swp", // MIPS_INS_SWP + "swr", // MIPS_INS_SWR + "swre", // MIPS_INS_SWRE + "swsp", // MIPS_INS_SWSP + "swxc1", // MIPS_INS_SWXC1 + "swxs", // MIPS_INS_SWXS + "swx", // MIPS_INS_SWX + "sync", // MIPS_INS_SYNC + "synci", // MIPS_INS_SYNCI + "syscall", // MIPS_INS_SYSCALL + "teq", // MIPS_INS_TEQ + "teqi", // MIPS_INS_TEQI + "tge", // MIPS_INS_TGE + "tgei", // MIPS_INS_TGEI + "tgeiu", // MIPS_INS_TGEIU + "tgeu", // MIPS_INS_TGEU + "tlbginv", // MIPS_INS_TLBGINV + "tlbginvf", // MIPS_INS_TLBGINVF + "tlbgp", // MIPS_INS_TLBGP + "tlbgr", // MIPS_INS_TLBGR + "tlbgwi", // MIPS_INS_TLBGWI + "tlbgwr", // MIPS_INS_TLBGWR + "tlbinv", // MIPS_INS_TLBINV + "tlbinvf", // MIPS_INS_TLBINVF + "tlbp", // MIPS_INS_TLBP + "tlbr", // MIPS_INS_TLBR + "tlbwi", // MIPS_INS_TLBWI + "tlbwr", // MIPS_INS_TLBWR + "tlt", // MIPS_INS_TLT + "tlti", // MIPS_INS_TLTI + "tltiu", // MIPS_INS_TLTIU + "tltu", // MIPS_INS_TLTU + "tne", // MIPS_INS_TNE + "tnei", // MIPS_INS_TNEI + "trunc_l_d", // MIPS_INS_TRUNC_L_D + "trunc_l_s", // MIPS_INS_TRUNC_L_S + "ualh", // MIPS_INS_UALH + "ualwm", // MIPS_INS_UALWM + "ualw", // MIPS_INS_UALW + "uash", // MIPS_INS_UASH + "uaswm", // MIPS_INS_UASWM + "uasw", // MIPS_INS_UASW + "v3mulu", // MIPS_INS_V3MULU + "vmm0", // MIPS_INS_VMM0 + "vmulu", // MIPS_INS_VMULU + "vshf_b", // MIPS_INS_VSHF_B + "vshf_d", // MIPS_INS_VSHF_D + "vshf_h", // MIPS_INS_VSHF_H + "vshf_w", // MIPS_INS_VSHF_W + "wait", // MIPS_INS_WAIT + "wrdsp", // MIPS_INS_WRDSP + "wrpgpr", // MIPS_INS_WRPGPR + "wsbh", // MIPS_INS_WSBH + "xor", // MIPS_INS_XOR + "xor16", // MIPS_INS_XOR16 + "xori_b", // MIPS_INS_XORI_B + "xori", // MIPS_INS_XORI + "xor_v", // MIPS_INS_XOR_V + "yield", // MIPS_INS_YIELD diff --git a/arch/Mips/MipsGenCSMappingInsnOp.inc b/arch/Mips/MipsGenCSMappingInsnOp.inc new file mode 100644 index 000000000..e2a978ebd --- /dev/null +++ b/arch/Mips/MipsGenCSMappingInsnOp.inc @@ -0,0 +1,18615 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{{{ /* MIPS_PHI (0) - MIPS_INS_INVALID - PHINODE */ + 0 +}}}, +{{{ /* MIPS_INLINEASM (1) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INLINEASM_BR (2) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_CFI_INSTRUCTION (3) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_EH_LABEL (4) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_GC_LABEL (5) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ANNOTATION_LABEL (6) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_KILL (7) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_EXTRACT_SUBREG (8) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_SUBREG (9) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_IMPLICIT_DEF (10) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SUBREG_TO_REG (11) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_COPY_TO_REGCLASS (12) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_DBG_VALUE (13) - MIPS_INS_INVALID - DBG_VALUE */ + 0 +}}}, +{{{ /* MIPS_DBG_VALUE_LIST (14) - MIPS_INS_INVALID - DBG_VALUE_LIST */ + 0 +}}}, +{{{ /* MIPS_DBG_INSTR_REF (15) - MIPS_INS_INVALID - DBG_INSTR_REF */ + 0 +}}}, +{{{ /* MIPS_DBG_PHI (16) - MIPS_INS_INVALID - DBG_PHI */ + 0 +}}}, +{{{ /* MIPS_DBG_LABEL (17) - MIPS_INS_INVALID - DBG_LABEL */ + 0 +}}}, +{{{ /* MIPS_REG_SEQUENCE (18) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_COPY (19) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BUNDLE (20) - MIPS_INS_INVALID - BUNDLE */ + 0 +}}}, +{{{ /* MIPS_LIFETIME_START (21) - MIPS_INS_INVALID - LIFETIME_START */ + 0 +}}}, +{{{ /* MIPS_LIFETIME_END (22) - MIPS_INS_INVALID - LIFETIME_END */ + 0 +}}}, +{{{ /* MIPS_PSEUDO_PROBE (23) - MIPS_INS_INVALID - PSEUDO_PROBE */ + 0 +}}}, +{{{ /* MIPS_ARITH_FENCE (24) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_STACKMAP (25) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FENTRY_CALL (26) - MIPS_INS_INVALID - # FEntry call */ + 0 +}}}, +{{{ /* MIPS_PATCHPOINT (27) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LOAD_STACK_GUARD (28) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PREALLOCATED_SETUP (29) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PREALLOCATED_ARG (30) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_STATEPOINT (31) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LOCAL_ESCAPE (32) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FAULTING_OP (33) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_OP (34) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_FUNCTION_ENTER (35) - MIPS_INS_INVALID - # XRay Function Enter. */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_RET (36) - MIPS_INS_INVALID - # XRay Function Patchable RET. */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_FUNCTION_EXIT (37) - MIPS_INS_INVALID - # XRay Function Exit. */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_TAIL_CALL (38) - MIPS_INS_INVALID - # XRay Tail Call Exit. */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_EVENT_CALL (39) - MIPS_INS_INVALID - # XRay Custom Event Log. */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_TYPED_EVENT_CALL (40) - MIPS_INS_INVALID - # XRay Typed Event Log. */ + 0 +}}}, +{{{ /* MIPS_ICALL_BRANCH_FUNNEL (41) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MEMBARRIER (42) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JUMP_TABLE_DEBUG_INFO (43) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ASSERT_SEXT (44) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ASSERT_ZEXT (45) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ASSERT_ALIGN (46) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ADD (47) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SUB (48) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_MUL (49) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SDIV (50) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UDIV (51) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SREM (52) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UREM (53) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SDIVREM (54) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UDIVREM (55) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_AND (56) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_OR (57) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_XOR (58) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_IMPLICIT_DEF (59) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_PHI (60) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FRAME_INDEX (61) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_GLOBAL_VALUE (62) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CONSTANT_POOL (63) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_EXTRACT (64) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UNMERGE_VALUES (65) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INSERT (66) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_MERGE_VALUES (67) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BUILD_VECTOR (68) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BUILD_VECTOR_TRUNC (69) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CONCAT_VECTORS (70) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_PTRTOINT (71) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTTOPTR (72) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BITCAST (73) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FREEZE (74) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CONSTANT_FOLD_BARRIER (75) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_FPTRUNC_ROUND (76) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_TRUNC (77) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_ROUND (78) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_LRINT (79) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_ROUNDEVEN (80) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_READCYCLECOUNTER (81) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_LOAD (82) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SEXTLOAD (83) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ZEXTLOAD (84) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INDEXED_LOAD (85) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INDEXED_SEXTLOAD (86) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INDEXED_ZEXTLOAD (87) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STORE (88) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INDEXED_STORE (89) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMIC_CMPXCHG_WITH_SUCCESS (90) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMIC_CMPXCHG (91) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_XCHG (92) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_ADD (93) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_SUB (94) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_AND (95) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_NAND (96) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_OR (97) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_XOR (98) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_MAX (99) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_MIN (100) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_UMAX (101) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_UMIN (102) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_FADD (103) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_FSUB (104) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_FMAX (105) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_FMIN (106) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_UINC_WRAP (107) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_UDEC_WRAP (108) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FENCE (109) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_PREFETCH (110) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BRCOND (111) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BRINDIRECT (112) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INVOKE_REGION_START (113) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC (114) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_W_SIDE_EFFECTS (115) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_CONVERGENT (116) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS (117) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ANYEXT (118) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_TRUNC (119) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CONSTANT (120) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FCONSTANT (121) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VASTART (122) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VAARG (123) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SEXT (124) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SEXT_INREG (125) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ZEXT (126) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SHL (127) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_LSHR (128) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ASHR (129) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FSHL (130) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FSHR (131) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ROTR (132) - MIPS_INS_INVALID - */ + 0 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MIPS_G_UADDSAT (149) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SADDSAT (150) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_USUBSAT (151) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SSUBSAT (152) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_USHLSAT (153) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SSHLSAT (154) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SMULFIX (155) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UMULFIX (156) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SMULFIXSAT (157) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UMULFIXSAT (158) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SDIVFIX (159) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UDIVFIX (160) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SDIVFIXSAT (161) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UDIVFIXSAT (162) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FADD (163) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FSUB (164) - MIPS_INS_INVALID - */ + 0 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(181) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FPTRUNC (182) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FPTOSI (183) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FPTOUI (184) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SITOFP (185) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UITOFP (186) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FABS (187) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FCOPYSIGN (188) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_IS_FPCLASS (189) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FCANONICALIZE (190) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMINNUM (191) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMAXNUM (192) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMINNUM_IEEE (193) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMAXNUM_IEEE (194) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMINIMUM (195) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMAXIMUM (196) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_GET_FPENV (197) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SET_FPENV (198) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_RESET_FPENV (199) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_GET_FPMODE (200) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SET_FPMODE (201) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_RESET_FPMODE (202) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_PTR_ADD (203) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_PTRMASK (204) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SMIN (205) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SMAX (206) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UMIN (207) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UMAX (208) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ABS (209) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_LROUND (210) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_LLROUND (211) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BR (212) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BRJT (213) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INSERT_VECTOR_ELT (214) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_EXTRACT_VECTOR_ELT (215) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SHUFFLE_VECTOR (216) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CTTZ (217) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CTTZ_ZERO_UNDEF (218) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CTLZ (219) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CTLZ_ZERO_UNDEF (220) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CTPOP (221) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BSWAP (222) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BITREVERSE (223) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FCEIL (224) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FCOS (225) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FSIN (226) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FSQRT (227) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FFLOOR (228) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FRINT (229) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FNEARBYINT (230) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ADDRSPACE_CAST (231) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BLOCK_ADDR (232) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_JUMP_TABLE (233) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_DYN_STACKALLOC (234) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STACKSAVE (235) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STACKRESTORE (236) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FADD (237) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FSUB (238) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FMUL (239) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FDIV (240) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FREM (241) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FMA (242) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FSQRT (243) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FLDEXP (244) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_READ_REGISTER (245) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_WRITE_REGISTER (246) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_MEMCPY (247) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_MEMCPY_INLINE (248) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_MEMMOVE (249) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_MEMSET (250) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BZERO (251) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_SEQ_FADD (252) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_SEQ_FMUL (253) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_FADD (254) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_FMUL (255) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_FMAX (256) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_FMIN (257) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_FMAXIMUM (258) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_FMINIMUM (259) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_ADD (260) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_MUL (261) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_AND (262) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_OR (263) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_XOR (264) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_SMAX (265) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_SMIN (266) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_UMAX (267) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_UMIN (268) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SBFX (269) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UBFX (270) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_ABSMacro (271) - MIPS_INS_ABS - abs $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{{{ /* MIPS_ADJCALLSTACKDOWN (272) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ADJCALLSTACKDOWN_NM (273) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ADJCALLSTACKUP (274) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ADJCALLSTACKUP_NM (275) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_ALIGN_NM (276) - MIPS_INS_ALIGN - align $rd, $rs, $rt, $bp */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bp */ + { 0 } +}}, +{{{ /* MIPS_AND_V_D_PSEUDO (277) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_AND_V_H_PSEUDO (278) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_AND_V_W_PSEUDO (279) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I16 (280) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I16_POSTRA (281) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I32 (282) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I32_POSTRA (283) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I64 (284) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I64_POSTRA (285) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I8 (286) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I8_POSTRA (287) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I16 (288) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I16_POSTRA (289) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I32 (290) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I32_POSTRA (291) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I64 (292) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I64_POSTRA (293) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I8 (294) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I8_POSTRA (295) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I16 (296) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I16_POSTRA (297) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I32 (298) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I32_POSTRA (299) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I64 (300) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I64_POSTRA (301) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I8 (302) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I8_POSTRA (303) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I16 (304) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I16_POSTRA (305) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I32 (306) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I32_POSTRA (307) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I64 (308) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I64_POSTRA (309) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I8 (310) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I8_POSTRA (311) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I16 (312) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I16_POSTRA (313) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I32 (314) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I32_POSTRA (315) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I64 (316) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I64_POSTRA (317) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I8 (318) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I8_POSTRA (319) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I16 (320) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I16_POSTRA (321) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I32 (322) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I32_POSTRA (323) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I64 (324) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I64_POSTRA (325) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I8 (326) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I8_POSTRA (327) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I16 (328) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I16_POSTRA (329) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I32 (330) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I32_POSTRA (331) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I64 (332) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I64_POSTRA (333) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I8 (334) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I8_POSTRA (335) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I16 (336) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I16_POSTRA (337) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I32 (338) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I32_POSTRA (339) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I64 (340) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I64_POSTRA (341) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I8 (342) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I8_POSTRA (343) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I16 (344) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I16_POSTRA (345) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I32 (346) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I32_POSTRA (347) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I64 (348) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I64_POSTRA (349) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I8 (350) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I8_POSTRA (351) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I16 (352) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I16_POSTRA (353) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I32 (354) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I32_POSTRA (355) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I64 (356) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I64_POSTRA (357) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I8 (358) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I8_POSTRA (359) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I16 (360) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I16_POSTRA (361) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I32 (362) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I32_POSTRA (363) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I64 (364) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I64_POSTRA (365) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I8 (366) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I8_POSTRA (367) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I16 (368) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I16_POSTRA (369) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I32 (370) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I32_POSTRA (371) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I64 (372) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I64_POSTRA (373) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I8 (374) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I8_POSTRA (375) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_B (376) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BAL_BR (377) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BAL_BR_MM (378) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_BEQLImmMacro (379) - MIPS_INS_BEQL - beql $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGE (380) - MIPS_INS_BGE - bge $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEImmMacro (381) - MIPS_INS_BGE - bge $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEL (382) - MIPS_INS_BGEL - bgel $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGELImmMacro (383) - MIPS_INS_BGEL - bgel $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEU (384) - MIPS_INS_BGEU - bgeu $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEUImmMacro (385) - MIPS_INS_BGEU - bgeu $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEUL (386) - MIPS_INS_BGEUL - bgeul $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEULImmMacro (387) - MIPS_INS_BGEUL - bgeul $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGT (388) - MIPS_INS_BGT - bgt $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTImmMacro (389) - MIPS_INS_BGT - bgt $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTL (390) - MIPS_INS_BGTL - bgtl $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTLImmMacro (391) - MIPS_INS_BGTL - bgtl $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTU (392) - MIPS_INS_BGTU - bgtu $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTUImmMacro (393) - MIPS_INS_BGTU - bgtu $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTUL (394) - MIPS_INS_BGTUL - bgtul $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTULImmMacro (395) - MIPS_INS_BGTUL - bgtul $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLE (396) - MIPS_INS_BLE - ble $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEImmMacro (397) - MIPS_INS_BLE - ble $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEL (398) - MIPS_INS_BLEL - blel $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLELImmMacro (399) - MIPS_INS_BLEL - blel $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEU (400) - MIPS_INS_BLEU - bleu $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEUImmMacro (401) - MIPS_INS_BLEU - bleu $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEUL (402) - MIPS_INS_BLEUL - bleul $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEULImmMacro (403) - MIPS_INS_BLEUL - bleul $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLT (404) - MIPS_INS_BLT - blt $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTImmMacro (405) - MIPS_INS_BLT - blt $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTL (406) - MIPS_INS_BLTL - bltl $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTLImmMacro (407) - MIPS_INS_BLTL - bltl $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTU (408) - MIPS_INS_BLTU - bltu $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTUImmMacro (409) - MIPS_INS_BLTU - bltu $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTUL (410) - MIPS_INS_BLTUL - bltul $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTULImmMacro (411) - MIPS_INS_BLTUL - bltul $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNELImmMacro (412) - MIPS_INS_BNEL - bnel $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BPOSGE32_PSEUDO (413) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BSEL_D_PSEUDO (414) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BSEL_FD_PSEUDO (415) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BSEL_FW_PSEUDO (416) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BSEL_H_PSEUDO (417) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BSEL_W_PSEUDO (418) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_B_MM (419) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_B_MMR6_Pseudo (420) - MIPS_INS_B - b $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_B_MM_Pseudo (421) - MIPS_INS_B - b $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BeqImm (422) - MIPS_INS_BEQ - beq $rt, $imm64, $offset */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BneImm (423) - MIPS_INS_BNE - bne $rt, $imm64, $offset */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BteqzT8CmpX16 (424) - MIPS_INS_INVALID - cmp $rx, $ry + bteqz $imm */ + 0 +}}}, +{{{ /* MIPS_BteqzT8CmpiX16 (425) - MIPS_INS_INVALID - cmpi $rx, $imm + bteqz $targ */ + 0 +}}}, +{{{ /* MIPS_BteqzT8SltX16 (426) - MIPS_INS_INVALID - slt $rx, $ry + bteqz $imm */ + 0 +}}}, +{{{ /* MIPS_BteqzT8SltiX16 (427) - MIPS_INS_INVALID - slti $rx, $imm + bteqz $targ */ + 0 +}}}, +{{{ /* MIPS_BteqzT8SltiuX16 (428) - MIPS_INS_INVALID - sltiu $rx, $imm + bteqz $targ */ + 0 +}}}, +{{{ /* MIPS_BteqzT8SltuX16 (429) - MIPS_INS_INVALID - sltu $rx, $ry + bteqz $imm */ + 0 +}}}, +{{{ /* MIPS_BtnezT8CmpX16 (430) - MIPS_INS_INVALID - cmp $rx, $ry + btnez $imm */ + 0 +}}}, +{{{ /* MIPS_BtnezT8CmpiX16 (431) - MIPS_INS_INVALID - cmpi $rx, $imm + btnez $targ */ + 0 +}}}, +{{{ /* MIPS_BtnezT8SltX16 (432) - MIPS_INS_INVALID - slt $rx, $ry + btnez $imm */ + 0 +}}}, +{{{ /* MIPS_BtnezT8SltiX16 (433) - MIPS_INS_INVALID - slti $rx, $imm + btnez $targ */ + 0 +}}}, +{{{ /* MIPS_BtnezT8SltiuX16 (434) - MIPS_INS_INVALID - sltiu $rx, $imm + btnez $targ */ + 0 +}}}, +{{{ /* MIPS_BtnezT8SltuX16 (435) - MIPS_INS_INVALID - sltu $rx, $ry + btnez $imm */ + 0 +}}}, +{{{ /* MIPS_BuildPairF64 (436) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BuildPairF64_64 (437) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_CFTC1 (438) - MIPS_INS_CFTC1 - cftc1 $rt, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{{{ /* MIPS_CONSTPOOL_ENTRY (439) - MIPS_INS_INVALID - foo */ + 0 +}}}, +{{{ /* MIPS_COPY_FD_PSEUDO (440) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_COPY_FW_PSEUDO (441) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_CTTC1 (442) - MIPS_INS_CTTC1 - cttc1 $rt, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_Constant32 (443) - MIPS_INS_INVALID - .word $imm */ + 0 +}}}, +{ /* MIPS_DMULImmMacro (444) - MIPS_INS_DMUL - dmul $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DMULMacro (445) - MIPS_INS_DMUL - dmul $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_DMULOMacro (446) - MIPS_INS_DMULO - dmulo $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_DMULOUMacro (447) - MIPS_INS_DMULOU - dmulou $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_DROL (448) - MIPS_INS_DROL - drol $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_DROLImm (449) - MIPS_INS_DROL - drol $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DROR (450) - MIPS_INS_DROR - dror $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_DRORImm (451) - MIPS_INS_DROR - dror $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DSDivIMacro (452) - MIPS_INS_DDIV - ddiv $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DSDivMacro (453) - MIPS_INS_DDIV - ddiv $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DSRemIMacro (454) - MIPS_INS_DREM - drem $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DSRemMacro (455) - MIPS_INS_DREM - drem $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DUDivIMacro (456) - MIPS_INS_DDIVU - ddivu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DUDivMacro (457) - MIPS_INS_DDIVU - ddivu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DURemIMacro (458) - MIPS_INS_DREMU - dremu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DURemMacro (459) - MIPS_INS_DREMU - dremu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_ERet (460) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ExtractElementF64 (461) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ExtractElementF64_64 (462) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FABS_D (463) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FABS_W (464) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FEXP2_D_1_PSEUDO (465) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FEXP2_W_1_PSEUDO (466) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FILL_FD_PSEUDO (467) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FILL_FW_PSEUDO (468) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_GotPrologue16 (469) - MIPS_INS_INVALID - li $rh, $immHi + addiu $rl, $$pc, $immLo + */ + 0 +}}}, +{{{ /* MIPS_INSERT_B_VIDX64_PSEUDO (470) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_B_VIDX_PSEUDO (471) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_D_VIDX64_PSEUDO (472) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_D_VIDX_PSEUDO (473) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_FD_PSEUDO (474) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_FD_VIDX64_PSEUDO (475) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_FD_VIDX_PSEUDO (476) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_FW_PSEUDO (477) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_FW_VIDX64_PSEUDO (478) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_FW_VIDX_PSEUDO (479) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_H_VIDX64_PSEUDO (480) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_H_VIDX_PSEUDO (481) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_W_VIDX64_PSEUDO (482) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_W_VIDX_PSEUDO (483) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JALR64Pseudo (484) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JALRCPseudo (485) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JALRHB64Pseudo (486) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JALRHBPseudo (487) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JALRPseudo (488) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JAL_MMR6 (489) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_JalOneReg (490) - MIPS_INS_JAL - jal $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JalTwoReg (491) - MIPS_INS_JAL - jal $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_LDMacro (492) - MIPS_INS_LD - ld $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LDR_D (493) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LDR_W (494) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LD_F16 (495) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LOAD_ACC128 (496) - MIPS_INS_INVALID - $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LOAD_ACC64 (497) - MIPS_INS_INVALID - $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LOAD_ACC64DSP (498) - MIPS_INS_INVALID - $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LOAD_CCOND_DSP (499) - MIPS_INS_INVALID - load_ccond_dsp $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_ADDiu (500) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_ADDiu2Op (501) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_DADDiu (502) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_DADDiu2Op (503) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_LUi (504) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_LUi2Op (505) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_LUi2Op_64 (506) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_LWM_MM (507) - MIPS_INS_LWM - lwm $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_LoadAddrImm32 (508) - MIPS_INS_LA - la $rt, $imm32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm32 */ + { 0 } +}}, +{ /* MIPS_LoadAddrImm64 (509) - MIPS_INS_DLA - dla $rt, $imm64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm64 */ + { 0 } +}}, +{ /* MIPS_LoadAddrReg32 (510) - MIPS_INS_LA - la $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LoadAddrReg64 (511) - MIPS_INS_DLA - dla $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LoadImm32 (512) - MIPS_INS_LI - li $rt, $imm32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm32 */ + { 0 } +}}, +{ /* MIPS_LoadImm64 (513) - MIPS_INS_DLI - dli $rt, $imm64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm64 */ + { 0 } +}}, +{ /* MIPS_LoadImmDoubleFGR (514) - MIPS_INS_LI_D - li.d $rd, $fpimm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* fpimm */ + { 0 } +}}, +{ /* MIPS_LoadImmDoubleFGR_32 (515) - MIPS_INS_LI_D - li.d $rd, $fpimm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* fpimm */ + { 0 } +}}, +{ /* MIPS_LoadImmDoubleGPR (516) - MIPS_INS_LI_D - li.d $rd, $fpimm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* fpimm */ + { 0 } +}}, +{ /* MIPS_LoadImmSingleFGR (517) - MIPS_INS_LI_S - li.s $rd, $fpimm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* fpimm */ + { 0 } +}}, +{ /* MIPS_LoadImmSingleGPR (518) - MIPS_INS_LI_S - li.s $rd, $fpimm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* fpimm */ + { 0 } +}}, +{{{ /* MIPS_LoadJumpTableOffset (519) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LwConstant32 (520) - MIPS_INS_INVALID - lw $rx, 1f + b 2f + .align 2 +1: .word $imm +2: */ + 0 +}}}, +{ /* MIPS_MFTACX (521) - MIPS_INS_MFTACX - mftacx $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFTACX_NM (522) - MIPS_INS_MFTACX - mftacx $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFTC0 (523) - MIPS_INS_MFTC0 - mftc0 $rd, $rt, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFTC0_NM (524) - MIPS_INS_MFTC0 - mftc0 $rd, $rt, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFTC1 (525) - MIPS_INS_MFTC1 - mftc1 $rt, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MFTDSP (526) - MIPS_INS_MFTDSP - mftdsp $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MFTDSP_NM (527) - MIPS_INS_MFTDSP - mftdsp $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MFTGPR (528) - MIPS_INS_MFTGPR - mftgpr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFTGPR_NM (529) - MIPS_INS_MFTGPR - mftgpr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFTHC1 (530) - MIPS_INS_MFTHC1 - mfthc1 $rt, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MFTHI (531) - MIPS_INS_MFTHI - mfthi $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFTHI_NM (532) - MIPS_INS_MFTHI - mfthi $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFTLO (533) - MIPS_INS_MFTLO - mftlo $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFTLO_NM (534) - MIPS_INS_MFTLO - mftlo $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{{{ /* MIPS_MIPSeh_return32 (535) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MIPSeh_return64 (536) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MSA_FP_EXTEND_D_PSEUDO (537) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MSA_FP_EXTEND_W_PSEUDO (538) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MSA_FP_ROUND_D_PSEUDO (539) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MSA_FP_ROUND_W_PSEUDO (540) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_MTTACX (541) - MIPS_INS_MTTACX - mttacx $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTACX_NM (542) - MIPS_INS_MTTACX - mttacx $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTC0 (543) - MIPS_INS_MTTC0 - mttc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTTC0_NM (544) - MIPS_INS_MTTC0 - mttc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTTC1 (545) - MIPS_INS_MTTC1 - mttc1 $rt, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTDSP (546) - MIPS_INS_MTTDSP - mttdsp $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTDSP_NM (547) - MIPS_INS_MTTDSP - mttdsp $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTGPR (548) - MIPS_INS_MTTGPR - mttgpr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_MTTGPR_NM (549) - MIPS_INS_MTTGPR - mttgpr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_MTTHC1 (550) - MIPS_INS_MTTHC1 - mtthc1 $rt, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTHI (551) - MIPS_INS_MTTHI - mtthi $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTHI_NM (552) - MIPS_INS_MTTHI - mtthi $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTLO (553) - MIPS_INS_MTTLO - mttlo $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTLO_NM (554) - MIPS_INS_MTTLO - mttlo $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULImmMacro (555) - MIPS_INS_MUL - mul $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MULOMacro (556) - MIPS_INS_MULO - mulo $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULOUMacro (557) - MIPS_INS_MULOU - mulou $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_MUSTTAILCALLREG_NM (558) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MUSTTAILCALL_NM (559) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MultRxRy16 (560) - MIPS_INS_INVALID - mult $rx, $ry */ + 0 +}}}, +{{{ /* MIPS_MultRxRyRz16 (561) - MIPS_INS_INVALID - mult $rx, $ry + mflo $rz */ + 0 +}}}, +{{{ /* MIPS_MultuRxRy16 (562) - MIPS_INS_INVALID - multu $rx, $ry */ + 0 +}}}, +{{{ /* MIPS_MultuRxRyRz16 (563) - MIPS_INS_INVALID - multu $rx, $ry + mflo $rz */ + 0 +}}}, +{{{ /* MIPS_NOP (564) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_NORImm (565) - MIPS_INS_NOR - nor $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_NORImm64 (566) - MIPS_INS_NOR - nor $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{{{ /* MIPS_NOR_V_D_PSEUDO (567) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_NOR_V_H_PSEUDO (568) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_NOR_V_W_PSEUDO (569) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_OR_V_D_PSEUDO (570) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_OR_V_H_PSEUDO (571) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_OR_V_W_PSEUDO (572) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_PseudoADDIU_NM (573) - MIPS_INS_ADDIU - addiu $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_PseudoANDI_NM (574) - MIPS_INS_ANDI - andi $rt, $rs, $mask */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { 0 } +}}, +{{{ /* MIPS_PseudoCMPU_EQ_QB (575) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoCMPU_LE_QB (576) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoCMPU_LT_QB (577) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoCMP_EQ_PH (578) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoCMP_LE_PH (579) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoCMP_LT_PH (580) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoCVT_D32_W (581) - MIPS_INS_INVALID - $fd, $fs */ + 0 +}}}, +{{{ /* MIPS_PseudoCVT_D64_L (582) - MIPS_INS_INVALID - $fd, $fs */ + 0 +}}}, +{{{ /* MIPS_PseudoCVT_D64_W (583) - MIPS_INS_INVALID - $fd, $fs */ + 0 +}}}, +{{{ /* MIPS_PseudoCVT_S_L (584) - MIPS_INS_INVALID - $fd, $fs */ + 0 +}}}, +{{{ /* MIPS_PseudoCVT_S_W (585) - MIPS_INS_INVALID - $fd, $fs */ + 0 +}}}, +{{{ /* MIPS_PseudoDMULT (586) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoDMULTu (587) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoDSDIV (588) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoDUDIV (589) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoD_SELECT_I (590) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoD_SELECT_I64 (591) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranch (592) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranch64 (593) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranch64R6 (594) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranchNM (595) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranchR6 (596) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranch_MM (597) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranch_MMR6 (598) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectHazardBranch (599) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectHazardBranch64 (600) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndrectHazardBranch64R6 (601) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndrectHazardBranchR6 (602) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_PseudoLA_NM (603) - MIPS_INS_LA - la $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_PseudoLI_NM (604) - MIPS_INS_LI - li $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{{{ /* MIPS_PseudoMADD (605) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMADDU (606) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMADDU_MM (607) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMADD_MM (608) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMFHI (609) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMFHI64 (610) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMFHI_MM (611) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMFLO (612) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMFLO64 (613) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMFLO_MM (614) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMSUB (615) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMSUBU (616) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMSUBU_MM (617) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMSUB_MM (618) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMTLOHI (619) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMTLOHI64 (620) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMTLOHI_DSP (621) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMTLOHI_MM (622) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMULT (623) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMULT_MM (624) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMULTu (625) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMULTu_MM (626) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoPICK_PH (627) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoPICK_QB (628) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoReturn (629) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoReturn64 (630) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoReturnNM (631) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSDIV (632) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_F_D32 (633) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_F_D64 (634) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_F_I (635) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_F_I64 (636) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_F_S (637) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_T_D32 (638) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_T_D64 (639) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_T_I (640) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_T_I64 (641) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_T_S (642) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECT_D32 (643) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECT_D64 (644) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECT_I (645) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECT_I64 (646) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECT_S (647) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_PseudoSUBU_NM (648) - MIPS_INS_SUBU - subu $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_PseudoTRUNC_W_D (649) - MIPS_INS_TRUNC_W_D - trunc.w.d $fd, $fs, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PseudoTRUNC_W_D32 (650) - MIPS_INS_TRUNC_W_D - trunc.w.d $fd, $fs, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PseudoTRUNC_W_S (651) - MIPS_INS_TRUNC_W_S - trunc.w.s $fd, $fs, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{{{ /* MIPS_PseudoUDIV (652) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_ROL (653) - MIPS_INS_ROL - rol $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_ROLImm (654) - MIPS_INS_ROL - rol $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ROR (655) - MIPS_INS_ROR - ror $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_RORImm (656) - MIPS_INS_ROR - ror $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{{{ /* MIPS_RetRA (657) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_RetRA16 (658) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SDC1_M1 (659) - MIPS_INS_S_D - s.d $fd, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SDIV_MM_Pseudo (660) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SDMacro (661) - MIPS_INS_SD - sd $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDivIMacro (662) - MIPS_INS_DIV - div $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SDivMacro (663) - MIPS_INS_DIV - div $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SEQIMacro (664) - MIPS_INS_SEQ - seq $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SEQMacro (665) - MIPS_INS_SEQ - seq $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SGE (666) - MIPS_INS_SGE - sge $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SGEImm (667) - MIPS_INS_SGE - sge $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGEImm64 (668) - MIPS_INS_SGE - sge $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGEU (669) - MIPS_INS_SGEU - sgeu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SGEUImm (670) - MIPS_INS_SGEU - sgeu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGEUImm64 (671) - MIPS_INS_SGEU - sgeu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGTImm (672) - MIPS_INS_SGT - sgt $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGTImm64 (673) - MIPS_INS_SGT - sgt $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGTUImm (674) - MIPS_INS_SGTU - sgtu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGTUImm64 (675) - MIPS_INS_SGTU - sgtu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLE (676) - MIPS_INS_SLE - sle $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLEImm (677) - MIPS_INS_SLE - sle $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLEImm64 (678) - MIPS_INS_SLE - sle $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLEU (679) - MIPS_INS_SLEU - sleu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLEUImm (680) - MIPS_INS_SLEU - sleu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLEUImm64 (681) - MIPS_INS_SLEU - sleu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLTImm64 (682) - MIPS_INS_SLT - slt $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLTUImm64 (683) - MIPS_INS_SLTU - sltu $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SNEIMacro (684) - MIPS_INS_SNE - sne $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SNEMacro (685) - MIPS_INS_SNE - sne $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_SNZ_B_PSEUDO (686) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SNZ_D_PSEUDO (687) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SNZ_H_PSEUDO (688) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SNZ_V_PSEUDO (689) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SNZ_W_PSEUDO (690) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SRemIMacro (691) - MIPS_INS_REM - rem $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SRemMacro (692) - MIPS_INS_REM - rem $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_STORE_ACC128 (693) - MIPS_INS_INVALID - $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_STORE_ACC64 (694) - MIPS_INS_INVALID - $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_STORE_ACC64DSP (695) - MIPS_INS_INVALID - $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_STORE_CCOND_DSP (696) - MIPS_INS_INVALID - store_ccond_dsp $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_STR_D (697) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_STR_W (698) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ST_F16 (699) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SWM_MM (700) - MIPS_INS_SWM - swm $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{{{ /* MIPS_SZ_B_PSEUDO (701) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SZ_D_PSEUDO (702) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SZ_H_PSEUDO (703) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SZ_V_PSEUDO (704) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SZ_W_PSEUDO (705) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SaaAddr (706) - MIPS_INS_SAA - saa $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SaadAddr (707) - MIPS_INS_SAAD - saad $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SelBeqZ (708) - MIPS_INS_INVALID - beqz $rt, .+4 + + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelBneZ (709) - MIPS_INS_INVALID - bnez $rt, .+4 + + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBteqZCmp (710) - MIPS_INS_INVALID - cmp $rl, $rr + bteqz .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBteqZCmpi (711) - MIPS_INS_INVALID - cmpi $rl, $imm + bteqz .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBteqZSlt (712) - MIPS_INS_INVALID - slt $rl, $rr + bteqz .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBteqZSlti (713) - MIPS_INS_INVALID - slti $rl, $imm + bteqz .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBteqZSltiu (714) - MIPS_INS_INVALID - sltiu $rl, $imm + bteqz .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBteqZSltu (715) - MIPS_INS_INVALID - sltu $rl, $rr + bteqz .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBtneZCmp (716) - MIPS_INS_INVALID - cmp $rl, $rr + btnez .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBtneZCmpi (717) - MIPS_INS_INVALID - cmpi $rl, $imm + btnez .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBtneZSlt (718) - MIPS_INS_INVALID - slt $rl, $rr + btnez .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBtneZSlti (719) - MIPS_INS_INVALID - slti $rl, $imm + btnez .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBtneZSltiu (720) - MIPS_INS_INVALID - sltiu $rl, $imm + btnez .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBtneZSltu (721) - MIPS_INS_INVALID - sltu $rl, $rr + btnez .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SltCCRxRy16 (722) - MIPS_INS_INVALID - slt $rx, $ry + move $cc, $$t8 */ + 0 +}}}, +{{{ /* MIPS_SltiCCRxImmX16 (723) - MIPS_INS_INVALID - slti $rx, $imm + move $cc, $$t8 */ + 0 +}}}, +{{{ /* MIPS_SltiuCCRxImmX16 (724) - MIPS_INS_INVALID - sltiu $rx, $imm + move $cc, $$t8 */ + 0 +}}}, +{{{ /* MIPS_SltuCCRxRy16 (725) - MIPS_INS_INVALID - sltu $rx, $ry + move $cc, $$t8 */ + 0 +}}}, +{{{ /* MIPS_SltuRxRyRz16 (726) - MIPS_INS_INVALID - sltu $rx, $ry + move $rz, $$t8 */ + 0 +}}}, +{{{ /* MIPS_TAILCALL (727) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALL64R6REG (728) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLHB64R6REG (729) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLHBR6REG (730) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLR6REG (731) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREG (732) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREG64 (733) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREGHB (734) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREGHB64 (735) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREG_MM (736) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREG_MMR6 (737) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREG_NM (738) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALL_MM (739) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALL_MMR6 (740) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALL_NM (741) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TRAP (742) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TRAP_MM (743) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_UDIV_MM_Pseudo (744) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_UDivIMacro (745) - MIPS_INS_DIVU - divu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_UDivMacro (746) - MIPS_INS_DIVU - divu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_URemIMacro (747) - MIPS_INS_REMU - remu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_URemMacro (748) - MIPS_INS_REMU - remu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_Ulh (749) - MIPS_INS_ULH - ulh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_Ulhu (750) - MIPS_INS_ULHU - ulhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_Ulw (751) - MIPS_INS_ULW - ulw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_Ush (752) - MIPS_INS_USH - ush $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_Usw (753) - MIPS_INS_USW - usw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_XOR_V_D_PSEUDO (754) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_XOR_V_H_PSEUDO (755) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_XOR_V_W_PSEUDO (756) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_ABSQ_S_PH (757) - MIPS_INS_ABSQ_S_PH - absq_s.ph $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ABSQ_S_PH_MM (758) - MIPS_INS_ABSQ_S_PH - absq_s.ph $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_ABSQ_S_QB (759) - MIPS_INS_ABSQ_S_QB - absq_s.qb $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ABSQ_S_QB_MMR2 (760) - MIPS_INS_ABSQ_S_QB - absq_s.qb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_ABSQ_S_W (761) - MIPS_INS_ABSQ_S_W - absq_s.w $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ABSQ_S_W_MM (762) - MIPS_INS_ABSQ_S_W - absq_s.w $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_ADD (763) - MIPS_INS_ADD - add $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDIU48_NM (764) - MIPS_INS_ADDIU - addiu[48] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUGP48_NM (765) - MIPS_INS_ADDIU - addiu[gp48] $rt, $rs, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_ADDIUGPB_NM (766) - MIPS_INS_ADDIU - addiu[gp.b] $rt, $rs, $offset */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_ADDIUGPW_NM (767) - MIPS_INS_ADDIU - addiu[gp.w] $rt, $rs, $offset */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_ADDIUNEG_NM (768) - MIPS_INS_ADDIU - addiu[neg] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUPC (769) - MIPS_INS_ADDIUPC - addiupc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUPC_MM (770) - MIPS_INS_ADDIUPC - addiupc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUPC_MMR6 (771) - MIPS_INS_ADDIUPC - addiupc $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUR1SP_MM (772) - MIPS_INS_ADDIUR1SP - addiur1sp $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUR1SP_NM (773) - MIPS_INS_ADDIU - addiu[r1.sp] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUR2_MM (774) - MIPS_INS_ADDIUR2 - addiur2 $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUR2_NM (775) - MIPS_INS_ADDIU - addiu[r2] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIURS5_NM (776) - MIPS_INS_ADDIU - addiu[rs5] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUS5_MM (777) - MIPS_INS_ADDIUS5 - addius5 $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUSP_MM (778) - MIPS_INS_ADDIUSP - addiusp $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIU_MMR6 (779) - MIPS_INS_ADDIU - addiu $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ADDIU_NM (780) - MIPS_INS_ADDIU - addiu[32] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDQH_PH (781) - MIPS_INS_ADDQH_PH - addqh.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_PH_MMR2 (782) - MIPS_INS_ADDQH_PH - addqh.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_R_PH (783) - MIPS_INS_ADDQH_R_PH - addqh_r.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_R_PH_MMR2 (784) - MIPS_INS_ADDQH_R_PH - addqh_r.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_R_W (785) - MIPS_INS_ADDQH_R_W - addqh_r.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_R_W_MMR2 (786) - MIPS_INS_ADDQH_R_W - addqh_r.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_W (787) - MIPS_INS_ADDQH_W - addqh.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_W_MMR2 (788) - MIPS_INS_ADDQH_W - addqh.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQ_PH (789) - MIPS_INS_ADDQ_PH - addq.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQ_PH_MM (790) - MIPS_INS_ADDQ_PH - addq.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQ_S_PH (791) - MIPS_INS_ADDQ_S_PH - addq_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQ_S_PH_MM (792) - MIPS_INS_ADDQ_S_PH - addq_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQ_S_W (793) - MIPS_INS_ADDQ_S_W - addq_s.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQ_S_W_MM (794) - MIPS_INS_ADDQ_S_W - addq_s.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDR_PS64 (795) - MIPS_INS_ADDR_PS - addr.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_ADDSC (796) - MIPS_INS_ADDSC - addsc $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDSC_MM (797) - MIPS_INS_ADDSC - addsc $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDS_A_B (798) - MIPS_INS_ADDS_A_B - adds_a.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_A_D (799) - MIPS_INS_ADDS_A_D - adds_a.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_A_H (800) - MIPS_INS_ADDS_A_H - adds_a.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_A_W (801) - MIPS_INS_ADDS_A_W - adds_a.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_S_B (802) - MIPS_INS_ADDS_S_B - adds_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_S_D (803) - MIPS_INS_ADDS_S_D - adds_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_S_H (804) - MIPS_INS_ADDS_S_H - adds_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_S_W (805) - MIPS_INS_ADDS_S_W - adds_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_U_B (806) - MIPS_INS_ADDS_U_B - adds_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_U_D (807) - MIPS_INS_ADDS_U_D - adds_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_U_H (808) - MIPS_INS_ADDS_U_H - adds_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_U_W (809) - MIPS_INS_ADDS_U_W - adds_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDU16_MM (810) - MIPS_INS_ADDU16 - addu16 $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU16_MMR6 (811) - MIPS_INS_ADDU16 - addu16 $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDUH_QB (812) - MIPS_INS_ADDUH_QB - adduh.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDUH_QB_MMR2 (813) - MIPS_INS_ADDUH_QB - adduh.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDUH_R_QB (814) - MIPS_INS_ADDUH_R_QB - adduh_r.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDUH_R_QB_MMR2 (815) - MIPS_INS_ADDUH_R_QB - adduh_r.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_MMR6 (816) - MIPS_INS_ADDU - addu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_PH (817) - MIPS_INS_ADDU_PH - addu.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_PH_MMR2 (818) - MIPS_INS_ADDU_PH - addu.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_QB (819) - MIPS_INS_ADDU_QB - addu.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_QB_MM (820) - MIPS_INS_ADDU_QB - addu.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_S_PH (821) - MIPS_INS_ADDU_S_PH - addu_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_S_PH_MMR2 (822) - MIPS_INS_ADDU_S_PH - addu_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_S_QB (823) - MIPS_INS_ADDU_S_QB - addu_s.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_S_QB_MM (824) - MIPS_INS_ADDU_S_QB - addu_s.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDVI_B (825) - MIPS_INS_ADDVI_B - addvi.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDVI_D (826) - MIPS_INS_ADDVI_D - addvi.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDVI_H (827) - MIPS_INS_ADDVI_H - addvi.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDVI_W (828) - MIPS_INS_ADDVI_W - addvi.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDV_B (829) - MIPS_INS_ADDV_B - addv.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDV_D (830) - MIPS_INS_ADDV_D - addv.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDV_H (831) - MIPS_INS_ADDV_H - addv.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDV_W (832) - MIPS_INS_ADDV_W - addv.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDWC (833) - MIPS_INS_ADDWC - addwc $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDWC_MM (834) - MIPS_INS_ADDWC - addwc $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADD_A_B (835) - MIPS_INS_ADD_A_B - add_a.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADD_A_D (836) - MIPS_INS_ADD_A_D - add_a.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADD_A_H (837) - MIPS_INS_ADD_A_H - add_a.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADD_A_W (838) - MIPS_INS_ADD_A_W - add_a.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADD_MM (839) - MIPS_INS_ADD - add $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADD_MMR6 (840) - MIPS_INS_ADD - add $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADD_NM (841) - MIPS_INS_ADD - add $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDi (842) - MIPS_INS_ADDI - addi $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ADDi_MM (843) - MIPS_INS_ADDI - addi $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ADDiu (844) - MIPS_INS_ADDIU - addiu $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ADDiu_MM (845) - MIPS_INS_ADDIU - addiu $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ADDu (846) - MIPS_INS_ADDU - addu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDu16_NM (847) - MIPS_INS_ADDU - addu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDu4x4_NM (848) - MIPS_INS_ADDU - addu $dst, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_ADDu_MM (849) - MIPS_INS_ADDU - addu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDu_NM (850) - MIPS_INS_ADDU - addu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ALIGN (851) - MIPS_INS_ALIGN - align $rd, $rs, $rt, $bp */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bp */ + { 0 } +}}, +{ /* MIPS_ALIGN_MMR6 (852) - MIPS_INS_ALIGN - align $rd, $rs, $rt, $bp */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bp */ + { 0 } +}}, +{ /* MIPS_ALUIPC (853) - MIPS_INS_ALUIPC - aluipc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ALUIPC_MMR6 (854) - MIPS_INS_ALUIPC - aluipc $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ALUIPC_NM (855) - MIPS_INS_ALUIPC - aluipc $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_AND (856) - MIPS_INS_AND - and $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_AND16_MM (857) - MIPS_INS_AND16 - and16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_AND16_MMR6 (858) - MIPS_INS_AND16 - and16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_AND16_NM (859) - MIPS_INS_AND - and $dst, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_AND64 (860) - MIPS_INS_INVALID - and $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_ANDI16_MM (861) - MIPS_INS_ANDI16 - andi16 $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ANDI16_MMR6 (862) - MIPS_INS_ANDI16 - andi16 $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ANDI16_NM (863) - MIPS_INS_ANDI - andi[16] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ANDI_B (864) - MIPS_INS_ANDI_B - andi.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_ANDI_MMR6 (865) - MIPS_INS_ANDI - andi $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ANDI_NM (866) - MIPS_INS_ANDI - andi[32] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_AND_MM (867) - MIPS_INS_AND - and $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_AND_MMR6 (868) - MIPS_INS_AND - and $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_AND_NM (869) - MIPS_INS_AND - and $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_AND_V (870) - MIPS_INS_AND_V - and.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ANDi (871) - MIPS_INS_ANDI - andi $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{{{ /* MIPS_ANDi64 (872) - MIPS_INS_INVALID - andi $rt, $rs, $imm16 */ + 0 +}}}, +{ /* MIPS_ANDi_MM (873) - MIPS_INS_ANDI - andi $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_APPEND (874) - MIPS_INS_APPEND - append $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_APPEND_MMR2 (875) - MIPS_INS_APPEND - append $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_ASUB_S_B (876) - MIPS_INS_ASUB_S_B - asub_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_S_D (877) - MIPS_INS_ASUB_S_D - asub_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_S_H (878) - MIPS_INS_ASUB_S_H - asub_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_S_W (879) - MIPS_INS_ASUB_S_W - asub_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_U_B (880) - MIPS_INS_ASUB_U_B - asub_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_U_D (881) - MIPS_INS_ASUB_U_D - asub_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_U_H (882) - MIPS_INS_ASUB_U_H - asub_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_U_W (883) - MIPS_INS_ASUB_U_W - asub_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AUI (884) - MIPS_INS_AUI - aui $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_AUIPC (885) - MIPS_INS_AUIPC - auipc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_AUIPC_MMR6 (886) - MIPS_INS_AUIPC - auipc $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_AUI_MMR6 (887) - MIPS_INS_AUI - aui $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_AVER_S_B (888) - MIPS_INS_AVER_S_B - aver_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_S_D (889) - MIPS_INS_AVER_S_D - aver_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_S_H (890) - MIPS_INS_AVER_S_H - aver_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_S_W (891) - MIPS_INS_AVER_S_W - aver_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_U_B (892) - MIPS_INS_AVER_U_B - aver_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_U_D (893) - MIPS_INS_AVER_U_D - aver_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_U_H (894) - MIPS_INS_AVER_U_H - aver_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_U_W (895) - MIPS_INS_AVER_U_W - aver_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_S_B (896) - MIPS_INS_AVE_S_B - ave_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_S_D (897) - MIPS_INS_AVE_S_D - ave_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_S_H (898) - MIPS_INS_AVE_S_H - ave_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_S_W (899) - MIPS_INS_AVE_S_W - ave_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_U_B (900) - MIPS_INS_AVE_U_B - ave_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_U_D (901) - MIPS_INS_AVE_U_D - ave_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_U_H (902) - MIPS_INS_AVE_U_H - ave_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_U_W (903) - MIPS_INS_AVE_U_W - ave_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AddiuRxImmX16 (904) - MIPS_INS_ADDIU - addiu $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_AddiuRxPcImmX16 (905) - MIPS_INS_ADDIU - addiu $rx, $$pc, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_AddiuRxRxImm16 (906) - MIPS_INS_ADDIU - addiu $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx_ */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{{{ /* MIPS_AddiuRxRxImmX16 (907) - MIPS_INS_INVALID - addiu $rx, $imm16 */ + 0 +}}}, +{ /* MIPS_AddiuRxRyOffMemX16 (908) - MIPS_INS_ADDIU - addiu $ry, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - CPU16RegsPlusSP */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_AddiuSpImm16 (909) - MIPS_INS_ADDIU - addiu $$sp, $imm8 # 16 bit inst */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_AddiuSpImmX16 (910) - MIPS_INS_ADDIU - addiu $$sp, $imm16 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_AdduRxRyRz16 (911) - MIPS_INS_ADDU - addu $rz, $rx, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_AndRxRxRy16 (912) - MIPS_INS_AND - and $rz, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_B16_MM (913) - MIPS_INS_B16 - b16 $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BADDu (914) - MIPS_INS_BADDU - baddu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_BAL (915) - MIPS_INS_BAL - bal $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BALC (916) - MIPS_INS_BALC - balc $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BALC16_NM (917) - MIPS_INS_BALC - balc[16] $addr */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_BALC_MMR6 (918) - MIPS_INS_BALC - balc $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BALC_NM (919) - MIPS_INS_BALC - balc $addr */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_BALIGN (920) - MIPS_INS_BALIGN - balign $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_BALIGN_MMR2 (921) - MIPS_INS_BALIGN - balign $rt, $rs, $bp */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bp */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_BALRSC_NM (922) - MIPS_INS_BALRSC - balrsc $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_BBEQZC_NM (923) - MIPS_INS_BBEQZC - bbeqzc $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BBIT0 (924) - MIPS_INS_BBIT0 - bbit0 $rs, $p, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* p */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BBIT032 (925) - MIPS_INS_BBIT032 - bbit032 $rs, $p, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* p */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BBIT1 (926) - MIPS_INS_BBIT1 - bbit1 $rs, $p, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* p */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BBIT132 (927) - MIPS_INS_BBIT132 - bbit132 $rs, $p, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* p */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BBNEZC_NM (928) - MIPS_INS_BBNEZC - bbnezc $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC (929) - MIPS_INS_BC - bc $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC16_MMR6 (930) - MIPS_INS_BC16 - bc16 $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC16_NM (931) - MIPS_INS_BC - bc $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_BC1EQZ (932) - MIPS_INS_BC1EQZ - bc1eqz $ft, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1EQZC_MMR6 (933) - MIPS_INS_BC1EQZC - bc1eqzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1F (934) - MIPS_INS_BC1F - bc1f $fcc, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1FL (935) - MIPS_INS_BC1FL - bc1fl $fcc, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1F_MM (936) - MIPS_INS_BC1F - bc1f $fcc, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1NEZ (937) - MIPS_INS_BC1NEZ - bc1nez $ft, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1NEZC_MMR6 (938) - MIPS_INS_BC1NEZC - bc1nezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1T (939) - MIPS_INS_BC1T - bc1t $fcc, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1TL (940) - MIPS_INS_BC1TL - bc1tl $fcc, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1T_MM (941) - MIPS_INS_BC1T - bc1t $fcc, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC2EQZ (942) - MIPS_INS_BC2EQZ - bc2eqz $ct, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ct */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC2EQZC_MMR6 (943) - MIPS_INS_BC2EQZC - bc2eqzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC2NEZ (944) - MIPS_INS_BC2NEZ - bc2nez $ct, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ct */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC2NEZC_MMR6 (945) - MIPS_INS_BC2NEZC - bc2nezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BCLRI_B (946) - MIPS_INS_BCLRI_B - bclri.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BCLRI_D (947) - MIPS_INS_BCLRI_D - bclri.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BCLRI_H (948) - MIPS_INS_BCLRI_H - bclri.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BCLRI_W (949) - MIPS_INS_BCLRI_W - bclri.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BCLR_B (950) - MIPS_INS_BCLR_B - bclr.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BCLR_D (951) - MIPS_INS_BCLR_D - bclr.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BCLR_H (952) - MIPS_INS_BCLR_H - bclr.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BCLR_W (953) - MIPS_INS_BCLR_W - bclr.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BC_MMR6 (954) - MIPS_INS_BC - bc $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC_NM (955) - MIPS_INS_BC - bc $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_BEQ (956) - MIPS_INS_BEQ - beq $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BEQ64 (957) - MIPS_INS_INVALID - beq $rs, $rt, $offset */ + 0 +}}}, +{ /* MIPS_BEQC (958) - MIPS_INS_BEQC - beqc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQC16_NM (959) - MIPS_INS_BEQC - beqc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQC64 (960) - MIPS_INS_BEQC - beqc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQC_MMR6 (961) - MIPS_INS_BEQC - beqc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQC_NM (962) - MIPS_INS_BEQC - beqc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQCzero_NM (963) - MIPS_INS_BEQC - beqc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQIC_NM (964) - MIPS_INS_BEQIC - beqic $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQL (965) - MIPS_INS_BEQL - beql $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZ16_MM (966) - MIPS_INS_BEQZ16 - beqz16 $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZALC (967) - MIPS_INS_BEQZALC - beqzalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZALC_MMR6 (968) - MIPS_INS_BEQZALC - beqzalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC (969) - MIPS_INS_BEQZC - beqzc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC16_MMR6 (970) - MIPS_INS_BEQZC16 - beqzc16 $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC16_NM (971) - MIPS_INS_BEQZC - beqzc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC64 (972) - MIPS_INS_BEQZC - beqzc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC_MM (973) - MIPS_INS_BEQZC - beqzc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC_MMR6 (974) - MIPS_INS_BEQZC - beqzc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC_NM (975) - MIPS_INS_BEQZC - beqzc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQ_MM (976) - MIPS_INS_BEQ - beq $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEC (977) - MIPS_INS_BGEC - bgec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEC64 (978) - MIPS_INS_BGEC - bgec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEC_MMR6 (979) - MIPS_INS_BGEC - bgec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEC_NM (980) - MIPS_INS_BGEC - bgec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEIC_NM (981) - MIPS_INS_BGEIC - bgeic $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEIUC_NM (982) - MIPS_INS_BGEIUC - bgeiuc $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEUC (983) - MIPS_INS_BGEUC - bgeuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEUC64 (984) - MIPS_INS_BGEUC - bgeuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEUC_MMR6 (985) - MIPS_INS_BGEUC - bgeuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEUC_NM (986) - MIPS_INS_BGEUC - bgeuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZ (987) - MIPS_INS_BGEZ - bgez $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BGEZ64 (988) - MIPS_INS_INVALID - bgez $rs, $offset */ + 0 +}}}, +{ /* MIPS_BGEZAL (989) - MIPS_INS_BGEZAL - bgezal $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZALC (990) - MIPS_INS_BGEZALC - bgezalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZALC_MMR6 (991) - MIPS_INS_BGEZALC - bgezalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZALL (992) - MIPS_INS_BGEZALL - bgezall $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZALS_MM (993) - MIPS_INS_BGEZALS - bgezals $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZAL_MM (994) - MIPS_INS_BGEZAL - bgezal $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZC (995) - MIPS_INS_BGEZC - bgezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZC64 (996) - MIPS_INS_BGEZC - bgezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZC_MMR6 (997) - MIPS_INS_BGEZC - bgezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZL (998) - MIPS_INS_BGEZL - bgezl $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZ_MM (999) - MIPS_INS_BGEZ - bgez $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZ (1000) - MIPS_INS_BGTZ - bgtz $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BGTZ64 (1001) - MIPS_INS_INVALID - bgtz $rs, $offset */ + 0 +}}}, +{ /* MIPS_BGTZALC (1002) - MIPS_INS_BGTZALC - bgtzalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZALC_MMR6 (1003) - MIPS_INS_BGTZALC - bgtzalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZC (1004) - MIPS_INS_BGTZC - bgtzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZC64 (1005) - MIPS_INS_BGTZC - bgtzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZC_MMR6 (1006) - MIPS_INS_BGTZC - bgtzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZL (1007) - MIPS_INS_BGTZL - bgtzl $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZ_MM (1008) - MIPS_INS_BGTZ - bgtz $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BINSLI_B (1009) - MIPS_INS_BINSLI_B - binsli.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSLI_D (1010) - MIPS_INS_BINSLI_D - binsli.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSLI_H (1011) - MIPS_INS_BINSLI_H - binsli.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSLI_W (1012) - MIPS_INS_BINSLI_W - binsli.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSL_B (1013) - MIPS_INS_BINSL_B - binsl.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSL_D (1014) - MIPS_INS_BINSL_D - binsl.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSL_H (1015) - MIPS_INS_BINSL_H - binsl.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSL_W (1016) - MIPS_INS_BINSL_W - binsl.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSRI_B (1017) - MIPS_INS_BINSRI_B - binsri.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSRI_D (1018) - MIPS_INS_BINSRI_D - binsri.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSRI_H (1019) - MIPS_INS_BINSRI_H - binsri.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSRI_W (1020) - MIPS_INS_BINSRI_W - binsri.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSR_B (1021) - MIPS_INS_BINSR_B - binsr.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSR_D (1022) - MIPS_INS_BINSR_D - binsr.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSR_H (1023) - MIPS_INS_BINSR_H - binsr.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSR_W (1024) - MIPS_INS_BINSR_W - binsr.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BITREV (1025) - MIPS_INS_BITREV - bitrev $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_BITREVW_NM (1026) - MIPS_INS_BITREVW - bitrevw $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_BITREV_MM (1027) - MIPS_INS_BITREV - bitrev $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_BITSWAP (1028) - MIPS_INS_BITSWAP - bitswap $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_BITSWAP_MMR6 (1029) - MIPS_INS_BITSWAP - bitswap $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_BLEZ (1030) - MIPS_INS_BLEZ - blez $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BLEZ64 (1031) - MIPS_INS_INVALID - blez $rs, $offset */ + 0 +}}}, +{ /* MIPS_BLEZALC (1032) - MIPS_INS_BLEZALC - blezalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEZALC_MMR6 (1033) - MIPS_INS_BLEZALC - blezalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEZC (1034) - MIPS_INS_BLEZC - blezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEZC64 (1035) - MIPS_INS_BLEZC - blezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEZC_MMR6 (1036) - MIPS_INS_BLEZC - blezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEZL (1037) - MIPS_INS_BLEZL - blezl $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEZ_MM (1038) - MIPS_INS_BLEZ - blez $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTC (1039) - MIPS_INS_BLTC - bltc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTC64 (1040) - MIPS_INS_BLTC - bltc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTC_MMR6 (1041) - MIPS_INS_BLTC - bltc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTC_NM (1042) - MIPS_INS_BLTC - bltc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTIC_NM (1043) - MIPS_INS_BLTIC - bltic $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTIUC_NM (1044) - MIPS_INS_BLTIUC - bltiuc $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTUC (1045) - MIPS_INS_BLTUC - bltuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTUC64 (1046) - MIPS_INS_BLTUC - bltuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTUC_MMR6 (1047) - MIPS_INS_BLTUC - bltuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTUC_NM (1048) - MIPS_INS_BLTUC - bltuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZ (1049) - MIPS_INS_BLTZ - bltz $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BLTZ64 (1050) - MIPS_INS_INVALID - bltz $rs, $offset */ + 0 +}}}, +{ /* MIPS_BLTZAL (1051) - MIPS_INS_BLTZAL - bltzal $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZALC (1052) - MIPS_INS_BLTZALC - bltzalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZALC_MMR6 (1053) - MIPS_INS_BLTZALC - bltzalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZALL (1054) - MIPS_INS_BLTZALL - bltzall $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZALS_MM (1055) - MIPS_INS_BLTZALS - bltzals $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZAL_MM (1056) - MIPS_INS_BLTZAL - bltzal $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZC (1057) - MIPS_INS_BLTZC - bltzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZC64 (1058) - MIPS_INS_BLTZC - bltzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZC_MMR6 (1059) - MIPS_INS_BLTZC - bltzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZL (1060) - MIPS_INS_BLTZL - bltzl $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZ_MM (1061) - MIPS_INS_BLTZ - bltz $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BMNZI_B (1062) - MIPS_INS_BMNZI_B - bmnzi.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_BMNZ_V (1063) - MIPS_INS_BMNZ_V - bmnz.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BMZI_B (1064) - MIPS_INS_BMZI_B - bmzi.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_BMZ_V (1065) - MIPS_INS_BMZ_V - bmz.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BNE (1066) - MIPS_INS_BNE - bne $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BNE64 (1067) - MIPS_INS_INVALID - bne $rs, $rt, $offset */ + 0 +}}}, +{ /* MIPS_BNEC (1068) - MIPS_INS_BNEC - bnec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEC16_NM (1069) - MIPS_INS_BNEC - bnec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEC64 (1070) - MIPS_INS_BNEC - bnec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEC_MMR6 (1071) - MIPS_INS_BNEC - bnec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEC_NM (1072) - MIPS_INS_BNEC - bnec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNECzero_NM (1073) - MIPS_INS_BNEC - bnec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEGI_B (1074) - MIPS_INS_BNEGI_B - bnegi.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BNEGI_D (1075) - MIPS_INS_BNEGI_D - bnegi.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BNEGI_H (1076) - MIPS_INS_BNEGI_H - bnegi.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BNEGI_W (1077) - MIPS_INS_BNEGI_W - bnegi.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BNEG_B (1078) - MIPS_INS_BNEG_B - bneg.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BNEG_D (1079) - MIPS_INS_BNEG_D - bneg.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BNEG_H (1080) - MIPS_INS_BNEG_H - bneg.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BNEG_W (1081) - MIPS_INS_BNEG_W - bneg.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BNEIC_NM (1082) - MIPS_INS_BNEIC - bneic $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEL (1083) - MIPS_INS_BNEL - bnel $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZ16_MM (1084) - MIPS_INS_BNEZ16 - bnez16 $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZALC (1085) - MIPS_INS_BNEZALC - bnezalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZALC_MMR6 (1086) - MIPS_INS_BNEZALC - bnezalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC (1087) - MIPS_INS_BNEZC - bnezc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC16_MMR6 (1088) - MIPS_INS_BNEZC16 - bnezc16 $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC16_NM (1089) - MIPS_INS_BNEZC - bnezc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC64 (1090) - MIPS_INS_BNEZC - bnezc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC_MM (1091) - MIPS_INS_BNEZC - bnezc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC_MMR6 (1092) - MIPS_INS_BNEZC - bnezc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC_NM (1093) - MIPS_INS_BNEZC - bnezc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNE_MM (1094) - MIPS_INS_BNE - bne $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNVC (1095) - MIPS_INS_BNVC - bnvc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNVC_MMR6 (1096) - MIPS_INS_BNVC - bnvc $rt, $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNZ_B (1097) - MIPS_INS_BNZ_B - bnz.b $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNZ_D (1098) - MIPS_INS_BNZ_D - bnz.d $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNZ_H (1099) - MIPS_INS_BNZ_H - bnz.h $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNZ_V (1100) - MIPS_INS_BNZ_V - bnz.v $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNZ_W (1101) - MIPS_INS_BNZ_W - bnz.w $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BOVC (1102) - MIPS_INS_BOVC - bovc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BOVC_MMR6 (1103) - MIPS_INS_BOVC - bovc $rt, $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BPOSGE32 (1104) - MIPS_INS_BPOSGE32 - bposge32 $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BPOSGE32C_MMR3 (1105) - MIPS_INS_BPOSGE32C - bposge32c $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BPOSGE32_MM (1106) - MIPS_INS_BPOSGE32 - bposge32 $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BREAK (1107) - MIPS_INS_BREAK - break $code_1, $code_2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_2 */ + { 0 } +}}, +{ /* MIPS_BREAK16_MM (1108) - MIPS_INS_BREAK16 - break16 $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_BREAK16_MMR6 (1109) - MIPS_INS_BREAK16 - break16 $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_BREAK16_NM (1110) - MIPS_INS_BREAK - break $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_BREAK_MM (1111) - MIPS_INS_BREAK - break $code_1, $code_2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_2 */ + { 0 } +}}, +{ /* MIPS_BREAK_MMR6 (1112) - MIPS_INS_BREAK - break $code_1, $code_2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_2 */ + { 0 } +}}, +{ /* MIPS_BREAK_NM (1113) - MIPS_INS_BREAK - break $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_BRSC_NM (1114) - MIPS_INS_BRSC - brsc $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* jti */ + { 0 } +}}, +{ /* MIPS_BSELI_B (1115) - MIPS_INS_BSELI_B - bseli.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_BSEL_V (1116) - MIPS_INS_BSEL_V - bsel.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BSETI_B (1117) - MIPS_INS_BSETI_B - bseti.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BSETI_D (1118) - MIPS_INS_BSETI_D - bseti.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BSETI_H (1119) - MIPS_INS_BSETI_H - bseti.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BSETI_W (1120) - MIPS_INS_BSETI_W - bseti.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BSET_B (1121) - MIPS_INS_BSET_B - bset.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BSET_D (1122) - MIPS_INS_BSET_D - bset.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BSET_H (1123) - MIPS_INS_BSET_H - bset.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BSET_W (1124) - MIPS_INS_BSET_W - bset.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BYTEREVW_NM (1125) - MIPS_INS_BYTEREVW - byterevw $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_BZ_B (1126) - MIPS_INS_BZ_B - bz.b $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BZ_D (1127) - MIPS_INS_BZ_D - bz.d $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BZ_H (1128) - MIPS_INS_BZ_H - bz.h $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BZ_V (1129) - MIPS_INS_BZ_V - bz.v $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BZ_W (1130) - MIPS_INS_BZ_W - bz.w $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BeqzRxImm16 (1131) - MIPS_INS_BEQZ - beqz $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_BeqzRxImmX16 (1132) - MIPS_INS_BEQZ - beqz $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_Bimm16 (1133) - MIPS_INS_B - b $imm11 # 16 bit inst */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm11 */ + { 0 } +}}, +{ /* MIPS_BimmX16 (1134) - MIPS_INS_B - b $imm16 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_BnezRxImm16 (1135) - MIPS_INS_BNEZ - bnez $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_BnezRxImmX16 (1136) - MIPS_INS_BNEZ - bnez $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_Break16 (1137) - MIPS_INS_BREAK - break 0 */ +{ + { 0 } +}}, +{ /* MIPS_Bteqz16 (1138) - MIPS_INS_BTEQZ - bteqz $imm8 # 16 bit inst */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_BteqzX16 (1139) - MIPS_INS_BTEQZ - bteqz $imm16 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_Btnez16 (1140) - MIPS_INS_BTNEZ - btnez $imm8 # 16 bit inst */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_BtnezX16 (1141) - MIPS_INS_BTNEZ - btnez $imm16 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_CACHE (1142) - MIPS_INS_CACHE - cache $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_CACHEE (1143) - MIPS_INS_CACHEE - cachee $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_CACHEE_MM (1144) - MIPS_INS_CACHEE - cachee $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_CACHE_MM (1145) - MIPS_INS_CACHE - cache $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_CACHE_MMR6 (1146) - MIPS_INS_CACHE - cache $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_CACHE_NM (1147) - MIPS_INS_CACHE - cache $op, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* op */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_CACHE_R6 (1148) - MIPS_INS_CACHE - cache $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_CEIL_L_D64 (1149) - MIPS_INS_CEIL_L_D - ceil.l.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_L_D_MMR6 (1150) - MIPS_INS_CEIL_L_D - ceil.l.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_L_S (1151) - MIPS_INS_CEIL_L_S - ceil.l.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_L_S_MMR6 (1152) - MIPS_INS_CEIL_L_S - ceil.l.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_D32 (1153) - MIPS_INS_CEIL_W_D - ceil.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_D64 (1154) - MIPS_INS_CEIL_W_D - ceil.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_D_MMR6 (1155) - MIPS_INS_CEIL_W_D - ceil.w.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_MM (1156) - MIPS_INS_CEIL_W_D - ceil.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_S (1157) - MIPS_INS_CEIL_W_S - ceil.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_S_MM (1158) - MIPS_INS_CEIL_W_S - ceil.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_S_MMR6 (1159) - MIPS_INS_CEIL_W_S - ceil.w.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEQI_B (1160) - MIPS_INS_CEQI_B - ceqi.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CEQI_D (1161) - MIPS_INS_CEQI_D - ceqi.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CEQI_H (1162) - MIPS_INS_CEQI_H - ceqi.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CEQI_W (1163) - MIPS_INS_CEQI_W - ceqi.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CEQ_B (1164) - MIPS_INS_CEQ_B - ceq.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CEQ_D (1165) - MIPS_INS_CEQ_D - ceq.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CEQ_H (1166) - MIPS_INS_CEQ_H - ceq.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CEQ_W (1167) - MIPS_INS_CEQ_W - ceq.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CFC1 (1168) - MIPS_INS_CFC1 - cfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CFC1_MM (1169) - MIPS_INS_CFC1 - cfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CFC2_MM (1170) - MIPS_INS_CFC2 - cfc2 $rt, $impl */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* impl */ + { 0 } +}}, +{ /* MIPS_CFCMSA (1171) - MIPS_INS_CFCMSA - cfcmsa $rd, $cs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cs */ + { 0 } +}}, +{ /* MIPS_CINS (1172) - MIPS_INS_CINS - cins $rt, $rs, $pos, $lenm1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lenm1 */ + { 0 } +}}, +{ /* MIPS_CINS32 (1173) - MIPS_INS_CINS32 - cins32 $rt, $rs, $pos, $lenm1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lenm1 */ + { 0 } +}}, +{{{ /* MIPS_CINS64_32 (1174) - MIPS_INS_INVALID - cins $rt, $rs, $pos, $lenm1 */ + 0 +}}}, +{{{ /* MIPS_CINS_i32 (1175) - MIPS_INS_INVALID - cins $rt, $rs, $pos, $lenm1 */ + 0 +}}}, +{ /* MIPS_CLASS_D (1176) - MIPS_INS_CLASS_D - class.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CLASS_D_MMR6 (1177) - MIPS_INS_CLASS_D - class.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CLASS_S (1178) - MIPS_INS_CLASS_S - class.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CLASS_S_MMR6 (1179) - MIPS_INS_CLASS_S - class.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CLEI_S_B (1180) - MIPS_INS_CLEI_S_B - clei_s.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_S_D (1181) - MIPS_INS_CLEI_S_D - clei_s.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_S_H (1182) - MIPS_INS_CLEI_S_H - clei_s.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_S_W (1183) - MIPS_INS_CLEI_S_W - clei_s.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_U_B (1184) - MIPS_INS_CLEI_U_B - clei_u.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_U_D (1185) - MIPS_INS_CLEI_U_D - clei_u.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_U_H (1186) - MIPS_INS_CLEI_U_H - clei_u.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_U_W (1187) - MIPS_INS_CLEI_U_W - clei_u.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLE_S_B (1188) - MIPS_INS_CLE_S_B - cle_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_S_D (1189) - MIPS_INS_CLE_S_D - cle_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_S_H (1190) - MIPS_INS_CLE_S_H - cle_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_S_W (1191) - MIPS_INS_CLE_S_W - cle_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_U_B (1192) - MIPS_INS_CLE_U_B - cle_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_U_D (1193) - MIPS_INS_CLE_U_D - cle_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_U_H (1194) - MIPS_INS_CLE_U_H - cle_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_U_W (1195) - MIPS_INS_CLE_U_W - cle_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLO (1196) - MIPS_INS_CLO - clo $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLO_MM (1197) - MIPS_INS_CLO - clo $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLO_MMR6 (1198) - MIPS_INS_CLO - clo $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLO_NM (1199) - MIPS_INS_CLO - clo $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLO_R6 (1200) - MIPS_INS_CLO - clo $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLTI_S_B (1201) - MIPS_INS_CLTI_S_B - clti_s.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_S_D (1202) - MIPS_INS_CLTI_S_D - clti_s.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_S_H (1203) - MIPS_INS_CLTI_S_H - clti_s.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_S_W (1204) - MIPS_INS_CLTI_S_W - clti_s.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_U_B (1205) - MIPS_INS_CLTI_U_B - clti_u.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_U_D (1206) - MIPS_INS_CLTI_U_D - clti_u.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_U_H (1207) - MIPS_INS_CLTI_U_H - clti_u.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_U_W (1208) - MIPS_INS_CLTI_U_W - clti_u.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLT_S_B (1209) - MIPS_INS_CLT_S_B - clt_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_S_D (1210) - MIPS_INS_CLT_S_D - clt_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_S_H (1211) - MIPS_INS_CLT_S_H - clt_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_S_W (1212) - MIPS_INS_CLT_S_W - clt_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_U_B (1213) - MIPS_INS_CLT_U_B - clt_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_U_D (1214) - MIPS_INS_CLT_U_D - clt_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_U_H (1215) - MIPS_INS_CLT_U_H - clt_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_U_W (1216) - MIPS_INS_CLT_U_W - clt_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLZ (1217) - MIPS_INS_CLZ - clz $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLZ_MM (1218) - MIPS_INS_CLZ - clz $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLZ_MMR6 (1219) - MIPS_INS_CLZ - clz $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLZ_NM (1220) - MIPS_INS_CLZ - clz $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLZ_R6 (1221) - MIPS_INS_CLZ - clz $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CMPGDU_EQ_QB (1222) - MIPS_INS_CMPGDU_EQ_QB - cmpgdu.eq.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGDU_EQ_QB_MMR2 (1223) - MIPS_INS_CMPGDU_EQ_QB - cmpgdu.eq.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGDU_LE_QB (1224) - MIPS_INS_CMPGDU_LE_QB - cmpgdu.le.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGDU_LE_QB_MMR2 (1225) - MIPS_INS_CMPGDU_LE_QB - cmpgdu.le.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGDU_LT_QB (1226) - MIPS_INS_CMPGDU_LT_QB - cmpgdu.lt.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGDU_LT_QB_MMR2 (1227) - MIPS_INS_CMPGDU_LT_QB - cmpgdu.lt.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGU_EQ_QB (1228) - MIPS_INS_CMPGU_EQ_QB - cmpgu.eq.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGU_EQ_QB_MM (1229) - MIPS_INS_CMPGU_EQ_QB - cmpgu.eq.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGU_LE_QB (1230) - MIPS_INS_CMPGU_LE_QB - cmpgu.le.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGU_LE_QB_MM (1231) - MIPS_INS_CMPGU_LE_QB - cmpgu.le.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGU_LT_QB (1232) - MIPS_INS_CMPGU_LT_QB - cmpgu.lt.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGU_LT_QB_MM (1233) - MIPS_INS_CMPGU_LT_QB - cmpgu.lt.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPU_EQ_QB (1234) - MIPS_INS_CMPU_EQ_QB - cmpu.eq.qb $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPU_EQ_QB_MM (1235) - MIPS_INS_CMPU_EQ_QB - cmpu.eq.qb $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPU_LE_QB (1236) - MIPS_INS_CMPU_LE_QB - cmpu.le.qb $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPU_LE_QB_MM (1237) - MIPS_INS_CMPU_LE_QB - cmpu.le.qb $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPU_LT_QB (1238) - MIPS_INS_CMPU_LT_QB - cmpu.lt.qb $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPU_LT_QB_MM (1239) - MIPS_INS_CMPU_LT_QB - cmpu.lt.qb $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_AF_D_MMR6 (1240) - MIPS_INS_CMP_AF_D - cmp.af.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_AF_S_MMR6 (1241) - MIPS_INS_CMP_AF_S - cmp.af.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_EQ_D (1242) - MIPS_INS_CMP_EQ_D - cmp.eq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_EQ_D_MMR6 (1243) - MIPS_INS_CMP_EQ_D - cmp.eq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_EQ_PH (1244) - MIPS_INS_CMP_EQ_PH - cmp.eq.ph $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_EQ_PH_MM (1245) - MIPS_INS_CMP_EQ_PH - cmp.eq.ph $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_EQ_S (1246) - MIPS_INS_CMP_EQ_S - cmp.eq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_EQ_S_MMR6 (1247) - MIPS_INS_CMP_EQ_S - cmp.eq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_F_D (1248) - MIPS_INS_CMP_AF_D - cmp.af.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_F_S (1249) - MIPS_INS_CMP_AF_S - cmp.af.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LE_D (1250) - MIPS_INS_CMP_LE_D - cmp.le.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LE_D_MMR6 (1251) - MIPS_INS_CMP_LE_D - cmp.le.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LE_PH (1252) - MIPS_INS_CMP_LE_PH - cmp.le.ph $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_LE_PH_MM (1253) - MIPS_INS_CMP_LE_PH - cmp.le.ph $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_LE_S (1254) - MIPS_INS_CMP_LE_S - cmp.le.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LE_S_MMR6 (1255) - MIPS_INS_CMP_LE_S - cmp.le.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LT_D (1256) - MIPS_INS_CMP_LT_D - cmp.lt.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LT_D_MMR6 (1257) - MIPS_INS_CMP_LT_D - cmp.lt.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LT_PH (1258) - MIPS_INS_CMP_LT_PH - cmp.lt.ph $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_LT_PH_MM (1259) - MIPS_INS_CMP_LT_PH - cmp.lt.ph $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_LT_S (1260) - MIPS_INS_CMP_LT_S - cmp.lt.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LT_S_MMR6 (1261) - MIPS_INS_CMP_LT_S - cmp.lt.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SAF_D (1262) - MIPS_INS_CMP_SAF_D - cmp.saf.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SAF_D_MMR6 (1263) - MIPS_INS_CMP_SAF_D - cmp.saf.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SAF_S (1264) - MIPS_INS_CMP_SAF_S - cmp.saf.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SAF_S_MMR6 (1265) - MIPS_INS_CMP_SAF_S - cmp.saf.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SEQ_D (1266) - MIPS_INS_CMP_SEQ_D - cmp.seq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SEQ_D_MMR6 (1267) - MIPS_INS_CMP_SEQ_D - cmp.seq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SEQ_S (1268) - MIPS_INS_CMP_SEQ_S - cmp.seq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SEQ_S_MMR6 (1269) - MIPS_INS_CMP_SEQ_S - cmp.seq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLE_D (1270) - MIPS_INS_CMP_SLE_D - cmp.sle.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLE_D_MMR6 (1271) - MIPS_INS_CMP_SLE_D - cmp.sle.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLE_S (1272) - MIPS_INS_CMP_SLE_S - cmp.sle.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLE_S_MMR6 (1273) - MIPS_INS_CMP_SLE_S - cmp.sle.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLT_D (1274) - MIPS_INS_CMP_SLT_D - cmp.slt.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLT_D_MMR6 (1275) - MIPS_INS_CMP_SLT_D - cmp.slt.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLT_S (1276) - MIPS_INS_CMP_SLT_S - cmp.slt.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLT_S_MMR6 (1277) - MIPS_INS_CMP_SLT_S - cmp.slt.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUEQ_D (1278) - MIPS_INS_CMP_SUEQ_D - cmp.sueq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUEQ_D_MMR6 (1279) - MIPS_INS_CMP_SUEQ_D - cmp.sueq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUEQ_S (1280) - MIPS_INS_CMP_SUEQ_S - cmp.sueq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUEQ_S_MMR6 (1281) - MIPS_INS_CMP_SUEQ_S - cmp.sueq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULE_D (1282) - MIPS_INS_CMP_SULE_D - cmp.sule.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULE_D_MMR6 (1283) - MIPS_INS_CMP_SULE_D - cmp.sule.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULE_S (1284) - MIPS_INS_CMP_SULE_S - cmp.sule.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULE_S_MMR6 (1285) - MIPS_INS_CMP_SULE_S - cmp.sule.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULT_D (1286) - MIPS_INS_CMP_SULT_D - cmp.sult.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULT_D_MMR6 (1287) - MIPS_INS_CMP_SULT_D - cmp.sult.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULT_S (1288) - MIPS_INS_CMP_SULT_S - cmp.sult.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULT_S_MMR6 (1289) - MIPS_INS_CMP_SULT_S - cmp.sult.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUN_D (1290) - MIPS_INS_CMP_SUN_D - cmp.sun.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUN_D_MMR6 (1291) - MIPS_INS_CMP_SUN_D - cmp.sun.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUN_S (1292) - MIPS_INS_CMP_SUN_S - cmp.sun.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUN_S_MMR6 (1293) - MIPS_INS_CMP_SUN_S - cmp.sun.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UEQ_D (1294) - MIPS_INS_CMP_UEQ_D - cmp.ueq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UEQ_D_MMR6 (1295) - MIPS_INS_CMP_UEQ_D - cmp.ueq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UEQ_S (1296) - MIPS_INS_CMP_UEQ_S - cmp.ueq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UEQ_S_MMR6 (1297) - MIPS_INS_CMP_UEQ_S - cmp.ueq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULE_D (1298) - MIPS_INS_CMP_ULE_D - cmp.ule.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULE_D_MMR6 (1299) - MIPS_INS_CMP_ULE_D - cmp.ule.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULE_S (1300) - MIPS_INS_CMP_ULE_S - cmp.ule.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULE_S_MMR6 (1301) - MIPS_INS_CMP_ULE_S - cmp.ule.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULT_D (1302) - MIPS_INS_CMP_ULT_D - cmp.ult.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULT_D_MMR6 (1303) - MIPS_INS_CMP_ULT_D - cmp.ult.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULT_S (1304) - MIPS_INS_CMP_ULT_S - cmp.ult.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULT_S_MMR6 (1305) - MIPS_INS_CMP_ULT_S - cmp.ult.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UN_D (1306) - MIPS_INS_CMP_UN_D - cmp.un.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UN_D_MMR6 (1307) - MIPS_INS_CMP_UN_D - cmp.un.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UN_S (1308) - MIPS_INS_CMP_UN_S - cmp.un.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UN_S_MMR6 (1309) - MIPS_INS_CMP_UN_S - cmp.un.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_COPY_S_B (1310) - MIPS_INS_COPY_S_B - copy_s.b $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_COPY_S_D (1311) - MIPS_INS_COPY_S_D - copy_s.d $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_COPY_S_H (1312) - MIPS_INS_COPY_S_H - copy_s.h $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_COPY_S_W (1313) - MIPS_INS_COPY_S_W - copy_s.w $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_COPY_U_B (1314) - MIPS_INS_COPY_U_B - copy_u.b $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_COPY_U_H (1315) - MIPS_INS_COPY_U_H - copy_u.h $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_COPY_U_W (1316) - MIPS_INS_COPY_U_W - copy_u.w $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_CRC32B (1317) - MIPS_INS_CRC32B - crc32b $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32B_NM (1318) - MIPS_INS_CRC32B - crc32b $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CRC32CB (1319) - MIPS_INS_CRC32CB - crc32cb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32CB_NM (1320) - MIPS_INS_CRC32CB - crc32cb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CRC32CD (1321) - MIPS_INS_CRC32CD - crc32cd $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32CH (1322) - MIPS_INS_CRC32CH - crc32ch $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32CH_NM (1323) - MIPS_INS_CRC32CH - crc32ch $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CRC32CW (1324) - MIPS_INS_CRC32CW - crc32cw $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32CW_NM (1325) - MIPS_INS_CRC32CW - crc32cw $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CRC32D (1326) - MIPS_INS_CRC32D - crc32d $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32H (1327) - MIPS_INS_CRC32H - crc32h $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32H_NM (1328) - MIPS_INS_CRC32H - crc32h $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CRC32W (1329) - MIPS_INS_CRC32W - crc32w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32W_NM (1330) - MIPS_INS_CRC32W - crc32w $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CTC1 (1331) - MIPS_INS_CTC1 - ctc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CTC1_MM (1332) - MIPS_INS_CTC1 - ctc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CTC2_MM (1333) - MIPS_INS_CTC2 - ctc2 $rt, $impl */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* impl */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CTCMSA (1334) - MIPS_INS_CTCMSA - ctcmsa $cd, $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CVT_D32_S (1335) - MIPS_INS_CVT_D_S - cvt.d.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D32_S_MM (1336) - MIPS_INS_CVT_D_S - cvt.d.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D32_W (1337) - MIPS_INS_CVT_D_W - cvt.d.w $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D32_W_MM (1338) - MIPS_INS_CVT_D_W - cvt.d.w $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D64_L (1339) - MIPS_INS_CVT_D_L - cvt.d.l $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D64_S (1340) - MIPS_INS_CVT_D_S - cvt.d.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D64_S_MM (1341) - MIPS_INS_CVT_D_S - cvt.d.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D64_W (1342) - MIPS_INS_CVT_D_W - cvt.d.w $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D64_W_MM (1343) - MIPS_INS_CVT_D_W - cvt.d.w $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D_L_MMR6 (1344) - MIPS_INS_CVT_D_L - cvt.d.l $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_L_D64 (1345) - MIPS_INS_CVT_L_D - cvt.l.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_L_D64_MM (1346) - MIPS_INS_CVT_L_D - cvt.l.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_L_D_MMR6 (1347) - MIPS_INS_CVT_L_D - cvt.l.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_L_S (1348) - MIPS_INS_CVT_L_S - cvt.l.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_L_S_MM (1349) - MIPS_INS_CVT_L_S - cvt.l.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_L_S_MMR6 (1350) - MIPS_INS_CVT_L_S - cvt.l.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_PS_PW64 (1351) - MIPS_INS_CVT_PS_PW - cvt.ps.pw $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_PS_S64 (1352) - MIPS_INS_CVT_PS_S - cvt.ps.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CVT_PW_PS64 (1353) - MIPS_INS_CVT_PW_PS - cvt.pw.ps $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_D32 (1354) - MIPS_INS_CVT_S_D - cvt.s.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_D32_MM (1355) - MIPS_INS_CVT_S_D - cvt.s.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_D64 (1356) - MIPS_INS_CVT_S_D - cvt.s.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_D64_MM (1357) - MIPS_INS_CVT_S_D - cvt.s.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_L (1358) - MIPS_INS_CVT_S_L - cvt.s.l $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_L_MMR6 (1359) - MIPS_INS_CVT_S_L - cvt.s.l $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_PL64 (1360) - MIPS_INS_CVT_S_PL - cvt.s.pl $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_PU64 (1361) - MIPS_INS_CVT_S_PU - cvt.s.pu $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_W (1362) - MIPS_INS_CVT_S_W - cvt.s.w $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_W_MM (1363) - MIPS_INS_CVT_S_W - cvt.s.w $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_W_MMR6 (1364) - MIPS_INS_CVT_S_W - cvt.s.w $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_D32 (1365) - MIPS_INS_CVT_W_D - cvt.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_D32_MM (1366) - MIPS_INS_CVT_W_D - cvt.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_D64 (1367) - MIPS_INS_CVT_W_D - cvt.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_D64_MM (1368) - MIPS_INS_CVT_W_D - cvt.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_S (1369) - MIPS_INS_CVT_W_S - cvt.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_S_MM (1370) - MIPS_INS_CVT_W_S - cvt.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_S_MMR6 (1371) - MIPS_INS_CVT_W_S - cvt.w.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_C_EQ_D32 (1372) - MIPS_INS_C_EQ_D - c.eq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_EQ_D32_MM (1373) - MIPS_INS_C_EQ_D - c.eq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_EQ_D64 (1374) - MIPS_INS_C_EQ_D - c.eq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_EQ_D64_MM (1375) - MIPS_INS_C_EQ_D - c.eq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_EQ_S (1376) - MIPS_INS_C_EQ_S - c.eq.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_EQ_S_MM (1377) - MIPS_INS_C_EQ_S - c.eq.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_F_D32 (1378) - MIPS_INS_C_F_D - c.f.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_F_D32_MM (1379) - MIPS_INS_C_F_D - c.f.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_F_D64 (1380) - MIPS_INS_C_F_D - c.f.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_F_D64_MM (1381) - MIPS_INS_C_F_D - c.f.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_F_S (1382) - MIPS_INS_C_F_S - c.f.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_F_S_MM (1383) - MIPS_INS_C_F_S - c.f.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LE_D32 (1384) - MIPS_INS_C_LE_D - c.le.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LE_D32_MM (1385) - MIPS_INS_C_LE_D - c.le.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LE_D64 (1386) - MIPS_INS_C_LE_D - c.le.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LE_D64_MM (1387) - MIPS_INS_C_LE_D - c.le.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LE_S (1388) - MIPS_INS_C_LE_S - c.le.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LE_S_MM (1389) - MIPS_INS_C_LE_S - c.le.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LT_D32 (1390) - MIPS_INS_C_LT_D - c.lt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LT_D32_MM (1391) - MIPS_INS_C_LT_D - c.lt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LT_D64 (1392) - MIPS_INS_C_LT_D - c.lt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LT_D64_MM (1393) - MIPS_INS_C_LT_D - c.lt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LT_S (1394) - MIPS_INS_C_LT_S - c.lt.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LT_S_MM (1395) - MIPS_INS_C_LT_S - c.lt.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGE_D32 (1396) - MIPS_INS_C_NGE_D - c.nge.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGE_D32_MM (1397) - MIPS_INS_C_NGE_D - c.nge.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGE_D64 (1398) - MIPS_INS_C_NGE_D - c.nge.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGE_D64_MM (1399) - MIPS_INS_C_NGE_D - c.nge.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGE_S (1400) - MIPS_INS_C_NGE_S - c.nge.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGE_S_MM (1401) - MIPS_INS_C_NGE_S - c.nge.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGLE_D32 (1402) - MIPS_INS_C_NGLE_D - c.ngle.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGLE_D32_MM (1403) - MIPS_INS_C_NGLE_D - c.ngle.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGLE_D64 (1404) - MIPS_INS_C_NGLE_D - c.ngle.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGLE_D64_MM (1405) - MIPS_INS_C_NGLE_D - c.ngle.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGLE_S (1406) - MIPS_INS_C_NGLE_S - c.ngle.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGLE_S_MM (1407) - MIPS_INS_C_NGLE_S - c.ngle.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGL_D32 (1408) - MIPS_INS_C_NGL_D - c.ngl.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGL_D32_MM (1409) - MIPS_INS_C_NGL_D - c.ngl.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGL_D64 (1410) - MIPS_INS_C_NGL_D - c.ngl.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGL_D64_MM (1411) - MIPS_INS_C_NGL_D - c.ngl.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGL_S (1412) - MIPS_INS_C_NGL_S - c.ngl.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGL_S_MM (1413) - MIPS_INS_C_NGL_S - c.ngl.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGT_D32 (1414) - MIPS_INS_C_NGT_D - c.ngt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGT_D32_MM (1415) - MIPS_INS_C_NGT_D - c.ngt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGT_D64 (1416) - MIPS_INS_C_NGT_D - c.ngt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGT_D64_MM (1417) - MIPS_INS_C_NGT_D - c.ngt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGT_S (1418) - MIPS_INS_C_NGT_S - c.ngt.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGT_S_MM (1419) - MIPS_INS_C_NGT_S - c.ngt.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLE_D32 (1420) - MIPS_INS_C_OLE_D - c.ole.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLE_D32_MM (1421) - MIPS_INS_C_OLE_D - c.ole.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLE_D64 (1422) - MIPS_INS_C_OLE_D - c.ole.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLE_D64_MM (1423) - MIPS_INS_C_OLE_D - c.ole.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLE_S (1424) - MIPS_INS_C_OLE_S - c.ole.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLE_S_MM (1425) - MIPS_INS_C_OLE_S - c.ole.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLT_D32 (1426) - MIPS_INS_C_OLT_D - c.olt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLT_D32_MM (1427) - MIPS_INS_C_OLT_D - c.olt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLT_D64 (1428) - MIPS_INS_C_OLT_D - c.olt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLT_D64_MM (1429) - MIPS_INS_C_OLT_D - c.olt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLT_S (1430) - MIPS_INS_C_OLT_S - c.olt.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLT_S_MM (1431) - MIPS_INS_C_OLT_S - c.olt.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SEQ_D32 (1432) - MIPS_INS_C_SEQ_D - c.seq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SEQ_D32_MM (1433) - MIPS_INS_C_SEQ_D - c.seq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SEQ_D64 (1434) - MIPS_INS_C_SEQ_D - c.seq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SEQ_D64_MM (1435) - MIPS_INS_C_SEQ_D - c.seq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SEQ_S (1436) - MIPS_INS_C_SEQ_S - c.seq.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SEQ_S_MM (1437) - MIPS_INS_C_SEQ_S - c.seq.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SF_D32 (1438) - MIPS_INS_C_SF_D - c.sf.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SF_D32_MM (1439) - MIPS_INS_C_SF_D - c.sf.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SF_D64 (1440) - MIPS_INS_C_SF_D - c.sf.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SF_D64_MM (1441) - MIPS_INS_C_SF_D - c.sf.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SF_S (1442) - MIPS_INS_C_SF_S - c.sf.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SF_S_MM (1443) - MIPS_INS_C_SF_S - c.sf.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UEQ_D32 (1444) - MIPS_INS_C_UEQ_D - c.ueq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UEQ_D32_MM (1445) - MIPS_INS_C_UEQ_D - c.ueq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UEQ_D64 (1446) - MIPS_INS_C_UEQ_D - c.ueq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UEQ_D64_MM (1447) - MIPS_INS_C_UEQ_D - c.ueq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UEQ_S (1448) - MIPS_INS_C_UEQ_S - c.ueq.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UEQ_S_MM (1449) - MIPS_INS_C_UEQ_S - c.ueq.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULE_D32 (1450) - MIPS_INS_C_ULE_D - c.ule.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULE_D32_MM (1451) - MIPS_INS_C_ULE_D - c.ule.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULE_D64 (1452) - MIPS_INS_C_ULE_D - c.ule.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULE_D64_MM (1453) - MIPS_INS_C_ULE_D - c.ule.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULE_S (1454) - MIPS_INS_C_ULE_S - c.ule.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULE_S_MM (1455) - MIPS_INS_C_ULE_S - c.ule.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULT_D32 (1456) - MIPS_INS_C_ULT_D - c.ult.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULT_D32_MM (1457) - MIPS_INS_C_ULT_D - c.ult.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULT_D64 (1458) - MIPS_INS_C_ULT_D - c.ult.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULT_D64_MM (1459) - MIPS_INS_C_ULT_D - c.ult.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULT_S (1460) - MIPS_INS_C_ULT_S - c.ult.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULT_S_MM (1461) - MIPS_INS_C_ULT_S - c.ult.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UN_D32 (1462) - MIPS_INS_C_UN_D - c.un.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UN_D32_MM (1463) - MIPS_INS_C_UN_D - c.un.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UN_D64 (1464) - MIPS_INS_C_UN_D - c.un.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UN_D64_MM (1465) - MIPS_INS_C_UN_D - c.un.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UN_S (1466) - MIPS_INS_C_UN_S - c.un.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UN_S_MM (1467) - MIPS_INS_C_UN_S - c.un.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CmpRxRy16 (1468) - MIPS_INS_CMP - cmp $rx, $ry */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_CmpiRxImm16 (1469) - MIPS_INS_CMPI - cmpi $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_CmpiRxImmX16 (1470) - MIPS_INS_CMPI - cmpi $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_DADD (1471) - MIPS_INS_DADD - dadd $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DADDi (1472) - MIPS_INS_DADDI - daddi $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_DADDiu (1473) - MIPS_INS_DADDIU - daddiu $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_DADDu (1474) - MIPS_INS_DADDU - daddu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DAHI (1475) - MIPS_INS_DAHI - dahi $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DALIGN (1476) - MIPS_INS_DALIGN - dalign $rd, $rs, $rt, $bp */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bp */ + { 0 } +}}, +{ /* MIPS_DATI (1477) - MIPS_INS_DATI - dati $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DAUI (1478) - MIPS_INS_DAUI - daui $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DBITSWAP (1479) - MIPS_INS_DBITSWAP - dbitswap $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DCLO (1480) - MIPS_INS_DCLO - dclo $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DCLO_R6 (1481) - MIPS_INS_DCLO - dclo $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DCLZ (1482) - MIPS_INS_DCLZ - dclz $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DCLZ_R6 (1483) - MIPS_INS_DCLZ - dclz $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DDIV (1484) - MIPS_INS_DDIV - ddiv $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DDIVU (1485) - MIPS_INS_DDIVU - ddivu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DERET (1486) - MIPS_INS_DERET - deret */ +{ + { 0 } +}}, +{ /* MIPS_DERET_MM (1487) - MIPS_INS_DERET - deret */ +{ + { 0 } +}}, +{ /* MIPS_DERET_MMR6 (1488) - MIPS_INS_DERET - deret */ +{ + { 0 } +}}, +{ /* MIPS_DERET_NM (1489) - MIPS_INS_DERET - deret */ +{ + { 0 } +}}, +{ /* MIPS_DEXT (1490) - MIPS_INS_DEXT - dext $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{{{ /* MIPS_DEXT64_32 (1491) - MIPS_INS_INVALID - dext $rt, $rs, $pos, $size */ + 0 +}}}, +{ /* MIPS_DEXTM (1492) - MIPS_INS_DEXTM - dextm $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_DEXTU (1493) - MIPS_INS_DEXTU - dextu $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_DI (1494) - MIPS_INS_DI - di $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DINS (1495) - MIPS_INS_DINS - dins $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_DINSM (1496) - MIPS_INS_DINSM - dinsm $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_DINSU (1497) - MIPS_INS_DINSU - dinsu $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_DIV (1498) - MIPS_INS_DIV - div $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DIVU (1499) - MIPS_INS_DIVU - divu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DIVU_MMR6 (1500) - MIPS_INS_DIVU - divu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DIVU_NM (1501) - MIPS_INS_DIVU - divu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DIV_MMR6 (1502) - MIPS_INS_DIV - div $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DIV_NM (1503) - MIPS_INS_DIV - div $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DIV_S_B (1504) - MIPS_INS_DIV_S_B - div_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_S_D (1505) - MIPS_INS_DIV_S_D - div_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_S_H (1506) - MIPS_INS_DIV_S_H - div_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_S_W (1507) - MIPS_INS_DIV_S_W - div_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_U_B (1508) - MIPS_INS_DIV_U_B - div_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_U_D (1509) - MIPS_INS_DIV_U_D - div_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_U_H (1510) - MIPS_INS_DIV_U_H - div_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_U_W (1511) - MIPS_INS_DIV_U_W - div_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DI_MM (1512) - MIPS_INS_DI - di $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DI_MMR6 (1513) - MIPS_INS_DI - di $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DI_NM (1514) - MIPS_INS_DI - di $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DLSA (1515) - MIPS_INS_DLSA - dlsa $rd, $rs, $rt, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_DLSA_R6 (1516) - MIPS_INS_DLSA - dlsa $rd, $rs, $rt, $imm2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm2 */ + { 0 } +}}, +{ /* MIPS_DMFC0 (1517) - MIPS_INS_DMFC0 - dmfc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_DMFC1 (1518) - MIPS_INS_DMFC1 - dmfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_DMFC2 (1519) - MIPS_INS_DMFC2 - dmfc2 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_DMFC2_OCTEON (1520) - MIPS_INS_DMFC2 - dmfc2 $rt, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_DMFGC0 (1521) - MIPS_INS_DMFGC0 - dmfgc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_DMOD (1522) - MIPS_INS_DMOD - dmod $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMODU (1523) - MIPS_INS_DMODU - dmodu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMT (1524) - MIPS_INS_DMT - dmt $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMTC0 (1525) - MIPS_INS_DMTC0 - dmtc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_DMTC1 (1526) - MIPS_INS_DMTC1 - dmtc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMTC2 (1527) - MIPS_INS_DMTC2 - dmtc2 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_DMTC2_OCTEON (1528) - MIPS_INS_DMTC2 - dmtc2 $rt, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_DMTGC0 (1529) - MIPS_INS_DMTGC0 - dmtgc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_DMT_NM (1530) - MIPS_INS_DMT - dmt $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMUH (1531) - MIPS_INS_DMUH - dmuh $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMUHU (1532) - MIPS_INS_DMUHU - dmuhu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMUL (1533) - MIPS_INS_DMUL - dmul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMULT (1534) - MIPS_INS_DMULT - dmult $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMULTu (1535) - MIPS_INS_DMULTU - dmultu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMULU (1536) - MIPS_INS_DMULU - dmulu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMUL_R6 (1537) - MIPS_INS_DMUL - dmul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DOTP_S_D (1538) - MIPS_INS_DOTP_S_D - dotp_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DOTP_S_H (1539) - MIPS_INS_DOTP_S_H - dotp_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DOTP_S_W (1540) - MIPS_INS_DOTP_S_W - dotp_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DOTP_U_D (1541) - MIPS_INS_DOTP_U_D - dotp_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DOTP_U_H (1542) - MIPS_INS_DOTP_U_H - dotp_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DOTP_U_W (1543) - MIPS_INS_DOTP_U_W - dotp_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPADD_S_D (1544) - MIPS_INS_DPADD_S_D - dpadd_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPADD_S_H (1545) - MIPS_INS_DPADD_S_H - dpadd_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPADD_S_W (1546) - MIPS_INS_DPADD_S_W - dpadd_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPADD_U_D (1547) - MIPS_INS_DPADD_U_D - dpadd_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPADD_U_H (1548) - MIPS_INS_DPADD_U_H - dpadd_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPADD_U_W (1549) - MIPS_INS_DPADD_U_W - dpadd_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPAQX_SA_W_PH (1550) - MIPS_INS_DPAQX_SA_W_PH - dpaqx_sa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQX_SA_W_PH_MMR2 (1551) - MIPS_INS_DPAQX_SA_W_PH - dpaqx_sa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQX_S_W_PH (1552) - MIPS_INS_DPAQX_S_W_PH - dpaqx_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQX_S_W_PH_MMR2 (1553) - MIPS_INS_DPAQX_S_W_PH - dpaqx_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQ_SA_L_W (1554) - MIPS_INS_DPAQ_SA_L_W - dpaq_sa.l.w $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQ_SA_L_W_MM (1555) - MIPS_INS_DPAQ_SA_L_W - dpaq_sa.l.w $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQ_S_W_PH (1556) - MIPS_INS_DPAQ_S_W_PH - dpaq_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQ_S_W_PH_MM (1557) - MIPS_INS_DPAQ_S_W_PH - dpaq_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAU_H_QBL (1558) - MIPS_INS_DPAU_H_QBL - dpau.h.qbl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAU_H_QBL_MM (1559) - MIPS_INS_DPAU_H_QBL - dpau.h.qbl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAU_H_QBR (1560) - MIPS_INS_DPAU_H_QBR - dpau.h.qbr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAU_H_QBR_MM (1561) - MIPS_INS_DPAU_H_QBR - dpau.h.qbr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAX_W_PH (1562) - MIPS_INS_DPAX_W_PH - dpax.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAX_W_PH_MMR2 (1563) - MIPS_INS_DPAX_W_PH - dpax.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPA_W_PH (1564) - MIPS_INS_DPA_W_PH - dpa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPA_W_PH_MMR2 (1565) - MIPS_INS_DPA_W_PH - dpa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPOP (1566) - MIPS_INS_DPOP - dpop $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DPSQX_SA_W_PH (1567) - MIPS_INS_DPSQX_SA_W_PH - dpsqx_sa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQX_SA_W_PH_MMR2 (1568) - MIPS_INS_DPSQX_SA_W_PH - dpsqx_sa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQX_S_W_PH (1569) - MIPS_INS_DPSQX_S_W_PH - dpsqx_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQX_S_W_PH_MMR2 (1570) - MIPS_INS_DPSQX_S_W_PH - dpsqx_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQ_SA_L_W (1571) - MIPS_INS_DPSQ_SA_L_W - dpsq_sa.l.w $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQ_SA_L_W_MM (1572) - MIPS_INS_DPSQ_SA_L_W - dpsq_sa.l.w $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQ_S_W_PH (1573) - MIPS_INS_DPSQ_S_W_PH - dpsq_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQ_S_W_PH_MM (1574) - MIPS_INS_DPSQ_S_W_PH - dpsq_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSUB_S_D (1575) - MIPS_INS_DPSUB_S_D - dpsub_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPSUB_S_H (1576) - MIPS_INS_DPSUB_S_H - dpsub_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPSUB_S_W (1577) - MIPS_INS_DPSUB_S_W - dpsub_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPSUB_U_D (1578) - MIPS_INS_DPSUB_U_D - dpsub_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPSUB_U_H (1579) - MIPS_INS_DPSUB_U_H - dpsub_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPSUB_U_W (1580) - MIPS_INS_DPSUB_U_W - dpsub_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPSU_H_QBL (1581) - MIPS_INS_DPSU_H_QBL - dpsu.h.qbl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSU_H_QBL_MM (1582) - MIPS_INS_DPSU_H_QBL - dpsu.h.qbl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSU_H_QBR (1583) - MIPS_INS_DPSU_H_QBR - dpsu.h.qbr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSU_H_QBR_MM (1584) - MIPS_INS_DPSU_H_QBR - dpsu.h.qbr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSX_W_PH (1585) - MIPS_INS_DPSX_W_PH - dpsx.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSX_W_PH_MMR2 (1586) - MIPS_INS_DPSX_W_PH - dpsx.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPS_W_PH (1587) - MIPS_INS_DPS_W_PH - dps.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPS_W_PH_MMR2 (1588) - MIPS_INS_DPS_W_PH - dps.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DROTR (1589) - MIPS_INS_DROTR - drotr $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DROTR32 (1590) - MIPS_INS_DROTR32 - drotr32 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DROTRV (1591) - MIPS_INS_DROTRV - drotrv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DSBH (1592) - MIPS_INS_DSBH - dsbh $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DSDIV (1593) - MIPS_INS_DDIV - ddiv $$zero, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DSHD (1594) - MIPS_INS_DSHD - dshd $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DSLL (1595) - MIPS_INS_DSLL - dsll $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DSLL32 (1596) - MIPS_INS_DSLL32 - dsll32 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{{{ /* MIPS_DSLL64_32 (1597) - MIPS_INS_INVALID - dsll $rd, $rt, 32 */ + 0 +}}}, +{ /* MIPS_DSLLV (1598) - MIPS_INS_DSLLV - dsllv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DSRA (1599) - MIPS_INS_DSRA - dsra $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DSRA32 (1600) - MIPS_INS_DSRA32 - dsra32 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DSRAV (1601) - MIPS_INS_DSRAV - dsrav $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DSRL (1602) - MIPS_INS_DSRL - dsrl $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DSRL32 (1603) - MIPS_INS_DSRL32 - dsrl32 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DSRLV (1604) - MIPS_INS_DSRLV - dsrlv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DSUB (1605) - MIPS_INS_DSUB - dsub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DSUBu (1606) - MIPS_INS_DSUBU - dsubu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DUDIV (1607) - MIPS_INS_DDIVU - ddivu $$zero, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DVP (1608) - MIPS_INS_DVP - dvp $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DVPE (1609) - MIPS_INS_DVPE - dvpe $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DVPE_NM (1610) - MIPS_INS_DVPE - dvpe $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DVP_MMR6 (1611) - MIPS_INS_DVP - dvp $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DivRxRy16 (1612) - MIPS_INS_DIV - div $$zero, $rx, $ry */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_DivuRxRy16 (1613) - MIPS_INS_DIVU - divu $$zero, $rx, $ry */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_EHB (1614) - MIPS_INS_EHB - ehb */ +{ + { 0 } +}}, +{ /* MIPS_EHB_MM (1615) - MIPS_INS_EHB - ehb */ +{ + { 0 } +}}, +{ /* MIPS_EHB_MMR6 (1616) - MIPS_INS_EHB - ehb */ +{ + { 0 } +}}, +{ /* MIPS_EHB_NM (1617) - MIPS_INS_EHB - ehb */ +{ + { 0 } +}}, +{ /* MIPS_EI (1618) - MIPS_INS_EI - ei $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EI_MM (1619) - MIPS_INS_EI - ei $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EI_MMR6 (1620) - MIPS_INS_EI - ei $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EI_NM (1621) - MIPS_INS_EI - ei $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EMT (1622) - MIPS_INS_EMT - emt $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EMT_NM (1623) - MIPS_INS_EMT - emt $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ERET (1624) - MIPS_INS_ERET - eret */ +{ + { 0 } +}}, +{ /* MIPS_ERETNC (1625) - MIPS_INS_ERETNC - eretnc */ +{ + { 0 } +}}, +{ /* MIPS_ERETNC_MMR6 (1626) - MIPS_INS_ERETNC - eretnc */ +{ + { 0 } +}}, +{ /* MIPS_ERETNC_NM (1627) - MIPS_INS_ERETNC - eretnc */ +{ + { 0 } +}}, +{ /* MIPS_ERET_MM (1628) - MIPS_INS_ERET - eret */ +{ + { 0 } +}}, +{ /* MIPS_ERET_MMR6 (1629) - MIPS_INS_ERET - eret */ +{ + { 0 } +}}, +{ /* MIPS_ERET_NM (1630) - MIPS_INS_ERET - eret */ +{ + { 0 } +}}, +{ /* MIPS_EVP (1631) - MIPS_INS_EVP - evp $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EVPE (1632) - MIPS_INS_EVPE - evpe $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EVPE_NM (1633) - MIPS_INS_EVPE - evpe $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EVP_MMR6 (1634) - MIPS_INS_EVP - evp $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXT (1635) - MIPS_INS_EXT - ext $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_EXTP (1636) - MIPS_INS_EXTP - extp $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTPDP (1637) - MIPS_INS_EXTPDP - extpdp $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTPDPV (1638) - MIPS_INS_EXTPDPV - extpdpv $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTPDPV_MM (1639) - MIPS_INS_EXTPDPV - extpdpv $rt, $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXTPDP_MM (1640) - MIPS_INS_EXTPDP - extpdp $rt, $ac, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_EXTPV (1641) - MIPS_INS_EXTPV - extpv $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTPV_MM (1642) - MIPS_INS_EXTPV - extpv $rt, $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXTP_MM (1643) - MIPS_INS_EXTP - extp $rt, $ac, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_EXTRV_RS_W (1644) - MIPS_INS_EXTRV_RS_W - extrv_rs.w $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_RS_W_MM (1645) - MIPS_INS_EXTRV_RS_W - extrv_rs.w $rt, $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_R_W (1646) - MIPS_INS_EXTRV_R_W - extrv_r.w $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_R_W_MM (1647) - MIPS_INS_EXTRV_R_W - extrv_r.w $rt, $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_S_H (1648) - MIPS_INS_EXTRV_S_H - extrv_s.h $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_S_H_MM (1649) - MIPS_INS_EXTRV_S_H - extrv_s.h $rt, $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_W (1650) - MIPS_INS_EXTRV_W - extrv.w $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_W_MM (1651) - MIPS_INS_EXTRV_W - extrv.w $rt, $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXTR_RS_W (1652) - MIPS_INS_EXTR_RS_W - extr_rs.w $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTR_RS_W_MM (1653) - MIPS_INS_EXTR_RS_W - extr_rs.w $rt, $ac, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_EXTR_R_W (1654) - MIPS_INS_EXTR_R_W - extr_r.w $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTR_R_W_MM (1655) - MIPS_INS_EXTR_R_W - extr_r.w $rt, $ac, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_EXTR_S_H (1656) - MIPS_INS_EXTR_S_H - extr_s.h $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTR_S_H_MM (1657) - MIPS_INS_EXTR_S_H - extr_s.h $rt, $ac, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_EXTR_W (1658) - MIPS_INS_EXTR_W - extr.w $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTR_W_MM (1659) - MIPS_INS_EXTR_W - extr.w $rt, $ac, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_EXTS (1660) - MIPS_INS_EXTS - exts $rt, $rs, $pos, $lenm1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lenm1 */ + { 0 } +}}, +{ /* MIPS_EXTS32 (1661) - MIPS_INS_EXTS32 - exts32 $rt, $rs, $pos, $lenm1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lenm1 */ + { 0 } +}}, +{ /* MIPS_EXTW_NM (1662) - MIPS_INS_EXTW - extw $rd, $rs, $rt, $shift */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift */ + { 0 } +}}, +{ /* MIPS_EXT_MM (1663) - MIPS_INS_EXT - ext $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_EXT_MMR6 (1664) - MIPS_INS_EXT - ext $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_EXT_NM (1665) - MIPS_INS_EXT - ext $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_FABS_D32 (1666) - MIPS_INS_ABS_D - abs.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FABS_D32_MM (1667) - MIPS_INS_ABS_D - abs.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FABS_D64 (1668) - MIPS_INS_ABS_D - abs.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FABS_D64_MM (1669) - MIPS_INS_ABS_D - abs.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FABS_S (1670) - MIPS_INS_ABS_S - abs.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FABS_S_MM (1671) - MIPS_INS_ABS_S - abs.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FADD_D (1672) - MIPS_INS_FADD_D - fadd.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FADD_D32 (1673) - MIPS_INS_ADD_D - add.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_D32_MM (1674) - MIPS_INS_ADD_D - add.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_D64 (1675) - MIPS_INS_ADD_D - add.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_D64_MM (1676) - MIPS_INS_ADD_D - add.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_PS64 (1677) - MIPS_INS_ADD_PS - add.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_S (1678) - MIPS_INS_ADD_S - add.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_S_MM (1679) - MIPS_INS_ADD_S - add.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_S_MMR6 (1680) - MIPS_INS_ADD_S - add.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FADD_W (1681) - MIPS_INS_FADD_W - fadd.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCAF_D (1682) - MIPS_INS_FCAF_D - fcaf.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCAF_W (1683) - MIPS_INS_FCAF_W - fcaf.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCEQ_D (1684) - MIPS_INS_FCEQ_D - fceq.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCEQ_W (1685) - MIPS_INS_FCEQ_W - fceq.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCLASS_D (1686) - MIPS_INS_FCLASS_D - fclass.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FCLASS_W (1687) - MIPS_INS_FCLASS_W - fclass.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FCLE_D (1688) - MIPS_INS_FCLE_D - fcle.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCLE_W (1689) - MIPS_INS_FCLE_W - fcle.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCLT_D (1690) - MIPS_INS_FCLT_D - fclt.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCLT_W (1691) - MIPS_INS_FCLT_W - fclt.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{{{ /* MIPS_FCMP_D32 (1692) - MIPS_INS_INVALID - c.$cond.d $fs, $ft */ + 0 +}}}, +{{{ /* MIPS_FCMP_D32_MM (1693) - MIPS_INS_INVALID - c.$cond.d $fs, $ft */ + 0 +}}}, +{{{ /* MIPS_FCMP_D64 (1694) - MIPS_INS_INVALID - c.$cond.d $fs, $ft */ + 0 +}}}, +{{{ /* MIPS_FCMP_S32 (1695) - MIPS_INS_INVALID - c.$cond.s $fs, $ft */ + 0 +}}}, +{{{ /* MIPS_FCMP_S32_MM (1696) - MIPS_INS_INVALID - c.$cond.s $fs, $ft */ + 0 +}}}, +{ /* MIPS_FCNE_D (1697) - MIPS_INS_FCNE_D - fcne.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCNE_W (1698) - MIPS_INS_FCNE_W - fcne.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCOR_D (1699) - MIPS_INS_FCOR_D - fcor.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCOR_W (1700) - MIPS_INS_FCOR_W - fcor.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCUEQ_D (1701) - MIPS_INS_FCUEQ_D - fcueq.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCUEQ_W (1702) - MIPS_INS_FCUEQ_W - fcueq.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCULE_D (1703) - MIPS_INS_FCULE_D - fcule.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCULE_W (1704) - MIPS_INS_FCULE_W - fcule.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCULT_D (1705) - MIPS_INS_FCULT_D - fcult.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCULT_W (1706) - MIPS_INS_FCULT_W - fcult.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCUNE_D (1707) - MIPS_INS_FCUNE_D - fcune.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCUNE_W (1708) - MIPS_INS_FCUNE_W - fcune.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCUN_D (1709) - MIPS_INS_FCUN_D - fcun.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCUN_W (1710) - MIPS_INS_FCUN_W - fcun.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FDIV_D (1711) - MIPS_INS_FDIV_D - fdiv.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FDIV_D32 (1712) - MIPS_INS_DIV_D - div.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FDIV_D32_MM (1713) - MIPS_INS_DIV_D - div.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FDIV_D64 (1714) - MIPS_INS_DIV_D - div.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FDIV_D64_MM (1715) - MIPS_INS_DIV_D - div.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FDIV_S (1716) - MIPS_INS_DIV_S - div.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FDIV_S_MM (1717) - MIPS_INS_DIV_S - div.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FDIV_S_MMR6 (1718) - MIPS_INS_DIV_S - div.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FDIV_W (1719) - MIPS_INS_FDIV_W - fdiv.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FEXDO_H (1720) - MIPS_INS_FEXDO_H - fexdo.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FEXDO_W (1721) - MIPS_INS_FEXDO_W - fexdo.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FEXP2_D (1722) - MIPS_INS_FEXP2_D - fexp2.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FEXP2_W (1723) - MIPS_INS_FEXP2_W - fexp2.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FEXUPL_D (1724) - MIPS_INS_FEXUPL_D - fexupl.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FEXUPL_W (1725) - MIPS_INS_FEXUPL_W - fexupl.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FEXUPR_D (1726) - MIPS_INS_FEXUPR_D - fexupr.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FEXUPR_W (1727) - MIPS_INS_FEXUPR_W - fexupr.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFINT_S_D (1728) - MIPS_INS_FFINT_S_D - ffint_s.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFINT_S_W (1729) - MIPS_INS_FFINT_S_W - ffint_s.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFINT_U_D (1730) - MIPS_INS_FFINT_U_D - ffint_u.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFINT_U_W (1731) - MIPS_INS_FFINT_U_W - ffint_u.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFQL_D (1732) - MIPS_INS_FFQL_D - ffql.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFQL_W (1733) - MIPS_INS_FFQL_W - ffql.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFQR_D (1734) - MIPS_INS_FFQR_D - ffqr.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFQR_W (1735) - MIPS_INS_FFQR_W - ffqr.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FILL_B (1736) - MIPS_INS_FILL_B - fill.b $wd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_FILL_D (1737) - MIPS_INS_FILL_D - fill.d $wd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_FILL_H (1738) - MIPS_INS_FILL_H - fill.h $wd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_FILL_W (1739) - MIPS_INS_FILL_W - fill.w $wd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_FLOG2_D (1740) - MIPS_INS_FLOG2_D - flog2.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FLOG2_W (1741) - MIPS_INS_FLOG2_W - flog2.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FLOOR_L_D64 (1742) - MIPS_INS_FLOOR_L_D - floor.l.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_L_D_MMR6 (1743) - MIPS_INS_FLOOR_L_D - floor.l.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_L_S (1744) - MIPS_INS_FLOOR_L_S - floor.l.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_L_S_MMR6 (1745) - MIPS_INS_FLOOR_L_S - floor.l.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_D32 (1746) - MIPS_INS_FLOOR_W_D - floor.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_D64 (1747) - MIPS_INS_FLOOR_W_D - floor.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_D_MMR6 (1748) - MIPS_INS_FLOOR_W_D - floor.w.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_MM (1749) - MIPS_INS_FLOOR_W_D - floor.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_S (1750) - MIPS_INS_FLOOR_W_S - floor.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_S_MM (1751) - MIPS_INS_FLOOR_W_S - floor.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_S_MMR6 (1752) - MIPS_INS_FLOOR_W_S - floor.w.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMADD_D (1753) - MIPS_INS_FMADD_D - fmadd.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMADD_W (1754) - MIPS_INS_FMADD_W - fmadd.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMAX_A_D (1755) - MIPS_INS_FMAX_A_D - fmax_a.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMAX_A_W (1756) - MIPS_INS_FMAX_A_W - fmax_a.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMAX_D (1757) - MIPS_INS_FMAX_D - fmax.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMAX_W (1758) - MIPS_INS_FMAX_W - fmax.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMIN_A_D (1759) - MIPS_INS_FMIN_A_D - fmin_a.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMIN_A_W (1760) - MIPS_INS_FMIN_A_W - fmin_a.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMIN_D (1761) - MIPS_INS_FMIN_D - fmin.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMIN_W (1762) - MIPS_INS_FMIN_W - fmin.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMOV_D32 (1763) - MIPS_INS_MOV_D - mov.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_D32_MM (1764) - MIPS_INS_MOV_D - mov.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_D64 (1765) - MIPS_INS_MOV_D - mov.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_D64_MM (1766) - MIPS_INS_MOV_D - mov.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_D_MMR6 (1767) - MIPS_INS_MOV_D - mov.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_S (1768) - MIPS_INS_MOV_S - mov.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_S_MM (1769) - MIPS_INS_MOV_S - mov.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_S_MMR6 (1770) - MIPS_INS_MOV_S - mov.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMSUB_D (1771) - MIPS_INS_FMSUB_D - fmsub.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMSUB_W (1772) - MIPS_INS_FMSUB_W - fmsub.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMUL_D (1773) - MIPS_INS_FMUL_D - fmul.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMUL_D32 (1774) - MIPS_INS_MUL_D - mul.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_D32_MM (1775) - MIPS_INS_MUL_D - mul.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_D64 (1776) - MIPS_INS_MUL_D - mul.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_D64_MM (1777) - MIPS_INS_MUL_D - mul.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_PS64 (1778) - MIPS_INS_MUL_PS - mul.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_S (1779) - MIPS_INS_MUL_S - mul.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_S_MM (1780) - MIPS_INS_MUL_S - mul.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_S_MMR6 (1781) - MIPS_INS_MUL_S - mul.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMUL_W (1782) - MIPS_INS_FMUL_W - fmul.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FNEG_D32 (1783) - MIPS_INS_NEG_D - neg.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FNEG_D32_MM (1784) - MIPS_INS_NEG_D - neg.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FNEG_D64 (1785) - MIPS_INS_NEG_D - neg.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FNEG_D64_MM (1786) - MIPS_INS_NEG_D - neg.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FNEG_S (1787) - MIPS_INS_NEG_S - neg.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FNEG_S_MM (1788) - MIPS_INS_NEG_S - neg.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FNEG_S_MMR6 (1789) - MIPS_INS_NEG_S - neg.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FORK (1790) - MIPS_INS_FORK - fork $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_FORK_NM (1791) - MIPS_INS_FORK - fork $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_FRCP_D (1792) - MIPS_INS_FRCP_D - frcp.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FRCP_W (1793) - MIPS_INS_FRCP_W - frcp.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FRINT_D (1794) - MIPS_INS_FRINT_D - frint.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FRINT_W (1795) - MIPS_INS_FRINT_W - frint.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FRSQRT_D (1796) - MIPS_INS_FRSQRT_D - frsqrt.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FRSQRT_W (1797) - MIPS_INS_FRSQRT_W - frsqrt.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FSAF_D (1798) - MIPS_INS_FSAF_D - fsaf.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSAF_W (1799) - MIPS_INS_FSAF_W - fsaf.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSEQ_D (1800) - MIPS_INS_FSEQ_D - fseq.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSEQ_W (1801) - MIPS_INS_FSEQ_W - fseq.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSLE_D (1802) - MIPS_INS_FSLE_D - fsle.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSLE_W (1803) - MIPS_INS_FSLE_W - fsle.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSLT_D (1804) - MIPS_INS_FSLT_D - fslt.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSLT_W (1805) - MIPS_INS_FSLT_W - fslt.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSNE_D (1806) - MIPS_INS_FSNE_D - fsne.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSNE_W (1807) - MIPS_INS_FSNE_W - fsne.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSOR_D (1808) - MIPS_INS_FSOR_D - fsor.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSOR_W (1809) - MIPS_INS_FSOR_W - fsor.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSQRT_D (1810) - MIPS_INS_FSQRT_D - fsqrt.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FSQRT_D32 (1811) - MIPS_INS_SQRT_D - sqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSQRT_D32_MM (1812) - MIPS_INS_SQRT_D - sqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSQRT_D64 (1813) - MIPS_INS_SQRT_D - sqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSQRT_D64_MM (1814) - MIPS_INS_SQRT_D - sqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSQRT_S (1815) - MIPS_INS_SQRT_S - sqrt.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSQRT_S_MM (1816) - MIPS_INS_SQRT_S - sqrt.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSQRT_W (1817) - MIPS_INS_FSQRT_W - fsqrt.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FSUB_D (1818) - MIPS_INS_FSUB_D - fsub.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUB_D32 (1819) - MIPS_INS_SUB_D - sub.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_D32_MM (1820) - MIPS_INS_SUB_D - sub.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_D64 (1821) - MIPS_INS_SUB_D - sub.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_D64_MM (1822) - MIPS_INS_SUB_D - sub.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_PS64 (1823) - MIPS_INS_SUB_PS - sub.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_S (1824) - MIPS_INS_SUB_S - sub.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_S_MM (1825) - MIPS_INS_SUB_S - sub.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_S_MMR6 (1826) - MIPS_INS_SUB_S - sub.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSUB_W (1827) - MIPS_INS_FSUB_W - fsub.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUEQ_D (1828) - MIPS_INS_FSUEQ_D - fsueq.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUEQ_W (1829) - MIPS_INS_FSUEQ_W - fsueq.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSULE_D (1830) - MIPS_INS_FSULE_D - fsule.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSULE_W (1831) - MIPS_INS_FSULE_W - fsule.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSULT_D (1832) - MIPS_INS_FSULT_D - fsult.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSULT_W (1833) - MIPS_INS_FSULT_W - fsult.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUNE_D (1834) - MIPS_INS_FSUNE_D - fsune.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUNE_W (1835) - MIPS_INS_FSUNE_W - fsune.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUN_D (1836) - MIPS_INS_FSUN_D - fsun.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUN_W (1837) - MIPS_INS_FSUN_W - fsun.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FTINT_S_D (1838) - MIPS_INS_FTINT_S_D - ftint_s.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTINT_S_W (1839) - MIPS_INS_FTINT_S_W - ftint_s.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTINT_U_D (1840) - MIPS_INS_FTINT_U_D - ftint_u.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTINT_U_W (1841) - MIPS_INS_FTINT_U_W - ftint_u.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTQ_H (1842) - MIPS_INS_FTQ_H - ftq.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FTQ_W (1843) - MIPS_INS_FTQ_W - ftq.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FTRUNC_S_D (1844) - MIPS_INS_FTRUNC_S_D - ftrunc_s.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTRUNC_S_W (1845) - MIPS_INS_FTRUNC_S_W - ftrunc_s.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTRUNC_U_D (1846) - MIPS_INS_FTRUNC_U_D - ftrunc_u.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTRUNC_U_W (1847) - MIPS_INS_FTRUNC_U_W - ftrunc_u.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_GINVI (1848) - MIPS_INS_GINVI - ginvi $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_GINVI_MMR6 (1849) - MIPS_INS_GINVI - ginvi $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_GINVI_NM (1850) - MIPS_INS_GINVI - ginvi $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_GINVT (1851) - MIPS_INS_GINVT - ginvt $rs, $type_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* type_ */ + { 0 } +}}, +{ /* MIPS_GINVT_MMR6 (1852) - MIPS_INS_GINVT - ginvt $rs, $type */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* type */ + { 0 } +}}, +{ /* MIPS_GINVT_NM (1853) - MIPS_INS_GINVT - ginvt $rs, $type */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* type */ + { 0 } +}}, +{ /* MIPS_HADD_S_D (1854) - MIPS_INS_HADD_S_D - hadd_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HADD_S_H (1855) - MIPS_INS_HADD_S_H - hadd_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HADD_S_W (1856) - MIPS_INS_HADD_S_W - hadd_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HADD_U_D (1857) - MIPS_INS_HADD_U_D - hadd_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HADD_U_H (1858) - MIPS_INS_HADD_U_H - hadd_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HADD_U_W (1859) - MIPS_INS_HADD_U_W - hadd_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HSUB_S_D (1860) - MIPS_INS_HSUB_S_D - hsub_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HSUB_S_H (1861) - MIPS_INS_HSUB_S_H - hsub_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HSUB_S_W (1862) - MIPS_INS_HSUB_S_W - hsub_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HSUB_U_D (1863) - MIPS_INS_HSUB_U_D - hsub_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HSUB_U_H (1864) - MIPS_INS_HSUB_U_H - hsub_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HSUB_U_W (1865) - MIPS_INS_HSUB_U_W - hsub_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HYPCALL (1866) - MIPS_INS_HYPCALL - hypcall $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_HYPCALL_MM (1867) - MIPS_INS_HYPCALL - hypcall $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_ILVEV_B (1868) - MIPS_INS_ILVEV_B - ilvev.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVEV_D (1869) - MIPS_INS_ILVEV_D - ilvev.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVEV_H (1870) - MIPS_INS_ILVEV_H - ilvev.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVEV_W (1871) - MIPS_INS_ILVEV_W - ilvev.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVL_B (1872) - MIPS_INS_ILVL_B - ilvl.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVL_D (1873) - MIPS_INS_ILVL_D - ilvl.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVL_H (1874) - MIPS_INS_ILVL_H - ilvl.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVL_W (1875) - MIPS_INS_ILVL_W - ilvl.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVOD_B (1876) - MIPS_INS_ILVOD_B - ilvod.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVOD_D (1877) - MIPS_INS_ILVOD_D - ilvod.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVOD_H (1878) - MIPS_INS_ILVOD_H - ilvod.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVOD_W (1879) - MIPS_INS_ILVOD_W - ilvod.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVR_B (1880) - MIPS_INS_ILVR_B - ilvr.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVR_D (1881) - MIPS_INS_ILVR_D - ilvr.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVR_H (1882) - MIPS_INS_ILVR_H - ilvr.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVR_W (1883) - MIPS_INS_ILVR_W - ilvr.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_INS (1884) - MIPS_INS_INS - ins $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_INSERT_B (1885) - MIPS_INS_INSERT_B - insert.b $wd[$n], $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_INSERT_D (1886) - MIPS_INS_INSERT_D - insert.d $wd[$n], $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_INSERT_H (1887) - MIPS_INS_INSERT_H - insert.h $wd[$n], $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_INSERT_W (1888) - MIPS_INS_INSERT_W - insert.w $wd[$n], $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_INSV (1889) - MIPS_INS_INSV - insv $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_INSVE_B (1890) - MIPS_INS_INSVE_B - insve.b $wd[$n], $ws[$n2] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n2 */ + { 0 } +}}, +{ /* MIPS_INSVE_D (1891) - MIPS_INS_INSVE_D - insve.d $wd[$n], $ws[$n2] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n2 */ + { 0 } +}}, +{ /* MIPS_INSVE_H (1892) - MIPS_INS_INSVE_H - insve.h $wd[$n], $ws[$n2] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n2 */ + { 0 } +}}, +{ /* MIPS_INSVE_W (1893) - MIPS_INS_INSVE_W - insve.w $wd[$n], $ws[$n2] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n2 */ + { 0 } +}}, +{ /* MIPS_INSV_MM (1894) - MIPS_INS_INSV - insv $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_INS_MM (1895) - MIPS_INS_INS - ins $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_INS_MMR6 (1896) - MIPS_INS_INS - ins $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_INS_NM (1897) - MIPS_INS_INS - ins $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_J (1898) - MIPS_INS_J - j $target */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* MIPS_JAL (1899) - MIPS_INS_JAL - jal $target */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* MIPS_JALR (1900) - MIPS_INS_JALR - jalr $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALR16_MM (1901) - MIPS_INS_JALR - jalr $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALR64 (1902) - MIPS_INS_JALR - jalr $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRC16_MMR6 (1903) - MIPS_INS_JALR - jalr $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRC16_NM (1904) - MIPS_INS_JALRC - jalrc $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRCHB_NM (1905) - MIPS_INS_JALRC_HB - jalrc.hb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRC_HB_MMR6 (1906) - MIPS_INS_JALRC_HB - jalrc.hb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRC_MMR6 (1907) - MIPS_INS_JALRC - jalrc $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRC_NM (1908) - MIPS_INS_JALRC - jalrc $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRS16_MM (1909) - MIPS_INS_JALRS16 - jalrs16 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRS_MM (1910) - MIPS_INS_JALRS - jalrs $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALR_HB (1911) - MIPS_INS_JALR_HB - jalr.hb $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALR_HB64 (1912) - MIPS_INS_JALR_HB - jalr.hb $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALR_MM (1913) - MIPS_INS_JALR - jalr $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALS_MM (1914) - MIPS_INS_JALS - jals $target */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* MIPS_JALX (1915) - MIPS_INS_JALX - jalx $target */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* MIPS_JALX_MM (1916) - MIPS_INS_JALX - jalx $target */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* MIPS_JAL_MM (1917) - MIPS_INS_JAL - jal $target */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* MIPS_JIALC (1918) - MIPS_INS_JIALC - jialc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_JIALC64 (1919) - MIPS_INS_JIALC - jialc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_JIALC_MMR6 (1920) - MIPS_INS_JIALC - jialc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_JIC (1921) - MIPS_INS_JIC - jic $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_JIC64 (1922) - MIPS_INS_JIC - jic $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_JIC_MMR6 (1923) - MIPS_INS_JIC - jic $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_JR (1924) - MIPS_INS_JR - jr $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR16_MM (1925) - MIPS_INS_JR16 - jr16 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR64 (1926) - MIPS_INS_JR - jr $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JRADDIUSP (1927) - MIPS_INS_JRADDIUSP - jraddiusp $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_JRC16_MM (1928) - MIPS_INS_JRC - jrc $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JRC16_MMR6 (1929) - MIPS_INS_JRC16 - jrc16 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JRCADDIUSP_MMR6 (1930) - MIPS_INS_JRCADDIUSP - jrcaddiusp $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_JRC_NM (1931) - MIPS_INS_JRC - jrc $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR_HB (1932) - MIPS_INS_JR_HB - jr.hb $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR_HB64 (1933) - MIPS_INS_JR_HB - jr.hb $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR_HB64_R6 (1934) - MIPS_INS_JR_HB - jr.hb $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR_HB_R6 (1935) - MIPS_INS_JR_HB - jr.hb $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR_MM (1936) - MIPS_INS_JR - jr $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_J_MM (1937) - MIPS_INS_J - j $target */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{{{ /* MIPS_Jal16 (1938) - MIPS_INS_INVALID - jal $imm26 + nop */ + 0 +}}}, +{{{ /* MIPS_JalB16 (1939) - MIPS_INS_INVALID - jal $imm26 # branch + nop */ + 0 +}}}, +{ /* MIPS_JrRa16 (1940) - MIPS_INS_JR - jr $$ra */ +{ + { 0 } +}}, +{ /* MIPS_JrcRa16 (1941) - MIPS_INS_JRC - jrc $$ra */ +{ + { 0 } +}}, +{ /* MIPS_JrcRx16 (1942) - MIPS_INS_JRC - jrc $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JumpLinkReg16 (1943) - MIPS_INS_JALRC - jalrc $rx */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { 0 } +}}, +{ /* MIPS_LAPC32_NM (1944) - MIPS_INS_LAPC_H - lapc.h $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_LAPC48_NM (1945) - MIPS_INS_LAPC_B - lapc.b $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_LB (1946) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LB16_NM (1947) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LB64 (1948) - MIPS_INS_INVALID - lb $rt, $addr */ + 0 +}}}, +{ /* MIPS_LBE (1949) - MIPS_INS_LBE - lbe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LBE_MM (1950) - MIPS_INS_LBE - lbe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBGP_NM (1951) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBU16_MM (1952) - MIPS_INS_LBU16 - lbu16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_LBU16_NM (1953) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBUGP_NM (1954) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBUX (1955) - MIPS_INS_LBUX - lbux $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LBUX_MM (1956) - MIPS_INS_LBUX - lbux $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LBUX_NM (1957) - MIPS_INS_LBUX - lbux $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBU_MMR6 (1958) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBU_NM (1959) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBUs9_NM (1960) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBX_NM (1961) - MIPS_INS_LBX - lbx $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LB_MM (1962) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LB_MMR6 (1963) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LB_NM (1964) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBs9_NM (1965) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBu (1966) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LBu64 (1967) - MIPS_INS_INVALID - lbu $rt, $addr */ + 0 +}}}, +{ /* MIPS_LBuE (1968) - MIPS_INS_LBUE - lbue $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LBuE_MM (1969) - MIPS_INS_LBUE - lbue $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBu_MM (1970) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LD (1971) - MIPS_INS_LD - ld $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC1 (1972) - MIPS_INS_LDC1 - ldc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC164 (1973) - MIPS_INS_LDC1 - ldc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC1_D64_MMR6 (1974) - MIPS_INS_LDC1 - ldc1 $ft, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC1_MM_D32 (1975) - MIPS_INS_LDC1 - ldc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC1_MM_D64 (1976) - MIPS_INS_LDC1 - ldc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC2 (1977) - MIPS_INS_LDC2 - ldc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC2_MMR6 (1978) - MIPS_INS_LDC2 - ldc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_LDC2_R6 (1979) - MIPS_INS_LDC2 - ldc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_LDC3 (1980) - MIPS_INS_LDC3 - ldc3 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDI_B (1981) - MIPS_INS_LDI_B - ldi.b $wd, $s10 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* s10 */ + { 0 } +}}, +{ /* MIPS_LDI_D (1982) - MIPS_INS_LDI_D - ldi.d $wd, $s10 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* s10 */ + { 0 } +}}, +{ /* MIPS_LDI_H (1983) - MIPS_INS_LDI_H - ldi.h $wd, $s10 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* s10 */ + { 0 } +}}, +{ /* MIPS_LDI_W (1984) - MIPS_INS_LDI_W - ldi.w $wd, $s10 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* s10 */ + { 0 } +}}, +{ /* MIPS_LDL (1985) - MIPS_INS_LDL - ldl $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LDPC (1986) - MIPS_INS_LDPC - ldpc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LDR (1987) - MIPS_INS_LDR - ldr $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LDXC1 (1988) - MIPS_INS_LDXC1 - ldxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LDXC164 (1989) - MIPS_INS_LDXC1 - ldxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LD_B (1990) - MIPS_INS_LD_B - ld.b $wd, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10 */ + { 0 } +}}, +{ /* MIPS_LD_D (1991) - MIPS_INS_LD_D - ld.d $wd, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10_lsl3 */ + { 0 } +}}, +{ /* MIPS_LD_H (1992) - MIPS_INS_LD_H - ld.h $wd, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10_lsl1 */ + { 0 } +}}, +{ /* MIPS_LD_W (1993) - MIPS_INS_LD_W - ld.w $wd, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10_lsl2 */ + { 0 } +}}, +{{{ /* MIPS_LEA_ADDIU_NM (1994) - MIPS_INS_INVALID - addiu $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LEA_ADDiu (1995) - MIPS_INS_INVALID - addiu $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LEA_ADDiu64 (1996) - MIPS_INS_INVALID - daddiu $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LEA_ADDiu_MM (1997) - MIPS_INS_INVALID - addiu $rt, $addr */ + 0 +}}}, +{ /* MIPS_LH (1998) - MIPS_INS_LH - lh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LH16_NM (1999) - MIPS_INS_LH - lh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LH64 (2000) - MIPS_INS_INVALID - lh $rt, $addr */ + 0 +}}}, +{ /* MIPS_LHE (2001) - MIPS_INS_LHE - lhe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LHE_MM (2002) - MIPS_INS_LHE - lhe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LHGP_NM (2003) - MIPS_INS_LH - lh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHU16_MM (2004) - MIPS_INS_LHU16 - lhu16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_LHU16_NM (2005) - MIPS_INS_LHU - lhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHUGP_NM (2006) - MIPS_INS_LHU - lhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHUXS_NM (2007) - MIPS_INS_LHUXS - lhuxs $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHUX_NM (2008) - MIPS_INS_LHUX - lhux $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHU_NM (2009) - MIPS_INS_LHU - lhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHUs9_NM (2010) - MIPS_INS_LHU - lhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHX (2011) - MIPS_INS_LHX - lhx $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LHXS_NM (2012) - MIPS_INS_LHXS - lhxs $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHX_MM (2013) - MIPS_INS_LHX - lhx $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LHX_NM (2014) - MIPS_INS_LHX - lhx $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LH_MM (2015) - MIPS_INS_LH - lh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LH_NM (2016) - MIPS_INS_LH - lh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHs9_NM (2017) - MIPS_INS_LH - lh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHu (2018) - MIPS_INS_LHU - lhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LHu64 (2019) - MIPS_INS_INVALID - lhu $rt, $addr */ + 0 +}}}, +{ /* MIPS_LHuE (2020) - MIPS_INS_LHUE - lhue $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LHuE_MM (2021) - MIPS_INS_LHUE - lhue $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LHu_MM (2022) - MIPS_INS_LHU - lhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LI16_MM (2023) - MIPS_INS_LI16 - li16 $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LI16_MMR6 (2024) - MIPS_INS_LI16 - li16 $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LI16_NM (2025) - MIPS_INS_LI - li $rt, $eu */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* eu */ + { 0 } +}}, +{ /* MIPS_LI48_NM (2026) - MIPS_INS_LI - li[48] $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LL (2027) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LL64 (2028) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LL64_R6 (2029) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LLD (2030) - MIPS_INS_LLD - lld $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LLD_R6 (2031) - MIPS_INS_LLD - lld $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LLE (2032) - MIPS_INS_LLE - lle $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LLE_MM (2033) - MIPS_INS_LLE - lle $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LLWP_NM (2034) - MIPS_INS_LLWP - llwp $rt, $ru, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ru */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LL_MM (2035) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_LL_MMR6 (2036) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LL_NM (2037) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LL_R6 (2038) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LSA (2039) - MIPS_INS_LSA - lsa $rd, $rs, $rt, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_LSA_MMR6 (2040) - MIPS_INS_LSA - lsa $rt, $rs, $rd, $imm2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm2 */ + { 0 } +}}, +{ /* MIPS_LSA_NM (2041) - MIPS_INS_LSA - lsa $rd, $rs, $rt, $shift */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift */ + { 0 } +}}, +{ /* MIPS_LSA_R6 (2042) - MIPS_INS_LSA - lsa $rd, $rs, $rt, $imm2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm2 */ + { 0 } +}}, +{ /* MIPS_LUI_MMR6 (2043) - MIPS_INS_LUI - lui $rt, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_LUI_NM (2044) - MIPS_INS_LUI - lui $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LUXC1 (2045) - MIPS_INS_LUXC1 - luxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LUXC164 (2046) - MIPS_INS_LUXC1 - luxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LUXC1_MM (2047) - MIPS_INS_LUXC1 - luxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LUi (2048) - MIPS_INS_LUI - lui $rt, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{{{ /* MIPS_LUi64 (2049) - MIPS_INS_INVALID - lui $rt, $imm16 */ + 0 +}}}, +{ /* MIPS_LUi_MM (2050) - MIPS_INS_LUI - lui $rt, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_LW (2051) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LW16_MM (2052) - MIPS_INS_LW16 - lw16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_LW16_NM (2053) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LW4x4_NM (2054) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LW64 (2055) - MIPS_INS_INVALID - lw $rt, $addr */ + 0 +}}}, +{ /* MIPS_LWC1 (2056) - MIPS_INS_LWC1 - lwc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWC1_MM (2057) - MIPS_INS_LWC1 - lwc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWC2 (2058) - MIPS_INS_LWC2 - lwc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWC2_MMR6 (2059) - MIPS_INS_LWC2 - lwc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_LWC2_R6 (2060) - MIPS_INS_LWC2 - lwc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_LWC3 (2061) - MIPS_INS_LWC3 - lwc3 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWDSP (2062) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWDSP_MM (2063) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWE (2064) - MIPS_INS_LWE - lwe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LWE_MM (2065) - MIPS_INS_LWE - lwe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LWGP16_NM (2066) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWGP_MM (2067) - MIPS_INS_LW - lw $rt, $offset */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* offset - ptr_gp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset - simm7_lsl2 */ + { 0 } +}}, +{ /* MIPS_LWGP_NM (2068) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWL (2069) - MIPS_INS_LWL - lwl $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{{{ /* MIPS_LWL64 (2070) - MIPS_INS_INVALID - lwl $rt, $addr */ + 0 +}}}, +{ /* MIPS_LWLE (2071) - MIPS_INS_LWLE - lwle $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LWLE_MM (2072) - MIPS_INS_LWLE - lwle $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LWL_MM (2073) - MIPS_INS_LWL - lwl $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LWM16_MM (2074) - MIPS_INS_LWM16 - lwm16 $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - uimm8 */ + { 0 } +}}, +{ /* MIPS_LWM16_MMR6 (2075) - MIPS_INS_LWM16 - lwm16 $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - uimm8 */ + { 0 } +}}, +{ /* MIPS_LWM32_MM (2076) - MIPS_INS_LWM32 - lwm32 $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_LWM_NM (2077) - MIPS_INS_LWM - lwm $rt, $addr, $rcount */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rcount */ + { 0 } +}}, +{ /* MIPS_LWPC (2078) - MIPS_INS_LWPC - lwpc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LWPC_MMR6 (2079) - MIPS_INS_LWPC - lwpc $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LWPC_NM (2080) - MIPS_INS_LWPC - lwpc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_LWP_MM (2081) - MIPS_INS_LWP - lwp $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_LWR (2082) - MIPS_INS_LWR - lwr $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{{{ /* MIPS_LWR64 (2083) - MIPS_INS_INVALID - lwr $rt, $addr */ + 0 +}}}, +{ /* MIPS_LWRE (2084) - MIPS_INS_LWRE - lwre $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LWRE_MM (2085) - MIPS_INS_LWRE - lwre $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LWR_MM (2086) - MIPS_INS_LWR - lwr $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LWSP16_NM (2087) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWSP_MM (2088) - MIPS_INS_LW - lw $rt, $offset */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* offset - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - simm5 */ + { 0 } +}}, +{ /* MIPS_LWUPC (2089) - MIPS_INS_LWUPC - lwupc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LWU_MM (2090) - MIPS_INS_LWU - lwu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_LWX (2091) - MIPS_INS_LWX - lwx $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LWXC1 (2092) - MIPS_INS_LWXC1 - lwxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LWXC1_MM (2093) - MIPS_INS_LWXC1 - lwxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LWXS16_NM (2094) - MIPS_INS_LWXS - lwxs $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWXS_MM (2095) - MIPS_INS_LWXS - lwxs $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LWXS_NM (2096) - MIPS_INS_LWXS - lwxs $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWX_MM (2097) - MIPS_INS_LWX - lwx $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LWX_NM (2098) - MIPS_INS_LWX - lwx $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LW_MM (2099) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LW_MMR6 (2100) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LW_NM (2101) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWs9_NM (2102) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWu (2103) - MIPS_INS_LWU - lwu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LbRxRyOffMemX16 (2104) - MIPS_INS_INVALID - lb $ry, $addr */ + 0 +}}}, +{{{ /* MIPS_LbuRxRyOffMemX16 (2105) - MIPS_INS_INVALID - lbu $ry, $addr */ + 0 +}}}, +{{{ /* MIPS_LhRxRyOffMemX16 (2106) - MIPS_INS_INVALID - lh $ry, $addr */ + 0 +}}}, +{{{ /* MIPS_LhuRxRyOffMemX16 (2107) - MIPS_INS_INVALID - lhu $ry, $addr */ + 0 +}}}, +{ /* MIPS_LiRxImm16 (2108) - MIPS_INS_LI - li $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{{{ /* MIPS_LiRxImmAlignX16 (2109) - MIPS_INS_INVALID - .align 2 + li $rx, $imm16 */ + 0 +}}}, +{ /* MIPS_LiRxImmX16 (2110) - MIPS_INS_LI - li $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_LwRxPcTcp16 (2111) - MIPS_INS_LW - lw $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_LwRxPcTcpX16 (2112) - MIPS_INS_LW - lw $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{{{ /* MIPS_LwRxRyOffMemX16 (2113) - MIPS_INS_INVALID - lw $ry, $addr */ + 0 +}}}, +{ /* MIPS_LwRxSpImmX16 (2114) - MIPS_INS_LW - lw $ry, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - CPU16RegsPlusSP */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_MADD (2115) - MIPS_INS_MADD - madd $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MADDF_D (2116) - MIPS_INS_MADDF_D - maddf.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADDF_D_MMR6 (2117) - MIPS_INS_MADDF_D - maddf.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADDF_S (2118) - MIPS_INS_MADDF_S - maddf.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADDF_S_MMR6 (2119) - MIPS_INS_MADDF_S - maddf.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADDR_Q_H (2120) - MIPS_INS_MADDR_Q_H - maddr_q.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADDR_Q_W (2121) - MIPS_INS_MADDR_Q_W - maddr_q.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADDU (2122) - MIPS_INS_MADDU - maddu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MADDU_DSP (2123) - MIPS_INS_MADDU - maddu $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MADDU_DSP_MM (2124) - MIPS_INS_MADDU - maddu $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MADDU_MM (2125) - MIPS_INS_MADDU - maddu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MADDV_B (2126) - MIPS_INS_MADDV_B - maddv.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADDV_D (2127) - MIPS_INS_MADDV_D - maddv.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADDV_H (2128) - MIPS_INS_MADDV_H - maddv.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADDV_W (2129) - MIPS_INS_MADDV_W - maddv.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADD_D32 (2130) - MIPS_INS_MADD_D - madd.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADD_D32_MM (2131) - MIPS_INS_MADD_D - madd.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADD_D64 (2132) - MIPS_INS_MADD_D - madd.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADD_DSP (2133) - MIPS_INS_MADD - madd $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MADD_DSP_MM (2134) - MIPS_INS_MADD - madd $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MADD_MM (2135) - MIPS_INS_MADD - madd $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MADD_Q_H (2136) - MIPS_INS_MADD_Q_H - madd_q.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADD_Q_W (2137) - MIPS_INS_MADD_Q_W - madd_q.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADD_S (2138) - MIPS_INS_MADD_S - madd.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADD_S_MM (2139) - MIPS_INS_MADD_S - madd.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAQ_SA_W_PHL (2140) - MIPS_INS_MAQ_SA_W_PHL - maq_sa.w.phl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_SA_W_PHL_MM (2141) - MIPS_INS_MAQ_SA_W_PHL - maq_sa.w.phl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_SA_W_PHR (2142) - MIPS_INS_MAQ_SA_W_PHR - maq_sa.w.phr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_SA_W_PHR_MM (2143) - MIPS_INS_MAQ_SA_W_PHR - maq_sa.w.phr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_S_W_PHL (2144) - MIPS_INS_MAQ_S_W_PHL - maq_s.w.phl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_S_W_PHL_MM (2145) - MIPS_INS_MAQ_S_W_PHL - maq_s.w.phl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_S_W_PHR (2146) - MIPS_INS_MAQ_S_W_PHR - maq_s.w.phr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_S_W_PHR_MM (2147) - MIPS_INS_MAQ_S_W_PHR - maq_s.w.phr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAXA_D (2148) - MIPS_INS_MAXA_D - maxa.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAXA_D_MMR6 (2149) - MIPS_INS_MAXA_D - maxa.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAXA_S (2150) - MIPS_INS_MAXA_S - maxa.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAXA_S_MMR6 (2151) - MIPS_INS_MAXA_S - maxa.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAXI_S_B (2152) - MIPS_INS_MAXI_S_B - maxi_s.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_S_D (2153) - MIPS_INS_MAXI_S_D - maxi_s.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_S_H (2154) - MIPS_INS_MAXI_S_H - maxi_s.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_S_W (2155) - MIPS_INS_MAXI_S_W - maxi_s.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_U_B (2156) - MIPS_INS_MAXI_U_B - maxi_u.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_U_D (2157) - MIPS_INS_MAXI_U_D - maxi_u.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_U_H (2158) - MIPS_INS_MAXI_U_H - maxi_u.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_U_W (2159) - MIPS_INS_MAXI_U_W - maxi_u.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAX_A_B (2160) - MIPS_INS_MAX_A_B - max_a.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_A_D (2161) - MIPS_INS_MAX_A_D - max_a.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_A_H (2162) - MIPS_INS_MAX_A_H - max_a.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_A_W (2163) - MIPS_INS_MAX_A_W - max_a.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_D (2164) - MIPS_INS_MAX_D - max.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAX_D_MMR6 (2165) - MIPS_INS_MAX_D - max.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAX_S (2166) - MIPS_INS_MAX_S - max.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAX_S_B (2167) - MIPS_INS_MAX_S_B - max_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_S_D (2168) - MIPS_INS_MAX_S_D - max_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_S_H (2169) - MIPS_INS_MAX_S_H - max_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_S_MMR6 (2170) - MIPS_INS_MAX_S - max.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAX_S_W (2171) - MIPS_INS_MAX_S_W - max_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_U_B (2172) - MIPS_INS_MAX_U_B - max_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_U_D (2173) - MIPS_INS_MAX_U_D - max_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_U_H (2174) - MIPS_INS_MAX_U_H - max_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_U_W (2175) - MIPS_INS_MAX_U_W - max_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MFC0 (2176) - MIPS_INS_MFC0 - mfc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFC0Sel_NM (2177) - MIPS_INS_MFC0 - mfc0 $rt, $c0s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { 0 } +}}, +{ /* MIPS_MFC0_MMR6 (2178) - MIPS_INS_MFC0 - mfc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFC0_NM (2179) - MIPS_INS_MFC0 - mfc0 $rt, $c0s, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFC1 (2180) - MIPS_INS_MFC1 - mfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFC1_D64 (2181) - MIPS_INS_MFC1 - mfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFC1_MM (2182) - MIPS_INS_MFC1 - mfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFC1_MMR6 (2183) - MIPS_INS_MFC1 - mfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFC2 (2184) - MIPS_INS_MFC2 - mfc2 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFC2_MMR6 (2185) - MIPS_INS_MFC2 - mfc2 $rt, $impl */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* impl */ + { 0 } +}}, +{ /* MIPS_MFGC0 (2186) - MIPS_INS_MFGC0 - mfgc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFGC0_MM (2187) - MIPS_INS_MFGC0 - mfgc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFHC0Sel_NM (2188) - MIPS_INS_MFHC0 - mfhc0 $rt, $c0s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { 0 } +}}, +{ /* MIPS_MFHC0_MMR6 (2189) - MIPS_INS_MFHC0 - mfhc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFHC0_NM (2190) - MIPS_INS_MFHC0 - mfhc0 $rt, $c0s, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFHC1_D32 (2191) - MIPS_INS_MFHC1 - mfhc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFHC1_D32_MM (2192) - MIPS_INS_MFHC1 - mfhc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFHC1_D64 (2193) - MIPS_INS_MFHC1 - mfhc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFHC1_D64_MM (2194) - MIPS_INS_MFHC1 - mfhc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFHC2_MMR6 (2195) - MIPS_INS_MFHC2 - mfhc2 $rt, $impl */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* impl */ + { 0 } +}}, +{ /* MIPS_MFHGC0 (2196) - MIPS_INS_MFHGC0 - mfhgc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFHGC0_MM (2197) - MIPS_INS_MFHGC0 - mfhgc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFHI (2198) - MIPS_INS_MFHI - mfhi $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_MFHI16_MM (2199) - MIPS_INS_MFHI16 - mfhi16 $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{{{ /* MIPS_MFHI64 (2200) - MIPS_INS_INVALID - mfhi $rd */ + 0 +}}}, +{ /* MIPS_MFHI_DSP (2201) - MIPS_INS_MFHI - mfhi $rd, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFHI_DSP_MM (2202) - MIPS_INS_MFHI - mfhi $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFHI_MM (2203) - MIPS_INS_MFHI - mfhi $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_MFLO (2204) - MIPS_INS_MFLO - mflo $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_MFLO16_MM (2205) - MIPS_INS_MFLO16 - mflo16 $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{{{ /* MIPS_MFLO64 (2206) - MIPS_INS_INVALID - mflo $rd */ + 0 +}}}, +{ /* MIPS_MFLO_DSP (2207) - MIPS_INS_MFLO - mflo $rd, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFLO_DSP_MM (2208) - MIPS_INS_MFLO - mflo $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFLO_MM (2209) - MIPS_INS_MFLO - mflo $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_MFTR (2210) - MIPS_INS_MFTR - mftr $rd, $rt, $u, $sel, $h */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */ + { 0 } +}}, +{ /* MIPS_MFTR_NM (2211) - MIPS_INS_MFTR - mftr $rd, $rt, $u, $sel, $h */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */ + { 0 } +}}, +{ /* MIPS_MINA_D (2212) - MIPS_INS_MINA_D - mina.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MINA_D_MMR6 (2213) - MIPS_INS_MINA_D - mina.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MINA_S (2214) - MIPS_INS_MINA_S - mina.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MINA_S_MMR6 (2215) - MIPS_INS_MINA_S - mina.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MINI_S_B (2216) - MIPS_INS_MINI_S_B - mini_s.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_S_D (2217) - MIPS_INS_MINI_S_D - mini_s.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_S_H (2218) - MIPS_INS_MINI_S_H - mini_s.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_S_W (2219) - MIPS_INS_MINI_S_W - mini_s.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_U_B (2220) - MIPS_INS_MINI_U_B - mini_u.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_U_D (2221) - MIPS_INS_MINI_U_D - mini_u.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_U_H (2222) - MIPS_INS_MINI_U_H - mini_u.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_U_W (2223) - MIPS_INS_MINI_U_W - mini_u.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MIN_A_B (2224) - MIPS_INS_MIN_A_B - min_a.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_A_D (2225) - MIPS_INS_MIN_A_D - min_a.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_A_H (2226) - MIPS_INS_MIN_A_H - min_a.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_A_W (2227) - MIPS_INS_MIN_A_W - min_a.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_D (2228) - MIPS_INS_MIN_D - min.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MIN_D_MMR6 (2229) - MIPS_INS_MIN_D - min.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MIN_S (2230) - MIPS_INS_MIN_S - min.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MIN_S_B (2231) - MIPS_INS_MIN_S_B - min_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_S_D (2232) - MIPS_INS_MIN_S_D - min_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_S_H (2233) - MIPS_INS_MIN_S_H - min_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_S_MMR6 (2234) - MIPS_INS_MIN_S - min.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MIN_S_W (2235) - MIPS_INS_MIN_S_W - min_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_U_B (2236) - MIPS_INS_MIN_U_B - min_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_U_D (2237) - MIPS_INS_MIN_U_D - min_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_U_H (2238) - MIPS_INS_MIN_U_H - min_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_U_W (2239) - MIPS_INS_MIN_U_W - min_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD (2240) - MIPS_INS_MOD - mod $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MODSUB (2241) - MIPS_INS_MODSUB - modsub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MODSUB_MM (2242) - MIPS_INS_MODSUB - modsub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MODU (2243) - MIPS_INS_MODU - modu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MODU_MMR6 (2244) - MIPS_INS_MODU - modu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MODU_NM (2245) - MIPS_INS_MODU - modu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MOD_MMR6 (2246) - MIPS_INS_MOD - mod $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MOD_NM (2247) - MIPS_INS_MOD - mod $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MOD_S_B (2248) - MIPS_INS_MOD_S_B - mod_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_S_D (2249) - MIPS_INS_MOD_S_D - mod_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_S_H (2250) - MIPS_INS_MOD_S_H - mod_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_S_W (2251) - MIPS_INS_MOD_S_W - mod_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_U_B (2252) - MIPS_INS_MOD_U_B - mod_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_U_D (2253) - MIPS_INS_MOD_U_D - mod_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_U_H (2254) - MIPS_INS_MOD_U_H - mod_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_U_W (2255) - MIPS_INS_MOD_U_W - mod_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOVE16_MM (2256) - MIPS_INS_MOVE - move $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MOVE16_MMR6 (2257) - MIPS_INS_MOVE16 - move16 $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MOVEBALC_NM (2258) - MIPS_INS_MOVE_BALC - move.balc $rd, $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_MOVEPREV_NM (2259) - MIPS_INS_MOVEP - movep $dst1, $dst2, $src1, $src2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src2 */ + { 0 } +}}, +{ /* MIPS_MOVEP_MM (2260) - MIPS_INS_MOVEP - movep $rd1, $rd2, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MOVEP_MMR6 (2261) - MIPS_INS_MOVEP - movep $rd1, $rd2, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MOVEP_NM (2262) - MIPS_INS_MOVEP - movep $dst1, $dst2, $src1, $src2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src2 */ + { 0 } +}}, +{ /* MIPS_MOVE_NM (2263) - MIPS_INS_MOVE - move $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MOVE_V (2264) - MIPS_INS_MOVE_V - move.v $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_MOVF_D32 (2265) - MIPS_INS_MOVF_D - movf.d $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVF_D32_MM (2266) - MIPS_INS_MOVF_D - movf.d $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVF_D64 (2267) - MIPS_INS_MOVF_D - movf.d $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVF_I (2268) - MIPS_INS_MOVF - movf $rd, $rs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{{{ /* MIPS_MOVF_I64 (2269) - MIPS_INS_INVALID - movf $rd, $rs, $fcc */ + 0 +}}}, +{ /* MIPS_MOVF_I_MM (2270) - MIPS_INS_MOVF - movf $rd, $rs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVF_S (2271) - MIPS_INS_MOVF_S - movf.s $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVF_S_MM (2272) - MIPS_INS_MOVF_S - movf.s $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{{{ /* MIPS_MOVN_I64_D64 (2273) - MIPS_INS_INVALID - movn.d $fd, $fs, $rt */ + 0 +}}}, +{{{ /* MIPS_MOVN_I64_I (2274) - MIPS_INS_INVALID - movn $rd, $rs, $rt */ + 0 +}}}, +{{{ /* MIPS_MOVN_I64_I64 (2275) - MIPS_INS_INVALID - movn $rd, $rs, $rt */ + 0 +}}}, +{{{ /* MIPS_MOVN_I64_S (2276) - MIPS_INS_INVALID - movn.s $fd, $fs, $rt */ + 0 +}}}, +{ /* MIPS_MOVN_I_D32 (2277) - MIPS_INS_MOVN_D - movn.d $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVN_I_D32_MM (2278) - MIPS_INS_MOVN_D - movn.d $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVN_I_D64 (2279) - MIPS_INS_MOVN_D - movn.d $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVN_I_I (2280) - MIPS_INS_MOVN - movn $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{{{ /* MIPS_MOVN_I_I64 (2281) - MIPS_INS_INVALID - movn $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_MOVN_I_MM (2282) - MIPS_INS_MOVN - movn $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVN_I_S (2283) - MIPS_INS_MOVN_S - movn.s $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVN_I_S_MM (2284) - MIPS_INS_MOVN_S - movn.s $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVN_NM (2285) - MIPS_INS_MOVN - movn $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVT_D32 (2286) - MIPS_INS_MOVT_D - movt.d $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVT_D32_MM (2287) - MIPS_INS_MOVT_D - movt.d $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVT_D64 (2288) - MIPS_INS_MOVT_D - movt.d $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVT_I (2289) - MIPS_INS_MOVT - movt $rd, $rs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{{{ /* MIPS_MOVT_I64 (2290) - MIPS_INS_INVALID - movt $rd, $rs, $fcc */ + 0 +}}}, +{ /* MIPS_MOVT_I_MM (2291) - MIPS_INS_MOVT - movt $rd, $rs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVT_S (2292) - MIPS_INS_MOVT_S - movt.s $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVT_S_MM (2293) - MIPS_INS_MOVT_S - movt.s $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{{{ /* MIPS_MOVZ_I64_D64 (2294) - MIPS_INS_INVALID - movz.d $fd, $fs, $rt */ + 0 +}}}, +{{{ /* MIPS_MOVZ_I64_I (2295) - MIPS_INS_INVALID - movz $rd, $rs, $rt */ + 0 +}}}, +{{{ /* MIPS_MOVZ_I64_I64 (2296) - MIPS_INS_INVALID - movz $rd, $rs, $rt */ + 0 +}}}, +{{{ /* MIPS_MOVZ_I64_S (2297) - MIPS_INS_INVALID - movz.s $fd, $fs, $rt */ + 0 +}}}, +{ /* MIPS_MOVZ_I_D32 (2298) - MIPS_INS_MOVZ_D - movz.d $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVZ_I_D32_MM (2299) - MIPS_INS_MOVZ_D - movz.d $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVZ_I_D64 (2300) - MIPS_INS_MOVZ_D - movz.d $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVZ_I_I (2301) - MIPS_INS_MOVZ - movz $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{{{ /* MIPS_MOVZ_I_I64 (2302) - MIPS_INS_INVALID - movz $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_MOVZ_I_MM (2303) - MIPS_INS_MOVZ - movz $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVZ_I_S (2304) - MIPS_INS_MOVZ_S - movz.s $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVZ_I_S_MM (2305) - MIPS_INS_MOVZ_S - movz.s $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVZ_NM (2306) - MIPS_INS_MOVZ - movz $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MSUB (2307) - MIPS_INS_MSUB - msub $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MSUBF_D (2308) - MIPS_INS_MSUBF_D - msubf.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUBF_D_MMR6 (2309) - MIPS_INS_MSUBF_D - msubf.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUBF_S (2310) - MIPS_INS_MSUBF_S - msubf.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUBF_S_MMR6 (2311) - MIPS_INS_MSUBF_S - msubf.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUBR_Q_H (2312) - MIPS_INS_MSUBR_Q_H - msubr_q.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUBR_Q_W (2313) - MIPS_INS_MSUBR_Q_W - msubr_q.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUBU (2314) - MIPS_INS_MSUBU - msubu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MSUBU_DSP (2315) - MIPS_INS_MSUBU - msubu $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MSUBU_DSP_MM (2316) - MIPS_INS_MSUBU - msubu $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MSUBU_MM (2317) - MIPS_INS_MSUBU - msubu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MSUBV_B (2318) - MIPS_INS_MSUBV_B - msubv.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUBV_D (2319) - MIPS_INS_MSUBV_D - msubv.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUBV_H (2320) - MIPS_INS_MSUBV_H - msubv.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUBV_W (2321) - MIPS_INS_MSUBV_W - msubv.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUB_D32 (2322) - MIPS_INS_MSUB_D - msub.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUB_D32_MM (2323) - MIPS_INS_MSUB_D - msub.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUB_D64 (2324) - MIPS_INS_MSUB_D - msub.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUB_DSP (2325) - MIPS_INS_MSUB - msub $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MSUB_DSP_MM (2326) - MIPS_INS_MSUB - msub $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MSUB_MM (2327) - MIPS_INS_MSUB - msub $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MSUB_Q_H (2328) - MIPS_INS_MSUB_Q_H - msub_q.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUB_Q_W (2329) - MIPS_INS_MSUB_Q_W - msub_q.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUB_S (2330) - MIPS_INS_MSUB_S - msub.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUB_S_MM (2331) - MIPS_INS_MSUB_S - msub.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MTC0 (2332) - MIPS_INS_MTC0 - mtc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTC0Sel_NM (2333) - MIPS_INS_MTC0 - mtc0 $rt, $c0s */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { 0 } +}}, +{ /* MIPS_MTC0_MMR6 (2334) - MIPS_INS_MTC0 - mtc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTC0_NM (2335) - MIPS_INS_MTC0 - mtc0 $rt, $c0s, $sel */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTC1 (2336) - MIPS_INS_MTC1 - mtc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTC1_D64 (2337) - MIPS_INS_MTC1 - mtc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTC1_D64_MM (2338) - MIPS_INS_MTC1 - mtc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTC1_MM (2339) - MIPS_INS_MTC1 - mtc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTC1_MMR6 (2340) - MIPS_INS_MTC1 - mtc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTC2 (2341) - MIPS_INS_MTC2 - mtc2 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTC2_MMR6 (2342) - MIPS_INS_MTC2 - mtc2 $rt, $impl */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* impl */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTGC0 (2343) - MIPS_INS_MTGC0 - mtgc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTGC0_MM (2344) - MIPS_INS_MTGC0 - mtgc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTHC0Sel_NM (2345) - MIPS_INS_MTHC0 - mthc0 $rt, $c0s */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { 0 } +}}, +{ /* MIPS_MTHC0_MMR6 (2346) - MIPS_INS_MTHC0 - mthc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTHC0_NM (2347) - MIPS_INS_MTHC0 - mthc0 $rt, $c0s, $sel */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTHC1_D32 (2348) - MIPS_INS_MTHC1 - mthc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTHC1_D32_MM (2349) - MIPS_INS_MTHC1 - mthc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTHC1_D64 (2350) - MIPS_INS_MTHC1 - mthc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTHC1_D64_MM (2351) - MIPS_INS_MTHC1 - mthc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTHC2_MMR6 (2352) - MIPS_INS_MTHC2 - mthc2 $rt, $impl */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* impl */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTHGC0 (2353) - MIPS_INS_MTHGC0 - mthgc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTHGC0_MM (2354) - MIPS_INS_MTHGC0 - mthgc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTHI (2355) - MIPS_INS_MTHI - mthi $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{{{ /* MIPS_MTHI64 (2356) - MIPS_INS_INVALID - mthi $rs */ + 0 +}}}, +{ /* MIPS_MTHI_DSP (2357) - MIPS_INS_MTHI - mthi $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTHI_DSP_MM (2358) - MIPS_INS_MTHI - mthi $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTHI_MM (2359) - MIPS_INS_MTHI - mthi $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTHLIP (2360) - MIPS_INS_MTHLIP - mthlip $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MTHLIP_MM (2361) - MIPS_INS_MTHLIP - mthlip $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MTLO (2362) - MIPS_INS_MTLO - mtlo $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{{{ /* MIPS_MTLO64 (2363) - MIPS_INS_INVALID - mtlo $rs */ + 0 +}}}, +{ /* MIPS_MTLO_DSP (2364) - MIPS_INS_MTLO - mtlo $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTLO_DSP_MM (2365) - MIPS_INS_MTLO - mtlo $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTLO_MM (2366) - MIPS_INS_MTLO - mtlo $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTM0 (2367) - MIPS_INS_MTM0 - mtm0 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTM1 (2368) - MIPS_INS_MTM1 - mtm1 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTM2 (2369) - MIPS_INS_MTM2 - mtm2 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTP0 (2370) - MIPS_INS_MTP0 - mtp0 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTP1 (2371) - MIPS_INS_MTP1 - mtp1 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTP2 (2372) - MIPS_INS_MTP2 - mtp2 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTTR (2373) - MIPS_INS_MTTR - mttr $rt, $rd, $u, $sel, $h */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */ + { 0 } +}}, +{ /* MIPS_MTTR_NM (2374) - MIPS_INS_MTTR - mttr $rt, $rd, $u, $sel, $h */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */ + { 0 } +}}, +{ /* MIPS_MUH (2375) - MIPS_INS_MUH - muh $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUHU (2376) - MIPS_INS_MUHU - muhu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUHU_MMR6 (2377) - MIPS_INS_MUHU - muhu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUHU_NM (2378) - MIPS_INS_MUHU - muhu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUH_MMR6 (2379) - MIPS_INS_MUH - muh $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUH_NM (2380) - MIPS_INS_MUH - muh $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL (2381) - MIPS_INS_MUL - mul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL4x4_NM (2382) - MIPS_INS_MUL - mul $dst, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MULEQ_S_W_PHL (2383) - MIPS_INS_MULEQ_S_W_PHL - muleq_s.w.phl $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEQ_S_W_PHL_MM (2384) - MIPS_INS_MULEQ_S_W_PHL - muleq_s.w.phl $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEQ_S_W_PHR (2385) - MIPS_INS_MULEQ_S_W_PHR - muleq_s.w.phr $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEQ_S_W_PHR_MM (2386) - MIPS_INS_MULEQ_S_W_PHR - muleq_s.w.phr $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEU_S_PH_QBL (2387) - MIPS_INS_MULEU_S_PH_QBL - muleu_s.ph.qbl $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEU_S_PH_QBL_MM (2388) - MIPS_INS_MULEU_S_PH_QBL - muleu_s.ph.qbl $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEU_S_PH_QBR (2389) - MIPS_INS_MULEU_S_PH_QBR - muleu_s.ph.qbr $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEU_S_PH_QBR_MM (2390) - MIPS_INS_MULEU_S_PH_QBR - muleu_s.ph.qbr $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_RS_PH (2391) - MIPS_INS_MULQ_RS_PH - mulq_rs.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_RS_PH_MM (2392) - MIPS_INS_MULQ_RS_PH - mulq_rs.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_RS_W (2393) - MIPS_INS_MULQ_RS_W - mulq_rs.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_RS_W_MMR2 (2394) - MIPS_INS_MULQ_RS_W - mulq_rs.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_S_PH (2395) - MIPS_INS_MULQ_S_PH - mulq_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_S_PH_MMR2 (2396) - MIPS_INS_MULQ_S_PH - mulq_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_S_W (2397) - MIPS_INS_MULQ_S_W - mulq_s.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_S_W_MMR2 (2398) - MIPS_INS_MULQ_S_W - mulq_s.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULR_PS64 (2399) - MIPS_INS_MULR_PS - mulr.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MULR_Q_H (2400) - MIPS_INS_MULR_Q_H - mulr_q.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MULR_Q_W (2401) - MIPS_INS_MULR_Q_W - mulr_q.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MULSAQ_S_W_PH (2402) - MIPS_INS_MULSAQ_S_W_PH - mulsaq_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MULSAQ_S_W_PH_MM (2403) - MIPS_INS_MULSAQ_S_W_PH - mulsaq_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MULSA_W_PH (2404) - MIPS_INS_MULSA_W_PH - mulsa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MULSA_W_PH_MMR2 (2405) - MIPS_INS_MULSA_W_PH - mulsa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MULT (2406) - MIPS_INS_MULT - mult $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULTU_DSP (2407) - MIPS_INS_MULTU - multu $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULTU_DSP_MM (2408) - MIPS_INS_MULTU - multu $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULT_DSP (2409) - MIPS_INS_MULT - mult $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULT_DSP_MM (2410) - MIPS_INS_MULT - mult $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULT_MM (2411) - MIPS_INS_MULT - mult $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULTu (2412) - MIPS_INS_MULTU - multu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULTu_MM (2413) - MIPS_INS_MULTU - multu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULU (2414) - MIPS_INS_MULU - mulu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULU_MMR6 (2415) - MIPS_INS_MULU - mulu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULU_NM (2416) - MIPS_INS_MULU - mulu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULV_B (2417) - MIPS_INS_MULV_B - mulv.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MULV_D (2418) - MIPS_INS_MULV_D - mulv.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MULV_H (2419) - MIPS_INS_MULV_H - mulv.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MULV_W (2420) - MIPS_INS_MULV_W - mulv.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MUL_MM (2421) - MIPS_INS_MUL - mul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_MMR6 (2422) - MIPS_INS_MUL - mul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_NM (2423) - MIPS_INS_MUL - mul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_PH (2424) - MIPS_INS_MUL_PH - mul.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_PH_MMR2 (2425) - MIPS_INS_MUL_PH - mul.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_Q_H (2426) - MIPS_INS_MUL_Q_H - mul_q.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MUL_Q_W (2427) - MIPS_INS_MUL_Q_W - mul_q.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MUL_R6 (2428) - MIPS_INS_MUL - mul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_S_PH (2429) - MIPS_INS_MUL_S_PH - mul_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_S_PH_MMR2 (2430) - MIPS_INS_MUL_S_PH - mul_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_Mfhi16 (2431) - MIPS_INS_MFHI - mfhi $rx */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { 0 } +}}, +{ /* MIPS_Mflo16 (2432) - MIPS_INS_MFLO - mflo $rx */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { 0 } +}}, +{ /* MIPS_Move32R16 (2433) - MIPS_INS_MOVE - move $r32, $rz */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r32 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { 0 } +}}, +{ /* MIPS_MoveR3216 (2434) - MIPS_INS_MOVE - move $ry, $r32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r32 */ + { 0 } +}}, +{ /* MIPS_NLOC_B (2435) - MIPS_INS_NLOC_B - nloc.b $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLOC_D (2436) - MIPS_INS_NLOC_D - nloc.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLOC_H (2437) - MIPS_INS_NLOC_H - nloc.h $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLOC_W (2438) - MIPS_INS_NLOC_W - nloc.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLZC_B (2439) - MIPS_INS_NLZC_B - nlzc.b $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLZC_D (2440) - MIPS_INS_NLZC_D - nlzc.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLZC_H (2441) - MIPS_INS_NLZC_H - nlzc.h $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLZC_W (2442) - MIPS_INS_NLZC_W - nlzc.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NMADD_D32 (2443) - MIPS_INS_NMADD_D - nmadd.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMADD_D32_MM (2444) - MIPS_INS_NMADD_D - nmadd.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMADD_D64 (2445) - MIPS_INS_NMADD_D - nmadd.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMADD_S (2446) - MIPS_INS_NMADD_S - nmadd.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMADD_S_MM (2447) - MIPS_INS_NMADD_S - nmadd.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMSUB_D32 (2448) - MIPS_INS_NMSUB_D - nmsub.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMSUB_D32_MM (2449) - MIPS_INS_NMSUB_D - nmsub.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMSUB_D64 (2450) - MIPS_INS_NMSUB_D - nmsub.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMSUB_S (2451) - MIPS_INS_NMSUB_S - nmsub.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMSUB_S_MM (2452) - MIPS_INS_NMSUB_S - nmsub.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NOP32_NM (2453) - MIPS_INS_NOP32 - nop32 */ +{ + { 0 } +}}, +{ /* MIPS_NOP_NM (2454) - MIPS_INS_NOP - nop */ +{ + { 0 } +}}, +{ /* MIPS_NOR (2455) - MIPS_INS_NOR - nor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_NOR64 (2456) - MIPS_INS_INVALID - nor $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_NORI_B (2457) - MIPS_INS_NORI_B - nori.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_NOR_MM (2458) - MIPS_INS_NOR - nor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_NOR_MMR6 (2459) - MIPS_INS_NOR - nor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_NOR_NM (2460) - MIPS_INS_NOR - nor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_NOR_V (2461) - MIPS_INS_NOR_V - nor.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_NOT16_MM (2462) - MIPS_INS_NOT16 - not16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_NOT16_MMR6 (2463) - MIPS_INS_NOT16 - not16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_NOT16_NM (2464) - MIPS_INS_NOT - not $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_NegRxRy16 (2465) - MIPS_INS_NEG - neg $rx, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_NotRxRy16 (2466) - MIPS_INS_NOT - not $rx, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_OR (2467) - MIPS_INS_OR - or $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_OR16_MM (2468) - MIPS_INS_OR16 - or16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_OR16_MMR6 (2469) - MIPS_INS_OR16 - or16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_OR16_NM (2470) - MIPS_INS_OR - or $dst, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_OR64 (2471) - MIPS_INS_INVALID - or $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_ORI_B (2472) - MIPS_INS_ORI_B - ori.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_ORI_MMR6 (2473) - MIPS_INS_ORI - ori $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ORI_NM (2474) - MIPS_INS_ORI - ori $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_OR_MM (2475) - MIPS_INS_OR - or $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_OR_MMR6 (2476) - MIPS_INS_OR - or $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_OR_NM (2477) - MIPS_INS_OR - or $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_OR_V (2478) - MIPS_INS_OR_V - or.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ORi (2479) - MIPS_INS_ORI - ori $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{{{ /* MIPS_ORi64 (2480) - MIPS_INS_INVALID - ori $rt, $rs, $imm16 */ + 0 +}}}, +{ /* MIPS_ORi_MM (2481) - MIPS_INS_ORI - ori $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_OrRxRxRy16 (2482) - MIPS_INS_OR - or $rz, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_PACKRL_PH (2483) - MIPS_INS_PACKRL_PH - packrl.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PACKRL_PH_MM (2484) - MIPS_INS_PACKRL_PH - packrl.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PAUSE (2485) - MIPS_INS_PAUSE - pause */ +{ + { 0 } +}}, +{ /* MIPS_PAUSE_MM (2486) - MIPS_INS_PAUSE - pause */ +{ + { 0 } +}}, +{ /* MIPS_PAUSE_MMR6 (2487) - MIPS_INS_PAUSE - pause */ +{ + { 0 } +}}, +{ /* MIPS_PAUSE_NM (2488) - MIPS_INS_PAUSE - pause */ +{ + { 0 } +}}, +{ /* MIPS_PCKEV_B (2489) - MIPS_INS_PCKEV_B - pckev.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKEV_D (2490) - MIPS_INS_PCKEV_D - pckev.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKEV_H (2491) - MIPS_INS_PCKEV_H - pckev.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKEV_W (2492) - MIPS_INS_PCKEV_W - pckev.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKOD_B (2493) - MIPS_INS_PCKOD_B - pckod.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKOD_D (2494) - MIPS_INS_PCKOD_D - pckod.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKOD_H (2495) - MIPS_INS_PCKOD_H - pckod.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKOD_W (2496) - MIPS_INS_PCKOD_W - pckod.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCNT_B (2497) - MIPS_INS_PCNT_B - pcnt.b $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_PCNT_D (2498) - MIPS_INS_PCNT_D - pcnt.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_PCNT_H (2499) - MIPS_INS_PCNT_H - pcnt.h $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_PCNT_W (2500) - MIPS_INS_PCNT_W - pcnt.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_PICK_PH (2501) - MIPS_INS_PICK_PH - pick.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PICK_PH_MM (2502) - MIPS_INS_PICK_PH - pick.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PICK_QB (2503) - MIPS_INS_PICK_QB - pick.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PICK_QB_MM (2504) - MIPS_INS_PICK_QB - pick.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PLL_PS64 (2505) - MIPS_INS_PLL_PS - pll.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_PLU_PS64 (2506) - MIPS_INS_PLU_PS - plu.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_POP (2507) - MIPS_INS_POP - pop $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBL (2508) - MIPS_INS_PRECEQU_PH_QBL - precequ.ph.qbl $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBLA (2509) - MIPS_INS_PRECEQU_PH_QBLA - precequ.ph.qbla $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBLA_MM (2510) - MIPS_INS_PRECEQU_PH_QBLA - precequ.ph.qbla $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBL_MM (2511) - MIPS_INS_PRECEQU_PH_QBL - precequ.ph.qbl $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBR (2512) - MIPS_INS_PRECEQU_PH_QBR - precequ.ph.qbr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBRA (2513) - MIPS_INS_PRECEQU_PH_QBRA - precequ.ph.qbra $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBRA_MM (2514) - MIPS_INS_PRECEQU_PH_QBRA - precequ.ph.qbra $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBR_MM (2515) - MIPS_INS_PRECEQU_PH_QBR - precequ.ph.qbr $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEQ_W_PHL (2516) - MIPS_INS_PRECEQ_W_PHL - preceq.w.phl $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEQ_W_PHL_MM (2517) - MIPS_INS_PRECEQ_W_PHL - preceq.w.phl $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEQ_W_PHR (2518) - MIPS_INS_PRECEQ_W_PHR - preceq.w.phr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEQ_W_PHR_MM (2519) - MIPS_INS_PRECEQ_W_PHR - preceq.w.phr $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBL (2520) - MIPS_INS_PRECEU_PH_QBL - preceu.ph.qbl $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBLA (2521) - MIPS_INS_PRECEU_PH_QBLA - preceu.ph.qbla $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBLA_MM (2522) - MIPS_INS_PRECEU_PH_QBLA - preceu.ph.qbla $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBL_MM (2523) - MIPS_INS_PRECEU_PH_QBL - preceu.ph.qbl $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBR (2524) - MIPS_INS_PRECEU_PH_QBR - preceu.ph.qbr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBRA (2525) - MIPS_INS_PRECEU_PH_QBRA - preceu.ph.qbra $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBRA_MM (2526) - MIPS_INS_PRECEU_PH_QBRA - preceu.ph.qbra $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBR_MM (2527) - MIPS_INS_PRECEU_PH_QBR - preceu.ph.qbr $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECRQU_S_QB_PH (2528) - MIPS_INS_PRECRQU_S_QB_PH - precrqu_s.qb.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQU_S_QB_PH_MM (2529) - MIPS_INS_PRECRQU_S_QB_PH - precrqu_s.qb.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQ_PH_W (2530) - MIPS_INS_PRECRQ_PH_W - precrq.ph.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQ_PH_W_MM (2531) - MIPS_INS_PRECRQ_PH_W - precrq.ph.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQ_QB_PH (2532) - MIPS_INS_PRECRQ_QB_PH - precrq.qb.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQ_QB_PH_MM (2533) - MIPS_INS_PRECRQ_QB_PH - precrq.qb.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQ_RS_PH_W (2534) - MIPS_INS_PRECRQ_RS_PH_W - precrq_rs.ph.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQ_RS_PH_W_MM (2535) - MIPS_INS_PRECRQ_RS_PH_W - precrq_rs.ph.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECR_QB_PH (2536) - MIPS_INS_PRECR_QB_PH - precr.qb.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECR_QB_PH_MMR2 (2537) - MIPS_INS_PRECR_QB_PH - precr.qb.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECR_SRA_PH_W (2538) - MIPS_INS_PRECR_SRA_PH_W - precr_sra.ph.w $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_PRECR_SRA_PH_W_MMR2 (2539) - MIPS_INS_PRECR_SRA_PH_W - precr_sra.ph.w $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_PRECR_SRA_R_PH_W (2540) - MIPS_INS_PRECR_SRA_R_PH_W - precr_sra_r.ph.w $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_PRECR_SRA_R_PH_W_MMR2 (2541) - MIPS_INS_PRECR_SRA_R_PH_W - precr_sra_r.ph.w $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_PREF (2542) - MIPS_INS_PREF - pref $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREFE (2543) - MIPS_INS_PREFE - prefe $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREFE_MM (2544) - MIPS_INS_PREFE - prefe $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREFX_MM (2545) - MIPS_INS_PREFX - prefx $hint, ${index}(${base}) */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREF_MM (2546) - MIPS_INS_PREF - pref $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREF_MMR6 (2547) - MIPS_INS_PREF - pref $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREF_NM (2548) - MIPS_INS_PREF - pref $op, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* op */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_PREF_R6 (2549) - MIPS_INS_PREF - pref $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREFs9_NM (2550) - MIPS_INS_PREF - pref $op, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* op */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_PREPEND (2551) - MIPS_INS_PREPEND - prepend $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_PREPEND_MMR2 (2552) - MIPS_INS_PREPEND - prepend $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_PUL_PS64 (2553) - MIPS_INS_PUL_PS - pul.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_PUU_PS64 (2554) - MIPS_INS_PUU_PS - puu.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_RADDU_W_QB (2555) - MIPS_INS_RADDU_W_QB - raddu.w.qb $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_RADDU_W_QB_MM (2556) - MIPS_INS_RADDU_W_QB - raddu.w.qb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_RDDSP (2557) - MIPS_INS_RDDSP - rddsp $rd, $mask */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { 0 } +}}, +{ /* MIPS_RDDSP_MM (2558) - MIPS_INS_RDDSP - rddsp $rt, $mask */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { 0 } +}}, +{ /* MIPS_RDHWR (2559) - MIPS_INS_RDHWR - rdhwr $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{{{ /* MIPS_RDHWR64 (2560) - MIPS_INS_INVALID - rdhwr $rt, $rd, $sel */ + 0 +}}}, +{ /* MIPS_RDHWR_MM (2561) - MIPS_INS_RDHWR - rdhwr $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_RDHWR_MMR6 (2562) - MIPS_INS_RDHWR - rdhwr $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_RDHWR_NM (2563) - MIPS_INS_RDHWR - rdhwr $rt, $hs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_RDPGPR_MMR6 (2564) - MIPS_INS_RDPGPR - rdpgpr $rt, $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_RDPGPR_NM (2565) - MIPS_INS_RDPGPR - rdpgpr $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_RECIP_D32 (2566) - MIPS_INS_RECIP_D - recip.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RECIP_D32_MM (2567) - MIPS_INS_RECIP_D - recip.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RECIP_D64 (2568) - MIPS_INS_RECIP_D - recip.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RECIP_D64_MM (2569) - MIPS_INS_RECIP_D - recip.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RECIP_S (2570) - MIPS_INS_RECIP_S - recip.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RECIP_S_MM (2571) - MIPS_INS_RECIP_S - recip.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_REPLV_PH (2572) - MIPS_INS_REPLV_PH - replv.ph $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_REPLV_PH_MM (2573) - MIPS_INS_REPLV_PH - replv.ph $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_REPLV_QB (2574) - MIPS_INS_REPLV_QB - replv.qb $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_REPLV_QB_MM (2575) - MIPS_INS_REPLV_QB - replv.qb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_REPL_PH (2576) - MIPS_INS_REPL_PH - repl.ph $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_REPL_PH_MM (2577) - MIPS_INS_REPL_PH - repl.ph $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_REPL_QB (2578) - MIPS_INS_REPL_QB - repl.qb $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_REPL_QB_MM (2579) - MIPS_INS_REPL_QB - repl.qb $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_RESTOREJRC16_NM (2580) - MIPS_INS_RESTORE_JRC - restore.jrc $adj$regs */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* adj */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } +}}, +{ /* MIPS_RESTOREJRC_NM (2581) - MIPS_INS_RESTORE_JRC - restore.jrc $adj$regs */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* adj */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } +}}, +{ /* MIPS_RESTORE_NM (2582) - MIPS_INS_RESTORE - restore $adj$regs */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* adj */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } +}}, +{ /* MIPS_RINT_D (2583) - MIPS_INS_RINT_D - rint.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RINT_D_MMR6 (2584) - MIPS_INS_RINT_D - rint.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RINT_S (2585) - MIPS_INS_RINT_S - rint.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RINT_S_MMR6 (2586) - MIPS_INS_RINT_S - rint.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROTR (2587) - MIPS_INS_ROTR - rotr $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_ROTRV (2588) - MIPS_INS_ROTRV - rotrv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_ROTRV_MM (2589) - MIPS_INS_ROTRV - rotrv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_ROTRV_NM (2590) - MIPS_INS_ROTRV - rotrv $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ROTR_MM (2591) - MIPS_INS_ROTR - rotr $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_ROTR_NM (2592) - MIPS_INS_ROTR - rotr $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ROTX_NM (2593) - MIPS_INS_ROTX - rotx $rt, $rs, $shift, $shiftx, $stripe */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shiftx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* stripe */ + { 0 } +}}, +{ /* MIPS_ROUND_L_D64 (2594) - MIPS_INS_ROUND_L_D - round.l.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_L_D_MMR6 (2595) - MIPS_INS_ROUND_L_D - round.l.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_L_S (2596) - MIPS_INS_ROUND_L_S - round.l.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_L_S_MMR6 (2597) - MIPS_INS_ROUND_L_S - round.l.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_D32 (2598) - MIPS_INS_ROUND_W_D - round.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_D64 (2599) - MIPS_INS_ROUND_W_D - round.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_D_MMR6 (2600) - MIPS_INS_ROUND_W_D - round.w.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_MM (2601) - MIPS_INS_ROUND_W_D - round.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_S (2602) - MIPS_INS_ROUND_W_S - round.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_S_MM (2603) - MIPS_INS_ROUND_W_S - round.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_S_MMR6 (2604) - MIPS_INS_ROUND_W_S - round.w.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RSQRT_D32 (2605) - MIPS_INS_RSQRT_D - rsqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RSQRT_D32_MM (2606) - MIPS_INS_RSQRT_D - rsqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RSQRT_D64 (2607) - MIPS_INS_RSQRT_D - rsqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RSQRT_D64_MM (2608) - MIPS_INS_RSQRT_D - rsqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RSQRT_S (2609) - MIPS_INS_RSQRT_S - rsqrt.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RSQRT_S_MM (2610) - MIPS_INS_RSQRT_S - rsqrt.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{{{ /* MIPS_Restore16 (2611) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_RestoreX16 (2612) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SAA (2613) - MIPS_INS_SAA - saa $rt, (${rs}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SAAD (2614) - MIPS_INS_SAAD - saad $rt, (${rs}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SAT_S_B (2615) - MIPS_INS_SAT_S_B - sat_s.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_S_D (2616) - MIPS_INS_SAT_S_D - sat_s.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_S_H (2617) - MIPS_INS_SAT_S_H - sat_s.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_S_W (2618) - MIPS_INS_SAT_S_W - sat_s.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_U_B (2619) - MIPS_INS_SAT_U_B - sat_u.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_U_D (2620) - MIPS_INS_SAT_U_D - sat_u.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_U_H (2621) - MIPS_INS_SAT_U_H - sat_u.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_U_W (2622) - MIPS_INS_SAT_U_W - sat_u.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAVE16_NM (2623) - MIPS_INS_SAVE - save $adj$regs */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* adj */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } +}}, +{ /* MIPS_SAVE_NM (2624) - MIPS_INS_SAVE - save $adj$regs */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* adj */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } +}}, +{ /* MIPS_SB (2625) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SB16_MM (2626) - MIPS_INS_SB16 - sb16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_SB16_MMR6 (2627) - MIPS_INS_SB16 - sb16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_SB16_NM (2628) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SB64 (2629) - MIPS_INS_INVALID - sb $rt, $addr */ + 0 +}}}, +{ /* MIPS_SBE (2630) - MIPS_INS_SBE - sbe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SBE_MM (2631) - MIPS_INS_SBE - sbe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SBGP_NM (2632) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SBX_NM (2633) - MIPS_INS_SBX - sbx $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SB_MM (2634) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SB_MMR6 (2635) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SB_NM (2636) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SBs9_NM (2637) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SC (2638) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SC64 (2639) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SC64_R6 (2640) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SCD (2641) - MIPS_INS_SCD - scd $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SCD_R6 (2642) - MIPS_INS_SCD - scd $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SCE (2643) - MIPS_INS_SCE - sce $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SCE_MM (2644) - MIPS_INS_SCE - sce $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SCWP_NM (2645) - MIPS_INS_SCWP - scwp $rt, $ru, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ru */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SC_MM (2646) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_SC_MMR6 (2647) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SC_NM (2648) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SC_R6 (2649) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SD (2650) - MIPS_INS_SD - sd $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDBBP (2651) - MIPS_INS_SDBBP - sdbbp $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SDBBP16_MM (2652) - MIPS_INS_SDBBP16 - sdbbp16 $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SDBBP16_MMR6 (2653) - MIPS_INS_SDBBP16 - sdbbp16 $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SDBBP16_NM (2654) - MIPS_INS_SDBBP - sdbbp $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SDBBP_MM (2655) - MIPS_INS_SDBBP - sdbbp $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SDBBP_MMR6 (2656) - MIPS_INS_SDBBP - sdbbp $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SDBBP_NM (2657) - MIPS_INS_SDBBP - sdbbp $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SDBBP_R6 (2658) - MIPS_INS_SDBBP - sdbbp $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SDC1 (2659) - MIPS_INS_SDC1 - sdc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDC164 (2660) - MIPS_INS_SDC1 - sdc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDC1_D64_MMR6 (2661) - MIPS_INS_SDC1 - sdc1 $ft, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDC1_MM_D32 (2662) - MIPS_INS_SDC1 - sdc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDC1_MM_D64 (2663) - MIPS_INS_SDC1 - sdc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDC2 (2664) - MIPS_INS_SDC2 - sdc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDC2_MMR6 (2665) - MIPS_INS_SDC2 - sdc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_SDC2_R6 (2666) - MIPS_INS_SDC2 - sdc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_SDC3 (2667) - MIPS_INS_SDC3 - sdc3 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDIV (2668) - MIPS_INS_DIV - div $$zero, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SDIV_MM (2669) - MIPS_INS_DIV - div $$zero, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SDL (2670) - MIPS_INS_SDL - sdl $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDR (2671) - MIPS_INS_SDR - sdr $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDXC1 (2672) - MIPS_INS_SDXC1 - sdxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SDXC164 (2673) - MIPS_INS_SDXC1 - sdxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SEB (2674) - MIPS_INS_SEB - seb $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_SEB64 (2675) - MIPS_INS_INVALID - seb $rd, $rt */ + 0 +}}}, +{ /* MIPS_SEB_MM (2676) - MIPS_INS_SEB - seb $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SEB_NM (2677) - MIPS_INS_SEB - seb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SEH (2678) - MIPS_INS_SEH - seh $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_SEH64 (2679) - MIPS_INS_INVALID - seh $rd, $rt */ + 0 +}}}, +{ /* MIPS_SEH_MM (2680) - MIPS_INS_SEH - seh $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SEH_NM (2681) - MIPS_INS_SEH - seh $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SELEQZ (2682) - MIPS_INS_SELEQZ - seleqz $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SELEQZ64 (2683) - MIPS_INS_SELEQZ - seleqz $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SELEQZ_D (2684) - MIPS_INS_SELEQZ_D - seleqz.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELEQZ_D_MMR6 (2685) - MIPS_INS_SELEQZ_D - seleqz.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELEQZ_MMR6 (2686) - MIPS_INS_SELEQZ - seleqz $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SELEQZ_S (2687) - MIPS_INS_SELEQZ_S - seleqz.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELEQZ_S_MMR6 (2688) - MIPS_INS_SELEQZ_S - seleqz.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELNEZ (2689) - MIPS_INS_SELNEZ - selnez $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SELNEZ64 (2690) - MIPS_INS_SELNEZ - selnez $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SELNEZ_D (2691) - MIPS_INS_SELNEZ_D - selnez.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELNEZ_D_MMR6 (2692) - MIPS_INS_SELNEZ_D - selnez.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELNEZ_MMR6 (2693) - MIPS_INS_SELNEZ - selnez $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SELNEZ_S (2694) - MIPS_INS_SELNEZ_S - selnez.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELNEZ_S_MMR6 (2695) - MIPS_INS_SELNEZ_S - selnez.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SEL_D (2696) - MIPS_INS_SEL_D - sel.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SEL_D_MMR6 (2697) - MIPS_INS_SEL_D - sel.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SEL_S (2698) - MIPS_INS_SEL_S - sel.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SEL_S_MMR6 (2699) - MIPS_INS_SEL_S - sel.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SEQ (2700) - MIPS_INS_SEQ - seq $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SEQI_NM (2701) - MIPS_INS_SEQI - seqi $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SEQi (2702) - MIPS_INS_SEQI - seqi $rt, $rs, $imm10 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm10 */ + { 0 } +}}, +{ /* MIPS_SH (2703) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SH16_MM (2704) - MIPS_INS_SH16 - sh16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_SH16_MMR6 (2705) - MIPS_INS_SH16 - sh16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_SH16_NM (2706) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SH64 (2707) - MIPS_INS_INVALID - sh $rt, $addr */ + 0 +}}}, +{ /* MIPS_SHE (2708) - MIPS_INS_SHE - she $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SHE_MM (2709) - MIPS_INS_SHE - she $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SHF_B (2710) - MIPS_INS_SHF_B - shf.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_SHF_H (2711) - MIPS_INS_SHF_H - shf.h $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_SHF_W (2712) - MIPS_INS_SHF_W - shf.w $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_SHGP_NM (2713) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SHILO (2714) - MIPS_INS_SHILO - shilo $ac, $shift */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_SHILOV (2715) - MIPS_INS_SHILOV - shilov $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_SHILOV_MM (2716) - MIPS_INS_SHILOV - shilov $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_SHILO_MM (2717) - MIPS_INS_SHILO - shilo $ac, $shift */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_SHLLV_PH (2718) - MIPS_INS_SHLLV_PH - shllv.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLLV_PH_MM (2719) - MIPS_INS_SHLLV_PH - shllv.ph $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHLLV_QB (2720) - MIPS_INS_SHLLV_QB - shllv.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLLV_QB_MM (2721) - MIPS_INS_SHLLV_QB - shllv.qb $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHLLV_S_PH (2722) - MIPS_INS_SHLLV_S_PH - shllv_s.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLLV_S_PH_MM (2723) - MIPS_INS_SHLLV_S_PH - shllv_s.ph $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHLLV_S_W (2724) - MIPS_INS_SHLLV_S_W - shllv_s.w $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLLV_S_W_MM (2725) - MIPS_INS_SHLLV_S_W - shllv_s.w $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHLL_PH (2726) - MIPS_INS_SHLL_PH - shll.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLL_PH_MM (2727) - MIPS_INS_SHLL_PH - shll.ph $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHLL_QB (2728) - MIPS_INS_SHLL_QB - shll.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLL_QB_MM (2729) - MIPS_INS_SHLL_QB - shll.qb $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHLL_S_PH (2730) - MIPS_INS_SHLL_S_PH - shll_s.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLL_S_PH_MM (2731) - MIPS_INS_SHLL_S_PH - shll_s.ph $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHLL_S_W (2732) - MIPS_INS_SHLL_S_W - shll_s.w $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLL_S_W_MM (2733) - MIPS_INS_SHLL_S_W - shll_s.w $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRAV_PH (2734) - MIPS_INS_SHRAV_PH - shrav.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRAV_PH_MM (2735) - MIPS_INS_SHRAV_PH - shrav.ph $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRAV_QB (2736) - MIPS_INS_SHRAV_QB - shrav.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRAV_QB_MMR2 (2737) - MIPS_INS_SHRAV_QB - shrav.qb $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRAV_R_PH (2738) - MIPS_INS_SHRAV_R_PH - shrav_r.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRAV_R_PH_MM (2739) - MIPS_INS_SHRAV_R_PH - shrav_r.ph $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRAV_R_QB (2740) - MIPS_INS_SHRAV_R_QB - shrav_r.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRAV_R_QB_MMR2 (2741) - MIPS_INS_SHRAV_R_QB - shrav_r.qb $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRAV_R_W (2742) - MIPS_INS_SHRAV_R_W - shrav_r.w $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRAV_R_W_MM (2743) - MIPS_INS_SHRAV_R_W - shrav_r.w $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRA_PH (2744) - MIPS_INS_SHRA_PH - shra.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRA_PH_MM (2745) - MIPS_INS_SHRA_PH - shra.ph $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRA_QB (2746) - MIPS_INS_SHRA_QB - shra.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRA_QB_MMR2 (2747) - MIPS_INS_SHRA_QB - shra.qb $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRA_R_PH (2748) - MIPS_INS_SHRA_R_PH - shra_r.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRA_R_PH_MM (2749) - MIPS_INS_SHRA_R_PH - shra_r.ph $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRA_R_QB (2750) - MIPS_INS_SHRA_R_QB - shra_r.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRA_R_QB_MMR2 (2751) - MIPS_INS_SHRA_R_QB - shra_r.qb $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRA_R_W (2752) - MIPS_INS_SHRA_R_W - shra_r.w $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRA_R_W_MM (2753) - MIPS_INS_SHRA_R_W - shra_r.w $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRLV_PH (2754) - MIPS_INS_SHRLV_PH - shrlv.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRLV_PH_MMR2 (2755) - MIPS_INS_SHRLV_PH - shrlv.ph $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRLV_QB (2756) - MIPS_INS_SHRLV_QB - shrlv.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRLV_QB_MM (2757) - MIPS_INS_SHRLV_QB - shrlv.qb $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRL_PH (2758) - MIPS_INS_SHRL_PH - shrl.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRL_PH_MMR2 (2759) - MIPS_INS_SHRL_PH - shrl.ph $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRL_QB (2760) - MIPS_INS_SHRL_QB - shrl.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRL_QB_MM (2761) - MIPS_INS_SHRL_QB - shrl.qb $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHXS_NM (2762) - MIPS_INS_SHXS - shxs $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SHX_NM (2763) - MIPS_INS_SHX - shx $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SH_MM (2764) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SH_MMR6 (2765) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SH_NM (2766) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SHs9_NM (2767) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SIGRIE (2768) - MIPS_INS_SIGRIE - sigrie $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SIGRIE_MMR6 (2769) - MIPS_INS_SIGRIE - sigrie $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SIGRIE_NM (2770) - MIPS_INS_SIGRIE - sigrie $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLDI_B (2771) - MIPS_INS_SLDI_B - sldi.b $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SLDI_D (2772) - MIPS_INS_SLDI_D - sldi.d $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SLDI_H (2773) - MIPS_INS_SLDI_H - sldi.h $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SLDI_W (2774) - MIPS_INS_SLDI_W - sldi.w $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SLD_B (2775) - MIPS_INS_SLD_B - sld.b $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLD_D (2776) - MIPS_INS_SLD_D - sld.d $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLD_H (2777) - MIPS_INS_SLD_H - sld.h $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLD_W (2778) - MIPS_INS_SLD_W - sld.w $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLL (2779) - MIPS_INS_SLL - sll $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SLL16_MM (2780) - MIPS_INS_SLL16 - sll16 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SLL16_MMR6 (2781) - MIPS_INS_SLL16 - sll16 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SLL16_NM (2782) - MIPS_INS_SLL - sll $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{{{ /* MIPS_SLL64_32 (2783) - MIPS_INS_INVALID - sll $rd, $rt, 0 */ + 0 +}}}, +{{{ /* MIPS_SLL64_64 (2784) - MIPS_INS_INVALID - sll $rd, $rt, 0 */ + 0 +}}}, +{ /* MIPS_SLLI_B (2785) - MIPS_INS_SLLI_B - slli.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SLLI_D (2786) - MIPS_INS_SLLI_D - slli.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SLLI_H (2787) - MIPS_INS_SLLI_H - slli.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SLLI_W (2788) - MIPS_INS_SLLI_W - slli.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SLLV (2789) - MIPS_INS_SLLV - sllv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SLLV_MM (2790) - MIPS_INS_SLLV - sllv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SLLV_NM (2791) - MIPS_INS_SLLV - sllv $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLL_B (2792) - MIPS_INS_SLL_B - sll.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SLL_D (2793) - MIPS_INS_SLL_D - sll.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SLL_H (2794) - MIPS_INS_SLL_H - sll.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SLL_MM (2795) - MIPS_INS_SLL - sll $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SLL_MMR6 (2796) - MIPS_INS_SLL - sll $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SLL_NM (2797) - MIPS_INS_SLL - sll $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLL_W (2798) - MIPS_INS_SLL_W - sll.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SLT (2799) - MIPS_INS_SLT - slt $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_SLT64 (2800) - MIPS_INS_INVALID - slt $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_SLTIU_NM (2801) - MIPS_INS_SLTIU - sltiu $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLTI_NM (2802) - MIPS_INS_SLTI - slti $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLTU_NM (2803) - MIPS_INS_SLTU - sltu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLT_MM (2804) - MIPS_INS_SLT - slt $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLT_NM (2805) - MIPS_INS_SLT - slt $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLTi (2806) - MIPS_INS_SLTI - slti $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{{{ /* MIPS_SLTi64 (2807) - MIPS_INS_INVALID - slti $rt, $rs, $imm16 */ + 0 +}}}, +{ /* MIPS_SLTi_MM (2808) - MIPS_INS_SLTI - slti $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_SLTiu (2809) - MIPS_INS_SLTIU - sltiu $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{{{ /* MIPS_SLTiu64 (2810) - MIPS_INS_INVALID - sltiu $rt, $rs, $imm16 */ + 0 +}}}, +{ /* MIPS_SLTiu_MM (2811) - MIPS_INS_SLTIU - sltiu $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_SLTu (2812) - MIPS_INS_SLTU - sltu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_SLTu64 (2813) - MIPS_INS_INVALID - sltu $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_SLTu_MM (2814) - MIPS_INS_SLTU - sltu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SNE (2815) - MIPS_INS_SNE - sne $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SNEi (2816) - MIPS_INS_SNEI - snei $rt, $rs, $imm10 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm10 */ + { 0 } +}}, +{ /* MIPS_SOV_NM (2817) - MIPS_INS_SOV - sov $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SPLATI_B (2818) - MIPS_INS_SPLATI_B - splati.b $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SPLATI_D (2819) - MIPS_INS_SPLATI_D - splati.d $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SPLATI_H (2820) - MIPS_INS_SPLATI_H - splati.h $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SPLATI_W (2821) - MIPS_INS_SPLATI_W - splati.w $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SPLAT_B (2822) - MIPS_INS_SPLAT_B - splat.b $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SPLAT_D (2823) - MIPS_INS_SPLAT_D - splat.d $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SPLAT_H (2824) - MIPS_INS_SPLAT_H - splat.h $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SPLAT_W (2825) - MIPS_INS_SPLAT_W - splat.w $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SRA (2826) - MIPS_INS_SRA - sra $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SRAI_B (2827) - MIPS_INS_SRAI_B - srai.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRAI_D (2828) - MIPS_INS_SRAI_D - srai.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRAI_H (2829) - MIPS_INS_SRAI_H - srai.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRAI_W (2830) - MIPS_INS_SRAI_W - srai.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRARI_B (2831) - MIPS_INS_SRARI_B - srari.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRARI_D (2832) - MIPS_INS_SRARI_D - srari.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRARI_H (2833) - MIPS_INS_SRARI_H - srari.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRARI_W (2834) - MIPS_INS_SRARI_W - srari.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRAR_B (2835) - MIPS_INS_SRAR_B - srar.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRAR_D (2836) - MIPS_INS_SRAR_D - srar.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRAR_H (2837) - MIPS_INS_SRAR_H - srar.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRAR_W (2838) - MIPS_INS_SRAR_W - srar.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRAV (2839) - MIPS_INS_SRAV - srav $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SRAV_MM (2840) - MIPS_INS_SRAV - srav $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SRAV_NM (2841) - MIPS_INS_SRAV - srav $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SRA_B (2842) - MIPS_INS_SRA_B - sra.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRA_D (2843) - MIPS_INS_SRA_D - sra.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRA_H (2844) - MIPS_INS_SRA_H - sra.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRA_MM (2845) - MIPS_INS_SRA - sra $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SRA_NM (2846) - MIPS_INS_SRA - sra $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SRA_W (2847) - MIPS_INS_SRA_W - sra.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRL (2848) - MIPS_INS_SRL - srl $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SRL16_MM (2849) - MIPS_INS_SRL16 - srl16 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SRL16_MMR6 (2850) - MIPS_INS_SRL16 - srl16 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SRL16_NM (2851) - MIPS_INS_SRL - srl $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SRLI_B (2852) - MIPS_INS_SRLI_B - srli.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLI_D (2853) - MIPS_INS_SRLI_D - srli.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLI_H (2854) - MIPS_INS_SRLI_H - srli.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLI_W (2855) - MIPS_INS_SRLI_W - srli.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLRI_B (2856) - MIPS_INS_SRLRI_B - srlri.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLRI_D (2857) - MIPS_INS_SRLRI_D - srlri.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLRI_H (2858) - MIPS_INS_SRLRI_H - srlri.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLRI_W (2859) - MIPS_INS_SRLRI_W - srlri.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLR_B (2860) - MIPS_INS_SRLR_B - srlr.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRLR_D (2861) - MIPS_INS_SRLR_D - srlr.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRLR_H (2862) - MIPS_INS_SRLR_H - srlr.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRLR_W (2863) - MIPS_INS_SRLR_W - srlr.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRLV (2864) - MIPS_INS_SRLV - srlv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SRLV_MM (2865) - MIPS_INS_SRLV - srlv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SRLV_NM (2866) - MIPS_INS_SRLV - srlv $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SRL_B (2867) - MIPS_INS_SRL_B - srl.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRL_D (2868) - MIPS_INS_SRL_D - srl.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRL_H (2869) - MIPS_INS_SRL_H - srl.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRL_MM (2870) - MIPS_INS_SRL - srl $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SRL_NM (2871) - MIPS_INS_SRL - srl $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SRL_W (2872) - MIPS_INS_SRL_W - srl.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SSNOP (2873) - MIPS_INS_SSNOP - ssnop */ +{ + { 0 } +}}, +{ /* MIPS_SSNOP_MM (2874) - MIPS_INS_SSNOP - ssnop */ +{ + { 0 } +}}, +{ /* MIPS_SSNOP_MMR6 (2875) - MIPS_INS_SSNOP - ssnop */ +{ + { 0 } +}}, +{ /* MIPS_ST_B (2876) - MIPS_INS_ST_B - st.b $wd, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10 */ + { 0 } +}}, +{ /* MIPS_ST_D (2877) - MIPS_INS_ST_D - st.d $wd, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10_lsl3 */ + { 0 } +}}, +{ /* MIPS_ST_H (2878) - MIPS_INS_ST_H - st.h $wd, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10_lsl1 */ + { 0 } +}}, +{ /* MIPS_ST_W (2879) - MIPS_INS_ST_W - st.w $wd, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10_lsl2 */ + { 0 } +}}, +{ /* MIPS_SUB (2880) - MIPS_INS_SUB - sub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_PH (2881) - MIPS_INS_SUBQH_PH - subqh.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_PH_MMR2 (2882) - MIPS_INS_SUBQH_PH - subqh.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_R_PH (2883) - MIPS_INS_SUBQH_R_PH - subqh_r.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_R_PH_MMR2 (2884) - MIPS_INS_SUBQH_R_PH - subqh_r.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_R_W (2885) - MIPS_INS_SUBQH_R_W - subqh_r.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_R_W_MMR2 (2886) - MIPS_INS_SUBQH_R_W - subqh_r.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_W (2887) - MIPS_INS_SUBQH_W - subqh.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_W_MMR2 (2888) - MIPS_INS_SUBQH_W - subqh.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQ_PH (2889) - MIPS_INS_SUBQ_PH - subq.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQ_PH_MM (2890) - MIPS_INS_SUBQ_PH - subq.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQ_S_PH (2891) - MIPS_INS_SUBQ_S_PH - subq_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQ_S_PH_MM (2892) - MIPS_INS_SUBQ_S_PH - subq_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQ_S_W (2893) - MIPS_INS_SUBQ_S_W - subq_s.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQ_S_W_MM (2894) - MIPS_INS_SUBQ_S_W - subq_s.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBSUS_U_B (2895) - MIPS_INS_SUBSUS_U_B - subsus_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUS_U_D (2896) - MIPS_INS_SUBSUS_U_D - subsus_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUS_U_H (2897) - MIPS_INS_SUBSUS_U_H - subsus_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUS_U_W (2898) - MIPS_INS_SUBSUS_U_W - subsus_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUU_S_B (2899) - MIPS_INS_SUBSUU_S_B - subsuu_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUU_S_D (2900) - MIPS_INS_SUBSUU_S_D - subsuu_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUU_S_H (2901) - MIPS_INS_SUBSUU_S_H - subsuu_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUU_S_W (2902) - MIPS_INS_SUBSUU_S_W - subsuu_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_S_B (2903) - MIPS_INS_SUBS_S_B - subs_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_S_D (2904) - MIPS_INS_SUBS_S_D - subs_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_S_H (2905) - MIPS_INS_SUBS_S_H - subs_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_S_W (2906) - MIPS_INS_SUBS_S_W - subs_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_U_B (2907) - MIPS_INS_SUBS_U_B - subs_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_U_D (2908) - MIPS_INS_SUBS_U_D - subs_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_U_H (2909) - MIPS_INS_SUBS_U_H - subs_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_U_W (2910) - MIPS_INS_SUBS_U_W - subs_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBU16_MM (2911) - MIPS_INS_SUBU16 - subu16 $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU16_MMR6 (2912) - MIPS_INS_SUBU16 - subu16 $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBUH_QB (2913) - MIPS_INS_SUBUH_QB - subuh.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBUH_QB_MMR2 (2914) - MIPS_INS_SUBUH_QB - subuh.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBUH_R_QB (2915) - MIPS_INS_SUBUH_R_QB - subuh_r.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBUH_R_QB_MMR2 (2916) - MIPS_INS_SUBUH_R_QB - subuh_r.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_MMR6 (2917) - MIPS_INS_SUBU - subu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_PH (2918) - MIPS_INS_SUBU_PH - subu.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_PH_MMR2 (2919) - MIPS_INS_SUBU_PH - subu.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_QB (2920) - MIPS_INS_SUBU_QB - subu.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_QB_MM (2921) - MIPS_INS_SUBU_QB - subu.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_S_PH (2922) - MIPS_INS_SUBU_S_PH - subu_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_S_PH_MMR2 (2923) - MIPS_INS_SUBU_S_PH - subu_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_S_QB (2924) - MIPS_INS_SUBU_S_QB - subu_s.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_S_QB_MM (2925) - MIPS_INS_SUBU_S_QB - subu_s.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBVI_B (2926) - MIPS_INS_SUBVI_B - subvi.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SUBVI_D (2927) - MIPS_INS_SUBVI_D - subvi.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SUBVI_H (2928) - MIPS_INS_SUBVI_H - subvi.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SUBVI_W (2929) - MIPS_INS_SUBVI_W - subvi.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SUBV_B (2930) - MIPS_INS_SUBV_B - subv.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBV_D (2931) - MIPS_INS_SUBV_D - subv.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBV_H (2932) - MIPS_INS_SUBV_H - subv.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBV_W (2933) - MIPS_INS_SUBV_W - subv.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUB_MM (2934) - MIPS_INS_SUB - sub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUB_MMR6 (2935) - MIPS_INS_SUB - sub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUB_NM (2936) - MIPS_INS_SUB - sub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBu (2937) - MIPS_INS_SUBU - subu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBu16_NM (2938) - MIPS_INS_SUBU - subu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBu_MM (2939) - MIPS_INS_SUBU - subu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBu_NM (2940) - MIPS_INS_SUBU - subu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUXC1 (2941) - MIPS_INS_SUXC1 - suxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SUXC164 (2942) - MIPS_INS_SUXC1 - suxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SUXC1_MM (2943) - MIPS_INS_SUXC1 - suxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SW (2944) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SW16_MM (2945) - MIPS_INS_SW16 - sw16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_SW16_MMR6 (2946) - MIPS_INS_SW16 - sw16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_SW16_NM (2947) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SW4x4_NM (2948) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SW64 (2949) - MIPS_INS_INVALID - sw $rt, $addr */ + 0 +}}}, +{ /* MIPS_SWC1 (2950) - MIPS_INS_SWC1 - swc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWC1_MM (2951) - MIPS_INS_SWC1 - swc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWC2 (2952) - MIPS_INS_SWC2 - swc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWC2_MMR6 (2953) - MIPS_INS_SWC2 - swc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_SWC2_R6 (2954) - MIPS_INS_SWC2 - swc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_SWC3 (2955) - MIPS_INS_SWC3 - swc3 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWDSP (2956) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWDSP_MM (2957) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWE (2958) - MIPS_INS_SWE - swe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SWE_MM (2959) - MIPS_INS_SWE - swe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SWGP16_NM (2960) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWGP_NM (2961) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWL (2962) - MIPS_INS_SWL - swl $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SWL64 (2963) - MIPS_INS_INVALID - swl $rt, $addr */ + 0 +}}}, +{ /* MIPS_SWLE (2964) - MIPS_INS_SWLE - swle $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SWLE_MM (2965) - MIPS_INS_SWLE - swle $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SWL_MM (2966) - MIPS_INS_SWL - swl $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_SWM16_MM (2967) - MIPS_INS_SWM16 - swm16 $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - uimm8 */ + { 0 } +}}, +{ /* MIPS_SWM16_MMR6 (2968) - MIPS_INS_SWM16 - swm16 $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - uimm8 */ + { 0 } +}}, +{ /* MIPS_SWM32_MM (2969) - MIPS_INS_SWM32 - swm32 $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_SWM_NM (2970) - MIPS_INS_SWM - swm $rt, $addr, $rcount */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rcount */ + { 0 } +}}, +{ /* MIPS_SWPC_NM (2971) - MIPS_INS_SWPC - swpc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_SWP_MM (2972) - MIPS_INS_SWP - swp $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_SWR (2973) - MIPS_INS_SWR - swr $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SWR64 (2974) - MIPS_INS_INVALID - swr $rt, $addr */ + 0 +}}}, +{ /* MIPS_SWRE (2975) - MIPS_INS_SWRE - swre $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SWRE_MM (2976) - MIPS_INS_SWRE - swre $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SWR_MM (2977) - MIPS_INS_SWR - swr $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_SWSP16_NM (2978) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWSP_MM (2979) - MIPS_INS_SWSP - swsp $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* offset - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - simm5 */ + { 0 } +}}, +{ /* MIPS_SWSP_MMR6 (2980) - MIPS_INS_SW - sw $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* offset - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - simm5 */ + { 0 } +}}, +{ /* MIPS_SWXC1 (2981) - MIPS_INS_SWXC1 - swxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SWXC1_MM (2982) - MIPS_INS_SWXC1 - swxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SWXS_NM (2983) - MIPS_INS_SWXS - swxs $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWX_NM (2984) - MIPS_INS_SWX - swx $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SW_MM (2985) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SW_MMR6 (2986) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SW_NM (2987) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWs9_NM (2988) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SYNC (2989) - MIPS_INS_SYNC - sync $stype */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* stype */ + { 0 } +}}, +{ /* MIPS_SYNCI (2990) - MIPS_INS_SYNCI - synci $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SYNCI_MM (2991) - MIPS_INS_SYNCI - synci $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SYNCI_MMR6 (2992) - MIPS_INS_SYNCI - synci $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SYNCI_NM (2993) - MIPS_INS_SYNCI - synci $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SYNCIs9_NM (2994) - MIPS_INS_SYNCI - synci $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SYNC_MM (2995) - MIPS_INS_SYNC - sync $stype */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* stype */ + { 0 } +}}, +{ /* MIPS_SYNC_MMR6 (2996) - MIPS_INS_SYNC - sync $stype */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* stype */ + { 0 } +}}, +{ /* MIPS_SYNC_NM (2997) - MIPS_INS_SYNC - sync $stype */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* stype */ + { 0 } +}}, +{ /* MIPS_SYSCALL (2998) - MIPS_INS_SYSCALL - syscall $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SYSCALL16_NM (2999) - MIPS_INS_SYSCALL - syscall $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SYSCALL_MM (3000) - MIPS_INS_SYSCALL - syscall $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SYSCALL_NM (3001) - MIPS_INS_SYSCALL - syscall $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{{{ /* MIPS_Save16 (3002) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SaveX16 (3003) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SbRxRyOffMemX16 (3004) - MIPS_INS_SB - sb $ry, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - CPU16Regs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SebRx16 (3005) - MIPS_INS_SEB - seb $rx */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx_ */ + { 0 } +}}, +{ /* MIPS_SehRx16 (3006) - MIPS_INS_SEH - seh $rx */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx_ */ + { 0 } +}}, +{ /* MIPS_ShRxRyOffMemX16 (3007) - MIPS_INS_SH - sh $ry, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - CPU16Regs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SllX16 (3008) - MIPS_INS_SLL - sll $rx, $ry, $sa6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa6 */ + { 0 } +}}, +{ /* MIPS_SllvRxRy16 (3009) - MIPS_INS_SLLV - sllv $rz, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_SltRxRy16 (3010) - MIPS_INS_SLT - slt $rx, $ry */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_SltiRxImm16 (3011) - MIPS_INS_SLTI - slti $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_SltiRxImmX16 (3012) - MIPS_INS_SLTI - slti $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_SltiuRxImm16 (3013) - MIPS_INS_SLTIU - sltiu $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_SltiuRxImmX16 (3014) - MIPS_INS_SLTIU - sltiu $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_SltuRxRy16 (3015) - MIPS_INS_SLTU - sltu $rx, $ry */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_SraX16 (3016) - MIPS_INS_SRA - sra $rx, $ry, $sa6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa6 */ + { 0 } +}}, +{ /* MIPS_SravRxRy16 (3017) - MIPS_INS_SRAV - srav $rz, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_SrlX16 (3018) - MIPS_INS_SRL - srl $rx, $ry, $sa6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa6 */ + { 0 } +}}, +{ /* MIPS_SrlvRxRy16 (3019) - MIPS_INS_SRLV - srlv $rz, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_SubuRxRyRz16 (3020) - MIPS_INS_SUBU - subu $rz, $rx, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_SwRxRyOffMemX16 (3021) - MIPS_INS_SW - sw $ry, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - CPU16Regs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SwRxSpImmX16 (3022) - MIPS_INS_SW - sw $ry, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - CPU16RegsPlusSP */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_TEQ (3023) - MIPS_INS_TEQ - teq $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TEQI (3024) - MIPS_INS_TEQI - teqi $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TEQI_MM (3025) - MIPS_INS_TEQI - teqi $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TEQ_MM (3026) - MIPS_INS_TEQ - teq $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TEQ_NM (3027) - MIPS_INS_TEQ - teq $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_TGE (3028) - MIPS_INS_TGE - tge $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TGEI (3029) - MIPS_INS_TGEI - tgei $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TGEIU (3030) - MIPS_INS_TGEIU - tgeiu $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TGEIU_MM (3031) - MIPS_INS_TGEIU - tgeiu $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TGEI_MM (3032) - MIPS_INS_TGEI - tgei $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TGEU (3033) - MIPS_INS_TGEU - tgeu $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TGEU_MM (3034) - MIPS_INS_TGEU - tgeu $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TGE_MM (3035) - MIPS_INS_TGE - tge $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TLBGINV (3036) - MIPS_INS_TLBGINV - tlbginv */ +{ + { 0 } +}}, +{ /* MIPS_TLBGINVF (3037) - MIPS_INS_TLBGINVF - tlbginvf */ +{ + { 0 } +}}, +{ /* MIPS_TLBGINVF_MM (3038) - MIPS_INS_TLBGINVF - tlbginvf */ +{ + { 0 } +}}, +{ /* MIPS_TLBGINV_MM (3039) - MIPS_INS_TLBGINV - tlbginv */ +{ + { 0 } +}}, +{ /* MIPS_TLBGP (3040) - MIPS_INS_TLBGP - tlbgp */ +{ + { 0 } +}}, +{ /* MIPS_TLBGP_MM (3041) - MIPS_INS_TLBGP - tlbgp */ +{ + { 0 } +}}, +{ /* MIPS_TLBGR (3042) - MIPS_INS_TLBGR - tlbgr */ +{ + { 0 } +}}, +{ /* MIPS_TLBGR_MM (3043) - MIPS_INS_TLBGR - tlbgr */ +{ + { 0 } +}}, +{ /* MIPS_TLBGWI (3044) - MIPS_INS_TLBGWI - tlbgwi */ +{ + { 0 } +}}, +{ /* MIPS_TLBGWI_MM (3045) - MIPS_INS_TLBGWI - tlbgwi */ +{ + { 0 } +}}, +{ /* MIPS_TLBGWR (3046) - MIPS_INS_TLBGWR - tlbgwr */ +{ + { 0 } +}}, +{ /* MIPS_TLBGWR_MM (3047) - MIPS_INS_TLBGWR - tlbgwr */ +{ + { 0 } +}}, +{ /* MIPS_TLBINV (3048) - MIPS_INS_TLBINV - tlbinv */ +{ + { 0 } +}}, +{ /* MIPS_TLBINVF (3049) - MIPS_INS_TLBINVF - tlbinvf */ +{ + { 0 } +}}, +{ /* MIPS_TLBINVF_MMR6 (3050) - MIPS_INS_TLBINVF - tlbinvf */ +{ + { 0 } +}}, +{ /* MIPS_TLBINVF_NM (3051) - MIPS_INS_TLBINVF - tlbinvf */ +{ + { 0 } +}}, +{ /* MIPS_TLBINV_MMR6 (3052) - MIPS_INS_TLBINV - tlbinv */ +{ + { 0 } +}}, +{ /* MIPS_TLBINV_NM (3053) - MIPS_INS_TLBINV - tlbinv */ +{ + { 0 } +}}, +{ /* MIPS_TLBP (3054) - MIPS_INS_TLBP - tlbp */ +{ + { 0 } +}}, +{ /* MIPS_TLBP_MM (3055) - MIPS_INS_TLBP - tlbp */ +{ + { 0 } +}}, +{ /* MIPS_TLBP_NM (3056) - MIPS_INS_TLBP - tlbp */ +{ + { 0 } +}}, +{ /* MIPS_TLBR (3057) - MIPS_INS_TLBR - tlbr */ +{ + { 0 } +}}, +{ /* MIPS_TLBR_MM (3058) - MIPS_INS_TLBR - tlbr */ +{ + { 0 } +}}, +{ /* MIPS_TLBR_NM (3059) - MIPS_INS_TLBR - tlbr */ +{ + { 0 } +}}, +{ /* MIPS_TLBWI (3060) - MIPS_INS_TLBWI - tlbwi */ +{ + { 0 } +}}, +{ /* MIPS_TLBWI_MM (3061) - MIPS_INS_TLBWI - tlbwi */ +{ + { 0 } +}}, +{ /* MIPS_TLBWI_NM (3062) - MIPS_INS_TLBWI - tlbwi */ +{ + { 0 } +}}, +{ /* MIPS_TLBWR (3063) - MIPS_INS_TLBWR - tlbwr */ +{ + { 0 } +}}, +{ /* MIPS_TLBWR_MM (3064) - MIPS_INS_TLBWR - tlbwr */ +{ + { 0 } +}}, +{ /* MIPS_TLBWR_NM (3065) - MIPS_INS_TLBWR - tlbwr */ +{ + { 0 } +}}, +{ /* MIPS_TLT (3066) - MIPS_INS_TLT - tlt $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TLTI (3067) - MIPS_INS_TLTI - tlti $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TLTIU_MM (3068) - MIPS_INS_TLTIU - tltiu $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TLTI_MM (3069) - MIPS_INS_TLTI - tlti $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TLTU (3070) - MIPS_INS_TLTU - tltu $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TLTU_MM (3071) - MIPS_INS_TLTU - tltu $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TLT_MM (3072) - MIPS_INS_TLT - tlt $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TNE (3073) - MIPS_INS_TNE - tne $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TNEI (3074) - MIPS_INS_TNEI - tnei $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TNEI_MM (3075) - MIPS_INS_TNEI - tnei $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TNE_MM (3076) - MIPS_INS_TNE - tne $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TNE_NM (3077) - MIPS_INS_TNE - tne $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_TRUNC_L_D64 (3078) - MIPS_INS_TRUNC_L_D - trunc.l.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_L_D_MMR6 (3079) - MIPS_INS_TRUNC_L_D - trunc.l.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_L_S (3080) - MIPS_INS_TRUNC_L_S - trunc.l.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_L_S_MMR6 (3081) - MIPS_INS_TRUNC_L_S - trunc.l.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_D32 (3082) - MIPS_INS_TRUNC_W_D - trunc.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_D64 (3083) - MIPS_INS_TRUNC_W_D - trunc.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_D_MMR6 (3084) - MIPS_INS_TRUNC_W_D - trunc.w.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_MM (3085) - MIPS_INS_TRUNC_W_D - trunc.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_S (3086) - MIPS_INS_TRUNC_W_S - trunc.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_S_MM (3087) - MIPS_INS_TRUNC_W_S - trunc.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_S_MMR6 (3088) - MIPS_INS_TRUNC_W_S - trunc.w.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TTLTIU (3089) - MIPS_INS_TLTIU - tltiu $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_UALH_NM (3090) - MIPS_INS_UALH - ualh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_UALWM_NM (3091) - MIPS_INS_UALWM - ualwm $rt, $addr, $rcount */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rcount */ + { 0 } +}}, +{ /* MIPS_UALW_NM (3092) - MIPS_INS_UALW - ualw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_UASH_NM (3093) - MIPS_INS_UASH - uash $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_UASWM_NM (3094) - MIPS_INS_UASWM - uaswm $rt, $addr, $rcount */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rcount */ + { 0 } +}}, +{ /* MIPS_UASW_NM (3095) - MIPS_INS_UASW - uasw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_UDIV (3096) - MIPS_INS_DIVU - divu $$zero, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_UDIV_MM (3097) - MIPS_INS_DIVU - divu $$zero, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_V3MULU (3098) - MIPS_INS_V3MULU - v3mulu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_VMM0 (3099) - MIPS_INS_VMM0 - vmm0 $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_VMULU (3100) - MIPS_INS_VMULU - vmulu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_VSHF_B (3101) - MIPS_INS_VSHF_B - vshf.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_VSHF_D (3102) - MIPS_INS_VSHF_D - vshf.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_VSHF_H (3103) - MIPS_INS_VSHF_H - vshf.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_VSHF_W (3104) - MIPS_INS_VSHF_W - vshf.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_WAIT (3105) - MIPS_INS_WAIT - wait */ +{ + { 0 } +}}, +{ /* MIPS_WAIT_MM (3106) - MIPS_INS_WAIT - wait $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_WAIT_MMR6 (3107) - MIPS_INS_WAIT - wait $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_WAIT_NM (3108) - MIPS_INS_WAIT - wait $cd */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cd */ + { 0 } +}}, +{ /* MIPS_WRDSP (3109) - MIPS_INS_WRDSP - wrdsp $rs, $mask */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { 0 } +}}, +{ /* MIPS_WRDSP_MM (3110) - MIPS_INS_WRDSP - wrdsp $rt, $mask */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { 0 } +}}, +{ /* MIPS_WRPGPR_MMR6 (3111) - MIPS_INS_WRPGPR - wrpgpr $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_WRPGPR_NM (3112) - MIPS_INS_WRPGPR - wrpgpr $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_WSBH (3113) - MIPS_INS_WSBH - wsbh $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_WSBH_MM (3114) - MIPS_INS_WSBH - wsbh $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_WSBH_MMR6 (3115) - MIPS_INS_WSBH - wsbh $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_XOR (3116) - MIPS_INS_XOR - xor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_XOR16_MM (3117) - MIPS_INS_XOR16 - xor16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_XOR16_MMR6 (3118) - MIPS_INS_XOR16 - xor16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_XOR16_NM (3119) - MIPS_INS_XOR - xor $dst, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_XOR64 (3120) - MIPS_INS_INVALID - xor $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_XORI_B (3121) - MIPS_INS_XORI_B - xori.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_XORI_MMR6 (3122) - MIPS_INS_XORI - xori $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_XORI_NM (3123) - MIPS_INS_XORI - xori $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_XOR_MM (3124) - MIPS_INS_XOR - xor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_XOR_MMR6 (3125) - MIPS_INS_XOR - xor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_XOR_NM (3126) - MIPS_INS_XOR - xor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_XOR_V (3127) - MIPS_INS_XOR_V - xor.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_XORi (3128) - MIPS_INS_XORI - xori $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{{{ /* MIPS_XORi64 (3129) - MIPS_INS_INVALID - xori $rt, $rs, $imm16 */ + 0 +}}}, +{ /* MIPS_XORi_MM (3130) - MIPS_INS_XORI - xori $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_XorRxRxRy16 (3131) - MIPS_INS_XOR - xor $rz, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_YIELD (3132) - MIPS_INS_YIELD - yield $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_YIELD_NM (3133) - MIPS_INS_YIELD - yield $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, diff --git a/arch/Mips/MipsGenCSOpGroup.inc b/arch/Mips/MipsGenCSOpGroup.inc new file mode 100644 index 000000000..7e991ab53 --- /dev/null +++ b/arch/Mips/MipsGenCSOpGroup.inc @@ -0,0 +1,45 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + Mips_OP_GROUP_Operand = 0, + Mips_OP_GROUP_BranchOperand = 1, + Mips_OP_GROUP_UImm_1_0 = 2, + Mips_OP_GROUP_UImm_2_0 = 3, + Mips_OP_GROUP_JumpOperand = 4, + Mips_OP_GROUP_MemOperand = 5, + Mips_OP_GROUP_RegisterList = 6, + Mips_OP_GROUP_UImm_3_0 = 7, + Mips_OP_GROUP_PCRel = 8, + Mips_OP_GROUP_UImm_32_0 = 9, + Mips_OP_GROUP_UImm_16_0 = 10, + Mips_OP_GROUP_UImm_8_0 = 11, + Mips_OP_GROUP_UImm_5_0 = 12, + Mips_OP_GROUP_Hi20PCRel = 13, + Mips_OP_GROUP_MemOperandEA = 14, + Mips_OP_GROUP_UImm_6_0 = 15, + Mips_OP_GROUP_UImm_4_0 = 16, + Mips_OP_GROUP_UImm_7_0 = 17, + Mips_OP_GROUP_UImm_10_0 = 18, + Mips_OP_GROUP_UImm_6_1 = 19, + Mips_OP_GROUP_UImm_5_1 = 20, + Mips_OP_GROUP_UImm_5_33 = 21, + Mips_OP_GROUP_UImm_5_32 = 22, + Mips_OP_GROUP_UImm_6_2 = 23, + Mips_OP_GROUP_UImm_2_1 = 24, + Mips_OP_GROUP_FCCOperand = 25, + Mips_OP_GROUP_UImm_0_0 = 26, + Mips_OP_GROUP_UImm_26_0 = 27, + Mips_OP_GROUP_Hi20 = 28, + Mips_OP_GROUP_NanoMipsRegisterList = 29, + Mips_OP_GROUP_UImm_12_0 = 30, + Mips_OP_GROUP_UImm_20_0 = 31, diff --git a/arch/Mips/MipsGenCSRegEnum.inc b/arch/Mips/MipsGenCSRegEnum.inc new file mode 100644 index 000000000..90d2ca390 --- /dev/null +++ b/arch/Mips/MipsGenCSRegEnum.inc @@ -0,0 +1,649 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + MIPS_REG_INVALID = 0, + MIPS_REG_AT = 1, + MIPS_REG_AT_NM = 2, + MIPS_REG_DSPCCOND = 3, + MIPS_REG_DSPCARRY = 4, + MIPS_REG_DSPEFI = 5, + MIPS_REG_DSPOUTFLAG = 6, + MIPS_REG_DSPPOS = 7, + MIPS_REG_DSPSCOUNT = 8, + MIPS_REG_FP = 9, + MIPS_REG_FP_NM = 10, + MIPS_REG_GP = 11, + MIPS_REG_GP_NM = 12, + MIPS_REG_MSAACCESS = 13, + MIPS_REG_MSACSR = 14, + MIPS_REG_MSAIR = 15, + MIPS_REG_MSAMAP = 16, + MIPS_REG_MSAMODIFY = 17, + MIPS_REG_MSAREQUEST = 18, + MIPS_REG_MSASAVE = 19, + MIPS_REG_MSAUNMAP = 20, + MIPS_REG_PC = 21, + MIPS_REG_RA = 22, + MIPS_REG_RA_NM = 23, + MIPS_REG_SP = 24, + MIPS_REG_SP_NM = 25, + MIPS_REG_ZERO = 26, + MIPS_REG_ZERO_NM = 27, + MIPS_REG_A0 = 28, + MIPS_REG_A1 = 29, + MIPS_REG_A2 = 30, + MIPS_REG_A3 = 31, + MIPS_REG_AC0 = 32, + MIPS_REG_AC1 = 33, + MIPS_REG_AC2 = 34, + MIPS_REG_AC3 = 35, + MIPS_REG_AT_64 = 36, + MIPS_REG_COP00 = 37, + MIPS_REG_COP01 = 38, + MIPS_REG_COP02 = 39, + MIPS_REG_COP03 = 40, + MIPS_REG_COP04 = 41, + MIPS_REG_COP05 = 42, + MIPS_REG_COP06 = 43, + MIPS_REG_COP07 = 44, + MIPS_REG_COP08 = 45, + MIPS_REG_COP09 = 46, + MIPS_REG_COP20 = 47, + MIPS_REG_COP21 = 48, + MIPS_REG_COP22 = 49, + MIPS_REG_COP23 = 50, + MIPS_REG_COP24 = 51, + MIPS_REG_COP25 = 52, + MIPS_REG_COP26 = 53, + MIPS_REG_COP27 = 54, + MIPS_REG_COP28 = 55, + MIPS_REG_COP29 = 56, + MIPS_REG_COP30 = 57, + MIPS_REG_COP31 = 58, + MIPS_REG_COP32 = 59, + MIPS_REG_COP33 = 60, + MIPS_REG_COP34 = 61, + MIPS_REG_COP35 = 62, + MIPS_REG_COP36 = 63, + MIPS_REG_COP37 = 64, + MIPS_REG_COP38 = 65, + MIPS_REG_COP39 = 66, + MIPS_REG_COP010 = 67, + MIPS_REG_COP011 = 68, + MIPS_REG_COP012 = 69, + MIPS_REG_COP013 = 70, + MIPS_REG_COP014 = 71, + MIPS_REG_COP015 = 72, + MIPS_REG_COP016 = 73, + MIPS_REG_COP017 = 74, + MIPS_REG_COP018 = 75, + MIPS_REG_COP019 = 76, + MIPS_REG_COP020 = 77, + MIPS_REG_COP021 = 78, + MIPS_REG_COP022 = 79, + MIPS_REG_COP023 = 80, + MIPS_REG_COP024 = 81, + MIPS_REG_COP025 = 82, + MIPS_REG_COP026 = 83, + MIPS_REG_COP027 = 84, + MIPS_REG_COP028 = 85, + MIPS_REG_COP029 = 86, + MIPS_REG_COP030 = 87, + MIPS_REG_COP031 = 88, + MIPS_REG_COP210 = 89, + MIPS_REG_COP211 = 90, + MIPS_REG_COP212 = 91, + MIPS_REG_COP213 = 92, + MIPS_REG_COP214 = 93, + MIPS_REG_COP215 = 94, + MIPS_REG_COP216 = 95, + MIPS_REG_COP217 = 96, + MIPS_REG_COP218 = 97, + MIPS_REG_COP219 = 98, + MIPS_REG_COP220 = 99, + MIPS_REG_COP221 = 100, + MIPS_REG_COP222 = 101, + MIPS_REG_COP223 = 102, + MIPS_REG_COP224 = 103, + MIPS_REG_COP225 = 104, + MIPS_REG_COP226 = 105, + MIPS_REG_COP227 = 106, + MIPS_REG_COP228 = 107, + MIPS_REG_COP229 = 108, + MIPS_REG_COP230 = 109, + MIPS_REG_COP231 = 110, + MIPS_REG_COP310 = 111, + MIPS_REG_COP311 = 112, + MIPS_REG_COP312 = 113, + MIPS_REG_COP313 = 114, + MIPS_REG_COP314 = 115, + MIPS_REG_COP315 = 116, + MIPS_REG_COP316 = 117, + MIPS_REG_COP317 = 118, + MIPS_REG_COP318 = 119, + MIPS_REG_COP319 = 120, + MIPS_REG_COP320 = 121, + MIPS_REG_COP321 = 122, + MIPS_REG_COP322 = 123, + MIPS_REG_COP323 = 124, + MIPS_REG_COP324 = 125, + MIPS_REG_COP325 = 126, + MIPS_REG_COP326 = 127, + MIPS_REG_COP327 = 128, + MIPS_REG_COP328 = 129, + MIPS_REG_COP329 = 130, + MIPS_REG_COP330 = 131, + MIPS_REG_COP331 = 132, + MIPS_REG_D0 = 133, + MIPS_REG_D1 = 134, + MIPS_REG_D2 = 135, + MIPS_REG_D3 = 136, + MIPS_REG_D4 = 137, + MIPS_REG_D5 = 138, + MIPS_REG_D6 = 139, + MIPS_REG_D7 = 140, + MIPS_REG_D8 = 141, + MIPS_REG_D9 = 142, + MIPS_REG_D10 = 143, + MIPS_REG_D11 = 144, + MIPS_REG_D12 = 145, + MIPS_REG_D13 = 146, + MIPS_REG_D14 = 147, + MIPS_REG_D15 = 148, + MIPS_REG_DSPOUTFLAG20 = 149, + MIPS_REG_DSPOUTFLAG21 = 150, + MIPS_REG_DSPOUTFLAG22 = 151, + MIPS_REG_DSPOUTFLAG23 = 152, + MIPS_REG_F0 = 153, + MIPS_REG_F1 = 154, + MIPS_REG_F2 = 155, + MIPS_REG_F3 = 156, + MIPS_REG_F4 = 157, + MIPS_REG_F5 = 158, + MIPS_REG_F6 = 159, + MIPS_REG_F7 = 160, + MIPS_REG_F8 = 161, + MIPS_REG_F9 = 162, + MIPS_REG_F10 = 163, + MIPS_REG_F11 = 164, + MIPS_REG_F12 = 165, + MIPS_REG_F13 = 166, + MIPS_REG_F14 = 167, + MIPS_REG_F15 = 168, + MIPS_REG_F16 = 169, + MIPS_REG_F17 = 170, + MIPS_REG_F18 = 171, + MIPS_REG_F19 = 172, + MIPS_REG_F20 = 173, + MIPS_REG_F21 = 174, + MIPS_REG_F22 = 175, + MIPS_REG_F23 = 176, + MIPS_REG_F24 = 177, + MIPS_REG_F25 = 178, + MIPS_REG_F26 = 179, + MIPS_REG_F27 = 180, + MIPS_REG_F28 = 181, + MIPS_REG_F29 = 182, + MIPS_REG_F30 = 183, + MIPS_REG_F31 = 184, + MIPS_REG_FCC0 = 185, + MIPS_REG_FCC1 = 186, + MIPS_REG_FCC2 = 187, + MIPS_REG_FCC3 = 188, + MIPS_REG_FCC4 = 189, + MIPS_REG_FCC5 = 190, + MIPS_REG_FCC6 = 191, + MIPS_REG_FCC7 = 192, + MIPS_REG_FCR0 = 193, + MIPS_REG_FCR1 = 194, + MIPS_REG_FCR2 = 195, + MIPS_REG_FCR3 = 196, + MIPS_REG_FCR4 = 197, + MIPS_REG_FCR5 = 198, + MIPS_REG_FCR6 = 199, + MIPS_REG_FCR7 = 200, + MIPS_REG_FCR8 = 201, + MIPS_REG_FCR9 = 202, + MIPS_REG_FCR10 = 203, + MIPS_REG_FCR11 = 204, + MIPS_REG_FCR12 = 205, + MIPS_REG_FCR13 = 206, + MIPS_REG_FCR14 = 207, + MIPS_REG_FCR15 = 208, + MIPS_REG_FCR16 = 209, + MIPS_REG_FCR17 = 210, + MIPS_REG_FCR18 = 211, + MIPS_REG_FCR19 = 212, + MIPS_REG_FCR20 = 213, + MIPS_REG_FCR21 = 214, + MIPS_REG_FCR22 = 215, + MIPS_REG_FCR23 = 216, + MIPS_REG_FCR24 = 217, + MIPS_REG_FCR25 = 218, + MIPS_REG_FCR26 = 219, + MIPS_REG_FCR27 = 220, + MIPS_REG_FCR28 = 221, + MIPS_REG_FCR29 = 222, + MIPS_REG_FCR30 = 223, + MIPS_REG_FCR31 = 224, + MIPS_REG_FP_64 = 225, + MIPS_REG_F_HI0 = 226, + MIPS_REG_F_HI1 = 227, + MIPS_REG_F_HI2 = 228, + MIPS_REG_F_HI3 = 229, + MIPS_REG_F_HI4 = 230, + MIPS_REG_F_HI5 = 231, + MIPS_REG_F_HI6 = 232, + MIPS_REG_F_HI7 = 233, + MIPS_REG_F_HI8 = 234, + MIPS_REG_F_HI9 = 235, + MIPS_REG_F_HI10 = 236, + MIPS_REG_F_HI11 = 237, + MIPS_REG_F_HI12 = 238, + MIPS_REG_F_HI13 = 239, + MIPS_REG_F_HI14 = 240, + MIPS_REG_F_HI15 = 241, + MIPS_REG_F_HI16 = 242, + MIPS_REG_F_HI17 = 243, + MIPS_REG_F_HI18 = 244, + MIPS_REG_F_HI19 = 245, + MIPS_REG_F_HI20 = 246, + MIPS_REG_F_HI21 = 247, + MIPS_REG_F_HI22 = 248, + MIPS_REG_F_HI23 = 249, + MIPS_REG_F_HI24 = 250, + MIPS_REG_F_HI25 = 251, + MIPS_REG_F_HI26 = 252, + MIPS_REG_F_HI27 = 253, + MIPS_REG_F_HI28 = 254, + MIPS_REG_F_HI29 = 255, + MIPS_REG_F_HI30 = 256, + MIPS_REG_F_HI31 = 257, + MIPS_REG_GP_64 = 258, + MIPS_REG_HI0 = 259, + MIPS_REG_HI1 = 260, + MIPS_REG_HI2 = 261, + MIPS_REG_HI3 = 262, + MIPS_REG_HWR0 = 263, + MIPS_REG_HWR1 = 264, + MIPS_REG_HWR2 = 265, + MIPS_REG_HWR3 = 266, + MIPS_REG_HWR4 = 267, + MIPS_REG_HWR5 = 268, + MIPS_REG_HWR6 = 269, + MIPS_REG_HWR7 = 270, + MIPS_REG_HWR8 = 271, + MIPS_REG_HWR9 = 272, + MIPS_REG_HWR10 = 273, + MIPS_REG_HWR11 = 274, + MIPS_REG_HWR12 = 275, + MIPS_REG_HWR13 = 276, + MIPS_REG_HWR14 = 277, + MIPS_REG_HWR15 = 278, + MIPS_REG_HWR16 = 279, + MIPS_REG_HWR17 = 280, + MIPS_REG_HWR18 = 281, + MIPS_REG_HWR19 = 282, + MIPS_REG_HWR20 = 283, + MIPS_REG_HWR21 = 284, + MIPS_REG_HWR22 = 285, + MIPS_REG_HWR23 = 286, + MIPS_REG_HWR24 = 287, + MIPS_REG_HWR25 = 288, + MIPS_REG_HWR26 = 289, + MIPS_REG_HWR27 = 290, + MIPS_REG_HWR28 = 291, + MIPS_REG_HWR29 = 292, + MIPS_REG_HWR30 = 293, + MIPS_REG_HWR31 = 294, + MIPS_REG_K0 = 295, + MIPS_REG_K1 = 296, + MIPS_REG_LO0 = 297, + MIPS_REG_LO1 = 298, + MIPS_REG_LO2 = 299, + MIPS_REG_LO3 = 300, + MIPS_REG_MPL0 = 301, + MIPS_REG_MPL1 = 302, + MIPS_REG_MPL2 = 303, + MIPS_REG_MSA8 = 304, + MIPS_REG_MSA9 = 305, + MIPS_REG_MSA10 = 306, + MIPS_REG_MSA11 = 307, + MIPS_REG_MSA12 = 308, + MIPS_REG_MSA13 = 309, + MIPS_REG_MSA14 = 310, + MIPS_REG_MSA15 = 311, + MIPS_REG_MSA16 = 312, + MIPS_REG_MSA17 = 313, + MIPS_REG_MSA18 = 314, + MIPS_REG_MSA19 = 315, + MIPS_REG_MSA20 = 316, + MIPS_REG_MSA21 = 317, + MIPS_REG_MSA22 = 318, + MIPS_REG_MSA23 = 319, + MIPS_REG_MSA24 = 320, + MIPS_REG_MSA25 = 321, + MIPS_REG_MSA26 = 322, + MIPS_REG_MSA27 = 323, + MIPS_REG_MSA28 = 324, + MIPS_REG_MSA29 = 325, + MIPS_REG_MSA30 = 326, + MIPS_REG_MSA31 = 327, + MIPS_REG_P0 = 328, + MIPS_REG_P1 = 329, + MIPS_REG_P2 = 330, + MIPS_REG_RA_64 = 331, + MIPS_REG_S0 = 332, + MIPS_REG_S1 = 333, + MIPS_REG_S2 = 334, + MIPS_REG_S3 = 335, + MIPS_REG_S4 = 336, + MIPS_REG_S5 = 337, + MIPS_REG_S6 = 338, + MIPS_REG_S7 = 339, + MIPS_REG_SP_64 = 340, + MIPS_REG_T0 = 341, + MIPS_REG_T1 = 342, + MIPS_REG_T2 = 343, + MIPS_REG_T3 = 344, + MIPS_REG_T4 = 345, + MIPS_REG_T5 = 346, + MIPS_REG_T6 = 347, + MIPS_REG_T7 = 348, + MIPS_REG_T8 = 349, + MIPS_REG_T9 = 350, + MIPS_REG_V0 = 351, + MIPS_REG_V1 = 352, + MIPS_REG_W0 = 353, + MIPS_REG_W1 = 354, + MIPS_REG_W2 = 355, + MIPS_REG_W3 = 356, + MIPS_REG_W4 = 357, + MIPS_REG_W5 = 358, + MIPS_REG_W6 = 359, + MIPS_REG_W7 = 360, + MIPS_REG_W8 = 361, + MIPS_REG_W9 = 362, + MIPS_REG_W10 = 363, + MIPS_REG_W11 = 364, + MIPS_REG_W12 = 365, + MIPS_REG_W13 = 366, + MIPS_REG_W14 = 367, + MIPS_REG_W15 = 368, + MIPS_REG_W16 = 369, + MIPS_REG_W17 = 370, + MIPS_REG_W18 = 371, + MIPS_REG_W19 = 372, + MIPS_REG_W20 = 373, + MIPS_REG_W21 = 374, + MIPS_REG_W22 = 375, + MIPS_REG_W23 = 376, + MIPS_REG_W24 = 377, + MIPS_REG_W25 = 378, + MIPS_REG_W26 = 379, + MIPS_REG_W27 = 380, + MIPS_REG_W28 = 381, + MIPS_REG_W29 = 382, + MIPS_REG_W30 = 383, + MIPS_REG_W31 = 384, + MIPS_REG_ZERO_64 = 385, + MIPS_REG_A0_NM = 386, + MIPS_REG_A1_NM = 387, + MIPS_REG_A2_NM = 388, + MIPS_REG_A3_NM = 389, + MIPS_REG_A4_NM = 390, + MIPS_REG_A5_NM = 391, + MIPS_REG_A6_NM = 392, + MIPS_REG_A7_NM = 393, + MIPS_REG_COP0SEL_BADINST = 394, + MIPS_REG_COP0SEL_BADINSTRP = 395, + MIPS_REG_COP0SEL_BADINSTRX = 396, + MIPS_REG_COP0SEL_BADVADDR = 397, + MIPS_REG_COP0SEL_BEVVA = 398, + MIPS_REG_COP0SEL_CACHEERR = 399, + MIPS_REG_COP0SEL_CAUSE = 400, + MIPS_REG_COP0SEL_CDMMBASE = 401, + MIPS_REG_COP0SEL_CMGCRBASE = 402, + MIPS_REG_COP0SEL_COMPARE = 403, + MIPS_REG_COP0SEL_CONFIG = 404, + MIPS_REG_COP0SEL_CONTEXT = 405, + MIPS_REG_COP0SEL_CONTEXTCONFIG = 406, + MIPS_REG_COP0SEL_COUNT = 407, + MIPS_REG_COP0SEL_DDATAHI = 408, + MIPS_REG_COP0SEL_DDATALO = 409, + MIPS_REG_COP0SEL_DEBUG = 410, + MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411, + MIPS_REG_COP0SEL_DEPC = 412, + MIPS_REG_COP0SEL_DESAVE = 413, + MIPS_REG_COP0SEL_DTAGHI = 414, + MIPS_REG_COP0SEL_DTAGLO = 415, + MIPS_REG_COP0SEL_EBASE = 416, + MIPS_REG_COP0SEL_ENTRYHI = 417, + MIPS_REG_COP0SEL_EPC = 418, + MIPS_REG_COP0SEL_ERRCTL = 419, + MIPS_REG_COP0SEL_ERROREPC = 420, + MIPS_REG_COP0SEL_GLOBALNUMBER = 421, + MIPS_REG_COP0SEL_GTOFFSET = 422, + MIPS_REG_COP0SEL_HWRENA = 423, + MIPS_REG_COP0SEL_IDATAHI = 424, + MIPS_REG_COP0SEL_IDATALO = 425, + MIPS_REG_COP0SEL_INDEX = 426, + MIPS_REG_COP0SEL_INTCTL = 427, + MIPS_REG_COP0SEL_ITAGHI = 428, + MIPS_REG_COP0SEL_ITAGLO = 429, + MIPS_REG_COP0SEL_LLADDR = 430, + MIPS_REG_COP0SEL_MAAR = 431, + MIPS_REG_COP0SEL_MAARI = 432, + MIPS_REG_COP0SEL_MEMORYMAPID = 433, + MIPS_REG_COP0SEL_MVPCONTROL = 434, + MIPS_REG_COP0SEL_NESTEDEPC = 435, + MIPS_REG_COP0SEL_NESTEDEXC = 436, + MIPS_REG_COP0SEL_PAGEGRAIN = 437, + MIPS_REG_COP0SEL_PAGEMASK = 438, + MIPS_REG_COP0SEL_PRID = 439, + MIPS_REG_COP0SEL_PWBASE = 440, + MIPS_REG_COP0SEL_PWCTL = 441, + MIPS_REG_COP0SEL_PWFIELD = 442, + MIPS_REG_COP0SEL_PWSIZE = 443, + MIPS_REG_COP0SEL_RANDOM = 444, + MIPS_REG_COP0SEL_SRSCTL = 445, + MIPS_REG_COP0SEL_SRSMAP = 446, + MIPS_REG_COP0SEL_STATUS = 447, + MIPS_REG_COP0SEL_TCBIND = 448, + MIPS_REG_COP0SEL_TCCONTEXT = 449, + MIPS_REG_COP0SEL_TCHALT = 450, + MIPS_REG_COP0SEL_TCOPT = 451, + MIPS_REG_COP0SEL_TCRESTART = 452, + MIPS_REG_COP0SEL_TCSCHEDULE = 453, + MIPS_REG_COP0SEL_TCSCHEFBACK = 454, + MIPS_REG_COP0SEL_TCSTATUS = 455, + MIPS_REG_COP0SEL_TRACECONTROL = 456, + MIPS_REG_COP0SEL_TRACEDBPC = 457, + MIPS_REG_COP0SEL_TRACEIBPC = 458, + MIPS_REG_COP0SEL_USERLOCAL = 459, + MIPS_REG_COP0SEL_VIEW_IPL = 460, + MIPS_REG_COP0SEL_VIEW_RIPL = 461, + MIPS_REG_COP0SEL_VPCONTROL = 462, + MIPS_REG_COP0SEL_VPECONTROL = 463, + MIPS_REG_COP0SEL_VPEOPT = 464, + MIPS_REG_COP0SEL_VPESCHEDULE = 465, + MIPS_REG_COP0SEL_VPESCHEFBACK = 466, + MIPS_REG_COP0SEL_WIRED = 467, + MIPS_REG_COP0SEL_XCONTEXT = 468, + MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469, + MIPS_REG_COP0SEL_YQMASK = 470, + MIPS_REG_K0_NM = 471, + MIPS_REG_K1_NM = 472, + MIPS_REG_S0_NM = 473, + MIPS_REG_S1_NM = 474, + MIPS_REG_S2_NM = 475, + MIPS_REG_S3_NM = 476, + MIPS_REG_S4_NM = 477, + MIPS_REG_S5_NM = 478, + MIPS_REG_S6_NM = 479, + MIPS_REG_S7_NM = 480, + MIPS_REG_T0_NM = 481, + MIPS_REG_T1_NM = 482, + MIPS_REG_T2_NM = 483, + MIPS_REG_T3_NM = 484, + MIPS_REG_T4_NM = 485, + MIPS_REG_T5_NM = 486, + MIPS_REG_T8_NM = 487, + MIPS_REG_T9_NM = 488, + MIPS_REG_A0_64 = 489, + MIPS_REG_A1_64 = 490, + MIPS_REG_A2_64 = 491, + MIPS_REG_A3_64 = 492, + MIPS_REG_AC0_64 = 493, + MIPS_REG_COP0SEL_CONFIG1 = 494, + MIPS_REG_COP0SEL_CONFIG2 = 495, + MIPS_REG_COP0SEL_CONFIG3 = 496, + MIPS_REG_COP0SEL_CONFIG4 = 497, + MIPS_REG_COP0SEL_CONFIG5 = 498, + MIPS_REG_COP0SEL_DEBUG2 = 499, + MIPS_REG_COP0SEL_ENTRYLO0 = 500, + MIPS_REG_COP0SEL_ENTRYLO1 = 501, + MIPS_REG_COP0SEL_GUESTCTL0 = 502, + MIPS_REG_COP0SEL_GUESTCTL1 = 503, + MIPS_REG_COP0SEL_GUESTCTL2 = 504, + MIPS_REG_COP0SEL_GUESTCTL3 = 505, + MIPS_REG_COP0SEL_KSCRATCH1 = 506, + MIPS_REG_COP0SEL_KSCRATCH2 = 507, + MIPS_REG_COP0SEL_KSCRATCH3 = 508, + MIPS_REG_COP0SEL_KSCRATCH4 = 509, + MIPS_REG_COP0SEL_KSCRATCH5 = 510, + MIPS_REG_COP0SEL_KSCRATCH6 = 511, + MIPS_REG_COP0SEL_MVPCONF0 = 512, + MIPS_REG_COP0SEL_MVPCONF1 = 513, + MIPS_REG_COP0SEL_PERFCNT0 = 514, + MIPS_REG_COP0SEL_PERFCNT1 = 515, + MIPS_REG_COP0SEL_PERFCNT2 = 516, + MIPS_REG_COP0SEL_PERFCNT3 = 517, + MIPS_REG_COP0SEL_PERFCNT4 = 518, + MIPS_REG_COP0SEL_PERFCNT5 = 519, + MIPS_REG_COP0SEL_PERFCNT6 = 520, + MIPS_REG_COP0SEL_PERFCNT7 = 521, + MIPS_REG_COP0SEL_PERFCTL0 = 522, + MIPS_REG_COP0SEL_PERFCTL1 = 523, + MIPS_REG_COP0SEL_PERFCTL2 = 524, + MIPS_REG_COP0SEL_PERFCTL3 = 525, + MIPS_REG_COP0SEL_PERFCTL4 = 526, + MIPS_REG_COP0SEL_PERFCTL5 = 527, + MIPS_REG_COP0SEL_PERFCTL6 = 528, + MIPS_REG_COP0SEL_PERFCTL7 = 529, + MIPS_REG_COP0SEL_SEGCTL0 = 530, + MIPS_REG_COP0SEL_SEGCTL1 = 531, + MIPS_REG_COP0SEL_SEGCTL2 = 532, + MIPS_REG_COP0SEL_SRSCONF0 = 533, + MIPS_REG_COP0SEL_SRSCONF1 = 534, + MIPS_REG_COP0SEL_SRSCONF2 = 535, + MIPS_REG_COP0SEL_SRSCONF3 = 536, + MIPS_REG_COP0SEL_SRSCONF4 = 537, + MIPS_REG_COP0SEL_SRSMAP2 = 538, + MIPS_REG_COP0SEL_TRACECONTROL2 = 539, + MIPS_REG_COP0SEL_TRACECONTROL3 = 540, + MIPS_REG_COP0SEL_USERTRACEDATA1 = 541, + MIPS_REG_COP0SEL_USERTRACEDATA2 = 542, + MIPS_REG_COP0SEL_VPECONF0 = 543, + MIPS_REG_COP0SEL_VPECONF1 = 544, + MIPS_REG_COP0SEL_WATCHHI0 = 545, + MIPS_REG_COP0SEL_WATCHHI1 = 546, + MIPS_REG_COP0SEL_WATCHHI2 = 547, + MIPS_REG_COP0SEL_WATCHHI3 = 548, + MIPS_REG_COP0SEL_WATCHHI4 = 549, + MIPS_REG_COP0SEL_WATCHHI5 = 550, + MIPS_REG_COP0SEL_WATCHHI6 = 551, + MIPS_REG_COP0SEL_WATCHHI7 = 552, + MIPS_REG_COP0SEL_WATCHHI8 = 553, + MIPS_REG_COP0SEL_WATCHHI9 = 554, + MIPS_REG_COP0SEL_WATCHHI10 = 555, + MIPS_REG_COP0SEL_WATCHHI11 = 556, + MIPS_REG_COP0SEL_WATCHHI12 = 557, + MIPS_REG_COP0SEL_WATCHHI13 = 558, + MIPS_REG_COP0SEL_WATCHHI14 = 559, + MIPS_REG_COP0SEL_WATCHHI15 = 560, + MIPS_REG_COP0SEL_WATCHLO0 = 561, + MIPS_REG_COP0SEL_WATCHLO1 = 562, + MIPS_REG_COP0SEL_WATCHLO2 = 563, + MIPS_REG_COP0SEL_WATCHLO3 = 564, + MIPS_REG_COP0SEL_WATCHLO4 = 565, + MIPS_REG_COP0SEL_WATCHLO5 = 566, + MIPS_REG_COP0SEL_WATCHLO6 = 567, + MIPS_REG_COP0SEL_WATCHLO7 = 568, + MIPS_REG_COP0SEL_WATCHLO8 = 569, + MIPS_REG_COP0SEL_WATCHLO9 = 570, + MIPS_REG_COP0SEL_WATCHLO10 = 571, + MIPS_REG_COP0SEL_WATCHLO11 = 572, + MIPS_REG_COP0SEL_WATCHLO12 = 573, + MIPS_REG_COP0SEL_WATCHLO13 = 574, + MIPS_REG_COP0SEL_WATCHLO14 = 575, + MIPS_REG_COP0SEL_WATCHLO15 = 576, + MIPS_REG_D0_64 = 577, + MIPS_REG_D1_64 = 578, + MIPS_REG_D2_64 = 579, + MIPS_REG_D3_64 = 580, + MIPS_REG_D4_64 = 581, + MIPS_REG_D5_64 = 582, + MIPS_REG_D6_64 = 583, + MIPS_REG_D7_64 = 584, + MIPS_REG_D8_64 = 585, + MIPS_REG_D9_64 = 586, + MIPS_REG_D10_64 = 587, + MIPS_REG_D11_64 = 588, + MIPS_REG_D12_64 = 589, + MIPS_REG_D13_64 = 590, + MIPS_REG_D14_64 = 591, + MIPS_REG_D15_64 = 592, + MIPS_REG_D16_64 = 593, + MIPS_REG_D17_64 = 594, + MIPS_REG_D18_64 = 595, + MIPS_REG_D19_64 = 596, + MIPS_REG_D20_64 = 597, + MIPS_REG_D21_64 = 598, + MIPS_REG_D22_64 = 599, + MIPS_REG_D23_64 = 600, + MIPS_REG_D24_64 = 601, + MIPS_REG_D25_64 = 602, + MIPS_REG_D26_64 = 603, + MIPS_REG_D27_64 = 604, + MIPS_REG_D28_64 = 605, + MIPS_REG_D29_64 = 606, + MIPS_REG_D30_64 = 607, + MIPS_REG_D31_64 = 608, + MIPS_REG_DSPOUTFLAG16_19 = 609, + MIPS_REG_HI0_64 = 610, + MIPS_REG_K0_64 = 611, + MIPS_REG_K1_64 = 612, + MIPS_REG_LO0_64 = 613, + MIPS_REG_S0_64 = 614, + MIPS_REG_S1_64 = 615, + MIPS_REG_S2_64 = 616, + MIPS_REG_S3_64 = 617, + MIPS_REG_S4_64 = 618, + MIPS_REG_S5_64 = 619, + MIPS_REG_S6_64 = 620, + MIPS_REG_S7_64 = 621, + MIPS_REG_T0_64 = 622, + MIPS_REG_T1_64 = 623, + MIPS_REG_T2_64 = 624, + MIPS_REG_T3_64 = 625, + MIPS_REG_T4_64 = 626, + MIPS_REG_T5_64 = 627, + MIPS_REG_T6_64 = 628, + MIPS_REG_T7_64 = 629, + MIPS_REG_T8_64 = 630, + MIPS_REG_T9_64 = 631, + MIPS_REG_V0_64 = 632, + MIPS_REG_V1_64 = 633, + MIPS_REG_COP0SEL_GUESTCTL0EXT = 634, + MIPS_REG_ENDING, // 635 diff --git a/arch/Mips/MipsGenDisassemblerTables.inc b/arch/Mips/MipsGenDisassemblerTables.inc index e926f7788..262ea8be8 100644 --- a/arch/Mips/MipsGenDisassemblerTables.inc +++ b/arch/Mips/MipsGenDisassemblerTables.inc @@ -1,13 +1,15 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* * Mips Disassembler *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ #include "../../MCInst.h" #include "../../LEB128.h" @@ -17,6915 +19,12096 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ - if (numBits == sizeof(InsnType)*8) \ + if (numBits == sizeof(InsnType) * 8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ return (insn & fieldMask) >> startBit; \ } +static bool Check(DecodeStatus *Out, const DecodeStatus In) { + *Out = (DecodeStatus) (*Out & In); + return *Out != MCDisassembler_Fail; +} + +static const uint8_t DecoderTable16[] = { +/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 17 +/* 8 */ MCD_OPC_CheckPredicate, 0, 92, 2, 0, // Skip to: 617 +/* 13 */ MCD_OPC_Decode, 237, 8, 0, // Opcode: Bimm16 +/* 17 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 31 +/* 22 */ MCD_OPC_CheckPredicate, 0, 78, 2, 0, // Skip to: 617 +/* 27 */ MCD_OPC_Decode, 235, 8, 1, // Opcode: BeqzRxImm16 +/* 31 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 45 +/* 36 */ MCD_OPC_CheckPredicate, 0, 64, 2, 0, // Skip to: 617 +/* 41 */ MCD_OPC_Decode, 239, 8, 1, // Opcode: BnezRxImm16 +/* 45 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 59 +/* 50 */ MCD_OPC_CheckPredicate, 0, 50, 2, 0, // Skip to: 617 +/* 55 */ MCD_OPC_Decode, 138, 7, 2, // Opcode: AddiuRxRxImm16 +/* 59 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 73 +/* 64 */ MCD_OPC_CheckPredicate, 0, 36, 2, 0, // Skip to: 617 +/* 69 */ MCD_OPC_Decode, 195, 23, 3, // Opcode: SltiRxImm16 +/* 73 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 87 +/* 78 */ MCD_OPC_CheckPredicate, 0, 22, 2, 0, // Skip to: 617 +/* 83 */ MCD_OPC_Decode, 197, 23, 3, // Opcode: SltiuRxImm16 +/* 87 */ MCD_OPC_FilterValue, 12, 73, 0, 0, // Skip to: 165 +/* 92 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 95 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 109 +/* 100 */ MCD_OPC_CheckPredicate, 0, 0, 2, 0, // Skip to: 617 +/* 105 */ MCD_OPC_Decode, 242, 8, 4, // Opcode: Bteqz16 +/* 109 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 123 +/* 114 */ MCD_OPC_CheckPredicate, 0, 242, 1, 0, // Skip to: 617 +/* 119 */ MCD_OPC_Decode, 244, 8, 4, // Opcode: Btnez16 +/* 123 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 137 +/* 128 */ MCD_OPC_CheckPredicate, 0, 228, 1, 0, // Skip to: 617 +/* 133 */ MCD_OPC_Decode, 141, 7, 4, // Opcode: AddiuSpImm16 +/* 137 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 151 +/* 142 */ MCD_OPC_CheckPredicate, 0, 214, 1, 0, // Skip to: 617 +/* 147 */ MCD_OPC_Decode, 129, 19, 5, // Opcode: Move32R16 +/* 151 */ MCD_OPC_FilterValue, 7, 205, 1, 0, // Skip to: 617 +/* 156 */ MCD_OPC_CheckPredicate, 0, 200, 1, 0, // Skip to: 617 +/* 161 */ MCD_OPC_Decode, 130, 19, 6, // Opcode: MoveR3216 +/* 165 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 179 +/* 170 */ MCD_OPC_CheckPredicate, 0, 186, 1, 0, // Skip to: 617 +/* 175 */ MCD_OPC_Decode, 188, 16, 3, // Opcode: LiRxImm16 +/* 179 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 193 +/* 184 */ MCD_OPC_CheckPredicate, 0, 172, 1, 0, // Skip to: 617 +/* 189 */ MCD_OPC_Decode, 189, 11, 3, // Opcode: CmpiRxImm16 +/* 193 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 207 +/* 198 */ MCD_OPC_CheckPredicate, 0, 158, 1, 0, // Skip to: 617 +/* 203 */ MCD_OPC_Decode, 191, 16, 7, // Opcode: LwRxPcTcp16 +/* 207 */ MCD_OPC_FilterValue, 28, 31, 0, 0, // Skip to: 243 +/* 212 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 215 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 229 +/* 220 */ MCD_OPC_CheckPredicate, 0, 136, 1, 0, // Skip to: 617 +/* 225 */ MCD_OPC_Decode, 143, 7, 8, // Opcode: AdduRxRyRz16 +/* 229 */ MCD_OPC_FilterValue, 3, 127, 1, 0, // Skip to: 617 +/* 234 */ MCD_OPC_CheckPredicate, 0, 122, 1, 0, // Skip to: 617 +/* 239 */ MCD_OPC_Decode, 204, 23, 8, // Opcode: SubuRxRyRz16 +/* 243 */ MCD_OPC_FilterValue, 29, 113, 1, 0, // Skip to: 617 +/* 248 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 251 */ MCD_OPC_FilterValue, 0, 80, 0, 0, // Skip to: 336 +/* 256 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 259 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 273 +/* 264 */ MCD_OPC_CheckPredicate, 0, 92, 1, 0, // Skip to: 617 +/* 269 */ MCD_OPC_Decode, 151, 15, 9, // Opcode: JumpLinkReg16 +/* 273 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 294 +/* 278 */ MCD_OPC_CheckPredicate, 0, 78, 1, 0, // Skip to: 617 +/* 283 */ MCD_OPC_CheckField, 8, 3, 0, 71, 1, 0, // Skip to: 617 +/* 290 */ MCD_OPC_Decode, 148, 15, 10, // Opcode: JrRa16 +/* 294 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 315 +/* 299 */ MCD_OPC_CheckPredicate, 0, 57, 1, 0, // Skip to: 617 +/* 304 */ MCD_OPC_CheckField, 8, 3, 0, 50, 1, 0, // Skip to: 617 +/* 311 */ MCD_OPC_Decode, 150, 15, 10, // Opcode: JrcRx16 +/* 315 */ MCD_OPC_FilterValue, 7, 41, 1, 0, // Skip to: 617 +/* 320 */ MCD_OPC_CheckPredicate, 0, 36, 1, 0, // Skip to: 617 +/* 325 */ MCD_OPC_CheckField, 8, 3, 0, 29, 1, 0, // Skip to: 617 +/* 332 */ MCD_OPC_Decode, 149, 15, 10, // Opcode: JrcRa16 +/* 336 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 350 +/* 341 */ MCD_OPC_CheckPredicate, 0, 15, 1, 0, // Skip to: 617 +/* 346 */ MCD_OPC_Decode, 194, 23, 11, // Opcode: SltRxRy16 +/* 350 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 364 +/* 355 */ MCD_OPC_CheckPredicate, 0, 1, 1, 0, // Skip to: 617 +/* 360 */ MCD_OPC_Decode, 199, 23, 11, // Opcode: SltuRxRy16 +/* 364 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 378 +/* 369 */ MCD_OPC_CheckPredicate, 0, 243, 0, 0, // Skip to: 617 +/* 374 */ MCD_OPC_Decode, 193, 23, 12, // Opcode: SllvRxRy16 +/* 378 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 399 +/* 383 */ MCD_OPC_CheckPredicate, 0, 229, 0, 0, // Skip to: 617 +/* 388 */ MCD_OPC_CheckField, 5, 6, 0, 222, 0, 0, // Skip to: 617 +/* 395 */ MCD_OPC_Decode, 241, 8, 10, // Opcode: Break16 +/* 399 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 413 +/* 404 */ MCD_OPC_CheckPredicate, 0, 208, 0, 0, // Skip to: 617 +/* 409 */ MCD_OPC_Decode, 203, 23, 12, // Opcode: SrlvRxRy16 +/* 413 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 427 +/* 418 */ MCD_OPC_CheckPredicate, 0, 194, 0, 0, // Skip to: 617 +/* 423 */ MCD_OPC_Decode, 201, 23, 12, // Opcode: SravRxRy16 +/* 427 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 441 +/* 432 */ MCD_OPC_CheckPredicate, 0, 180, 0, 0, // Skip to: 617 +/* 437 */ MCD_OPC_Decode, 188, 11, 11, // Opcode: CmpRxRy16 +/* 441 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 455 +/* 446 */ MCD_OPC_CheckPredicate, 0, 166, 0, 0, // Skip to: 617 +/* 451 */ MCD_OPC_Decode, 144, 7, 12, // Opcode: AndRxRxRy16 +/* 455 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 469 +/* 460 */ MCD_OPC_CheckPredicate, 0, 152, 0, 0, // Skip to: 617 +/* 465 */ MCD_OPC_Decode, 178, 19, 12, // Opcode: OrRxRxRy16 +/* 469 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 483 +/* 474 */ MCD_OPC_CheckPredicate, 0, 138, 0, 0, // Skip to: 617 +/* 479 */ MCD_OPC_Decode, 187, 24, 12, // Opcode: XorRxRxRy16 +/* 483 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 497 +/* 488 */ MCD_OPC_CheckPredicate, 0, 124, 0, 0, // Skip to: 617 +/* 493 */ MCD_OPC_Decode, 162, 19, 11, // Opcode: NotRxRy16 +/* 497 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 518 +/* 502 */ MCD_OPC_CheckPredicate, 0, 110, 0, 0, // Skip to: 617 +/* 507 */ MCD_OPC_CheckField, 5, 3, 0, 103, 0, 0, // Skip to: 617 +/* 514 */ MCD_OPC_Decode, 255, 18, 9, // Opcode: Mfhi16 +/* 518 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 554 +/* 523 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 526 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 540 +/* 531 */ MCD_OPC_CheckPredicate, 0, 81, 0, 0, // Skip to: 617 +/* 536 */ MCD_OPC_Decode, 189, 23, 13, // Opcode: SebRx16 +/* 540 */ MCD_OPC_FilterValue, 5, 72, 0, 0, // Skip to: 617 +/* 545 */ MCD_OPC_CheckPredicate, 0, 67, 0, 0, // Skip to: 617 +/* 550 */ MCD_OPC_Decode, 190, 23, 13, // Opcode: SehRx16 +/* 554 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 575 +/* 559 */ MCD_OPC_CheckPredicate, 0, 53, 0, 0, // Skip to: 617 +/* 564 */ MCD_OPC_CheckField, 5, 3, 0, 46, 0, 0, // Skip to: 617 +/* 571 */ MCD_OPC_Decode, 128, 19, 9, // Opcode: Mflo16 +/* 575 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 589 +/* 580 */ MCD_OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 617 +/* 585 */ MCD_OPC_Decode, 204, 12, 11, // Opcode: DivRxRy16 +/* 589 */ MCD_OPC_FilterValue, 27, 9, 0, 0, // Skip to: 603 +/* 594 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 617 +/* 599 */ MCD_OPC_Decode, 205, 12, 11, // Opcode: DivuRxRy16 +/* 603 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 617 +/* 608 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 617 +/* 613 */ MCD_OPC_Decode, 161, 19, 11, // Opcode: NegRxRy16 +/* 617 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTable32[] = { +/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 31 +/* 8 */ MCD_OPC_CheckPredicate, 0, 2, 2, 0, // Skip to: 527 +/* 13 */ MCD_OPC_CheckField, 27, 5, 30, 251, 1, 0, // Skip to: 527 +/* 20 */ MCD_OPC_CheckField, 5, 3, 0, 244, 1, 0, // Skip to: 527 +/* 27 */ MCD_OPC_Decode, 137, 7, 14, // Opcode: AddiuRxPcImmX16 +/* 31 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 59 +/* 36 */ MCD_OPC_CheckPredicate, 0, 230, 1, 0, // Skip to: 527 +/* 41 */ MCD_OPC_CheckField, 27, 5, 30, 223, 1, 0, // Skip to: 527 +/* 48 */ MCD_OPC_CheckField, 5, 6, 0, 216, 1, 0, // Skip to: 527 +/* 55 */ MCD_OPC_Decode, 238, 8, 15, // Opcode: BimmX16 +/* 59 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 87 +/* 64 */ MCD_OPC_CheckPredicate, 0, 202, 1, 0, // Skip to: 527 +/* 69 */ MCD_OPC_CheckField, 27, 5, 30, 195, 1, 0, // Skip to: 527 +/* 76 */ MCD_OPC_CheckField, 5, 3, 0, 188, 1, 0, // Skip to: 527 +/* 83 */ MCD_OPC_Decode, 236, 8, 16, // Opcode: BeqzRxImmX16 +/* 87 */ MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 115 +/* 92 */ MCD_OPC_CheckPredicate, 0, 174, 1, 0, // Skip to: 527 +/* 97 */ MCD_OPC_CheckField, 27, 5, 30, 167, 1, 0, // Skip to: 527 +/* 104 */ MCD_OPC_CheckField, 5, 3, 0, 160, 1, 0, // Skip to: 527 +/* 111 */ MCD_OPC_Decode, 240, 8, 16, // Opcode: BnezRxImmX16 +/* 115 */ MCD_OPC_FilterValue, 6, 106, 0, 0, // Skip to: 226 +/* 120 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ... +/* 123 */ MCD_OPC_FilterValue, 30, 143, 1, 0, // Skip to: 527 +/* 128 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 131 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 181 +/* 136 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 139 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 153 +/* 144 */ MCD_OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 181 +/* 149 */ MCD_OPC_Decode, 192, 23, 17, // Opcode: SllX16 +/* 153 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 167 +/* 158 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 181 +/* 163 */ MCD_OPC_Decode, 202, 23, 17, // Opcode: SrlX16 +/* 167 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 181 +/* 172 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 181 +/* 177 */ MCD_OPC_Decode, 200, 23, 17, // Opcode: SraX16 +/* 181 */ MCD_OPC_ExtractField, 5, 6, // Inst{10-5} ... +/* 184 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 198 +/* 189 */ MCD_OPC_CheckPredicate, 0, 77, 1, 0, // Skip to: 527 +/* 194 */ MCD_OPC_Decode, 243, 8, 18, // Opcode: BteqzX16 +/* 198 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 212 +/* 203 */ MCD_OPC_CheckPredicate, 0, 63, 1, 0, // Skip to: 527 +/* 208 */ MCD_OPC_Decode, 245, 8, 18, // Opcode: BtnezX16 +/* 212 */ MCD_OPC_FilterValue, 24, 54, 1, 0, // Skip to: 527 +/* 217 */ MCD_OPC_CheckPredicate, 0, 49, 1, 0, // Skip to: 527 +/* 222 */ MCD_OPC_Decode, 142, 7, 18, // Opcode: AddiuSpImmX16 +/* 226 */ MCD_OPC_FilterValue, 8, 23, 0, 0, // Skip to: 254 +/* 231 */ MCD_OPC_CheckPredicate, 0, 35, 1, 0, // Skip to: 527 +/* 236 */ MCD_OPC_CheckField, 27, 5, 30, 28, 1, 0, // Skip to: 527 +/* 243 */ MCD_OPC_CheckField, 4, 1, 0, 21, 1, 0, // Skip to: 527 +/* 250 */ MCD_OPC_Decode, 140, 7, 19, // Opcode: AddiuRxRyOffMemX16 +/* 254 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 282 +/* 259 */ MCD_OPC_CheckPredicate, 0, 7, 1, 0, // Skip to: 527 +/* 264 */ MCD_OPC_CheckField, 27, 5, 30, 0, 1, 0, // Skip to: 527 +/* 271 */ MCD_OPC_CheckField, 5, 3, 0, 249, 0, 0, // Skip to: 527 +/* 278 */ MCD_OPC_Decode, 136, 7, 14, // Opcode: AddiuRxImmX16 +/* 282 */ MCD_OPC_FilterValue, 10, 23, 0, 0, // Skip to: 310 +/* 287 */ MCD_OPC_CheckPredicate, 0, 235, 0, 0, // Skip to: 527 +/* 292 */ MCD_OPC_CheckField, 27, 5, 30, 228, 0, 0, // Skip to: 527 +/* 299 */ MCD_OPC_CheckField, 5, 3, 0, 221, 0, 0, // Skip to: 527 +/* 306 */ MCD_OPC_Decode, 196, 23, 14, // Opcode: SltiRxImmX16 +/* 310 */ MCD_OPC_FilterValue, 11, 23, 0, 0, // Skip to: 338 +/* 315 */ MCD_OPC_CheckPredicate, 0, 207, 0, 0, // Skip to: 527 +/* 320 */ MCD_OPC_CheckField, 27, 5, 30, 200, 0, 0, // Skip to: 527 +/* 327 */ MCD_OPC_CheckField, 5, 3, 0, 193, 0, 0, // Skip to: 527 +/* 334 */ MCD_OPC_Decode, 198, 23, 14, // Opcode: SltiuRxImmX16 +/* 338 */ MCD_OPC_FilterValue, 13, 23, 0, 0, // Skip to: 366 +/* 343 */ MCD_OPC_CheckPredicate, 0, 179, 0, 0, // Skip to: 527 +/* 348 */ MCD_OPC_CheckField, 27, 5, 30, 172, 0, 0, // Skip to: 527 +/* 355 */ MCD_OPC_CheckField, 5, 3, 0, 165, 0, 0, // Skip to: 527 +/* 362 */ MCD_OPC_Decode, 190, 16, 14, // Opcode: LiRxImmX16 +/* 366 */ MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 394 +/* 371 */ MCD_OPC_CheckPredicate, 0, 151, 0, 0, // Skip to: 527 +/* 376 */ MCD_OPC_CheckField, 27, 5, 30, 144, 0, 0, // Skip to: 527 +/* 383 */ MCD_OPC_CheckField, 5, 3, 0, 137, 0, 0, // Skip to: 527 +/* 390 */ MCD_OPC_Decode, 190, 11, 14, // Opcode: CmpiRxImmX16 +/* 394 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 415 +/* 399 */ MCD_OPC_CheckPredicate, 0, 123, 0, 0, // Skip to: 527 +/* 404 */ MCD_OPC_CheckField, 27, 5, 30, 116, 0, 0, // Skip to: 527 +/* 411 */ MCD_OPC_Decode, 194, 16, 19, // Opcode: LwRxSpImmX16 +/* 415 */ MCD_OPC_FilterValue, 22, 23, 0, 0, // Skip to: 443 +/* 420 */ MCD_OPC_CheckPredicate, 0, 102, 0, 0, // Skip to: 527 +/* 425 */ MCD_OPC_CheckField, 27, 5, 30, 95, 0, 0, // Skip to: 527 +/* 432 */ MCD_OPC_CheckField, 5, 3, 0, 88, 0, 0, // Skip to: 527 +/* 439 */ MCD_OPC_Decode, 192, 16, 20, // Opcode: LwRxPcTcpX16 +/* 443 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 464 +/* 448 */ MCD_OPC_CheckPredicate, 0, 74, 0, 0, // Skip to: 527 +/* 453 */ MCD_OPC_CheckField, 27, 5, 30, 67, 0, 0, // Skip to: 527 +/* 460 */ MCD_OPC_Decode, 188, 23, 19, // Opcode: SbRxRyOffMemX16 +/* 464 */ MCD_OPC_FilterValue, 25, 16, 0, 0, // Skip to: 485 +/* 469 */ MCD_OPC_CheckPredicate, 0, 53, 0, 0, // Skip to: 527 +/* 474 */ MCD_OPC_CheckField, 27, 5, 30, 46, 0, 0, // Skip to: 527 +/* 481 */ MCD_OPC_Decode, 191, 23, 19, // Opcode: ShRxRyOffMemX16 +/* 485 */ MCD_OPC_FilterValue, 26, 16, 0, 0, // Skip to: 506 +/* 490 */ MCD_OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 527 +/* 495 */ MCD_OPC_CheckField, 27, 5, 30, 25, 0, 0, // Skip to: 527 +/* 502 */ MCD_OPC_Decode, 206, 23, 19, // Opcode: SwRxSpImmX16 +/* 506 */ MCD_OPC_FilterValue, 27, 16, 0, 0, // Skip to: 527 +/* 511 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 527 +/* 516 */ MCD_OPC_CheckField, 27, 5, 30, 4, 0, 0, // Skip to: 527 +/* 523 */ MCD_OPC_Decode, 205, 23, 19, // Opcode: SwRxRyOffMemX16 +/* 527 */ MCD_OPC_Fail, + 0 +}; + static const uint8_t DecoderTableCOP3_32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15 -/* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51 -/* 11 */ MCD_OPC_Decode, 220, 7, 10, // Opcode: LWC3 -/* 15 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 27 -/* 19 */ MCD_OPC_CheckPredicate, 2, 28, 0, // Skip to: 51 -/* 23 */ MCD_OPC_Decode, 167, 7, 10, // Opcode: LDC3 -/* 27 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 39 -/* 31 */ MCD_OPC_CheckPredicate, 1, 16, 0, // Skip to: 51 -/* 35 */ MCD_OPC_Decode, 242, 12, 10, // Opcode: SWC3 -/* 39 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 51 -/* 43 */ MCD_OPC_CheckPredicate, 2, 4, 0, // Skip to: 51 -/* 47 */ MCD_OPC_Decode, 161, 11, 10, // Opcode: SDC3 -/* 51 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 51, 9, 0, 0, // Skip to: 17 +/* 8 */ MCD_OPC_CheckPredicate, 1, 46, 0, 0, // Skip to: 59 +/* 13 */ MCD_OPC_Decode, 141, 16, 21, // Opcode: LWC3 +/* 17 */ MCD_OPC_FilterValue, 55, 9, 0, 0, // Skip to: 31 +/* 22 */ MCD_OPC_CheckPredicate, 2, 32, 0, 0, // Skip to: 59 +/* 27 */ MCD_OPC_Decode, 188, 15, 21, // Opcode: LDC3 +/* 31 */ MCD_OPC_FilterValue, 59, 9, 0, 0, // Skip to: 45 +/* 36 */ MCD_OPC_CheckPredicate, 1, 18, 0, 0, // Skip to: 59 +/* 41 */ MCD_OPC_Decode, 139, 23, 21, // Opcode: SWC3 +/* 45 */ MCD_OPC_FilterValue, 63, 9, 0, 0, // Skip to: 59 +/* 50 */ MCD_OPC_CheckPredicate, 2, 4, 0, 0, // Skip to: 59 +/* 55 */ MCD_OPC_Decode, 235, 20, 21, // Opcode: SDC3 +/* 59 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableCnMips32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 39 +/* 8 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 11 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25 +/* 16 */ MCD_OPC_CheckPredicate, 3, 239, 1, 0, // Skip to: 516 +/* 21 */ MCD_OPC_Decode, 240, 11, 22, // Opcode: DMFC2_OCTEON +/* 25 */ MCD_OPC_FilterValue, 5, 230, 1, 0, // Skip to: 516 +/* 30 */ MCD_OPC_CheckPredicate, 3, 225, 1, 0, // Skip to: 516 +/* 35 */ MCD_OPC_Decode, 248, 11, 22, // Opcode: DMTC2_OCTEON +/* 39 */ MCD_OPC_FilterValue, 28, 160, 1, 0, // Skip to: 460 +/* 44 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 47 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 68 +/* 52 */ MCD_OPC_CheckPredicate, 3, 203, 1, 0, // Skip to: 516 +/* 57 */ MCD_OPC_CheckField, 6, 5, 0, 196, 1, 0, // Skip to: 516 +/* 64 */ MCD_OPC_Decode, 253, 11, 23, // Opcode: DMUL +/* 68 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 89 +/* 73 */ MCD_OPC_CheckPredicate, 3, 182, 1, 0, // Skip to: 516 +/* 78 */ MCD_OPC_CheckField, 6, 15, 0, 175, 1, 0, // Skip to: 516 +/* 85 */ MCD_OPC_Decode, 191, 18, 24, // Opcode: MTM0 +/* 89 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 110 +/* 94 */ MCD_OPC_CheckPredicate, 3, 161, 1, 0, // Skip to: 516 +/* 99 */ MCD_OPC_CheckField, 6, 15, 0, 154, 1, 0, // Skip to: 516 +/* 106 */ MCD_OPC_Decode, 194, 18, 24, // Opcode: MTP0 +/* 110 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 131 +/* 115 */ MCD_OPC_CheckPredicate, 3, 140, 1, 0, // Skip to: 516 +/* 120 */ MCD_OPC_CheckField, 6, 15, 0, 133, 1, 0, // Skip to: 516 +/* 127 */ MCD_OPC_Decode, 195, 18, 24, // Opcode: MTP1 +/* 131 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 152 +/* 136 */ MCD_OPC_CheckPredicate, 3, 119, 1, 0, // Skip to: 516 +/* 141 */ MCD_OPC_CheckField, 6, 15, 0, 112, 1, 0, // Skip to: 516 +/* 148 */ MCD_OPC_Decode, 196, 18, 24, // Opcode: MTP2 +/* 152 */ MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 173 +/* 157 */ MCD_OPC_CheckPredicate, 3, 98, 1, 0, // Skip to: 516 +/* 162 */ MCD_OPC_CheckField, 6, 15, 0, 91, 1, 0, // Skip to: 516 +/* 169 */ MCD_OPC_Decode, 192, 18, 24, // Opcode: MTM1 +/* 173 */ MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 194 +/* 178 */ MCD_OPC_CheckPredicate, 3, 77, 1, 0, // Skip to: 516 +/* 183 */ MCD_OPC_CheckField, 6, 15, 0, 70, 1, 0, // Skip to: 516 +/* 190 */ MCD_OPC_Decode, 193, 18, 24, // Opcode: MTM2 +/* 194 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 215 +/* 199 */ MCD_OPC_CheckPredicate, 3, 56, 1, 0, // Skip to: 516 +/* 204 */ MCD_OPC_CheckField, 6, 5, 0, 49, 1, 0, // Skip to: 516 +/* 211 */ MCD_OPC_Decode, 156, 24, 23, // Opcode: VMULU +/* 215 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 236 +/* 220 */ MCD_OPC_CheckPredicate, 3, 35, 1, 0, // Skip to: 516 +/* 225 */ MCD_OPC_CheckField, 6, 5, 0, 28, 1, 0, // Skip to: 516 +/* 232 */ MCD_OPC_Decode, 155, 24, 23, // Opcode: VMM0 +/* 236 */ MCD_OPC_FilterValue, 17, 16, 0, 0, // Skip to: 257 +/* 241 */ MCD_OPC_CheckPredicate, 3, 14, 1, 0, // Skip to: 516 +/* 246 */ MCD_OPC_CheckField, 6, 5, 0, 7, 1, 0, // Skip to: 516 +/* 253 */ MCD_OPC_Decode, 154, 24, 23, // Opcode: V3MULU +/* 257 */ MCD_OPC_FilterValue, 40, 16, 0, 0, // Skip to: 278 +/* 262 */ MCD_OPC_CheckPredicate, 3, 249, 0, 0, // Skip to: 516 +/* 267 */ MCD_OPC_CheckField, 6, 5, 0, 242, 0, 0, // Skip to: 516 +/* 274 */ MCD_OPC_Decode, 146, 7, 23, // Opcode: BADDu +/* 278 */ MCD_OPC_FilterValue, 42, 16, 0, 0, // Skip to: 299 +/* 283 */ MCD_OPC_CheckPredicate, 3, 228, 0, 0, // Skip to: 516 +/* 288 */ MCD_OPC_CheckField, 6, 5, 0, 221, 0, 0, // Skip to: 516 +/* 295 */ MCD_OPC_Decode, 140, 21, 23, // Opcode: SEQ +/* 299 */ MCD_OPC_FilterValue, 43, 16, 0, 0, // Skip to: 320 +/* 304 */ MCD_OPC_CheckPredicate, 3, 207, 0, 0, // Skip to: 516 +/* 309 */ MCD_OPC_CheckField, 6, 5, 0, 200, 0, 0, // Skip to: 516 +/* 316 */ MCD_OPC_Decode, 255, 21, 23, // Opcode: SNE +/* 320 */ MCD_OPC_FilterValue, 44, 23, 0, 0, // Skip to: 348 +/* 325 */ MCD_OPC_CheckPredicate, 3, 186, 0, 0, // Skip to: 516 +/* 330 */ MCD_OPC_CheckField, 16, 5, 0, 179, 0, 0, // Skip to: 516 +/* 337 */ MCD_OPC_CheckField, 6, 5, 0, 172, 0, 0, // Skip to: 516 +/* 344 */ MCD_OPC_Decode, 203, 19, 25, // Opcode: POP +/* 348 */ MCD_OPC_FilterValue, 45, 23, 0, 0, // Skip to: 376 +/* 353 */ MCD_OPC_CheckPredicate, 3, 158, 0, 0, // Skip to: 516 +/* 358 */ MCD_OPC_CheckField, 16, 5, 0, 151, 0, 0, // Skip to: 516 +/* 365 */ MCD_OPC_CheckField, 6, 5, 0, 144, 0, 0, // Skip to: 516 +/* 372 */ MCD_OPC_Decode, 158, 12, 26, // Opcode: DPOP +/* 376 */ MCD_OPC_FilterValue, 46, 9, 0, 0, // Skip to: 390 +/* 381 */ MCD_OPC_CheckPredicate, 3, 130, 0, 0, // Skip to: 516 +/* 386 */ MCD_OPC_Decode, 142, 21, 27, // Opcode: SEQi +/* 390 */ MCD_OPC_FilterValue, 47, 9, 0, 0, // Skip to: 404 +/* 395 */ MCD_OPC_CheckPredicate, 3, 116, 0, 0, // Skip to: 516 +/* 400 */ MCD_OPC_Decode, 128, 22, 27, // Opcode: SNEi +/* 404 */ MCD_OPC_FilterValue, 50, 9, 0, 0, // Skip to: 418 +/* 409 */ MCD_OPC_CheckPredicate, 4, 102, 0, 0, // Skip to: 516 +/* 414 */ MCD_OPC_Decode, 148, 9, 28, // Opcode: CINS +/* 418 */ MCD_OPC_FilterValue, 51, 9, 0, 0, // Skip to: 432 +/* 423 */ MCD_OPC_CheckPredicate, 4, 88, 0, 0, // Skip to: 516 +/* 428 */ MCD_OPC_Decode, 149, 9, 28, // Opcode: CINS32 +/* 432 */ MCD_OPC_FilterValue, 58, 9, 0, 0, // Skip to: 446 +/* 437 */ MCD_OPC_CheckPredicate, 4, 74, 0, 0, // Skip to: 516 +/* 442 */ MCD_OPC_Decode, 252, 12, 28, // Opcode: EXTS +/* 446 */ MCD_OPC_FilterValue, 59, 65, 0, 0, // Skip to: 516 +/* 451 */ MCD_OPC_CheckPredicate, 4, 60, 0, 0, // Skip to: 516 +/* 456 */ MCD_OPC_Decode, 253, 12, 28, // Opcode: EXTS32 +/* 460 */ MCD_OPC_FilterValue, 50, 9, 0, 0, // Skip to: 474 +/* 465 */ MCD_OPC_CheckPredicate, 3, 46, 0, 0, // Skip to: 516 +/* 470 */ MCD_OPC_Decode, 156, 7, 29, // Opcode: BBIT0 +/* 474 */ MCD_OPC_FilterValue, 54, 9, 0, 0, // Skip to: 488 +/* 479 */ MCD_OPC_CheckPredicate, 3, 32, 0, 0, // Skip to: 516 +/* 484 */ MCD_OPC_Decode, 157, 7, 29, // Opcode: BBIT032 +/* 488 */ MCD_OPC_FilterValue, 58, 9, 0, 0, // Skip to: 502 +/* 493 */ MCD_OPC_CheckPredicate, 3, 18, 0, 0, // Skip to: 516 +/* 498 */ MCD_OPC_Decode, 158, 7, 29, // Opcode: BBIT1 +/* 502 */ MCD_OPC_FilterValue, 62, 9, 0, 0, // Skip to: 516 +/* 507 */ MCD_OPC_CheckPredicate, 3, 4, 0, 0, // Skip to: 516 +/* 512 */ MCD_OPC_Decode, 159, 7, 29, // Opcode: BBIT132 +/* 516 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableCnMipsP32[] = { +/* 0 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... +/* 3 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 24 +/* 8 */ MCD_OPC_CheckPredicate, 5, 32, 0, 0, // Skip to: 45 +/* 13 */ MCD_OPC_CheckField, 26, 6, 28, 25, 0, 0, // Skip to: 45 +/* 20 */ MCD_OPC_Decode, 181, 20, 30, // Opcode: SAA +/* 24 */ MCD_OPC_FilterValue, 25, 16, 0, 0, // Skip to: 45 +/* 29 */ MCD_OPC_CheckPredicate, 5, 11, 0, 0, // Skip to: 45 +/* 34 */ MCD_OPC_CheckField, 26, 6, 28, 4, 0, 0, // Skip to: 45 +/* 41 */ MCD_OPC_Decode, 182, 20, 30, // Opcode: SAAD +/* 45 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMicroMips16[] = { /* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 3 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 33 -/* 7 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 10 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 21 -/* 14 */ MCD_OPC_CheckPredicate, 3, 19, 2, // Skip to: 549 -/* 18 */ MCD_OPC_Decode, 52, 11, // Opcode: ADDU16_MM -/* 21 */ MCD_OPC_FilterValue, 1, 12, 2, // Skip to: 549 -/* 25 */ MCD_OPC_CheckPredicate, 3, 8, 2, // Skip to: 549 -/* 29 */ MCD_OPC_Decode, 214, 12, 11, // Opcode: SUBU16_MM -/* 33 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 45 -/* 37 */ MCD_OPC_CheckPredicate, 3, 252, 1, // Skip to: 549 -/* 41 */ MCD_OPC_Decode, 155, 7, 12, // Opcode: LBU16_MM -/* 45 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 57 -/* 49 */ MCD_OPC_CheckPredicate, 3, 240, 1, // Skip to: 549 -/* 53 */ MCD_OPC_Decode, 233, 8, 13, // Opcode: MOVE16_MM -/* 57 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 88 -/* 61 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 64 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 76 -/* 68 */ MCD_OPC_CheckPredicate, 3, 221, 1, // Skip to: 549 -/* 72 */ MCD_OPC_Decode, 226, 11, 14, // Opcode: SLL16_MM -/* 76 */ MCD_OPC_FilterValue, 1, 213, 1, // Skip to: 549 -/* 80 */ MCD_OPC_CheckPredicate, 3, 209, 1, // Skip to: 549 -/* 84 */ MCD_OPC_Decode, 160, 12, 14, // Opcode: SRL16_MM -/* 88 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 100 -/* 92 */ MCD_OPC_CheckPredicate, 3, 197, 1, // Skip to: 549 -/* 96 */ MCD_OPC_Decode, 186, 7, 12, // Opcode: LHU16_MM -/* 100 */ MCD_OPC_FilterValue, 11, 7, 0, // Skip to: 111 -/* 104 */ MCD_OPC_CheckPredicate, 3, 185, 1, // Skip to: 549 -/* 108 */ MCD_OPC_Decode, 86, 15, // Opcode: ANDI16_MM -/* 111 */ MCD_OPC_FilterValue, 17, 226, 0, // Skip to: 341 -/* 115 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... -/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 -/* 122 */ MCD_OPC_CheckPredicate, 3, 167, 1, // Skip to: 549 -/* 126 */ MCD_OPC_Decode, 130, 10, 16, // Opcode: NOT16_MM -/* 130 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 142 -/* 134 */ MCD_OPC_CheckPredicate, 3, 155, 1, // Skip to: 549 -/* 138 */ MCD_OPC_Decode, 237, 13, 17, // Opcode: XOR16_MM -/* 142 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 153 -/* 146 */ MCD_OPC_CheckPredicate, 3, 143, 1, // Skip to: 549 -/* 150 */ MCD_OPC_Decode, 84, 17, // Opcode: AND16_MM -/* 153 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 165 -/* 157 */ MCD_OPC_CheckPredicate, 3, 132, 1, // Skip to: 549 -/* 161 */ MCD_OPC_Decode, 134, 10, 17, // Opcode: OR16_MM -/* 165 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 177 -/* 169 */ MCD_OPC_CheckPredicate, 3, 120, 1, // Skip to: 549 -/* 173 */ MCD_OPC_Decode, 225, 7, 18, // Opcode: LWM16_MM -/* 177 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 189 -/* 181 */ MCD_OPC_CheckPredicate, 3, 108, 1, // Skip to: 549 -/* 185 */ MCD_OPC_Decode, 246, 12, 18, // Opcode: SWM16_MM -/* 189 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 220 -/* 193 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 196 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 208 -/* 200 */ MCD_OPC_CheckPredicate, 3, 89, 1, // Skip to: 549 -/* 204 */ MCD_OPC_Decode, 137, 7, 19, // Opcode: JR16_MM -/* 208 */ MCD_OPC_FilterValue, 1, 81, 1, // Skip to: 549 -/* 212 */ MCD_OPC_CheckPredicate, 3, 77, 1, // Skip to: 549 -/* 216 */ MCD_OPC_Decode, 140, 7, 19, // Opcode: JRC16_MM -/* 220 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 251 -/* 224 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 227 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 239 -/* 231 */ MCD_OPC_CheckPredicate, 3, 58, 1, // Skip to: 549 -/* 235 */ MCD_OPC_Decode, 250, 6, 19, // Opcode: JALR16_MM -/* 239 */ MCD_OPC_FilterValue, 1, 50, 1, // Skip to: 549 -/* 243 */ MCD_OPC_CheckPredicate, 3, 46, 1, // Skip to: 549 -/* 247 */ MCD_OPC_Decode, 254, 6, 19, // Opcode: JALRS16_MM -/* 251 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 269 -/* 255 */ MCD_OPC_CheckPredicate, 3, 34, 1, // Skip to: 549 -/* 259 */ MCD_OPC_CheckField, 5, 1, 0, 28, 1, // Skip to: 549 -/* 265 */ MCD_OPC_Decode, 187, 8, 19, // Opcode: MFHI16_MM -/* 269 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 287 -/* 273 */ MCD_OPC_CheckPredicate, 3, 16, 1, // Skip to: 549 -/* 277 */ MCD_OPC_CheckField, 5, 1, 0, 10, 1, // Skip to: 549 -/* 283 */ MCD_OPC_Decode, 192, 8, 19, // Opcode: MFLO16_MM -/* 287 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 305 -/* 291 */ MCD_OPC_CheckPredicate, 3, 254, 0, // Skip to: 549 -/* 295 */ MCD_OPC_CheckField, 4, 2, 0, 248, 0, // Skip to: 549 -/* 301 */ MCD_OPC_Decode, 172, 2, 20, // Opcode: BREAK16_MM -/* 305 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 323 -/* 309 */ MCD_OPC_CheckPredicate, 3, 236, 0, // Skip to: 549 -/* 313 */ MCD_OPC_CheckField, 4, 2, 0, 230, 0, // Skip to: 549 -/* 319 */ MCD_OPC_Decode, 153, 11, 20, // Opcode: SDBBP16_MM -/* 323 */ MCD_OPC_FilterValue, 12, 222, 0, // Skip to: 549 -/* 327 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 549 -/* 331 */ MCD_OPC_CheckField, 5, 1, 0, 212, 0, // Skip to: 549 -/* 337 */ MCD_OPC_Decode, 139, 7, 21, // Opcode: JRADDIUSP -/* 341 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 353 -/* 345 */ MCD_OPC_CheckPredicate, 3, 200, 0, // Skip to: 549 -/* 349 */ MCD_OPC_Decode, 233, 7, 22, // Opcode: LWSP_MM -/* 353 */ MCD_OPC_FilterValue, 19, 25, 0, // Skip to: 382 -/* 357 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 360 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 371 -/* 364 */ MCD_OPC_CheckPredicate, 3, 181, 0, // Skip to: 549 -/* 368 */ MCD_OPC_Decode, 30, 23, // Opcode: ADDIUS5_MM -/* 371 */ MCD_OPC_FilterValue, 1, 174, 0, // Skip to: 549 -/* 375 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 549 -/* 379 */ MCD_OPC_Decode, 31, 24, // Opcode: ADDIUSP_MM -/* 382 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 394 -/* 386 */ MCD_OPC_CheckPredicate, 3, 159, 0, // Skip to: 549 -/* 390 */ MCD_OPC_Decode, 221, 7, 25, // Opcode: LWGP_MM -/* 394 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 406 -/* 398 */ MCD_OPC_CheckPredicate, 3, 147, 0, // Skip to: 549 -/* 402 */ MCD_OPC_Decode, 214, 7, 12, // Opcode: LW16_MM -/* 406 */ MCD_OPC_FilterValue, 27, 25, 0, // Skip to: 435 -/* 410 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 413 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 424 -/* 417 */ MCD_OPC_CheckPredicate, 3, 128, 0, // Skip to: 549 -/* 421 */ MCD_OPC_Decode, 29, 26, // Opcode: ADDIUR2_MM -/* 424 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 549 -/* 428 */ MCD_OPC_CheckPredicate, 3, 117, 0, // Skip to: 549 -/* 432 */ MCD_OPC_Decode, 28, 27, // Opcode: ADDIUR1SP_MM -/* 435 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 453 -/* 439 */ MCD_OPC_CheckPredicate, 3, 106, 0, // Skip to: 549 -/* 443 */ MCD_OPC_CheckField, 0, 1, 0, 100, 0, // Skip to: 549 -/* 449 */ MCD_OPC_Decode, 234, 8, 28, // Opcode: MOVEP_MM -/* 453 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 465 -/* 457 */ MCD_OPC_CheckPredicate, 3, 88, 0, // Skip to: 549 -/* 461 */ MCD_OPC_Decode, 143, 11, 12, // Opcode: SB16_MM -/* 465 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 477 -/* 469 */ MCD_OPC_CheckPredicate, 3, 76, 0, // Skip to: 549 -/* 473 */ MCD_OPC_Decode, 210, 1, 29, // Opcode: BEQZ16_MM -/* 477 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 489 -/* 481 */ MCD_OPC_CheckPredicate, 3, 64, 0, // Skip to: 549 -/* 485 */ MCD_OPC_Decode, 187, 11, 12, // Opcode: SH16_MM -/* 489 */ MCD_OPC_FilterValue, 43, 8, 0, // Skip to: 501 -/* 493 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 549 -/* 497 */ MCD_OPC_Decode, 157, 2, 29, // Opcode: BNEZ16_MM -/* 501 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 513 -/* 505 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 549 -/* 509 */ MCD_OPC_Decode, 253, 12, 22, // Opcode: SWSP_MM -/* 513 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 525 -/* 517 */ MCD_OPC_CheckPredicate, 4, 28, 0, // Skip to: 549 -/* 521 */ MCD_OPC_Decode, 165, 1, 30, // Opcode: B16_MM -/* 525 */ MCD_OPC_FilterValue, 58, 8, 0, // Skip to: 537 -/* 529 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 549 -/* 533 */ MCD_OPC_Decode, 236, 12, 12, // Opcode: SW16_MM -/* 537 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 549 -/* 541 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 549 -/* 545 */ MCD_OPC_Decode, 192, 7, 31, // Opcode: LI16_MM -/* 549 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 39 +/* 8 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 11 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25 +/* 16 */ MCD_OPC_CheckPredicate, 6, 114, 2, 0, // Skip to: 647 +/* 21 */ MCD_OPC_Decode, 170, 6, 31, // Opcode: ADDU16_MM +/* 25 */ MCD_OPC_FilterValue, 1, 105, 2, 0, // Skip to: 647 +/* 30 */ MCD_OPC_CheckPredicate, 6, 100, 2, 0, // Skip to: 647 +/* 35 */ MCD_OPC_Decode, 223, 22, 31, // Opcode: SUBU16_MM +/* 39 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 53 +/* 44 */ MCD_OPC_CheckPredicate, 7, 86, 2, 0, // Skip to: 647 +/* 49 */ MCD_OPC_Decode, 160, 15, 32, // Opcode: LBU16_MM +/* 53 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 67 +/* 58 */ MCD_OPC_CheckPredicate, 6, 72, 2, 0, // Skip to: 647 +/* 63 */ MCD_OPC_Decode, 208, 17, 33, // Opcode: MOVE16_MM +/* 67 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 103 +/* 72 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 75 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 89 +/* 80 */ MCD_OPC_CheckPredicate, 6, 50, 2, 0, // Skip to: 647 +/* 85 */ MCD_OPC_Decode, 220, 21, 34, // Opcode: SLL16_MM +/* 89 */ MCD_OPC_FilterValue, 1, 41, 2, 0, // Skip to: 647 +/* 94 */ MCD_OPC_CheckPredicate, 6, 36, 2, 0, // Skip to: 647 +/* 99 */ MCD_OPC_Decode, 161, 22, 34, // Opcode: SRL16_MM +/* 103 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 117 +/* 108 */ MCD_OPC_CheckPredicate, 7, 22, 2, 0, // Skip to: 647 +/* 113 */ MCD_OPC_Decode, 212, 15, 32, // Opcode: LHU16_MM +/* 117 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 131 +/* 122 */ MCD_OPC_CheckPredicate, 6, 8, 2, 0, // Skip to: 647 +/* 127 */ MCD_OPC_Decode, 221, 6, 35, // Opcode: ANDI16_MM +/* 131 */ MCD_OPC_FilterValue, 17, 8, 1, 0, // Skip to: 400 +/* 136 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 139 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 153 +/* 144 */ MCD_OPC_CheckPredicate, 6, 242, 1, 0, // Skip to: 647 +/* 149 */ MCD_OPC_Decode, 158, 19, 36, // Opcode: NOT16_MM +/* 153 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 167 +/* 158 */ MCD_OPC_CheckPredicate, 6, 228, 1, 0, // Skip to: 647 +/* 163 */ MCD_OPC_Decode, 173, 24, 37, // Opcode: XOR16_MM +/* 167 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 181 +/* 172 */ MCD_OPC_CheckPredicate, 6, 214, 1, 0, // Skip to: 647 +/* 177 */ MCD_OPC_Decode, 217, 6, 37, // Opcode: AND16_MM +/* 181 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 195 +/* 186 */ MCD_OPC_CheckPredicate, 6, 200, 1, 0, // Skip to: 647 +/* 191 */ MCD_OPC_Decode, 164, 19, 37, // Opcode: OR16_MM +/* 195 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 209 +/* 200 */ MCD_OPC_CheckPredicate, 6, 186, 1, 0, // Skip to: 647 +/* 205 */ MCD_OPC_Decode, 154, 16, 38, // Opcode: LWM16_MM +/* 209 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 223 +/* 214 */ MCD_OPC_CheckPredicate, 6, 172, 1, 0, // Skip to: 647 +/* 219 */ MCD_OPC_Decode, 151, 23, 38, // Opcode: SWM16_MM +/* 223 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 259 +/* 228 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 231 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 245 +/* 236 */ MCD_OPC_CheckPredicate, 6, 150, 1, 0, // Skip to: 647 +/* 241 */ MCD_OPC_Decode, 133, 15, 39, // Opcode: JR16_MM +/* 245 */ MCD_OPC_FilterValue, 1, 141, 1, 0, // Skip to: 647 +/* 250 */ MCD_OPC_CheckPredicate, 6, 136, 1, 0, // Skip to: 647 +/* 255 */ MCD_OPC_Decode, 136, 15, 39, // Opcode: JRC16_MM +/* 259 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 295 +/* 264 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 267 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 281 +/* 272 */ MCD_OPC_CheckPredicate, 6, 114, 1, 0, // Skip to: 647 +/* 277 */ MCD_OPC_Decode, 237, 14, 39, // Opcode: JALR16_MM +/* 281 */ MCD_OPC_FilterValue, 1, 105, 1, 0, // Skip to: 647 +/* 286 */ MCD_OPC_CheckPredicate, 6, 100, 1, 0, // Skip to: 647 +/* 291 */ MCD_OPC_Decode, 245, 14, 39, // Opcode: JALRS16_MM +/* 295 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 316 +/* 300 */ MCD_OPC_CheckPredicate, 6, 86, 1, 0, // Skip to: 647 +/* 305 */ MCD_OPC_CheckField, 5, 1, 0, 79, 1, 0, // Skip to: 647 +/* 312 */ MCD_OPC_Decode, 151, 17, 39, // Opcode: MFHI16_MM +/* 316 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 337 +/* 321 */ MCD_OPC_CheckPredicate, 6, 65, 1, 0, // Skip to: 647 +/* 326 */ MCD_OPC_CheckField, 5, 1, 0, 58, 1, 0, // Skip to: 647 +/* 333 */ MCD_OPC_Decode, 157, 17, 39, // Opcode: MFLO16_MM +/* 337 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 358 +/* 342 */ MCD_OPC_CheckPredicate, 6, 44, 1, 0, // Skip to: 647 +/* 347 */ MCD_OPC_CheckField, 4, 2, 0, 37, 1, 0, // Skip to: 647 +/* 354 */ MCD_OPC_Decode, 212, 8, 40, // Opcode: BREAK16_MM +/* 358 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 379 +/* 363 */ MCD_OPC_CheckPredicate, 6, 23, 1, 0, // Skip to: 647 +/* 368 */ MCD_OPC_CheckField, 4, 2, 0, 16, 1, 0, // Skip to: 647 +/* 375 */ MCD_OPC_Decode, 220, 20, 40, // Opcode: SDBBP16_MM +/* 379 */ MCD_OPC_FilterValue, 12, 7, 1, 0, // Skip to: 647 +/* 384 */ MCD_OPC_CheckPredicate, 6, 2, 1, 0, // Skip to: 647 +/* 389 */ MCD_OPC_CheckField, 5, 1, 0, 251, 0, 0, // Skip to: 647 +/* 396 */ MCD_OPC_Decode, 135, 15, 41, // Opcode: JRADDIUSP +/* 400 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 414 +/* 405 */ MCD_OPC_CheckPredicate, 7, 237, 0, 0, // Skip to: 647 +/* 410 */ MCD_OPC_Decode, 168, 16, 42, // Opcode: LWSP_MM +/* 414 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 450 +/* 419 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 422 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 436 +/* 427 */ MCD_OPC_CheckPredicate, 7, 215, 0, 0, // Skip to: 647 +/* 432 */ MCD_OPC_Decode, 137, 6, 43, // Opcode: ADDIUS5_MM +/* 436 */ MCD_OPC_FilterValue, 1, 206, 0, 0, // Skip to: 647 +/* 441 */ MCD_OPC_CheckPredicate, 7, 201, 0, 0, // Skip to: 647 +/* 446 */ MCD_OPC_Decode, 138, 6, 44, // Opcode: ADDIUSP_MM +/* 450 */ MCD_OPC_FilterValue, 25, 9, 0, 0, // Skip to: 464 +/* 455 */ MCD_OPC_CheckPredicate, 7, 187, 0, 0, // Skip to: 647 +/* 460 */ MCD_OPC_Decode, 147, 16, 45, // Opcode: LWGP_MM +/* 464 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 478 +/* 469 */ MCD_OPC_CheckPredicate, 7, 173, 0, 0, // Skip to: 647 +/* 474 */ MCD_OPC_Decode, 132, 16, 32, // Opcode: LW16_MM +/* 478 */ MCD_OPC_FilterValue, 27, 31, 0, 0, // Skip to: 514 +/* 483 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 486 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 500 +/* 491 */ MCD_OPC_CheckPredicate, 7, 151, 0, 0, // Skip to: 647 +/* 496 */ MCD_OPC_Decode, 134, 6, 46, // Opcode: ADDIUR2_MM +/* 500 */ MCD_OPC_FilterValue, 1, 142, 0, 0, // Skip to: 647 +/* 505 */ MCD_OPC_CheckPredicate, 7, 137, 0, 0, // Skip to: 647 +/* 510 */ MCD_OPC_Decode, 132, 6, 47, // Opcode: ADDIUR1SP_MM +/* 514 */ MCD_OPC_FilterValue, 33, 16, 0, 0, // Skip to: 535 +/* 519 */ MCD_OPC_CheckPredicate, 6, 123, 0, 0, // Skip to: 647 +/* 524 */ MCD_OPC_CheckField, 0, 1, 0, 116, 0, 0, // Skip to: 647 +/* 531 */ MCD_OPC_Decode, 212, 17, 48, // Opcode: MOVEP_MM +/* 535 */ MCD_OPC_FilterValue, 34, 9, 0, 0, // Skip to: 549 +/* 540 */ MCD_OPC_CheckPredicate, 6, 102, 0, 0, // Skip to: 647 +/* 545 */ MCD_OPC_Decode, 194, 20, 32, // Opcode: SB16_MM +/* 549 */ MCD_OPC_FilterValue, 35, 9, 0, 0, // Skip to: 563 +/* 554 */ MCD_OPC_CheckPredicate, 6, 88, 0, 0, // Skip to: 647 +/* 559 */ MCD_OPC_Decode, 198, 7, 49, // Opcode: BEQZ16_MM +/* 563 */ MCD_OPC_FilterValue, 42, 9, 0, 0, // Skip to: 577 +/* 568 */ MCD_OPC_CheckPredicate, 6, 74, 0, 0, // Skip to: 647 +/* 573 */ MCD_OPC_Decode, 144, 21, 32, // Opcode: SH16_MM +/* 577 */ MCD_OPC_FilterValue, 43, 9, 0, 0, // Skip to: 591 +/* 582 */ MCD_OPC_CheckPredicate, 6, 60, 0, 0, // Skip to: 647 +/* 587 */ MCD_OPC_Decode, 188, 8, 49, // Opcode: BNEZ16_MM +/* 591 */ MCD_OPC_FilterValue, 50, 9, 0, 0, // Skip to: 605 +/* 596 */ MCD_OPC_CheckPredicate, 6, 46, 0, 0, // Skip to: 647 +/* 601 */ MCD_OPC_Decode, 163, 23, 42, // Opcode: SWSP_MM +/* 605 */ MCD_OPC_FilterValue, 51, 9, 0, 0, // Skip to: 619 +/* 610 */ MCD_OPC_CheckPredicate, 7, 32, 0, 0, // Skip to: 647 +/* 615 */ MCD_OPC_Decode, 145, 7, 50, // Opcode: B16_MM +/* 619 */ MCD_OPC_FilterValue, 58, 9, 0, 0, // Skip to: 633 +/* 624 */ MCD_OPC_CheckPredicate, 6, 18, 0, 0, // Skip to: 647 +/* 629 */ MCD_OPC_Decode, 129, 23, 32, // Opcode: SW16_MM +/* 633 */ MCD_OPC_FilterValue, 59, 9, 0, 0, // Skip to: 647 +/* 638 */ MCD_OPC_CheckPredicate, 6, 4, 0, 0, // Skip to: 647 +/* 643 */ MCD_OPC_Decode, 231, 15, 51, // Opcode: LI16_MM +/* 647 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMicroMips32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 189, 3, // Skip to: 964 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 0, 90, 0, // Skip to: 104 -/* 14 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 17 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 68 -/* 21 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... -/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 -/* 28 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 60 -/* 32 */ MCD_OPC_Decode, 181, 12, 0, // Opcode: SSNOP_MM -/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 -/* 40 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 60 -/* 44 */ MCD_OPC_Decode, 140, 5, 0, // Opcode: EHB_MM -/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 -/* 52 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 60 -/* 56 */ MCD_OPC_Decode, 148, 10, 0, // Opcode: PAUSE_MM -/* 60 */ MCD_OPC_CheckPredicate, 3, 38, 6, // Skip to: 1638 -/* 64 */ MCD_OPC_Decode, 238, 11, 32, // Opcode: SLL_MM -/* 68 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 80 -/* 72 */ MCD_OPC_CheckPredicate, 3, 26, 6, // Skip to: 1638 -/* 76 */ MCD_OPC_Decode, 178, 12, 32, // Opcode: SRL_MM -/* 80 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 92 -/* 84 */ MCD_OPC_CheckPredicate, 3, 14, 6, // Skip to: 1638 -/* 88 */ MCD_OPC_Decode, 157, 12, 32, // Opcode: SRA_MM -/* 92 */ MCD_OPC_FilterValue, 3, 6, 6, // Skip to: 1638 -/* 96 */ MCD_OPC_CheckPredicate, 3, 2, 6, // Skip to: 1638 -/* 100 */ MCD_OPC_Decode, 250, 10, 32, // Opcode: ROTR_MM -/* 104 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 116 -/* 108 */ MCD_OPC_CheckPredicate, 3, 246, 5, // Skip to: 1638 -/* 112 */ MCD_OPC_Decode, 173, 2, 33, // Opcode: BREAK_MM -/* 116 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 128 -/* 120 */ MCD_OPC_CheckPredicate, 3, 234, 5, // Skip to: 1638 -/* 124 */ MCD_OPC_Decode, 246, 6, 34, // Opcode: INS_MM -/* 128 */ MCD_OPC_FilterValue, 16, 180, 0, // Skip to: 312 -/* 132 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 135 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 147 -/* 139 */ MCD_OPC_CheckPredicate, 3, 215, 5, // Skip to: 1638 -/* 143 */ MCD_OPC_Decode, 234, 11, 35, // Opcode: SLLV_MM -/* 147 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 159 -/* 151 */ MCD_OPC_CheckPredicate, 3, 203, 5, // Skip to: 1638 -/* 155 */ MCD_OPC_Decode, 174, 12, 35, // Opcode: SRLV_MM -/* 159 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 171 -/* 163 */ MCD_OPC_CheckPredicate, 3, 191, 5, // Skip to: 1638 -/* 167 */ MCD_OPC_Decode, 153, 12, 35, // Opcode: SRAV_MM -/* 171 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 183 -/* 175 */ MCD_OPC_CheckPredicate, 3, 179, 5, // Skip to: 1638 -/* 179 */ MCD_OPC_Decode, 249, 10, 35, // Opcode: ROTRV_MM -/* 183 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 194 -/* 187 */ MCD_OPC_CheckPredicate, 3, 167, 5, // Skip to: 1638 -/* 191 */ MCD_OPC_Decode, 72, 36, // Opcode: ADD_MM -/* 194 */ MCD_OPC_FilterValue, 5, 7, 0, // Skip to: 205 -/* 198 */ MCD_OPC_CheckPredicate, 3, 156, 5, // Skip to: 1638 -/* 202 */ MCD_OPC_Decode, 78, 36, // Opcode: ADDu_MM -/* 205 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 217 -/* 209 */ MCD_OPC_CheckPredicate, 3, 145, 5, // Skip to: 1638 -/* 213 */ MCD_OPC_Decode, 229, 12, 36, // Opcode: SUB_MM -/* 217 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 229 -/* 221 */ MCD_OPC_CheckPredicate, 3, 133, 5, // Skip to: 1638 -/* 225 */ MCD_OPC_Decode, 231, 12, 36, // Opcode: SUBu_MM -/* 229 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 241 -/* 233 */ MCD_OPC_CheckPredicate, 3, 121, 5, // Skip to: 1638 -/* 237 */ MCD_OPC_Decode, 217, 9, 36, // Opcode: MUL_MM -/* 241 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 252 -/* 245 */ MCD_OPC_CheckPredicate, 3, 109, 5, // Skip to: 1638 -/* 249 */ MCD_OPC_Decode, 88, 36, // Opcode: AND_MM -/* 252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 264 -/* 256 */ MCD_OPC_CheckPredicate, 3, 98, 5, // Skip to: 1638 -/* 260 */ MCD_OPC_Decode, 137, 10, 36, // Opcode: OR_MM -/* 264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 276 -/* 268 */ MCD_OPC_CheckPredicate, 3, 86, 5, // Skip to: 1638 -/* 272 */ MCD_OPC_Decode, 253, 9, 36, // Opcode: NOR_MM -/* 276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 288 -/* 280 */ MCD_OPC_CheckPredicate, 3, 74, 5, // Skip to: 1638 -/* 284 */ MCD_OPC_Decode, 240, 13, 36, // Opcode: XOR_MM -/* 288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 300 -/* 292 */ MCD_OPC_CheckPredicate, 3, 62, 5, // Skip to: 1638 -/* 296 */ MCD_OPC_Decode, 242, 11, 36, // Opcode: SLT_MM -/* 300 */ MCD_OPC_FilterValue, 14, 54, 5, // Skip to: 1638 -/* 304 */ MCD_OPC_CheckPredicate, 3, 50, 5, // Skip to: 1638 -/* 308 */ MCD_OPC_Decode, 251, 11, 36, // Opcode: SLTu_MM -/* 312 */ MCD_OPC_FilterValue, 24, 39, 0, // Skip to: 355 -/* 316 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 319 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 331 -/* 323 */ MCD_OPC_CheckPredicate, 3, 31, 5, // Skip to: 1638 -/* 327 */ MCD_OPC_Decode, 253, 8, 37, // Opcode: MOVN_I_MM -/* 331 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 343 -/* 335 */ MCD_OPC_CheckPredicate, 3, 19, 5, // Skip to: 1638 -/* 339 */ MCD_OPC_Decode, 145, 9, 37, // Opcode: MOVZ_I_MM -/* 343 */ MCD_OPC_FilterValue, 4, 11, 5, // Skip to: 1638 -/* 347 */ MCD_OPC_CheckPredicate, 3, 7, 5, // Skip to: 1638 -/* 351 */ MCD_OPC_Decode, 239, 7, 38, // Opcode: LWXS_MM -/* 355 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 367 -/* 359 */ MCD_OPC_CheckPredicate, 3, 251, 4, // Skip to: 1638 -/* 363 */ MCD_OPC_Decode, 160, 5, 39, // Opcode: EXT_MM -/* 367 */ MCD_OPC_FilterValue, 60, 243, 4, // Skip to: 1638 -/* 371 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... -/* 374 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 386 -/* 378 */ MCD_OPC_CheckPredicate, 3, 232, 4, // Skip to: 1638 -/* 382 */ MCD_OPC_Decode, 185, 13, 40, // Opcode: TEQ_MM -/* 386 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 398 -/* 390 */ MCD_OPC_CheckPredicate, 3, 220, 4, // Skip to: 1638 -/* 394 */ MCD_OPC_Decode, 193, 13, 40, // Opcode: TGE_MM -/* 398 */ MCD_OPC_FilterValue, 13, 123, 0, // Skip to: 525 -/* 402 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 405 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 423 -/* 409 */ MCD_OPC_CheckPredicate, 3, 201, 4, // Skip to: 1638 -/* 413 */ MCD_OPC_CheckField, 16, 10, 0, 195, 4, // Skip to: 1638 -/* 419 */ MCD_OPC_Decode, 195, 13, 0, // Opcode: TLBP_MM -/* 423 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 441 -/* 427 */ MCD_OPC_CheckPredicate, 3, 183, 4, // Skip to: 1638 -/* 431 */ MCD_OPC_CheckField, 16, 10, 0, 177, 4, // Skip to: 1638 -/* 437 */ MCD_OPC_Decode, 197, 13, 0, // Opcode: TLBR_MM -/* 441 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 459 -/* 445 */ MCD_OPC_CheckPredicate, 3, 165, 4, // Skip to: 1638 -/* 449 */ MCD_OPC_CheckField, 16, 10, 0, 159, 4, // Skip to: 1638 -/* 455 */ MCD_OPC_Decode, 199, 13, 0, // Opcode: TLBWI_MM -/* 459 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 477 -/* 463 */ MCD_OPC_CheckPredicate, 3, 147, 4, // Skip to: 1638 -/* 467 */ MCD_OPC_CheckField, 16, 10, 0, 141, 4, // Skip to: 1638 -/* 473 */ MCD_OPC_Decode, 201, 13, 0, // Opcode: TLBWR_MM -/* 477 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 489 -/* 481 */ MCD_OPC_CheckPredicate, 3, 129, 4, // Skip to: 1638 -/* 485 */ MCD_OPC_Decode, 232, 13, 41, // Opcode: WAIT_MM -/* 489 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 507 -/* 493 */ MCD_OPC_CheckPredicate, 3, 117, 4, // Skip to: 1638 -/* 497 */ MCD_OPC_CheckField, 16, 10, 0, 111, 4, // Skip to: 1638 -/* 503 */ MCD_OPC_Decode, 175, 4, 0, // Opcode: DERET_MM -/* 507 */ MCD_OPC_FilterValue, 15, 103, 4, // Skip to: 1638 -/* 511 */ MCD_OPC_CheckPredicate, 3, 99, 4, // Skip to: 1638 -/* 515 */ MCD_OPC_CheckField, 16, 10, 0, 93, 4, // Skip to: 1638 -/* 521 */ MCD_OPC_Decode, 144, 5, 0, // Opcode: ERET_MM -/* 525 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 537 -/* 529 */ MCD_OPC_CheckPredicate, 3, 81, 4, // Skip to: 1638 -/* 533 */ MCD_OPC_Decode, 192, 13, 40, // Opcode: TGEU_MM -/* 537 */ MCD_OPC_FilterValue, 29, 39, 0, // Skip to: 580 -/* 541 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 544 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 562 -/* 548 */ MCD_OPC_CheckPredicate, 3, 62, 4, // Skip to: 1638 -/* 552 */ MCD_OPC_CheckField, 21, 5, 0, 56, 4, // Skip to: 1638 -/* 558 */ MCD_OPC_Decode, 193, 4, 42, // Opcode: DI_MM -/* 562 */ MCD_OPC_FilterValue, 5, 48, 4, // Skip to: 1638 -/* 566 */ MCD_OPC_CheckPredicate, 3, 44, 4, // Skip to: 1638 -/* 570 */ MCD_OPC_CheckField, 21, 5, 0, 38, 4, // Skip to: 1638 -/* 576 */ MCD_OPC_Decode, 142, 5, 42, // Opcode: EI_MM -/* 580 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 592 -/* 584 */ MCD_OPC_CheckPredicate, 3, 26, 4, // Skip to: 1638 -/* 588 */ MCD_OPC_Decode, 208, 13, 40, // Opcode: TLT_MM -/* 592 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 604 -/* 596 */ MCD_OPC_CheckPredicate, 3, 14, 4, // Skip to: 1638 -/* 600 */ MCD_OPC_Decode, 207, 13, 40, // Opcode: TLTU_MM -/* 604 */ MCD_OPC_FilterValue, 44, 171, 0, // Skip to: 779 -/* 608 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 611 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 623 -/* 615 */ MCD_OPC_CheckPredicate, 3, 251, 3, // Skip to: 1638 -/* 619 */ MCD_OPC_Decode, 170, 11, 43, // Opcode: SEB_MM -/* 623 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 635 -/* 627 */ MCD_OPC_CheckPredicate, 3, 239, 3, // Skip to: 1638 -/* 631 */ MCD_OPC_Decode, 173, 11, 43, // Opcode: SEH_MM -/* 635 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 647 -/* 639 */ MCD_OPC_CheckPredicate, 3, 227, 3, // Skip to: 1638 -/* 643 */ MCD_OPC_Decode, 134, 3, 43, // Opcode: CLO_MM -/* 647 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 659 -/* 651 */ MCD_OPC_CheckPredicate, 3, 215, 3, // Skip to: 1638 -/* 655 */ MCD_OPC_Decode, 153, 3, 43, // Opcode: CLZ_MM -/* 659 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 671 -/* 663 */ MCD_OPC_CheckPredicate, 3, 203, 3, // Skip to: 1638 -/* 667 */ MCD_OPC_Decode, 240, 10, 44, // Opcode: RDHWR_MM -/* 671 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 683 -/* 675 */ MCD_OPC_CheckPredicate, 3, 191, 3, // Skip to: 1638 -/* 679 */ MCD_OPC_Decode, 235, 13, 43, // Opcode: WSBH_MM -/* 683 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 695 -/* 687 */ MCD_OPC_CheckPredicate, 3, 179, 3, // Skip to: 1638 -/* 691 */ MCD_OPC_Decode, 209, 9, 45, // Opcode: MULT_MM -/* 695 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 707 -/* 699 */ MCD_OPC_CheckPredicate, 3, 167, 3, // Skip to: 1638 -/* 703 */ MCD_OPC_Decode, 211, 9, 45, // Opcode: MULTu_MM -/* 707 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 719 -/* 711 */ MCD_OPC_CheckPredicate, 3, 155, 3, // Skip to: 1638 -/* 715 */ MCD_OPC_Decode, 163, 11, 45, // Opcode: SDIV_MM -/* 719 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 731 -/* 723 */ MCD_OPC_CheckPredicate, 3, 143, 3, // Skip to: 1638 -/* 727 */ MCD_OPC_Decode, 223, 13, 45, // Opcode: UDIV_MM -/* 731 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 743 -/* 735 */ MCD_OPC_CheckPredicate, 3, 131, 3, // Skip to: 1638 -/* 739 */ MCD_OPC_Decode, 146, 8, 45, // Opcode: MADD_MM -/* 743 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 755 -/* 747 */ MCD_OPC_CheckPredicate, 3, 119, 3, // Skip to: 1638 -/* 751 */ MCD_OPC_Decode, 137, 8, 45, // Opcode: MADDU_MM -/* 755 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 767 -/* 759 */ MCD_OPC_CheckPredicate, 3, 107, 3, // Skip to: 1638 -/* 763 */ MCD_OPC_Decode, 164, 9, 45, // Opcode: MSUB_MM -/* 767 */ MCD_OPC_FilterValue, 15, 99, 3, // Skip to: 1638 -/* 771 */ MCD_OPC_CheckPredicate, 3, 95, 3, // Skip to: 1638 -/* 775 */ MCD_OPC_Decode, 155, 9, 45, // Opcode: MSUBU_MM -/* 779 */ MCD_OPC_FilterValue, 45, 45, 0, // Skip to: 828 -/* 783 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 786 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 804 -/* 790 */ MCD_OPC_CheckPredicate, 3, 76, 3, // Skip to: 1638 -/* 794 */ MCD_OPC_CheckField, 21, 5, 0, 70, 3, // Skip to: 1638 -/* 800 */ MCD_OPC_Decode, 131, 13, 46, // Opcode: SYNC_MM -/* 804 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 816 -/* 808 */ MCD_OPC_CheckPredicate, 3, 58, 3, // Skip to: 1638 -/* 812 */ MCD_OPC_Decode, 133, 13, 41, // Opcode: SYSCALL_MM -/* 816 */ MCD_OPC_FilterValue, 13, 50, 3, // Skip to: 1638 -/* 820 */ MCD_OPC_CheckPredicate, 3, 46, 3, // Skip to: 1638 -/* 824 */ MCD_OPC_Decode, 154, 11, 41, // Opcode: SDBBP_MM -/* 828 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 840 -/* 832 */ MCD_OPC_CheckPredicate, 3, 34, 3, // Skip to: 1638 -/* 836 */ MCD_OPC_Decode, 212, 13, 40, // Opcode: TNE_MM -/* 840 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 919 -/* 844 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 847 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 865 -/* 851 */ MCD_OPC_CheckPredicate, 3, 15, 3, // Skip to: 1638 -/* 855 */ MCD_OPC_CheckField, 21, 5, 0, 9, 3, // Skip to: 1638 -/* 861 */ MCD_OPC_Decode, 190, 8, 42, // Opcode: MFHI_MM -/* 865 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 883 -/* 869 */ MCD_OPC_CheckPredicate, 3, 253, 2, // Skip to: 1638 -/* 873 */ MCD_OPC_CheckField, 21, 5, 0, 247, 2, // Skip to: 1638 -/* 879 */ MCD_OPC_Decode, 195, 8, 42, // Opcode: MFLO_MM -/* 883 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 901 -/* 887 */ MCD_OPC_CheckPredicate, 3, 235, 2, // Skip to: 1638 -/* 891 */ MCD_OPC_CheckField, 21, 5, 0, 229, 2, // Skip to: 1638 -/* 897 */ MCD_OPC_Decode, 179, 9, 42, // Opcode: MTHI_MM -/* 901 */ MCD_OPC_FilterValue, 3, 221, 2, // Skip to: 1638 -/* 905 */ MCD_OPC_CheckPredicate, 3, 217, 2, // Skip to: 1638 -/* 909 */ MCD_OPC_CheckField, 21, 5, 0, 211, 2, // Skip to: 1638 -/* 915 */ MCD_OPC_Decode, 184, 9, 42, // Opcode: MTLO_MM -/* 919 */ MCD_OPC_FilterValue, 60, 203, 2, // Skip to: 1638 -/* 923 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 926 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 952 -/* 930 */ MCD_OPC_CheckPredicate, 3, 10, 0, // Skip to: 944 -/* 934 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 944 -/* 940 */ MCD_OPC_Decode, 143, 7, 42, // Opcode: JR_MM -/* 944 */ MCD_OPC_CheckPredicate, 3, 178, 2, // Skip to: 1638 -/* 948 */ MCD_OPC_Decode, 129, 7, 43, // Opcode: JALR_MM -/* 952 */ MCD_OPC_FilterValue, 4, 170, 2, // Skip to: 1638 -/* 956 */ MCD_OPC_CheckPredicate, 3, 166, 2, // Skip to: 1638 -/* 960 */ MCD_OPC_Decode, 255, 6, 43, // Opcode: JALRS_MM -/* 964 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 975 -/* 968 */ MCD_OPC_CheckPredicate, 3, 154, 2, // Skip to: 1638 -/* 972 */ MCD_OPC_Decode, 74, 47, // Opcode: ADDi_MM -/* 975 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 987 -/* 979 */ MCD_OPC_CheckPredicate, 3, 143, 2, // Skip to: 1638 -/* 983 */ MCD_OPC_Decode, 160, 7, 48, // Opcode: LBu_MM -/* 987 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 999 -/* 991 */ MCD_OPC_CheckPredicate, 3, 131, 2, // Skip to: 1638 -/* 995 */ MCD_OPC_Decode, 145, 11, 48, // Opcode: SB_MM -/* 999 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1011 -/* 1003 */ MCD_OPC_CheckPredicate, 3, 119, 2, // Skip to: 1638 -/* 1007 */ MCD_OPC_Decode, 157, 7, 48, // Opcode: LB_MM -/* 1011 */ MCD_OPC_FilterValue, 8, 63, 0, // Skip to: 1078 -/* 1015 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 1018 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1030 -/* 1022 */ MCD_OPC_CheckPredicate, 3, 100, 2, // Skip to: 1638 -/* 1026 */ MCD_OPC_Decode, 229, 7, 49, // Opcode: LWP_MM -/* 1030 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1042 -/* 1034 */ MCD_OPC_CheckPredicate, 3, 88, 2, // Skip to: 1638 -/* 1038 */ MCD_OPC_Decode, 226, 7, 49, // Opcode: LWM32_MM -/* 1042 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1054 -/* 1046 */ MCD_OPC_CheckPredicate, 3, 76, 2, // Skip to: 1638 -/* 1050 */ MCD_OPC_Decode, 221, 2, 50, // Opcode: CACHE_MM -/* 1054 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1066 -/* 1058 */ MCD_OPC_CheckPredicate, 3, 64, 2, // Skip to: 1638 -/* 1062 */ MCD_OPC_Decode, 249, 12, 49, // Opcode: SWP_MM -/* 1066 */ MCD_OPC_FilterValue, 13, 56, 2, // Skip to: 1638 -/* 1070 */ MCD_OPC_CheckPredicate, 3, 52, 2, // Skip to: 1638 -/* 1074 */ MCD_OPC_Decode, 247, 12, 49, // Opcode: SWM32_MM -/* 1078 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1089 -/* 1082 */ MCD_OPC_CheckPredicate, 3, 40, 2, // Skip to: 1638 -/* 1086 */ MCD_OPC_Decode, 76, 47, // Opcode: ADDiu_MM -/* 1089 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1101 -/* 1093 */ MCD_OPC_CheckPredicate, 3, 29, 2, // Skip to: 1638 -/* 1097 */ MCD_OPC_Decode, 191, 7, 48, // Opcode: LHu_MM -/* 1101 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1113 -/* 1105 */ MCD_OPC_CheckPredicate, 3, 17, 2, // Skip to: 1638 -/* 1109 */ MCD_OPC_Decode, 216, 11, 48, // Opcode: SH_MM -/* 1113 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1125 -/* 1117 */ MCD_OPC_CheckPredicate, 3, 5, 2, // Skip to: 1638 -/* 1121 */ MCD_OPC_Decode, 188, 7, 48, // Opcode: LH_MM -/* 1125 */ MCD_OPC_FilterValue, 16, 207, 0, // Skip to: 1336 -/* 1129 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1144 -/* 1136 */ MCD_OPC_CheckPredicate, 3, 242, 1, // Skip to: 1638 -/* 1140 */ MCD_OPC_Decode, 140, 2, 51, // Opcode: BLTZ_MM -/* 1144 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1156 -/* 1148 */ MCD_OPC_CheckPredicate, 3, 230, 1, // Skip to: 1638 -/* 1152 */ MCD_OPC_Decode, 137, 2, 51, // Opcode: BLTZAL_MM -/* 1156 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1168 -/* 1160 */ MCD_OPC_CheckPredicate, 3, 218, 1, // Skip to: 1638 -/* 1164 */ MCD_OPC_Decode, 226, 1, 51, // Opcode: BGEZ_MM -/* 1168 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1180 -/* 1172 */ MCD_OPC_CheckPredicate, 3, 206, 1, // Skip to: 1638 -/* 1176 */ MCD_OPC_Decode, 223, 1, 51, // Opcode: BGEZAL_MM -/* 1180 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1192 -/* 1184 */ MCD_OPC_CheckPredicate, 3, 194, 1, // Skip to: 1638 -/* 1188 */ MCD_OPC_Decode, 128, 2, 51, // Opcode: BLEZ_MM -/* 1192 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1204 -/* 1196 */ MCD_OPC_CheckPredicate, 3, 182, 1, // Skip to: 1638 -/* 1200 */ MCD_OPC_Decode, 160, 2, 51, // Opcode: BNEZC_MM -/* 1204 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1216 -/* 1208 */ MCD_OPC_CheckPredicate, 3, 170, 1, // Skip to: 1638 -/* 1212 */ MCD_OPC_Decode, 232, 1, 51, // Opcode: BGTZ_MM -/* 1216 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1228 -/* 1220 */ MCD_OPC_CheckPredicate, 3, 158, 1, // Skip to: 1638 -/* 1224 */ MCD_OPC_Decode, 213, 1, 51, // Opcode: BEQZC_MM -/* 1228 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1240 -/* 1232 */ MCD_OPC_CheckPredicate, 3, 146, 1, // Skip to: 1638 -/* 1236 */ MCD_OPC_Decode, 205, 13, 52, // Opcode: TLTI_MM -/* 1240 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1252 -/* 1244 */ MCD_OPC_CheckPredicate, 3, 134, 1, // Skip to: 1638 -/* 1248 */ MCD_OPC_Decode, 190, 13, 52, // Opcode: TGEI_MM -/* 1252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1264 -/* 1256 */ MCD_OPC_CheckPredicate, 3, 122, 1, // Skip to: 1638 -/* 1260 */ MCD_OPC_Decode, 204, 13, 52, // Opcode: TLTIU_MM -/* 1264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1276 -/* 1268 */ MCD_OPC_CheckPredicate, 3, 110, 1, // Skip to: 1638 -/* 1272 */ MCD_OPC_Decode, 189, 13, 52, // Opcode: TGEIU_MM -/* 1276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1288 -/* 1280 */ MCD_OPC_CheckPredicate, 3, 98, 1, // Skip to: 1638 -/* 1284 */ MCD_OPC_Decode, 211, 13, 52, // Opcode: TNEI_MM -/* 1288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1300 -/* 1292 */ MCD_OPC_CheckPredicate, 3, 86, 1, // Skip to: 1638 -/* 1296 */ MCD_OPC_Decode, 212, 7, 52, // Opcode: LUi_MM -/* 1300 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1312 -/* 1304 */ MCD_OPC_CheckPredicate, 3, 74, 1, // Skip to: 1638 -/* 1308 */ MCD_OPC_Decode, 184, 13, 52, // Opcode: TEQI_MM -/* 1312 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1324 -/* 1316 */ MCD_OPC_CheckPredicate, 3, 62, 1, // Skip to: 1638 -/* 1320 */ MCD_OPC_Decode, 136, 2, 51, // Opcode: BLTZALS_MM -/* 1324 */ MCD_OPC_FilterValue, 19, 54, 1, // Skip to: 1638 -/* 1328 */ MCD_OPC_CheckPredicate, 3, 50, 1, // Skip to: 1638 -/* 1332 */ MCD_OPC_Decode, 222, 1, 51, // Opcode: BGEZALS_MM -/* 1336 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 1348 -/* 1340 */ MCD_OPC_CheckPredicate, 3, 38, 1, // Skip to: 1638 -/* 1344 */ MCD_OPC_Decode, 144, 10, 53, // Opcode: ORi_MM -/* 1348 */ MCD_OPC_FilterValue, 21, 29, 0, // Skip to: 1381 -/* 1352 */ MCD_OPC_ExtractField, 0, 13, // Inst{12-0} ... -/* 1355 */ MCD_OPC_FilterValue, 251, 2, 8, 0, // Skip to: 1368 -/* 1360 */ MCD_OPC_CheckPredicate, 3, 18, 1, // Skip to: 1638 -/* 1364 */ MCD_OPC_Decode, 241, 8, 54, // Opcode: MOVF_I_MM -/* 1368 */ MCD_OPC_FilterValue, 251, 18, 9, 1, // Skip to: 1638 -/* 1373 */ MCD_OPC_CheckPredicate, 3, 5, 1, // Skip to: 1638 -/* 1377 */ MCD_OPC_Decode, 133, 9, 54, // Opcode: MOVT_I_MM -/* 1381 */ MCD_OPC_FilterValue, 24, 99, 0, // Skip to: 1484 -/* 1385 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 1388 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1400 -/* 1392 */ MCD_OPC_CheckPredicate, 3, 242, 0, // Skip to: 1638 -/* 1396 */ MCD_OPC_Decode, 224, 7, 49, // Opcode: LWL_MM -/* 1400 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1412 -/* 1404 */ MCD_OPC_CheckPredicate, 3, 230, 0, // Skip to: 1638 -/* 1408 */ MCD_OPC_Decode, 232, 7, 49, // Opcode: LWR_MM -/* 1412 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1424 -/* 1416 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 1638 -/* 1420 */ MCD_OPC_Decode, 182, 10, 50, // Opcode: PREF_MM -/* 1424 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1436 -/* 1428 */ MCD_OPC_CheckPredicate, 3, 206, 0, // Skip to: 1638 -/* 1432 */ MCD_OPC_Decode, 196, 7, 49, // Opcode: LL_MM -/* 1436 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1448 -/* 1440 */ MCD_OPC_CheckPredicate, 3, 194, 0, // Skip to: 1638 -/* 1444 */ MCD_OPC_Decode, 245, 12, 49, // Opcode: SWL_MM -/* 1448 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1460 -/* 1452 */ MCD_OPC_CheckPredicate, 3, 182, 0, // Skip to: 1638 -/* 1456 */ MCD_OPC_Decode, 252, 12, 49, // Opcode: SWR_MM -/* 1460 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1472 -/* 1464 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 1638 -/* 1468 */ MCD_OPC_Decode, 149, 11, 49, // Opcode: SC_MM -/* 1472 */ MCD_OPC_FilterValue, 14, 162, 0, // Skip to: 1638 -/* 1476 */ MCD_OPC_CheckPredicate, 3, 158, 0, // Skip to: 1638 -/* 1480 */ MCD_OPC_Decode, 235, 7, 49, // Opcode: LWU_MM -/* 1484 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1496 -/* 1488 */ MCD_OPC_CheckPredicate, 3, 146, 0, // Skip to: 1638 -/* 1492 */ MCD_OPC_Decode, 247, 13, 53, // Opcode: XORi_MM -/* 1496 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1508 -/* 1500 */ MCD_OPC_CheckPredicate, 3, 134, 0, // Skip to: 1638 -/* 1504 */ MCD_OPC_Decode, 130, 7, 55, // Opcode: JALS_MM -/* 1508 */ MCD_OPC_FilterValue, 30, 7, 0, // Skip to: 1519 -/* 1512 */ MCD_OPC_CheckPredicate, 3, 122, 0, // Skip to: 1638 -/* 1516 */ MCD_OPC_Decode, 27, 56, // Opcode: ADDIUPC_MM -/* 1519 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 1531 -/* 1523 */ MCD_OPC_CheckPredicate, 3, 111, 0, // Skip to: 1638 -/* 1527 */ MCD_OPC_Decode, 245, 11, 47, // Opcode: SLTi_MM -/* 1531 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 1543 -/* 1535 */ MCD_OPC_CheckPredicate, 3, 99, 0, // Skip to: 1638 -/* 1539 */ MCD_OPC_Decode, 214, 1, 57, // Opcode: BEQ_MM -/* 1543 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 1555 -/* 1547 */ MCD_OPC_CheckPredicate, 3, 87, 0, // Skip to: 1638 -/* 1551 */ MCD_OPC_Decode, 248, 11, 47, // Opcode: SLTiu_MM -/* 1555 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 1567 -/* 1559 */ MCD_OPC_CheckPredicate, 3, 75, 0, // Skip to: 1638 -/* 1563 */ MCD_OPC_Decode, 161, 2, 57, // Opcode: BNE_MM -/* 1567 */ MCD_OPC_FilterValue, 52, 7, 0, // Skip to: 1578 -/* 1571 */ MCD_OPC_CheckPredicate, 3, 63, 0, // Skip to: 1638 -/* 1575 */ MCD_OPC_Decode, 95, 53, // Opcode: ANDi_MM -/* 1578 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 1590 -/* 1582 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 1638 -/* 1586 */ MCD_OPC_Decode, 144, 7, 55, // Opcode: J_MM -/* 1590 */ MCD_OPC_FilterValue, 60, 8, 0, // Skip to: 1602 -/* 1594 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 1638 -/* 1598 */ MCD_OPC_Decode, 132, 7, 55, // Opcode: JALX_MM -/* 1602 */ MCD_OPC_FilterValue, 61, 8, 0, // Skip to: 1614 -/* 1606 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 1638 -/* 1610 */ MCD_OPC_Decode, 133, 7, 55, // Opcode: JAL_MM -/* 1614 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 1626 -/* 1618 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 1638 -/* 1622 */ MCD_OPC_Decode, 128, 13, 48, // Opcode: SW_MM -/* 1626 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 1638 -/* 1630 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 1638 -/* 1634 */ MCD_OPC_Decode, 240, 7, 48, // Opcode: LW_MM -/* 1638 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 0, 238, 14, 0, // Skip to: 3830 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 0, 104, 0, 0, // Skip to: 120 +/* 16 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 19 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 78 +/* 24 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... +/* 27 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 41 +/* 32 */ MCD_OPC_CheckPredicate, 7, 32, 0, 0, // Skip to: 69 +/* 37 */ MCD_OPC_Decode, 186, 22, 10, // Opcode: SSNOP_MM +/* 41 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 55 +/* 46 */ MCD_OPC_CheckPredicate, 7, 18, 0, 0, // Skip to: 69 +/* 51 */ MCD_OPC_Decode, 207, 12, 10, // Opcode: EHB_MM +/* 55 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 69 +/* 60 */ MCD_OPC_CheckPredicate, 7, 4, 0, 0, // Skip to: 69 +/* 65 */ MCD_OPC_Decode, 182, 19, 10, // Opcode: PAUSE_MM +/* 69 */ MCD_OPC_CheckPredicate, 7, 101, 25, 0, // Skip to: 6575 +/* 74 */ MCD_OPC_Decode, 235, 21, 52, // Opcode: SLL_MM +/* 78 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 92 +/* 83 */ MCD_OPC_CheckPredicate, 7, 87, 25, 0, // Skip to: 6575 +/* 88 */ MCD_OPC_Decode, 182, 22, 52, // Opcode: SRL_MM +/* 92 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 106 +/* 97 */ MCD_OPC_CheckPredicate, 7, 73, 25, 0, // Skip to: 6575 +/* 102 */ MCD_OPC_Decode, 157, 22, 52, // Opcode: SRA_MM +/* 106 */ MCD_OPC_FilterValue, 3, 64, 25, 0, // Skip to: 6575 +/* 111 */ MCD_OPC_CheckPredicate, 7, 59, 25, 0, // Skip to: 6575 +/* 116 */ MCD_OPC_Decode, 159, 20, 52, // Opcode: ROTR_MM +/* 120 */ MCD_OPC_FilterValue, 5, 227, 0, 0, // Skip to: 352 +/* 125 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 128 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 149 +/* 133 */ MCD_OPC_CheckPredicate, 8, 37, 25, 0, // Skip to: 6575 +/* 138 */ MCD_OPC_CheckField, 11, 5, 0, 30, 25, 0, // Skip to: 6575 +/* 145 */ MCD_OPC_Decode, 221, 9, 53, // Opcode: CMP_EQ_PH_MM +/* 149 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 170 +/* 154 */ MCD_OPC_CheckPredicate, 8, 16, 25, 0, // Skip to: 6575 +/* 159 */ MCD_OPC_CheckField, 11, 5, 0, 9, 25, 0, // Skip to: 6575 +/* 166 */ MCD_OPC_Decode, 235, 9, 53, // Opcode: CMP_LT_PH_MM +/* 170 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 191 +/* 175 */ MCD_OPC_CheckPredicate, 8, 251, 24, 0, // Skip to: 6575 +/* 180 */ MCD_OPC_CheckField, 11, 5, 0, 244, 24, 0, // Skip to: 6575 +/* 187 */ MCD_OPC_Decode, 229, 9, 53, // Opcode: CMP_LE_PH_MM +/* 191 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 205 +/* 196 */ MCD_OPC_CheckPredicate, 9, 230, 24, 0, // Skip to: 6575 +/* 201 */ MCD_OPC_Decode, 199, 9, 54, // Opcode: CMPGDU_EQ_QB_MMR2 +/* 205 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 219 +/* 210 */ MCD_OPC_CheckPredicate, 9, 216, 24, 0, // Skip to: 6575 +/* 215 */ MCD_OPC_Decode, 203, 9, 54, // Opcode: CMPGDU_LT_QB_MMR2 +/* 219 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 233 +/* 224 */ MCD_OPC_CheckPredicate, 9, 202, 24, 0, // Skip to: 6575 +/* 229 */ MCD_OPC_Decode, 201, 9, 54, // Opcode: CMPGDU_LE_QB_MMR2 +/* 233 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 254 +/* 238 */ MCD_OPC_CheckPredicate, 8, 188, 24, 0, // Skip to: 6575 +/* 243 */ MCD_OPC_CheckField, 11, 5, 0, 181, 24, 0, // Skip to: 6575 +/* 250 */ MCD_OPC_Decode, 211, 9, 53, // Opcode: CMPU_EQ_QB_MM +/* 254 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 275 +/* 259 */ MCD_OPC_CheckPredicate, 8, 167, 24, 0, // Skip to: 6575 +/* 264 */ MCD_OPC_CheckField, 11, 5, 0, 160, 24, 0, // Skip to: 6575 +/* 271 */ MCD_OPC_Decode, 215, 9, 53, // Opcode: CMPU_LT_QB_MM +/* 275 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 296 +/* 280 */ MCD_OPC_CheckPredicate, 8, 146, 24, 0, // Skip to: 6575 +/* 285 */ MCD_OPC_CheckField, 11, 5, 0, 139, 24, 0, // Skip to: 6575 +/* 292 */ MCD_OPC_Decode, 213, 9, 53, // Opcode: CMPU_LE_QB_MM +/* 296 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 310 +/* 301 */ MCD_OPC_CheckPredicate, 8, 125, 24, 0, // Skip to: 6575 +/* 306 */ MCD_OPC_Decode, 154, 6, 55, // Opcode: ADDQ_S_W_MM +/* 310 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 324 +/* 315 */ MCD_OPC_CheckPredicate, 8, 111, 24, 0, // Skip to: 6575 +/* 320 */ MCD_OPC_Decode, 206, 22, 55, // Opcode: SUBQ_S_W_MM +/* 324 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 338 +/* 329 */ MCD_OPC_CheckPredicate, 8, 97, 24, 0, // Skip to: 6575 +/* 334 */ MCD_OPC_Decode, 157, 6, 55, // Opcode: ADDSC_MM +/* 338 */ MCD_OPC_FilterValue, 15, 88, 24, 0, // Skip to: 6575 +/* 343 */ MCD_OPC_CheckPredicate, 8, 83, 24, 0, // Skip to: 6575 +/* 348 */ MCD_OPC_Decode, 194, 6, 55, // Opcode: ADDWC_MM +/* 352 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 366 +/* 357 */ MCD_OPC_CheckPredicate, 7, 69, 24, 0, // Skip to: 6575 +/* 362 */ MCD_OPC_Decode, 215, 8, 56, // Opcode: BREAK_MM +/* 366 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 380 +/* 371 */ MCD_OPC_CheckPredicate, 6, 55, 24, 0, // Skip to: 6575 +/* 376 */ MCD_OPC_Decode, 231, 14, 57, // Opcode: INS_MM +/* 380 */ MCD_OPC_FilterValue, 13, 167, 1, 0, // Skip to: 808 +/* 385 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 388 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 402 +/* 393 */ MCD_OPC_CheckPredicate, 8, 33, 24, 0, // Skip to: 6575 +/* 398 */ MCD_OPC_Decode, 150, 6, 58, // Opcode: ADDQ_PH_MM +/* 402 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 416 +/* 407 */ MCD_OPC_CheckPredicate, 9, 19, 24, 0, // Skip to: 6575 +/* 412 */ MCD_OPC_Decode, 142, 6, 58, // Opcode: ADDQH_PH_MMR2 +/* 416 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 430 +/* 421 */ MCD_OPC_CheckPredicate, 9, 5, 24, 0, // Skip to: 6575 +/* 426 */ MCD_OPC_Decode, 148, 6, 55, // Opcode: ADDQH_W_MMR2 +/* 430 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 444 +/* 435 */ MCD_OPC_CheckPredicate, 8, 247, 23, 0, // Skip to: 6575 +/* 440 */ MCD_OPC_Decode, 180, 6, 58, // Opcode: ADDU_QB_MM +/* 444 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 458 +/* 449 */ MCD_OPC_CheckPredicate, 9, 233, 23, 0, // Skip to: 6575 +/* 454 */ MCD_OPC_Decode, 178, 6, 58, // Opcode: ADDU_PH_MMR2 +/* 458 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 472 +/* 463 */ MCD_OPC_CheckPredicate, 9, 219, 23, 0, // Skip to: 6575 +/* 468 */ MCD_OPC_Decode, 173, 6, 58, // Opcode: ADDUH_QB_MMR2 +/* 472 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 486 +/* 477 */ MCD_OPC_CheckPredicate, 8, 205, 23, 0, // Skip to: 6575 +/* 482 */ MCD_OPC_Decode, 175, 21, 59, // Opcode: SHRAV_PH_MM +/* 486 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 500 +/* 491 */ MCD_OPC_CheckPredicate, 9, 191, 23, 0, // Skip to: 6575 +/* 496 */ MCD_OPC_Decode, 177, 21, 59, // Opcode: SHRAV_QB_MMR2 +/* 500 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 514 +/* 505 */ MCD_OPC_CheckPredicate, 8, 177, 23, 0, // Skip to: 6575 +/* 510 */ MCD_OPC_Decode, 202, 22, 58, // Opcode: SUBQ_PH_MM +/* 514 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 528 +/* 519 */ MCD_OPC_CheckPredicate, 9, 163, 23, 0, // Skip to: 6575 +/* 524 */ MCD_OPC_Decode, 194, 22, 58, // Opcode: SUBQH_PH_MMR2 +/* 528 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 542 +/* 533 */ MCD_OPC_CheckPredicate, 9, 149, 23, 0, // Skip to: 6575 +/* 538 */ MCD_OPC_Decode, 200, 22, 55, // Opcode: SUBQH_W_MMR2 +/* 542 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 556 +/* 547 */ MCD_OPC_CheckPredicate, 8, 135, 23, 0, // Skip to: 6575 +/* 552 */ MCD_OPC_Decode, 233, 22, 58, // Opcode: SUBU_QB_MM +/* 556 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 570 +/* 561 */ MCD_OPC_CheckPredicate, 9, 121, 23, 0, // Skip to: 6575 +/* 566 */ MCD_OPC_Decode, 231, 22, 58, // Opcode: SUBU_PH_MMR2 +/* 570 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 584 +/* 575 */ MCD_OPC_CheckPredicate, 9, 107, 23, 0, // Skip to: 6575 +/* 580 */ MCD_OPC_Decode, 226, 22, 58, // Opcode: SUBUH_QB_MMR2 +/* 584 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 598 +/* 589 */ MCD_OPC_CheckPredicate, 9, 93, 23, 0, // Skip to: 6575 +/* 594 */ MCD_OPC_Decode, 235, 19, 60, // Opcode: PRECR_SRA_PH_W_MMR2 +/* 598 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 612 +/* 603 */ MCD_OPC_CheckPredicate, 8, 79, 23, 0, // Skip to: 6575 +/* 608 */ MCD_OPC_Decode, 152, 6, 58, // Opcode: ADDQ_S_PH_MM +/* 612 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 626 +/* 617 */ MCD_OPC_CheckPredicate, 9, 65, 23, 0, // Skip to: 6575 +/* 622 */ MCD_OPC_Decode, 144, 6, 58, // Opcode: ADDQH_R_PH_MMR2 +/* 626 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 640 +/* 631 */ MCD_OPC_CheckPredicate, 9, 51, 23, 0, // Skip to: 6575 +/* 636 */ MCD_OPC_Decode, 146, 6, 55, // Opcode: ADDQH_R_W_MMR2 +/* 640 */ MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 654 +/* 645 */ MCD_OPC_CheckPredicate, 8, 37, 23, 0, // Skip to: 6575 +/* 650 */ MCD_OPC_Decode, 184, 6, 58, // Opcode: ADDU_S_QB_MM +/* 654 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 668 +/* 659 */ MCD_OPC_CheckPredicate, 9, 23, 23, 0, // Skip to: 6575 +/* 664 */ MCD_OPC_Decode, 182, 6, 58, // Opcode: ADDU_S_PH_MMR2 +/* 668 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 682 +/* 673 */ MCD_OPC_CheckPredicate, 9, 9, 23, 0, // Skip to: 6575 +/* 678 */ MCD_OPC_Decode, 175, 6, 58, // Opcode: ADDUH_R_QB_MMR2 +/* 682 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 696 +/* 687 */ MCD_OPC_CheckPredicate, 8, 251, 22, 0, // Skip to: 6575 +/* 692 */ MCD_OPC_Decode, 179, 21, 59, // Opcode: SHRAV_R_PH_MM +/* 696 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 710 +/* 701 */ MCD_OPC_CheckPredicate, 9, 237, 22, 0, // Skip to: 6575 +/* 706 */ MCD_OPC_Decode, 181, 21, 59, // Opcode: SHRAV_R_QB_MMR2 +/* 710 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 724 +/* 715 */ MCD_OPC_CheckPredicate, 8, 223, 22, 0, // Skip to: 6575 +/* 720 */ MCD_OPC_Decode, 204, 22, 58, // Opcode: SUBQ_S_PH_MM +/* 724 */ MCD_OPC_FilterValue, 25, 9, 0, 0, // Skip to: 738 +/* 729 */ MCD_OPC_CheckPredicate, 9, 209, 22, 0, // Skip to: 6575 +/* 734 */ MCD_OPC_Decode, 196, 22, 58, // Opcode: SUBQH_R_PH_MMR2 +/* 738 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 752 +/* 743 */ MCD_OPC_CheckPredicate, 9, 195, 22, 0, // Skip to: 6575 +/* 748 */ MCD_OPC_Decode, 198, 22, 55, // Opcode: SUBQH_R_W_MMR2 +/* 752 */ MCD_OPC_FilterValue, 27, 9, 0, 0, // Skip to: 766 +/* 757 */ MCD_OPC_CheckPredicate, 8, 181, 22, 0, // Skip to: 6575 +/* 762 */ MCD_OPC_Decode, 237, 22, 58, // Opcode: SUBU_S_QB_MM +/* 766 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 780 +/* 771 */ MCD_OPC_CheckPredicate, 9, 167, 22, 0, // Skip to: 6575 +/* 776 */ MCD_OPC_Decode, 235, 22, 58, // Opcode: SUBU_S_PH_MMR2 +/* 780 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 794 +/* 785 */ MCD_OPC_CheckPredicate, 9, 153, 22, 0, // Skip to: 6575 +/* 790 */ MCD_OPC_Decode, 228, 22, 58, // Opcode: SUBUH_R_QB_MMR2 +/* 794 */ MCD_OPC_FilterValue, 31, 144, 22, 0, // Skip to: 6575 +/* 799 */ MCD_OPC_CheckPredicate, 9, 139, 22, 0, // Skip to: 6575 +/* 804 */ MCD_OPC_Decode, 237, 19, 60, // Opcode: PRECR_SRA_R_PH_W_MMR2 +/* 808 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 844 +/* 813 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 816 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 830 +/* 821 */ MCD_OPC_CheckPredicate, 8, 117, 22, 0, // Skip to: 6575 +/* 826 */ MCD_OPC_Decode, 159, 21, 59, // Opcode: SHLLV_PH_MM +/* 830 */ MCD_OPC_FilterValue, 16, 108, 22, 0, // Skip to: 6575 +/* 835 */ MCD_OPC_CheckPredicate, 8, 103, 22, 0, // Skip to: 6575 +/* 840 */ MCD_OPC_Decode, 163, 21, 59, // Opcode: SHLLV_S_PH_MM +/* 844 */ MCD_OPC_FilterValue, 16, 213, 0, 0, // Skip to: 1062 +/* 849 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 852 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 866 +/* 857 */ MCD_OPC_CheckPredicate, 7, 81, 22, 0, // Skip to: 6575 +/* 862 */ MCD_OPC_Decode, 230, 21, 61, // Opcode: SLLV_MM +/* 866 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 880 +/* 871 */ MCD_OPC_CheckPredicate, 7, 67, 22, 0, // Skip to: 6575 +/* 876 */ MCD_OPC_Decode, 177, 22, 61, // Opcode: SRLV_MM +/* 880 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 894 +/* 885 */ MCD_OPC_CheckPredicate, 7, 53, 22, 0, // Skip to: 6575 +/* 890 */ MCD_OPC_Decode, 152, 22, 61, // Opcode: SRAV_MM +/* 894 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 908 +/* 899 */ MCD_OPC_CheckPredicate, 7, 39, 22, 0, // Skip to: 6575 +/* 904 */ MCD_OPC_Decode, 157, 20, 61, // Opcode: ROTRV_MM +/* 908 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 922 +/* 913 */ MCD_OPC_CheckPredicate, 6, 25, 22, 0, // Skip to: 6575 +/* 918 */ MCD_OPC_Decode, 199, 6, 55, // Opcode: ADD_MM +/* 922 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 936 +/* 927 */ MCD_OPC_CheckPredicate, 6, 11, 22, 0, // Skip to: 6575 +/* 932 */ MCD_OPC_Decode, 209, 6, 55, // Opcode: ADDu_MM +/* 936 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 950 +/* 941 */ MCD_OPC_CheckPredicate, 6, 253, 21, 0, // Skip to: 6575 +/* 946 */ MCD_OPC_Decode, 246, 22, 55, // Opcode: SUB_MM +/* 950 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 964 +/* 955 */ MCD_OPC_CheckPredicate, 6, 239, 21, 0, // Skip to: 6575 +/* 960 */ MCD_OPC_Decode, 251, 22, 55, // Opcode: SUBu_MM +/* 964 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 978 +/* 969 */ MCD_OPC_CheckPredicate, 6, 225, 21, 0, // Skip to: 6575 +/* 974 */ MCD_OPC_Decode, 245, 18, 55, // Opcode: MUL_MM +/* 978 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 992 +/* 983 */ MCD_OPC_CheckPredicate, 6, 211, 21, 0, // Skip to: 6575 +/* 988 */ MCD_OPC_Decode, 227, 6, 55, // Opcode: AND_MM +/* 992 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 1006 +/* 997 */ MCD_OPC_CheckPredicate, 6, 197, 21, 0, // Skip to: 6575 +/* 1002 */ MCD_OPC_Decode, 171, 19, 55, // Opcode: OR_MM +/* 1006 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 1020 +/* 1011 */ MCD_OPC_CheckPredicate, 6, 183, 21, 0, // Skip to: 6575 +/* 1016 */ MCD_OPC_Decode, 154, 19, 55, // Opcode: NOR_MM +/* 1020 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 1034 +/* 1025 */ MCD_OPC_CheckPredicate, 6, 169, 21, 0, // Skip to: 6575 +/* 1030 */ MCD_OPC_Decode, 180, 24, 55, // Opcode: XOR_MM +/* 1034 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 1048 +/* 1039 */ MCD_OPC_CheckPredicate, 7, 155, 21, 0, // Skip to: 6575 +/* 1044 */ MCD_OPC_Decode, 244, 21, 55, // Opcode: SLT_MM +/* 1048 */ MCD_OPC_FilterValue, 14, 146, 21, 0, // Skip to: 6575 +/* 1053 */ MCD_OPC_CheckPredicate, 7, 141, 21, 0, // Skip to: 6575 +/* 1058 */ MCD_OPC_Decode, 254, 21, 55, // Opcode: SLTu_MM +/* 1062 */ MCD_OPC_FilterValue, 21, 199, 0, 0, // Skip to: 1266 +/* 1067 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1070 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1084 +/* 1075 */ MCD_OPC_CheckPredicate, 8, 119, 21, 0, // Skip to: 6575 +/* 1080 */ MCD_OPC_Decode, 212, 18, 58, // Opcode: MULEU_S_PH_QBL_MM +/* 1084 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 1098 +/* 1089 */ MCD_OPC_CheckPredicate, 8, 105, 21, 0, // Skip to: 6575 +/* 1094 */ MCD_OPC_Decode, 214, 18, 58, // Opcode: MULEU_S_PH_QBR_MM +/* 1098 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1112 +/* 1103 */ MCD_OPC_CheckPredicate, 8, 91, 21, 0, // Skip to: 6575 +/* 1108 */ MCD_OPC_Decode, 216, 18, 58, // Opcode: MULQ_RS_PH_MM +/* 1112 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1126 +/* 1117 */ MCD_OPC_CheckPredicate, 9, 77, 21, 0, // Skip to: 6575 +/* 1122 */ MCD_OPC_Decode, 220, 18, 58, // Opcode: MULQ_S_PH_MMR2 +/* 1126 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1140 +/* 1131 */ MCD_OPC_CheckPredicate, 9, 63, 21, 0, // Skip to: 6575 +/* 1136 */ MCD_OPC_Decode, 218, 18, 55, // Opcode: MULQ_RS_W_MMR2 +/* 1140 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 1154 +/* 1145 */ MCD_OPC_CheckPredicate, 9, 49, 21, 0, // Skip to: 6575 +/* 1150 */ MCD_OPC_Decode, 222, 18, 55, // Opcode: MULQ_S_W_MMR2 +/* 1154 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 1168 +/* 1159 */ MCD_OPC_CheckPredicate, 9, 35, 21, 0, // Skip to: 6575 +/* 1164 */ MCD_OPC_Decode, 235, 6, 62, // Opcode: APPEND_MMR2 +/* 1168 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 1182 +/* 1173 */ MCD_OPC_CheckPredicate, 9, 21, 21, 0, // Skip to: 6575 +/* 1178 */ MCD_OPC_Decode, 248, 19, 62, // Opcode: PREPEND_MMR2 +/* 1182 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 1196 +/* 1187 */ MCD_OPC_CheckPredicate, 8, 7, 21, 0, // Skip to: 6575 +/* 1192 */ MCD_OPC_Decode, 194, 17, 55, // Opcode: MODSUB_MM +/* 1196 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 1210 +/* 1201 */ MCD_OPC_CheckPredicate, 8, 249, 20, 0, // Skip to: 6575 +/* 1206 */ MCD_OPC_Decode, 183, 21, 61, // Opcode: SHRAV_R_W_MM +/* 1210 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 1224 +/* 1215 */ MCD_OPC_CheckPredicate, 9, 235, 20, 0, // Skip to: 6575 +/* 1220 */ MCD_OPC_Decode, 195, 21, 59, // Opcode: SHRLV_PH_MMR2 +/* 1224 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 1238 +/* 1229 */ MCD_OPC_CheckPredicate, 8, 221, 20, 0, // Skip to: 6575 +/* 1234 */ MCD_OPC_Decode, 197, 21, 59, // Opcode: SHRLV_QB_MM +/* 1238 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 1252 +/* 1243 */ MCD_OPC_CheckPredicate, 8, 207, 20, 0, // Skip to: 6575 +/* 1248 */ MCD_OPC_Decode, 161, 21, 59, // Opcode: SHLLV_QB_MM +/* 1252 */ MCD_OPC_FilterValue, 15, 198, 20, 0, // Skip to: 6575 +/* 1257 */ MCD_OPC_CheckPredicate, 8, 193, 20, 0, // Skip to: 6575 +/* 1262 */ MCD_OPC_Decode, 165, 21, 61, // Opcode: SHLLV_S_W_MM +/* 1266 */ MCD_OPC_FilterValue, 24, 45, 0, 0, // Skip to: 1316 +/* 1271 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1274 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1288 +/* 1279 */ MCD_OPC_CheckPredicate, 6, 171, 20, 0, // Skip to: 6575 +/* 1284 */ MCD_OPC_Decode, 234, 17, 63, // Opcode: MOVN_I_MM +/* 1288 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1302 +/* 1293 */ MCD_OPC_CheckPredicate, 6, 157, 20, 0, // Skip to: 6575 +/* 1298 */ MCD_OPC_Decode, 255, 17, 63, // Opcode: MOVZ_I_MM +/* 1302 */ MCD_OPC_FilterValue, 4, 148, 20, 0, // Skip to: 6575 +/* 1307 */ MCD_OPC_CheckPredicate, 7, 143, 20, 0, // Skip to: 6575 +/* 1312 */ MCD_OPC_Decode, 175, 16, 64, // Opcode: LWXS_MM +/* 1316 */ MCD_OPC_FilterValue, 29, 23, 0, 0, // Skip to: 1344 +/* 1321 */ MCD_OPC_CheckPredicate, 8, 129, 20, 0, // Skip to: 6575 +/* 1326 */ MCD_OPC_CheckField, 22, 4, 0, 122, 20, 0, // Skip to: 6575 +/* 1333 */ MCD_OPC_CheckField, 6, 8, 0, 115, 20, 0, // Skip to: 6575 +/* 1340 */ MCD_OPC_Decode, 157, 21, 65, // Opcode: SHILO_MM +/* 1344 */ MCD_OPC_FilterValue, 37, 73, 0, 0, // Skip to: 1422 +/* 1349 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1352 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1366 +/* 1357 */ MCD_OPC_CheckPredicate, 8, 93, 20, 0, // Skip to: 6575 +/* 1362 */ MCD_OPC_Decode, 208, 18, 54, // Opcode: MULEQ_S_W_PHL_MM +/* 1366 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1380 +/* 1371 */ MCD_OPC_CheckPredicate, 8, 79, 20, 0, // Skip to: 6575 +/* 1376 */ MCD_OPC_Decode, 210, 18, 54, // Opcode: MULEQ_S_W_PHR_MM +/* 1380 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1394 +/* 1385 */ MCD_OPC_CheckPredicate, 8, 65, 20, 0, // Skip to: 6575 +/* 1390 */ MCD_OPC_Decode, 221, 15, 64, // Opcode: LHX_MM +/* 1394 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1408 +/* 1399 */ MCD_OPC_CheckPredicate, 8, 51, 20, 0, // Skip to: 6575 +/* 1404 */ MCD_OPC_Decode, 177, 16, 64, // Opcode: LWX_MM +/* 1408 */ MCD_OPC_FilterValue, 8, 42, 20, 0, // Skip to: 6575 +/* 1413 */ MCD_OPC_CheckPredicate, 8, 37, 20, 0, // Skip to: 6575 +/* 1418 */ MCD_OPC_Decode, 164, 15, 64, // Opcode: LBUX_MM +/* 1422 */ MCD_OPC_FilterValue, 44, 9, 0, 0, // Skip to: 1436 +/* 1427 */ MCD_OPC_CheckPredicate, 6, 23, 20, 0, // Skip to: 6575 +/* 1432 */ MCD_OPC_Decode, 255, 12, 66, // Opcode: EXT_MM +/* 1436 */ MCD_OPC_FilterValue, 45, 143, 0, 0, // Skip to: 1584 +/* 1441 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1444 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1458 +/* 1449 */ MCD_OPC_CheckPredicate, 9, 1, 20, 0, // Skip to: 6575 +/* 1454 */ MCD_OPC_Decode, 249, 18, 58, // Opcode: MUL_PH_MMR2 +/* 1458 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1472 +/* 1463 */ MCD_OPC_CheckPredicate, 9, 243, 19, 0, // Skip to: 6575 +/* 1468 */ MCD_OPC_Decode, 233, 19, 58, // Opcode: PRECR_QB_PH_MMR2 +/* 1472 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1486 +/* 1477 */ MCD_OPC_CheckPredicate, 8, 229, 19, 0, // Skip to: 6575 +/* 1482 */ MCD_OPC_Decode, 229, 19, 58, // Opcode: PRECRQ_QB_PH_MM +/* 1486 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 1500 +/* 1491 */ MCD_OPC_CheckPredicate, 8, 215, 19, 0, // Skip to: 6575 +/* 1496 */ MCD_OPC_Decode, 227, 19, 67, // Opcode: PRECRQ_PH_W_MM +/* 1500 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1514 +/* 1505 */ MCD_OPC_CheckPredicate, 8, 201, 19, 0, // Skip to: 6575 +/* 1510 */ MCD_OPC_Decode, 231, 19, 67, // Opcode: PRECRQ_RS_PH_W_MM +/* 1514 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1528 +/* 1519 */ MCD_OPC_CheckPredicate, 8, 187, 19, 0, // Skip to: 6575 +/* 1524 */ MCD_OPC_Decode, 225, 19, 58, // Opcode: PRECRQU_S_QB_PH_MM +/* 1528 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1542 +/* 1533 */ MCD_OPC_CheckPredicate, 8, 173, 19, 0, // Skip to: 6575 +/* 1538 */ MCD_OPC_Decode, 180, 19, 58, // Opcode: PACKRL_PH_MM +/* 1542 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 1556 +/* 1547 */ MCD_OPC_CheckPredicate, 8, 159, 19, 0, // Skip to: 6575 +/* 1552 */ MCD_OPC_Decode, 200, 19, 58, // Opcode: PICK_QB_MM +/* 1556 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 1570 +/* 1561 */ MCD_OPC_CheckPredicate, 8, 145, 19, 0, // Skip to: 6575 +/* 1566 */ MCD_OPC_Decode, 198, 19, 58, // Opcode: PICK_PH_MM +/* 1570 */ MCD_OPC_FilterValue, 16, 136, 19, 0, // Skip to: 6575 +/* 1575 */ MCD_OPC_CheckPredicate, 9, 131, 19, 0, // Skip to: 6575 +/* 1580 */ MCD_OPC_Decode, 254, 18, 58, // Opcode: MUL_S_PH_MMR2 +/* 1584 */ MCD_OPC_FilterValue, 52, 45, 0, 0, // Skip to: 1634 +/* 1589 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1592 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 1613 +/* 1597 */ MCD_OPC_CheckPredicate, 10, 109, 19, 0, // Skip to: 6575 +/* 1602 */ MCD_OPC_CheckField, 14, 2, 0, 102, 19, 0, // Skip to: 6575 +/* 1609 */ MCD_OPC_Decode, 149, 17, 68, // Opcode: MFHGC0_MM +/* 1613 */ MCD_OPC_FilterValue, 27, 93, 19, 0, // Skip to: 6575 +/* 1618 */ MCD_OPC_CheckPredicate, 10, 88, 19, 0, // Skip to: 6575 +/* 1623 */ MCD_OPC_CheckField, 14, 2, 0, 81, 19, 0, // Skip to: 6575 +/* 1630 */ MCD_OPC_Decode, 178, 18, 69, // Opcode: MTHGC0_MM +/* 1634 */ MCD_OPC_FilterValue, 53, 109, 0, 0, // Skip to: 1748 +/* 1639 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1642 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 1656 +/* 1647 */ MCD_OPC_CheckPredicate, 8, 59, 19, 0, // Skip to: 6575 +/* 1652 */ MCD_OPC_Decode, 193, 21, 52, // Opcode: SHRA_R_W_MM +/* 1656 */ MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 1677 +/* 1661 */ MCD_OPC_CheckPredicate, 8, 45, 19, 0, // Skip to: 6575 +/* 1666 */ MCD_OPC_CheckField, 11, 1, 0, 38, 19, 0, // Skip to: 6575 +/* 1673 */ MCD_OPC_Decode, 185, 21, 70, // Opcode: SHRA_PH_MM +/* 1677 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 1713 +/* 1682 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 1685 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1699 +/* 1690 */ MCD_OPC_CheckPredicate, 8, 16, 19, 0, // Skip to: 6575 +/* 1695 */ MCD_OPC_Decode, 167, 21, 70, // Opcode: SHLL_PH_MM +/* 1699 */ MCD_OPC_FilterValue, 1, 7, 19, 0, // Skip to: 6575 +/* 1704 */ MCD_OPC_CheckPredicate, 8, 2, 19, 0, // Skip to: 6575 +/* 1709 */ MCD_OPC_Decode, 171, 21, 70, // Opcode: SHLL_S_PH_MM +/* 1713 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 1727 +/* 1718 */ MCD_OPC_CheckPredicate, 8, 244, 18, 0, // Skip to: 6575 +/* 1723 */ MCD_OPC_Decode, 173, 21, 52, // Opcode: SHLL_S_W_MM +/* 1727 */ MCD_OPC_FilterValue, 28, 235, 18, 0, // Skip to: 6575 +/* 1732 */ MCD_OPC_CheckPredicate, 8, 230, 18, 0, // Skip to: 6575 +/* 1737 */ MCD_OPC_CheckField, 11, 1, 0, 223, 18, 0, // Skip to: 6575 +/* 1744 */ MCD_OPC_Decode, 189, 21, 70, // Opcode: SHRA_R_PH_MM +/* 1748 */ MCD_OPC_FilterValue, 60, 8, 8, 0, // Skip to: 3809 +/* 1753 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1756 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1792 +/* 1761 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 1764 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1778 +/* 1769 */ MCD_OPC_CheckPredicate, 7, 193, 18, 0, // Skip to: 6575 +/* 1774 */ MCD_OPC_Decode, 210, 23, 71, // Opcode: TEQ_MM +/* 1778 */ MCD_OPC_FilterValue, 1, 184, 18, 0, // Skip to: 6575 +/* 1783 */ MCD_OPC_CheckPredicate, 7, 179, 18, 0, // Skip to: 6575 +/* 1788 */ MCD_OPC_Decode, 128, 24, 71, // Opcode: TLT_MM +/* 1792 */ MCD_OPC_FilterValue, 1, 131, 0, 0, // Skip to: 1928 +/* 1797 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 1800 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 1850 +/* 1805 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1808 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1829 +/* 1813 */ MCD_OPC_CheckPredicate, 8, 149, 18, 0, // Skip to: 6575 +/* 1818 */ MCD_OPC_CheckField, 21, 5, 0, 142, 18, 0, // Skip to: 6575 +/* 1825 */ MCD_OPC_Decode, 154, 17, 72, // Opcode: MFHI_DSP_MM +/* 1829 */ MCD_OPC_FilterValue, 1, 133, 18, 0, // Skip to: 6575 +/* 1834 */ MCD_OPC_CheckPredicate, 8, 128, 18, 0, // Skip to: 6575 +/* 1839 */ MCD_OPC_CheckField, 21, 5, 0, 121, 18, 0, // Skip to: 6575 +/* 1846 */ MCD_OPC_Decode, 182, 18, 73, // Opcode: MTHI_DSP_MM +/* 1850 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1864 +/* 1855 */ MCD_OPC_CheckPredicate, 8, 107, 18, 0, // Skip to: 6575 +/* 1860 */ MCD_OPC_Decode, 169, 21, 74, // Opcode: SHLL_QB_MM +/* 1864 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 1914 +/* 1869 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1872 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1893 +/* 1877 */ MCD_OPC_CheckPredicate, 8, 85, 18, 0, // Skip to: 6575 +/* 1882 */ MCD_OPC_CheckField, 21, 5, 0, 78, 18, 0, // Skip to: 6575 +/* 1889 */ MCD_OPC_Decode, 160, 17, 72, // Opcode: MFLO_DSP_MM +/* 1893 */ MCD_OPC_FilterValue, 1, 69, 18, 0, // Skip to: 6575 +/* 1898 */ MCD_OPC_CheckPredicate, 8, 64, 18, 0, // Skip to: 6575 +/* 1903 */ MCD_OPC_CheckField, 21, 5, 0, 57, 18, 0, // Skip to: 6575 +/* 1910 */ MCD_OPC_Decode, 189, 18, 75, // Opcode: MTLO_DSP_MM +/* 1914 */ MCD_OPC_FilterValue, 3, 48, 18, 0, // Skip to: 6575 +/* 1919 */ MCD_OPC_CheckPredicate, 8, 43, 18, 0, // Skip to: 6575 +/* 1924 */ MCD_OPC_Decode, 201, 21, 74, // Opcode: SHRL_QB_MM +/* 1928 */ MCD_OPC_FilterValue, 2, 101, 0, 0, // Skip to: 2034 +/* 1933 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 1936 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1950 +/* 1941 */ MCD_OPC_CheckPredicate, 9, 21, 18, 0, // Skip to: 6575 +/* 1946 */ MCD_OPC_Decode, 157, 12, 76, // Opcode: DPA_W_PH_MMR2 +/* 1950 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1964 +/* 1955 */ MCD_OPC_CheckPredicate, 9, 7, 18, 0, // Skip to: 6575 +/* 1960 */ MCD_OPC_Decode, 153, 7, 77, // Opcode: BALIGN_MMR2 +/* 1964 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1978 +/* 1969 */ MCD_OPC_CheckPredicate, 9, 249, 17, 0, // Skip to: 6575 +/* 1974 */ MCD_OPC_Decode, 155, 12, 76, // Opcode: DPAX_W_PH_MMR2 +/* 1978 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1992 +/* 1983 */ MCD_OPC_CheckPredicate, 8, 235, 17, 0, // Skip to: 6575 +/* 1988 */ MCD_OPC_Decode, 151, 12, 76, // Opcode: DPAU_H_QBL_MM +/* 1992 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2006 +/* 1997 */ MCD_OPC_CheckPredicate, 8, 221, 17, 0, // Skip to: 6575 +/* 2002 */ MCD_OPC_Decode, 234, 12, 78, // Opcode: EXTPV_MM +/* 2006 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2020 +/* 2011 */ MCD_OPC_CheckPredicate, 8, 207, 17, 0, // Skip to: 6575 +/* 2016 */ MCD_OPC_Decode, 153, 12, 76, // Opcode: DPAU_H_QBR_MM +/* 2020 */ MCD_OPC_FilterValue, 7, 198, 17, 0, // Skip to: 6575 +/* 2025 */ MCD_OPC_CheckPredicate, 8, 193, 17, 0, // Skip to: 6575 +/* 2030 */ MCD_OPC_Decode, 231, 12, 78, // Opcode: EXTPDPV_MM +/* 2034 */ MCD_OPC_FilterValue, 4, 171, 0, 0, // Skip to: 2210 +/* 2039 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 2042 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2056 +/* 2047 */ MCD_OPC_CheckPredicate, 9, 171, 17, 0, // Skip to: 6575 +/* 2052 */ MCD_OPC_Decode, 248, 5, 79, // Opcode: ABSQ_S_QB_MMR2 +/* 2056 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2070 +/* 2061 */ MCD_OPC_CheckPredicate, 8, 157, 17, 0, // Skip to: 6575 +/* 2066 */ MCD_OPC_Decode, 246, 5, 79, // Opcode: ABSQ_S_PH_MM +/* 2070 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2084 +/* 2075 */ MCD_OPC_CheckPredicate, 8, 143, 17, 0, // Skip to: 6575 +/* 2080 */ MCD_OPC_Decode, 250, 5, 80, // Opcode: ABSQ_S_W_MM +/* 2084 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2098 +/* 2089 */ MCD_OPC_CheckPredicate, 8, 129, 17, 0, // Skip to: 6575 +/* 2094 */ MCD_OPC_Decode, 131, 8, 80, // Opcode: BITREV_MM +/* 2098 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2112 +/* 2103 */ MCD_OPC_CheckPredicate, 8, 115, 17, 0, // Skip to: 6575 +/* 2108 */ MCD_OPC_Decode, 230, 14, 81, // Opcode: INSV_MM +/* 2112 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 2126 +/* 2117 */ MCD_OPC_CheckPredicate, 8, 101, 17, 0, // Skip to: 6575 +/* 2122 */ MCD_OPC_Decode, 213, 19, 82, // Opcode: PRECEQ_W_PHL_MM +/* 2126 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 2140 +/* 2131 */ MCD_OPC_CheckPredicate, 8, 87, 17, 0, // Skip to: 6575 +/* 2136 */ MCD_OPC_Decode, 215, 19, 82, // Opcode: PRECEQ_W_PHR_MM +/* 2140 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 2154 +/* 2145 */ MCD_OPC_CheckPredicate, 8, 73, 17, 0, // Skip to: 6575 +/* 2150 */ MCD_OPC_Decode, 207, 19, 79, // Opcode: PRECEQU_PH_QBL_MM +/* 2154 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 2168 +/* 2159 */ MCD_OPC_CheckPredicate, 8, 59, 17, 0, // Skip to: 6575 +/* 2164 */ MCD_OPC_Decode, 211, 19, 79, // Opcode: PRECEQU_PH_QBR_MM +/* 2168 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 2182 +/* 2173 */ MCD_OPC_CheckPredicate, 8, 45, 17, 0, // Skip to: 6575 +/* 2178 */ MCD_OPC_Decode, 219, 19, 79, // Opcode: PRECEU_PH_QBL_MM +/* 2182 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 2196 +/* 2187 */ MCD_OPC_CheckPredicate, 8, 31, 17, 0, // Skip to: 6575 +/* 2192 */ MCD_OPC_Decode, 223, 19, 79, // Opcode: PRECEU_PH_QBR_MM +/* 2196 */ MCD_OPC_FilterValue, 30, 22, 17, 0, // Skip to: 6575 +/* 2201 */ MCD_OPC_CheckPredicate, 8, 17, 17, 0, // Skip to: 6575 +/* 2206 */ MCD_OPC_Decode, 252, 19, 82, // Opcode: RADDU_W_QB_MM +/* 2210 */ MCD_OPC_FilterValue, 5, 87, 0, 0, // Skip to: 2302 +/* 2215 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... +/* 2218 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2232 +/* 2223 */ MCD_OPC_CheckPredicate, 10, 251, 16, 0, // Skip to: 6575 +/* 2228 */ MCD_OPC_Decode, 225, 23, 10, // Opcode: TLBGP_MM +/* 2232 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2246 +/* 2237 */ MCD_OPC_CheckPredicate, 10, 237, 16, 0, // Skip to: 6575 +/* 2242 */ MCD_OPC_Decode, 227, 23, 10, // Opcode: TLBGR_MM +/* 2246 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2260 +/* 2251 */ MCD_OPC_CheckPredicate, 10, 223, 16, 0, // Skip to: 6575 +/* 2256 */ MCD_OPC_Decode, 229, 23, 10, // Opcode: TLBGWI_MM +/* 2260 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2274 +/* 2265 */ MCD_OPC_CheckPredicate, 10, 209, 16, 0, // Skip to: 6575 +/* 2270 */ MCD_OPC_Decode, 231, 23, 10, // Opcode: TLBGWR_MM +/* 2274 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2288 +/* 2279 */ MCD_OPC_CheckPredicate, 10, 195, 16, 0, // Skip to: 6575 +/* 2284 */ MCD_OPC_Decode, 223, 23, 10, // Opcode: TLBGINV_MM +/* 2288 */ MCD_OPC_FilterValue, 10, 186, 16, 0, // Skip to: 6575 +/* 2293 */ MCD_OPC_CheckPredicate, 10, 181, 16, 0, // Skip to: 6575 +/* 2298 */ MCD_OPC_Decode, 222, 23, 10, // Opcode: TLBGINVF_MM +/* 2302 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 2338 +/* 2307 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 2310 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2324 +/* 2315 */ MCD_OPC_CheckPredicate, 9, 159, 16, 0, // Skip to: 6575 +/* 2320 */ MCD_OPC_Decode, 187, 21, 74, // Opcode: SHRA_QB_MMR2 +/* 2324 */ MCD_OPC_FilterValue, 2, 150, 16, 0, // Skip to: 6575 +/* 2329 */ MCD_OPC_CheckPredicate, 9, 145, 16, 0, // Skip to: 6575 +/* 2334 */ MCD_OPC_Decode, 191, 21, 74, // Opcode: SHRA_R_QB_MMR2 +/* 2338 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 2374 +/* 2343 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 2346 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2360 +/* 2351 */ MCD_OPC_CheckPredicate, 7, 123, 16, 0, // Skip to: 6575 +/* 2356 */ MCD_OPC_Decode, 219, 23, 71, // Opcode: TGE_MM +/* 2360 */ MCD_OPC_FilterValue, 1, 114, 16, 0, // Skip to: 6575 +/* 2365 */ MCD_OPC_CheckPredicate, 7, 109, 16, 0, // Skip to: 6575 +/* 2370 */ MCD_OPC_Decode, 255, 23, 71, // Opcode: TLTU_MM +/* 2374 */ MCD_OPC_FilterValue, 9, 101, 0, 0, // Skip to: 2480 +/* 2379 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 2382 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2403 +/* 2387 */ MCD_OPC_CheckPredicate, 8, 87, 16, 0, // Skip to: 6575 +/* 2392 */ MCD_OPC_CheckField, 21, 5, 0, 80, 16, 0, // Skip to: 6575 +/* 2399 */ MCD_OPC_Decode, 185, 18, 83, // Opcode: MTHLIP_MM +/* 2403 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2417 +/* 2408 */ MCD_OPC_CheckPredicate, 8, 66, 16, 0, // Skip to: 6575 +/* 2413 */ MCD_OPC_Decode, 227, 16, 76, // Opcode: MAQ_S_W_PHR_MM +/* 2417 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2438 +/* 2422 */ MCD_OPC_CheckPredicate, 8, 52, 16, 0, // Skip to: 6575 +/* 2427 */ MCD_OPC_CheckField, 21, 5, 0, 45, 16, 0, // Skip to: 6575 +/* 2434 */ MCD_OPC_Decode, 156, 21, 83, // Opcode: SHILOV_MM +/* 2438 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2452 +/* 2443 */ MCD_OPC_CheckPredicate, 8, 31, 16, 0, // Skip to: 6575 +/* 2448 */ MCD_OPC_Decode, 225, 16, 76, // Opcode: MAQ_S_W_PHL_MM +/* 2452 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2466 +/* 2457 */ MCD_OPC_CheckPredicate, 8, 17, 16, 0, // Skip to: 6575 +/* 2462 */ MCD_OPC_Decode, 223, 16, 76, // Opcode: MAQ_SA_W_PHR_MM +/* 2466 */ MCD_OPC_FilterValue, 7, 8, 16, 0, // Skip to: 6575 +/* 2471 */ MCD_OPC_CheckPredicate, 8, 3, 16, 0, // Skip to: 6575 +/* 2476 */ MCD_OPC_Decode, 221, 16, 76, // Opcode: MAQ_SA_W_PHL_MM +/* 2480 */ MCD_OPC_FilterValue, 10, 115, 0, 0, // Skip to: 2600 +/* 2485 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 2488 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2502 +/* 2493 */ MCD_OPC_CheckPredicate, 8, 237, 15, 0, // Skip to: 6575 +/* 2498 */ MCD_OPC_Decode, 149, 12, 76, // Opcode: DPAQ_S_W_PH_MM +/* 2502 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2516 +/* 2507 */ MCD_OPC_CheckPredicate, 8, 223, 15, 0, // Skip to: 6575 +/* 2512 */ MCD_OPC_Decode, 214, 16, 76, // Opcode: MADD_DSP_MM +/* 2516 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2530 +/* 2521 */ MCD_OPC_CheckPredicate, 8, 209, 15, 0, // Skip to: 6575 +/* 2526 */ MCD_OPC_Decode, 147, 12, 76, // Opcode: DPAQ_SA_L_W_MM +/* 2530 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2544 +/* 2535 */ MCD_OPC_CheckPredicate, 8, 195, 15, 0, // Skip to: 6575 +/* 2540 */ MCD_OPC_Decode, 204, 16, 76, // Opcode: MADDU_DSP_MM +/* 2544 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2558 +/* 2549 */ MCD_OPC_CheckPredicate, 9, 181, 15, 0, // Skip to: 6575 +/* 2554 */ MCD_OPC_Decode, 145, 12, 76, // Opcode: DPAQX_S_W_PH_MMR2 +/* 2558 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2572 +/* 2563 */ MCD_OPC_CheckPredicate, 8, 167, 15, 0, // Skip to: 6575 +/* 2568 */ MCD_OPC_Decode, 150, 18, 76, // Opcode: MSUB_DSP_MM +/* 2572 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2586 +/* 2577 */ MCD_OPC_CheckPredicate, 9, 153, 15, 0, // Skip to: 6575 +/* 2582 */ MCD_OPC_Decode, 143, 12, 76, // Opcode: DPAQX_SA_W_PH_MMR2 +/* 2586 */ MCD_OPC_FilterValue, 7, 144, 15, 0, // Skip to: 6575 +/* 2591 */ MCD_OPC_CheckPredicate, 8, 139, 15, 0, // Skip to: 6575 +/* 2596 */ MCD_OPC_Decode, 140, 18, 76, // Opcode: MSUBU_DSP_MM +/* 2600 */ MCD_OPC_FilterValue, 12, 27, 1, 0, // Skip to: 2888 +/* 2605 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 2608 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2622 +/* 2613 */ MCD_OPC_CheckPredicate, 8, 117, 15, 0, // Skip to: 6575 +/* 2618 */ MCD_OPC_Decode, 141, 20, 84, // Opcode: REPLV_PH_MM +/* 2622 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2636 +/* 2627 */ MCD_OPC_CheckPredicate, 8, 103, 15, 0, // Skip to: 6575 +/* 2632 */ MCD_OPC_Decode, 143, 20, 84, // Opcode: REPLV_QB_MM +/* 2636 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2650 +/* 2641 */ MCD_OPC_CheckPredicate, 7, 89, 15, 0, // Skip to: 6575 +/* 2646 */ MCD_OPC_Decode, 244, 20, 80, // Opcode: SEB_MM +/* 2650 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 2664 +/* 2655 */ MCD_OPC_CheckPredicate, 7, 75, 15, 0, // Skip to: 6575 +/* 2660 */ MCD_OPC_Decode, 248, 20, 80, // Opcode: SEH_MM +/* 2664 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2678 +/* 2669 */ MCD_OPC_CheckPredicate, 7, 61, 15, 0, // Skip to: 6575 +/* 2674 */ MCD_OPC_Decode, 173, 9, 80, // Opcode: CLO_MM +/* 2678 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 2692 +/* 2683 */ MCD_OPC_CheckPredicate, 7, 47, 15, 0, // Skip to: 6575 +/* 2688 */ MCD_OPC_Decode, 194, 9, 80, // Opcode: CLZ_MM +/* 2692 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 2706 +/* 2697 */ MCD_OPC_CheckPredicate, 6, 33, 15, 0, // Skip to: 6575 +/* 2702 */ MCD_OPC_Decode, 129, 20, 85, // Opcode: RDHWR_MM +/* 2706 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 2720 +/* 2711 */ MCD_OPC_CheckPredicate, 8, 19, 15, 0, // Skip to: 6575 +/* 2716 */ MCD_OPC_Decode, 206, 19, 79, // Opcode: PRECEQU_PH_QBLA_MM +/* 2720 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 2734 +/* 2725 */ MCD_OPC_CheckPredicate, 7, 5, 15, 0, // Skip to: 6575 +/* 2730 */ MCD_OPC_Decode, 170, 24, 80, // Opcode: WSBH_MM +/* 2734 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 2748 +/* 2739 */ MCD_OPC_CheckPredicate, 6, 247, 14, 0, // Skip to: 6575 +/* 2744 */ MCD_OPC_Decode, 235, 18, 86, // Opcode: MULT_MM +/* 2748 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 2762 +/* 2753 */ MCD_OPC_CheckPredicate, 8, 233, 14, 0, // Skip to: 6575 +/* 2758 */ MCD_OPC_Decode, 210, 19, 79, // Opcode: PRECEQU_PH_QBRA_MM +/* 2762 */ MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 2776 +/* 2767 */ MCD_OPC_CheckPredicate, 6, 219, 14, 0, // Skip to: 6575 +/* 2772 */ MCD_OPC_Decode, 237, 18, 86, // Opcode: MULTu_MM +/* 2776 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 2790 +/* 2781 */ MCD_OPC_CheckPredicate, 6, 205, 14, 0, // Skip to: 6575 +/* 2786 */ MCD_OPC_Decode, 237, 20, 86, // Opcode: SDIV_MM +/* 2790 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 2804 +/* 2795 */ MCD_OPC_CheckPredicate, 8, 191, 14, 0, // Skip to: 6575 +/* 2800 */ MCD_OPC_Decode, 218, 19, 79, // Opcode: PRECEU_PH_QBLA_MM +/* 2804 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 2818 +/* 2809 */ MCD_OPC_CheckPredicate, 6, 177, 14, 0, // Skip to: 6575 +/* 2814 */ MCD_OPC_Decode, 153, 24, 86, // Opcode: UDIV_MM +/* 2818 */ MCD_OPC_FilterValue, 25, 9, 0, 0, // Skip to: 2832 +/* 2823 */ MCD_OPC_CheckPredicate, 6, 163, 14, 0, // Skip to: 6575 +/* 2828 */ MCD_OPC_Decode, 215, 16, 86, // Opcode: MADD_MM +/* 2832 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 2846 +/* 2837 */ MCD_OPC_CheckPredicate, 8, 149, 14, 0, // Skip to: 6575 +/* 2842 */ MCD_OPC_Decode, 222, 19, 79, // Opcode: PRECEU_PH_QBRA_MM +/* 2846 */ MCD_OPC_FilterValue, 27, 9, 0, 0, // Skip to: 2860 +/* 2851 */ MCD_OPC_CheckPredicate, 6, 135, 14, 0, // Skip to: 6575 +/* 2856 */ MCD_OPC_Decode, 205, 16, 86, // Opcode: MADDU_MM +/* 2860 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 2874 +/* 2865 */ MCD_OPC_CheckPredicate, 6, 121, 14, 0, // Skip to: 6575 +/* 2870 */ MCD_OPC_Decode, 151, 18, 86, // Opcode: MSUB_MM +/* 2874 */ MCD_OPC_FilterValue, 31, 112, 14, 0, // Skip to: 6575 +/* 2879 */ MCD_OPC_CheckPredicate, 6, 107, 14, 0, // Skip to: 6575 +/* 2884 */ MCD_OPC_Decode, 141, 18, 86, // Opcode: MSUBU_MM +/* 2888 */ MCD_OPC_FilterValue, 13, 206, 0, 0, // Skip to: 3099 +/* 2893 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 2896 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2917 +/* 2901 */ MCD_OPC_CheckPredicate, 7, 85, 14, 0, // Skip to: 6575 +/* 2906 */ MCD_OPC_CheckField, 16, 10, 0, 78, 14, 0, // Skip to: 6575 +/* 2913 */ MCD_OPC_Decode, 239, 23, 10, // Opcode: TLBP_MM +/* 2917 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2938 +/* 2922 */ MCD_OPC_CheckPredicate, 7, 64, 14, 0, // Skip to: 6575 +/* 2927 */ MCD_OPC_CheckField, 16, 10, 0, 57, 14, 0, // Skip to: 6575 +/* 2934 */ MCD_OPC_Decode, 242, 23, 10, // Opcode: TLBR_MM +/* 2938 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 2959 +/* 2943 */ MCD_OPC_CheckPredicate, 7, 43, 14, 0, // Skip to: 6575 +/* 2948 */ MCD_OPC_CheckField, 16, 10, 0, 36, 14, 0, // Skip to: 6575 +/* 2955 */ MCD_OPC_Decode, 245, 23, 10, // Opcode: TLBWI_MM +/* 2959 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2980 +/* 2964 */ MCD_OPC_CheckPredicate, 7, 22, 14, 0, // Skip to: 6575 +/* 2969 */ MCD_OPC_CheckField, 16, 10, 0, 15, 14, 0, // Skip to: 6575 +/* 2976 */ MCD_OPC_Decode, 248, 23, 10, // Opcode: TLBWR_MM +/* 2980 */ MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 3001 +/* 2985 */ MCD_OPC_CheckPredicate, 7, 1, 14, 0, // Skip to: 6575 +/* 2990 */ MCD_OPC_CheckField, 21, 5, 0, 250, 13, 0, // Skip to: 6575 +/* 2997 */ MCD_OPC_Decode, 179, 23, 87, // Opcode: SYNC_MM +/* 3001 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 3015 +/* 3006 */ MCD_OPC_CheckPredicate, 7, 236, 13, 0, // Skip to: 6575 +/* 3011 */ MCD_OPC_Decode, 184, 23, 88, // Opcode: SYSCALL_MM +/* 3015 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 3029 +/* 3020 */ MCD_OPC_CheckPredicate, 7, 222, 13, 0, // Skip to: 6575 +/* 3025 */ MCD_OPC_Decode, 162, 24, 88, // Opcode: WAIT_MM +/* 3029 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 3043 +/* 3034 */ MCD_OPC_CheckPredicate, 10, 208, 13, 0, // Skip to: 6575 +/* 3039 */ MCD_OPC_Decode, 203, 14, 88, // Opcode: HYPCALL_MM +/* 3043 */ MCD_OPC_FilterValue, 27, 9, 0, 0, // Skip to: 3057 +/* 3048 */ MCD_OPC_CheckPredicate, 7, 194, 13, 0, // Skip to: 6575 +/* 3053 */ MCD_OPC_Decode, 223, 20, 88, // Opcode: SDBBP_MM +/* 3057 */ MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 3078 +/* 3062 */ MCD_OPC_CheckPredicate, 7, 180, 13, 0, // Skip to: 6575 +/* 3067 */ MCD_OPC_CheckField, 16, 10, 0, 173, 13, 0, // Skip to: 6575 +/* 3074 */ MCD_OPC_Decode, 207, 11, 10, // Opcode: DERET_MM +/* 3078 */ MCD_OPC_FilterValue, 30, 164, 13, 0, // Skip to: 6575 +/* 3083 */ MCD_OPC_CheckPredicate, 7, 159, 13, 0, // Skip to: 6575 +/* 3088 */ MCD_OPC_CheckField, 16, 10, 0, 152, 13, 0, // Skip to: 6575 +/* 3095 */ MCD_OPC_Decode, 220, 12, 10, // Opcode: ERET_MM +/* 3099 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 3120 +/* 3104 */ MCD_OPC_CheckPredicate, 9, 138, 13, 0, // Skip to: 6575 +/* 3109 */ MCD_OPC_CheckField, 11, 1, 0, 131, 13, 0, // Skip to: 6575 +/* 3116 */ MCD_OPC_Decode, 199, 21, 70, // Opcode: SHRL_PH_MMR2 +/* 3120 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 3156 +/* 3125 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 3128 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3142 +/* 3133 */ MCD_OPC_CheckPredicate, 7, 109, 13, 0, // Skip to: 6575 +/* 3138 */ MCD_OPC_Decode, 218, 23, 71, // Opcode: TGEU_MM +/* 3142 */ MCD_OPC_FilterValue, 1, 100, 13, 0, // Skip to: 6575 +/* 3147 */ MCD_OPC_CheckPredicate, 7, 95, 13, 0, // Skip to: 6575 +/* 3152 */ MCD_OPC_Decode, 132, 24, 71, // Opcode: TNE_MM +/* 3156 */ MCD_OPC_FilterValue, 18, 115, 0, 0, // Skip to: 3276 +/* 3161 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3164 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3178 +/* 3169 */ MCD_OPC_CheckPredicate, 9, 73, 13, 0, // Skip to: 6575 +/* 3174 */ MCD_OPC_Decode, 180, 12, 76, // Opcode: DPS_W_PH_MMR2 +/* 3178 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3192 +/* 3183 */ MCD_OPC_CheckPredicate, 8, 59, 13, 0, // Skip to: 6575 +/* 3188 */ MCD_OPC_Decode, 234, 18, 89, // Opcode: MULT_DSP_MM +/* 3192 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3206 +/* 3197 */ MCD_OPC_CheckPredicate, 9, 45, 13, 0, // Skip to: 6575 +/* 3202 */ MCD_OPC_Decode, 178, 12, 76, // Opcode: DPSX_W_PH_MMR2 +/* 3206 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3220 +/* 3211 */ MCD_OPC_CheckPredicate, 8, 31, 13, 0, // Skip to: 6575 +/* 3216 */ MCD_OPC_Decode, 232, 18, 89, // Opcode: MULTU_DSP_MM +/* 3220 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3234 +/* 3225 */ MCD_OPC_CheckPredicate, 8, 17, 13, 0, // Skip to: 6575 +/* 3230 */ MCD_OPC_Decode, 174, 12, 76, // Opcode: DPSU_H_QBL_MM +/* 3234 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3248 +/* 3239 */ MCD_OPC_CheckPredicate, 9, 3, 13, 0, // Skip to: 6575 +/* 3244 */ MCD_OPC_Decode, 229, 18, 76, // Opcode: MULSA_W_PH_MMR2 +/* 3248 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3262 +/* 3253 */ MCD_OPC_CheckPredicate, 8, 245, 12, 0, // Skip to: 6575 +/* 3258 */ MCD_OPC_Decode, 176, 12, 76, // Opcode: DPSU_H_QBR_MM +/* 3262 */ MCD_OPC_FilterValue, 7, 236, 12, 0, // Skip to: 6575 +/* 3267 */ MCD_OPC_CheckPredicate, 8, 231, 12, 0, // Skip to: 6575 +/* 3272 */ MCD_OPC_Decode, 227, 18, 76, // Opcode: MULSAQ_S_W_PH_MM +/* 3276 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 3297 +/* 3281 */ MCD_OPC_CheckPredicate, 10, 217, 12, 0, // Skip to: 6575 +/* 3286 */ MCD_OPC_CheckField, 14, 2, 0, 210, 12, 0, // Skip to: 6575 +/* 3293 */ MCD_OPC_Decode, 139, 17, 68, // Opcode: MFGC0_MM +/* 3297 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 3333 +/* 3302 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3305 */ MCD_OPC_FilterValue, 25, 9, 0, 0, // Skip to: 3319 +/* 3310 */ MCD_OPC_CheckPredicate, 7, 188, 12, 0, // Skip to: 6575 +/* 3315 */ MCD_OPC_Decode, 146, 9, 90, // Opcode: CFC2_MM +/* 3319 */ MCD_OPC_FilterValue, 27, 179, 12, 0, // Skip to: 6575 +/* 3324 */ MCD_OPC_CheckPredicate, 7, 174, 12, 0, // Skip to: 6575 +/* 3329 */ MCD_OPC_Decode, 181, 10, 91, // Opcode: CTC2_MM +/* 3333 */ MCD_OPC_FilterValue, 21, 87, 0, 0, // Skip to: 3425 +/* 3338 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3341 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3362 +/* 3346 */ MCD_OPC_CheckPredicate, 6, 152, 12, 0, // Skip to: 6575 +/* 3351 */ MCD_OPC_CheckField, 21, 5, 0, 145, 12, 0, // Skip to: 6575 +/* 3358 */ MCD_OPC_Decode, 155, 17, 92, // Opcode: MFHI_MM +/* 3362 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 3383 +/* 3367 */ MCD_OPC_CheckPredicate, 6, 131, 12, 0, // Skip to: 6575 +/* 3372 */ MCD_OPC_CheckField, 21, 5, 0, 124, 12, 0, // Skip to: 6575 +/* 3379 */ MCD_OPC_Decode, 161, 17, 92, // Opcode: MFLO_MM +/* 3383 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 3404 +/* 3388 */ MCD_OPC_CheckPredicate, 6, 110, 12, 0, // Skip to: 6575 +/* 3393 */ MCD_OPC_CheckField, 21, 5, 0, 103, 12, 0, // Skip to: 6575 +/* 3400 */ MCD_OPC_Decode, 183, 18, 92, // Opcode: MTHI_MM +/* 3404 */ MCD_OPC_FilterValue, 7, 94, 12, 0, // Skip to: 6575 +/* 3409 */ MCD_OPC_CheckPredicate, 6, 89, 12, 0, // Skip to: 6575 +/* 3414 */ MCD_OPC_CheckField, 21, 5, 0, 82, 12, 0, // Skip to: 6575 +/* 3421 */ MCD_OPC_Decode, 190, 18, 92, // Opcode: MTLO_MM +/* 3425 */ MCD_OPC_FilterValue, 23, 16, 0, 0, // Skip to: 3446 +/* 3430 */ MCD_OPC_CheckPredicate, 8, 68, 12, 0, // Skip to: 6575 +/* 3435 */ MCD_OPC_CheckField, 11, 2, 0, 61, 12, 0, // Skip to: 6575 +/* 3442 */ MCD_OPC_Decode, 147, 20, 93, // Opcode: REPL_QB_MM +/* 3446 */ MCD_OPC_FilterValue, 25, 115, 0, 0, // Skip to: 3566 +/* 3451 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3454 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3468 +/* 3459 */ MCD_OPC_CheckPredicate, 8, 39, 12, 0, // Skip to: 6575 +/* 3464 */ MCD_OPC_Decode, 254, 19, 94, // Opcode: RDDSP_MM +/* 3468 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3482 +/* 3473 */ MCD_OPC_CheckPredicate, 8, 25, 12, 0, // Skip to: 6575 +/* 3478 */ MCD_OPC_Decode, 251, 12, 95, // Opcode: EXTR_W_MM +/* 3482 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3496 +/* 3487 */ MCD_OPC_CheckPredicate, 8, 11, 12, 0, // Skip to: 6575 +/* 3492 */ MCD_OPC_Decode, 166, 24, 94, // Opcode: WRDSP_MM +/* 3496 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3510 +/* 3501 */ MCD_OPC_CheckPredicate, 8, 253, 11, 0, // Skip to: 6575 +/* 3506 */ MCD_OPC_Decode, 247, 12, 95, // Opcode: EXTR_R_W_MM +/* 3510 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3524 +/* 3515 */ MCD_OPC_CheckPredicate, 8, 239, 11, 0, // Skip to: 6575 +/* 3520 */ MCD_OPC_Decode, 235, 12, 95, // Opcode: EXTP_MM +/* 3524 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3538 +/* 3529 */ MCD_OPC_CheckPredicate, 8, 225, 11, 0, // Skip to: 6575 +/* 3534 */ MCD_OPC_Decode, 245, 12, 95, // Opcode: EXTR_RS_W_MM +/* 3538 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3552 +/* 3543 */ MCD_OPC_CheckPredicate, 8, 211, 11, 0, // Skip to: 6575 +/* 3548 */ MCD_OPC_Decode, 232, 12, 95, // Opcode: EXTPDP_MM +/* 3552 */ MCD_OPC_FilterValue, 7, 202, 11, 0, // Skip to: 6575 +/* 3557 */ MCD_OPC_CheckPredicate, 8, 197, 11, 0, // Skip to: 6575 +/* 3562 */ MCD_OPC_Decode, 249, 12, 95, // Opcode: EXTR_S_H_MM +/* 3566 */ MCD_OPC_FilterValue, 26, 115, 0, 0, // Skip to: 3686 +/* 3571 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3574 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3588 +/* 3579 */ MCD_OPC_CheckPredicate, 8, 175, 11, 0, // Skip to: 6575 +/* 3584 */ MCD_OPC_Decode, 166, 12, 76, // Opcode: DPSQ_S_W_PH_MM +/* 3588 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3602 +/* 3593 */ MCD_OPC_CheckPredicate, 8, 161, 11, 0, // Skip to: 6575 +/* 3598 */ MCD_OPC_Decode, 243, 12, 78, // Opcode: EXTRV_W_MM +/* 3602 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3616 +/* 3607 */ MCD_OPC_CheckPredicate, 8, 147, 11, 0, // Skip to: 6575 +/* 3612 */ MCD_OPC_Decode, 164, 12, 76, // Opcode: DPSQ_SA_L_W_MM +/* 3616 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3630 +/* 3621 */ MCD_OPC_CheckPredicate, 8, 133, 11, 0, // Skip to: 6575 +/* 3626 */ MCD_OPC_Decode, 239, 12, 78, // Opcode: EXTRV_R_W_MM +/* 3630 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3644 +/* 3635 */ MCD_OPC_CheckPredicate, 9, 119, 11, 0, // Skip to: 6575 +/* 3640 */ MCD_OPC_Decode, 162, 12, 76, // Opcode: DPSQX_S_W_PH_MMR2 +/* 3644 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3658 +/* 3649 */ MCD_OPC_CheckPredicate, 8, 105, 11, 0, // Skip to: 6575 +/* 3654 */ MCD_OPC_Decode, 237, 12, 78, // Opcode: EXTRV_RS_W_MM +/* 3658 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3672 +/* 3663 */ MCD_OPC_CheckPredicate, 9, 91, 11, 0, // Skip to: 6575 +/* 3668 */ MCD_OPC_Decode, 160, 12, 76, // Opcode: DPSQX_SA_W_PH_MMR2 +/* 3672 */ MCD_OPC_FilterValue, 7, 82, 11, 0, // Skip to: 6575 +/* 3677 */ MCD_OPC_CheckPredicate, 8, 77, 11, 0, // Skip to: 6575 +/* 3682 */ MCD_OPC_Decode, 241, 12, 78, // Opcode: EXTRV_S_H_MM +/* 3686 */ MCD_OPC_FilterValue, 27, 16, 0, 0, // Skip to: 3707 +/* 3691 */ MCD_OPC_CheckPredicate, 10, 63, 11, 0, // Skip to: 6575 +/* 3696 */ MCD_OPC_CheckField, 14, 2, 0, 56, 11, 0, // Skip to: 6575 +/* 3703 */ MCD_OPC_Decode, 168, 18, 69, // Opcode: MTGC0_MM +/* 3707 */ MCD_OPC_FilterValue, 28, 47, 0, 0, // Skip to: 3759 +/* 3712 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3715 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 3745 +/* 3720 */ MCD_OPC_CheckPredicate, 6, 11, 0, 0, // Skip to: 3736 +/* 3725 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 3736 +/* 3732 */ MCD_OPC_Decode, 144, 15, 92, // Opcode: JR_MM +/* 3736 */ MCD_OPC_CheckPredicate, 6, 18, 11, 0, // Skip to: 6575 +/* 3741 */ MCD_OPC_Decode, 249, 14, 80, // Opcode: JALR_MM +/* 3745 */ MCD_OPC_FilterValue, 9, 9, 11, 0, // Skip to: 6575 +/* 3750 */ MCD_OPC_CheckPredicate, 6, 4, 11, 0, // Skip to: 6575 +/* 3755 */ MCD_OPC_Decode, 246, 14, 80, // Opcode: JALRS_MM +/* 3759 */ MCD_OPC_FilterValue, 29, 251, 10, 0, // Skip to: 6575 +/* 3764 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3767 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 3788 +/* 3772 */ MCD_OPC_CheckPredicate, 7, 238, 10, 0, // Skip to: 6575 +/* 3777 */ MCD_OPC_CheckField, 21, 5, 0, 231, 10, 0, // Skip to: 6575 +/* 3784 */ MCD_OPC_Decode, 232, 11, 92, // Opcode: DI_MM +/* 3788 */ MCD_OPC_FilterValue, 10, 222, 10, 0, // Skip to: 6575 +/* 3793 */ MCD_OPC_CheckPredicate, 7, 217, 10, 0, // Skip to: 6575 +/* 3798 */ MCD_OPC_CheckField, 21, 5, 0, 210, 10, 0, // Skip to: 6575 +/* 3805 */ MCD_OPC_Decode, 211, 12, 92, // Opcode: EI_MM +/* 3809 */ MCD_OPC_FilterValue, 61, 201, 10, 0, // Skip to: 6575 +/* 3814 */ MCD_OPC_CheckPredicate, 8, 196, 10, 0, // Skip to: 6575 +/* 3819 */ MCD_OPC_CheckField, 6, 5, 0, 189, 10, 0, // Skip to: 6575 +/* 3826 */ MCD_OPC_Decode, 145, 20, 96, // Opcode: REPL_PH_MM +/* 3830 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3844 +/* 3835 */ MCD_OPC_CheckPredicate, 6, 175, 10, 0, // Skip to: 6575 +/* 3840 */ MCD_OPC_Decode, 203, 6, 97, // Opcode: ADDi_MM +/* 3844 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3858 +/* 3849 */ MCD_OPC_CheckPredicate, 7, 161, 10, 0, // Skip to: 6575 +/* 3854 */ MCD_OPC_Decode, 178, 15, 98, // Opcode: LBu_MM +/* 3858 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3872 +/* 3863 */ MCD_OPC_CheckPredicate, 7, 147, 10, 0, // Skip to: 6575 +/* 3868 */ MCD_OPC_Decode, 202, 20, 98, // Opcode: SB_MM +/* 3872 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 3886 +/* 3877 */ MCD_OPC_CheckPredicate, 7, 133, 10, 0, // Skip to: 6575 +/* 3882 */ MCD_OPC_Decode, 170, 15, 98, // Opcode: LB_MM +/* 3886 */ MCD_OPC_FilterValue, 8, 73, 0, 0, // Skip to: 3964 +/* 3891 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3894 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3908 +/* 3899 */ MCD_OPC_CheckPredicate, 7, 111, 10, 0, // Skip to: 6575 +/* 3904 */ MCD_OPC_Decode, 161, 16, 99, // Opcode: LWP_MM +/* 3908 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3922 +/* 3913 */ MCD_OPC_CheckPredicate, 7, 97, 10, 0, // Skip to: 6575 +/* 3918 */ MCD_OPC_Decode, 156, 16, 99, // Opcode: LWM32_MM +/* 3922 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3936 +/* 3927 */ MCD_OPC_CheckPredicate, 6, 83, 10, 0, // Skip to: 6575 +/* 3932 */ MCD_OPC_Decode, 249, 8, 100, // Opcode: CACHE_MM +/* 3936 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 3950 +/* 3941 */ MCD_OPC_CheckPredicate, 7, 69, 10, 0, // Skip to: 6575 +/* 3946 */ MCD_OPC_Decode, 156, 23, 99, // Opcode: SWP_MM +/* 3950 */ MCD_OPC_FilterValue, 13, 60, 10, 0, // Skip to: 6575 +/* 3955 */ MCD_OPC_CheckPredicate, 7, 55, 10, 0, // Skip to: 6575 +/* 3960 */ MCD_OPC_Decode, 153, 23, 99, // Opcode: SWM32_MM +/* 3964 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 3978 +/* 3969 */ MCD_OPC_CheckPredicate, 6, 41, 10, 0, // Skip to: 6575 +/* 3974 */ MCD_OPC_Decode, 205, 6, 97, // Opcode: ADDiu_MM +/* 3978 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 3992 +/* 3983 */ MCD_OPC_CheckPredicate, 7, 27, 10, 0, // Skip to: 6575 +/* 3988 */ MCD_OPC_Decode, 230, 15, 98, // Opcode: LHu_MM +/* 3992 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 4006 +/* 3997 */ MCD_OPC_CheckPredicate, 7, 13, 10, 0, // Skip to: 6575 +/* 4002 */ MCD_OPC_Decode, 204, 21, 98, // Opcode: SH_MM +/* 4006 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 4020 +/* 4011 */ MCD_OPC_CheckPredicate, 7, 255, 9, 0, // Skip to: 6575 +/* 4016 */ MCD_OPC_Decode, 223, 15, 98, // Opcode: LH_MM +/* 4020 */ MCD_OPC_FilterValue, 16, 83, 1, 0, // Skip to: 4364 +/* 4025 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 4028 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4042 +/* 4033 */ MCD_OPC_CheckPredicate, 6, 233, 9, 0, // Skip to: 6575 +/* 4038 */ MCD_OPC_Decode, 165, 8, 101, // Opcode: BLTZ_MM +/* 4042 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4056 +/* 4047 */ MCD_OPC_CheckPredicate, 6, 219, 9, 0, // Skip to: 6575 +/* 4052 */ MCD_OPC_Decode, 160, 8, 101, // Opcode: BLTZAL_MM +/* 4056 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4070 +/* 4061 */ MCD_OPC_CheckPredicate, 6, 205, 9, 0, // Skip to: 6575 +/* 4066 */ MCD_OPC_Decode, 231, 7, 101, // Opcode: BGEZ_MM +/* 4070 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 4084 +/* 4075 */ MCD_OPC_CheckPredicate, 6, 191, 9, 0, // Skip to: 6575 +/* 4080 */ MCD_OPC_Decode, 226, 7, 101, // Opcode: BGEZAL_MM +/* 4084 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4098 +/* 4089 */ MCD_OPC_CheckPredicate, 6, 177, 9, 0, // Skip to: 6575 +/* 4094 */ MCD_OPC_Decode, 142, 8, 101, // Opcode: BLEZ_MM +/* 4098 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4112 +/* 4103 */ MCD_OPC_CheckPredicate, 6, 163, 9, 0, // Skip to: 6575 +/* 4108 */ MCD_OPC_Decode, 195, 8, 101, // Opcode: BNEZC_MM +/* 4112 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4126 +/* 4117 */ MCD_OPC_CheckPredicate, 6, 149, 9, 0, // Skip to: 6575 +/* 4122 */ MCD_OPC_Decode, 240, 7, 101, // Opcode: BGTZ_MM +/* 4126 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 4140 +/* 4131 */ MCD_OPC_CheckPredicate, 6, 135, 9, 0, // Skip to: 6575 +/* 4136 */ MCD_OPC_Decode, 205, 7, 101, // Opcode: BEQZC_MM +/* 4140 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 4154 +/* 4145 */ MCD_OPC_CheckPredicate, 6, 121, 9, 0, // Skip to: 6575 +/* 4150 */ MCD_OPC_Decode, 253, 23, 102, // Opcode: TLTI_MM +/* 4154 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 4168 +/* 4159 */ MCD_OPC_CheckPredicate, 6, 107, 9, 0, // Skip to: 6575 +/* 4164 */ MCD_OPC_Decode, 216, 23, 102, // Opcode: TGEI_MM +/* 4168 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 4182 +/* 4173 */ MCD_OPC_CheckPredicate, 6, 93, 9, 0, // Skip to: 6575 +/* 4178 */ MCD_OPC_Decode, 252, 23, 102, // Opcode: TLTIU_MM +/* 4182 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 4196 +/* 4187 */ MCD_OPC_CheckPredicate, 6, 79, 9, 0, // Skip to: 6575 +/* 4192 */ MCD_OPC_Decode, 215, 23, 102, // Opcode: TGEIU_MM +/* 4196 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 4210 +/* 4201 */ MCD_OPC_CheckPredicate, 6, 65, 9, 0, // Skip to: 6575 +/* 4206 */ MCD_OPC_Decode, 131, 24, 102, // Opcode: TNEI_MM +/* 4210 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 4224 +/* 4215 */ MCD_OPC_CheckPredicate, 6, 51, 9, 0, // Skip to: 6575 +/* 4220 */ MCD_OPC_Decode, 130, 16, 103, // Opcode: LUi_MM +/* 4224 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 4238 +/* 4229 */ MCD_OPC_CheckPredicate, 6, 37, 9, 0, // Skip to: 6575 +/* 4234 */ MCD_OPC_Decode, 209, 23, 102, // Opcode: TEQI_MM +/* 4238 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 4252 +/* 4243 */ MCD_OPC_CheckPredicate, 6, 23, 9, 0, // Skip to: 6575 +/* 4248 */ MCD_OPC_Decode, 175, 23, 104, // Opcode: SYNCI_MM +/* 4252 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 4266 +/* 4257 */ MCD_OPC_CheckPredicate, 6, 9, 9, 0, // Skip to: 6575 +/* 4262 */ MCD_OPC_Decode, 159, 8, 101, // Opcode: BLTZALS_MM +/* 4266 */ MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 4280 +/* 4271 */ MCD_OPC_CheckPredicate, 6, 251, 8, 0, // Skip to: 6575 +/* 4276 */ MCD_OPC_Decode, 225, 7, 101, // Opcode: BGEZALS_MM +/* 4280 */ MCD_OPC_FilterValue, 25, 16, 0, 0, // Skip to: 4301 +/* 4285 */ MCD_OPC_CheckPredicate, 11, 237, 8, 0, // Skip to: 6575 +/* 4290 */ MCD_OPC_CheckField, 16, 5, 0, 230, 8, 0, // Skip to: 6575 +/* 4297 */ MCD_OPC_Decode, 209, 8, 105, // Opcode: BPOSGE32C_MMR3 +/* 4301 */ MCD_OPC_FilterValue, 27, 16, 0, 0, // Skip to: 4322 +/* 4306 */ MCD_OPC_CheckPredicate, 12, 216, 8, 0, // Skip to: 6575 +/* 4311 */ MCD_OPC_CheckField, 16, 5, 0, 209, 8, 0, // Skip to: 6575 +/* 4318 */ MCD_OPC_Decode, 210, 8, 106, // Opcode: BPOSGE32_MM +/* 4322 */ MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 4343 +/* 4327 */ MCD_OPC_CheckPredicate, 13, 195, 8, 0, // Skip to: 6575 +/* 4332 */ MCD_OPC_CheckField, 16, 2, 0, 188, 8, 0, // Skip to: 6575 +/* 4339 */ MCD_OPC_Decode, 168, 7, 107, // Opcode: BC1F_MM +/* 4343 */ MCD_OPC_FilterValue, 29, 179, 8, 0, // Skip to: 6575 +/* 4348 */ MCD_OPC_CheckPredicate, 13, 174, 8, 0, // Skip to: 6575 +/* 4353 */ MCD_OPC_CheckField, 16, 2, 0, 167, 8, 0, // Skip to: 6575 +/* 4360 */ MCD_OPC_Decode, 173, 7, 107, // Opcode: BC1T_MM +/* 4364 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 4378 +/* 4369 */ MCD_OPC_CheckPredicate, 6, 153, 8, 0, // Skip to: 6575 +/* 4374 */ MCD_OPC_Decode, 177, 19, 108, // Opcode: ORi_MM +/* 4378 */ MCD_OPC_FilterValue, 21, 234, 5, 0, // Skip to: 5897 +/* 4383 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 4386 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4400 +/* 4391 */ MCD_OPC_CheckPredicate, 14, 131, 8, 0, // Skip to: 6575 +/* 4396 */ MCD_OPC_Decode, 219, 16, 109, // Opcode: MADD_S_MM +/* 4400 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4414 +/* 4405 */ MCD_OPC_CheckPredicate, 14, 117, 8, 0, // Skip to: 6575 +/* 4410 */ MCD_OPC_Decode, 143, 19, 109, // Opcode: NMADD_S_MM +/* 4414 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 4478 +/* 4419 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4422 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4436 +/* 4427 */ MCD_OPC_CheckPredicate, 13, 95, 8, 0, // Skip to: 6575 +/* 4432 */ MCD_OPC_Decode, 173, 16, 110, // Opcode: LWXC1_MM +/* 4436 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4450 +/* 4441 */ MCD_OPC_CheckPredicate, 13, 81, 8, 0, // Skip to: 6575 +/* 4446 */ MCD_OPC_Decode, 166, 23, 110, // Opcode: SWXC1_MM +/* 4450 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4464 +/* 4455 */ MCD_OPC_CheckPredicate, 15, 67, 8, 0, // Skip to: 6575 +/* 4460 */ MCD_OPC_Decode, 255, 15, 111, // Opcode: LUXC1_MM +/* 4464 */ MCD_OPC_FilterValue, 6, 58, 8, 0, // Skip to: 6575 +/* 4469 */ MCD_OPC_CheckPredicate, 15, 53, 8, 0, // Skip to: 6575 +/* 4474 */ MCD_OPC_Decode, 255, 22, 111, // Opcode: SUXC1_MM +/* 4478 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 4492 +/* 4483 */ MCD_OPC_CheckPredicate, 16, 39, 8, 0, // Skip to: 6575 +/* 4488 */ MCD_OPC_Decode, 211, 16, 112, // Opcode: MADD_D32_MM +/* 4492 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 4506 +/* 4497 */ MCD_OPC_CheckPredicate, 16, 25, 8, 0, // Skip to: 6575 +/* 4502 */ MCD_OPC_Decode, 140, 19, 112, // Opcode: NMADD_D32_MM +/* 4506 */ MCD_OPC_FilterValue, 32, 101, 0, 0, // Skip to: 4612 +/* 4511 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4514 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4535 +/* 4519 */ MCD_OPC_CheckPredicate, 13, 3, 8, 0, // Skip to: 6575 +/* 4524 */ MCD_OPC_CheckField, 11, 2, 0, 252, 7, 0, // Skip to: 6575 +/* 4531 */ MCD_OPC_Decode, 224, 17, 113, // Opcode: MOVF_S_MM +/* 4535 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 4556 +/* 4540 */ MCD_OPC_CheckPredicate, 13, 238, 7, 0, // Skip to: 6575 +/* 4545 */ MCD_OPC_CheckField, 11, 2, 0, 231, 7, 0, // Skip to: 6575 +/* 4552 */ MCD_OPC_Decode, 245, 17, 113, // Opcode: MOVT_S_MM +/* 4556 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4570 +/* 4561 */ MCD_OPC_CheckPredicate, 6, 217, 7, 0, // Skip to: 6575 +/* 4566 */ MCD_OPC_Decode, 241, 19, 114, // Opcode: PREFX_MM +/* 4570 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 4591 +/* 4575 */ MCD_OPC_CheckPredicate, 17, 203, 7, 0, // Skip to: 6575 +/* 4580 */ MCD_OPC_CheckField, 11, 2, 0, 196, 7, 0, // Skip to: 6575 +/* 4587 */ MCD_OPC_Decode, 218, 17, 115, // Opcode: MOVF_D32_MM +/* 4591 */ MCD_OPC_FilterValue, 9, 187, 7, 0, // Skip to: 6575 +/* 4596 */ MCD_OPC_CheckPredicate, 17, 182, 7, 0, // Skip to: 6575 +/* 4601 */ MCD_OPC_CheckField, 11, 2, 0, 175, 7, 0, // Skip to: 6575 +/* 4608 */ MCD_OPC_Decode, 239, 17, 115, // Opcode: MOVT_D32_MM +/* 4612 */ MCD_OPC_FilterValue, 33, 9, 0, 0, // Skip to: 4626 +/* 4617 */ MCD_OPC_CheckPredicate, 14, 161, 7, 0, // Skip to: 6575 +/* 4622 */ MCD_OPC_Decode, 155, 18, 109, // Opcode: MSUB_S_MM +/* 4626 */ MCD_OPC_FilterValue, 34, 9, 0, 0, // Skip to: 4640 +/* 4631 */ MCD_OPC_CheckPredicate, 14, 147, 7, 0, // Skip to: 6575 +/* 4636 */ MCD_OPC_Decode, 148, 19, 109, // Opcode: NMSUB_S_MM +/* 4640 */ MCD_OPC_FilterValue, 41, 9, 0, 0, // Skip to: 4654 +/* 4645 */ MCD_OPC_CheckPredicate, 16, 133, 7, 0, // Skip to: 6575 +/* 4650 */ MCD_OPC_Decode, 147, 18, 112, // Opcode: MSUB_D32_MM +/* 4654 */ MCD_OPC_FilterValue, 42, 9, 0, 0, // Skip to: 4668 +/* 4659 */ MCD_OPC_CheckPredicate, 16, 119, 7, 0, // Skip to: 6575 +/* 4664 */ MCD_OPC_Decode, 145, 19, 112, // Opcode: NMSUB_D32_MM +/* 4668 */ MCD_OPC_FilterValue, 48, 59, 0, 0, // Skip to: 4732 +/* 4673 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4676 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4690 +/* 4681 */ MCD_OPC_CheckPredicate, 18, 97, 7, 0, // Skip to: 6575 +/* 4686 */ MCD_OPC_Decode, 138, 13, 116, // Opcode: FADD_D32_MM +/* 4690 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4704 +/* 4695 */ MCD_OPC_CheckPredicate, 18, 83, 7, 0, // Skip to: 6575 +/* 4700 */ MCD_OPC_Decode, 156, 14, 116, // Opcode: FSUB_D32_MM +/* 4704 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4718 +/* 4709 */ MCD_OPC_CheckPredicate, 18, 69, 7, 0, // Skip to: 6575 +/* 4714 */ MCD_OPC_Decode, 239, 13, 116, // Opcode: FMUL_D32_MM +/* 4718 */ MCD_OPC_FilterValue, 7, 60, 7, 0, // Skip to: 6575 +/* 4723 */ MCD_OPC_CheckPredicate, 18, 55, 7, 0, // Skip to: 6575 +/* 4728 */ MCD_OPC_Decode, 177, 13, 116, // Opcode: FDIV_D32_MM +/* 4732 */ MCD_OPC_FilterValue, 56, 59, 0, 0, // Skip to: 4796 +/* 4737 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 4740 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4754 +/* 4745 */ MCD_OPC_CheckPredicate, 13, 33, 7, 0, // Skip to: 6575 +/* 4750 */ MCD_OPC_Decode, 236, 17, 117, // Opcode: MOVN_I_S_MM +/* 4754 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4768 +/* 4759 */ MCD_OPC_CheckPredicate, 13, 19, 7, 0, // Skip to: 6575 +/* 4764 */ MCD_OPC_Decode, 129, 18, 117, // Opcode: MOVZ_I_S_MM +/* 4768 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4782 +/* 4773 */ MCD_OPC_CheckPredicate, 17, 5, 7, 0, // Skip to: 6575 +/* 4778 */ MCD_OPC_Decode, 230, 17, 118, // Opcode: MOVN_I_D32_MM +/* 4782 */ MCD_OPC_FilterValue, 5, 252, 6, 0, // Skip to: 6575 +/* 4787 */ MCD_OPC_CheckPredicate, 17, 247, 6, 0, // Skip to: 6575 +/* 4792 */ MCD_OPC_Decode, 251, 17, 118, // Opcode: MOVZ_I_D32_MM +/* 4796 */ MCD_OPC_FilterValue, 59, 96, 2, 0, // Skip to: 5409 +/* 4801 */ MCD_OPC_ExtractField, 6, 7, // Inst{12-6} ... +/* 4804 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4825 +/* 4809 */ MCD_OPC_CheckPredicate, 19, 225, 6, 0, // Skip to: 6575 +/* 4814 */ MCD_OPC_CheckField, 13, 3, 1, 218, 6, 0, // Skip to: 6575 +/* 4821 */ MCD_OPC_Decode, 134, 17, 119, // Opcode: MFC1_MM +/* 4825 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 4846 +/* 4830 */ MCD_OPC_CheckPredicate, 18, 204, 6, 0, // Skip to: 6575 +/* 4835 */ MCD_OPC_CheckField, 13, 3, 1, 197, 6, 0, // Skip to: 6575 +/* 4842 */ MCD_OPC_Decode, 228, 13, 120, // Opcode: FMOV_D32_MM +/* 4846 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 4882 +/* 4851 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4854 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4868 +/* 4859 */ MCD_OPC_CheckPredicate, 20, 175, 6, 0, // Skip to: 6575 +/* 4864 */ MCD_OPC_Decode, 197, 10, 121, // Opcode: CVT_L_S_MM +/* 4868 */ MCD_OPC_FilterValue, 2, 166, 6, 0, // Skip to: 6575 +/* 4873 */ MCD_OPC_CheckPredicate, 20, 161, 6, 0, // Skip to: 6575 +/* 4878 */ MCD_OPC_Decode, 194, 10, 122, // Opcode: CVT_L_D64_MM +/* 4882 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4896 +/* 4887 */ MCD_OPC_CheckPredicate, 13, 147, 6, 0, // Skip to: 6575 +/* 4892 */ MCD_OPC_Decode, 222, 17, 123, // Opcode: MOVF_I_MM +/* 4896 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 4932 +/* 4901 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4904 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4918 +/* 4909 */ MCD_OPC_CheckPredicate, 19, 125, 6, 0, // Skip to: 6575 +/* 4914 */ MCD_OPC_Decode, 178, 20, 124, // Opcode: RSQRT_S_MM +/* 4918 */ MCD_OPC_FilterValue, 2, 116, 6, 0, // Skip to: 6575 +/* 4923 */ MCD_OPC_CheckPredicate, 18, 111, 6, 0, // Skip to: 6575 +/* 4928 */ MCD_OPC_Decode, 174, 20, 120, // Opcode: RSQRT_D32_MM +/* 4932 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 4968 +/* 4937 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4940 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4954 +/* 4945 */ MCD_OPC_CheckPredicate, 19, 89, 6, 0, // Skip to: 6575 +/* 4950 */ MCD_OPC_Decode, 135, 13, 124, // Opcode: FABS_S_MM +/* 4954 */ MCD_OPC_FilterValue, 1, 80, 6, 0, // Skip to: 6575 +/* 4959 */ MCD_OPC_CheckPredicate, 18, 75, 6, 0, // Skip to: 6575 +/* 4964 */ MCD_OPC_Decode, 131, 13, 120, // Opcode: FABS_D32_MM +/* 4968 */ MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 4989 +/* 4973 */ MCD_OPC_CheckPredicate, 19, 61, 6, 0, // Skip to: 6575 +/* 4978 */ MCD_OPC_CheckField, 13, 3, 1, 54, 6, 0, // Skip to: 6575 +/* 4985 */ MCD_OPC_Decode, 163, 18, 125, // Opcode: MTC1_MM +/* 4989 */ MCD_OPC_FilterValue, 36, 31, 0, 0, // Skip to: 5025 +/* 4994 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4997 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5011 +/* 5002 */ MCD_OPC_CheckPredicate, 19, 32, 6, 0, // Skip to: 6575 +/* 5007 */ MCD_OPC_Decode, 218, 10, 124, // Opcode: CVT_W_S_MM +/* 5011 */ MCD_OPC_FilterValue, 2, 23, 6, 0, // Skip to: 6575 +/* 5016 */ MCD_OPC_CheckPredicate, 18, 18, 6, 0, // Skip to: 6575 +/* 5021 */ MCD_OPC_Decode, 214, 10, 126, // Opcode: CVT_W_D32_MM +/* 5025 */ MCD_OPC_FilterValue, 37, 9, 0, 0, // Skip to: 5039 +/* 5030 */ MCD_OPC_CheckPredicate, 13, 4, 6, 0, // Skip to: 6575 +/* 5035 */ MCD_OPC_Decode, 243, 17, 123, // Opcode: MOVT_I_MM +/* 5039 */ MCD_OPC_FilterValue, 40, 31, 0, 0, // Skip to: 5075 +/* 5044 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5047 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5061 +/* 5052 */ MCD_OPC_CheckPredicate, 19, 238, 5, 0, // Skip to: 6575 +/* 5057 */ MCD_OPC_Decode, 152, 14, 124, // Opcode: FSQRT_S_MM +/* 5061 */ MCD_OPC_FilterValue, 2, 229, 5, 0, // Skip to: 6575 +/* 5066 */ MCD_OPC_CheckPredicate, 18, 224, 5, 0, // Skip to: 6575 +/* 5071 */ MCD_OPC_Decode, 148, 14, 120, // Opcode: FSQRT_D32_MM +/* 5075 */ MCD_OPC_FilterValue, 44, 59, 0, 0, // Skip to: 5139 +/* 5080 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5083 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5097 +/* 5088 */ MCD_OPC_CheckPredicate, 19, 202, 5, 0, // Skip to: 6575 +/* 5093 */ MCD_OPC_Decode, 215, 13, 124, // Opcode: FLOOR_W_S_MM +/* 5097 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5111 +/* 5102 */ MCD_OPC_CheckPredicate, 19, 188, 5, 0, // Skip to: 6575 +/* 5107 */ MCD_OPC_Decode, 143, 24, 124, // Opcode: TRUNC_W_S_MM +/* 5111 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 5125 +/* 5116 */ MCD_OPC_CheckPredicate, 18, 174, 5, 0, // Skip to: 6575 +/* 5121 */ MCD_OPC_Decode, 213, 13, 126, // Opcode: FLOOR_W_MM +/* 5125 */ MCD_OPC_FilterValue, 3, 165, 5, 0, // Skip to: 6575 +/* 5130 */ MCD_OPC_CheckPredicate, 18, 160, 5, 0, // Skip to: 6575 +/* 5135 */ MCD_OPC_Decode, 141, 24, 126, // Opcode: TRUNC_W_MM +/* 5139 */ MCD_OPC_FilterValue, 45, 16, 0, 0, // Skip to: 5160 +/* 5144 */ MCD_OPC_CheckPredicate, 18, 146, 5, 0, // Skip to: 6575 +/* 5149 */ MCD_OPC_CheckField, 13, 3, 1, 139, 5, 0, // Skip to: 6575 +/* 5156 */ MCD_OPC_Decode, 248, 13, 120, // Opcode: FNEG_D32_MM +/* 5160 */ MCD_OPC_FilterValue, 64, 32, 0, 0, // Skip to: 5197 +/* 5165 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5168 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5182 +/* 5173 */ MCD_OPC_CheckPredicate, 19, 117, 5, 0, // Skip to: 6575 +/* 5178 */ MCD_OPC_Decode, 145, 9, 127, // Opcode: CFC1_MM +/* 5182 */ MCD_OPC_FilterValue, 1, 108, 5, 0, // Skip to: 6575 +/* 5187 */ MCD_OPC_CheckPredicate, 18, 103, 5, 0, // Skip to: 6575 +/* 5192 */ MCD_OPC_Decode, 144, 17, 128, 1, // Opcode: MFHC1_D32_MM +/* 5197 */ MCD_OPC_FilterValue, 72, 31, 0, 0, // Skip to: 5233 +/* 5202 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5205 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5219 +/* 5210 */ MCD_OPC_CheckPredicate, 19, 80, 5, 0, // Skip to: 6575 +/* 5215 */ MCD_OPC_Decode, 139, 20, 124, // Opcode: RECIP_S_MM +/* 5219 */ MCD_OPC_FilterValue, 2, 71, 5, 0, // Skip to: 6575 +/* 5224 */ MCD_OPC_CheckPredicate, 18, 66, 5, 0, // Skip to: 6575 +/* 5229 */ MCD_OPC_Decode, 135, 20, 120, // Opcode: RECIP_D32_MM +/* 5233 */ MCD_OPC_FilterValue, 77, 33, 0, 0, // Skip to: 5271 +/* 5238 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5241 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5256 +/* 5246 */ MCD_OPC_CheckPredicate, 18, 44, 5, 0, // Skip to: 6575 +/* 5251 */ MCD_OPC_Decode, 184, 10, 129, 1, // Opcode: CVT_D32_S_MM +/* 5256 */ MCD_OPC_FilterValue, 1, 34, 5, 0, // Skip to: 6575 +/* 5261 */ MCD_OPC_CheckPredicate, 18, 29, 5, 0, // Skip to: 6575 +/* 5266 */ MCD_OPC_Decode, 186, 10, 129, 1, // Opcode: CVT_D32_W_MM +/* 5271 */ MCD_OPC_FilterValue, 96, 33, 0, 0, // Skip to: 5309 +/* 5276 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5279 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5294 +/* 5284 */ MCD_OPC_CheckPredicate, 19, 6, 5, 0, // Skip to: 6575 +/* 5289 */ MCD_OPC_Decode, 180, 10, 130, 1, // Opcode: CTC1_MM +/* 5294 */ MCD_OPC_FilterValue, 1, 252, 4, 0, // Skip to: 6575 +/* 5299 */ MCD_OPC_CheckPredicate, 18, 247, 4, 0, // Skip to: 6575 +/* 5304 */ MCD_OPC_Decode, 173, 18, 131, 1, // Opcode: MTHC1_D32_MM +/* 5309 */ MCD_OPC_FilterValue, 108, 59, 0, 0, // Skip to: 5373 +/* 5314 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5317 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5331 +/* 5322 */ MCD_OPC_CheckPredicate, 19, 224, 4, 0, // Skip to: 6575 +/* 5327 */ MCD_OPC_Decode, 134, 9, 124, // Opcode: CEIL_W_S_MM +/* 5331 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5345 +/* 5336 */ MCD_OPC_CheckPredicate, 19, 210, 4, 0, // Skip to: 6575 +/* 5341 */ MCD_OPC_Decode, 171, 20, 124, // Opcode: ROUND_W_S_MM +/* 5345 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 5359 +/* 5350 */ MCD_OPC_CheckPredicate, 18, 196, 4, 0, // Skip to: 6575 +/* 5355 */ MCD_OPC_Decode, 132, 9, 126, // Opcode: CEIL_W_MM +/* 5359 */ MCD_OPC_FilterValue, 3, 187, 4, 0, // Skip to: 6575 +/* 5364 */ MCD_OPC_CheckPredicate, 18, 182, 4, 0, // Skip to: 6575 +/* 5369 */ MCD_OPC_Decode, 169, 20, 126, // Opcode: ROUND_W_MM +/* 5373 */ MCD_OPC_FilterValue, 109, 173, 4, 0, // Skip to: 6575 +/* 5378 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5381 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5395 +/* 5386 */ MCD_OPC_CheckPredicate, 18, 160, 4, 0, // Skip to: 6575 +/* 5391 */ MCD_OPC_Decode, 203, 10, 126, // Opcode: CVT_S_D32_MM +/* 5395 */ MCD_OPC_FilterValue, 1, 151, 4, 0, // Skip to: 6575 +/* 5400 */ MCD_OPC_CheckPredicate, 19, 146, 4, 0, // Skip to: 6575 +/* 5405 */ MCD_OPC_Decode, 211, 10, 124, // Opcode: CVT_S_W_MM +/* 5409 */ MCD_OPC_FilterValue, 60, 137, 4, 0, // Skip to: 6575 +/* 5414 */ MCD_OPC_ExtractField, 6, 7, // Inst{12-6} ... +/* 5417 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5432 +/* 5422 */ MCD_OPC_CheckPredicate, 13, 124, 4, 0, // Skip to: 6575 +/* 5427 */ MCD_OPC_Decode, 231, 10, 132, 1, // Opcode: C_F_S_MM +/* 5432 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5447 +/* 5437 */ MCD_OPC_CheckPredicate, 13, 109, 4, 0, // Skip to: 6575 +/* 5442 */ MCD_OPC_Decode, 187, 11, 132, 1, // Opcode: C_UN_S_MM +/* 5447 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5462 +/* 5452 */ MCD_OPC_CheckPredicate, 13, 94, 4, 0, // Skip to: 6575 +/* 5457 */ MCD_OPC_Decode, 225, 10, 132, 1, // Opcode: C_EQ_S_MM +/* 5462 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5477 +/* 5467 */ MCD_OPC_CheckPredicate, 13, 79, 4, 0, // Skip to: 6575 +/* 5472 */ MCD_OPC_Decode, 169, 11, 132, 1, // Opcode: C_UEQ_S_MM +/* 5477 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 5492 +/* 5482 */ MCD_OPC_CheckPredicate, 13, 64, 4, 0, // Skip to: 6575 +/* 5487 */ MCD_OPC_Decode, 151, 11, 132, 1, // Opcode: C_OLT_S_MM +/* 5492 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 5507 +/* 5497 */ MCD_OPC_CheckPredicate, 13, 49, 4, 0, // Skip to: 6575 +/* 5502 */ MCD_OPC_Decode, 181, 11, 132, 1, // Opcode: C_ULT_S_MM +/* 5507 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 5522 +/* 5512 */ MCD_OPC_CheckPredicate, 13, 34, 4, 0, // Skip to: 6575 +/* 5517 */ MCD_OPC_Decode, 145, 11, 132, 1, // Opcode: C_OLE_S_MM +/* 5522 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 5537 +/* 5527 */ MCD_OPC_CheckPredicate, 13, 19, 4, 0, // Skip to: 6575 +/* 5532 */ MCD_OPC_Decode, 175, 11, 132, 1, // Opcode: C_ULE_S_MM +/* 5537 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 5552 +/* 5542 */ MCD_OPC_CheckPredicate, 13, 4, 4, 0, // Skip to: 6575 +/* 5547 */ MCD_OPC_Decode, 163, 11, 132, 1, // Opcode: C_SF_S_MM +/* 5552 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 5567 +/* 5557 */ MCD_OPC_CheckPredicate, 13, 245, 3, 0, // Skip to: 6575 +/* 5562 */ MCD_OPC_Decode, 255, 10, 132, 1, // Opcode: C_NGLE_S_MM +/* 5567 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 5582 +/* 5572 */ MCD_OPC_CheckPredicate, 13, 230, 3, 0, // Skip to: 6575 +/* 5577 */ MCD_OPC_Decode, 157, 11, 132, 1, // Opcode: C_SEQ_S_MM +/* 5582 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 5597 +/* 5587 */ MCD_OPC_CheckPredicate, 13, 215, 3, 0, // Skip to: 6575 +/* 5592 */ MCD_OPC_Decode, 133, 11, 132, 1, // Opcode: C_NGL_S_MM +/* 5597 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 5612 +/* 5602 */ MCD_OPC_CheckPredicate, 13, 200, 3, 0, // Skip to: 6575 +/* 5607 */ MCD_OPC_Decode, 243, 10, 132, 1, // Opcode: C_LT_S_MM +/* 5612 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5627 +/* 5617 */ MCD_OPC_CheckPredicate, 13, 185, 3, 0, // Skip to: 6575 +/* 5622 */ MCD_OPC_Decode, 249, 10, 132, 1, // Opcode: C_NGE_S_MM +/* 5627 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 5642 +/* 5632 */ MCD_OPC_CheckPredicate, 13, 170, 3, 0, // Skip to: 6575 +/* 5637 */ MCD_OPC_Decode, 237, 10, 132, 1, // Opcode: C_LE_S_MM +/* 5642 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5657 +/* 5647 */ MCD_OPC_CheckPredicate, 13, 155, 3, 0, // Skip to: 6575 +/* 5652 */ MCD_OPC_Decode, 139, 11, 132, 1, // Opcode: C_NGT_S_MM +/* 5657 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 5672 +/* 5662 */ MCD_OPC_CheckPredicate, 17, 140, 3, 0, // Skip to: 6575 +/* 5667 */ MCD_OPC_Decode, 227, 10, 133, 1, // Opcode: C_F_D32_MM +/* 5672 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 5687 +/* 5677 */ MCD_OPC_CheckPredicate, 17, 125, 3, 0, // Skip to: 6575 +/* 5682 */ MCD_OPC_Decode, 183, 11, 133, 1, // Opcode: C_UN_D32_MM +/* 5687 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 5702 +/* 5692 */ MCD_OPC_CheckPredicate, 17, 110, 3, 0, // Skip to: 6575 +/* 5697 */ MCD_OPC_Decode, 221, 10, 133, 1, // Opcode: C_EQ_D32_MM +/* 5702 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 5717 +/* 5707 */ MCD_OPC_CheckPredicate, 17, 95, 3, 0, // Skip to: 6575 +/* 5712 */ MCD_OPC_Decode, 165, 11, 133, 1, // Opcode: C_UEQ_D32_MM +/* 5717 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 5732 +/* 5722 */ MCD_OPC_CheckPredicate, 17, 80, 3, 0, // Skip to: 6575 +/* 5727 */ MCD_OPC_Decode, 147, 11, 133, 1, // Opcode: C_OLT_D32_MM +/* 5732 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 5747 +/* 5737 */ MCD_OPC_CheckPredicate, 17, 65, 3, 0, // Skip to: 6575 +/* 5742 */ MCD_OPC_Decode, 177, 11, 133, 1, // Opcode: C_ULT_D32_MM +/* 5747 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 5762 +/* 5752 */ MCD_OPC_CheckPredicate, 17, 50, 3, 0, // Skip to: 6575 +/* 5757 */ MCD_OPC_Decode, 141, 11, 133, 1, // Opcode: C_OLE_D32_MM +/* 5762 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 5777 +/* 5767 */ MCD_OPC_CheckPredicate, 17, 35, 3, 0, // Skip to: 6575 +/* 5772 */ MCD_OPC_Decode, 171, 11, 133, 1, // Opcode: C_ULE_D32_MM +/* 5777 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 5792 +/* 5782 */ MCD_OPC_CheckPredicate, 17, 20, 3, 0, // Skip to: 6575 +/* 5787 */ MCD_OPC_Decode, 159, 11, 133, 1, // Opcode: C_SF_D32_MM +/* 5792 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 5807 +/* 5797 */ MCD_OPC_CheckPredicate, 17, 5, 3, 0, // Skip to: 6575 +/* 5802 */ MCD_OPC_Decode, 251, 10, 133, 1, // Opcode: C_NGLE_D32_MM +/* 5807 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 5822 +/* 5812 */ MCD_OPC_CheckPredicate, 17, 246, 2, 0, // Skip to: 6575 +/* 5817 */ MCD_OPC_Decode, 153, 11, 133, 1, // Opcode: C_SEQ_D32_MM +/* 5822 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 5837 +/* 5827 */ MCD_OPC_CheckPredicate, 17, 231, 2, 0, // Skip to: 6575 +/* 5832 */ MCD_OPC_Decode, 129, 11, 133, 1, // Opcode: C_NGL_D32_MM +/* 5837 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 5852 +/* 5842 */ MCD_OPC_CheckPredicate, 17, 216, 2, 0, // Skip to: 6575 +/* 5847 */ MCD_OPC_Decode, 239, 10, 133, 1, // Opcode: C_LT_D32_MM +/* 5852 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 5867 +/* 5857 */ MCD_OPC_CheckPredicate, 17, 201, 2, 0, // Skip to: 6575 +/* 5862 */ MCD_OPC_Decode, 245, 10, 133, 1, // Opcode: C_NGE_D32_MM +/* 5867 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 5882 +/* 5872 */ MCD_OPC_CheckPredicate, 17, 186, 2, 0, // Skip to: 6575 +/* 5877 */ MCD_OPC_Decode, 233, 10, 133, 1, // Opcode: C_LE_D32_MM +/* 5882 */ MCD_OPC_FilterValue, 31, 176, 2, 0, // Skip to: 6575 +/* 5887 */ MCD_OPC_CheckPredicate, 17, 171, 2, 0, // Skip to: 6575 +/* 5892 */ MCD_OPC_Decode, 135, 11, 133, 1, // Opcode: C_NGT_D32_MM +/* 5897 */ MCD_OPC_FilterValue, 22, 48, 0, 0, // Skip to: 5950 +/* 5902 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 5905 */ MCD_OPC_FilterValue, 197, 1, 9, 0, 0, // Skip to: 5920 +/* 5911 */ MCD_OPC_CheckPredicate, 8, 147, 2, 0, // Skip to: 6575 +/* 5916 */ MCD_OPC_Decode, 205, 9, 54, // Opcode: CMPGU_EQ_QB_MM +/* 5920 */ MCD_OPC_FilterValue, 133, 2, 9, 0, 0, // Skip to: 5935 +/* 5926 */ MCD_OPC_CheckPredicate, 8, 132, 2, 0, // Skip to: 6575 +/* 5931 */ MCD_OPC_Decode, 209, 9, 54, // Opcode: CMPGU_LT_QB_MM +/* 5935 */ MCD_OPC_FilterValue, 197, 2, 122, 2, 0, // Skip to: 6575 +/* 5941 */ MCD_OPC_CheckPredicate, 8, 117, 2, 0, // Skip to: 6575 +/* 5946 */ MCD_OPC_Decode, 207, 9, 54, // Opcode: CMPGU_LE_QB_MM +/* 5950 */ MCD_OPC_FilterValue, 24, 115, 1, 0, // Skip to: 6326 +/* 5955 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5958 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5972 +/* 5963 */ MCD_OPC_CheckPredicate, 6, 95, 2, 0, // Skip to: 6575 +/* 5968 */ MCD_OPC_Decode, 153, 16, 99, // Opcode: LWL_MM +/* 5972 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5986 +/* 5977 */ MCD_OPC_CheckPredicate, 6, 81, 2, 0, // Skip to: 6575 +/* 5982 */ MCD_OPC_Decode, 166, 16, 99, // Opcode: LWR_MM +/* 5986 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6000 +/* 5991 */ MCD_OPC_CheckPredicate, 6, 67, 2, 0, // Skip to: 6575 +/* 5996 */ MCD_OPC_Decode, 242, 19, 100, // Opcode: PREF_MM +/* 6000 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 6014 +/* 6005 */ MCD_OPC_CheckPredicate, 6, 53, 2, 0, // Skip to: 6575 +/* 6010 */ MCD_OPC_Decode, 243, 15, 99, // Opcode: LL_MM +/* 6014 */ MCD_OPC_FilterValue, 6, 123, 0, 0, // Skip to: 6142 +/* 6019 */ MCD_OPC_ExtractField, 9, 3, // Inst{11-9} ... +/* 6022 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6037 +/* 6027 */ MCD_OPC_CheckPredicate, 21, 31, 2, 0, // Skip to: 6575 +/* 6032 */ MCD_OPC_Decode, 177, 15, 134, 1, // Opcode: LBuE_MM +/* 6037 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6052 +/* 6042 */ MCD_OPC_CheckPredicate, 21, 16, 2, 0, // Skip to: 6575 +/* 6047 */ MCD_OPC_Decode, 229, 15, 134, 1, // Opcode: LHuE_MM +/* 6052 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6067 +/* 6057 */ MCD_OPC_CheckPredicate, 22, 1, 2, 0, // Skip to: 6575 +/* 6062 */ MCD_OPC_Decode, 152, 16, 134, 1, // Opcode: LWLE_MM +/* 6067 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 6082 +/* 6072 */ MCD_OPC_CheckPredicate, 22, 242, 1, 0, // Skip to: 6575 +/* 6077 */ MCD_OPC_Decode, 165, 16, 134, 1, // Opcode: LWRE_MM +/* 6082 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 6097 +/* 6087 */ MCD_OPC_CheckPredicate, 21, 227, 1, 0, // Skip to: 6575 +/* 6092 */ MCD_OPC_Decode, 158, 15, 134, 1, // Opcode: LBE_MM +/* 6097 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 6112 +/* 6102 */ MCD_OPC_CheckPredicate, 21, 212, 1, 0, // Skip to: 6575 +/* 6107 */ MCD_OPC_Decode, 210, 15, 134, 1, // Opcode: LHE_MM +/* 6112 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 6127 +/* 6117 */ MCD_OPC_CheckPredicate, 21, 197, 1, 0, // Skip to: 6575 +/* 6122 */ MCD_OPC_Decode, 241, 15, 134, 1, // Opcode: LLE_MM +/* 6127 */ MCD_OPC_FilterValue, 7, 187, 1, 0, // Skip to: 6575 +/* 6132 */ MCD_OPC_CheckPredicate, 21, 182, 1, 0, // Skip to: 6575 +/* 6137 */ MCD_OPC_Decode, 145, 16, 134, 1, // Opcode: LWE_MM +/* 6142 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 6156 +/* 6147 */ MCD_OPC_CheckPredicate, 6, 167, 1, 0, // Skip to: 6575 +/* 6152 */ MCD_OPC_Decode, 150, 23, 99, // Opcode: SWL_MM +/* 6156 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 6170 +/* 6161 */ MCD_OPC_CheckPredicate, 6, 153, 1, 0, // Skip to: 6575 +/* 6166 */ MCD_OPC_Decode, 161, 23, 99, // Opcode: SWR_MM +/* 6170 */ MCD_OPC_FilterValue, 10, 123, 0, 0, // Skip to: 6298 +/* 6175 */ MCD_OPC_ExtractField, 9, 3, // Inst{11-9} ... +/* 6178 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6193 +/* 6183 */ MCD_OPC_CheckPredicate, 22, 131, 1, 0, // Skip to: 6575 +/* 6188 */ MCD_OPC_Decode, 149, 23, 134, 1, // Opcode: SWLE_MM +/* 6193 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6208 +/* 6198 */ MCD_OPC_CheckPredicate, 22, 116, 1, 0, // Skip to: 6575 +/* 6203 */ MCD_OPC_Decode, 160, 23, 134, 1, // Opcode: SWRE_MM +/* 6208 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6223 +/* 6213 */ MCD_OPC_CheckPredicate, 21, 101, 1, 0, // Skip to: 6575 +/* 6218 */ MCD_OPC_Decode, 240, 19, 135, 1, // Opcode: PREFE_MM +/* 6223 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 6238 +/* 6228 */ MCD_OPC_CheckPredicate, 21, 86, 1, 0, // Skip to: 6575 +/* 6233 */ MCD_OPC_Decode, 248, 8, 135, 1, // Opcode: CACHEE_MM +/* 6238 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 6253 +/* 6243 */ MCD_OPC_CheckPredicate, 21, 71, 1, 0, // Skip to: 6575 +/* 6248 */ MCD_OPC_Decode, 199, 20, 134, 1, // Opcode: SBE_MM +/* 6253 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 6268 +/* 6258 */ MCD_OPC_CheckPredicate, 21, 56, 1, 0, // Skip to: 6575 +/* 6263 */ MCD_OPC_Decode, 149, 21, 134, 1, // Opcode: SHE_MM +/* 6268 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 6283 +/* 6273 */ MCD_OPC_CheckPredicate, 21, 41, 1, 0, // Skip to: 6575 +/* 6278 */ MCD_OPC_Decode, 212, 20, 134, 1, // Opcode: SCE_MM +/* 6283 */ MCD_OPC_FilterValue, 7, 31, 1, 0, // Skip to: 6575 +/* 6288 */ MCD_OPC_CheckPredicate, 21, 26, 1, 0, // Skip to: 6575 +/* 6293 */ MCD_OPC_Decode, 143, 23, 134, 1, // Opcode: SWE_MM +/* 6298 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 6312 +/* 6303 */ MCD_OPC_CheckPredicate, 6, 11, 1, 0, // Skip to: 6575 +/* 6308 */ MCD_OPC_Decode, 214, 20, 99, // Opcode: SC_MM +/* 6312 */ MCD_OPC_FilterValue, 14, 2, 1, 0, // Skip to: 6575 +/* 6317 */ MCD_OPC_CheckPredicate, 6, 253, 0, 0, // Skip to: 6575 +/* 6322 */ MCD_OPC_Decode, 170, 16, 99, // Opcode: LWU_MM +/* 6326 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 6340 +/* 6331 */ MCD_OPC_CheckPredicate, 6, 239, 0, 0, // Skip to: 6575 +/* 6336 */ MCD_OPC_Decode, 186, 24, 108, // Opcode: XORi_MM +/* 6340 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 6355 +/* 6345 */ MCD_OPC_CheckPredicate, 6, 225, 0, 0, // Skip to: 6575 +/* 6350 */ MCD_OPC_Decode, 250, 14, 136, 1, // Opcode: JALS_MM +/* 6355 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 6370 +/* 6360 */ MCD_OPC_CheckPredicate, 6, 210, 0, 0, // Skip to: 6575 +/* 6365 */ MCD_OPC_Decode, 130, 6, 137, 1, // Opcode: ADDIUPC_MM +/* 6370 */ MCD_OPC_FilterValue, 36, 9, 0, 0, // Skip to: 6384 +/* 6375 */ MCD_OPC_CheckPredicate, 7, 195, 0, 0, // Skip to: 6575 +/* 6380 */ MCD_OPC_Decode, 248, 21, 97, // Opcode: SLTi_MM +/* 6384 */ MCD_OPC_FilterValue, 37, 10, 0, 0, // Skip to: 6399 +/* 6389 */ MCD_OPC_CheckPredicate, 6, 181, 0, 0, // Skip to: 6575 +/* 6394 */ MCD_OPC_Decode, 208, 7, 138, 1, // Opcode: BEQ_MM +/* 6399 */ MCD_OPC_FilterValue, 38, 10, 0, 0, // Skip to: 6414 +/* 6404 */ MCD_OPC_CheckPredicate, 19, 166, 0, 0, // Skip to: 6575 +/* 6409 */ MCD_OPC_Decode, 135, 23, 139, 1, // Opcode: SWC1_MM +/* 6414 */ MCD_OPC_FilterValue, 39, 10, 0, 0, // Skip to: 6429 +/* 6419 */ MCD_OPC_CheckPredicate, 19, 151, 0, 0, // Skip to: 6575 +/* 6424 */ MCD_OPC_Decode, 137, 16, 139, 1, // Opcode: LWC1_MM +/* 6429 */ MCD_OPC_FilterValue, 44, 9, 0, 0, // Skip to: 6443 +/* 6434 */ MCD_OPC_CheckPredicate, 7, 136, 0, 0, // Skip to: 6575 +/* 6439 */ MCD_OPC_Decode, 251, 21, 97, // Opcode: SLTiu_MM +/* 6443 */ MCD_OPC_FilterValue, 45, 10, 0, 0, // Skip to: 6458 +/* 6448 */ MCD_OPC_CheckPredicate, 6, 122, 0, 0, // Skip to: 6575 +/* 6453 */ MCD_OPC_Decode, 198, 8, 138, 1, // Opcode: BNE_MM +/* 6458 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 6473 +/* 6463 */ MCD_OPC_CheckPredicate, 18, 107, 0, 0, // Skip to: 6575 +/* 6468 */ MCD_OPC_Decode, 230, 20, 139, 1, // Opcode: SDC1_MM_D32 +/* 6473 */ MCD_OPC_FilterValue, 47, 10, 0, 0, // Skip to: 6488 +/* 6478 */ MCD_OPC_CheckPredicate, 18, 92, 0, 0, // Skip to: 6575 +/* 6483 */ MCD_OPC_Decode, 183, 15, 139, 1, // Opcode: LDC1_MM_D32 +/* 6488 */ MCD_OPC_FilterValue, 52, 9, 0, 0, // Skip to: 6502 +/* 6493 */ MCD_OPC_CheckPredicate, 6, 77, 0, 0, // Skip to: 6575 +/* 6498 */ MCD_OPC_Decode, 233, 6, 108, // Opcode: ANDi_MM +/* 6502 */ MCD_OPC_FilterValue, 53, 10, 0, 0, // Skip to: 6517 +/* 6507 */ MCD_OPC_CheckPredicate, 6, 63, 0, 0, // Skip to: 6575 +/* 6512 */ MCD_OPC_Decode, 145, 15, 136, 1, // Opcode: J_MM +/* 6517 */ MCD_OPC_FilterValue, 60, 10, 0, 0, // Skip to: 6532 +/* 6522 */ MCD_OPC_CheckPredicate, 6, 48, 0, 0, // Skip to: 6575 +/* 6527 */ MCD_OPC_Decode, 252, 14, 140, 1, // Opcode: JALX_MM +/* 6532 */ MCD_OPC_FilterValue, 61, 10, 0, 0, // Skip to: 6547 +/* 6537 */ MCD_OPC_CheckPredicate, 6, 33, 0, 0, // Skip to: 6575 +/* 6542 */ MCD_OPC_Decode, 253, 14, 136, 1, // Opcode: JAL_MM +/* 6547 */ MCD_OPC_FilterValue, 62, 9, 0, 0, // Skip to: 6561 +/* 6552 */ MCD_OPC_CheckPredicate, 7, 18, 0, 0, // Skip to: 6575 +/* 6557 */ MCD_OPC_Decode, 169, 23, 98, // Opcode: SW_MM +/* 6561 */ MCD_OPC_FilterValue, 63, 9, 0, 0, // Skip to: 6575 +/* 6566 */ MCD_OPC_CheckPredicate, 7, 4, 0, 0, // Skip to: 6575 +/* 6571 */ MCD_OPC_Decode, 179, 16, 98, // Opcode: LW_MM +/* 6575 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMicroMipsDSP32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 62, 10, 0, 0, // Skip to: 18 +/* 8 */ MCD_OPC_CheckPredicate, 8, 20, 0, 0, // Skip to: 33 +/* 13 */ MCD_OPC_Decode, 141, 23, 141, 1, // Opcode: SWDSP_MM +/* 18 */ MCD_OPC_FilterValue, 63, 10, 0, 0, // Skip to: 33 +/* 23 */ MCD_OPC_CheckPredicate, 8, 5, 0, 0, // Skip to: 33 +/* 28 */ MCD_OPC_Decode, 143, 16, 141, 1, // Opcode: LWDSP_MM +/* 33 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMicroMipsFP6432[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 21, 39, 1, 0, // Skip to: 303 +/* 8 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 11 */ MCD_OPC_FilterValue, 59, 48, 0, 0, // Skip to: 64 +/* 16 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 19 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 34 +/* 24 */ MCD_OPC_CheckPredicate, 20, 48, 1, 0, // Skip to: 333 +/* 29 */ MCD_OPC_Decode, 162, 18, 142, 1, // Opcode: MTC1_D64_MM +/* 34 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 49 +/* 39 */ MCD_OPC_CheckPredicate, 20, 33, 1, 0, // Skip to: 333 +/* 44 */ MCD_OPC_Decode, 146, 17, 143, 1, // Opcode: MFHC1_D64_MM +/* 49 */ MCD_OPC_FilterValue, 7, 23, 1, 0, // Skip to: 333 +/* 54 */ MCD_OPC_CheckPredicate, 20, 18, 1, 0, // Skip to: 333 +/* 59 */ MCD_OPC_Decode, 175, 18, 144, 1, // Opcode: MTHC1_D64_MM +/* 64 */ MCD_OPC_FilterValue, 123, 16, 0, 0, // Skip to: 85 +/* 69 */ MCD_OPC_CheckPredicate, 20, 3, 1, 0, // Skip to: 333 +/* 74 */ MCD_OPC_CheckField, 11, 5, 4, 252, 0, 0, // Skip to: 333 +/* 81 */ MCD_OPC_Decode, 230, 13, 122, // Opcode: FMOV_D64_MM +/* 85 */ MCD_OPC_FilterValue, 176, 2, 10, 0, 0, // Skip to: 101 +/* 91 */ MCD_OPC_CheckPredicate, 20, 237, 0, 0, // Skip to: 333 +/* 96 */ MCD_OPC_Decode, 140, 13, 145, 1, // Opcode: FADD_D64_MM +/* 101 */ MCD_OPC_FilterValue, 187, 2, 17, 0, 0, // Skip to: 124 +/* 107 */ MCD_OPC_CheckPredicate, 20, 221, 0, 0, // Skip to: 333 +/* 112 */ MCD_OPC_CheckField, 11, 5, 9, 214, 0, 0, // Skip to: 333 +/* 119 */ MCD_OPC_Decode, 216, 10, 146, 1, // Opcode: CVT_W_D64_MM +/* 124 */ MCD_OPC_FilterValue, 240, 2, 10, 0, 0, // Skip to: 140 +/* 130 */ MCD_OPC_CheckPredicate, 20, 198, 0, 0, // Skip to: 333 +/* 135 */ MCD_OPC_Decode, 158, 14, 145, 1, // Opcode: FSUB_D64_MM +/* 140 */ MCD_OPC_FilterValue, 176, 3, 10, 0, 0, // Skip to: 156 +/* 146 */ MCD_OPC_CheckPredicate, 20, 182, 0, 0, // Skip to: 333 +/* 151 */ MCD_OPC_Decode, 241, 13, 145, 1, // Opcode: FMUL_D64_MM +/* 156 */ MCD_OPC_FilterValue, 240, 3, 10, 0, 0, // Skip to: 172 +/* 162 */ MCD_OPC_CheckPredicate, 20, 166, 0, 0, // Skip to: 333 +/* 167 */ MCD_OPC_Decode, 179, 13, 145, 1, // Opcode: FDIV_D64_MM +/* 172 */ MCD_OPC_FilterValue, 187, 4, 45, 0, 0, // Skip to: 223 +/* 178 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 181 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 195 +/* 186 */ MCD_OPC_CheckPredicate, 20, 142, 0, 0, // Skip to: 333 +/* 191 */ MCD_OPC_Decode, 176, 20, 122, // Opcode: RSQRT_D64_MM +/* 195 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 209 +/* 200 */ MCD_OPC_CheckPredicate, 20, 128, 0, 0, // Skip to: 333 +/* 205 */ MCD_OPC_Decode, 150, 14, 122, // Opcode: FSQRT_D64_MM +/* 209 */ MCD_OPC_FilterValue, 10, 119, 0, 0, // Skip to: 333 +/* 214 */ MCD_OPC_CheckPredicate, 20, 114, 0, 0, // Skip to: 333 +/* 219 */ MCD_OPC_Decode, 137, 20, 122, // Opcode: RECIP_D64_MM +/* 223 */ MCD_OPC_FilterValue, 251, 6, 104, 0, 0, // Skip to: 333 +/* 229 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 232 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 246 +/* 237 */ MCD_OPC_CheckPredicate, 20, 91, 0, 0, // Skip to: 333 +/* 242 */ MCD_OPC_Decode, 189, 10, 121, // Opcode: CVT_D64_S_MM +/* 246 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 261 +/* 251 */ MCD_OPC_CheckPredicate, 20, 77, 0, 0, // Skip to: 333 +/* 256 */ MCD_OPC_Decode, 205, 10, 146, 1, // Opcode: CVT_S_D64_MM +/* 261 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 275 +/* 266 */ MCD_OPC_CheckPredicate, 20, 62, 0, 0, // Skip to: 333 +/* 271 */ MCD_OPC_Decode, 133, 13, 122, // Opcode: FABS_D64_MM +/* 275 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 289 +/* 280 */ MCD_OPC_CheckPredicate, 20, 48, 0, 0, // Skip to: 333 +/* 285 */ MCD_OPC_Decode, 250, 13, 122, // Opcode: FNEG_D64_MM +/* 289 */ MCD_OPC_FilterValue, 6, 39, 0, 0, // Skip to: 333 +/* 294 */ MCD_OPC_CheckPredicate, 20, 34, 0, 0, // Skip to: 333 +/* 299 */ MCD_OPC_Decode, 191, 10, 121, // Opcode: CVT_D64_W_MM +/* 303 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 318 +/* 308 */ MCD_OPC_CheckPredicate, 23, 20, 0, 0, // Skip to: 333 +/* 313 */ MCD_OPC_Decode, 229, 20, 139, 1, // Opcode: SDC1_D64_MMR6 +/* 318 */ MCD_OPC_FilterValue, 47, 10, 0, 0, // Skip to: 333 +/* 323 */ MCD_OPC_CheckPredicate, 23, 5, 0, 0, // Skip to: 333 +/* 328 */ MCD_OPC_Decode, 182, 15, 139, 1, // Opcode: LDC1_D64_MMR6 +/* 333 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMicroMipsR616[] = { +/* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 3 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 41 +/* 8 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 11 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 26 +/* 16 */ MCD_OPC_CheckPredicate, 24, 173, 1, 0, // Skip to: 450 +/* 21 */ MCD_OPC_Decode, 171, 6, 147, 1, // Opcode: ADDU16_MMR6 +/* 26 */ MCD_OPC_FilterValue, 1, 163, 1, 0, // Skip to: 450 +/* 31 */ MCD_OPC_CheckPredicate, 24, 158, 1, 0, // Skip to: 450 +/* 36 */ MCD_OPC_Decode, 224, 22, 147, 1, // Opcode: SUBU16_MMR6 +/* 41 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 55 +/* 46 */ MCD_OPC_CheckPredicate, 24, 143, 1, 0, // Skip to: 450 +/* 51 */ MCD_OPC_Decode, 209, 17, 33, // Opcode: MOVE16_MMR6 +/* 55 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 91 +/* 60 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 63 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 77 +/* 68 */ MCD_OPC_CheckPredicate, 24, 121, 1, 0, // Skip to: 450 +/* 73 */ MCD_OPC_Decode, 221, 21, 34, // Opcode: SLL16_MMR6 +/* 77 */ MCD_OPC_FilterValue, 1, 112, 1, 0, // Skip to: 450 +/* 82 */ MCD_OPC_CheckPredicate, 24, 107, 1, 0, // Skip to: 450 +/* 87 */ MCD_OPC_Decode, 162, 22, 34, // Opcode: SRL16_MMR6 +/* 91 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 105 +/* 96 */ MCD_OPC_CheckPredicate, 24, 93, 1, 0, // Skip to: 450 +/* 101 */ MCD_OPC_Decode, 222, 6, 35, // Opcode: ANDI16_MMR6 +/* 105 */ MCD_OPC_FilterValue, 17, 228, 0, 0, // Skip to: 338 +/* 110 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 113 */ MCD_OPC_FilterValue, 0, 206, 0, 0, // Skip to: 324 +/* 118 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 121 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 159 +/* 126 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 129 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 144 +/* 134 */ MCD_OPC_CheckPredicate, 24, 55, 1, 0, // Skip to: 450 +/* 139 */ MCD_OPC_Decode, 159, 19, 148, 1, // Opcode: NOT16_MMR6 +/* 144 */ MCD_OPC_FilterValue, 1, 45, 1, 0, // Skip to: 450 +/* 149 */ MCD_OPC_CheckPredicate, 24, 40, 1, 0, // Skip to: 450 +/* 154 */ MCD_OPC_Decode, 174, 24, 149, 1, // Opcode: XOR16_MMR6 +/* 159 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 197 +/* 164 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 167 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 182 +/* 172 */ MCD_OPC_CheckPredicate, 24, 17, 1, 0, // Skip to: 450 +/* 177 */ MCD_OPC_Decode, 218, 6, 149, 1, // Opcode: AND16_MMR6 +/* 182 */ MCD_OPC_FilterValue, 1, 7, 1, 0, // Skip to: 450 +/* 187 */ MCD_OPC_CheckPredicate, 24, 2, 1, 0, // Skip to: 450 +/* 192 */ MCD_OPC_Decode, 165, 19, 149, 1, // Opcode: OR16_MMR6 +/* 197 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 233 +/* 202 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 205 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 219 +/* 210 */ MCD_OPC_CheckPredicate, 24, 235, 0, 0, // Skip to: 450 +/* 215 */ MCD_OPC_Decode, 155, 16, 38, // Opcode: LWM16_MMR6 +/* 219 */ MCD_OPC_FilterValue, 1, 226, 0, 0, // Skip to: 450 +/* 224 */ MCD_OPC_CheckPredicate, 24, 221, 0, 0, // Skip to: 450 +/* 229 */ MCD_OPC_Decode, 152, 23, 38, // Opcode: SWM16_MMR6 +/* 233 */ MCD_OPC_FilterValue, 3, 212, 0, 0, // Skip to: 450 +/* 238 */ MCD_OPC_ExtractField, 3, 2, // Inst{4-3} ... +/* 241 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 256 +/* 246 */ MCD_OPC_CheckPredicate, 24, 199, 0, 0, // Skip to: 450 +/* 251 */ MCD_OPC_Decode, 137, 15, 150, 1, // Opcode: JRC16_MMR6 +/* 256 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 271 +/* 261 */ MCD_OPC_CheckPredicate, 24, 184, 0, 0, // Skip to: 450 +/* 266 */ MCD_OPC_Decode, 239, 14, 150, 1, // Opcode: JALRC16_MMR6 +/* 271 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 286 +/* 276 */ MCD_OPC_CheckPredicate, 24, 169, 0, 0, // Skip to: 450 +/* 281 */ MCD_OPC_Decode, 138, 15, 151, 1, // Opcode: JRCADDIUSP_MMR6 +/* 286 */ MCD_OPC_FilterValue, 3, 159, 0, 0, // Skip to: 450 +/* 291 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 294 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 309 +/* 299 */ MCD_OPC_CheckPredicate, 24, 146, 0, 0, // Skip to: 450 +/* 304 */ MCD_OPC_Decode, 213, 8, 152, 1, // Opcode: BREAK16_MMR6 +/* 309 */ MCD_OPC_FilterValue, 1, 136, 0, 0, // Skip to: 450 +/* 314 */ MCD_OPC_CheckPredicate, 24, 131, 0, 0, // Skip to: 450 +/* 319 */ MCD_OPC_Decode, 221, 20, 152, 1, // Opcode: SDBBP16_MMR6 +/* 324 */ MCD_OPC_FilterValue, 1, 121, 0, 0, // Skip to: 450 +/* 329 */ MCD_OPC_CheckPredicate, 24, 116, 0, 0, // Skip to: 450 +/* 334 */ MCD_OPC_Decode, 213, 17, 48, // Opcode: MOVEP_MMR6 +/* 338 */ MCD_OPC_FilterValue, 34, 9, 0, 0, // Skip to: 352 +/* 343 */ MCD_OPC_CheckPredicate, 24, 102, 0, 0, // Skip to: 450 +/* 348 */ MCD_OPC_Decode, 195, 20, 32, // Opcode: SB16_MMR6 +/* 352 */ MCD_OPC_FilterValue, 35, 9, 0, 0, // Skip to: 366 +/* 357 */ MCD_OPC_CheckPredicate, 24, 88, 0, 0, // Skip to: 450 +/* 362 */ MCD_OPC_Decode, 202, 7, 49, // Opcode: BEQZC16_MMR6 +/* 366 */ MCD_OPC_FilterValue, 42, 9, 0, 0, // Skip to: 380 +/* 371 */ MCD_OPC_CheckPredicate, 24, 74, 0, 0, // Skip to: 450 +/* 376 */ MCD_OPC_Decode, 145, 21, 32, // Opcode: SH16_MMR6 +/* 380 */ MCD_OPC_FilterValue, 43, 9, 0, 0, // Skip to: 394 +/* 385 */ MCD_OPC_CheckPredicate, 24, 60, 0, 0, // Skip to: 450 +/* 390 */ MCD_OPC_Decode, 192, 8, 49, // Opcode: BNEZC16_MMR6 +/* 394 */ MCD_OPC_FilterValue, 50, 9, 0, 0, // Skip to: 408 +/* 399 */ MCD_OPC_CheckPredicate, 24, 46, 0, 0, // Skip to: 450 +/* 404 */ MCD_OPC_Decode, 164, 23, 42, // Opcode: SWSP_MMR6 +/* 408 */ MCD_OPC_FilterValue, 51, 9, 0, 0, // Skip to: 422 +/* 413 */ MCD_OPC_CheckPredicate, 24, 32, 0, 0, // Skip to: 450 +/* 418 */ MCD_OPC_Decode, 162, 7, 50, // Opcode: BC16_MMR6 +/* 422 */ MCD_OPC_FilterValue, 58, 9, 0, 0, // Skip to: 436 +/* 427 */ MCD_OPC_CheckPredicate, 24, 18, 0, 0, // Skip to: 450 +/* 432 */ MCD_OPC_Decode, 130, 23, 32, // Opcode: SW16_MMR6 +/* 436 */ MCD_OPC_FilterValue, 59, 9, 0, 0, // Skip to: 450 +/* 441 */ MCD_OPC_CheckPredicate, 24, 4, 0, 0, // Skip to: 450 +/* 446 */ MCD_OPC_Decode, 232, 15, 51, // Opcode: LI16_MMR6 +/* 450 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMicroMipsR632[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 98, 4, 0, // Skip to: 1130 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 0, 112, 0, 0, // Skip to: 128 +/* 16 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 19 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 78 +/* 24 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... +/* 27 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 41 +/* 32 */ MCD_OPC_CheckPredicate, 24, 32, 0, 0, // Skip to: 69 +/* 37 */ MCD_OPC_Decode, 187, 22, 10, // Opcode: SSNOP_MMR6 +/* 41 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 55 +/* 46 */ MCD_OPC_CheckPredicate, 24, 18, 0, 0, // Skip to: 69 +/* 51 */ MCD_OPC_Decode, 208, 12, 10, // Opcode: EHB_MMR6 +/* 55 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 69 +/* 60 */ MCD_OPC_CheckPredicate, 24, 4, 0, 0, // Skip to: 69 +/* 65 */ MCD_OPC_Decode, 183, 19, 10, // Opcode: PAUSE_MMR6 +/* 69 */ MCD_OPC_CheckPredicate, 24, 80, 12, 0, // Skip to: 3226 +/* 74 */ MCD_OPC_Decode, 236, 21, 52, // Opcode: SLL_MMR6 +/* 78 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 92 +/* 83 */ MCD_OPC_CheckPredicate, 24, 66, 12, 0, // Skip to: 3226 +/* 88 */ MCD_OPC_Decode, 254, 20, 55, // Opcode: SELEQZ_MMR6 +/* 92 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 106 +/* 97 */ MCD_OPC_CheckPredicate, 24, 52, 12, 0, // Skip to: 3226 +/* 102 */ MCD_OPC_Decode, 133, 21, 55, // Opcode: SELNEZ_MMR6 +/* 106 */ MCD_OPC_FilterValue, 7, 43, 12, 0, // Skip to: 3226 +/* 111 */ MCD_OPC_CheckPredicate, 24, 38, 12, 0, // Skip to: 3226 +/* 116 */ MCD_OPC_CheckField, 14, 2, 0, 31, 12, 0, // Skip to: 3226 +/* 123 */ MCD_OPC_Decode, 130, 20, 153, 1, // Opcode: RDHWR_MMR6 +/* 128 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 142 +/* 133 */ MCD_OPC_CheckPredicate, 24, 16, 12, 0, // Skip to: 3226 +/* 138 */ MCD_OPC_Decode, 216, 8, 56, // Opcode: BREAK_MMR6 +/* 142 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 156 +/* 147 */ MCD_OPC_CheckPredicate, 24, 2, 12, 0, // Skip to: 3226 +/* 152 */ MCD_OPC_Decode, 232, 14, 57, // Opcode: INS_MMR6 +/* 156 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 178 +/* 161 */ MCD_OPC_CheckPredicate, 24, 244, 11, 0, // Skip to: 3226 +/* 166 */ MCD_OPC_CheckField, 6, 3, 0, 237, 11, 0, // Skip to: 3226 +/* 173 */ MCD_OPC_Decode, 248, 15, 154, 1, // Opcode: LSA_MMR6 +/* 178 */ MCD_OPC_FilterValue, 16, 136, 0, 0, // Skip to: 319 +/* 183 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 186 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 207 +/* 191 */ MCD_OPC_CheckPredicate, 24, 214, 11, 0, // Skip to: 3226 +/* 196 */ MCD_OPC_CheckField, 16, 5, 0, 207, 11, 0, // Skip to: 3226 +/* 203 */ MCD_OPC_Decode, 195, 9, 25, // Opcode: CLZ_MMR6 +/* 207 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 221 +/* 212 */ MCD_OPC_CheckPredicate, 24, 193, 11, 0, // Skip to: 3226 +/* 217 */ MCD_OPC_Decode, 200, 6, 55, // Opcode: ADD_MMR6 +/* 221 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 235 +/* 226 */ MCD_OPC_CheckPredicate, 24, 179, 11, 0, // Skip to: 3226 +/* 231 */ MCD_OPC_Decode, 176, 6, 55, // Opcode: ADDU_MMR6 +/* 235 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 249 +/* 240 */ MCD_OPC_CheckPredicate, 24, 165, 11, 0, // Skip to: 3226 +/* 245 */ MCD_OPC_Decode, 247, 22, 55, // Opcode: SUB_MMR6 +/* 249 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 263 +/* 254 */ MCD_OPC_CheckPredicate, 24, 151, 11, 0, // Skip to: 3226 +/* 259 */ MCD_OPC_Decode, 229, 22, 55, // Opcode: SUBU_MMR6 +/* 263 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 277 +/* 268 */ MCD_OPC_CheckPredicate, 24, 137, 11, 0, // Skip to: 3226 +/* 273 */ MCD_OPC_Decode, 228, 6, 55, // Opcode: AND_MMR6 +/* 277 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 291 +/* 282 */ MCD_OPC_CheckPredicate, 24, 123, 11, 0, // Skip to: 3226 +/* 287 */ MCD_OPC_Decode, 172, 19, 55, // Opcode: OR_MMR6 +/* 291 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 305 +/* 296 */ MCD_OPC_CheckPredicate, 24, 109, 11, 0, // Skip to: 3226 +/* 301 */ MCD_OPC_Decode, 155, 19, 55, // Opcode: NOR_MMR6 +/* 305 */ MCD_OPC_FilterValue, 12, 100, 11, 0, // Skip to: 3226 +/* 310 */ MCD_OPC_CheckPredicate, 24, 95, 11, 0, // Skip to: 3226 +/* 315 */ MCD_OPC_Decode, 181, 24, 55, // Opcode: XOR_MMR6 +/* 319 */ MCD_OPC_FilterValue, 24, 115, 0, 0, // Skip to: 439 +/* 324 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 327 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 341 +/* 332 */ MCD_OPC_CheckPredicate, 24, 73, 11, 0, // Skip to: 3226 +/* 337 */ MCD_OPC_Decode, 246, 18, 55, // Opcode: MUL_MMR6 +/* 341 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 355 +/* 346 */ MCD_OPC_CheckPredicate, 24, 59, 11, 0, // Skip to: 3226 +/* 351 */ MCD_OPC_Decode, 203, 18, 55, // Opcode: MUH_MMR6 +/* 355 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 369 +/* 360 */ MCD_OPC_CheckPredicate, 24, 45, 11, 0, // Skip to: 3226 +/* 365 */ MCD_OPC_Decode, 239, 18, 55, // Opcode: MULU_MMR6 +/* 369 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 383 +/* 374 */ MCD_OPC_CheckPredicate, 24, 31, 11, 0, // Skip to: 3226 +/* 379 */ MCD_OPC_Decode, 201, 18, 55, // Opcode: MUHU_MMR6 +/* 383 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 397 +/* 388 */ MCD_OPC_CheckPredicate, 24, 17, 11, 0, // Skip to: 3226 +/* 393 */ MCD_OPC_Decode, 222, 11, 55, // Opcode: DIV_MMR6 +/* 397 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 411 +/* 402 */ MCD_OPC_CheckPredicate, 24, 3, 11, 0, // Skip to: 3226 +/* 407 */ MCD_OPC_Decode, 198, 17, 55, // Opcode: MOD_MMR6 +/* 411 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 425 +/* 416 */ MCD_OPC_CheckPredicate, 24, 245, 10, 0, // Skip to: 3226 +/* 421 */ MCD_OPC_Decode, 220, 11, 55, // Opcode: DIVU_MMR6 +/* 425 */ MCD_OPC_FilterValue, 7, 236, 10, 0, // Skip to: 3226 +/* 430 */ MCD_OPC_CheckPredicate, 24, 231, 10, 0, // Skip to: 3226 +/* 435 */ MCD_OPC_Decode, 196, 17, 55, // Opcode: MODU_MMR6 +/* 439 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 461 +/* 444 */ MCD_OPC_CheckPredicate, 24, 217, 10, 0, // Skip to: 3226 +/* 449 */ MCD_OPC_CheckField, 6, 3, 0, 210, 10, 0, // Skip to: 3226 +/* 456 */ MCD_OPC_Decode, 212, 6, 155, 1, // Opcode: ALIGN_MMR6 +/* 461 */ MCD_OPC_FilterValue, 44, 9, 0, 0, // Skip to: 475 +/* 466 */ MCD_OPC_CheckPredicate, 24, 195, 10, 0, // Skip to: 3226 +/* 471 */ MCD_OPC_Decode, 128, 13, 66, // Opcode: EXT_MMR6 +/* 475 */ MCD_OPC_FilterValue, 52, 45, 0, 0, // Skip to: 525 +/* 480 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 483 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 504 +/* 488 */ MCD_OPC_CheckPredicate, 24, 173, 10, 0, // Skip to: 3226 +/* 493 */ MCD_OPC_CheckField, 14, 2, 0, 166, 10, 0, // Skip to: 3226 +/* 500 */ MCD_OPC_Decode, 141, 17, 68, // Opcode: MFHC0_MMR6 +/* 504 */ MCD_OPC_FilterValue, 11, 157, 10, 0, // Skip to: 3226 +/* 509 */ MCD_OPC_CheckPredicate, 24, 152, 10, 0, // Skip to: 3226 +/* 514 */ MCD_OPC_CheckField, 14, 2, 0, 145, 10, 0, // Skip to: 3226 +/* 521 */ MCD_OPC_Decode, 170, 18, 69, // Opcode: MTHC0_MMR6 +/* 525 */ MCD_OPC_FilterValue, 60, 66, 2, 0, // Skip to: 1108 +/* 530 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 533 */ MCD_OPC_FilterValue, 0, 138, 0, 0, // Skip to: 676 +/* 538 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 541 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 555 +/* 546 */ MCD_OPC_CheckPredicate, 24, 115, 10, 0, // Skip to: 3226 +/* 551 */ MCD_OPC_Decode, 130, 17, 68, // Opcode: MFC0_MMR6 +/* 555 */ MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 605 +/* 560 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 563 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 584 +/* 568 */ MCD_OPC_CheckPredicate, 24, 93, 10, 0, // Skip to: 3226 +/* 573 */ MCD_OPC_CheckField, 21, 5, 0, 86, 10, 0, // Skip to: 3226 +/* 580 */ MCD_OPC_Decode, 203, 12, 92, // Opcode: DVP_MMR6 +/* 584 */ MCD_OPC_FilterValue, 7, 77, 10, 0, // Skip to: 3226 +/* 589 */ MCD_OPC_CheckPredicate, 24, 72, 10, 0, // Skip to: 3226 +/* 594 */ MCD_OPC_CheckField, 21, 5, 0, 65, 10, 0, // Skip to: 3226 +/* 601 */ MCD_OPC_Decode, 226, 12, 92, // Opcode: EVP_MMR6 +/* 605 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 619 +/* 610 */ MCD_OPC_CheckPredicate, 24, 51, 10, 0, // Skip to: 3226 +/* 615 */ MCD_OPC_Decode, 158, 18, 69, // Opcode: MTC0_MMR6 +/* 619 */ MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 640 +/* 624 */ MCD_OPC_CheckPredicate, 24, 37, 10, 0, // Skip to: 3226 +/* 629 */ MCD_OPC_CheckField, 11, 3, 1, 30, 10, 0, // Skip to: 3226 +/* 636 */ MCD_OPC_Decode, 133, 8, 86, // Opcode: BITSWAP_MMR6 +/* 640 */ MCD_OPC_FilterValue, 28, 21, 10, 0, // Skip to: 3226 +/* 645 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 648 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 662 +/* 653 */ MCD_OPC_CheckPredicate, 24, 8, 10, 0, // Skip to: 3226 +/* 658 */ MCD_OPC_Decode, 243, 14, 80, // Opcode: JALRC_MMR6 +/* 662 */ MCD_OPC_FilterValue, 3, 255, 9, 0, // Skip to: 3226 +/* 667 */ MCD_OPC_CheckPredicate, 24, 250, 9, 0, // Skip to: 3226 +/* 672 */ MCD_OPC_Decode, 242, 14, 80, // Opcode: JALRC_HB_MMR6 +/* 676 */ MCD_OPC_FilterValue, 1, 10, 1, 0, // Skip to: 947 +/* 681 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 684 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 734 +/* 689 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 692 */ MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 713 +/* 697 */ MCD_OPC_CheckPredicate, 24, 220, 9, 0, // Skip to: 3226 +/* 702 */ MCD_OPC_CheckField, 16, 10, 0, 213, 9, 0, // Skip to: 3226 +/* 709 */ MCD_OPC_Decode, 236, 23, 10, // Opcode: TLBINV_MMR6 +/* 713 */ MCD_OPC_FilterValue, 29, 204, 9, 0, // Skip to: 3226 +/* 718 */ MCD_OPC_CheckPredicate, 24, 199, 9, 0, // Skip to: 3226 +/* 723 */ MCD_OPC_CheckField, 21, 5, 0, 192, 9, 0, // Skip to: 3226 +/* 730 */ MCD_OPC_Decode, 233, 11, 92, // Opcode: DI_MMR6 +/* 734 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 770 +/* 739 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 742 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 756 +/* 747 */ MCD_OPC_CheckPredicate, 24, 170, 9, 0, // Skip to: 3226 +/* 752 */ MCD_OPC_Decode, 174, 9, 80, // Opcode: CLO_MMR6 +/* 756 */ MCD_OPC_FilterValue, 20, 161, 9, 0, // Skip to: 3226 +/* 761 */ MCD_OPC_CheckPredicate, 24, 156, 9, 0, // Skip to: 3226 +/* 766 */ MCD_OPC_Decode, 137, 17, 90, // Opcode: MFC2_MMR6 +/* 770 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 820 +/* 775 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 778 */ MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 799 +/* 783 */ MCD_OPC_CheckPredicate, 24, 134, 9, 0, // Skip to: 3226 +/* 788 */ MCD_OPC_CheckField, 16, 10, 0, 127, 9, 0, // Skip to: 3226 +/* 795 */ MCD_OPC_Decode, 234, 23, 10, // Opcode: TLBINVF_MMR6 +/* 799 */ MCD_OPC_FilterValue, 29, 118, 9, 0, // Skip to: 3226 +/* 804 */ MCD_OPC_CheckPredicate, 24, 113, 9, 0, // Skip to: 3226 +/* 809 */ MCD_OPC_CheckField, 21, 5, 0, 106, 9, 0, // Skip to: 3226 +/* 816 */ MCD_OPC_Decode, 212, 12, 92, // Opcode: EI_MMR6 +/* 820 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 841 +/* 825 */ MCD_OPC_CheckPredicate, 24, 92, 9, 0, // Skip to: 3226 +/* 830 */ MCD_OPC_CheckField, 6, 5, 20, 85, 9, 0, // Skip to: 3226 +/* 837 */ MCD_OPC_Decode, 166, 18, 91, // Opcode: MTC2_MMR6 +/* 841 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 869 +/* 846 */ MCD_OPC_CheckPredicate, 25, 71, 9, 0, // Skip to: 3226 +/* 851 */ MCD_OPC_CheckField, 21, 5, 0, 64, 9, 0, // Skip to: 3226 +/* 858 */ MCD_OPC_CheckField, 6, 5, 5, 57, 9, 0, // Skip to: 3226 +/* 865 */ MCD_OPC_Decode, 185, 14, 92, // Opcode: GINVI_MMR6 +/* 869 */ MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 897 +/* 874 */ MCD_OPC_CheckPredicate, 24, 43, 9, 0, // Skip to: 3226 +/* 879 */ MCD_OPC_CheckField, 21, 5, 0, 36, 9, 0, // Skip to: 3226 +/* 886 */ MCD_OPC_CheckField, 6, 5, 13, 29, 9, 0, // Skip to: 3226 +/* 893 */ MCD_OPC_Decode, 180, 23, 87, // Opcode: SYNC_MMR6 +/* 897 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 926 +/* 902 */ MCD_OPC_CheckPredicate, 25, 15, 9, 0, // Skip to: 3226 +/* 907 */ MCD_OPC_CheckField, 21, 5, 0, 8, 9, 0, // Skip to: 3226 +/* 914 */ MCD_OPC_CheckField, 6, 3, 5, 1, 9, 0, // Skip to: 3226 +/* 921 */ MCD_OPC_Decode, 188, 14, 156, 1, // Opcode: GINVT_MMR6 +/* 926 */ MCD_OPC_FilterValue, 7, 247, 8, 0, // Skip to: 3226 +/* 931 */ MCD_OPC_CheckPredicate, 24, 242, 8, 0, // Skip to: 3226 +/* 936 */ MCD_OPC_CheckField, 6, 5, 12, 235, 8, 0, // Skip to: 3226 +/* 943 */ MCD_OPC_Decode, 171, 24, 80, // Opcode: WSBH_MMR6 +/* 947 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 997 +/* 952 */ MCD_OPC_ExtractField, 6, 8, // Inst{13-6} ... +/* 955 */ MCD_OPC_FilterValue, 52, 9, 0, 0, // Skip to: 969 +/* 960 */ MCD_OPC_CheckPredicate, 24, 213, 8, 0, // Skip to: 3226 +/* 965 */ MCD_OPC_Decode, 147, 17, 90, // Opcode: MFHC2_MMR6 +/* 969 */ MCD_OPC_FilterValue, 77, 9, 0, 0, // Skip to: 983 +/* 974 */ MCD_OPC_CheckPredicate, 24, 199, 8, 0, // Skip to: 3226 +/* 979 */ MCD_OPC_Decode, 163, 24, 88, // Opcode: WAIT_MMR6 +/* 983 */ MCD_OPC_FilterValue, 116, 190, 8, 0, // Skip to: 3226 +/* 988 */ MCD_OPC_CheckPredicate, 24, 185, 8, 0, // Skip to: 3226 +/* 993 */ MCD_OPC_Decode, 176, 18, 91, // Opcode: MTHC2_MMR6 +/* 997 */ MCD_OPC_FilterValue, 3, 176, 8, 0, // Skip to: 3226 +/* 1002 */ MCD_OPC_ExtractField, 6, 8, // Inst{13-6} ... +/* 1005 */ MCD_OPC_FilterValue, 109, 9, 0, 0, // Skip to: 1019 +/* 1010 */ MCD_OPC_CheckPredicate, 24, 163, 8, 0, // Skip to: 3226 +/* 1015 */ MCD_OPC_Decode, 224, 20, 88, // Opcode: SDBBP_MMR6 +/* 1019 */ MCD_OPC_FilterValue, 133, 1, 9, 0, 0, // Skip to: 1034 +/* 1025 */ MCD_OPC_CheckPredicate, 24, 148, 8, 0, // Skip to: 3226 +/* 1030 */ MCD_OPC_Decode, 132, 20, 80, // Opcode: RDPGPR_MMR6 +/* 1034 */ MCD_OPC_FilterValue, 141, 1, 16, 0, 0, // Skip to: 1056 +/* 1040 */ MCD_OPC_CheckPredicate, 24, 133, 8, 0, // Skip to: 3226 +/* 1045 */ MCD_OPC_CheckField, 16, 10, 0, 126, 8, 0, // Skip to: 3226 +/* 1052 */ MCD_OPC_Decode, 208, 11, 10, // Opcode: DERET_MMR6 +/* 1056 */ MCD_OPC_FilterValue, 197, 1, 9, 0, 0, // Skip to: 1071 +/* 1062 */ MCD_OPC_CheckPredicate, 24, 111, 8, 0, // Skip to: 3226 +/* 1067 */ MCD_OPC_Decode, 167, 24, 80, // Opcode: WRPGPR_MMR6 +/* 1071 */ MCD_OPC_FilterValue, 205, 1, 101, 8, 0, // Skip to: 3226 +/* 1077 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 1080 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1094 +/* 1085 */ MCD_OPC_CheckPredicate, 24, 88, 8, 0, // Skip to: 3226 +/* 1090 */ MCD_OPC_Decode, 221, 12, 10, // Opcode: ERET_MMR6 +/* 1094 */ MCD_OPC_FilterValue, 1, 79, 8, 0, // Skip to: 3226 +/* 1099 */ MCD_OPC_CheckPredicate, 24, 74, 8, 0, // Skip to: 3226 +/* 1104 */ MCD_OPC_Decode, 218, 12, 10, // Opcode: ERETNC_MMR6 +/* 1108 */ MCD_OPC_FilterValue, 63, 65, 8, 0, // Skip to: 3226 +/* 1113 */ MCD_OPC_CheckPredicate, 24, 60, 8, 0, // Skip to: 3226 +/* 1118 */ MCD_OPC_CheckField, 22, 4, 0, 53, 8, 0, // Skip to: 3226 +/* 1125 */ MCD_OPC_Decode, 209, 21, 157, 1, // Opcode: SIGRIE_MMR6 +/* 1130 */ MCD_OPC_FilterValue, 4, 26, 0, 0, // Skip to: 1161 +/* 1135 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 1152 +/* 1140 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 1152 +/* 1147 */ MCD_OPC_Decode, 251, 15, 158, 1, // Opcode: LUI_MMR6 +/* 1152 */ MCD_OPC_CheckPredicate, 24, 21, 8, 0, // Skip to: 3226 +/* 1157 */ MCD_OPC_Decode, 247, 6, 108, // Opcode: AUI_MMR6 +/* 1161 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1176 +/* 1166 */ MCD_OPC_CheckPredicate, 24, 7, 8, 0, // Skip to: 3226 +/* 1171 */ MCD_OPC_Decode, 166, 15, 159, 1, // Opcode: LBU_MMR6 +/* 1176 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1190 +/* 1181 */ MCD_OPC_CheckPredicate, 24, 248, 7, 0, // Skip to: 3226 +/* 1186 */ MCD_OPC_Decode, 203, 20, 98, // Opcode: SB_MMR6 +/* 1190 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1205 +/* 1195 */ MCD_OPC_CheckPredicate, 24, 234, 7, 0, // Skip to: 3226 +/* 1200 */ MCD_OPC_Decode, 171, 15, 159, 1, // Opcode: LB_MMR6 +/* 1205 */ MCD_OPC_FilterValue, 8, 105, 0, 0, // Skip to: 1315 +/* 1210 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 1213 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1235 +/* 1218 */ MCD_OPC_CheckPredicate, 24, 211, 7, 0, // Skip to: 3226 +/* 1223 */ MCD_OPC_CheckField, 11, 1, 0, 204, 7, 0, // Skip to: 3226 +/* 1230 */ MCD_OPC_Decode, 139, 16, 160, 1, // Opcode: LWC2_MMR6 +/* 1235 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1257 +/* 1240 */ MCD_OPC_CheckPredicate, 24, 189, 7, 0, // Skip to: 3226 +/* 1245 */ MCD_OPC_CheckField, 11, 1, 0, 182, 7, 0, // Skip to: 3226 +/* 1252 */ MCD_OPC_Decode, 186, 15, 160, 1, // Opcode: LDC2_MMR6 +/* 1257 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1271 +/* 1262 */ MCD_OPC_CheckPredicate, 24, 167, 7, 0, // Skip to: 3226 +/* 1267 */ MCD_OPC_Decode, 250, 8, 100, // Opcode: CACHE_MMR6 +/* 1271 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 1293 +/* 1276 */ MCD_OPC_CheckPredicate, 24, 153, 7, 0, // Skip to: 3226 +/* 1281 */ MCD_OPC_CheckField, 11, 1, 0, 146, 7, 0, // Skip to: 3226 +/* 1288 */ MCD_OPC_Decode, 137, 23, 160, 1, // Opcode: SWC2_MMR6 +/* 1293 */ MCD_OPC_FilterValue, 10, 136, 7, 0, // Skip to: 3226 +/* 1298 */ MCD_OPC_CheckPredicate, 24, 131, 7, 0, // Skip to: 3226 +/* 1303 */ MCD_OPC_CheckField, 11, 1, 0, 124, 7, 0, // Skip to: 3226 +/* 1310 */ MCD_OPC_Decode, 233, 20, 160, 1, // Opcode: SDC2_MMR6 +/* 1315 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 1329 +/* 1320 */ MCD_OPC_CheckPredicate, 24, 109, 7, 0, // Skip to: 3226 +/* 1325 */ MCD_OPC_Decode, 139, 6, 97, // Opcode: ADDIU_MMR6 +/* 1329 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 1343 +/* 1334 */ MCD_OPC_CheckPredicate, 24, 95, 7, 0, // Skip to: 3226 +/* 1339 */ MCD_OPC_Decode, 205, 21, 98, // Opcode: SH_MMR6 +/* 1343 */ MCD_OPC_FilterValue, 16, 78, 0, 0, // Skip to: 1426 +/* 1348 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 1351 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1366 +/* 1356 */ MCD_OPC_CheckPredicate, 26, 73, 7, 0, // Skip to: 3226 +/* 1361 */ MCD_OPC_Decode, 165, 7, 161, 1, // Opcode: BC1EQZC_MMR6 +/* 1366 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1381 +/* 1371 */ MCD_OPC_CheckPredicate, 26, 58, 7, 0, // Skip to: 3226 +/* 1376 */ MCD_OPC_Decode, 170, 7, 161, 1, // Opcode: BC1NEZC_MMR6 +/* 1381 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1396 +/* 1386 */ MCD_OPC_CheckPredicate, 24, 43, 7, 0, // Skip to: 3226 +/* 1391 */ MCD_OPC_Decode, 175, 7, 162, 1, // Opcode: BC2EQZC_MMR6 +/* 1396 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1411 +/* 1401 */ MCD_OPC_CheckPredicate, 24, 28, 7, 0, // Skip to: 3226 +/* 1406 */ MCD_OPC_Decode, 177, 7, 162, 1, // Opcode: BC2NEZC_MMR6 +/* 1411 */ MCD_OPC_FilterValue, 12, 18, 7, 0, // Skip to: 3226 +/* 1416 */ MCD_OPC_CheckPredicate, 24, 13, 7, 0, // Skip to: 3226 +/* 1421 */ MCD_OPC_Decode, 176, 23, 163, 1, // Opcode: SYNCI_MMR6 +/* 1426 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 1440 +/* 1431 */ MCD_OPC_CheckPredicate, 24, 254, 6, 0, // Skip to: 3226 +/* 1436 */ MCD_OPC_Decode, 169, 19, 108, // Opcode: ORI_MMR6 +/* 1440 */ MCD_OPC_FilterValue, 21, 87, 5, 0, // Skip to: 2812 +/* 1445 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 1448 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1463 +/* 1453 */ MCD_OPC_CheckPredicate, 26, 232, 6, 0, // Skip to: 3226 +/* 1458 */ MCD_OPC_Decode, 186, 17, 164, 1, // Opcode: MIN_S_MMR6 +/* 1463 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1478 +/* 1468 */ MCD_OPC_CheckPredicate, 26, 217, 6, 0, // Skip to: 3226 +/* 1473 */ MCD_OPC_Decode, 217, 9, 165, 1, // Opcode: CMP_AF_S_MMR6 +/* 1478 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1493 +/* 1483 */ MCD_OPC_CheckPredicate, 26, 202, 6, 0, // Skip to: 3226 +/* 1488 */ MCD_OPC_Decode, 250, 16, 164, 1, // Opcode: MAX_S_MMR6 +/* 1493 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 1508 +/* 1498 */ MCD_OPC_CheckPredicate, 26, 187, 6, 0, // Skip to: 3226 +/* 1503 */ MCD_OPC_Decode, 216, 9, 166, 1, // Opcode: CMP_AF_D_MMR6 +/* 1508 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 1530 +/* 1513 */ MCD_OPC_CheckPredicate, 24, 172, 6, 0, // Skip to: 3226 +/* 1518 */ MCD_OPC_CheckField, 11, 5, 0, 165, 6, 0, // Skip to: 3226 +/* 1525 */ MCD_OPC_Decode, 154, 20, 167, 1, // Opcode: RINT_S_MMR6 +/* 1530 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 1545 +/* 1535 */ MCD_OPC_CheckPredicate, 26, 150, 6, 0, // Skip to: 3226 +/* 1540 */ MCD_OPC_Decode, 167, 17, 164, 1, // Opcode: MINA_S_MMR6 +/* 1545 */ MCD_OPC_FilterValue, 43, 10, 0, 0, // Skip to: 1560 +/* 1550 */ MCD_OPC_CheckPredicate, 26, 135, 6, 0, // Skip to: 3226 +/* 1555 */ MCD_OPC_Decode, 231, 16, 164, 1, // Opcode: MAXA_S_MMR6 +/* 1560 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 1575 +/* 1565 */ MCD_OPC_CheckPredicate, 26, 120, 6, 0, // Skip to: 3226 +/* 1570 */ MCD_OPC_Decode, 144, 13, 168, 1, // Opcode: FADD_S_MMR6 +/* 1575 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 1590 +/* 1580 */ MCD_OPC_CheckPredicate, 24, 105, 6, 0, // Skip to: 3226 +/* 1585 */ MCD_OPC_Decode, 128, 21, 164, 1, // Opcode: SELEQZ_S_MMR6 +/* 1590 */ MCD_OPC_FilterValue, 59, 31, 0, 0, // Skip to: 1626 +/* 1595 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 1598 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1612 +/* 1603 */ MCD_OPC_CheckPredicate, 26, 82, 6, 0, // Skip to: 3226 +/* 1608 */ MCD_OPC_Decode, 135, 17, 119, // Opcode: MFC1_MMR6 +/* 1612 */ MCD_OPC_FilterValue, 5, 73, 6, 0, // Skip to: 3226 +/* 1617 */ MCD_OPC_CheckPredicate, 26, 68, 6, 0, // Skip to: 3226 +/* 1622 */ MCD_OPC_Decode, 164, 18, 125, // Opcode: MTC1_MMR6 +/* 1626 */ MCD_OPC_FilterValue, 69, 10, 0, 0, // Skip to: 1641 +/* 1631 */ MCD_OPC_CheckPredicate, 26, 54, 6, 0, // Skip to: 3226 +/* 1636 */ MCD_OPC_Decode, 157, 10, 165, 1, // Opcode: CMP_UN_S_MMR6 +/* 1641 */ MCD_OPC_FilterValue, 85, 10, 0, 0, // Skip to: 1656 +/* 1646 */ MCD_OPC_CheckPredicate, 26, 39, 6, 0, // Skip to: 3226 +/* 1651 */ MCD_OPC_Decode, 155, 10, 166, 1, // Opcode: CMP_UN_D_MMR6 +/* 1656 */ MCD_OPC_FilterValue, 96, 17, 0, 0, // Skip to: 1678 +/* 1661 */ MCD_OPC_CheckPredicate, 24, 24, 6, 0, // Skip to: 3226 +/* 1666 */ MCD_OPC_CheckField, 11, 5, 0, 17, 6, 0, // Skip to: 3226 +/* 1673 */ MCD_OPC_Decode, 155, 9, 167, 1, // Opcode: CLASS_S_MMR6 +/* 1678 */ MCD_OPC_FilterValue, 112, 10, 0, 0, // Skip to: 1693 +/* 1683 */ MCD_OPC_CheckPredicate, 26, 2, 6, 0, // Skip to: 3226 +/* 1688 */ MCD_OPC_Decode, 162, 14, 168, 1, // Opcode: FSUB_S_MMR6 +/* 1693 */ MCD_OPC_FilterValue, 120, 10, 0, 0, // Skip to: 1708 +/* 1698 */ MCD_OPC_CheckPredicate, 24, 243, 5, 0, // Skip to: 3226 +/* 1703 */ MCD_OPC_Decode, 135, 21, 164, 1, // Opcode: SELNEZ_S_MMR6 +/* 1708 */ MCD_OPC_FilterValue, 123, 31, 0, 0, // Skip to: 1744 +/* 1713 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 1716 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1730 +/* 1721 */ MCD_OPC_CheckPredicate, 26, 220, 5, 0, // Skip to: 3226 +/* 1726 */ MCD_OPC_Decode, 234, 13, 124, // Opcode: FMOV_S_MMR6 +/* 1730 */ MCD_OPC_FilterValue, 4, 211, 5, 0, // Skip to: 3226 +/* 1735 */ MCD_OPC_CheckPredicate, 26, 206, 5, 0, // Skip to: 3226 +/* 1740 */ MCD_OPC_Decode, 231, 13, 122, // Opcode: FMOV_D_MMR6 +/* 1744 */ MCD_OPC_FilterValue, 133, 1, 10, 0, 0, // Skip to: 1760 +/* 1750 */ MCD_OPC_CheckPredicate, 26, 191, 5, 0, // Skip to: 3226 +/* 1755 */ MCD_OPC_Decode, 223, 9, 165, 1, // Opcode: CMP_EQ_S_MMR6 +/* 1760 */ MCD_OPC_FilterValue, 149, 1, 10, 0, 0, // Skip to: 1776 +/* 1766 */ MCD_OPC_CheckPredicate, 26, 175, 5, 0, // Skip to: 3226 +/* 1771 */ MCD_OPC_Decode, 219, 9, 166, 1, // Opcode: CMP_EQ_D_MMR6 +/* 1776 */ MCD_OPC_FilterValue, 176, 1, 10, 0, 0, // Skip to: 1792 +/* 1782 */ MCD_OPC_CheckPredicate, 26, 159, 5, 0, // Skip to: 3226 +/* 1787 */ MCD_OPC_Decode, 245, 13, 168, 1, // Opcode: FMUL_S_MMR6 +/* 1792 */ MCD_OPC_FilterValue, 184, 1, 10, 0, 0, // Skip to: 1808 +/* 1798 */ MCD_OPC_CheckPredicate, 24, 143, 5, 0, // Skip to: 3226 +/* 1803 */ MCD_OPC_Decode, 139, 21, 169, 1, // Opcode: SEL_S_MMR6 +/* 1808 */ MCD_OPC_FilterValue, 197, 1, 10, 0, 0, // Skip to: 1824 +/* 1814 */ MCD_OPC_CheckPredicate, 26, 127, 5, 0, // Skip to: 3226 +/* 1819 */ MCD_OPC_Decode, 145, 10, 165, 1, // Opcode: CMP_UEQ_S_MMR6 +/* 1824 */ MCD_OPC_FilterValue, 213, 1, 10, 0, 0, // Skip to: 1840 +/* 1830 */ MCD_OPC_CheckPredicate, 26, 111, 5, 0, // Skip to: 3226 +/* 1835 */ MCD_OPC_Decode, 143, 10, 166, 1, // Opcode: CMP_UEQ_D_MMR6 +/* 1840 */ MCD_OPC_FilterValue, 240, 1, 10, 0, 0, // Skip to: 1856 +/* 1846 */ MCD_OPC_CheckPredicate, 26, 95, 5, 0, // Skip to: 3226 +/* 1851 */ MCD_OPC_Decode, 182, 13, 168, 1, // Opcode: FDIV_S_MMR6 +/* 1856 */ MCD_OPC_FilterValue, 133, 2, 10, 0, 0, // Skip to: 1872 +/* 1862 */ MCD_OPC_CheckPredicate, 26, 79, 5, 0, // Skip to: 3226 +/* 1867 */ MCD_OPC_Decode, 237, 9, 165, 1, // Opcode: CMP_LT_S_MMR6 +/* 1872 */ MCD_OPC_FilterValue, 149, 2, 10, 0, 0, // Skip to: 1888 +/* 1878 */ MCD_OPC_CheckPredicate, 26, 63, 5, 0, // Skip to: 3226 +/* 1883 */ MCD_OPC_Decode, 233, 9, 166, 1, // Opcode: CMP_LT_D_MMR6 +/* 1888 */ MCD_OPC_FilterValue, 187, 2, 45, 0, 0, // Skip to: 1939 +/* 1894 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 1897 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1911 +/* 1902 */ MCD_OPC_CheckPredicate, 26, 39, 5, 0, // Skip to: 3226 +/* 1907 */ MCD_OPC_Decode, 198, 10, 121, // Opcode: CVT_L_S_MMR6 +/* 1911 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1925 +/* 1916 */ MCD_OPC_CheckPredicate, 26, 25, 5, 0, // Skip to: 3226 +/* 1921 */ MCD_OPC_Decode, 219, 10, 124, // Opcode: CVT_W_S_MMR6 +/* 1925 */ MCD_OPC_FilterValue, 8, 16, 5, 0, // Skip to: 3226 +/* 1930 */ MCD_OPC_CheckPredicate, 26, 11, 5, 0, // Skip to: 3226 +/* 1935 */ MCD_OPC_Decode, 195, 10, 122, // Opcode: CVT_L_D_MMR6 +/* 1939 */ MCD_OPC_FilterValue, 197, 2, 10, 0, 0, // Skip to: 1955 +/* 1945 */ MCD_OPC_CheckPredicate, 26, 252, 4, 0, // Skip to: 3226 +/* 1950 */ MCD_OPC_Decode, 153, 10, 165, 1, // Opcode: CMP_ULT_S_MMR6 +/* 1955 */ MCD_OPC_FilterValue, 213, 2, 10, 0, 0, // Skip to: 1971 +/* 1961 */ MCD_OPC_CheckPredicate, 26, 236, 4, 0, // Skip to: 3226 +/* 1966 */ MCD_OPC_Decode, 151, 10, 166, 1, // Opcode: CMP_ULT_D_MMR6 +/* 1971 */ MCD_OPC_FilterValue, 133, 3, 10, 0, 0, // Skip to: 1987 +/* 1977 */ MCD_OPC_CheckPredicate, 26, 220, 4, 0, // Skip to: 3226 +/* 1982 */ MCD_OPC_Decode, 231, 9, 165, 1, // Opcode: CMP_LE_S_MMR6 +/* 1987 */ MCD_OPC_FilterValue, 149, 3, 10, 0, 0, // Skip to: 2003 +/* 1993 */ MCD_OPC_CheckPredicate, 26, 204, 4, 0, // Skip to: 3226 +/* 1998 */ MCD_OPC_Decode, 227, 9, 166, 1, // Opcode: CMP_LE_D_MMR6 +/* 2003 */ MCD_OPC_FilterValue, 184, 3, 10, 0, 0, // Skip to: 2019 +/* 2009 */ MCD_OPC_CheckPredicate, 26, 188, 4, 0, // Skip to: 3226 +/* 2014 */ MCD_OPC_Decode, 199, 16, 170, 1, // Opcode: MADDF_S_MMR6 +/* 2019 */ MCD_OPC_FilterValue, 197, 3, 10, 0, 0, // Skip to: 2035 +/* 2025 */ MCD_OPC_CheckPredicate, 26, 172, 4, 0, // Skip to: 3226 +/* 2030 */ MCD_OPC_Decode, 149, 10, 165, 1, // Opcode: CMP_ULE_S_MMR6 +/* 2035 */ MCD_OPC_FilterValue, 213, 3, 10, 0, 0, // Skip to: 2051 +/* 2041 */ MCD_OPC_CheckPredicate, 26, 156, 4, 0, // Skip to: 3226 +/* 2046 */ MCD_OPC_Decode, 147, 10, 166, 1, // Opcode: CMP_ULE_D_MMR6 +/* 2051 */ MCD_OPC_FilterValue, 248, 3, 10, 0, 0, // Skip to: 2067 +/* 2057 */ MCD_OPC_CheckPredicate, 26, 140, 4, 0, // Skip to: 3226 +/* 2062 */ MCD_OPC_Decode, 135, 18, 170, 1, // Opcode: MSUBF_S_MMR6 +/* 2067 */ MCD_OPC_FilterValue, 131, 4, 10, 0, 0, // Skip to: 2083 +/* 2073 */ MCD_OPC_CheckPredicate, 26, 124, 4, 0, // Skip to: 3226 +/* 2078 */ MCD_OPC_Decode, 181, 17, 145, 1, // Opcode: MIN_D_MMR6 +/* 2083 */ MCD_OPC_FilterValue, 133, 4, 10, 0, 0, // Skip to: 2099 +/* 2089 */ MCD_OPC_CheckPredicate, 26, 108, 4, 0, // Skip to: 3226 +/* 2094 */ MCD_OPC_Decode, 241, 9, 165, 1, // Opcode: CMP_SAF_S_MMR6 +/* 2099 */ MCD_OPC_FilterValue, 139, 4, 10, 0, 0, // Skip to: 2115 +/* 2105 */ MCD_OPC_CheckPredicate, 26, 92, 4, 0, // Skip to: 3226 +/* 2110 */ MCD_OPC_Decode, 245, 16, 145, 1, // Opcode: MAX_D_MMR6 +/* 2115 */ MCD_OPC_FilterValue, 149, 4, 10, 0, 0, // Skip to: 2131 +/* 2121 */ MCD_OPC_CheckPredicate, 26, 76, 4, 0, // Skip to: 3226 +/* 2126 */ MCD_OPC_Decode, 239, 9, 166, 1, // Opcode: CMP_SAF_D_MMR6 +/* 2131 */ MCD_OPC_FilterValue, 160, 4, 17, 0, 0, // Skip to: 2154 +/* 2137 */ MCD_OPC_CheckPredicate, 24, 60, 4, 0, // Skip to: 3226 +/* 2142 */ MCD_OPC_CheckField, 11, 5, 0, 53, 4, 0, // Skip to: 3226 +/* 2149 */ MCD_OPC_Decode, 152, 20, 171, 1, // Opcode: RINT_D_MMR6 +/* 2154 */ MCD_OPC_FilterValue, 163, 4, 10, 0, 0, // Skip to: 2170 +/* 2160 */ MCD_OPC_CheckPredicate, 26, 37, 4, 0, // Skip to: 3226 +/* 2165 */ MCD_OPC_Decode, 165, 17, 145, 1, // Opcode: MINA_D_MMR6 +/* 2170 */ MCD_OPC_FilterValue, 171, 4, 10, 0, 0, // Skip to: 2186 +/* 2176 */ MCD_OPC_CheckPredicate, 26, 21, 4, 0, // Skip to: 3226 +/* 2181 */ MCD_OPC_Decode, 229, 16, 145, 1, // Opcode: MAXA_D_MMR6 +/* 2186 */ MCD_OPC_FilterValue, 184, 4, 10, 0, 0, // Skip to: 2202 +/* 2192 */ MCD_OPC_CheckPredicate, 24, 5, 4, 0, // Skip to: 3226 +/* 2197 */ MCD_OPC_Decode, 253, 20, 145, 1, // Opcode: SELEQZ_D_MMR6 +/* 2202 */ MCD_OPC_FilterValue, 197, 4, 10, 0, 0, // Skip to: 2218 +/* 2208 */ MCD_OPC_CheckPredicate, 26, 245, 3, 0, // Skip to: 3226 +/* 2213 */ MCD_OPC_Decode, 141, 10, 165, 1, // Opcode: CMP_SUN_S_MMR6 +/* 2218 */ MCD_OPC_FilterValue, 213, 4, 10, 0, 0, // Skip to: 2234 +/* 2224 */ MCD_OPC_CheckPredicate, 26, 229, 3, 0, // Skip to: 3226 +/* 2229 */ MCD_OPC_Decode, 139, 10, 166, 1, // Opcode: CMP_SUN_D_MMR6 +/* 2234 */ MCD_OPC_FilterValue, 224, 4, 17, 0, 0, // Skip to: 2257 +/* 2240 */ MCD_OPC_CheckPredicate, 24, 213, 3, 0, // Skip to: 3226 +/* 2245 */ MCD_OPC_CheckField, 11, 5, 0, 206, 3, 0, // Skip to: 3226 +/* 2252 */ MCD_OPC_Decode, 153, 9, 171, 1, // Opcode: CLASS_D_MMR6 +/* 2257 */ MCD_OPC_FilterValue, 248, 4, 10, 0, 0, // Skip to: 2273 +/* 2263 */ MCD_OPC_CheckPredicate, 24, 190, 3, 0, // Skip to: 3226 +/* 2268 */ MCD_OPC_Decode, 132, 21, 145, 1, // Opcode: SELNEZ_D_MMR6 +/* 2273 */ MCD_OPC_FilterValue, 133, 5, 10, 0, 0, // Skip to: 2289 +/* 2279 */ MCD_OPC_CheckPredicate, 26, 174, 3, 0, // Skip to: 3226 +/* 2284 */ MCD_OPC_Decode, 245, 9, 165, 1, // Opcode: CMP_SEQ_S_MMR6 +/* 2289 */ MCD_OPC_FilterValue, 149, 5, 10, 0, 0, // Skip to: 2305 +/* 2295 */ MCD_OPC_CheckPredicate, 26, 158, 3, 0, // Skip to: 3226 +/* 2300 */ MCD_OPC_Decode, 243, 9, 166, 1, // Opcode: CMP_SEQ_D_MMR6 +/* 2305 */ MCD_OPC_FilterValue, 184, 5, 10, 0, 0, // Skip to: 2321 +/* 2311 */ MCD_OPC_CheckPredicate, 24, 142, 3, 0, // Skip to: 3226 +/* 2316 */ MCD_OPC_Decode, 137, 21, 172, 1, // Opcode: SEL_D_MMR6 +/* 2321 */ MCD_OPC_FilterValue, 197, 5, 10, 0, 0, // Skip to: 2337 +/* 2327 */ MCD_OPC_CheckPredicate, 26, 126, 3, 0, // Skip to: 3226 +/* 2332 */ MCD_OPC_Decode, 129, 10, 165, 1, // Opcode: CMP_SUEQ_S_MMR6 +/* 2337 */ MCD_OPC_FilterValue, 213, 5, 10, 0, 0, // Skip to: 2353 +/* 2343 */ MCD_OPC_CheckPredicate, 26, 110, 3, 0, // Skip to: 3226 +/* 2348 */ MCD_OPC_Decode, 255, 9, 166, 1, // Opcode: CMP_SUEQ_D_MMR6 +/* 2353 */ MCD_OPC_FilterValue, 133, 6, 10, 0, 0, // Skip to: 2369 +/* 2359 */ MCD_OPC_CheckPredicate, 26, 94, 3, 0, // Skip to: 3226 +/* 2364 */ MCD_OPC_Decode, 253, 9, 165, 1, // Opcode: CMP_SLT_S_MMR6 +/* 2369 */ MCD_OPC_FilterValue, 149, 6, 10, 0, 0, // Skip to: 2385 +/* 2375 */ MCD_OPC_CheckPredicate, 26, 78, 3, 0, // Skip to: 3226 +/* 2380 */ MCD_OPC_Decode, 251, 9, 166, 1, // Opcode: CMP_SLT_D_MMR6 +/* 2385 */ MCD_OPC_FilterValue, 187, 6, 228, 0, 0, // Skip to: 2619 +/* 2391 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 2394 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2408 +/* 2399 */ MCD_OPC_CheckPredicate, 26, 54, 3, 0, // Skip to: 3226 +/* 2404 */ MCD_OPC_Decode, 209, 13, 121, // Opcode: FLOOR_L_S_MMR6 +/* 2408 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2422 +/* 2413 */ MCD_OPC_CheckPredicate, 26, 40, 3, 0, // Skip to: 3226 +/* 2418 */ MCD_OPC_Decode, 216, 13, 124, // Opcode: FLOOR_W_S_MMR6 +/* 2422 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2436 +/* 2427 */ MCD_OPC_CheckPredicate, 26, 26, 3, 0, // Skip to: 3226 +/* 2432 */ MCD_OPC_Decode, 128, 9, 121, // Opcode: CEIL_L_S_MMR6 +/* 2436 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2450 +/* 2441 */ MCD_OPC_CheckPredicate, 26, 12, 3, 0, // Skip to: 3226 +/* 2446 */ MCD_OPC_Decode, 135, 9, 124, // Opcode: CEIL_W_S_MMR6 +/* 2450 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2464 +/* 2455 */ MCD_OPC_CheckPredicate, 26, 254, 2, 0, // Skip to: 3226 +/* 2460 */ MCD_OPC_Decode, 137, 24, 121, // Opcode: TRUNC_L_S_MMR6 +/* 2464 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2478 +/* 2469 */ MCD_OPC_CheckPredicate, 26, 240, 2, 0, // Skip to: 3226 +/* 2474 */ MCD_OPC_Decode, 144, 24, 124, // Opcode: TRUNC_W_S_MMR6 +/* 2478 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2492 +/* 2483 */ MCD_OPC_CheckPredicate, 26, 226, 2, 0, // Skip to: 3226 +/* 2488 */ MCD_OPC_Decode, 165, 20, 121, // Opcode: ROUND_L_S_MMR6 +/* 2492 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 2506 +/* 2497 */ MCD_OPC_CheckPredicate, 26, 212, 2, 0, // Skip to: 3226 +/* 2502 */ MCD_OPC_Decode, 172, 20, 124, // Opcode: ROUND_W_S_MMR6 +/* 2506 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2520 +/* 2511 */ MCD_OPC_CheckPredicate, 26, 198, 2, 0, // Skip to: 3226 +/* 2516 */ MCD_OPC_Decode, 207, 13, 122, // Opcode: FLOOR_L_D_MMR6 +/* 2520 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2534 +/* 2525 */ MCD_OPC_CheckPredicate, 26, 184, 2, 0, // Skip to: 3226 +/* 2530 */ MCD_OPC_Decode, 212, 13, 126, // Opcode: FLOOR_W_D_MMR6 +/* 2534 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 2548 +/* 2539 */ MCD_OPC_CheckPredicate, 26, 170, 2, 0, // Skip to: 3226 +/* 2544 */ MCD_OPC_Decode, 254, 8, 122, // Opcode: CEIL_L_D_MMR6 +/* 2548 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 2562 +/* 2553 */ MCD_OPC_CheckPredicate, 26, 156, 2, 0, // Skip to: 3226 +/* 2558 */ MCD_OPC_Decode, 131, 9, 126, // Opcode: CEIL_W_D_MMR6 +/* 2562 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 2576 +/* 2567 */ MCD_OPC_CheckPredicate, 26, 142, 2, 0, // Skip to: 3226 +/* 2572 */ MCD_OPC_Decode, 135, 24, 122, // Opcode: TRUNC_L_D_MMR6 +/* 2576 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2591 +/* 2581 */ MCD_OPC_CheckPredicate, 26, 128, 2, 0, // Skip to: 3226 +/* 2586 */ MCD_OPC_Decode, 140, 24, 146, 1, // Opcode: TRUNC_W_D_MMR6 +/* 2591 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 2605 +/* 2596 */ MCD_OPC_CheckPredicate, 26, 113, 2, 0, // Skip to: 3226 +/* 2601 */ MCD_OPC_Decode, 163, 20, 122, // Opcode: ROUND_L_D_MMR6 +/* 2605 */ MCD_OPC_FilterValue, 15, 104, 2, 0, // Skip to: 3226 +/* 2610 */ MCD_OPC_CheckPredicate, 26, 99, 2, 0, // Skip to: 3226 +/* 2615 */ MCD_OPC_Decode, 168, 20, 122, // Opcode: ROUND_W_D_MMR6 +/* 2619 */ MCD_OPC_FilterValue, 197, 6, 10, 0, 0, // Skip to: 2635 +/* 2625 */ MCD_OPC_CheckPredicate, 26, 84, 2, 0, // Skip to: 3226 +/* 2630 */ MCD_OPC_Decode, 137, 10, 165, 1, // Opcode: CMP_SULT_S_MMR6 +/* 2635 */ MCD_OPC_FilterValue, 213, 6, 10, 0, 0, // Skip to: 2651 +/* 2641 */ MCD_OPC_CheckPredicate, 26, 68, 2, 0, // Skip to: 3226 +/* 2646 */ MCD_OPC_Decode, 135, 10, 166, 1, // Opcode: CMP_SULT_D_MMR6 +/* 2651 */ MCD_OPC_FilterValue, 251, 6, 59, 0, 0, // Skip to: 2716 +/* 2657 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 2660 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2674 +/* 2665 */ MCD_OPC_CheckPredicate, 26, 44, 2, 0, // Skip to: 3226 +/* 2670 */ MCD_OPC_Decode, 253, 13, 124, // Opcode: FNEG_S_MMR6 +/* 2674 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 2688 +/* 2679 */ MCD_OPC_CheckPredicate, 26, 30, 2, 0, // Skip to: 3226 +/* 2684 */ MCD_OPC_Decode, 212, 10, 124, // Opcode: CVT_S_W_MMR6 +/* 2688 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 2702 +/* 2693 */ MCD_OPC_CheckPredicate, 23, 16, 2, 0, // Skip to: 3226 +/* 2698 */ MCD_OPC_Decode, 192, 10, 122, // Opcode: CVT_D_L_MMR6 +/* 2702 */ MCD_OPC_FilterValue, 11, 7, 2, 0, // Skip to: 3226 +/* 2707 */ MCD_OPC_CheckPredicate, 23, 2, 2, 0, // Skip to: 3226 +/* 2712 */ MCD_OPC_Decode, 207, 10, 121, // Opcode: CVT_S_L_MMR6 +/* 2716 */ MCD_OPC_FilterValue, 133, 7, 10, 0, 0, // Skip to: 2732 +/* 2722 */ MCD_OPC_CheckPredicate, 26, 243, 1, 0, // Skip to: 3226 +/* 2727 */ MCD_OPC_Decode, 249, 9, 165, 1, // Opcode: CMP_SLE_S_MMR6 +/* 2732 */ MCD_OPC_FilterValue, 149, 7, 10, 0, 0, // Skip to: 2748 +/* 2738 */ MCD_OPC_CheckPredicate, 26, 227, 1, 0, // Skip to: 3226 +/* 2743 */ MCD_OPC_Decode, 247, 9, 166, 1, // Opcode: CMP_SLE_D_MMR6 +/* 2748 */ MCD_OPC_FilterValue, 184, 7, 10, 0, 0, // Skip to: 2764 +/* 2754 */ MCD_OPC_CheckPredicate, 26, 211, 1, 0, // Skip to: 3226 +/* 2759 */ MCD_OPC_Decode, 197, 16, 172, 1, // Opcode: MADDF_D_MMR6 +/* 2764 */ MCD_OPC_FilterValue, 197, 7, 10, 0, 0, // Skip to: 2780 +/* 2770 */ MCD_OPC_CheckPredicate, 26, 195, 1, 0, // Skip to: 3226 +/* 2775 */ MCD_OPC_Decode, 133, 10, 165, 1, // Opcode: CMP_SULE_S_MMR6 +/* 2780 */ MCD_OPC_FilterValue, 213, 7, 10, 0, 0, // Skip to: 2796 +/* 2786 */ MCD_OPC_CheckPredicate, 26, 179, 1, 0, // Skip to: 3226 +/* 2791 */ MCD_OPC_Decode, 131, 10, 166, 1, // Opcode: CMP_SULE_D_MMR6 +/* 2796 */ MCD_OPC_FilterValue, 248, 7, 168, 1, 0, // Skip to: 3226 +/* 2802 */ MCD_OPC_CheckPredicate, 26, 163, 1, 0, // Skip to: 3226 +/* 2807 */ MCD_OPC_Decode, 133, 18, 172, 1, // Opcode: MSUBF_D_MMR6 +/* 2812 */ MCD_OPC_FilterValue, 24, 61, 0, 0, // Skip to: 2878 +/* 2817 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 2820 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2834 +/* 2825 */ MCD_OPC_CheckPredicate, 24, 140, 1, 0, // Skip to: 3226 +/* 2830 */ MCD_OPC_Decode, 243, 19, 100, // Opcode: PREF_MMR6 +/* 2834 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 2856 +/* 2839 */ MCD_OPC_CheckPredicate, 24, 126, 1, 0, // Skip to: 3226 +/* 2844 */ MCD_OPC_CheckField, 9, 3, 0, 119, 1, 0, // Skip to: 3226 +/* 2851 */ MCD_OPC_Decode, 244, 15, 134, 1, // Opcode: LL_MMR6 +/* 2856 */ MCD_OPC_FilterValue, 11, 109, 1, 0, // Skip to: 3226 +/* 2861 */ MCD_OPC_CheckPredicate, 24, 104, 1, 0, // Skip to: 3226 +/* 2866 */ MCD_OPC_CheckField, 9, 3, 0, 97, 1, 0, // Skip to: 3226 +/* 2873 */ MCD_OPC_Decode, 215, 20, 134, 1, // Opcode: SC_MMR6 +/* 2878 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 2892 +/* 2883 */ MCD_OPC_CheckPredicate, 24, 82, 1, 0, // Skip to: 3226 +/* 2888 */ MCD_OPC_Decode, 178, 24, 108, // Opcode: XORI_MMR6 +/* 2892 */ MCD_OPC_FilterValue, 29, 27, 0, 0, // Skip to: 2924 +/* 2897 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 2914 +/* 2902 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 2914 +/* 2909 */ MCD_OPC_Decode, 200, 7, 173, 1, // Opcode: BEQZALC_MMR6 +/* 2914 */ MCD_OPC_CheckPredicate, 24, 51, 1, 0, // Skip to: 3226 +/* 2919 */ MCD_OPC_Decode, 193, 7, 173, 1, // Opcode: BEQC_MMR6 +/* 2924 */ MCD_OPC_FilterValue, 30, 71, 0, 0, // Skip to: 3000 +/* 2929 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... +/* 2932 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2947 +/* 2937 */ MCD_OPC_CheckPredicate, 24, 28, 1, 0, // Skip to: 3226 +/* 2942 */ MCD_OPC_Decode, 131, 6, 174, 1, // Opcode: ADDIUPC_MMR6 +/* 2947 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2962 +/* 2952 */ MCD_OPC_CheckPredicate, 24, 13, 1, 0, // Skip to: 3226 +/* 2957 */ MCD_OPC_Decode, 159, 16, 174, 1, // Opcode: LWPC_MMR6 +/* 2962 */ MCD_OPC_FilterValue, 3, 3, 1, 0, // Skip to: 3226 +/* 2967 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... +/* 2970 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 2985 +/* 2975 */ MCD_OPC_CheckPredicate, 24, 246, 0, 0, // Skip to: 3226 +/* 2980 */ MCD_OPC_Decode, 246, 6, 175, 1, // Opcode: AUIPC_MMR6 +/* 2985 */ MCD_OPC_FilterValue, 7, 236, 0, 0, // Skip to: 3226 +/* 2990 */ MCD_OPC_CheckPredicate, 24, 231, 0, 0, // Skip to: 3226 +/* 2995 */ MCD_OPC_Decode, 214, 6, 175, 1, // Opcode: ALUIPC_MMR6 +/* 3000 */ MCD_OPC_FilterValue, 31, 27, 0, 0, // Skip to: 3032 +/* 3005 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 3022 +/* 3010 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 3022 +/* 3017 */ MCD_OPC_Decode, 190, 8, 176, 1, // Opcode: BNEZALC_MMR6 +/* 3022 */ MCD_OPC_CheckPredicate, 24, 199, 0, 0, // Skip to: 3226 +/* 3027 */ MCD_OPC_Decode, 175, 8, 176, 1, // Opcode: BNEC_MMR6 +/* 3032 */ MCD_OPC_FilterValue, 32, 26, 0, 0, // Skip to: 3063 +/* 3037 */ MCD_OPC_CheckPredicate, 24, 11, 0, 0, // Skip to: 3053 +/* 3042 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 3053 +/* 3049 */ MCD_OPC_Decode, 128, 15, 103, // Opcode: JIALC_MMR6 +/* 3053 */ MCD_OPC_CheckPredicate, 24, 168, 0, 0, // Skip to: 3226 +/* 3058 */ MCD_OPC_Decode, 206, 7, 177, 1, // Opcode: BEQZC_MMR6 +/* 3063 */ MCD_OPC_FilterValue, 37, 10, 0, 0, // Skip to: 3078 +/* 3068 */ MCD_OPC_CheckPredicate, 24, 153, 0, 0, // Skip to: 3226 +/* 3073 */ MCD_OPC_Decode, 186, 7, 178, 1, // Opcode: BC_MMR6 +/* 3078 */ MCD_OPC_FilterValue, 40, 26, 0, 0, // Skip to: 3109 +/* 3083 */ MCD_OPC_CheckPredicate, 24, 11, 0, 0, // Skip to: 3099 +/* 3088 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 3099 +/* 3095 */ MCD_OPC_Decode, 131, 15, 103, // Opcode: JIC_MMR6 +/* 3099 */ MCD_OPC_CheckPredicate, 24, 122, 0, 0, // Skip to: 3226 +/* 3104 */ MCD_OPC_Decode, 196, 8, 177, 1, // Opcode: BNEZC_MMR6 +/* 3109 */ MCD_OPC_FilterValue, 45, 10, 0, 0, // Skip to: 3124 +/* 3114 */ MCD_OPC_CheckPredicate, 24, 107, 0, 0, // Skip to: 3226 +/* 3119 */ MCD_OPC_Decode, 150, 7, 178, 1, // Opcode: BALC_MMR6 +/* 3124 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 3139 +/* 3129 */ MCD_OPC_CheckPredicate, 24, 92, 0, 0, // Skip to: 3226 +/* 3134 */ MCD_OPC_Decode, 217, 7, 179, 1, // Opcode: BGEUC_MMR6 +/* 3139 */ MCD_OPC_FilterValue, 52, 9, 0, 0, // Skip to: 3153 +/* 3144 */ MCD_OPC_CheckPredicate, 24, 77, 0, 0, // Skip to: 3226 +/* 3149 */ MCD_OPC_Decode, 225, 6, 108, // Opcode: ANDI_MMR6 +/* 3153 */ MCD_OPC_FilterValue, 53, 10, 0, 0, // Skip to: 3168 +/* 3158 */ MCD_OPC_CheckPredicate, 24, 63, 0, 0, // Skip to: 3226 +/* 3163 */ MCD_OPC_Decode, 145, 8, 180, 1, // Opcode: BLTC_MMR6 +/* 3168 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 3183 +/* 3173 */ MCD_OPC_CheckPredicate, 24, 48, 0, 0, // Skip to: 3226 +/* 3178 */ MCD_OPC_Decode, 151, 8, 181, 1, // Opcode: BLTUC_MMR6 +/* 3183 */ MCD_OPC_FilterValue, 61, 10, 0, 0, // Skip to: 3198 +/* 3188 */ MCD_OPC_CheckPredicate, 24, 33, 0, 0, // Skip to: 3226 +/* 3193 */ MCD_OPC_Decode, 211, 7, 182, 1, // Opcode: BGEC_MMR6 +/* 3198 */ MCD_OPC_FilterValue, 62, 9, 0, 0, // Skip to: 3212 +/* 3203 */ MCD_OPC_CheckPredicate, 24, 18, 0, 0, // Skip to: 3226 +/* 3208 */ MCD_OPC_Decode, 170, 23, 98, // Opcode: SW_MMR6 +/* 3212 */ MCD_OPC_FilterValue, 63, 9, 0, 0, // Skip to: 3226 +/* 3217 */ MCD_OPC_CheckPredicate, 24, 4, 0, 0, // Skip to: 3226 +/* 3222 */ MCD_OPC_Decode, 180, 16, 98, // Opcode: LW_MMR6 +/* 3226 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMicroMipsR6_Ambiguous32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 18 +/* 8 */ MCD_OPC_CheckPredicate, 24, 84, 0, 0, // Skip to: 97 +/* 13 */ MCD_OPC_Decode, 207, 8, 173, 1, // Opcode: BOVC_MMR6 +/* 18 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 33 +/* 23 */ MCD_OPC_CheckPredicate, 24, 69, 0, 0, // Skip to: 97 +/* 28 */ MCD_OPC_Decode, 200, 8, 176, 1, // Opcode: BNVC_MMR6 +/* 33 */ MCD_OPC_FilterValue, 48, 27, 0, 0, // Skip to: 65 +/* 38 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 55 +/* 43 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 55 +/* 50 */ MCD_OPC_Decode, 137, 8, 179, 1, // Opcode: BLEZALC_MMR6 +/* 55 */ MCD_OPC_CheckPredicate, 24, 37, 0, 0, // Skip to: 97 +/* 60 */ MCD_OPC_Decode, 223, 7, 179, 1, // Opcode: BGEZALC_MMR6 +/* 65 */ MCD_OPC_FilterValue, 56, 27, 0, 0, // Skip to: 97 +/* 70 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 87 +/* 75 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 87 +/* 82 */ MCD_OPC_Decode, 235, 7, 181, 1, // Opcode: BGTZALC_MMR6 +/* 87 */ MCD_OPC_CheckPredicate, 24, 5, 0, 0, // Skip to: 97 +/* 92 */ MCD_OPC_Decode, 157, 8, 181, 1, // Opcode: BLTZALC_MMR6 +/* 97 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMips32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 173, 3, // Skip to: 948 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 68 -/* 14 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 17 */ MCD_OPC_FilterValue, 0, 137, 53, // Skip to: 13726 -/* 21 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... -/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 -/* 28 */ MCD_OPC_CheckPredicate, 5, 28, 0, // Skip to: 60 -/* 32 */ MCD_OPC_Decode, 180, 12, 0, // Opcode: SSNOP -/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 -/* 40 */ MCD_OPC_CheckPredicate, 5, 16, 0, // Skip to: 60 -/* 44 */ MCD_OPC_Decode, 139, 5, 0, // Opcode: EHB -/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 -/* 52 */ MCD_OPC_CheckPredicate, 6, 4, 0, // Skip to: 60 -/* 56 */ MCD_OPC_Decode, 147, 10, 0, // Opcode: PAUSE -/* 60 */ MCD_OPC_CheckPredicate, 1, 94, 53, // Skip to: 13726 -/* 64 */ MCD_OPC_Decode, 225, 11, 58, // Opcode: SLL -/* 68 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 111 -/* 72 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 75 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 93 -/* 79 */ MCD_OPC_CheckPredicate, 7, 75, 53, // Skip to: 13726 -/* 83 */ MCD_OPC_CheckField, 6, 5, 0, 69, 53, // Skip to: 13726 -/* 89 */ MCD_OPC_Decode, 239, 8, 59, // Opcode: MOVF_I -/* 93 */ MCD_OPC_FilterValue, 1, 61, 53, // Skip to: 13726 -/* 97 */ MCD_OPC_CheckPredicate, 7, 57, 53, // Skip to: 13726 -/* 101 */ MCD_OPC_CheckField, 6, 5, 0, 51, 53, // Skip to: 13726 -/* 107 */ MCD_OPC_Decode, 131, 9, 59, // Opcode: MOVT_I -/* 111 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 142 -/* 115 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 -/* 122 */ MCD_OPC_CheckPredicate, 1, 32, 53, // Skip to: 13726 -/* 126 */ MCD_OPC_Decode, 159, 12, 58, // Opcode: SRL -/* 130 */ MCD_OPC_FilterValue, 1, 24, 53, // Skip to: 13726 -/* 134 */ MCD_OPC_CheckPredicate, 6, 20, 53, // Skip to: 13726 -/* 138 */ MCD_OPC_Decode, 247, 10, 58, // Opcode: ROTR -/* 142 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 160 -/* 146 */ MCD_OPC_CheckPredicate, 5, 8, 53, // Skip to: 13726 -/* 150 */ MCD_OPC_CheckField, 21, 5, 0, 2, 53, // Skip to: 13726 -/* 156 */ MCD_OPC_Decode, 139, 12, 58, // Opcode: SRA -/* 160 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 178 -/* 164 */ MCD_OPC_CheckPredicate, 5, 246, 52, // Skip to: 13726 -/* 168 */ MCD_OPC_CheckField, 6, 5, 0, 240, 52, // Skip to: 13726 -/* 174 */ MCD_OPC_Decode, 233, 11, 36, // Opcode: SLLV -/* 178 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 196 -/* 182 */ MCD_OPC_CheckPredicate, 8, 228, 52, // Skip to: 13726 -/* 186 */ MCD_OPC_CheckField, 8, 3, 0, 222, 52, // Skip to: 13726 -/* 192 */ MCD_OPC_Decode, 205, 7, 60, // Opcode: LSA -/* 196 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 227 -/* 200 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 215 -/* 207 */ MCD_OPC_CheckPredicate, 5, 203, 52, // Skip to: 13726 -/* 211 */ MCD_OPC_Decode, 173, 12, 36, // Opcode: SRLV -/* 215 */ MCD_OPC_FilterValue, 1, 195, 52, // Skip to: 13726 -/* 219 */ MCD_OPC_CheckPredicate, 6, 191, 52, // Skip to: 13726 -/* 223 */ MCD_OPC_Decode, 248, 10, 36, // Opcode: ROTRV -/* 227 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 245 -/* 231 */ MCD_OPC_CheckPredicate, 5, 179, 52, // Skip to: 13726 -/* 235 */ MCD_OPC_CheckField, 6, 5, 0, 173, 52, // Skip to: 13726 -/* 241 */ MCD_OPC_Decode, 152, 12, 36, // Opcode: SRAV -/* 245 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 276 -/* 249 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... -/* 252 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 264 -/* 256 */ MCD_OPC_CheckPredicate, 5, 154, 52, // Skip to: 13726 -/* 260 */ MCD_OPC_Decode, 136, 7, 61, // Opcode: JR -/* 264 */ MCD_OPC_FilterValue, 16, 146, 52, // Skip to: 13726 -/* 268 */ MCD_OPC_CheckPredicate, 9, 142, 52, // Skip to: 13726 -/* 272 */ MCD_OPC_Decode, 141, 7, 61, // Opcode: JR_HB -/* 276 */ MCD_OPC_FilterValue, 9, 39, 0, // Skip to: 319 -/* 280 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 283 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 301 -/* 287 */ MCD_OPC_CheckPredicate, 1, 123, 52, // Skip to: 13726 -/* 291 */ MCD_OPC_CheckField, 16, 5, 0, 117, 52, // Skip to: 13726 -/* 297 */ MCD_OPC_Decode, 249, 6, 62, // Opcode: JALR -/* 301 */ MCD_OPC_FilterValue, 16, 109, 52, // Skip to: 13726 -/* 305 */ MCD_OPC_CheckPredicate, 10, 105, 52, // Skip to: 13726 -/* 309 */ MCD_OPC_CheckField, 16, 5, 0, 99, 52, // Skip to: 13726 -/* 315 */ MCD_OPC_Decode, 128, 7, 62, // Opcode: JALR_HB -/* 319 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 337 -/* 323 */ MCD_OPC_CheckPredicate, 7, 87, 52, // Skip to: 13726 -/* 327 */ MCD_OPC_CheckField, 6, 5, 0, 81, 52, // Skip to: 13726 -/* 333 */ MCD_OPC_Decode, 143, 9, 63, // Opcode: MOVZ_I_I -/* 337 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 355 -/* 341 */ MCD_OPC_CheckPredicate, 7, 69, 52, // Skip to: 13726 -/* 345 */ MCD_OPC_CheckField, 6, 5, 0, 63, 52, // Skip to: 13726 -/* 351 */ MCD_OPC_Decode, 251, 8, 63, // Opcode: MOVN_I_I -/* 355 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 367 -/* 359 */ MCD_OPC_CheckPredicate, 5, 51, 52, // Skip to: 13726 -/* 363 */ MCD_OPC_Decode, 132, 13, 64, // Opcode: SYSCALL -/* 367 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 379 -/* 371 */ MCD_OPC_CheckPredicate, 5, 39, 52, // Skip to: 13726 -/* 375 */ MCD_OPC_Decode, 171, 2, 33, // Opcode: BREAK -/* 379 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 391 -/* 383 */ MCD_OPC_CheckPredicate, 10, 27, 52, // Skip to: 13726 -/* 387 */ MCD_OPC_Decode, 129, 13, 65, // Opcode: SYNC -/* 391 */ MCD_OPC_FilterValue, 16, 43, 0, // Skip to: 438 -/* 395 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 398 */ MCD_OPC_FilterValue, 0, 12, 52, // Skip to: 13726 -/* 402 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 405 */ MCD_OPC_FilterValue, 0, 5, 52, // Skip to: 13726 -/* 409 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 412 */ MCD_OPC_FilterValue, 0, 254, 51, // Skip to: 13726 -/* 416 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 430 -/* 420 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 430 -/* 426 */ MCD_OPC_Decode, 186, 8, 66, // Opcode: MFHI -/* 430 */ MCD_OPC_CheckPredicate, 12, 236, 51, // Skip to: 13726 -/* 434 */ MCD_OPC_Decode, 189, 8, 67, // Opcode: MFHI_DSP -/* 438 */ MCD_OPC_FilterValue, 17, 36, 0, // Skip to: 478 -/* 442 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 445 */ MCD_OPC_FilterValue, 0, 221, 51, // Skip to: 13726 -/* 449 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... -/* 452 */ MCD_OPC_FilterValue, 0, 214, 51, // Skip to: 13726 -/* 456 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 470 -/* 460 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 470 -/* 466 */ MCD_OPC_Decode, 176, 9, 61, // Opcode: MTHI -/* 470 */ MCD_OPC_CheckPredicate, 12, 196, 51, // Skip to: 13726 -/* 474 */ MCD_OPC_Decode, 178, 9, 68, // Opcode: MTHI_DSP -/* 478 */ MCD_OPC_FilterValue, 18, 43, 0, // Skip to: 525 -/* 482 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 485 */ MCD_OPC_FilterValue, 0, 181, 51, // Skip to: 13726 -/* 489 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 492 */ MCD_OPC_FilterValue, 0, 174, 51, // Skip to: 13726 -/* 496 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 499 */ MCD_OPC_FilterValue, 0, 167, 51, // Skip to: 13726 -/* 503 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 517 -/* 507 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 517 -/* 513 */ MCD_OPC_Decode, 191, 8, 66, // Opcode: MFLO -/* 517 */ MCD_OPC_CheckPredicate, 12, 149, 51, // Skip to: 13726 -/* 521 */ MCD_OPC_Decode, 194, 8, 67, // Opcode: MFLO_DSP -/* 525 */ MCD_OPC_FilterValue, 19, 36, 0, // Skip to: 565 -/* 529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 532 */ MCD_OPC_FilterValue, 0, 134, 51, // Skip to: 13726 +/* 3 */ MCD_OPC_FilterValue, 0, 101, 4, 0, // Skip to: 1133 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 79 +/* 16 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 19 */ MCD_OPC_FilterValue, 0, 178, 66, 0, // Skip to: 17098 +/* 24 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... +/* 27 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 41 +/* 32 */ MCD_OPC_CheckPredicate, 27, 32, 0, 0, // Skip to: 69 +/* 37 */ MCD_OPC_Decode, 185, 22, 10, // Opcode: SSNOP +/* 41 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 55 +/* 46 */ MCD_OPC_CheckPredicate, 27, 18, 0, 0, // Skip to: 69 +/* 51 */ MCD_OPC_Decode, 206, 12, 10, // Opcode: EHB +/* 55 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 69 +/* 60 */ MCD_OPC_CheckPredicate, 28, 4, 0, 0, // Skip to: 69 +/* 65 */ MCD_OPC_Decode, 181, 19, 10, // Opcode: PAUSE +/* 69 */ MCD_OPC_CheckPredicate, 27, 128, 66, 0, // Skip to: 17098 +/* 74 */ MCD_OPC_Decode, 219, 21, 183, 1, // Opcode: SLL +/* 79 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 131 +/* 84 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 87 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 109 +/* 92 */ MCD_OPC_CheckPredicate, 29, 105, 66, 0, // Skip to: 17098 +/* 97 */ MCD_OPC_CheckField, 6, 5, 0, 98, 66, 0, // Skip to: 17098 +/* 104 */ MCD_OPC_Decode, 220, 17, 184, 1, // Opcode: MOVF_I +/* 109 */ MCD_OPC_FilterValue, 1, 88, 66, 0, // Skip to: 17098 +/* 114 */ MCD_OPC_CheckPredicate, 29, 83, 66, 0, // Skip to: 17098 +/* 119 */ MCD_OPC_CheckField, 6, 5, 0, 76, 66, 0, // Skip to: 17098 +/* 126 */ MCD_OPC_Decode, 241, 17, 184, 1, // Opcode: MOVT_I +/* 131 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 169 +/* 136 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 139 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 154 +/* 144 */ MCD_OPC_CheckPredicate, 27, 53, 66, 0, // Skip to: 17098 +/* 149 */ MCD_OPC_Decode, 160, 22, 183, 1, // Opcode: SRL +/* 154 */ MCD_OPC_FilterValue, 1, 43, 66, 0, // Skip to: 17098 +/* 159 */ MCD_OPC_CheckPredicate, 28, 38, 66, 0, // Skip to: 17098 +/* 164 */ MCD_OPC_Decode, 155, 20, 183, 1, // Opcode: ROTR +/* 169 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 191 +/* 174 */ MCD_OPC_CheckPredicate, 27, 23, 66, 0, // Skip to: 17098 +/* 179 */ MCD_OPC_CheckField, 21, 5, 0, 16, 66, 0, // Skip to: 17098 +/* 186 */ MCD_OPC_Decode, 138, 22, 183, 1, // Opcode: SRA +/* 191 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 212 +/* 196 */ MCD_OPC_CheckPredicate, 27, 1, 66, 0, // Skip to: 17098 +/* 201 */ MCD_OPC_CheckField, 6, 5, 0, 250, 65, 0, // Skip to: 17098 +/* 208 */ MCD_OPC_Decode, 229, 21, 55, // Opcode: SLLV +/* 212 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 234 +/* 217 */ MCD_OPC_CheckPredicate, 30, 236, 65, 0, // Skip to: 17098 +/* 222 */ MCD_OPC_CheckField, 8, 3, 0, 229, 65, 0, // Skip to: 17098 +/* 229 */ MCD_OPC_Decode, 247, 15, 185, 1, // Opcode: LSA +/* 234 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 270 +/* 239 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 242 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 256 +/* 247 */ MCD_OPC_CheckPredicate, 27, 206, 65, 0, // Skip to: 17098 +/* 252 */ MCD_OPC_Decode, 176, 22, 55, // Opcode: SRLV +/* 256 */ MCD_OPC_FilterValue, 1, 197, 65, 0, // Skip to: 17098 +/* 261 */ MCD_OPC_CheckPredicate, 28, 192, 65, 0, // Skip to: 17098 +/* 266 */ MCD_OPC_Decode, 156, 20, 55, // Opcode: ROTRV +/* 270 */ MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 291 +/* 275 */ MCD_OPC_CheckPredicate, 27, 178, 65, 0, // Skip to: 17098 +/* 280 */ MCD_OPC_CheckField, 6, 5, 0, 171, 65, 0, // Skip to: 17098 +/* 287 */ MCD_OPC_Decode, 151, 22, 55, // Opcode: SRAV +/* 291 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 329 +/* 296 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... +/* 299 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 314 +/* 304 */ MCD_OPC_CheckPredicate, 31, 149, 65, 0, // Skip to: 17098 +/* 309 */ MCD_OPC_Decode, 132, 15, 186, 1, // Opcode: JR +/* 314 */ MCD_OPC_FilterValue, 16, 139, 65, 0, // Skip to: 17098 +/* 319 */ MCD_OPC_CheckPredicate, 32, 134, 65, 0, // Skip to: 17098 +/* 324 */ MCD_OPC_Decode, 140, 15, 186, 1, // Opcode: JR_HB +/* 329 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 379 +/* 334 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 337 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 358 +/* 342 */ MCD_OPC_CheckPredicate, 33, 111, 65, 0, // Skip to: 17098 +/* 347 */ MCD_OPC_CheckField, 16, 5, 0, 104, 65, 0, // Skip to: 17098 +/* 354 */ MCD_OPC_Decode, 236, 14, 25, // Opcode: JALR +/* 358 */ MCD_OPC_FilterValue, 16, 95, 65, 0, // Skip to: 17098 +/* 363 */ MCD_OPC_CheckPredicate, 34, 90, 65, 0, // Skip to: 17098 +/* 368 */ MCD_OPC_CheckField, 16, 5, 0, 83, 65, 0, // Skip to: 17098 +/* 375 */ MCD_OPC_Decode, 247, 14, 25, // Opcode: JALR_HB +/* 379 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 401 +/* 384 */ MCD_OPC_CheckPredicate, 35, 69, 65, 0, // Skip to: 17098 +/* 389 */ MCD_OPC_CheckField, 6, 5, 0, 62, 65, 0, // Skip to: 17098 +/* 396 */ MCD_OPC_Decode, 253, 17, 187, 1, // Opcode: MOVZ_I_I +/* 401 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 423 +/* 406 */ MCD_OPC_CheckPredicate, 35, 47, 65, 0, // Skip to: 17098 +/* 411 */ MCD_OPC_CheckField, 6, 5, 0, 40, 65, 0, // Skip to: 17098 +/* 418 */ MCD_OPC_Decode, 232, 17, 187, 1, // Opcode: MOVN_I_I +/* 423 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 438 +/* 428 */ MCD_OPC_CheckPredicate, 27, 25, 65, 0, // Skip to: 17098 +/* 433 */ MCD_OPC_Decode, 182, 23, 188, 1, // Opcode: SYSCALL +/* 438 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 452 +/* 443 */ MCD_OPC_CheckPredicate, 27, 10, 65, 0, // Skip to: 17098 +/* 448 */ MCD_OPC_Decode, 211, 8, 56, // Opcode: BREAK +/* 452 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 467 +/* 457 */ MCD_OPC_CheckPredicate, 36, 252, 64, 0, // Skip to: 17098 +/* 462 */ MCD_OPC_Decode, 173, 23, 189, 1, // Opcode: SYNC +/* 467 */ MCD_OPC_FilterValue, 16, 51, 0, 0, // Skip to: 523 +/* 472 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 475 */ MCD_OPC_FilterValue, 0, 234, 64, 0, // Skip to: 17098 +/* 480 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 483 */ MCD_OPC_FilterValue, 0, 226, 64, 0, // Skip to: 17098 +/* 488 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 491 */ MCD_OPC_FilterValue, 0, 218, 64, 0, // Skip to: 17098 +/* 496 */ MCD_OPC_CheckPredicate, 31, 12, 0, 0, // Skip to: 513 +/* 501 */ MCD_OPC_CheckField, 21, 2, 0, 5, 0, 0, // Skip to: 513 +/* 508 */ MCD_OPC_Decode, 150, 17, 190, 1, // Opcode: MFHI +/* 513 */ MCD_OPC_CheckPredicate, 37, 196, 64, 0, // Skip to: 17098 +/* 518 */ MCD_OPC_Decode, 153, 17, 191, 1, // Opcode: MFHI_DSP +/* 523 */ MCD_OPC_FilterValue, 17, 43, 0, 0, // Skip to: 571 +/* 528 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 531 */ MCD_OPC_FilterValue, 0, 178, 64, 0, // Skip to: 17098 /* 536 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... -/* 539 */ MCD_OPC_FilterValue, 0, 127, 51, // Skip to: 13726 -/* 543 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 557 -/* 547 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 557 -/* 553 */ MCD_OPC_Decode, 181, 9, 61, // Opcode: MTLO -/* 557 */ MCD_OPC_CheckPredicate, 12, 109, 51, // Skip to: 13726 -/* 561 */ MCD_OPC_Decode, 183, 9, 69, // Opcode: MTLO_DSP -/* 565 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 583 -/* 569 */ MCD_OPC_CheckPredicate, 14, 97, 51, // Skip to: 13726 -/* 573 */ MCD_OPC_CheckField, 8, 3, 0, 91, 51, // Skip to: 13726 -/* 579 */ MCD_OPC_Decode, 194, 4, 70, // Opcode: DLSA -/* 583 */ MCD_OPC_FilterValue, 24, 36, 0, // Skip to: 623 -/* 587 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 590 */ MCD_OPC_FilterValue, 0, 76, 51, // Skip to: 13726 -/* 594 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 597 */ MCD_OPC_FilterValue, 0, 69, 51, // Skip to: 13726 -/* 601 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 615 -/* 605 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 615 -/* 611 */ MCD_OPC_Decode, 206, 9, 43, // Opcode: MULT -/* 615 */ MCD_OPC_CheckPredicate, 12, 51, 51, // Skip to: 13726 -/* 619 */ MCD_OPC_Decode, 208, 9, 71, // Opcode: MULT_DSP -/* 623 */ MCD_OPC_FilterValue, 25, 36, 0, // Skip to: 663 -/* 627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 630 */ MCD_OPC_FilterValue, 0, 36, 51, // Skip to: 13726 -/* 634 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 637 */ MCD_OPC_FilterValue, 0, 29, 51, // Skip to: 13726 -/* 641 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 655 -/* 645 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 655 -/* 651 */ MCD_OPC_Decode, 210, 9, 43, // Opcode: MULTu -/* 655 */ MCD_OPC_CheckPredicate, 12, 11, 51, // Skip to: 13726 -/* 659 */ MCD_OPC_Decode, 207, 9, 71, // Opcode: MULTU_DSP -/* 663 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 681 -/* 667 */ MCD_OPC_CheckPredicate, 13, 255, 50, // Skip to: 13726 -/* 671 */ MCD_OPC_CheckField, 6, 10, 0, 249, 50, // Skip to: 13726 -/* 677 */ MCD_OPC_Decode, 162, 11, 43, // Opcode: SDIV -/* 681 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 699 -/* 685 */ MCD_OPC_CheckPredicate, 13, 237, 50, // Skip to: 13726 -/* 689 */ MCD_OPC_CheckField, 6, 10, 0, 231, 50, // Skip to: 13726 -/* 695 */ MCD_OPC_Decode, 222, 13, 43, // Opcode: UDIV -/* 699 */ MCD_OPC_FilterValue, 32, 13, 0, // Skip to: 716 -/* 703 */ MCD_OPC_CheckPredicate, 5, 219, 50, // Skip to: 13726 -/* 707 */ MCD_OPC_CheckField, 6, 5, 0, 213, 50, // Skip to: 13726 -/* 713 */ MCD_OPC_Decode, 25, 35, // Opcode: ADD -/* 716 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 733 -/* 720 */ MCD_OPC_CheckPredicate, 5, 202, 50, // Skip to: 13726 -/* 724 */ MCD_OPC_CheckField, 6, 5, 0, 196, 50, // Skip to: 13726 -/* 730 */ MCD_OPC_Decode, 77, 35, // Opcode: ADDu -/* 733 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 751 -/* 737 */ MCD_OPC_CheckPredicate, 5, 185, 50, // Skip to: 13726 -/* 741 */ MCD_OPC_CheckField, 6, 5, 0, 179, 50, // Skip to: 13726 -/* 747 */ MCD_OPC_Decode, 190, 12, 35, // Opcode: SUB -/* 751 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 769 -/* 755 */ MCD_OPC_CheckPredicate, 5, 167, 50, // Skip to: 13726 -/* 759 */ MCD_OPC_CheckField, 6, 5, 0, 161, 50, // Skip to: 13726 -/* 765 */ MCD_OPC_Decode, 230, 12, 35, // Opcode: SUBu -/* 769 */ MCD_OPC_FilterValue, 36, 13, 0, // Skip to: 786 -/* 773 */ MCD_OPC_CheckPredicate, 1, 149, 50, // Skip to: 13726 -/* 777 */ MCD_OPC_CheckField, 6, 5, 0, 143, 50, // Skip to: 13726 -/* 783 */ MCD_OPC_Decode, 83, 35, // Opcode: AND -/* 786 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 804 -/* 790 */ MCD_OPC_CheckPredicate, 1, 132, 50, // Skip to: 13726 -/* 794 */ MCD_OPC_CheckField, 6, 5, 0, 126, 50, // Skip to: 13726 -/* 800 */ MCD_OPC_Decode, 133, 10, 35, // Opcode: OR -/* 804 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 822 -/* 808 */ MCD_OPC_CheckPredicate, 1, 114, 50, // Skip to: 13726 -/* 812 */ MCD_OPC_CheckField, 6, 5, 0, 108, 50, // Skip to: 13726 -/* 818 */ MCD_OPC_Decode, 236, 13, 35, // Opcode: XOR -/* 822 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 840 -/* 826 */ MCD_OPC_CheckPredicate, 5, 96, 50, // Skip to: 13726 -/* 830 */ MCD_OPC_CheckField, 6, 5, 0, 90, 50, // Skip to: 13726 -/* 836 */ MCD_OPC_Decode, 250, 9, 35, // Opcode: NOR -/* 840 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 858 -/* 844 */ MCD_OPC_CheckPredicate, 5, 78, 50, // Skip to: 13726 -/* 848 */ MCD_OPC_CheckField, 6, 5, 0, 72, 50, // Skip to: 13726 -/* 854 */ MCD_OPC_Decode, 240, 11, 35, // Opcode: SLT -/* 858 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 876 -/* 862 */ MCD_OPC_CheckPredicate, 5, 60, 50, // Skip to: 13726 -/* 866 */ MCD_OPC_CheckField, 6, 5, 0, 54, 50, // Skip to: 13726 -/* 872 */ MCD_OPC_Decode, 249, 11, 35, // Opcode: SLTu -/* 876 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 888 -/* 880 */ MCD_OPC_CheckPredicate, 15, 42, 50, // Skip to: 13726 -/* 884 */ MCD_OPC_Decode, 186, 13, 72, // Opcode: TGE -/* 888 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 900 -/* 892 */ MCD_OPC_CheckPredicate, 15, 30, 50, // Skip to: 13726 -/* 896 */ MCD_OPC_Decode, 191, 13, 72, // Opcode: TGEU -/* 900 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 912 -/* 904 */ MCD_OPC_CheckPredicate, 15, 18, 50, // Skip to: 13726 -/* 908 */ MCD_OPC_Decode, 202, 13, 72, // Opcode: TLT -/* 912 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 924 -/* 916 */ MCD_OPC_CheckPredicate, 15, 6, 50, // Skip to: 13726 -/* 920 */ MCD_OPC_Decode, 206, 13, 72, // Opcode: TLTU -/* 924 */ MCD_OPC_FilterValue, 52, 8, 0, // Skip to: 936 -/* 928 */ MCD_OPC_CheckPredicate, 15, 250, 49, // Skip to: 13726 -/* 932 */ MCD_OPC_Decode, 182, 13, 72, // Opcode: TEQ -/* 936 */ MCD_OPC_FilterValue, 54, 242, 49, // Skip to: 13726 -/* 940 */ MCD_OPC_CheckPredicate, 15, 238, 49, // Skip to: 13726 -/* 944 */ MCD_OPC_Decode, 209, 13, 72, // Opcode: TNE -/* 948 */ MCD_OPC_FilterValue, 1, 201, 0, // Skip to: 1153 -/* 952 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 955 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 967 -/* 959 */ MCD_OPC_CheckPredicate, 5, 219, 49, // Skip to: 13726 -/* 963 */ MCD_OPC_Decode, 131, 2, 73, // Opcode: BLTZ -/* 967 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 979 -/* 971 */ MCD_OPC_CheckPredicate, 5, 207, 49, // Skip to: 13726 -/* 975 */ MCD_OPC_Decode, 217, 1, 73, // Opcode: BGEZ -/* 979 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 991 -/* 983 */ MCD_OPC_CheckPredicate, 16, 195, 49, // Skip to: 13726 -/* 987 */ MCD_OPC_Decode, 139, 2, 73, // Opcode: BLTZL -/* 991 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1003 -/* 995 */ MCD_OPC_CheckPredicate, 16, 183, 49, // Skip to: 13726 -/* 999 */ MCD_OPC_Decode, 225, 1, 73, // Opcode: BGEZL -/* 1003 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1015 -/* 1007 */ MCD_OPC_CheckPredicate, 16, 171, 49, // Skip to: 13726 -/* 1011 */ MCD_OPC_Decode, 187, 13, 74, // Opcode: TGEI -/* 1015 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1027 -/* 1019 */ MCD_OPC_CheckPredicate, 16, 159, 49, // Skip to: 13726 -/* 1023 */ MCD_OPC_Decode, 188, 13, 74, // Opcode: TGEIU -/* 1027 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1039 -/* 1031 */ MCD_OPC_CheckPredicate, 16, 147, 49, // Skip to: 13726 -/* 1035 */ MCD_OPC_Decode, 203, 13, 74, // Opcode: TLTI -/* 1039 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1051 -/* 1043 */ MCD_OPC_CheckPredicate, 16, 135, 49, // Skip to: 13726 -/* 1047 */ MCD_OPC_Decode, 221, 13, 74, // Opcode: TTLTIU -/* 1051 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1063 -/* 1055 */ MCD_OPC_CheckPredicate, 16, 123, 49, // Skip to: 13726 -/* 1059 */ MCD_OPC_Decode, 183, 13, 74, // Opcode: TEQI -/* 1063 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1075 -/* 1067 */ MCD_OPC_CheckPredicate, 16, 111, 49, // Skip to: 13726 -/* 1071 */ MCD_OPC_Decode, 210, 13, 74, // Opcode: TNEI -/* 1075 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1087 -/* 1079 */ MCD_OPC_CheckPredicate, 13, 99, 49, // Skip to: 13726 -/* 1083 */ MCD_OPC_Decode, 133, 2, 73, // Opcode: BLTZAL -/* 1087 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1099 -/* 1091 */ MCD_OPC_CheckPredicate, 13, 87, 49, // Skip to: 13726 -/* 1095 */ MCD_OPC_Decode, 219, 1, 73, // Opcode: BGEZAL -/* 1099 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1111 -/* 1103 */ MCD_OPC_CheckPredicate, 16, 75, 49, // Skip to: 13726 -/* 1107 */ MCD_OPC_Decode, 135, 2, 73, // Opcode: BLTZALL -/* 1111 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 1123 -/* 1115 */ MCD_OPC_CheckPredicate, 16, 63, 49, // Skip to: 13726 -/* 1119 */ MCD_OPC_Decode, 221, 1, 73, // Opcode: BGEZALL -/* 1123 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 1141 -/* 1127 */ MCD_OPC_CheckPredicate, 12, 51, 49, // Skip to: 13726 -/* 1131 */ MCD_OPC_CheckField, 21, 5, 0, 45, 49, // Skip to: 13726 -/* 1137 */ MCD_OPC_Decode, 169, 2, 75, // Opcode: BPOSGE32 -/* 1141 */ MCD_OPC_FilterValue, 31, 37, 49, // Skip to: 13726 -/* 1145 */ MCD_OPC_CheckPredicate, 6, 33, 49, // Skip to: 13726 -/* 1149 */ MCD_OPC_Decode, 130, 13, 76, // Opcode: SYNCI -/* 1153 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1165 -/* 1157 */ MCD_OPC_CheckPredicate, 10, 21, 49, // Skip to: 13726 -/* 1161 */ MCD_OPC_Decode, 247, 6, 77, // Opcode: J -/* 1165 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1177 -/* 1169 */ MCD_OPC_CheckPredicate, 5, 9, 49, // Skip to: 13726 -/* 1173 */ MCD_OPC_Decode, 248, 6, 77, // Opcode: JAL -/* 1177 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1189 -/* 1181 */ MCD_OPC_CheckPredicate, 5, 253, 48, // Skip to: 13726 -/* 1185 */ MCD_OPC_Decode, 206, 1, 78, // Opcode: BEQ -/* 1189 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1201 -/* 1193 */ MCD_OPC_CheckPredicate, 5, 241, 48, // Skip to: 13726 -/* 1197 */ MCD_OPC_Decode, 145, 2, 78, // Opcode: BNE -/* 1201 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1219 -/* 1205 */ MCD_OPC_CheckPredicate, 5, 229, 48, // Skip to: 13726 -/* 1209 */ MCD_OPC_CheckField, 16, 5, 0, 223, 48, // Skip to: 13726 -/* 1215 */ MCD_OPC_Decode, 251, 1, 73, // Opcode: BLEZ -/* 1219 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1237 -/* 1223 */ MCD_OPC_CheckPredicate, 5, 211, 48, // Skip to: 13726 -/* 1227 */ MCD_OPC_CheckField, 16, 5, 0, 205, 48, // Skip to: 13726 -/* 1233 */ MCD_OPC_Decode, 227, 1, 73, // Opcode: BGTZ -/* 1237 */ MCD_OPC_FilterValue, 8, 7, 0, // Skip to: 1248 -/* 1241 */ MCD_OPC_CheckPredicate, 13, 193, 48, // Skip to: 13726 -/* 1245 */ MCD_OPC_Decode, 73, 79, // Opcode: ADDi -/* 1248 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 1259 -/* 1252 */ MCD_OPC_CheckPredicate, 1, 182, 48, // Skip to: 13726 -/* 1256 */ MCD_OPC_Decode, 75, 79, // Opcode: ADDiu -/* 1259 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1271 -/* 1263 */ MCD_OPC_CheckPredicate, 5, 171, 48, // Skip to: 13726 -/* 1267 */ MCD_OPC_Decode, 243, 11, 79, // Opcode: SLTi -/* 1271 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1283 -/* 1275 */ MCD_OPC_CheckPredicate, 5, 159, 48, // Skip to: 13726 -/* 1279 */ MCD_OPC_Decode, 246, 11, 79, // Opcode: SLTiu -/* 1283 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1294 -/* 1287 */ MCD_OPC_CheckPredicate, 1, 147, 48, // Skip to: 13726 -/* 1291 */ MCD_OPC_Decode, 93, 80, // Opcode: ANDi -/* 1294 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1306 -/* 1298 */ MCD_OPC_CheckPredicate, 5, 136, 48, // Skip to: 13726 -/* 1302 */ MCD_OPC_Decode, 142, 10, 80, // Opcode: ORi -/* 1306 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1318 -/* 1310 */ MCD_OPC_CheckPredicate, 5, 124, 48, // Skip to: 13726 -/* 1314 */ MCD_OPC_Decode, 245, 13, 80, // Opcode: XORi -/* 1318 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1336 -/* 1322 */ MCD_OPC_CheckPredicate, 5, 112, 48, // Skip to: 13726 -/* 1326 */ MCD_OPC_CheckField, 21, 5, 0, 106, 48, // Skip to: 13726 -/* 1332 */ MCD_OPC_Decode, 210, 7, 52, // Opcode: LUi -/* 1336 */ MCD_OPC_FilterValue, 16, 220, 0, // Skip to: 1560 -/* 1340 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1343 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1361 -/* 1347 */ MCD_OPC_CheckPredicate, 10, 87, 48, // Skip to: 13726 -/* 1351 */ MCD_OPC_CheckField, 3, 8, 0, 81, 48, // Skip to: 13726 -/* 1357 */ MCD_OPC_Decode, 179, 8, 81, // Opcode: MFC0 -/* 1361 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1379 -/* 1365 */ MCD_OPC_CheckPredicate, 10, 69, 48, // Skip to: 13726 -/* 1369 */ MCD_OPC_CheckField, 3, 8, 0, 63, 48, // Skip to: 13726 -/* 1375 */ MCD_OPC_Decode, 169, 9, 81, // Opcode: MTC0 -/* 1379 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1434 -/* 1383 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1386 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1398 -/* 1390 */ MCD_OPC_CheckPredicate, 13, 44, 48, // Skip to: 13726 -/* 1394 */ MCD_OPC_Decode, 176, 1, 82, // Opcode: BC0F -/* 1398 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1410 -/* 1402 */ MCD_OPC_CheckPredicate, 13, 32, 48, // Skip to: 13726 -/* 1406 */ MCD_OPC_Decode, 178, 1, 82, // Opcode: BC0T -/* 1410 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1422 -/* 1414 */ MCD_OPC_CheckPredicate, 13, 20, 48, // Skip to: 13726 -/* 1418 */ MCD_OPC_Decode, 177, 1, 82, // Opcode: BC0FL -/* 1422 */ MCD_OPC_FilterValue, 3, 12, 48, // Skip to: 13726 -/* 1426 */ MCD_OPC_CheckPredicate, 13, 8, 48, // Skip to: 13726 -/* 1430 */ MCD_OPC_Decode, 179, 1, 82, // Opcode: BC0TL -/* 1434 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 1469 -/* 1438 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... -/* 1441 */ MCD_OPC_FilterValue, 128, 192, 1, 8, 0, // Skip to: 1455 -/* 1447 */ MCD_OPC_CheckPredicate, 6, 243, 47, // Skip to: 13726 -/* 1451 */ MCD_OPC_Decode, 179, 4, 42, // Opcode: DI -/* 1455 */ MCD_OPC_FilterValue, 160, 192, 1, 233, 47, // Skip to: 13726 -/* 1461 */ MCD_OPC_CheckPredicate, 6, 229, 47, // Skip to: 13726 -/* 1465 */ MCD_OPC_Decode, 141, 5, 42, // Opcode: EI -/* 1469 */ MCD_OPC_FilterValue, 16, 221, 47, // Skip to: 13726 -/* 1473 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... -/* 1476 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1488 -/* 1480 */ MCD_OPC_CheckPredicate, 5, 210, 47, // Skip to: 13726 -/* 1484 */ MCD_OPC_Decode, 196, 13, 0, // Opcode: TLBR -/* 1488 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1500 -/* 1492 */ MCD_OPC_CheckPredicate, 5, 198, 47, // Skip to: 13726 -/* 1496 */ MCD_OPC_Decode, 198, 13, 0, // Opcode: TLBWI -/* 1500 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1512 -/* 1504 */ MCD_OPC_CheckPredicate, 5, 186, 47, // Skip to: 13726 -/* 1508 */ MCD_OPC_Decode, 200, 13, 0, // Opcode: TLBWR -/* 1512 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1524 -/* 1516 */ MCD_OPC_CheckPredicate, 5, 174, 47, // Skip to: 13726 -/* 1520 */ MCD_OPC_Decode, 194, 13, 0, // Opcode: TLBP -/* 1524 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1536 -/* 1528 */ MCD_OPC_CheckPredicate, 17, 162, 47, // Skip to: 13726 -/* 1532 */ MCD_OPC_Decode, 143, 5, 0, // Opcode: ERET -/* 1536 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1548 -/* 1540 */ MCD_OPC_CheckPredicate, 10, 150, 47, // Skip to: 13726 -/* 1544 */ MCD_OPC_Decode, 174, 4, 0, // Opcode: DERET -/* 1548 */ MCD_OPC_FilterValue, 32, 142, 47, // Skip to: 13726 -/* 1552 */ MCD_OPC_CheckPredicate, 18, 138, 47, // Skip to: 13726 -/* 1556 */ MCD_OPC_Decode, 231, 13, 0, // Opcode: WAIT -/* 1560 */ MCD_OPC_FilterValue, 17, 21, 6, // Skip to: 3121 -/* 1564 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1567 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1585 -/* 1571 */ MCD_OPC_CheckPredicate, 5, 119, 47, // Skip to: 13726 -/* 1575 */ MCD_OPC_CheckField, 0, 11, 0, 113, 47, // Skip to: 13726 -/* 1581 */ MCD_OPC_Decode, 180, 8, 83, // Opcode: MFC1 -/* 1585 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 1603 -/* 1589 */ MCD_OPC_CheckPredicate, 19, 101, 47, // Skip to: 13726 -/* 1593 */ MCD_OPC_CheckField, 0, 11, 0, 95, 47, // Skip to: 13726 -/* 1599 */ MCD_OPC_Decode, 197, 4, 84, // Opcode: DMFC1 -/* 1603 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 1621 -/* 1607 */ MCD_OPC_CheckPredicate, 5, 83, 47, // Skip to: 13726 -/* 1611 */ MCD_OPC_CheckField, 0, 11, 0, 77, 47, // Skip to: 13726 -/* 1617 */ MCD_OPC_Decode, 238, 2, 85, // Opcode: CFC1 -/* 1621 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 1639 -/* 1625 */ MCD_OPC_CheckPredicate, 20, 65, 47, // Skip to: 13726 -/* 1629 */ MCD_OPC_CheckField, 0, 11, 0, 59, 47, // Skip to: 13726 -/* 1635 */ MCD_OPC_Decode, 183, 8, 86, // Opcode: MFHC1_D32 -/* 1639 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1657 -/* 1643 */ MCD_OPC_CheckPredicate, 5, 47, 47, // Skip to: 13726 -/* 1647 */ MCD_OPC_CheckField, 0, 11, 0, 41, 47, // Skip to: 13726 -/* 1653 */ MCD_OPC_Decode, 170, 9, 87, // Opcode: MTC1 -/* 1657 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1675 -/* 1661 */ MCD_OPC_CheckPredicate, 19, 29, 47, // Skip to: 13726 -/* 1665 */ MCD_OPC_CheckField, 0, 11, 0, 23, 47, // Skip to: 13726 -/* 1671 */ MCD_OPC_Decode, 202, 4, 88, // Opcode: DMTC1 -/* 1675 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1693 -/* 1679 */ MCD_OPC_CheckPredicate, 5, 11, 47, // Skip to: 13726 -/* 1683 */ MCD_OPC_CheckField, 0, 11, 0, 5, 47, // Skip to: 13726 -/* 1689 */ MCD_OPC_Decode, 210, 3, 89, // Opcode: CTC1 -/* 1693 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1711 -/* 1697 */ MCD_OPC_CheckPredicate, 20, 249, 46, // Skip to: 13726 -/* 1701 */ MCD_OPC_CheckField, 0, 11, 0, 243, 46, // Skip to: 13726 -/* 1707 */ MCD_OPC_Decode, 173, 9, 90, // Opcode: MTHC1_D32 -/* 1711 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1766 -/* 1715 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1718 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1730 -/* 1722 */ MCD_OPC_CheckPredicate, 13, 224, 46, // Skip to: 13726 -/* 1726 */ MCD_OPC_Decode, 181, 1, 91, // Opcode: BC1F -/* 1730 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1742 -/* 1734 */ MCD_OPC_CheckPredicate, 13, 212, 46, // Skip to: 13726 -/* 1738 */ MCD_OPC_Decode, 185, 1, 91, // Opcode: BC1T -/* 1742 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1754 -/* 1746 */ MCD_OPC_CheckPredicate, 16, 200, 46, // Skip to: 13726 -/* 1750 */ MCD_OPC_Decode, 182, 1, 91, // Opcode: BC1FL -/* 1754 */ MCD_OPC_FilterValue, 3, 192, 46, // Skip to: 13726 -/* 1758 */ MCD_OPC_CheckPredicate, 16, 188, 46, // Skip to: 13726 -/* 1762 */ MCD_OPC_Decode, 186, 1, 91, // Opcode: BC1TL -/* 1766 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1778 -/* 1770 */ MCD_OPC_CheckPredicate, 8, 176, 46, // Skip to: 13726 -/* 1774 */ MCD_OPC_Decode, 192, 2, 92, // Opcode: BZ_V -/* 1778 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1790 -/* 1782 */ MCD_OPC_CheckPredicate, 8, 164, 46, // Skip to: 13726 -/* 1786 */ MCD_OPC_Decode, 166, 2, 92, // Opcode: BNZ_V -/* 1790 */ MCD_OPC_FilterValue, 16, 80, 2, // Skip to: 2386 -/* 1794 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1797 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1809 -/* 1801 */ MCD_OPC_CheckPredicate, 5, 145, 46, // Skip to: 13726 -/* 1805 */ MCD_OPC_Decode, 174, 5, 93, // Opcode: FADD_S -/* 1809 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1821 -/* 1813 */ MCD_OPC_CheckPredicate, 5, 133, 46, // Skip to: 13726 -/* 1817 */ MCD_OPC_Decode, 176, 6, 93, // Opcode: FSUB_S -/* 1821 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1833 -/* 1825 */ MCD_OPC_CheckPredicate, 5, 121, 46, // Skip to: 13726 -/* 1829 */ MCD_OPC_Decode, 139, 6, 93, // Opcode: FMUL_S -/* 1833 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1845 -/* 1837 */ MCD_OPC_CheckPredicate, 5, 109, 46, // Skip to: 13726 -/* 1841 */ MCD_OPC_Decode, 210, 5, 93, // Opcode: FDIV_S -/* 1845 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1863 -/* 1849 */ MCD_OPC_CheckPredicate, 15, 97, 46, // Skip to: 13726 -/* 1853 */ MCD_OPC_CheckField, 16, 5, 0, 91, 46, // Skip to: 13726 -/* 1859 */ MCD_OPC_Decode, 169, 6, 94, // Opcode: FSQRT_S -/* 1863 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1881 -/* 1867 */ MCD_OPC_CheckPredicate, 5, 79, 46, // Skip to: 13726 -/* 1871 */ MCD_OPC_CheckField, 16, 5, 0, 73, 46, // Skip to: 13726 -/* 1877 */ MCD_OPC_Decode, 167, 5, 94, // Opcode: FABS_S -/* 1881 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1899 -/* 1885 */ MCD_OPC_CheckPredicate, 5, 61, 46, // Skip to: 13726 -/* 1889 */ MCD_OPC_CheckField, 16, 5, 0, 55, 46, // Skip to: 13726 -/* 1895 */ MCD_OPC_Decode, 131, 6, 94, // Opcode: FMOV_S -/* 1899 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1917 -/* 1903 */ MCD_OPC_CheckPredicate, 5, 43, 46, // Skip to: 13726 -/* 1907 */ MCD_OPC_CheckField, 16, 5, 0, 37, 46, // Skip to: 13726 -/* 1913 */ MCD_OPC_Decode, 145, 6, 94, // Opcode: FNEG_S -/* 1917 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 1935 -/* 1921 */ MCD_OPC_CheckPredicate, 15, 25, 46, // Skip to: 13726 -/* 1925 */ MCD_OPC_CheckField, 16, 5, 0, 19, 46, // Skip to: 13726 -/* 1931 */ MCD_OPC_Decode, 128, 11, 94, // Opcode: ROUND_W_S -/* 1935 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 1953 -/* 1939 */ MCD_OPC_CheckPredicate, 15, 7, 46, // Skip to: 13726 -/* 1943 */ MCD_OPC_CheckField, 16, 5, 0, 1, 46, // Skip to: 13726 -/* 1949 */ MCD_OPC_Decode, 219, 13, 94, // Opcode: TRUNC_W_S -/* 1953 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 1971 -/* 1957 */ MCD_OPC_CheckPredicate, 15, 245, 45, // Skip to: 13726 -/* 1961 */ MCD_OPC_CheckField, 16, 5, 0, 239, 45, // Skip to: 13726 -/* 1967 */ MCD_OPC_Decode, 228, 2, 94, // Opcode: CEIL_W_S -/* 1971 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1989 -/* 1975 */ MCD_OPC_CheckPredicate, 15, 227, 45, // Skip to: 13726 -/* 1979 */ MCD_OPC_CheckField, 16, 5, 0, 221, 45, // Skip to: 13726 -/* 1985 */ MCD_OPC_Decode, 244, 5, 94, // Opcode: FLOOR_W_S -/* 1989 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2020 -/* 1993 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1996 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2008 -/* 2000 */ MCD_OPC_CheckPredicate, 7, 202, 45, // Skip to: 13726 -/* 2004 */ MCD_OPC_Decode, 242, 8, 95, // Opcode: MOVF_S -/* 2008 */ MCD_OPC_FilterValue, 1, 194, 45, // Skip to: 13726 -/* 2012 */ MCD_OPC_CheckPredicate, 7, 190, 45, // Skip to: 13726 -/* 2016 */ MCD_OPC_Decode, 134, 9, 95, // Opcode: MOVT_S -/* 2020 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2032 -/* 2024 */ MCD_OPC_CheckPredicate, 7, 178, 45, // Skip to: 13726 -/* 2028 */ MCD_OPC_Decode, 146, 9, 96, // Opcode: MOVZ_I_S -/* 2032 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2044 -/* 2036 */ MCD_OPC_CheckPredicate, 7, 166, 45, // Skip to: 13726 -/* 2040 */ MCD_OPC_Decode, 254, 8, 96, // Opcode: MOVN_I_S -/* 2044 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 2062 -/* 2048 */ MCD_OPC_CheckPredicate, 21, 154, 45, // Skip to: 13726 -/* 2052 */ MCD_OPC_CheckField, 16, 5, 0, 148, 45, // Skip to: 13726 -/* 2058 */ MCD_OPC_Decode, 213, 3, 97, // Opcode: CVT_D32_S -/* 2062 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2080 -/* 2066 */ MCD_OPC_CheckPredicate, 5, 136, 45, // Skip to: 13726 -/* 2070 */ MCD_OPC_CheckField, 16, 5, 0, 130, 45, // Skip to: 13726 -/* 2076 */ MCD_OPC_Decode, 233, 3, 94, // Opcode: CVT_W_S -/* 2080 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2098 -/* 2084 */ MCD_OPC_CheckPredicate, 22, 118, 45, // Skip to: 13726 -/* 2088 */ MCD_OPC_CheckField, 16, 5, 0, 112, 45, // Skip to: 13726 -/* 2094 */ MCD_OPC_Decode, 222, 3, 98, // Opcode: CVT_L_S -/* 2098 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2116 -/* 2102 */ MCD_OPC_CheckPredicate, 13, 100, 45, // Skip to: 13726 -/* 2106 */ MCD_OPC_CheckField, 6, 5, 0, 94, 45, // Skip to: 13726 -/* 2112 */ MCD_OPC_Decode, 240, 3, 99, // Opcode: C_F_S -/* 2116 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2134 -/* 2120 */ MCD_OPC_CheckPredicate, 13, 82, 45, // Skip to: 13726 -/* 2124 */ MCD_OPC_CheckField, 6, 5, 0, 76, 45, // Skip to: 13726 -/* 2130 */ MCD_OPC_Decode, 154, 4, 99, // Opcode: C_UN_S -/* 2134 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2152 -/* 2138 */ MCD_OPC_CheckPredicate, 13, 64, 45, // Skip to: 13726 -/* 2142 */ MCD_OPC_CheckField, 6, 5, 0, 58, 45, // Skip to: 13726 -/* 2148 */ MCD_OPC_Decode, 237, 3, 99, // Opcode: C_EQ_S -/* 2152 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2170 -/* 2156 */ MCD_OPC_CheckPredicate, 13, 46, 45, // Skip to: 13726 -/* 2160 */ MCD_OPC_CheckField, 6, 5, 0, 40, 45, // Skip to: 13726 -/* 2166 */ MCD_OPC_Decode, 145, 4, 99, // Opcode: C_UEQ_S -/* 2170 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2188 -/* 2174 */ MCD_OPC_CheckPredicate, 13, 28, 45, // Skip to: 13726 -/* 2178 */ MCD_OPC_CheckField, 6, 5, 0, 22, 45, // Skip to: 13726 -/* 2184 */ MCD_OPC_Decode, 136, 4, 99, // Opcode: C_OLT_S -/* 2188 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2206 -/* 2192 */ MCD_OPC_CheckPredicate, 13, 10, 45, // Skip to: 13726 -/* 2196 */ MCD_OPC_CheckField, 6, 5, 0, 4, 45, // Skip to: 13726 -/* 2202 */ MCD_OPC_Decode, 151, 4, 99, // Opcode: C_ULT_S -/* 2206 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2224 -/* 2210 */ MCD_OPC_CheckPredicate, 13, 248, 44, // Skip to: 13726 -/* 2214 */ MCD_OPC_CheckField, 6, 5, 0, 242, 44, // Skip to: 13726 -/* 2220 */ MCD_OPC_Decode, 133, 4, 99, // Opcode: C_OLE_S -/* 2224 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2242 -/* 2228 */ MCD_OPC_CheckPredicate, 13, 230, 44, // Skip to: 13726 -/* 2232 */ MCD_OPC_CheckField, 6, 5, 0, 224, 44, // Skip to: 13726 -/* 2238 */ MCD_OPC_Decode, 148, 4, 99, // Opcode: C_ULE_S -/* 2242 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2260 -/* 2246 */ MCD_OPC_CheckPredicate, 13, 212, 44, // Skip to: 13726 -/* 2250 */ MCD_OPC_CheckField, 6, 5, 0, 206, 44, // Skip to: 13726 -/* 2256 */ MCD_OPC_Decode, 142, 4, 99, // Opcode: C_SF_S -/* 2260 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2278 -/* 2264 */ MCD_OPC_CheckPredicate, 13, 194, 44, // Skip to: 13726 -/* 2268 */ MCD_OPC_CheckField, 6, 5, 0, 188, 44, // Skip to: 13726 -/* 2274 */ MCD_OPC_Decode, 252, 3, 99, // Opcode: C_NGLE_S -/* 2278 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2296 -/* 2282 */ MCD_OPC_CheckPredicate, 13, 176, 44, // Skip to: 13726 -/* 2286 */ MCD_OPC_CheckField, 6, 5, 0, 170, 44, // Skip to: 13726 -/* 2292 */ MCD_OPC_Decode, 139, 4, 99, // Opcode: C_SEQ_S -/* 2296 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2314 -/* 2300 */ MCD_OPC_CheckPredicate, 13, 158, 44, // Skip to: 13726 -/* 2304 */ MCD_OPC_CheckField, 6, 5, 0, 152, 44, // Skip to: 13726 -/* 2310 */ MCD_OPC_Decode, 255, 3, 99, // Opcode: C_NGL_S -/* 2314 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2332 -/* 2318 */ MCD_OPC_CheckPredicate, 13, 140, 44, // Skip to: 13726 -/* 2322 */ MCD_OPC_CheckField, 6, 5, 0, 134, 44, // Skip to: 13726 -/* 2328 */ MCD_OPC_Decode, 246, 3, 99, // Opcode: C_LT_S -/* 2332 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2350 -/* 2336 */ MCD_OPC_CheckPredicate, 13, 122, 44, // Skip to: 13726 -/* 2340 */ MCD_OPC_CheckField, 6, 5, 0, 116, 44, // Skip to: 13726 -/* 2346 */ MCD_OPC_Decode, 249, 3, 99, // Opcode: C_NGE_S -/* 2350 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2368 -/* 2354 */ MCD_OPC_CheckPredicate, 13, 104, 44, // Skip to: 13726 -/* 2358 */ MCD_OPC_CheckField, 6, 5, 0, 98, 44, // Skip to: 13726 -/* 2364 */ MCD_OPC_Decode, 243, 3, 99, // Opcode: C_LE_S -/* 2368 */ MCD_OPC_FilterValue, 63, 90, 44, // Skip to: 13726 -/* 2372 */ MCD_OPC_CheckPredicate, 13, 86, 44, // Skip to: 13726 -/* 2376 */ MCD_OPC_CheckField, 6, 5, 0, 80, 44, // Skip to: 13726 -/* 2382 */ MCD_OPC_Decode, 130, 4, 99, // Opcode: C_NGT_S -/* 2386 */ MCD_OPC_FilterValue, 17, 80, 2, // Skip to: 2982 -/* 2390 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 2393 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2405 -/* 2397 */ MCD_OPC_CheckPredicate, 21, 61, 44, // Skip to: 13726 -/* 2401 */ MCD_OPC_Decode, 171, 5, 100, // Opcode: FADD_D32 -/* 2405 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2417 -/* 2409 */ MCD_OPC_CheckPredicate, 21, 49, 44, // Skip to: 13726 -/* 2413 */ MCD_OPC_Decode, 173, 6, 100, // Opcode: FSUB_D32 -/* 2417 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2429 -/* 2421 */ MCD_OPC_CheckPredicate, 21, 37, 44, // Skip to: 13726 -/* 2425 */ MCD_OPC_Decode, 136, 6, 100, // Opcode: FMUL_D32 -/* 2429 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2441 -/* 2433 */ MCD_OPC_CheckPredicate, 21, 25, 44, // Skip to: 13726 -/* 2437 */ MCD_OPC_Decode, 207, 5, 100, // Opcode: FDIV_D32 -/* 2441 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 2459 -/* 2445 */ MCD_OPC_CheckPredicate, 23, 13, 44, // Skip to: 13726 -/* 2449 */ MCD_OPC_CheckField, 16, 5, 0, 7, 44, // Skip to: 13726 -/* 2455 */ MCD_OPC_Decode, 166, 6, 101, // Opcode: FSQRT_D32 -/* 2459 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 2477 -/* 2463 */ MCD_OPC_CheckPredicate, 21, 251, 43, // Skip to: 13726 -/* 2467 */ MCD_OPC_CheckField, 16, 5, 0, 245, 43, // Skip to: 13726 -/* 2473 */ MCD_OPC_Decode, 164, 5, 101, // Opcode: FABS_D32 -/* 2477 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2495 -/* 2481 */ MCD_OPC_CheckPredicate, 21, 233, 43, // Skip to: 13726 -/* 2485 */ MCD_OPC_CheckField, 16, 5, 0, 227, 43, // Skip to: 13726 -/* 2491 */ MCD_OPC_Decode, 128, 6, 101, // Opcode: FMOV_D32 -/* 2495 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2513 -/* 2499 */ MCD_OPC_CheckPredicate, 21, 215, 43, // Skip to: 13726 -/* 2503 */ MCD_OPC_CheckField, 16, 5, 0, 209, 43, // Skip to: 13726 -/* 2509 */ MCD_OPC_Decode, 142, 6, 101, // Opcode: FNEG_D32 -/* 2513 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 2531 -/* 2517 */ MCD_OPC_CheckPredicate, 23, 197, 43, // Skip to: 13726 -/* 2521 */ MCD_OPC_CheckField, 16, 5, 0, 191, 43, // Skip to: 13726 -/* 2527 */ MCD_OPC_Decode, 253, 10, 102, // Opcode: ROUND_W_D32 -/* 2531 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 2549 -/* 2535 */ MCD_OPC_CheckPredicate, 23, 179, 43, // Skip to: 13726 -/* 2539 */ MCD_OPC_CheckField, 16, 5, 0, 173, 43, // Skip to: 13726 -/* 2545 */ MCD_OPC_Decode, 216, 13, 102, // Opcode: TRUNC_W_D32 -/* 2549 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 2567 -/* 2553 */ MCD_OPC_CheckPredicate, 23, 161, 43, // Skip to: 13726 -/* 2557 */ MCD_OPC_CheckField, 16, 5, 0, 155, 43, // Skip to: 13726 -/* 2563 */ MCD_OPC_Decode, 225, 2, 102, // Opcode: CEIL_W_D32 -/* 2567 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 2585 -/* 2571 */ MCD_OPC_CheckPredicate, 23, 143, 43, // Skip to: 13726 -/* 2575 */ MCD_OPC_CheckField, 16, 5, 0, 137, 43, // Skip to: 13726 -/* 2581 */ MCD_OPC_Decode, 241, 5, 102, // Opcode: FLOOR_W_D32 -/* 2585 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2616 -/* 2589 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 2592 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2604 -/* 2596 */ MCD_OPC_CheckPredicate, 24, 118, 43, // Skip to: 13726 -/* 2600 */ MCD_OPC_Decode, 236, 8, 103, // Opcode: MOVF_D32 -/* 2604 */ MCD_OPC_FilterValue, 1, 110, 43, // Skip to: 13726 -/* 2608 */ MCD_OPC_CheckPredicate, 24, 106, 43, // Skip to: 13726 -/* 2612 */ MCD_OPC_Decode, 128, 9, 103, // Opcode: MOVT_D32 -/* 2616 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2628 -/* 2620 */ MCD_OPC_CheckPredicate, 24, 94, 43, // Skip to: 13726 -/* 2624 */ MCD_OPC_Decode, 140, 9, 104, // Opcode: MOVZ_I_D32 -/* 2628 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2640 -/* 2632 */ MCD_OPC_CheckPredicate, 24, 82, 43, // Skip to: 13726 -/* 2636 */ MCD_OPC_Decode, 248, 8, 104, // Opcode: MOVN_I_D32 -/* 2640 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2658 -/* 2644 */ MCD_OPC_CheckPredicate, 21, 70, 43, // Skip to: 13726 -/* 2648 */ MCD_OPC_CheckField, 16, 5, 0, 64, 43, // Skip to: 13726 -/* 2654 */ MCD_OPC_Decode, 224, 3, 102, // Opcode: CVT_S_D32 -/* 2658 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2676 -/* 2662 */ MCD_OPC_CheckPredicate, 21, 52, 43, // Skip to: 13726 -/* 2666 */ MCD_OPC_CheckField, 16, 5, 0, 46, 43, // Skip to: 13726 -/* 2672 */ MCD_OPC_Decode, 230, 3, 102, // Opcode: CVT_W_D32 -/* 2676 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2694 -/* 2680 */ MCD_OPC_CheckPredicate, 22, 34, 43, // Skip to: 13726 -/* 2684 */ MCD_OPC_CheckField, 16, 5, 0, 28, 43, // Skip to: 13726 -/* 2690 */ MCD_OPC_Decode, 220, 3, 105, // Opcode: CVT_L_D64 -/* 2694 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2712 -/* 2698 */ MCD_OPC_CheckPredicate, 25, 16, 43, // Skip to: 13726 -/* 2702 */ MCD_OPC_CheckField, 6, 5, 0, 10, 43, // Skip to: 13726 -/* 2708 */ MCD_OPC_Decode, 238, 3, 106, // Opcode: C_F_D32 -/* 2712 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2730 -/* 2716 */ MCD_OPC_CheckPredicate, 25, 254, 42, // Skip to: 13726 -/* 2720 */ MCD_OPC_CheckField, 6, 5, 0, 248, 42, // Skip to: 13726 -/* 2726 */ MCD_OPC_Decode, 152, 4, 106, // Opcode: C_UN_D32 -/* 2730 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2748 -/* 2734 */ MCD_OPC_CheckPredicate, 25, 236, 42, // Skip to: 13726 -/* 2738 */ MCD_OPC_CheckField, 6, 5, 0, 230, 42, // Skip to: 13726 -/* 2744 */ MCD_OPC_Decode, 235, 3, 106, // Opcode: C_EQ_D32 -/* 2748 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2766 -/* 2752 */ MCD_OPC_CheckPredicate, 25, 218, 42, // Skip to: 13726 -/* 2756 */ MCD_OPC_CheckField, 6, 5, 0, 212, 42, // Skip to: 13726 -/* 2762 */ MCD_OPC_Decode, 143, 4, 106, // Opcode: C_UEQ_D32 -/* 2766 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2784 -/* 2770 */ MCD_OPC_CheckPredicate, 25, 200, 42, // Skip to: 13726 -/* 2774 */ MCD_OPC_CheckField, 6, 5, 0, 194, 42, // Skip to: 13726 -/* 2780 */ MCD_OPC_Decode, 134, 4, 106, // Opcode: C_OLT_D32 -/* 2784 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2802 -/* 2788 */ MCD_OPC_CheckPredicate, 25, 182, 42, // Skip to: 13726 -/* 2792 */ MCD_OPC_CheckField, 6, 5, 0, 176, 42, // Skip to: 13726 -/* 2798 */ MCD_OPC_Decode, 149, 4, 106, // Opcode: C_ULT_D32 -/* 2802 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2820 -/* 2806 */ MCD_OPC_CheckPredicate, 25, 164, 42, // Skip to: 13726 -/* 2810 */ MCD_OPC_CheckField, 6, 5, 0, 158, 42, // Skip to: 13726 -/* 2816 */ MCD_OPC_Decode, 131, 4, 106, // Opcode: C_OLE_D32 -/* 2820 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2838 -/* 2824 */ MCD_OPC_CheckPredicate, 25, 146, 42, // Skip to: 13726 -/* 2828 */ MCD_OPC_CheckField, 6, 5, 0, 140, 42, // Skip to: 13726 -/* 2834 */ MCD_OPC_Decode, 146, 4, 106, // Opcode: C_ULE_D32 -/* 2838 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2856 -/* 2842 */ MCD_OPC_CheckPredicate, 25, 128, 42, // Skip to: 13726 -/* 2846 */ MCD_OPC_CheckField, 6, 5, 0, 122, 42, // Skip to: 13726 -/* 2852 */ MCD_OPC_Decode, 140, 4, 106, // Opcode: C_SF_D32 -/* 2856 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2874 -/* 2860 */ MCD_OPC_CheckPredicate, 25, 110, 42, // Skip to: 13726 -/* 2864 */ MCD_OPC_CheckField, 6, 5, 0, 104, 42, // Skip to: 13726 -/* 2870 */ MCD_OPC_Decode, 250, 3, 106, // Opcode: C_NGLE_D32 -/* 2874 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2892 -/* 2878 */ MCD_OPC_CheckPredicate, 25, 92, 42, // Skip to: 13726 -/* 2882 */ MCD_OPC_CheckField, 6, 5, 0, 86, 42, // Skip to: 13726 -/* 2888 */ MCD_OPC_Decode, 137, 4, 106, // Opcode: C_SEQ_D32 -/* 2892 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2910 -/* 2896 */ MCD_OPC_CheckPredicate, 25, 74, 42, // Skip to: 13726 -/* 2900 */ MCD_OPC_CheckField, 6, 5, 0, 68, 42, // Skip to: 13726 -/* 2906 */ MCD_OPC_Decode, 253, 3, 106, // Opcode: C_NGL_D32 -/* 2910 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2928 -/* 2914 */ MCD_OPC_CheckPredicate, 25, 56, 42, // Skip to: 13726 -/* 2918 */ MCD_OPC_CheckField, 6, 5, 0, 50, 42, // Skip to: 13726 -/* 2924 */ MCD_OPC_Decode, 244, 3, 106, // Opcode: C_LT_D32 -/* 2928 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2946 -/* 2932 */ MCD_OPC_CheckPredicate, 25, 38, 42, // Skip to: 13726 -/* 2936 */ MCD_OPC_CheckField, 6, 5, 0, 32, 42, // Skip to: 13726 -/* 2942 */ MCD_OPC_Decode, 247, 3, 106, // Opcode: C_NGE_D32 -/* 2946 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2964 -/* 2950 */ MCD_OPC_CheckPredicate, 25, 20, 42, // Skip to: 13726 -/* 2954 */ MCD_OPC_CheckField, 6, 5, 0, 14, 42, // Skip to: 13726 -/* 2960 */ MCD_OPC_Decode, 241, 3, 106, // Opcode: C_LE_D32 -/* 2964 */ MCD_OPC_FilterValue, 63, 6, 42, // Skip to: 13726 -/* 2968 */ MCD_OPC_CheckPredicate, 25, 2, 42, // Skip to: 13726 -/* 2972 */ MCD_OPC_CheckField, 6, 5, 0, 252, 41, // Skip to: 13726 -/* 2978 */ MCD_OPC_Decode, 128, 4, 106, // Opcode: C_NGT_D32 -/* 2982 */ MCD_OPC_FilterValue, 20, 39, 0, // Skip to: 3025 -/* 2986 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 2989 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3007 -/* 2993 */ MCD_OPC_CheckPredicate, 5, 233, 41, // Skip to: 13726 -/* 2997 */ MCD_OPC_CheckField, 16, 5, 0, 227, 41, // Skip to: 13726 -/* 3003 */ MCD_OPC_Decode, 228, 3, 94, // Opcode: CVT_S_W -/* 3007 */ MCD_OPC_FilterValue, 33, 219, 41, // Skip to: 13726 -/* 3011 */ MCD_OPC_CheckPredicate, 21, 215, 41, // Skip to: 13726 -/* 3015 */ MCD_OPC_CheckField, 16, 5, 0, 209, 41, // Skip to: 13726 -/* 3021 */ MCD_OPC_Decode, 214, 3, 97, // Opcode: CVT_D32_W -/* 3025 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 3037 -/* 3029 */ MCD_OPC_CheckPredicate, 8, 197, 41, // Skip to: 13726 -/* 3033 */ MCD_OPC_Decode, 189, 2, 92, // Opcode: BZ_B -/* 3037 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 3049 -/* 3041 */ MCD_OPC_CheckPredicate, 8, 185, 41, // Skip to: 13726 -/* 3045 */ MCD_OPC_Decode, 191, 2, 107, // Opcode: BZ_H -/* 3049 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 3061 -/* 3053 */ MCD_OPC_CheckPredicate, 8, 173, 41, // Skip to: 13726 -/* 3057 */ MCD_OPC_Decode, 193, 2, 108, // Opcode: BZ_W -/* 3061 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 3073 -/* 3065 */ MCD_OPC_CheckPredicate, 8, 161, 41, // Skip to: 13726 -/* 3069 */ MCD_OPC_Decode, 190, 2, 109, // Opcode: BZ_D -/* 3073 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 3085 -/* 3077 */ MCD_OPC_CheckPredicate, 8, 149, 41, // Skip to: 13726 -/* 3081 */ MCD_OPC_Decode, 163, 2, 92, // Opcode: BNZ_B -/* 3085 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3097 -/* 3089 */ MCD_OPC_CheckPredicate, 8, 137, 41, // Skip to: 13726 -/* 3093 */ MCD_OPC_Decode, 165, 2, 107, // Opcode: BNZ_H -/* 3097 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 3109 -/* 3101 */ MCD_OPC_CheckPredicate, 8, 125, 41, // Skip to: 13726 -/* 3105 */ MCD_OPC_Decode, 167, 2, 108, // Opcode: BNZ_W -/* 3109 */ MCD_OPC_FilterValue, 31, 117, 41, // Skip to: 13726 -/* 3113 */ MCD_OPC_CheckPredicate, 8, 113, 41, // Skip to: 13726 -/* 3117 */ MCD_OPC_Decode, 164, 2, 109, // Opcode: BNZ_D -/* 3121 */ MCD_OPC_FilterValue, 18, 94, 0, // Skip to: 3219 -/* 3125 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 3128 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3146 -/* 3132 */ MCD_OPC_CheckPredicate, 5, 94, 41, // Skip to: 13726 -/* 3136 */ MCD_OPC_CheckField, 3, 8, 0, 88, 41, // Skip to: 13726 -/* 3142 */ MCD_OPC_Decode, 182, 8, 81, // Opcode: MFC2 -/* 3146 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 3164 -/* 3150 */ MCD_OPC_CheckPredicate, 5, 76, 41, // Skip to: 13726 -/* 3154 */ MCD_OPC_CheckField, 3, 8, 0, 70, 41, // Skip to: 13726 -/* 3160 */ MCD_OPC_Decode, 172, 9, 81, // Opcode: MTC2 -/* 3164 */ MCD_OPC_FilterValue, 8, 62, 41, // Skip to: 13726 -/* 3168 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 3171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3183 -/* 3175 */ MCD_OPC_CheckPredicate, 13, 51, 41, // Skip to: 13726 -/* 3179 */ MCD_OPC_Decode, 189, 1, 82, // Opcode: BC2F -/* 3183 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3195 -/* 3187 */ MCD_OPC_CheckPredicate, 13, 39, 41, // Skip to: 13726 -/* 3191 */ MCD_OPC_Decode, 192, 1, 82, // Opcode: BC2T -/* 3195 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3207 -/* 3199 */ MCD_OPC_CheckPredicate, 13, 27, 41, // Skip to: 13726 -/* 3203 */ MCD_OPC_Decode, 190, 1, 82, // Opcode: BC2FL -/* 3207 */ MCD_OPC_FilterValue, 3, 19, 41, // Skip to: 13726 -/* 3211 */ MCD_OPC_CheckPredicate, 13, 15, 41, // Skip to: 13726 -/* 3215 */ MCD_OPC_Decode, 193, 1, 82, // Opcode: BC2TL -/* 3219 */ MCD_OPC_FilterValue, 19, 9, 1, // Skip to: 3488 -/* 3223 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 3226 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 3281 -/* 3230 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 3233 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3245 -/* 3237 */ MCD_OPC_CheckPredicate, 13, 40, 0, // Skip to: 3281 -/* 3241 */ MCD_OPC_Decode, 194, 1, 82, // Opcode: BC3F -/* 3245 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3257 -/* 3249 */ MCD_OPC_CheckPredicate, 13, 28, 0, // Skip to: 3281 -/* 3253 */ MCD_OPC_Decode, 196, 1, 82, // Opcode: BC3T -/* 3257 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3269 -/* 3261 */ MCD_OPC_CheckPredicate, 13, 16, 0, // Skip to: 3281 -/* 3265 */ MCD_OPC_Decode, 195, 1, 82, // Opcode: BC3FL -/* 3269 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3281 -/* 3273 */ MCD_OPC_CheckPredicate, 13, 4, 0, // Skip to: 3281 -/* 3277 */ MCD_OPC_Decode, 197, 1, 82, // Opcode: BC3TL -/* 3281 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3284 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3302 -/* 3288 */ MCD_OPC_CheckPredicate, 26, 194, 40, // Skip to: 13726 -/* 3292 */ MCD_OPC_CheckField, 11, 5, 0, 188, 40, // Skip to: 13726 -/* 3298 */ MCD_OPC_Decode, 237, 7, 110, // Opcode: LWXC1 -/* 3302 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3320 -/* 3306 */ MCD_OPC_CheckPredicate, 27, 176, 40, // Skip to: 13726 -/* 3310 */ MCD_OPC_CheckField, 11, 5, 0, 170, 40, // Skip to: 13726 -/* 3316 */ MCD_OPC_Decode, 175, 7, 111, // Opcode: LDXC1 -/* 3320 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 3338 -/* 3324 */ MCD_OPC_CheckPredicate, 28, 158, 40, // Skip to: 13726 -/* 3328 */ MCD_OPC_CheckField, 11, 5, 0, 152, 40, // Skip to: 13726 -/* 3334 */ MCD_OPC_Decode, 207, 7, 111, // Opcode: LUXC1 -/* 3338 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3356 -/* 3342 */ MCD_OPC_CheckPredicate, 26, 140, 40, // Skip to: 13726 -/* 3346 */ MCD_OPC_CheckField, 6, 5, 0, 134, 40, // Skip to: 13726 -/* 3352 */ MCD_OPC_Decode, 254, 12, 112, // Opcode: SWXC1 -/* 3356 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3374 -/* 3360 */ MCD_OPC_CheckPredicate, 27, 122, 40, // Skip to: 13726 -/* 3364 */ MCD_OPC_CheckField, 6, 5, 0, 116, 40, // Skip to: 13726 -/* 3370 */ MCD_OPC_Decode, 166, 11, 113, // Opcode: SDXC1 -/* 3374 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 3392 -/* 3378 */ MCD_OPC_CheckPredicate, 28, 104, 40, // Skip to: 13726 -/* 3382 */ MCD_OPC_CheckField, 6, 5, 0, 98, 40, // Skip to: 13726 -/* 3388 */ MCD_OPC_Decode, 232, 12, 113, // Opcode: SUXC1 -/* 3392 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3404 -/* 3396 */ MCD_OPC_CheckPredicate, 26, 86, 40, // Skip to: 13726 -/* 3400 */ MCD_OPC_Decode, 149, 8, 114, // Opcode: MADD_S -/* 3404 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3416 -/* 3408 */ MCD_OPC_CheckPredicate, 29, 74, 40, // Skip to: 13726 -/* 3412 */ MCD_OPC_Decode, 142, 8, 115, // Opcode: MADD_D32 -/* 3416 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3428 -/* 3420 */ MCD_OPC_CheckPredicate, 26, 62, 40, // Skip to: 13726 -/* 3424 */ MCD_OPC_Decode, 167, 9, 114, // Opcode: MSUB_S -/* 3428 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3440 -/* 3432 */ MCD_OPC_CheckPredicate, 29, 50, 40, // Skip to: 13726 -/* 3436 */ MCD_OPC_Decode, 160, 9, 115, // Opcode: MSUB_D32 -/* 3440 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 3452 -/* 3444 */ MCD_OPC_CheckPredicate, 26, 38, 40, // Skip to: 13726 -/* 3448 */ MCD_OPC_Decode, 242, 9, 114, // Opcode: NMADD_S -/* 3452 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3464 -/* 3456 */ MCD_OPC_CheckPredicate, 29, 26, 40, // Skip to: 13726 -/* 3460 */ MCD_OPC_Decode, 239, 9, 115, // Opcode: NMADD_D32 -/* 3464 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 3476 -/* 3468 */ MCD_OPC_CheckPredicate, 26, 14, 40, // Skip to: 13726 -/* 3472 */ MCD_OPC_Decode, 247, 9, 114, // Opcode: NMSUB_S -/* 3476 */ MCD_OPC_FilterValue, 57, 6, 40, // Skip to: 13726 -/* 3480 */ MCD_OPC_CheckPredicate, 29, 2, 40, // Skip to: 13726 -/* 3484 */ MCD_OPC_Decode, 244, 9, 115, // Opcode: NMSUB_D32 -/* 3488 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 3500 -/* 3492 */ MCD_OPC_CheckPredicate, 16, 246, 39, // Skip to: 13726 -/* 3496 */ MCD_OPC_Decode, 209, 1, 78, // Opcode: BEQL -/* 3500 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 3512 -/* 3504 */ MCD_OPC_CheckPredicate, 16, 234, 39, // Skip to: 13726 -/* 3508 */ MCD_OPC_Decode, 156, 2, 78, // Opcode: BNEL -/* 3512 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 3530 -/* 3516 */ MCD_OPC_CheckPredicate, 16, 222, 39, // Skip to: 13726 -/* 3520 */ MCD_OPC_CheckField, 16, 5, 0, 216, 39, // Skip to: 13726 -/* 3526 */ MCD_OPC_Decode, 255, 1, 73, // Opcode: BLEZL -/* 3530 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3548 -/* 3534 */ MCD_OPC_CheckPredicate, 16, 204, 39, // Skip to: 13726 -/* 3538 */ MCD_OPC_CheckField, 16, 5, 0, 198, 39, // Skip to: 13726 -/* 3544 */ MCD_OPC_Decode, 231, 1, 73, // Opcode: BGTZL -/* 3548 */ MCD_OPC_FilterValue, 28, 229, 0, // Skip to: 3781 -/* 3552 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3555 */ MCD_OPC_FilterValue, 0, 36, 0, // Skip to: 3595 -/* 3559 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3562 */ MCD_OPC_FilterValue, 0, 176, 39, // Skip to: 13726 -/* 3566 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3569 */ MCD_OPC_FilterValue, 0, 169, 39, // Skip to: 13726 -/* 3573 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3587 -/* 3577 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3587 -/* 3583 */ MCD_OPC_Decode, 130, 8, 43, // Opcode: MADD -/* 3587 */ MCD_OPC_CheckPredicate, 12, 151, 39, // Skip to: 13726 -/* 3591 */ MCD_OPC_Decode, 145, 8, 116, // Opcode: MADD_DSP -/* 3595 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 3635 -/* 3599 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3602 */ MCD_OPC_FilterValue, 0, 136, 39, // Skip to: 13726 -/* 3606 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3609 */ MCD_OPC_FilterValue, 0, 129, 39, // Skip to: 13726 -/* 3613 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3627 -/* 3617 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3627 -/* 3623 */ MCD_OPC_Decode, 135, 8, 43, // Opcode: MADDU -/* 3627 */ MCD_OPC_CheckPredicate, 12, 111, 39, // Skip to: 13726 -/* 3631 */ MCD_OPC_Decode, 136, 8, 116, // Opcode: MADDU_DSP -/* 3635 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3653 -/* 3639 */ MCD_OPC_CheckPredicate, 9, 99, 39, // Skip to: 13726 -/* 3643 */ MCD_OPC_CheckField, 6, 5, 0, 93, 39, // Skip to: 13726 -/* 3649 */ MCD_OPC_Decode, 193, 9, 35, // Opcode: MUL -/* 3653 */ MCD_OPC_FilterValue, 4, 36, 0, // Skip to: 3693 -/* 3657 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3660 */ MCD_OPC_FilterValue, 0, 78, 39, // Skip to: 13726 -/* 3664 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3667 */ MCD_OPC_FilterValue, 0, 71, 39, // Skip to: 13726 -/* 3671 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3685 -/* 3675 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3685 -/* 3681 */ MCD_OPC_Decode, 148, 9, 43, // Opcode: MSUB -/* 3685 */ MCD_OPC_CheckPredicate, 12, 53, 39, // Skip to: 13726 -/* 3689 */ MCD_OPC_Decode, 163, 9, 116, // Opcode: MSUB_DSP -/* 3693 */ MCD_OPC_FilterValue, 5, 36, 0, // Skip to: 3733 -/* 3697 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3700 */ MCD_OPC_FilterValue, 0, 38, 39, // Skip to: 13726 -/* 3704 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3707 */ MCD_OPC_FilterValue, 0, 31, 39, // Skip to: 13726 -/* 3711 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3725 -/* 3715 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3725 -/* 3721 */ MCD_OPC_Decode, 153, 9, 43, // Opcode: MSUBU -/* 3725 */ MCD_OPC_CheckPredicate, 12, 13, 39, // Skip to: 13726 -/* 3729 */ MCD_OPC_Decode, 154, 9, 116, // Opcode: MSUBU_DSP -/* 3733 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3751 -/* 3737 */ MCD_OPC_CheckPredicate, 9, 1, 39, // Skip to: 13726 -/* 3741 */ MCD_OPC_CheckField, 6, 5, 0, 251, 38, // Skip to: 13726 -/* 3747 */ MCD_OPC_Decode, 152, 3, 117, // Opcode: CLZ -/* 3751 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3769 -/* 3755 */ MCD_OPC_CheckPredicate, 9, 239, 38, // Skip to: 13726 -/* 3759 */ MCD_OPC_CheckField, 6, 5, 0, 233, 38, // Skip to: 13726 -/* 3765 */ MCD_OPC_Decode, 133, 3, 117, // Opcode: CLO -/* 3769 */ MCD_OPC_FilterValue, 63, 225, 38, // Skip to: 13726 -/* 3773 */ MCD_OPC_CheckPredicate, 9, 221, 38, // Skip to: 13726 -/* 3777 */ MCD_OPC_Decode, 152, 11, 64, // Opcode: SDBBP -/* 3781 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3793 -/* 3785 */ MCD_OPC_CheckPredicate, 9, 209, 38, // Skip to: 13726 -/* 3789 */ MCD_OPC_Decode, 131, 7, 77, // Opcode: JALX -/* 3793 */ MCD_OPC_FilterValue, 30, 28, 28, // Skip to: 10993 -/* 3797 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3800 */ MCD_OPC_FilterValue, 0, 50, 0, // Skip to: 3854 -/* 3804 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 3807 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3818 -/* 3811 */ MCD_OPC_CheckPredicate, 8, 183, 38, // Skip to: 13726 -/* 3815 */ MCD_OPC_Decode, 87, 118, // Opcode: ANDI_B -/* 3818 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3830 -/* 3822 */ MCD_OPC_CheckPredicate, 8, 172, 38, // Skip to: 13726 -/* 3826 */ MCD_OPC_Decode, 136, 10, 118, // Opcode: ORI_B -/* 3830 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3842 -/* 3834 */ MCD_OPC_CheckPredicate, 8, 160, 38, // Skip to: 13726 -/* 3838 */ MCD_OPC_Decode, 252, 9, 118, // Opcode: NORI_B -/* 3842 */ MCD_OPC_FilterValue, 3, 152, 38, // Skip to: 13726 -/* 3846 */ MCD_OPC_CheckPredicate, 8, 148, 38, // Skip to: 13726 -/* 3850 */ MCD_OPC_Decode, 239, 13, 118, // Opcode: XORI_B -/* 3854 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 3897 -/* 3858 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 3861 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3873 -/* 3865 */ MCD_OPC_CheckPredicate, 8, 129, 38, // Skip to: 13726 -/* 3869 */ MCD_OPC_Decode, 141, 2, 119, // Opcode: BMNZI_B -/* 3873 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3885 -/* 3877 */ MCD_OPC_CheckPredicate, 8, 117, 38, // Skip to: 13726 -/* 3881 */ MCD_OPC_Decode, 143, 2, 119, // Opcode: BMZI_B -/* 3885 */ MCD_OPC_FilterValue, 2, 109, 38, // Skip to: 13726 -/* 3889 */ MCD_OPC_CheckPredicate, 8, 105, 38, // Skip to: 13726 -/* 3893 */ MCD_OPC_Decode, 174, 2, 119, // Opcode: BSELI_B -/* 3897 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 3940 -/* 3901 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 3904 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3916 -/* 3908 */ MCD_OPC_CheckPredicate, 8, 86, 38, // Skip to: 13726 -/* 3912 */ MCD_OPC_Decode, 189, 11, 118, // Opcode: SHF_B -/* 3916 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3928 -/* 3920 */ MCD_OPC_CheckPredicate, 8, 74, 38, // Skip to: 13726 -/* 3924 */ MCD_OPC_Decode, 190, 11, 120, // Opcode: SHF_H -/* 3928 */ MCD_OPC_FilterValue, 2, 66, 38, // Skip to: 13726 -/* 3932 */ MCD_OPC_CheckPredicate, 8, 62, 38, // Skip to: 13726 -/* 3936 */ MCD_OPC_Decode, 191, 11, 121, // Opcode: SHF_W -/* 3940 */ MCD_OPC_FilterValue, 6, 31, 1, // Skip to: 4231 -/* 3944 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 3947 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3958 -/* 3951 */ MCD_OPC_CheckPredicate, 8, 43, 38, // Skip to: 13726 -/* 3955 */ MCD_OPC_Decode, 59, 122, // Opcode: ADDVI_B -/* 3958 */ MCD_OPC_FilterValue, 1, 7, 0, // Skip to: 3969 -/* 3962 */ MCD_OPC_CheckPredicate, 8, 32, 38, // Skip to: 13726 -/* 3966 */ MCD_OPC_Decode, 61, 123, // Opcode: ADDVI_H -/* 3969 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 3980 -/* 3973 */ MCD_OPC_CheckPredicate, 8, 21, 38, // Skip to: 13726 -/* 3977 */ MCD_OPC_Decode, 62, 124, // Opcode: ADDVI_W -/* 3980 */ MCD_OPC_FilterValue, 3, 7, 0, // Skip to: 3991 -/* 3984 */ MCD_OPC_CheckPredicate, 8, 10, 38, // Skip to: 13726 -/* 3988 */ MCD_OPC_Decode, 60, 125, // Opcode: ADDVI_D -/* 3991 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 4003 -/* 3995 */ MCD_OPC_CheckPredicate, 8, 255, 37, // Skip to: 13726 -/* 3999 */ MCD_OPC_Decode, 221, 12, 122, // Opcode: SUBVI_B -/* 4003 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 4015 -/* 4007 */ MCD_OPC_CheckPredicate, 8, 243, 37, // Skip to: 13726 -/* 4011 */ MCD_OPC_Decode, 223, 12, 123, // Opcode: SUBVI_H -/* 4015 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 4027 -/* 4019 */ MCD_OPC_CheckPredicate, 8, 231, 37, // Skip to: 13726 -/* 4023 */ MCD_OPC_Decode, 224, 12, 124, // Opcode: SUBVI_W -/* 4027 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 4039 -/* 4031 */ MCD_OPC_CheckPredicate, 8, 219, 37, // Skip to: 13726 -/* 4035 */ MCD_OPC_Decode, 222, 12, 125, // Opcode: SUBVI_D -/* 4039 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4051 -/* 4043 */ MCD_OPC_CheckPredicate, 8, 207, 37, // Skip to: 13726 -/* 4047 */ MCD_OPC_Decode, 157, 8, 122, // Opcode: MAXI_S_B -/* 4051 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4063 -/* 4055 */ MCD_OPC_CheckPredicate, 8, 195, 37, // Skip to: 13726 -/* 4059 */ MCD_OPC_Decode, 159, 8, 123, // Opcode: MAXI_S_H -/* 4063 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4075 -/* 4067 */ MCD_OPC_CheckPredicate, 8, 183, 37, // Skip to: 13726 -/* 4071 */ MCD_OPC_Decode, 160, 8, 124, // Opcode: MAXI_S_W -/* 4075 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4087 -/* 4079 */ MCD_OPC_CheckPredicate, 8, 171, 37, // Skip to: 13726 -/* 4083 */ MCD_OPC_Decode, 158, 8, 125, // Opcode: MAXI_S_D -/* 4087 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4099 -/* 4091 */ MCD_OPC_CheckPredicate, 8, 159, 37, // Skip to: 13726 -/* 4095 */ MCD_OPC_Decode, 161, 8, 122, // Opcode: MAXI_U_B -/* 4099 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4111 -/* 4103 */ MCD_OPC_CheckPredicate, 8, 147, 37, // Skip to: 13726 -/* 4107 */ MCD_OPC_Decode, 163, 8, 123, // Opcode: MAXI_U_H -/* 4111 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4123 -/* 4115 */ MCD_OPC_CheckPredicate, 8, 135, 37, // Skip to: 13726 -/* 4119 */ MCD_OPC_Decode, 164, 8, 124, // Opcode: MAXI_U_W -/* 4123 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4135 -/* 4127 */ MCD_OPC_CheckPredicate, 8, 123, 37, // Skip to: 13726 -/* 4131 */ MCD_OPC_Decode, 162, 8, 125, // Opcode: MAXI_U_D -/* 4135 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4147 -/* 4139 */ MCD_OPC_CheckPredicate, 8, 111, 37, // Skip to: 13726 -/* 4143 */ MCD_OPC_Decode, 198, 8, 122, // Opcode: MINI_S_B -/* 4147 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4159 -/* 4151 */ MCD_OPC_CheckPredicate, 8, 99, 37, // Skip to: 13726 -/* 4155 */ MCD_OPC_Decode, 200, 8, 123, // Opcode: MINI_S_H -/* 4159 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4171 -/* 4163 */ MCD_OPC_CheckPredicate, 8, 87, 37, // Skip to: 13726 -/* 4167 */ MCD_OPC_Decode, 201, 8, 124, // Opcode: MINI_S_W -/* 4171 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4183 -/* 4175 */ MCD_OPC_CheckPredicate, 8, 75, 37, // Skip to: 13726 -/* 4179 */ MCD_OPC_Decode, 199, 8, 125, // Opcode: MINI_S_D -/* 4183 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4195 -/* 4187 */ MCD_OPC_CheckPredicate, 8, 63, 37, // Skip to: 13726 -/* 4191 */ MCD_OPC_Decode, 202, 8, 122, // Opcode: MINI_U_B -/* 4195 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4207 -/* 4199 */ MCD_OPC_CheckPredicate, 8, 51, 37, // Skip to: 13726 -/* 4203 */ MCD_OPC_Decode, 204, 8, 123, // Opcode: MINI_U_H -/* 4207 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4219 -/* 4211 */ MCD_OPC_CheckPredicate, 8, 39, 37, // Skip to: 13726 -/* 4215 */ MCD_OPC_Decode, 205, 8, 124, // Opcode: MINI_U_W -/* 4219 */ MCD_OPC_FilterValue, 23, 31, 37, // Skip to: 13726 -/* 4223 */ MCD_OPC_CheckPredicate, 8, 27, 37, // Skip to: 13726 -/* 4227 */ MCD_OPC_Decode, 203, 8, 125, // Opcode: MINI_U_D -/* 4231 */ MCD_OPC_FilterValue, 7, 37, 1, // Skip to: 4528 -/* 4235 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 4238 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4250 -/* 4242 */ MCD_OPC_CheckPredicate, 8, 8, 37, // Skip to: 13726 -/* 4246 */ MCD_OPC_Decode, 230, 2, 122, // Opcode: CEQI_B -/* 4250 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 4262 -/* 4254 */ MCD_OPC_CheckPredicate, 8, 252, 36, // Skip to: 13726 -/* 4258 */ MCD_OPC_Decode, 232, 2, 123, // Opcode: CEQI_H -/* 4262 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 4274 -/* 4266 */ MCD_OPC_CheckPredicate, 8, 240, 36, // Skip to: 13726 -/* 4270 */ MCD_OPC_Decode, 233, 2, 124, // Opcode: CEQI_W -/* 4274 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 4286 -/* 4278 */ MCD_OPC_CheckPredicate, 8, 228, 36, // Skip to: 13726 -/* 4282 */ MCD_OPC_Decode, 231, 2, 125, // Opcode: CEQI_D -/* 4286 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4298 -/* 4290 */ MCD_OPC_CheckPredicate, 8, 216, 36, // Skip to: 13726 -/* 4294 */ MCD_OPC_Decode, 136, 3, 122, // Opcode: CLTI_S_B -/* 4298 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4310 -/* 4302 */ MCD_OPC_CheckPredicate, 8, 204, 36, // Skip to: 13726 -/* 4306 */ MCD_OPC_Decode, 138, 3, 123, // Opcode: CLTI_S_H -/* 4310 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4322 -/* 4314 */ MCD_OPC_CheckPredicate, 8, 192, 36, // Skip to: 13726 -/* 4318 */ MCD_OPC_Decode, 139, 3, 124, // Opcode: CLTI_S_W -/* 4322 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4334 -/* 4326 */ MCD_OPC_CheckPredicate, 8, 180, 36, // Skip to: 13726 -/* 4330 */ MCD_OPC_Decode, 137, 3, 125, // Opcode: CLTI_S_D -/* 4334 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4346 -/* 4338 */ MCD_OPC_CheckPredicate, 8, 168, 36, // Skip to: 13726 -/* 4342 */ MCD_OPC_Decode, 140, 3, 122, // Opcode: CLTI_U_B -/* 4346 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4358 -/* 4350 */ MCD_OPC_CheckPredicate, 8, 156, 36, // Skip to: 13726 -/* 4354 */ MCD_OPC_Decode, 142, 3, 123, // Opcode: CLTI_U_H -/* 4358 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4370 -/* 4362 */ MCD_OPC_CheckPredicate, 8, 144, 36, // Skip to: 13726 -/* 4366 */ MCD_OPC_Decode, 143, 3, 124, // Opcode: CLTI_U_W -/* 4370 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4382 -/* 4374 */ MCD_OPC_CheckPredicate, 8, 132, 36, // Skip to: 13726 -/* 4378 */ MCD_OPC_Decode, 141, 3, 125, // Opcode: CLTI_U_D -/* 4382 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4394 -/* 4386 */ MCD_OPC_CheckPredicate, 8, 120, 36, // Skip to: 13726 -/* 4390 */ MCD_OPC_Decode, 245, 2, 122, // Opcode: CLEI_S_B -/* 4394 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4406 -/* 4398 */ MCD_OPC_CheckPredicate, 8, 108, 36, // Skip to: 13726 -/* 4402 */ MCD_OPC_Decode, 247, 2, 123, // Opcode: CLEI_S_H -/* 4406 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4418 -/* 4410 */ MCD_OPC_CheckPredicate, 8, 96, 36, // Skip to: 13726 -/* 4414 */ MCD_OPC_Decode, 248, 2, 124, // Opcode: CLEI_S_W -/* 4418 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4430 -/* 4422 */ MCD_OPC_CheckPredicate, 8, 84, 36, // Skip to: 13726 -/* 4426 */ MCD_OPC_Decode, 246, 2, 125, // Opcode: CLEI_S_D -/* 4430 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4442 -/* 4434 */ MCD_OPC_CheckPredicate, 8, 72, 36, // Skip to: 13726 -/* 4438 */ MCD_OPC_Decode, 249, 2, 122, // Opcode: CLEI_U_B -/* 4442 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4454 -/* 4446 */ MCD_OPC_CheckPredicate, 8, 60, 36, // Skip to: 13726 -/* 4450 */ MCD_OPC_Decode, 251, 2, 123, // Opcode: CLEI_U_H -/* 4454 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4466 -/* 4458 */ MCD_OPC_CheckPredicate, 8, 48, 36, // Skip to: 13726 -/* 4462 */ MCD_OPC_Decode, 252, 2, 124, // Opcode: CLEI_U_W -/* 4466 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 4478 -/* 4470 */ MCD_OPC_CheckPredicate, 8, 36, 36, // Skip to: 13726 -/* 4474 */ MCD_OPC_Decode, 250, 2, 125, // Opcode: CLEI_U_D -/* 4478 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 4490 -/* 4482 */ MCD_OPC_CheckPredicate, 8, 24, 36, // Skip to: 13726 -/* 4486 */ MCD_OPC_Decode, 168, 7, 126, // Opcode: LDI_B -/* 4490 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 4502 -/* 4494 */ MCD_OPC_CheckPredicate, 8, 12, 36, // Skip to: 13726 -/* 4498 */ MCD_OPC_Decode, 170, 7, 127, // Opcode: LDI_H -/* 4502 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 4515 -/* 4506 */ MCD_OPC_CheckPredicate, 8, 0, 36, // Skip to: 13726 -/* 4510 */ MCD_OPC_Decode, 171, 7, 128, 1, // Opcode: LDI_W -/* 4515 */ MCD_OPC_FilterValue, 27, 247, 35, // Skip to: 13726 -/* 4519 */ MCD_OPC_CheckPredicate, 8, 243, 35, // Skip to: 13726 -/* 4523 */ MCD_OPC_Decode, 169, 7, 129, 1, // Opcode: LDI_D -/* 4528 */ MCD_OPC_FilterValue, 9, 61, 2, // Skip to: 5105 -/* 4532 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 4535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4548 -/* 4539 */ MCD_OPC_CheckPredicate, 8, 223, 35, // Skip to: 13726 -/* 4543 */ MCD_OPC_Decode, 230, 11, 130, 1, // Opcode: SLLI_D -/* 4548 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 4606 -/* 4552 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4555 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4567 -/* 4559 */ MCD_OPC_CheckPredicate, 8, 203, 35, // Skip to: 13726 -/* 4563 */ MCD_OPC_Decode, 232, 11, 124, // Opcode: SLLI_W -/* 4567 */ MCD_OPC_FilterValue, 1, 195, 35, // Skip to: 13726 -/* 4571 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4574 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4587 -/* 4578 */ MCD_OPC_CheckPredicate, 8, 184, 35, // Skip to: 13726 -/* 4582 */ MCD_OPC_Decode, 231, 11, 131, 1, // Opcode: SLLI_H -/* 4587 */ MCD_OPC_FilterValue, 1, 175, 35, // Skip to: 13726 -/* 4591 */ MCD_OPC_CheckPredicate, 8, 171, 35, // Skip to: 13726 -/* 4595 */ MCD_OPC_CheckField, 19, 1, 0, 165, 35, // Skip to: 13726 -/* 4601 */ MCD_OPC_Decode, 229, 11, 132, 1, // Opcode: SLLI_B -/* 4606 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4619 -/* 4610 */ MCD_OPC_CheckPredicate, 8, 152, 35, // Skip to: 13726 -/* 4614 */ MCD_OPC_Decode, 141, 12, 130, 1, // Opcode: SRAI_D -/* 4619 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 4677 -/* 4623 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4626 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4638 -/* 4630 */ MCD_OPC_CheckPredicate, 8, 132, 35, // Skip to: 13726 -/* 4634 */ MCD_OPC_Decode, 143, 12, 124, // Opcode: SRAI_W -/* 4638 */ MCD_OPC_FilterValue, 1, 124, 35, // Skip to: 13726 -/* 4642 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4645 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4658 -/* 4649 */ MCD_OPC_CheckPredicate, 8, 113, 35, // Skip to: 13726 -/* 4653 */ MCD_OPC_Decode, 142, 12, 131, 1, // Opcode: SRAI_H -/* 4658 */ MCD_OPC_FilterValue, 1, 104, 35, // Skip to: 13726 -/* 4662 */ MCD_OPC_CheckPredicate, 8, 100, 35, // Skip to: 13726 -/* 4666 */ MCD_OPC_CheckField, 19, 1, 0, 94, 35, // Skip to: 13726 -/* 4672 */ MCD_OPC_Decode, 140, 12, 132, 1, // Opcode: SRAI_B -/* 4677 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 4690 -/* 4681 */ MCD_OPC_CheckPredicate, 8, 81, 35, // Skip to: 13726 -/* 4685 */ MCD_OPC_Decode, 162, 12, 130, 1, // Opcode: SRLI_D -/* 4690 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 4748 -/* 4694 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4697 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4709 -/* 4701 */ MCD_OPC_CheckPredicate, 8, 61, 35, // Skip to: 13726 -/* 4705 */ MCD_OPC_Decode, 164, 12, 124, // Opcode: SRLI_W -/* 4709 */ MCD_OPC_FilterValue, 1, 53, 35, // Skip to: 13726 -/* 4713 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4716 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4729 -/* 4720 */ MCD_OPC_CheckPredicate, 8, 42, 35, // Skip to: 13726 -/* 4724 */ MCD_OPC_Decode, 163, 12, 131, 1, // Opcode: SRLI_H -/* 4729 */ MCD_OPC_FilterValue, 1, 33, 35, // Skip to: 13726 -/* 4733 */ MCD_OPC_CheckPredicate, 8, 29, 35, // Skip to: 13726 -/* 4737 */ MCD_OPC_CheckField, 19, 1, 0, 23, 35, // Skip to: 13726 -/* 4743 */ MCD_OPC_Decode, 161, 12, 132, 1, // Opcode: SRLI_B -/* 4748 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 4761 -/* 4752 */ MCD_OPC_CheckPredicate, 8, 10, 35, // Skip to: 13726 -/* 4756 */ MCD_OPC_Decode, 199, 1, 130, 1, // Opcode: BCLRI_D -/* 4761 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 4819 -/* 4765 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4768 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4780 -/* 4772 */ MCD_OPC_CheckPredicate, 8, 246, 34, // Skip to: 13726 -/* 4776 */ MCD_OPC_Decode, 201, 1, 124, // Opcode: BCLRI_W -/* 4780 */ MCD_OPC_FilterValue, 1, 238, 34, // Skip to: 13726 -/* 4784 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4787 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4800 -/* 4791 */ MCD_OPC_CheckPredicate, 8, 227, 34, // Skip to: 13726 -/* 4795 */ MCD_OPC_Decode, 200, 1, 131, 1, // Opcode: BCLRI_H -/* 4800 */ MCD_OPC_FilterValue, 1, 218, 34, // Skip to: 13726 -/* 4804 */ MCD_OPC_CheckPredicate, 8, 214, 34, // Skip to: 13726 -/* 4808 */ MCD_OPC_CheckField, 19, 1, 0, 208, 34, // Skip to: 13726 -/* 4814 */ MCD_OPC_Decode, 198, 1, 132, 1, // Opcode: BCLRI_B -/* 4819 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 4832 -/* 4823 */ MCD_OPC_CheckPredicate, 8, 195, 34, // Skip to: 13726 -/* 4827 */ MCD_OPC_Decode, 182, 2, 130, 1, // Opcode: BSETI_D -/* 4832 */ MCD_OPC_FilterValue, 9, 54, 0, // Skip to: 4890 -/* 4836 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4839 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4851 -/* 4843 */ MCD_OPC_CheckPredicate, 8, 175, 34, // Skip to: 13726 -/* 4847 */ MCD_OPC_Decode, 184, 2, 124, // Opcode: BSETI_W -/* 4851 */ MCD_OPC_FilterValue, 1, 167, 34, // Skip to: 13726 -/* 4855 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4858 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4871 -/* 4862 */ MCD_OPC_CheckPredicate, 8, 156, 34, // Skip to: 13726 -/* 4866 */ MCD_OPC_Decode, 183, 2, 131, 1, // Opcode: BSETI_H -/* 4871 */ MCD_OPC_FilterValue, 1, 147, 34, // Skip to: 13726 -/* 4875 */ MCD_OPC_CheckPredicate, 8, 143, 34, // Skip to: 13726 -/* 4879 */ MCD_OPC_CheckField, 19, 1, 0, 137, 34, // Skip to: 13726 -/* 4885 */ MCD_OPC_Decode, 181, 2, 132, 1, // Opcode: BSETI_B -/* 4890 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 4903 -/* 4894 */ MCD_OPC_CheckPredicate, 8, 124, 34, // Skip to: 13726 -/* 4898 */ MCD_OPC_Decode, 149, 2, 130, 1, // Opcode: BNEGI_D -/* 4903 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 4961 -/* 4907 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4910 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4922 -/* 4914 */ MCD_OPC_CheckPredicate, 8, 104, 34, // Skip to: 13726 -/* 4918 */ MCD_OPC_Decode, 151, 2, 124, // Opcode: BNEGI_W -/* 4922 */ MCD_OPC_FilterValue, 1, 96, 34, // Skip to: 13726 -/* 4926 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4929 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4942 -/* 4933 */ MCD_OPC_CheckPredicate, 8, 85, 34, // Skip to: 13726 -/* 4937 */ MCD_OPC_Decode, 150, 2, 131, 1, // Opcode: BNEGI_H -/* 4942 */ MCD_OPC_FilterValue, 1, 76, 34, // Skip to: 13726 -/* 4946 */ MCD_OPC_CheckPredicate, 8, 72, 34, // Skip to: 13726 -/* 4950 */ MCD_OPC_CheckField, 19, 1, 0, 66, 34, // Skip to: 13726 -/* 4956 */ MCD_OPC_Decode, 148, 2, 132, 1, // Opcode: BNEGI_B -/* 4961 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 4974 -/* 4965 */ MCD_OPC_CheckPredicate, 8, 53, 34, // Skip to: 13726 -/* 4969 */ MCD_OPC_Decode, 234, 1, 133, 1, // Opcode: BINSLI_D -/* 4974 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 5033 -/* 4978 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4981 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4994 -/* 4985 */ MCD_OPC_CheckPredicate, 8, 33, 34, // Skip to: 13726 -/* 4989 */ MCD_OPC_Decode, 236, 1, 134, 1, // Opcode: BINSLI_W -/* 4994 */ MCD_OPC_FilterValue, 1, 24, 34, // Skip to: 13726 -/* 4998 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5001 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5014 -/* 5005 */ MCD_OPC_CheckPredicate, 8, 13, 34, // Skip to: 13726 -/* 5009 */ MCD_OPC_Decode, 235, 1, 135, 1, // Opcode: BINSLI_H -/* 5014 */ MCD_OPC_FilterValue, 1, 4, 34, // Skip to: 13726 -/* 5018 */ MCD_OPC_CheckPredicate, 8, 0, 34, // Skip to: 13726 -/* 5022 */ MCD_OPC_CheckField, 19, 1, 0, 250, 33, // Skip to: 13726 -/* 5028 */ MCD_OPC_Decode, 233, 1, 136, 1, // Opcode: BINSLI_B -/* 5033 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5046 -/* 5037 */ MCD_OPC_CheckPredicate, 8, 237, 33, // Skip to: 13726 -/* 5041 */ MCD_OPC_Decode, 242, 1, 133, 1, // Opcode: BINSRI_D -/* 5046 */ MCD_OPC_FilterValue, 15, 228, 33, // Skip to: 13726 -/* 5050 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5053 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5066 -/* 5057 */ MCD_OPC_CheckPredicate, 8, 217, 33, // Skip to: 13726 -/* 5061 */ MCD_OPC_Decode, 244, 1, 134, 1, // Opcode: BINSRI_W -/* 5066 */ MCD_OPC_FilterValue, 1, 208, 33, // Skip to: 13726 -/* 5070 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5073 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5086 -/* 5077 */ MCD_OPC_CheckPredicate, 8, 197, 33, // Skip to: 13726 -/* 5081 */ MCD_OPC_Decode, 243, 1, 135, 1, // Opcode: BINSRI_H -/* 5086 */ MCD_OPC_FilterValue, 1, 188, 33, // Skip to: 13726 -/* 5090 */ MCD_OPC_CheckPredicate, 8, 184, 33, // Skip to: 13726 -/* 5094 */ MCD_OPC_CheckField, 19, 1, 0, 178, 33, // Skip to: 13726 -/* 5100 */ MCD_OPC_Decode, 241, 1, 136, 1, // Opcode: BINSRI_B -/* 5105 */ MCD_OPC_FilterValue, 10, 31, 1, // Skip to: 5396 -/* 5109 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5112 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5125 -/* 5116 */ MCD_OPC_CheckPredicate, 8, 158, 33, // Skip to: 13726 -/* 5120 */ MCD_OPC_Decode, 135, 11, 130, 1, // Opcode: SAT_S_D -/* 5125 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 5183 -/* 5129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5144 -/* 5136 */ MCD_OPC_CheckPredicate, 8, 138, 33, // Skip to: 13726 -/* 5140 */ MCD_OPC_Decode, 137, 11, 124, // Opcode: SAT_S_W -/* 5144 */ MCD_OPC_FilterValue, 1, 130, 33, // Skip to: 13726 -/* 5148 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5151 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5164 -/* 5155 */ MCD_OPC_CheckPredicate, 8, 119, 33, // Skip to: 13726 -/* 5159 */ MCD_OPC_Decode, 136, 11, 131, 1, // Opcode: SAT_S_H -/* 5164 */ MCD_OPC_FilterValue, 1, 110, 33, // Skip to: 13726 -/* 5168 */ MCD_OPC_CheckPredicate, 8, 106, 33, // Skip to: 13726 -/* 5172 */ MCD_OPC_CheckField, 19, 1, 0, 100, 33, // Skip to: 13726 -/* 5178 */ MCD_OPC_Decode, 134, 11, 132, 1, // Opcode: SAT_S_B -/* 5183 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5196 -/* 5187 */ MCD_OPC_CheckPredicate, 8, 87, 33, // Skip to: 13726 -/* 5191 */ MCD_OPC_Decode, 139, 11, 130, 1, // Opcode: SAT_U_D -/* 5196 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 5254 -/* 5200 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5215 -/* 5207 */ MCD_OPC_CheckPredicate, 8, 67, 33, // Skip to: 13726 -/* 5211 */ MCD_OPC_Decode, 141, 11, 124, // Opcode: SAT_U_W -/* 5215 */ MCD_OPC_FilterValue, 1, 59, 33, // Skip to: 13726 -/* 5219 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5222 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5235 -/* 5226 */ MCD_OPC_CheckPredicate, 8, 48, 33, // Skip to: 13726 -/* 5230 */ MCD_OPC_Decode, 140, 11, 131, 1, // Opcode: SAT_U_H -/* 5235 */ MCD_OPC_FilterValue, 1, 39, 33, // Skip to: 13726 -/* 5239 */ MCD_OPC_CheckPredicate, 8, 35, 33, // Skip to: 13726 -/* 5243 */ MCD_OPC_CheckField, 19, 1, 0, 29, 33, // Skip to: 13726 -/* 5249 */ MCD_OPC_Decode, 138, 11, 132, 1, // Opcode: SAT_U_B -/* 5254 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5267 -/* 5258 */ MCD_OPC_CheckPredicate, 8, 16, 33, // Skip to: 13726 -/* 5262 */ MCD_OPC_Decode, 145, 12, 130, 1, // Opcode: SRARI_D -/* 5267 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 5325 -/* 5271 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5274 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5286 -/* 5278 */ MCD_OPC_CheckPredicate, 8, 252, 32, // Skip to: 13726 -/* 5282 */ MCD_OPC_Decode, 147, 12, 124, // Opcode: SRARI_W -/* 5286 */ MCD_OPC_FilterValue, 1, 244, 32, // Skip to: 13726 -/* 5290 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5293 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5306 -/* 5297 */ MCD_OPC_CheckPredicate, 8, 233, 32, // Skip to: 13726 -/* 5301 */ MCD_OPC_Decode, 146, 12, 131, 1, // Opcode: SRARI_H -/* 5306 */ MCD_OPC_FilterValue, 1, 224, 32, // Skip to: 13726 -/* 5310 */ MCD_OPC_CheckPredicate, 8, 220, 32, // Skip to: 13726 -/* 5314 */ MCD_OPC_CheckField, 19, 1, 0, 214, 32, // Skip to: 13726 -/* 5320 */ MCD_OPC_Decode, 144, 12, 132, 1, // Opcode: SRARI_B -/* 5325 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5338 -/* 5329 */ MCD_OPC_CheckPredicate, 8, 201, 32, // Skip to: 13726 -/* 5333 */ MCD_OPC_Decode, 166, 12, 130, 1, // Opcode: SRLRI_D -/* 5338 */ MCD_OPC_FilterValue, 7, 192, 32, // Skip to: 13726 -/* 5342 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5345 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5357 -/* 5349 */ MCD_OPC_CheckPredicate, 8, 181, 32, // Skip to: 13726 -/* 5353 */ MCD_OPC_Decode, 168, 12, 124, // Opcode: SRLRI_W -/* 5357 */ MCD_OPC_FilterValue, 1, 173, 32, // Skip to: 13726 -/* 5361 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5364 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5377 -/* 5368 */ MCD_OPC_CheckPredicate, 8, 162, 32, // Skip to: 13726 -/* 5372 */ MCD_OPC_Decode, 167, 12, 131, 1, // Opcode: SRLRI_H -/* 5377 */ MCD_OPC_FilterValue, 1, 153, 32, // Skip to: 13726 -/* 5381 */ MCD_OPC_CheckPredicate, 8, 149, 32, // Skip to: 13726 -/* 5385 */ MCD_OPC_CheckField, 19, 1, 0, 143, 32, // Skip to: 13726 -/* 5391 */ MCD_OPC_Decode, 165, 12, 132, 1, // Opcode: SRLRI_B -/* 5396 */ MCD_OPC_FilterValue, 13, 163, 1, // Skip to: 5819 -/* 5400 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 5403 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5416 -/* 5407 */ MCD_OPC_CheckPredicate, 8, 123, 32, // Skip to: 13726 -/* 5411 */ MCD_OPC_Decode, 235, 11, 137, 1, // Opcode: SLL_B -/* 5416 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5429 -/* 5420 */ MCD_OPC_CheckPredicate, 8, 110, 32, // Skip to: 13726 -/* 5424 */ MCD_OPC_Decode, 237, 11, 138, 1, // Opcode: SLL_H -/* 5429 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5442 -/* 5433 */ MCD_OPC_CheckPredicate, 8, 97, 32, // Skip to: 13726 -/* 5437 */ MCD_OPC_Decode, 239, 11, 139, 1, // Opcode: SLL_W -/* 5442 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5455 -/* 5446 */ MCD_OPC_CheckPredicate, 8, 84, 32, // Skip to: 13726 -/* 5450 */ MCD_OPC_Decode, 236, 11, 140, 1, // Opcode: SLL_D -/* 5455 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5468 -/* 5459 */ MCD_OPC_CheckPredicate, 8, 71, 32, // Skip to: 13726 -/* 5463 */ MCD_OPC_Decode, 154, 12, 137, 1, // Opcode: SRA_B -/* 5468 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5481 -/* 5472 */ MCD_OPC_CheckPredicate, 8, 58, 32, // Skip to: 13726 -/* 5476 */ MCD_OPC_Decode, 156, 12, 138, 1, // Opcode: SRA_H -/* 5481 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5494 -/* 5485 */ MCD_OPC_CheckPredicate, 8, 45, 32, // Skip to: 13726 -/* 5489 */ MCD_OPC_Decode, 158, 12, 139, 1, // Opcode: SRA_W -/* 5494 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5507 -/* 5498 */ MCD_OPC_CheckPredicate, 8, 32, 32, // Skip to: 13726 -/* 5502 */ MCD_OPC_Decode, 155, 12, 140, 1, // Opcode: SRA_D -/* 5507 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5520 -/* 5511 */ MCD_OPC_CheckPredicate, 8, 19, 32, // Skip to: 13726 -/* 5515 */ MCD_OPC_Decode, 175, 12, 137, 1, // Opcode: SRL_B -/* 5520 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5533 -/* 5524 */ MCD_OPC_CheckPredicate, 8, 6, 32, // Skip to: 13726 -/* 5528 */ MCD_OPC_Decode, 177, 12, 138, 1, // Opcode: SRL_H -/* 5533 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5546 -/* 5537 */ MCD_OPC_CheckPredicate, 8, 249, 31, // Skip to: 13726 -/* 5541 */ MCD_OPC_Decode, 179, 12, 139, 1, // Opcode: SRL_W -/* 5546 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5559 -/* 5550 */ MCD_OPC_CheckPredicate, 8, 236, 31, // Skip to: 13726 -/* 5554 */ MCD_OPC_Decode, 176, 12, 140, 1, // Opcode: SRL_D -/* 5559 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5572 -/* 5563 */ MCD_OPC_CheckPredicate, 8, 223, 31, // Skip to: 13726 -/* 5567 */ MCD_OPC_Decode, 202, 1, 137, 1, // Opcode: BCLR_B -/* 5572 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5585 -/* 5576 */ MCD_OPC_CheckPredicate, 8, 210, 31, // Skip to: 13726 -/* 5580 */ MCD_OPC_Decode, 204, 1, 138, 1, // Opcode: BCLR_H -/* 5585 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5598 -/* 5589 */ MCD_OPC_CheckPredicate, 8, 197, 31, // Skip to: 13726 -/* 5593 */ MCD_OPC_Decode, 205, 1, 139, 1, // Opcode: BCLR_W -/* 5598 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5611 -/* 5602 */ MCD_OPC_CheckPredicate, 8, 184, 31, // Skip to: 13726 -/* 5606 */ MCD_OPC_Decode, 203, 1, 140, 1, // Opcode: BCLR_D -/* 5611 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 5624 -/* 5615 */ MCD_OPC_CheckPredicate, 8, 171, 31, // Skip to: 13726 -/* 5619 */ MCD_OPC_Decode, 185, 2, 137, 1, // Opcode: BSET_B -/* 5624 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 5637 -/* 5628 */ MCD_OPC_CheckPredicate, 8, 158, 31, // Skip to: 13726 -/* 5632 */ MCD_OPC_Decode, 187, 2, 138, 1, // Opcode: BSET_H -/* 5637 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 5650 -/* 5641 */ MCD_OPC_CheckPredicate, 8, 145, 31, // Skip to: 13726 -/* 5645 */ MCD_OPC_Decode, 188, 2, 139, 1, // Opcode: BSET_W -/* 5650 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 5663 -/* 5654 */ MCD_OPC_CheckPredicate, 8, 132, 31, // Skip to: 13726 -/* 5658 */ MCD_OPC_Decode, 186, 2, 140, 1, // Opcode: BSET_D -/* 5663 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 5676 -/* 5667 */ MCD_OPC_CheckPredicate, 8, 119, 31, // Skip to: 13726 -/* 5671 */ MCD_OPC_Decode, 152, 2, 137, 1, // Opcode: BNEG_B -/* 5676 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 5689 -/* 5680 */ MCD_OPC_CheckPredicate, 8, 106, 31, // Skip to: 13726 -/* 5684 */ MCD_OPC_Decode, 154, 2, 138, 1, // Opcode: BNEG_H -/* 5689 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 5702 -/* 5693 */ MCD_OPC_CheckPredicate, 8, 93, 31, // Skip to: 13726 -/* 5697 */ MCD_OPC_Decode, 155, 2, 139, 1, // Opcode: BNEG_W -/* 5702 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 5715 -/* 5706 */ MCD_OPC_CheckPredicate, 8, 80, 31, // Skip to: 13726 -/* 5710 */ MCD_OPC_Decode, 153, 2, 140, 1, // Opcode: BNEG_D -/* 5715 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 5728 -/* 5719 */ MCD_OPC_CheckPredicate, 8, 67, 31, // Skip to: 13726 -/* 5723 */ MCD_OPC_Decode, 237, 1, 141, 1, // Opcode: BINSL_B -/* 5728 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 5741 -/* 5732 */ MCD_OPC_CheckPredicate, 8, 54, 31, // Skip to: 13726 -/* 5736 */ MCD_OPC_Decode, 239, 1, 142, 1, // Opcode: BINSL_H -/* 5741 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 5754 -/* 5745 */ MCD_OPC_CheckPredicate, 8, 41, 31, // Skip to: 13726 -/* 5749 */ MCD_OPC_Decode, 240, 1, 143, 1, // Opcode: BINSL_W -/* 5754 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 5767 -/* 5758 */ MCD_OPC_CheckPredicate, 8, 28, 31, // Skip to: 13726 -/* 5762 */ MCD_OPC_Decode, 238, 1, 144, 1, // Opcode: BINSL_D -/* 5767 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 5780 -/* 5771 */ MCD_OPC_CheckPredicate, 8, 15, 31, // Skip to: 13726 -/* 5775 */ MCD_OPC_Decode, 245, 1, 141, 1, // Opcode: BINSR_B -/* 5780 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 5793 -/* 5784 */ MCD_OPC_CheckPredicate, 8, 2, 31, // Skip to: 13726 -/* 5788 */ MCD_OPC_Decode, 247, 1, 142, 1, // Opcode: BINSR_H -/* 5793 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 5806 -/* 5797 */ MCD_OPC_CheckPredicate, 8, 245, 30, // Skip to: 13726 -/* 5801 */ MCD_OPC_Decode, 248, 1, 143, 1, // Opcode: BINSR_W -/* 5806 */ MCD_OPC_FilterValue, 31, 236, 30, // Skip to: 13726 -/* 5810 */ MCD_OPC_CheckPredicate, 8, 232, 30, // Skip to: 13726 -/* 5814 */ MCD_OPC_Decode, 246, 1, 144, 1, // Opcode: BINSR_D -/* 5819 */ MCD_OPC_FilterValue, 14, 159, 1, // Skip to: 6238 -/* 5823 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 5826 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5838 -/* 5830 */ MCD_OPC_CheckPredicate, 8, 212, 30, // Skip to: 13726 -/* 5834 */ MCD_OPC_Decode, 63, 137, 1, // Opcode: ADDV_B -/* 5838 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5850 -/* 5842 */ MCD_OPC_CheckPredicate, 8, 200, 30, // Skip to: 13726 -/* 5846 */ MCD_OPC_Decode, 65, 138, 1, // Opcode: ADDV_H -/* 5850 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5862 -/* 5854 */ MCD_OPC_CheckPredicate, 8, 188, 30, // Skip to: 13726 -/* 5858 */ MCD_OPC_Decode, 66, 139, 1, // Opcode: ADDV_W -/* 5862 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 5874 -/* 5866 */ MCD_OPC_CheckPredicate, 8, 176, 30, // Skip to: 13726 -/* 5870 */ MCD_OPC_Decode, 64, 140, 1, // Opcode: ADDV_D -/* 5874 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5887 -/* 5878 */ MCD_OPC_CheckPredicate, 8, 164, 30, // Skip to: 13726 -/* 5882 */ MCD_OPC_Decode, 225, 12, 137, 1, // Opcode: SUBV_B -/* 5887 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5900 -/* 5891 */ MCD_OPC_CheckPredicate, 8, 151, 30, // Skip to: 13726 -/* 5895 */ MCD_OPC_Decode, 227, 12, 138, 1, // Opcode: SUBV_H -/* 5900 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5913 -/* 5904 */ MCD_OPC_CheckPredicate, 8, 138, 30, // Skip to: 13726 -/* 5908 */ MCD_OPC_Decode, 228, 12, 139, 1, // Opcode: SUBV_W -/* 5913 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5926 -/* 5917 */ MCD_OPC_CheckPredicate, 8, 125, 30, // Skip to: 13726 -/* 5921 */ MCD_OPC_Decode, 226, 12, 140, 1, // Opcode: SUBV_D -/* 5926 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5939 -/* 5930 */ MCD_OPC_CheckPredicate, 8, 112, 30, // Skip to: 13726 -/* 5934 */ MCD_OPC_Decode, 171, 8, 137, 1, // Opcode: MAX_S_B -/* 5939 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5952 -/* 5943 */ MCD_OPC_CheckPredicate, 8, 99, 30, // Skip to: 13726 -/* 5947 */ MCD_OPC_Decode, 173, 8, 138, 1, // Opcode: MAX_S_H -/* 5952 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5965 -/* 5956 */ MCD_OPC_CheckPredicate, 8, 86, 30, // Skip to: 13726 -/* 5960 */ MCD_OPC_Decode, 174, 8, 139, 1, // Opcode: MAX_S_W -/* 5965 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5978 -/* 5969 */ MCD_OPC_CheckPredicate, 8, 73, 30, // Skip to: 13726 -/* 5973 */ MCD_OPC_Decode, 172, 8, 140, 1, // Opcode: MAX_S_D -/* 5978 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5991 -/* 5982 */ MCD_OPC_CheckPredicate, 8, 60, 30, // Skip to: 13726 -/* 5986 */ MCD_OPC_Decode, 175, 8, 137, 1, // Opcode: MAX_U_B -/* 5991 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6004 -/* 5995 */ MCD_OPC_CheckPredicate, 8, 47, 30, // Skip to: 13726 -/* 5999 */ MCD_OPC_Decode, 177, 8, 138, 1, // Opcode: MAX_U_H -/* 6004 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6017 -/* 6008 */ MCD_OPC_CheckPredicate, 8, 34, 30, // Skip to: 13726 -/* 6012 */ MCD_OPC_Decode, 178, 8, 139, 1, // Opcode: MAX_U_W -/* 6017 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6030 -/* 6021 */ MCD_OPC_CheckPredicate, 8, 21, 30, // Skip to: 13726 -/* 6025 */ MCD_OPC_Decode, 176, 8, 140, 1, // Opcode: MAX_U_D -/* 6030 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6043 -/* 6034 */ MCD_OPC_CheckPredicate, 8, 8, 30, // Skip to: 13726 -/* 6038 */ MCD_OPC_Decode, 212, 8, 137, 1, // Opcode: MIN_S_B -/* 6043 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6056 -/* 6047 */ MCD_OPC_CheckPredicate, 8, 251, 29, // Skip to: 13726 -/* 6051 */ MCD_OPC_Decode, 214, 8, 138, 1, // Opcode: MIN_S_H -/* 6056 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6069 -/* 6060 */ MCD_OPC_CheckPredicate, 8, 238, 29, // Skip to: 13726 -/* 6064 */ MCD_OPC_Decode, 215, 8, 139, 1, // Opcode: MIN_S_W -/* 6069 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6082 -/* 6073 */ MCD_OPC_CheckPredicate, 8, 225, 29, // Skip to: 13726 -/* 6077 */ MCD_OPC_Decode, 213, 8, 140, 1, // Opcode: MIN_S_D -/* 6082 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6095 -/* 6086 */ MCD_OPC_CheckPredicate, 8, 212, 29, // Skip to: 13726 -/* 6090 */ MCD_OPC_Decode, 216, 8, 137, 1, // Opcode: MIN_U_B -/* 6095 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6108 -/* 6099 */ MCD_OPC_CheckPredicate, 8, 199, 29, // Skip to: 13726 -/* 6103 */ MCD_OPC_Decode, 218, 8, 138, 1, // Opcode: MIN_U_H -/* 6108 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6121 -/* 6112 */ MCD_OPC_CheckPredicate, 8, 186, 29, // Skip to: 13726 -/* 6116 */ MCD_OPC_Decode, 219, 8, 139, 1, // Opcode: MIN_U_W -/* 6121 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6134 -/* 6125 */ MCD_OPC_CheckPredicate, 8, 173, 29, // Skip to: 13726 -/* 6129 */ MCD_OPC_Decode, 217, 8, 140, 1, // Opcode: MIN_U_D -/* 6134 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6147 -/* 6138 */ MCD_OPC_CheckPredicate, 8, 160, 29, // Skip to: 13726 -/* 6142 */ MCD_OPC_Decode, 165, 8, 137, 1, // Opcode: MAX_A_B -/* 6147 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6160 -/* 6151 */ MCD_OPC_CheckPredicate, 8, 147, 29, // Skip to: 13726 -/* 6155 */ MCD_OPC_Decode, 167, 8, 138, 1, // Opcode: MAX_A_H -/* 6160 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6173 -/* 6164 */ MCD_OPC_CheckPredicate, 8, 134, 29, // Skip to: 13726 -/* 6168 */ MCD_OPC_Decode, 168, 8, 139, 1, // Opcode: MAX_A_W -/* 6173 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6186 -/* 6177 */ MCD_OPC_CheckPredicate, 8, 121, 29, // Skip to: 13726 -/* 6181 */ MCD_OPC_Decode, 166, 8, 140, 1, // Opcode: MAX_A_D -/* 6186 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6199 -/* 6190 */ MCD_OPC_CheckPredicate, 8, 108, 29, // Skip to: 13726 -/* 6194 */ MCD_OPC_Decode, 206, 8, 137, 1, // Opcode: MIN_A_B -/* 6199 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6212 -/* 6203 */ MCD_OPC_CheckPredicate, 8, 95, 29, // Skip to: 13726 -/* 6207 */ MCD_OPC_Decode, 208, 8, 138, 1, // Opcode: MIN_A_H -/* 6212 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6225 -/* 6216 */ MCD_OPC_CheckPredicate, 8, 82, 29, // Skip to: 13726 -/* 6220 */ MCD_OPC_Decode, 209, 8, 139, 1, // Opcode: MIN_A_W -/* 6225 */ MCD_OPC_FilterValue, 31, 73, 29, // Skip to: 13726 -/* 6229 */ MCD_OPC_CheckPredicate, 8, 69, 29, // Skip to: 13726 -/* 6233 */ MCD_OPC_Decode, 207, 8, 140, 1, // Opcode: MIN_A_D -/* 6238 */ MCD_OPC_FilterValue, 15, 7, 1, // Skip to: 6505 -/* 6242 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 6245 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6258 -/* 6249 */ MCD_OPC_CheckPredicate, 8, 49, 29, // Skip to: 13726 -/* 6253 */ MCD_OPC_Decode, 234, 2, 137, 1, // Opcode: CEQ_B -/* 6258 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6271 -/* 6262 */ MCD_OPC_CheckPredicate, 8, 36, 29, // Skip to: 13726 -/* 6266 */ MCD_OPC_Decode, 236, 2, 138, 1, // Opcode: CEQ_H -/* 6271 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6284 -/* 6275 */ MCD_OPC_CheckPredicate, 8, 23, 29, // Skip to: 13726 -/* 6279 */ MCD_OPC_Decode, 237, 2, 139, 1, // Opcode: CEQ_W -/* 6284 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6297 -/* 6288 */ MCD_OPC_CheckPredicate, 8, 10, 29, // Skip to: 13726 -/* 6292 */ MCD_OPC_Decode, 235, 2, 140, 1, // Opcode: CEQ_D -/* 6297 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 6310 -/* 6301 */ MCD_OPC_CheckPredicate, 8, 253, 28, // Skip to: 13726 -/* 6305 */ MCD_OPC_Decode, 144, 3, 137, 1, // Opcode: CLT_S_B -/* 6310 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 6323 -/* 6314 */ MCD_OPC_CheckPredicate, 8, 240, 28, // Skip to: 13726 -/* 6318 */ MCD_OPC_Decode, 146, 3, 138, 1, // Opcode: CLT_S_H -/* 6323 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 6336 -/* 6327 */ MCD_OPC_CheckPredicate, 8, 227, 28, // Skip to: 13726 -/* 6331 */ MCD_OPC_Decode, 147, 3, 139, 1, // Opcode: CLT_S_W -/* 6336 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 6349 -/* 6340 */ MCD_OPC_CheckPredicate, 8, 214, 28, // Skip to: 13726 -/* 6344 */ MCD_OPC_Decode, 145, 3, 140, 1, // Opcode: CLT_S_D -/* 6349 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 6362 -/* 6353 */ MCD_OPC_CheckPredicate, 8, 201, 28, // Skip to: 13726 -/* 6357 */ MCD_OPC_Decode, 148, 3, 137, 1, // Opcode: CLT_U_B -/* 6362 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6375 -/* 6366 */ MCD_OPC_CheckPredicate, 8, 188, 28, // Skip to: 13726 -/* 6370 */ MCD_OPC_Decode, 150, 3, 138, 1, // Opcode: CLT_U_H -/* 6375 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6388 -/* 6379 */ MCD_OPC_CheckPredicate, 8, 175, 28, // Skip to: 13726 -/* 6383 */ MCD_OPC_Decode, 151, 3, 139, 1, // Opcode: CLT_U_W -/* 6388 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6401 -/* 6392 */ MCD_OPC_CheckPredicate, 8, 162, 28, // Skip to: 13726 -/* 6396 */ MCD_OPC_Decode, 149, 3, 140, 1, // Opcode: CLT_U_D -/* 6401 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6414 -/* 6405 */ MCD_OPC_CheckPredicate, 8, 149, 28, // Skip to: 13726 -/* 6409 */ MCD_OPC_Decode, 253, 2, 137, 1, // Opcode: CLE_S_B -/* 6414 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6427 -/* 6418 */ MCD_OPC_CheckPredicate, 8, 136, 28, // Skip to: 13726 -/* 6422 */ MCD_OPC_Decode, 255, 2, 138, 1, // Opcode: CLE_S_H -/* 6427 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6440 -/* 6431 */ MCD_OPC_CheckPredicate, 8, 123, 28, // Skip to: 13726 -/* 6435 */ MCD_OPC_Decode, 128, 3, 139, 1, // Opcode: CLE_S_W -/* 6440 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6453 -/* 6444 */ MCD_OPC_CheckPredicate, 8, 110, 28, // Skip to: 13726 -/* 6448 */ MCD_OPC_Decode, 254, 2, 140, 1, // Opcode: CLE_S_D -/* 6453 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6466 -/* 6457 */ MCD_OPC_CheckPredicate, 8, 97, 28, // Skip to: 13726 -/* 6461 */ MCD_OPC_Decode, 129, 3, 137, 1, // Opcode: CLE_U_B -/* 6466 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6479 -/* 6470 */ MCD_OPC_CheckPredicate, 8, 84, 28, // Skip to: 13726 -/* 6474 */ MCD_OPC_Decode, 131, 3, 138, 1, // Opcode: CLE_U_H -/* 6479 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6492 -/* 6483 */ MCD_OPC_CheckPredicate, 8, 71, 28, // Skip to: 13726 -/* 6487 */ MCD_OPC_Decode, 132, 3, 139, 1, // Opcode: CLE_U_W -/* 6492 */ MCD_OPC_FilterValue, 23, 62, 28, // Skip to: 13726 -/* 6496 */ MCD_OPC_CheckPredicate, 8, 58, 28, // Skip to: 13726 -/* 6500 */ MCD_OPC_Decode, 130, 3, 140, 1, // Opcode: CLE_U_D -/* 6505 */ MCD_OPC_FilterValue, 16, 147, 1, // Skip to: 6912 -/* 6509 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 6512 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6524 -/* 6516 */ MCD_OPC_CheckPredicate, 8, 38, 28, // Skip to: 13726 -/* 6520 */ MCD_OPC_Decode, 68, 137, 1, // Opcode: ADD_A_B -/* 6524 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6536 -/* 6528 */ MCD_OPC_CheckPredicate, 8, 26, 28, // Skip to: 13726 -/* 6532 */ MCD_OPC_Decode, 70, 138, 1, // Opcode: ADD_A_H -/* 6536 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6548 -/* 6540 */ MCD_OPC_CheckPredicate, 8, 14, 28, // Skip to: 13726 -/* 6544 */ MCD_OPC_Decode, 71, 139, 1, // Opcode: ADD_A_W -/* 6548 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6560 -/* 6552 */ MCD_OPC_CheckPredicate, 8, 2, 28, // Skip to: 13726 -/* 6556 */ MCD_OPC_Decode, 69, 140, 1, // Opcode: ADD_A_D -/* 6560 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 6572 -/* 6564 */ MCD_OPC_CheckPredicate, 8, 246, 27, // Skip to: 13726 -/* 6568 */ MCD_OPC_Decode, 40, 137, 1, // Opcode: ADDS_A_B -/* 6572 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6584 -/* 6576 */ MCD_OPC_CheckPredicate, 8, 234, 27, // Skip to: 13726 -/* 6580 */ MCD_OPC_Decode, 42, 138, 1, // Opcode: ADDS_A_H -/* 6584 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6596 -/* 6588 */ MCD_OPC_CheckPredicate, 8, 222, 27, // Skip to: 13726 -/* 6592 */ MCD_OPC_Decode, 43, 139, 1, // Opcode: ADDS_A_W -/* 6596 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 6608 -/* 6600 */ MCD_OPC_CheckPredicate, 8, 210, 27, // Skip to: 13726 -/* 6604 */ MCD_OPC_Decode, 41, 140, 1, // Opcode: ADDS_A_D -/* 6608 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6620 -/* 6612 */ MCD_OPC_CheckPredicate, 8, 198, 27, // Skip to: 13726 -/* 6616 */ MCD_OPC_Decode, 44, 137, 1, // Opcode: ADDS_S_B -/* 6620 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6632 -/* 6624 */ MCD_OPC_CheckPredicate, 8, 186, 27, // Skip to: 13726 -/* 6628 */ MCD_OPC_Decode, 46, 138, 1, // Opcode: ADDS_S_H -/* 6632 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6644 -/* 6636 */ MCD_OPC_CheckPredicate, 8, 174, 27, // Skip to: 13726 -/* 6640 */ MCD_OPC_Decode, 47, 139, 1, // Opcode: ADDS_S_W -/* 6644 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 6656 -/* 6648 */ MCD_OPC_CheckPredicate, 8, 162, 27, // Skip to: 13726 -/* 6652 */ MCD_OPC_Decode, 45, 140, 1, // Opcode: ADDS_S_D -/* 6656 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 6668 -/* 6660 */ MCD_OPC_CheckPredicate, 8, 150, 27, // Skip to: 13726 -/* 6664 */ MCD_OPC_Decode, 48, 137, 1, // Opcode: ADDS_U_B -/* 6668 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6680 -/* 6672 */ MCD_OPC_CheckPredicate, 8, 138, 27, // Skip to: 13726 -/* 6676 */ MCD_OPC_Decode, 50, 138, 1, // Opcode: ADDS_U_H -/* 6680 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 6692 -/* 6684 */ MCD_OPC_CheckPredicate, 8, 126, 27, // Skip to: 13726 -/* 6688 */ MCD_OPC_Decode, 51, 139, 1, // Opcode: ADDS_U_W -/* 6692 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 6704 -/* 6696 */ MCD_OPC_CheckPredicate, 8, 114, 27, // Skip to: 13726 -/* 6700 */ MCD_OPC_Decode, 49, 140, 1, // Opcode: ADDS_U_D -/* 6704 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6717 -/* 6708 */ MCD_OPC_CheckPredicate, 8, 102, 27, // Skip to: 13726 -/* 6712 */ MCD_OPC_Decode, 147, 1, 137, 1, // Opcode: AVE_S_B -/* 6717 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6730 -/* 6721 */ MCD_OPC_CheckPredicate, 8, 89, 27, // Skip to: 13726 -/* 6725 */ MCD_OPC_Decode, 149, 1, 138, 1, // Opcode: AVE_S_H -/* 6730 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6743 -/* 6734 */ MCD_OPC_CheckPredicate, 8, 76, 27, // Skip to: 13726 -/* 6738 */ MCD_OPC_Decode, 150, 1, 139, 1, // Opcode: AVE_S_W -/* 6743 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6756 -/* 6747 */ MCD_OPC_CheckPredicate, 8, 63, 27, // Skip to: 13726 -/* 6751 */ MCD_OPC_Decode, 148, 1, 140, 1, // Opcode: AVE_S_D -/* 6756 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6769 -/* 6760 */ MCD_OPC_CheckPredicate, 8, 50, 27, // Skip to: 13726 -/* 6764 */ MCD_OPC_Decode, 151, 1, 137, 1, // Opcode: AVE_U_B -/* 6769 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6782 -/* 6773 */ MCD_OPC_CheckPredicate, 8, 37, 27, // Skip to: 13726 -/* 6777 */ MCD_OPC_Decode, 153, 1, 138, 1, // Opcode: AVE_U_H -/* 6782 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6795 -/* 6786 */ MCD_OPC_CheckPredicate, 8, 24, 27, // Skip to: 13726 -/* 6790 */ MCD_OPC_Decode, 154, 1, 139, 1, // Opcode: AVE_U_W -/* 6795 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6808 -/* 6799 */ MCD_OPC_CheckPredicate, 8, 11, 27, // Skip to: 13726 -/* 6803 */ MCD_OPC_Decode, 152, 1, 140, 1, // Opcode: AVE_U_D -/* 6808 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6821 -/* 6812 */ MCD_OPC_CheckPredicate, 8, 254, 26, // Skip to: 13726 -/* 6816 */ MCD_OPC_Decode, 139, 1, 137, 1, // Opcode: AVER_S_B -/* 6821 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6834 -/* 6825 */ MCD_OPC_CheckPredicate, 8, 241, 26, // Skip to: 13726 -/* 6829 */ MCD_OPC_Decode, 141, 1, 138, 1, // Opcode: AVER_S_H -/* 6834 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6847 -/* 6838 */ MCD_OPC_CheckPredicate, 8, 228, 26, // Skip to: 13726 -/* 6842 */ MCD_OPC_Decode, 142, 1, 139, 1, // Opcode: AVER_S_W -/* 6847 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6860 -/* 6851 */ MCD_OPC_CheckPredicate, 8, 215, 26, // Skip to: 13726 -/* 6855 */ MCD_OPC_Decode, 140, 1, 140, 1, // Opcode: AVER_S_D -/* 6860 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6873 -/* 6864 */ MCD_OPC_CheckPredicate, 8, 202, 26, // Skip to: 13726 -/* 6868 */ MCD_OPC_Decode, 143, 1, 137, 1, // Opcode: AVER_U_B -/* 6873 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6886 -/* 6877 */ MCD_OPC_CheckPredicate, 8, 189, 26, // Skip to: 13726 -/* 6881 */ MCD_OPC_Decode, 145, 1, 138, 1, // Opcode: AVER_U_H -/* 6886 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6899 -/* 6890 */ MCD_OPC_CheckPredicate, 8, 176, 26, // Skip to: 13726 -/* 6894 */ MCD_OPC_Decode, 146, 1, 139, 1, // Opcode: AVER_U_W -/* 6899 */ MCD_OPC_FilterValue, 31, 167, 26, // Skip to: 13726 -/* 6903 */ MCD_OPC_CheckPredicate, 8, 163, 26, // Skip to: 13726 -/* 6907 */ MCD_OPC_Decode, 144, 1, 140, 1, // Opcode: AVER_U_D -/* 6912 */ MCD_OPC_FilterValue, 17, 51, 1, // Skip to: 7223 -/* 6916 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 6919 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6932 -/* 6923 */ MCD_OPC_CheckPredicate, 8, 143, 26, // Skip to: 13726 -/* 6927 */ MCD_OPC_Decode, 206, 12, 137, 1, // Opcode: SUBS_S_B -/* 6932 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6945 -/* 6936 */ MCD_OPC_CheckPredicate, 8, 130, 26, // Skip to: 13726 -/* 6940 */ MCD_OPC_Decode, 208, 12, 138, 1, // Opcode: SUBS_S_H -/* 6945 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6958 -/* 6949 */ MCD_OPC_CheckPredicate, 8, 117, 26, // Skip to: 13726 -/* 6953 */ MCD_OPC_Decode, 209, 12, 139, 1, // Opcode: SUBS_S_W -/* 6958 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6971 -/* 6962 */ MCD_OPC_CheckPredicate, 8, 104, 26, // Skip to: 13726 -/* 6966 */ MCD_OPC_Decode, 207, 12, 140, 1, // Opcode: SUBS_S_D -/* 6971 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 6984 -/* 6975 */ MCD_OPC_CheckPredicate, 8, 91, 26, // Skip to: 13726 -/* 6979 */ MCD_OPC_Decode, 210, 12, 137, 1, // Opcode: SUBS_U_B -/* 6984 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 6997 -/* 6988 */ MCD_OPC_CheckPredicate, 8, 78, 26, // Skip to: 13726 -/* 6992 */ MCD_OPC_Decode, 212, 12, 138, 1, // Opcode: SUBS_U_H -/* 6997 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7010 -/* 7001 */ MCD_OPC_CheckPredicate, 8, 65, 26, // Skip to: 13726 -/* 7005 */ MCD_OPC_Decode, 213, 12, 139, 1, // Opcode: SUBS_U_W -/* 7010 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7023 -/* 7014 */ MCD_OPC_CheckPredicate, 8, 52, 26, // Skip to: 13726 -/* 7018 */ MCD_OPC_Decode, 211, 12, 140, 1, // Opcode: SUBS_U_D -/* 7023 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7036 -/* 7027 */ MCD_OPC_CheckPredicate, 8, 39, 26, // Skip to: 13726 -/* 7031 */ MCD_OPC_Decode, 198, 12, 137, 1, // Opcode: SUBSUS_U_B -/* 7036 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7049 -/* 7040 */ MCD_OPC_CheckPredicate, 8, 26, 26, // Skip to: 13726 -/* 7044 */ MCD_OPC_Decode, 200, 12, 138, 1, // Opcode: SUBSUS_U_H -/* 7049 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7062 -/* 7053 */ MCD_OPC_CheckPredicate, 8, 13, 26, // Skip to: 13726 -/* 7057 */ MCD_OPC_Decode, 201, 12, 139, 1, // Opcode: SUBSUS_U_W -/* 7062 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7075 -/* 7066 */ MCD_OPC_CheckPredicate, 8, 0, 26, // Skip to: 13726 -/* 7070 */ MCD_OPC_Decode, 199, 12, 140, 1, // Opcode: SUBSUS_U_D -/* 7075 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7088 -/* 7079 */ MCD_OPC_CheckPredicate, 8, 243, 25, // Skip to: 13726 -/* 7083 */ MCD_OPC_Decode, 202, 12, 137, 1, // Opcode: SUBSUU_S_B -/* 7088 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7101 -/* 7092 */ MCD_OPC_CheckPredicate, 8, 230, 25, // Skip to: 13726 -/* 7096 */ MCD_OPC_Decode, 204, 12, 138, 1, // Opcode: SUBSUU_S_H -/* 7101 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7114 -/* 7105 */ MCD_OPC_CheckPredicate, 8, 217, 25, // Skip to: 13726 -/* 7109 */ MCD_OPC_Decode, 205, 12, 139, 1, // Opcode: SUBSUU_S_W -/* 7114 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7127 -/* 7118 */ MCD_OPC_CheckPredicate, 8, 204, 25, // Skip to: 13726 -/* 7122 */ MCD_OPC_Decode, 203, 12, 140, 1, // Opcode: SUBSUU_S_D -/* 7127 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 7139 -/* 7131 */ MCD_OPC_CheckPredicate, 8, 191, 25, // Skip to: 13726 -/* 7135 */ MCD_OPC_Decode, 97, 137, 1, // Opcode: ASUB_S_B -/* 7139 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 7151 -/* 7143 */ MCD_OPC_CheckPredicate, 8, 179, 25, // Skip to: 13726 -/* 7147 */ MCD_OPC_Decode, 99, 138, 1, // Opcode: ASUB_S_H -/* 7151 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 7163 -/* 7155 */ MCD_OPC_CheckPredicate, 8, 167, 25, // Skip to: 13726 -/* 7159 */ MCD_OPC_Decode, 100, 139, 1, // Opcode: ASUB_S_W -/* 7163 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 7175 -/* 7167 */ MCD_OPC_CheckPredicate, 8, 155, 25, // Skip to: 13726 -/* 7171 */ MCD_OPC_Decode, 98, 140, 1, // Opcode: ASUB_S_D -/* 7175 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 7187 -/* 7179 */ MCD_OPC_CheckPredicate, 8, 143, 25, // Skip to: 13726 -/* 7183 */ MCD_OPC_Decode, 101, 137, 1, // Opcode: ASUB_U_B -/* 7187 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 7199 -/* 7191 */ MCD_OPC_CheckPredicate, 8, 131, 25, // Skip to: 13726 -/* 7195 */ MCD_OPC_Decode, 103, 138, 1, // Opcode: ASUB_U_H -/* 7199 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 7211 -/* 7203 */ MCD_OPC_CheckPredicate, 8, 119, 25, // Skip to: 13726 -/* 7207 */ MCD_OPC_Decode, 104, 139, 1, // Opcode: ASUB_U_W -/* 7211 */ MCD_OPC_FilterValue, 23, 111, 25, // Skip to: 13726 -/* 7215 */ MCD_OPC_CheckPredicate, 8, 107, 25, // Skip to: 13726 -/* 7219 */ MCD_OPC_Decode, 102, 140, 1, // Opcode: ASUB_U_D -/* 7223 */ MCD_OPC_FilterValue, 18, 111, 1, // Skip to: 7594 -/* 7227 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 7230 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7243 -/* 7234 */ MCD_OPC_CheckPredicate, 8, 88, 25, // Skip to: 13726 -/* 7238 */ MCD_OPC_Decode, 213, 9, 137, 1, // Opcode: MULV_B -/* 7243 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7256 -/* 7247 */ MCD_OPC_CheckPredicate, 8, 75, 25, // Skip to: 13726 -/* 7251 */ MCD_OPC_Decode, 215, 9, 138, 1, // Opcode: MULV_H -/* 7256 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7269 -/* 7260 */ MCD_OPC_CheckPredicate, 8, 62, 25, // Skip to: 13726 -/* 7264 */ MCD_OPC_Decode, 216, 9, 139, 1, // Opcode: MULV_W -/* 7269 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7282 -/* 7273 */ MCD_OPC_CheckPredicate, 8, 49, 25, // Skip to: 13726 -/* 7277 */ MCD_OPC_Decode, 214, 9, 140, 1, // Opcode: MULV_D -/* 7282 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7295 -/* 7286 */ MCD_OPC_CheckPredicate, 8, 36, 25, // Skip to: 13726 -/* 7290 */ MCD_OPC_Decode, 138, 8, 141, 1, // Opcode: MADDV_B -/* 7295 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7308 -/* 7299 */ MCD_OPC_CheckPredicate, 8, 23, 25, // Skip to: 13726 -/* 7303 */ MCD_OPC_Decode, 140, 8, 142, 1, // Opcode: MADDV_H -/* 7308 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7321 -/* 7312 */ MCD_OPC_CheckPredicate, 8, 10, 25, // Skip to: 13726 -/* 7316 */ MCD_OPC_Decode, 141, 8, 143, 1, // Opcode: MADDV_W -/* 7321 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7334 -/* 7325 */ MCD_OPC_CheckPredicate, 8, 253, 24, // Skip to: 13726 -/* 7329 */ MCD_OPC_Decode, 139, 8, 144, 1, // Opcode: MADDV_D -/* 7334 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7347 -/* 7338 */ MCD_OPC_CheckPredicate, 8, 240, 24, // Skip to: 13726 -/* 7342 */ MCD_OPC_Decode, 156, 9, 141, 1, // Opcode: MSUBV_B -/* 7347 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7360 -/* 7351 */ MCD_OPC_CheckPredicate, 8, 227, 24, // Skip to: 13726 -/* 7355 */ MCD_OPC_Decode, 158, 9, 142, 1, // Opcode: MSUBV_H -/* 7360 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7373 -/* 7364 */ MCD_OPC_CheckPredicate, 8, 214, 24, // Skip to: 13726 -/* 7368 */ MCD_OPC_Decode, 159, 9, 143, 1, // Opcode: MSUBV_W -/* 7373 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7386 -/* 7377 */ MCD_OPC_CheckPredicate, 8, 201, 24, // Skip to: 13726 -/* 7381 */ MCD_OPC_Decode, 157, 9, 144, 1, // Opcode: MSUBV_D -/* 7386 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 7399 -/* 7390 */ MCD_OPC_CheckPredicate, 8, 188, 24, // Skip to: 13726 -/* 7394 */ MCD_OPC_Decode, 185, 4, 137, 1, // Opcode: DIV_S_B -/* 7399 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7412 -/* 7403 */ MCD_OPC_CheckPredicate, 8, 175, 24, // Skip to: 13726 -/* 7407 */ MCD_OPC_Decode, 187, 4, 138, 1, // Opcode: DIV_S_H -/* 7412 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7425 -/* 7416 */ MCD_OPC_CheckPredicate, 8, 162, 24, // Skip to: 13726 -/* 7420 */ MCD_OPC_Decode, 188, 4, 139, 1, // Opcode: DIV_S_W -/* 7425 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7438 -/* 7429 */ MCD_OPC_CheckPredicate, 8, 149, 24, // Skip to: 13726 -/* 7433 */ MCD_OPC_Decode, 186, 4, 140, 1, // Opcode: DIV_S_D -/* 7438 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 7451 -/* 7442 */ MCD_OPC_CheckPredicate, 8, 136, 24, // Skip to: 13726 -/* 7446 */ MCD_OPC_Decode, 189, 4, 137, 1, // Opcode: DIV_U_B -/* 7451 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7464 -/* 7455 */ MCD_OPC_CheckPredicate, 8, 123, 24, // Skip to: 13726 -/* 7459 */ MCD_OPC_Decode, 191, 4, 138, 1, // Opcode: DIV_U_H -/* 7464 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7477 -/* 7468 */ MCD_OPC_CheckPredicate, 8, 110, 24, // Skip to: 13726 -/* 7472 */ MCD_OPC_Decode, 192, 4, 139, 1, // Opcode: DIV_U_W -/* 7477 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 7490 -/* 7481 */ MCD_OPC_CheckPredicate, 8, 97, 24, // Skip to: 13726 -/* 7485 */ MCD_OPC_Decode, 190, 4, 140, 1, // Opcode: DIV_U_D -/* 7490 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 7503 -/* 7494 */ MCD_OPC_CheckPredicate, 8, 84, 24, // Skip to: 13726 -/* 7498 */ MCD_OPC_Decode, 225, 8, 137, 1, // Opcode: MOD_S_B -/* 7503 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 7516 -/* 7507 */ MCD_OPC_CheckPredicate, 8, 71, 24, // Skip to: 13726 -/* 7511 */ MCD_OPC_Decode, 227, 8, 138, 1, // Opcode: MOD_S_H -/* 7516 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 7529 -/* 7520 */ MCD_OPC_CheckPredicate, 8, 58, 24, // Skip to: 13726 -/* 7524 */ MCD_OPC_Decode, 228, 8, 139, 1, // Opcode: MOD_S_W -/* 7529 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 7542 -/* 7533 */ MCD_OPC_CheckPredicate, 8, 45, 24, // Skip to: 13726 -/* 7537 */ MCD_OPC_Decode, 226, 8, 140, 1, // Opcode: MOD_S_D -/* 7542 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 7555 -/* 7546 */ MCD_OPC_CheckPredicate, 8, 32, 24, // Skip to: 13726 -/* 7550 */ MCD_OPC_Decode, 229, 8, 137, 1, // Opcode: MOD_U_B -/* 7555 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 7568 -/* 7559 */ MCD_OPC_CheckPredicate, 8, 19, 24, // Skip to: 13726 -/* 7563 */ MCD_OPC_Decode, 231, 8, 138, 1, // Opcode: MOD_U_H -/* 7568 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 7581 -/* 7572 */ MCD_OPC_CheckPredicate, 8, 6, 24, // Skip to: 13726 -/* 7576 */ MCD_OPC_Decode, 232, 8, 139, 1, // Opcode: MOD_U_W -/* 7581 */ MCD_OPC_FilterValue, 31, 253, 23, // Skip to: 13726 -/* 7585 */ MCD_OPC_CheckPredicate, 8, 249, 23, // Skip to: 13726 -/* 7589 */ MCD_OPC_Decode, 230, 8, 140, 1, // Opcode: MOD_U_D -/* 7594 */ MCD_OPC_FilterValue, 19, 237, 0, // Skip to: 7835 -/* 7598 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 7601 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7614 -/* 7605 */ MCD_OPC_CheckPredicate, 8, 229, 23, // Skip to: 13726 -/* 7609 */ MCD_OPC_Decode, 212, 4, 145, 1, // Opcode: DOTP_S_H -/* 7614 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7627 -/* 7618 */ MCD_OPC_CheckPredicate, 8, 216, 23, // Skip to: 13726 -/* 7622 */ MCD_OPC_Decode, 213, 4, 146, 1, // Opcode: DOTP_S_W -/* 7627 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7640 -/* 7631 */ MCD_OPC_CheckPredicate, 8, 203, 23, // Skip to: 13726 -/* 7635 */ MCD_OPC_Decode, 211, 4, 147, 1, // Opcode: DOTP_S_D -/* 7640 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7653 -/* 7644 */ MCD_OPC_CheckPredicate, 8, 190, 23, // Skip to: 13726 -/* 7648 */ MCD_OPC_Decode, 215, 4, 145, 1, // Opcode: DOTP_U_H -/* 7653 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7666 -/* 7657 */ MCD_OPC_CheckPredicate, 8, 177, 23, // Skip to: 13726 -/* 7661 */ MCD_OPC_Decode, 216, 4, 146, 1, // Opcode: DOTP_U_W -/* 7666 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7679 -/* 7670 */ MCD_OPC_CheckPredicate, 8, 164, 23, // Skip to: 13726 -/* 7674 */ MCD_OPC_Decode, 214, 4, 147, 1, // Opcode: DOTP_U_D -/* 7679 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7692 -/* 7683 */ MCD_OPC_CheckPredicate, 8, 151, 23, // Skip to: 13726 -/* 7687 */ MCD_OPC_Decode, 218, 4, 148, 1, // Opcode: DPADD_S_H -/* 7692 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7705 -/* 7696 */ MCD_OPC_CheckPredicate, 8, 138, 23, // Skip to: 13726 -/* 7700 */ MCD_OPC_Decode, 219, 4, 149, 1, // Opcode: DPADD_S_W -/* 7705 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7718 -/* 7709 */ MCD_OPC_CheckPredicate, 8, 125, 23, // Skip to: 13726 -/* 7713 */ MCD_OPC_Decode, 217, 4, 150, 1, // Opcode: DPADD_S_D -/* 7718 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7731 -/* 7722 */ MCD_OPC_CheckPredicate, 8, 112, 23, // Skip to: 13726 -/* 7726 */ MCD_OPC_Decode, 221, 4, 148, 1, // Opcode: DPADD_U_H -/* 7731 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7744 -/* 7735 */ MCD_OPC_CheckPredicate, 8, 99, 23, // Skip to: 13726 -/* 7739 */ MCD_OPC_Decode, 222, 4, 149, 1, // Opcode: DPADD_U_W -/* 7744 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7757 -/* 7748 */ MCD_OPC_CheckPredicate, 8, 86, 23, // Skip to: 13726 -/* 7752 */ MCD_OPC_Decode, 220, 4, 150, 1, // Opcode: DPADD_U_D -/* 7757 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7770 -/* 7761 */ MCD_OPC_CheckPredicate, 8, 73, 23, // Skip to: 13726 -/* 7765 */ MCD_OPC_Decode, 237, 4, 148, 1, // Opcode: DPSUB_S_H -/* 7770 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7783 -/* 7774 */ MCD_OPC_CheckPredicate, 8, 60, 23, // Skip to: 13726 -/* 7778 */ MCD_OPC_Decode, 238, 4, 149, 1, // Opcode: DPSUB_S_W -/* 7783 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7796 -/* 7787 */ MCD_OPC_CheckPredicate, 8, 47, 23, // Skip to: 13726 -/* 7791 */ MCD_OPC_Decode, 236, 4, 150, 1, // Opcode: DPSUB_S_D -/* 7796 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7809 -/* 7800 */ MCD_OPC_CheckPredicate, 8, 34, 23, // Skip to: 13726 -/* 7804 */ MCD_OPC_Decode, 240, 4, 148, 1, // Opcode: DPSUB_U_H -/* 7809 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7822 -/* 7813 */ MCD_OPC_CheckPredicate, 8, 21, 23, // Skip to: 13726 -/* 7817 */ MCD_OPC_Decode, 241, 4, 149, 1, // Opcode: DPSUB_U_W -/* 7822 */ MCD_OPC_FilterValue, 23, 12, 23, // Skip to: 13726 -/* 7826 */ MCD_OPC_CheckPredicate, 8, 8, 23, // Skip to: 13726 -/* 7830 */ MCD_OPC_Decode, 239, 4, 150, 1, // Opcode: DPSUB_U_D -/* 7835 */ MCD_OPC_FilterValue, 20, 163, 1, // Skip to: 8258 -/* 7839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 7842 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7855 -/* 7846 */ MCD_OPC_CheckPredicate, 8, 244, 22, // Skip to: 13726 -/* 7850 */ MCD_OPC_Decode, 221, 11, 151, 1, // Opcode: SLD_B -/* 7855 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7868 -/* 7859 */ MCD_OPC_CheckPredicate, 8, 231, 22, // Skip to: 13726 -/* 7863 */ MCD_OPC_Decode, 223, 11, 152, 1, // Opcode: SLD_H -/* 7868 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7881 -/* 7872 */ MCD_OPC_CheckPredicate, 8, 218, 22, // Skip to: 13726 -/* 7876 */ MCD_OPC_Decode, 224, 11, 153, 1, // Opcode: SLD_W -/* 7881 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7894 -/* 7885 */ MCD_OPC_CheckPredicate, 8, 205, 22, // Skip to: 13726 -/* 7889 */ MCD_OPC_Decode, 222, 11, 154, 1, // Opcode: SLD_D -/* 7894 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7907 -/* 7898 */ MCD_OPC_CheckPredicate, 8, 192, 22, // Skip to: 13726 -/* 7902 */ MCD_OPC_Decode, 135, 12, 155, 1, // Opcode: SPLAT_B -/* 7907 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7920 -/* 7911 */ MCD_OPC_CheckPredicate, 8, 179, 22, // Skip to: 13726 -/* 7915 */ MCD_OPC_Decode, 137, 12, 156, 1, // Opcode: SPLAT_H -/* 7920 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7933 -/* 7924 */ MCD_OPC_CheckPredicate, 8, 166, 22, // Skip to: 13726 -/* 7928 */ MCD_OPC_Decode, 138, 12, 157, 1, // Opcode: SPLAT_W -/* 7933 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7946 -/* 7937 */ MCD_OPC_CheckPredicate, 8, 153, 22, // Skip to: 13726 -/* 7941 */ MCD_OPC_Decode, 136, 12, 158, 1, // Opcode: SPLAT_D -/* 7946 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7959 -/* 7950 */ MCD_OPC_CheckPredicate, 8, 140, 22, // Skip to: 13726 -/* 7954 */ MCD_OPC_Decode, 149, 10, 137, 1, // Opcode: PCKEV_B -/* 7959 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7972 -/* 7963 */ MCD_OPC_CheckPredicate, 8, 127, 22, // Skip to: 13726 -/* 7967 */ MCD_OPC_Decode, 151, 10, 138, 1, // Opcode: PCKEV_H -/* 7972 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7985 -/* 7976 */ MCD_OPC_CheckPredicate, 8, 114, 22, // Skip to: 13726 -/* 7980 */ MCD_OPC_Decode, 152, 10, 139, 1, // Opcode: PCKEV_W -/* 7985 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7998 -/* 7989 */ MCD_OPC_CheckPredicate, 8, 101, 22, // Skip to: 13726 -/* 7993 */ MCD_OPC_Decode, 150, 10, 140, 1, // Opcode: PCKEV_D -/* 7998 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8011 -/* 8002 */ MCD_OPC_CheckPredicate, 8, 88, 22, // Skip to: 13726 -/* 8006 */ MCD_OPC_Decode, 153, 10, 137, 1, // Opcode: PCKOD_B -/* 8011 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 8024 -/* 8015 */ MCD_OPC_CheckPredicate, 8, 75, 22, // Skip to: 13726 -/* 8019 */ MCD_OPC_Decode, 155, 10, 138, 1, // Opcode: PCKOD_H -/* 8024 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 8037 -/* 8028 */ MCD_OPC_CheckPredicate, 8, 62, 22, // Skip to: 13726 -/* 8032 */ MCD_OPC_Decode, 156, 10, 139, 1, // Opcode: PCKOD_W -/* 8037 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 8050 -/* 8041 */ MCD_OPC_CheckPredicate, 8, 49, 22, // Skip to: 13726 -/* 8045 */ MCD_OPC_Decode, 154, 10, 140, 1, // Opcode: PCKOD_D -/* 8050 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8063 -/* 8054 */ MCD_OPC_CheckPredicate, 8, 36, 22, // Skip to: 13726 -/* 8058 */ MCD_OPC_Decode, 216, 6, 137, 1, // Opcode: ILVL_B -/* 8063 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8076 -/* 8067 */ MCD_OPC_CheckPredicate, 8, 23, 22, // Skip to: 13726 -/* 8071 */ MCD_OPC_Decode, 218, 6, 138, 1, // Opcode: ILVL_H -/* 8076 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8089 -/* 8080 */ MCD_OPC_CheckPredicate, 8, 10, 22, // Skip to: 13726 -/* 8084 */ MCD_OPC_Decode, 219, 6, 139, 1, // Opcode: ILVL_W -/* 8089 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8102 -/* 8093 */ MCD_OPC_CheckPredicate, 8, 253, 21, // Skip to: 13726 -/* 8097 */ MCD_OPC_Decode, 217, 6, 140, 1, // Opcode: ILVL_D -/* 8102 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 8115 -/* 8106 */ MCD_OPC_CheckPredicate, 8, 240, 21, // Skip to: 13726 -/* 8110 */ MCD_OPC_Decode, 224, 6, 137, 1, // Opcode: ILVR_B -/* 8115 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8128 -/* 8119 */ MCD_OPC_CheckPredicate, 8, 227, 21, // Skip to: 13726 -/* 8123 */ MCD_OPC_Decode, 226, 6, 138, 1, // Opcode: ILVR_H -/* 8128 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8141 -/* 8132 */ MCD_OPC_CheckPredicate, 8, 214, 21, // Skip to: 13726 -/* 8136 */ MCD_OPC_Decode, 227, 6, 139, 1, // Opcode: ILVR_W -/* 8141 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8154 -/* 8145 */ MCD_OPC_CheckPredicate, 8, 201, 21, // Skip to: 13726 -/* 8149 */ MCD_OPC_Decode, 225, 6, 140, 1, // Opcode: ILVR_D -/* 8154 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 8167 -/* 8158 */ MCD_OPC_CheckPredicate, 8, 188, 21, // Skip to: 13726 -/* 8162 */ MCD_OPC_Decode, 212, 6, 137, 1, // Opcode: ILVEV_B -/* 8167 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8180 -/* 8171 */ MCD_OPC_CheckPredicate, 8, 175, 21, // Skip to: 13726 -/* 8175 */ MCD_OPC_Decode, 214, 6, 138, 1, // Opcode: ILVEV_H -/* 8180 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8193 -/* 8184 */ MCD_OPC_CheckPredicate, 8, 162, 21, // Skip to: 13726 -/* 8188 */ MCD_OPC_Decode, 215, 6, 139, 1, // Opcode: ILVEV_W -/* 8193 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8206 -/* 8197 */ MCD_OPC_CheckPredicate, 8, 149, 21, // Skip to: 13726 -/* 8201 */ MCD_OPC_Decode, 213, 6, 140, 1, // Opcode: ILVEV_D -/* 8206 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 8219 -/* 8210 */ MCD_OPC_CheckPredicate, 8, 136, 21, // Skip to: 13726 -/* 8214 */ MCD_OPC_Decode, 220, 6, 137, 1, // Opcode: ILVOD_B -/* 8219 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8232 -/* 8223 */ MCD_OPC_CheckPredicate, 8, 123, 21, // Skip to: 13726 -/* 8227 */ MCD_OPC_Decode, 222, 6, 138, 1, // Opcode: ILVOD_H -/* 8232 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8245 -/* 8236 */ MCD_OPC_CheckPredicate, 8, 110, 21, // Skip to: 13726 -/* 8240 */ MCD_OPC_Decode, 223, 6, 139, 1, // Opcode: ILVOD_W -/* 8245 */ MCD_OPC_FilterValue, 31, 101, 21, // Skip to: 13726 -/* 8249 */ MCD_OPC_CheckPredicate, 8, 97, 21, // Skip to: 13726 -/* 8253 */ MCD_OPC_Decode, 221, 6, 140, 1, // Opcode: ILVOD_D -/* 8258 */ MCD_OPC_FilterValue, 21, 59, 1, // Skip to: 8577 -/* 8262 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 8265 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8278 -/* 8269 */ MCD_OPC_CheckPredicate, 8, 77, 21, // Skip to: 13726 -/* 8273 */ MCD_OPC_Decode, 227, 13, 141, 1, // Opcode: VSHF_B -/* 8278 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8291 -/* 8282 */ MCD_OPC_CheckPredicate, 8, 64, 21, // Skip to: 13726 -/* 8286 */ MCD_OPC_Decode, 229, 13, 142, 1, // Opcode: VSHF_H -/* 8291 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8304 -/* 8295 */ MCD_OPC_CheckPredicate, 8, 51, 21, // Skip to: 13726 -/* 8299 */ MCD_OPC_Decode, 230, 13, 143, 1, // Opcode: VSHF_W -/* 8304 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 8317 -/* 8308 */ MCD_OPC_CheckPredicate, 8, 38, 21, // Skip to: 13726 -/* 8312 */ MCD_OPC_Decode, 228, 13, 144, 1, // Opcode: VSHF_D -/* 8317 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8330 -/* 8321 */ MCD_OPC_CheckPredicate, 8, 25, 21, // Skip to: 13726 -/* 8325 */ MCD_OPC_Decode, 148, 12, 137, 1, // Opcode: SRAR_B -/* 8330 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 8343 -/* 8334 */ MCD_OPC_CheckPredicate, 8, 12, 21, // Skip to: 13726 -/* 8338 */ MCD_OPC_Decode, 150, 12, 138, 1, // Opcode: SRAR_H -/* 8343 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 8356 -/* 8347 */ MCD_OPC_CheckPredicate, 8, 255, 20, // Skip to: 13726 -/* 8351 */ MCD_OPC_Decode, 151, 12, 139, 1, // Opcode: SRAR_W -/* 8356 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 8369 -/* 8360 */ MCD_OPC_CheckPredicate, 8, 242, 20, // Skip to: 13726 -/* 8364 */ MCD_OPC_Decode, 149, 12, 140, 1, // Opcode: SRAR_D -/* 8369 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8382 -/* 8373 */ MCD_OPC_CheckPredicate, 8, 229, 20, // Skip to: 13726 -/* 8377 */ MCD_OPC_Decode, 169, 12, 137, 1, // Opcode: SRLR_B -/* 8382 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 8395 -/* 8386 */ MCD_OPC_CheckPredicate, 8, 216, 20, // Skip to: 13726 -/* 8390 */ MCD_OPC_Decode, 171, 12, 138, 1, // Opcode: SRLR_H -/* 8395 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 8408 -/* 8399 */ MCD_OPC_CheckPredicate, 8, 203, 20, // Skip to: 13726 -/* 8403 */ MCD_OPC_Decode, 172, 12, 139, 1, // Opcode: SRLR_W -/* 8408 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 8421 -/* 8412 */ MCD_OPC_CheckPredicate, 8, 190, 20, // Skip to: 13726 -/* 8416 */ MCD_OPC_Decode, 170, 12, 140, 1, // Opcode: SRLR_D -/* 8421 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8434 -/* 8425 */ MCD_OPC_CheckPredicate, 8, 177, 20, // Skip to: 13726 -/* 8429 */ MCD_OPC_Decode, 201, 6, 145, 1, // Opcode: HADD_S_H -/* 8434 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8447 -/* 8438 */ MCD_OPC_CheckPredicate, 8, 164, 20, // Skip to: 13726 -/* 8442 */ MCD_OPC_Decode, 202, 6, 146, 1, // Opcode: HADD_S_W -/* 8447 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8460 -/* 8451 */ MCD_OPC_CheckPredicate, 8, 151, 20, // Skip to: 13726 -/* 8455 */ MCD_OPC_Decode, 200, 6, 147, 1, // Opcode: HADD_S_D -/* 8460 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8473 -/* 8464 */ MCD_OPC_CheckPredicate, 8, 138, 20, // Skip to: 13726 -/* 8468 */ MCD_OPC_Decode, 204, 6, 145, 1, // Opcode: HADD_U_H -/* 8473 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8486 -/* 8477 */ MCD_OPC_CheckPredicate, 8, 125, 20, // Skip to: 13726 -/* 8481 */ MCD_OPC_Decode, 205, 6, 146, 1, // Opcode: HADD_U_W -/* 8486 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8499 -/* 8490 */ MCD_OPC_CheckPredicate, 8, 112, 20, // Skip to: 13726 -/* 8494 */ MCD_OPC_Decode, 203, 6, 147, 1, // Opcode: HADD_U_D -/* 8499 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8512 -/* 8503 */ MCD_OPC_CheckPredicate, 8, 99, 20, // Skip to: 13726 -/* 8507 */ MCD_OPC_Decode, 207, 6, 145, 1, // Opcode: HSUB_S_H -/* 8512 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8525 -/* 8516 */ MCD_OPC_CheckPredicate, 8, 86, 20, // Skip to: 13726 -/* 8520 */ MCD_OPC_Decode, 208, 6, 146, 1, // Opcode: HSUB_S_W -/* 8525 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8538 -/* 8529 */ MCD_OPC_CheckPredicate, 8, 73, 20, // Skip to: 13726 -/* 8533 */ MCD_OPC_Decode, 206, 6, 147, 1, // Opcode: HSUB_S_D -/* 8538 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8551 -/* 8542 */ MCD_OPC_CheckPredicate, 8, 60, 20, // Skip to: 13726 -/* 8546 */ MCD_OPC_Decode, 210, 6, 145, 1, // Opcode: HSUB_U_H -/* 8551 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8564 -/* 8555 */ MCD_OPC_CheckPredicate, 8, 47, 20, // Skip to: 13726 -/* 8559 */ MCD_OPC_Decode, 211, 6, 146, 1, // Opcode: HSUB_U_W -/* 8564 */ MCD_OPC_FilterValue, 31, 38, 20, // Skip to: 13726 -/* 8568 */ MCD_OPC_CheckPredicate, 8, 34, 20, // Skip to: 13726 -/* 8572 */ MCD_OPC_Decode, 209, 6, 147, 1, // Opcode: HSUB_U_D -/* 8577 */ MCD_OPC_FilterValue, 25, 230, 1, // Skip to: 9067 -/* 8581 */ MCD_OPC_ExtractField, 20, 6, // Inst{25-20} ... -/* 8584 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8597 -/* 8588 */ MCD_OPC_CheckPredicate, 8, 14, 20, // Skip to: 13726 -/* 8592 */ MCD_OPC_Decode, 217, 11, 159, 1, // Opcode: SLDI_B -/* 8597 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8616 -/* 8601 */ MCD_OPC_CheckPredicate, 8, 1, 20, // Skip to: 13726 -/* 8605 */ MCD_OPC_CheckField, 19, 1, 0, 251, 19, // Skip to: 13726 -/* 8611 */ MCD_OPC_Decode, 219, 11, 160, 1, // Opcode: SLDI_H -/* 8616 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 8674 -/* 8620 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8623 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8636 -/* 8627 */ MCD_OPC_CheckPredicate, 8, 231, 19, // Skip to: 13726 -/* 8631 */ MCD_OPC_Decode, 220, 11, 161, 1, // Opcode: SLDI_W -/* 8636 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8655 -/* 8640 */ MCD_OPC_CheckPredicate, 8, 218, 19, // Skip to: 13726 -/* 8644 */ MCD_OPC_CheckField, 17, 1, 0, 212, 19, // Skip to: 13726 -/* 8650 */ MCD_OPC_Decode, 218, 11, 162, 1, // Opcode: SLDI_D -/* 8655 */ MCD_OPC_FilterValue, 3, 203, 19, // Skip to: 13726 -/* 8659 */ MCD_OPC_CheckPredicate, 8, 199, 19, // Skip to: 13726 -/* 8663 */ MCD_OPC_CheckField, 16, 2, 2, 193, 19, // Skip to: 13726 -/* 8669 */ MCD_OPC_Decode, 212, 3, 163, 1, // Opcode: CTCMSA -/* 8674 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8687 -/* 8678 */ MCD_OPC_CheckPredicate, 8, 180, 19, // Skip to: 13726 -/* 8682 */ MCD_OPC_Decode, 131, 12, 164, 1, // Opcode: SPLATI_B -/* 8687 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 8706 -/* 8691 */ MCD_OPC_CheckPredicate, 8, 167, 19, // Skip to: 13726 -/* 8695 */ MCD_OPC_CheckField, 19, 1, 0, 161, 19, // Skip to: 13726 -/* 8701 */ MCD_OPC_Decode, 133, 12, 165, 1, // Opcode: SPLATI_H -/* 8706 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 8764 -/* 8710 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8713 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8726 -/* 8717 */ MCD_OPC_CheckPredicate, 8, 141, 19, // Skip to: 13726 -/* 8721 */ MCD_OPC_Decode, 134, 12, 166, 1, // Opcode: SPLATI_W -/* 8726 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8745 -/* 8730 */ MCD_OPC_CheckPredicate, 8, 128, 19, // Skip to: 13726 -/* 8734 */ MCD_OPC_CheckField, 17, 1, 0, 122, 19, // Skip to: 13726 -/* 8740 */ MCD_OPC_Decode, 132, 12, 167, 1, // Opcode: SPLATI_D -/* 8745 */ MCD_OPC_FilterValue, 3, 113, 19, // Skip to: 13726 -/* 8749 */ MCD_OPC_CheckPredicate, 8, 109, 19, // Skip to: 13726 -/* 8753 */ MCD_OPC_CheckField, 16, 2, 2, 103, 19, // Skip to: 13726 -/* 8759 */ MCD_OPC_Decode, 240, 2, 168, 1, // Opcode: CFCMSA -/* 8764 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8777 -/* 8768 */ MCD_OPC_CheckPredicate, 8, 90, 19, // Skip to: 13726 -/* 8772 */ MCD_OPC_Decode, 202, 3, 169, 1, // Opcode: COPY_S_B -/* 8777 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 8796 -/* 8781 */ MCD_OPC_CheckPredicate, 8, 77, 19, // Skip to: 13726 -/* 8785 */ MCD_OPC_CheckField, 19, 1, 0, 71, 19, // Skip to: 13726 -/* 8791 */ MCD_OPC_Decode, 204, 3, 170, 1, // Opcode: COPY_S_H -/* 8796 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 8854 -/* 8800 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8803 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8816 -/* 8807 */ MCD_OPC_CheckPredicate, 8, 51, 19, // Skip to: 13726 -/* 8811 */ MCD_OPC_Decode, 205, 3, 171, 1, // Opcode: COPY_S_W -/* 8816 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8835 -/* 8820 */ MCD_OPC_CheckPredicate, 14, 38, 19, // Skip to: 13726 -/* 8824 */ MCD_OPC_CheckField, 17, 1, 0, 32, 19, // Skip to: 13726 -/* 8830 */ MCD_OPC_Decode, 203, 3, 172, 1, // Opcode: COPY_S_D -/* 8835 */ MCD_OPC_FilterValue, 3, 23, 19, // Skip to: 13726 -/* 8839 */ MCD_OPC_CheckPredicate, 8, 19, 19, // Skip to: 13726 -/* 8843 */ MCD_OPC_CheckField, 16, 2, 2, 13, 19, // Skip to: 13726 -/* 8849 */ MCD_OPC_Decode, 235, 8, 173, 1, // Opcode: MOVE_V -/* 8854 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8867 -/* 8858 */ MCD_OPC_CheckPredicate, 8, 0, 19, // Skip to: 13726 -/* 8862 */ MCD_OPC_Decode, 206, 3, 169, 1, // Opcode: COPY_U_B -/* 8867 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 8886 -/* 8871 */ MCD_OPC_CheckPredicate, 8, 243, 18, // Skip to: 13726 -/* 8875 */ MCD_OPC_CheckField, 19, 1, 0, 237, 18, // Skip to: 13726 -/* 8881 */ MCD_OPC_Decode, 208, 3, 170, 1, // Opcode: COPY_U_H -/* 8886 */ MCD_OPC_FilterValue, 15, 35, 0, // Skip to: 8925 -/* 8890 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8893 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8906 -/* 8897 */ MCD_OPC_CheckPredicate, 8, 217, 18, // Skip to: 13726 -/* 8901 */ MCD_OPC_Decode, 209, 3, 171, 1, // Opcode: COPY_U_W -/* 8906 */ MCD_OPC_FilterValue, 2, 208, 18, // Skip to: 13726 -/* 8910 */ MCD_OPC_CheckPredicate, 14, 204, 18, // Skip to: 13726 -/* 8914 */ MCD_OPC_CheckField, 17, 1, 0, 198, 18, // Skip to: 13726 -/* 8920 */ MCD_OPC_Decode, 207, 3, 172, 1, // Opcode: COPY_U_D -/* 8925 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8938 -/* 8929 */ MCD_OPC_CheckPredicate, 8, 185, 18, // Skip to: 13726 -/* 8933 */ MCD_OPC_Decode, 229, 6, 174, 1, // Opcode: INSERT_B -/* 8938 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 8957 -/* 8942 */ MCD_OPC_CheckPredicate, 8, 172, 18, // Skip to: 13726 -/* 8946 */ MCD_OPC_CheckField, 19, 1, 0, 166, 18, // Skip to: 13726 -/* 8952 */ MCD_OPC_Decode, 237, 6, 175, 1, // Opcode: INSERT_H -/* 8957 */ MCD_OPC_FilterValue, 19, 35, 0, // Skip to: 8996 -/* 8961 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8964 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8977 -/* 8968 */ MCD_OPC_CheckPredicate, 8, 146, 18, // Skip to: 13726 -/* 8972 */ MCD_OPC_Decode, 239, 6, 176, 1, // Opcode: INSERT_W -/* 8977 */ MCD_OPC_FilterValue, 2, 137, 18, // Skip to: 13726 -/* 8981 */ MCD_OPC_CheckPredicate, 14, 133, 18, // Skip to: 13726 -/* 8985 */ MCD_OPC_CheckField, 17, 1, 0, 127, 18, // Skip to: 13726 -/* 8991 */ MCD_OPC_Decode, 231, 6, 177, 1, // Opcode: INSERT_D -/* 8996 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9009 -/* 9000 */ MCD_OPC_CheckPredicate, 8, 114, 18, // Skip to: 13726 -/* 9004 */ MCD_OPC_Decode, 242, 6, 178, 1, // Opcode: INSVE_B -/* 9009 */ MCD_OPC_FilterValue, 22, 15, 0, // Skip to: 9028 -/* 9013 */ MCD_OPC_CheckPredicate, 8, 101, 18, // Skip to: 13726 -/* 9017 */ MCD_OPC_CheckField, 19, 1, 0, 95, 18, // Skip to: 13726 -/* 9023 */ MCD_OPC_Decode, 244, 6, 178, 1, // Opcode: INSVE_H -/* 9028 */ MCD_OPC_FilterValue, 23, 86, 18, // Skip to: 13726 -/* 9032 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 9035 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9048 -/* 9039 */ MCD_OPC_CheckPredicate, 8, 75, 18, // Skip to: 13726 -/* 9043 */ MCD_OPC_Decode, 245, 6, 178, 1, // Opcode: INSVE_W -/* 9048 */ MCD_OPC_FilterValue, 2, 66, 18, // Skip to: 13726 -/* 9052 */ MCD_OPC_CheckPredicate, 8, 62, 18, // Skip to: 13726 -/* 9056 */ MCD_OPC_CheckField, 17, 1, 0, 56, 18, // Skip to: 13726 -/* 9062 */ MCD_OPC_Decode, 243, 6, 178, 1, // Opcode: INSVE_D -/* 9067 */ MCD_OPC_FilterValue, 26, 163, 1, // Skip to: 9490 -/* 9071 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 9074 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9087 -/* 9078 */ MCD_OPC_CheckPredicate, 8, 36, 18, // Skip to: 13726 -/* 9082 */ MCD_OPC_Decode, 178, 5, 139, 1, // Opcode: FCAF_W -/* 9087 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9100 -/* 9091 */ MCD_OPC_CheckPredicate, 8, 23, 18, // Skip to: 13726 -/* 9095 */ MCD_OPC_Decode, 177, 5, 140, 1, // Opcode: FCAF_D -/* 9100 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9113 -/* 9104 */ MCD_OPC_CheckPredicate, 8, 10, 18, // Skip to: 13726 -/* 9108 */ MCD_OPC_Decode, 205, 5, 139, 1, // Opcode: FCUN_W -/* 9113 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9126 -/* 9117 */ MCD_OPC_CheckPredicate, 8, 253, 17, // Skip to: 13726 -/* 9121 */ MCD_OPC_Decode, 204, 5, 140, 1, // Opcode: FCUN_D -/* 9126 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9139 -/* 9130 */ MCD_OPC_CheckPredicate, 8, 240, 17, // Skip to: 13726 -/* 9134 */ MCD_OPC_Decode, 180, 5, 139, 1, // Opcode: FCEQ_W -/* 9139 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9152 -/* 9143 */ MCD_OPC_CheckPredicate, 8, 227, 17, // Skip to: 13726 -/* 9147 */ MCD_OPC_Decode, 179, 5, 140, 1, // Opcode: FCEQ_D -/* 9152 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9165 -/* 9156 */ MCD_OPC_CheckPredicate, 8, 214, 17, // Skip to: 13726 -/* 9160 */ MCD_OPC_Decode, 197, 5, 139, 1, // Opcode: FCUEQ_W -/* 9165 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9178 -/* 9169 */ MCD_OPC_CheckPredicate, 8, 201, 17, // Skip to: 13726 -/* 9173 */ MCD_OPC_Decode, 196, 5, 140, 1, // Opcode: FCUEQ_D -/* 9178 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9191 -/* 9182 */ MCD_OPC_CheckPredicate, 8, 188, 17, // Skip to: 13726 -/* 9186 */ MCD_OPC_Decode, 186, 5, 139, 1, // Opcode: FCLT_W -/* 9191 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9204 -/* 9195 */ MCD_OPC_CheckPredicate, 8, 175, 17, // Skip to: 13726 -/* 9199 */ MCD_OPC_Decode, 185, 5, 140, 1, // Opcode: FCLT_D -/* 9204 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9217 -/* 9208 */ MCD_OPC_CheckPredicate, 8, 162, 17, // Skip to: 13726 -/* 9212 */ MCD_OPC_Decode, 201, 5, 139, 1, // Opcode: FCULT_W -/* 9217 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9230 -/* 9221 */ MCD_OPC_CheckPredicate, 8, 149, 17, // Skip to: 13726 -/* 9225 */ MCD_OPC_Decode, 200, 5, 140, 1, // Opcode: FCULT_D -/* 9230 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9243 -/* 9234 */ MCD_OPC_CheckPredicate, 8, 136, 17, // Skip to: 13726 -/* 9238 */ MCD_OPC_Decode, 184, 5, 139, 1, // Opcode: FCLE_W -/* 9243 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9256 -/* 9247 */ MCD_OPC_CheckPredicate, 8, 123, 17, // Skip to: 13726 -/* 9251 */ MCD_OPC_Decode, 183, 5, 140, 1, // Opcode: FCLE_D -/* 9256 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9269 -/* 9260 */ MCD_OPC_CheckPredicate, 8, 110, 17, // Skip to: 13726 -/* 9264 */ MCD_OPC_Decode, 199, 5, 139, 1, // Opcode: FCULE_W -/* 9269 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9282 -/* 9273 */ MCD_OPC_CheckPredicate, 8, 97, 17, // Skip to: 13726 -/* 9277 */ MCD_OPC_Decode, 198, 5, 140, 1, // Opcode: FCULE_D -/* 9282 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9295 -/* 9286 */ MCD_OPC_CheckPredicate, 8, 84, 17, // Skip to: 13726 -/* 9290 */ MCD_OPC_Decode, 154, 6, 139, 1, // Opcode: FSAF_W -/* 9295 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9308 -/* 9299 */ MCD_OPC_CheckPredicate, 8, 71, 17, // Skip to: 13726 -/* 9303 */ MCD_OPC_Decode, 153, 6, 140, 1, // Opcode: FSAF_D -/* 9308 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 9321 -/* 9312 */ MCD_OPC_CheckPredicate, 8, 58, 17, // Skip to: 13726 -/* 9316 */ MCD_OPC_Decode, 188, 6, 139, 1, // Opcode: FSUN_W -/* 9321 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 9334 -/* 9325 */ MCD_OPC_CheckPredicate, 8, 45, 17, // Skip to: 13726 -/* 9329 */ MCD_OPC_Decode, 187, 6, 140, 1, // Opcode: FSUN_D -/* 9334 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9347 -/* 9338 */ MCD_OPC_CheckPredicate, 8, 32, 17, // Skip to: 13726 -/* 9342 */ MCD_OPC_Decode, 156, 6, 139, 1, // Opcode: FSEQ_W -/* 9347 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9360 -/* 9351 */ MCD_OPC_CheckPredicate, 8, 19, 17, // Skip to: 13726 -/* 9355 */ MCD_OPC_Decode, 155, 6, 140, 1, // Opcode: FSEQ_D -/* 9360 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 9373 -/* 9364 */ MCD_OPC_CheckPredicate, 8, 6, 17, // Skip to: 13726 -/* 9368 */ MCD_OPC_Decode, 180, 6, 139, 1, // Opcode: FSUEQ_W -/* 9373 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 9386 -/* 9377 */ MCD_OPC_CheckPredicate, 8, 249, 16, // Skip to: 13726 -/* 9381 */ MCD_OPC_Decode, 179, 6, 140, 1, // Opcode: FSUEQ_D -/* 9386 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9399 -/* 9390 */ MCD_OPC_CheckPredicate, 8, 236, 16, // Skip to: 13726 -/* 9394 */ MCD_OPC_Decode, 160, 6, 139, 1, // Opcode: FSLT_W -/* 9399 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9412 -/* 9403 */ MCD_OPC_CheckPredicate, 8, 223, 16, // Skip to: 13726 -/* 9407 */ MCD_OPC_Decode, 159, 6, 140, 1, // Opcode: FSLT_D -/* 9412 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9425 -/* 9416 */ MCD_OPC_CheckPredicate, 8, 210, 16, // Skip to: 13726 -/* 9420 */ MCD_OPC_Decode, 184, 6, 139, 1, // Opcode: FSULT_W -/* 9425 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9438 -/* 9429 */ MCD_OPC_CheckPredicate, 8, 197, 16, // Skip to: 13726 -/* 9433 */ MCD_OPC_Decode, 183, 6, 140, 1, // Opcode: FSULT_D -/* 9438 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9451 -/* 9442 */ MCD_OPC_CheckPredicate, 8, 184, 16, // Skip to: 13726 -/* 9446 */ MCD_OPC_Decode, 158, 6, 139, 1, // Opcode: FSLE_W -/* 9451 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9464 -/* 9455 */ MCD_OPC_CheckPredicate, 8, 171, 16, // Skip to: 13726 -/* 9459 */ MCD_OPC_Decode, 157, 6, 140, 1, // Opcode: FSLE_D -/* 9464 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9477 -/* 9468 */ MCD_OPC_CheckPredicate, 8, 158, 16, // Skip to: 13726 -/* 9472 */ MCD_OPC_Decode, 182, 6, 139, 1, // Opcode: FSULE_W -/* 9477 */ MCD_OPC_FilterValue, 31, 149, 16, // Skip to: 13726 -/* 9481 */ MCD_OPC_CheckPredicate, 8, 145, 16, // Skip to: 13726 -/* 9485 */ MCD_OPC_Decode, 181, 6, 140, 1, // Opcode: FSULE_D -/* 9490 */ MCD_OPC_FilterValue, 27, 85, 1, // Skip to: 9835 -/* 9494 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 9497 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9510 -/* 9501 */ MCD_OPC_CheckPredicate, 8, 125, 16, // Skip to: 13726 -/* 9505 */ MCD_OPC_Decode, 176, 5, 139, 1, // Opcode: FADD_W -/* 9510 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9523 -/* 9514 */ MCD_OPC_CheckPredicate, 8, 112, 16, // Skip to: 13726 -/* 9518 */ MCD_OPC_Decode, 170, 5, 140, 1, // Opcode: FADD_D -/* 9523 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9536 -/* 9527 */ MCD_OPC_CheckPredicate, 8, 99, 16, // Skip to: 13726 -/* 9531 */ MCD_OPC_Decode, 178, 6, 139, 1, // Opcode: FSUB_W -/* 9536 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9549 -/* 9540 */ MCD_OPC_CheckPredicate, 8, 86, 16, // Skip to: 13726 -/* 9544 */ MCD_OPC_Decode, 172, 6, 140, 1, // Opcode: FSUB_D -/* 9549 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9562 -/* 9553 */ MCD_OPC_CheckPredicate, 8, 73, 16, // Skip to: 13726 -/* 9557 */ MCD_OPC_Decode, 141, 6, 139, 1, // Opcode: FMUL_W -/* 9562 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9575 -/* 9566 */ MCD_OPC_CheckPredicate, 8, 60, 16, // Skip to: 13726 -/* 9570 */ MCD_OPC_Decode, 135, 6, 140, 1, // Opcode: FMUL_D -/* 9575 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9588 -/* 9579 */ MCD_OPC_CheckPredicate, 8, 47, 16, // Skip to: 13726 -/* 9583 */ MCD_OPC_Decode, 212, 5, 139, 1, // Opcode: FDIV_W -/* 9588 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9601 -/* 9592 */ MCD_OPC_CheckPredicate, 8, 34, 16, // Skip to: 13726 -/* 9596 */ MCD_OPC_Decode, 206, 5, 140, 1, // Opcode: FDIV_D -/* 9601 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9614 -/* 9605 */ MCD_OPC_CheckPredicate, 8, 21, 16, // Skip to: 13726 -/* 9609 */ MCD_OPC_Decode, 247, 5, 143, 1, // Opcode: FMADD_W -/* 9614 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9627 -/* 9618 */ MCD_OPC_CheckPredicate, 8, 8, 16, // Skip to: 13726 -/* 9622 */ MCD_OPC_Decode, 246, 5, 144, 1, // Opcode: FMADD_D -/* 9627 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9640 -/* 9631 */ MCD_OPC_CheckPredicate, 8, 251, 15, // Skip to: 13726 -/* 9635 */ MCD_OPC_Decode, 134, 6, 143, 1, // Opcode: FMSUB_W -/* 9640 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9653 -/* 9644 */ MCD_OPC_CheckPredicate, 8, 238, 15, // Skip to: 13726 -/* 9648 */ MCD_OPC_Decode, 133, 6, 144, 1, // Opcode: FMSUB_D -/* 9653 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9666 -/* 9657 */ MCD_OPC_CheckPredicate, 8, 225, 15, // Skip to: 13726 -/* 9661 */ MCD_OPC_Decode, 217, 5, 139, 1, // Opcode: FEXP2_W -/* 9666 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9679 -/* 9670 */ MCD_OPC_CheckPredicate, 8, 212, 15, // Skip to: 13726 -/* 9674 */ MCD_OPC_Decode, 215, 5, 140, 1, // Opcode: FEXP2_D -/* 9679 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9692 -/* 9683 */ MCD_OPC_CheckPredicate, 8, 199, 15, // Skip to: 13726 -/* 9687 */ MCD_OPC_Decode, 213, 5, 179, 1, // Opcode: FEXDO_H -/* 9692 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9705 -/* 9696 */ MCD_OPC_CheckPredicate, 8, 186, 15, // Skip to: 13726 -/* 9700 */ MCD_OPC_Decode, 214, 5, 180, 1, // Opcode: FEXDO_W -/* 9705 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9718 -/* 9709 */ MCD_OPC_CheckPredicate, 8, 173, 15, // Skip to: 13726 -/* 9713 */ MCD_OPC_Decode, 193, 6, 179, 1, // Opcode: FTQ_H -/* 9718 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9731 -/* 9722 */ MCD_OPC_CheckPredicate, 8, 160, 15, // Skip to: 13726 -/* 9726 */ MCD_OPC_Decode, 194, 6, 180, 1, // Opcode: FTQ_W -/* 9731 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9744 -/* 9735 */ MCD_OPC_CheckPredicate, 8, 147, 15, // Skip to: 13726 -/* 9739 */ MCD_OPC_Decode, 255, 5, 139, 1, // Opcode: FMIN_W -/* 9744 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9757 -/* 9748 */ MCD_OPC_CheckPredicate, 8, 134, 15, // Skip to: 13726 -/* 9752 */ MCD_OPC_Decode, 254, 5, 140, 1, // Opcode: FMIN_D -/* 9757 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9770 -/* 9761 */ MCD_OPC_CheckPredicate, 8, 121, 15, // Skip to: 13726 -/* 9765 */ MCD_OPC_Decode, 253, 5, 139, 1, // Opcode: FMIN_A_W -/* 9770 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9783 -/* 9774 */ MCD_OPC_CheckPredicate, 8, 108, 15, // Skip to: 13726 -/* 9778 */ MCD_OPC_Decode, 252, 5, 140, 1, // Opcode: FMIN_A_D -/* 9783 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9796 -/* 9787 */ MCD_OPC_CheckPredicate, 8, 95, 15, // Skip to: 13726 -/* 9791 */ MCD_OPC_Decode, 251, 5, 139, 1, // Opcode: FMAX_W -/* 9796 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9809 -/* 9800 */ MCD_OPC_CheckPredicate, 8, 82, 15, // Skip to: 13726 -/* 9804 */ MCD_OPC_Decode, 250, 5, 140, 1, // Opcode: FMAX_D -/* 9809 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9822 -/* 9813 */ MCD_OPC_CheckPredicate, 8, 69, 15, // Skip to: 13726 -/* 9817 */ MCD_OPC_Decode, 249, 5, 139, 1, // Opcode: FMAX_A_W -/* 9822 */ MCD_OPC_FilterValue, 31, 60, 15, // Skip to: 13726 -/* 9826 */ MCD_OPC_CheckPredicate, 8, 56, 15, // Skip to: 13726 -/* 9830 */ MCD_OPC_Decode, 248, 5, 140, 1, // Opcode: FMAX_A_D -/* 9835 */ MCD_OPC_FilterValue, 28, 59, 1, // Skip to: 10154 -/* 9839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 9842 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9855 -/* 9846 */ MCD_OPC_CheckPredicate, 8, 36, 15, // Skip to: 13726 -/* 9850 */ MCD_OPC_Decode, 195, 5, 139, 1, // Opcode: FCOR_W -/* 9855 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9868 -/* 9859 */ MCD_OPC_CheckPredicate, 8, 23, 15, // Skip to: 13726 -/* 9863 */ MCD_OPC_Decode, 194, 5, 140, 1, // Opcode: FCOR_D -/* 9868 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9881 -/* 9872 */ MCD_OPC_CheckPredicate, 8, 10, 15, // Skip to: 13726 -/* 9876 */ MCD_OPC_Decode, 203, 5, 139, 1, // Opcode: FCUNE_W -/* 9881 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9894 -/* 9885 */ MCD_OPC_CheckPredicate, 8, 253, 14, // Skip to: 13726 -/* 9889 */ MCD_OPC_Decode, 202, 5, 140, 1, // Opcode: FCUNE_D -/* 9894 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9907 -/* 9898 */ MCD_OPC_CheckPredicate, 8, 240, 14, // Skip to: 13726 -/* 9902 */ MCD_OPC_Decode, 193, 5, 139, 1, // Opcode: FCNE_W -/* 9907 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9920 -/* 9911 */ MCD_OPC_CheckPredicate, 8, 227, 14, // Skip to: 13726 -/* 9915 */ MCD_OPC_Decode, 192, 5, 140, 1, // Opcode: FCNE_D -/* 9920 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9933 -/* 9924 */ MCD_OPC_CheckPredicate, 8, 214, 14, // Skip to: 13726 -/* 9928 */ MCD_OPC_Decode, 219, 9, 138, 1, // Opcode: MUL_Q_H -/* 9933 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9946 -/* 9937 */ MCD_OPC_CheckPredicate, 8, 201, 14, // Skip to: 13726 -/* 9941 */ MCD_OPC_Decode, 220, 9, 139, 1, // Opcode: MUL_Q_W -/* 9946 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9959 -/* 9950 */ MCD_OPC_CheckPredicate, 8, 188, 14, // Skip to: 13726 -/* 9954 */ MCD_OPC_Decode, 147, 8, 142, 1, // Opcode: MADD_Q_H -/* 9959 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9972 -/* 9963 */ MCD_OPC_CheckPredicate, 8, 175, 14, // Skip to: 13726 -/* 9967 */ MCD_OPC_Decode, 148, 8, 143, 1, // Opcode: MADD_Q_W -/* 9972 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9985 -/* 9976 */ MCD_OPC_CheckPredicate, 8, 162, 14, // Skip to: 13726 -/* 9980 */ MCD_OPC_Decode, 165, 9, 142, 1, // Opcode: MSUB_Q_H -/* 9985 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9998 -/* 9989 */ MCD_OPC_CheckPredicate, 8, 149, 14, // Skip to: 13726 -/* 9993 */ MCD_OPC_Decode, 166, 9, 143, 1, // Opcode: MSUB_Q_W -/* 9998 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10011 -/* 10002 */ MCD_OPC_CheckPredicate, 8, 136, 14, // Skip to: 13726 -/* 10006 */ MCD_OPC_Decode, 164, 6, 139, 1, // Opcode: FSOR_W -/* 10011 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10024 -/* 10015 */ MCD_OPC_CheckPredicate, 8, 123, 14, // Skip to: 13726 -/* 10019 */ MCD_OPC_Decode, 163, 6, 140, 1, // Opcode: FSOR_D -/* 10024 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10037 -/* 10028 */ MCD_OPC_CheckPredicate, 8, 110, 14, // Skip to: 13726 -/* 10032 */ MCD_OPC_Decode, 186, 6, 139, 1, // Opcode: FSUNE_W -/* 10037 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10050 -/* 10041 */ MCD_OPC_CheckPredicate, 8, 97, 14, // Skip to: 13726 -/* 10045 */ MCD_OPC_Decode, 185, 6, 140, 1, // Opcode: FSUNE_D -/* 10050 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10063 -/* 10054 */ MCD_OPC_CheckPredicate, 8, 84, 14, // Skip to: 13726 -/* 10058 */ MCD_OPC_Decode, 162, 6, 139, 1, // Opcode: FSNE_W -/* 10063 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10076 -/* 10067 */ MCD_OPC_CheckPredicate, 8, 71, 14, // Skip to: 13726 -/* 10071 */ MCD_OPC_Decode, 161, 6, 140, 1, // Opcode: FSNE_D -/* 10076 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10089 -/* 10080 */ MCD_OPC_CheckPredicate, 8, 58, 14, // Skip to: 13726 -/* 10084 */ MCD_OPC_Decode, 202, 9, 138, 1, // Opcode: MULR_Q_H -/* 10089 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10102 -/* 10093 */ MCD_OPC_CheckPredicate, 8, 45, 14, // Skip to: 13726 -/* 10097 */ MCD_OPC_Decode, 203, 9, 139, 1, // Opcode: MULR_Q_W -/* 10102 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10115 -/* 10106 */ MCD_OPC_CheckPredicate, 8, 32, 14, // Skip to: 13726 -/* 10110 */ MCD_OPC_Decode, 133, 8, 142, 1, // Opcode: MADDR_Q_H -/* 10115 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10128 -/* 10119 */ MCD_OPC_CheckPredicate, 8, 19, 14, // Skip to: 13726 -/* 10123 */ MCD_OPC_Decode, 134, 8, 143, 1, // Opcode: MADDR_Q_W -/* 10128 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10141 -/* 10132 */ MCD_OPC_CheckPredicate, 8, 6, 14, // Skip to: 13726 -/* 10136 */ MCD_OPC_Decode, 151, 9, 142, 1, // Opcode: MSUBR_Q_H -/* 10141 */ MCD_OPC_FilterValue, 29, 253, 13, // Skip to: 13726 -/* 10145 */ MCD_OPC_CheckPredicate, 8, 249, 13, // Skip to: 13726 -/* 10149 */ MCD_OPC_Decode, 152, 9, 143, 1, // Opcode: MSUBR_Q_W -/* 10154 */ MCD_OPC_FilterValue, 30, 219, 2, // Skip to: 10889 -/* 10158 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 10161 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10173 -/* 10165 */ MCD_OPC_CheckPredicate, 8, 229, 13, // Skip to: 13726 -/* 10169 */ MCD_OPC_Decode, 89, 137, 1, // Opcode: AND_V -/* 10173 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10186 -/* 10177 */ MCD_OPC_CheckPredicate, 8, 217, 13, // Skip to: 13726 -/* 10181 */ MCD_OPC_Decode, 138, 10, 137, 1, // Opcode: OR_V -/* 10186 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10199 -/* 10190 */ MCD_OPC_CheckPredicate, 8, 204, 13, // Skip to: 13726 -/* 10194 */ MCD_OPC_Decode, 254, 9, 137, 1, // Opcode: NOR_V -/* 10199 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10212 -/* 10203 */ MCD_OPC_CheckPredicate, 8, 191, 13, // Skip to: 13726 -/* 10207 */ MCD_OPC_Decode, 241, 13, 137, 1, // Opcode: XOR_V -/* 10212 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10225 -/* 10216 */ MCD_OPC_CheckPredicate, 8, 178, 13, // Skip to: 13726 -/* 10220 */ MCD_OPC_Decode, 142, 2, 141, 1, // Opcode: BMNZ_V -/* 10225 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10238 -/* 10229 */ MCD_OPC_CheckPredicate, 8, 165, 13, // Skip to: 13726 -/* 10233 */ MCD_OPC_Decode, 144, 2, 141, 1, // Opcode: BMZ_V -/* 10238 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10251 -/* 10242 */ MCD_OPC_CheckPredicate, 8, 152, 13, // Skip to: 13726 -/* 10246 */ MCD_OPC_Decode, 179, 2, 141, 1, // Opcode: BSEL_V -/* 10251 */ MCD_OPC_FilterValue, 24, 211, 0, // Skip to: 10466 -/* 10255 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 10258 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10271 -/* 10262 */ MCD_OPC_CheckPredicate, 8, 132, 13, // Skip to: 13726 -/* 10266 */ MCD_OPC_Decode, 231, 5, 181, 1, // Opcode: FILL_B -/* 10271 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10284 -/* 10275 */ MCD_OPC_CheckPredicate, 8, 119, 13, // Skip to: 13726 -/* 10279 */ MCD_OPC_Decode, 235, 5, 182, 1, // Opcode: FILL_H -/* 10284 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10297 -/* 10288 */ MCD_OPC_CheckPredicate, 8, 106, 13, // Skip to: 13726 -/* 10292 */ MCD_OPC_Decode, 236, 5, 183, 1, // Opcode: FILL_W -/* 10297 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10310 -/* 10301 */ MCD_OPC_CheckPredicate, 14, 93, 13, // Skip to: 13726 -/* 10305 */ MCD_OPC_Decode, 232, 5, 184, 1, // Opcode: FILL_D -/* 10310 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10323 -/* 10314 */ MCD_OPC_CheckPredicate, 8, 80, 13, // Skip to: 13726 -/* 10318 */ MCD_OPC_Decode, 157, 10, 173, 1, // Opcode: PCNT_B -/* 10323 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10336 -/* 10327 */ MCD_OPC_CheckPredicate, 8, 67, 13, // Skip to: 13726 -/* 10331 */ MCD_OPC_Decode, 159, 10, 185, 1, // Opcode: PCNT_H -/* 10336 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10349 -/* 10340 */ MCD_OPC_CheckPredicate, 8, 54, 13, // Skip to: 13726 -/* 10344 */ MCD_OPC_Decode, 160, 10, 186, 1, // Opcode: PCNT_W -/* 10349 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10362 -/* 10353 */ MCD_OPC_CheckPredicate, 8, 41, 13, // Skip to: 13726 -/* 10357 */ MCD_OPC_Decode, 158, 10, 187, 1, // Opcode: PCNT_D -/* 10362 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10375 -/* 10366 */ MCD_OPC_CheckPredicate, 8, 28, 13, // Skip to: 13726 -/* 10370 */ MCD_OPC_Decode, 231, 9, 173, 1, // Opcode: NLOC_B -/* 10375 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10388 -/* 10379 */ MCD_OPC_CheckPredicate, 8, 15, 13, // Skip to: 13726 -/* 10383 */ MCD_OPC_Decode, 233, 9, 185, 1, // Opcode: NLOC_H -/* 10388 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10401 -/* 10392 */ MCD_OPC_CheckPredicate, 8, 2, 13, // Skip to: 13726 -/* 10396 */ MCD_OPC_Decode, 234, 9, 186, 1, // Opcode: NLOC_W -/* 10401 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10414 -/* 10405 */ MCD_OPC_CheckPredicate, 8, 245, 12, // Skip to: 13726 -/* 10409 */ MCD_OPC_Decode, 232, 9, 187, 1, // Opcode: NLOC_D -/* 10414 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10427 -/* 10418 */ MCD_OPC_CheckPredicate, 8, 232, 12, // Skip to: 13726 -/* 10422 */ MCD_OPC_Decode, 235, 9, 173, 1, // Opcode: NLZC_B -/* 10427 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10440 -/* 10431 */ MCD_OPC_CheckPredicate, 8, 219, 12, // Skip to: 13726 -/* 10435 */ MCD_OPC_Decode, 237, 9, 185, 1, // Opcode: NLZC_H -/* 10440 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10453 -/* 10444 */ MCD_OPC_CheckPredicate, 8, 206, 12, // Skip to: 13726 -/* 10448 */ MCD_OPC_Decode, 238, 9, 186, 1, // Opcode: NLZC_W -/* 10453 */ MCD_OPC_FilterValue, 15, 197, 12, // Skip to: 13726 -/* 10457 */ MCD_OPC_CheckPredicate, 8, 193, 12, // Skip to: 13726 -/* 10461 */ MCD_OPC_Decode, 236, 9, 187, 1, // Opcode: NLZC_D -/* 10466 */ MCD_OPC_FilterValue, 25, 184, 12, // Skip to: 13726 -/* 10470 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 10473 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10486 -/* 10477 */ MCD_OPC_CheckPredicate, 8, 173, 12, // Skip to: 13726 -/* 10481 */ MCD_OPC_Decode, 182, 5, 186, 1, // Opcode: FCLASS_W -/* 10486 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10499 -/* 10490 */ MCD_OPC_CheckPredicate, 8, 160, 12, // Skip to: 13726 -/* 10494 */ MCD_OPC_Decode, 181, 5, 187, 1, // Opcode: FCLASS_D -/* 10499 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10512 -/* 10503 */ MCD_OPC_CheckPredicate, 8, 147, 12, // Skip to: 13726 -/* 10507 */ MCD_OPC_Decode, 196, 6, 186, 1, // Opcode: FTRUNC_S_W -/* 10512 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10525 -/* 10516 */ MCD_OPC_CheckPredicate, 8, 134, 12, // Skip to: 13726 -/* 10520 */ MCD_OPC_Decode, 195, 6, 187, 1, // Opcode: FTRUNC_S_D -/* 10525 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10538 -/* 10529 */ MCD_OPC_CheckPredicate, 8, 121, 12, // Skip to: 13726 -/* 10533 */ MCD_OPC_Decode, 198, 6, 186, 1, // Opcode: FTRUNC_U_W -/* 10538 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10551 -/* 10542 */ MCD_OPC_CheckPredicate, 8, 108, 12, // Skip to: 13726 -/* 10546 */ MCD_OPC_Decode, 197, 6, 187, 1, // Opcode: FTRUNC_U_D -/* 10551 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10564 -/* 10555 */ MCD_OPC_CheckPredicate, 8, 95, 12, // Skip to: 13726 -/* 10559 */ MCD_OPC_Decode, 171, 6, 186, 1, // Opcode: FSQRT_W -/* 10564 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10577 -/* 10568 */ MCD_OPC_CheckPredicate, 8, 82, 12, // Skip to: 13726 -/* 10572 */ MCD_OPC_Decode, 165, 6, 187, 1, // Opcode: FSQRT_D -/* 10577 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10590 -/* 10581 */ MCD_OPC_CheckPredicate, 8, 69, 12, // Skip to: 13726 -/* 10585 */ MCD_OPC_Decode, 152, 6, 186, 1, // Opcode: FRSQRT_W -/* 10590 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10603 -/* 10594 */ MCD_OPC_CheckPredicate, 8, 56, 12, // Skip to: 13726 -/* 10598 */ MCD_OPC_Decode, 151, 6, 187, 1, // Opcode: FRSQRT_D -/* 10603 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10616 -/* 10607 */ MCD_OPC_CheckPredicate, 8, 43, 12, // Skip to: 13726 -/* 10611 */ MCD_OPC_Decode, 148, 6, 186, 1, // Opcode: FRCP_W -/* 10616 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10629 -/* 10620 */ MCD_OPC_CheckPredicate, 8, 30, 12, // Skip to: 13726 -/* 10624 */ MCD_OPC_Decode, 147, 6, 187, 1, // Opcode: FRCP_D -/* 10629 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10642 -/* 10633 */ MCD_OPC_CheckPredicate, 8, 17, 12, // Skip to: 13726 -/* 10637 */ MCD_OPC_Decode, 150, 6, 186, 1, // Opcode: FRINT_W -/* 10642 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10655 -/* 10646 */ MCD_OPC_CheckPredicate, 8, 4, 12, // Skip to: 13726 -/* 10650 */ MCD_OPC_Decode, 149, 6, 187, 1, // Opcode: FRINT_D -/* 10655 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10668 -/* 10659 */ MCD_OPC_CheckPredicate, 8, 247, 11, // Skip to: 13726 -/* 10663 */ MCD_OPC_Decode, 238, 5, 186, 1, // Opcode: FLOG2_W -/* 10668 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 10681 -/* 10672 */ MCD_OPC_CheckPredicate, 8, 234, 11, // Skip to: 13726 -/* 10676 */ MCD_OPC_Decode, 237, 5, 187, 1, // Opcode: FLOG2_D -/* 10681 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 10694 -/* 10685 */ MCD_OPC_CheckPredicate, 8, 221, 11, // Skip to: 13726 -/* 10689 */ MCD_OPC_Decode, 220, 5, 188, 1, // Opcode: FEXUPL_W -/* 10694 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 10707 -/* 10698 */ MCD_OPC_CheckPredicate, 8, 208, 11, // Skip to: 13726 -/* 10702 */ MCD_OPC_Decode, 219, 5, 189, 1, // Opcode: FEXUPL_D -/* 10707 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10720 -/* 10711 */ MCD_OPC_CheckPredicate, 8, 195, 11, // Skip to: 13726 -/* 10715 */ MCD_OPC_Decode, 222, 5, 188, 1, // Opcode: FEXUPR_W -/* 10720 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10733 -/* 10724 */ MCD_OPC_CheckPredicate, 8, 182, 11, // Skip to: 13726 -/* 10728 */ MCD_OPC_Decode, 221, 5, 189, 1, // Opcode: FEXUPR_D -/* 10733 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10746 -/* 10737 */ MCD_OPC_CheckPredicate, 8, 169, 11, // Skip to: 13726 -/* 10741 */ MCD_OPC_Decode, 228, 5, 188, 1, // Opcode: FFQL_W -/* 10746 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10759 -/* 10750 */ MCD_OPC_CheckPredicate, 8, 156, 11, // Skip to: 13726 -/* 10754 */ MCD_OPC_Decode, 227, 5, 189, 1, // Opcode: FFQL_D -/* 10759 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10772 -/* 10763 */ MCD_OPC_CheckPredicate, 8, 143, 11, // Skip to: 13726 -/* 10767 */ MCD_OPC_Decode, 230, 5, 188, 1, // Opcode: FFQR_W -/* 10772 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10785 -/* 10776 */ MCD_OPC_CheckPredicate, 8, 130, 11, // Skip to: 13726 -/* 10780 */ MCD_OPC_Decode, 229, 5, 189, 1, // Opcode: FFQR_D -/* 10785 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10798 -/* 10789 */ MCD_OPC_CheckPredicate, 8, 117, 11, // Skip to: 13726 -/* 10793 */ MCD_OPC_Decode, 190, 6, 186, 1, // Opcode: FTINT_S_W -/* 10798 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10811 -/* 10802 */ MCD_OPC_CheckPredicate, 8, 104, 11, // Skip to: 13726 -/* 10806 */ MCD_OPC_Decode, 189, 6, 187, 1, // Opcode: FTINT_S_D -/* 10811 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10824 -/* 10815 */ MCD_OPC_CheckPredicate, 8, 91, 11, // Skip to: 13726 -/* 10819 */ MCD_OPC_Decode, 192, 6, 186, 1, // Opcode: FTINT_U_W -/* 10824 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10837 -/* 10828 */ MCD_OPC_CheckPredicate, 8, 78, 11, // Skip to: 13726 -/* 10832 */ MCD_OPC_Decode, 191, 6, 187, 1, // Opcode: FTINT_U_D -/* 10837 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10850 -/* 10841 */ MCD_OPC_CheckPredicate, 8, 65, 11, // Skip to: 13726 -/* 10845 */ MCD_OPC_Decode, 224, 5, 186, 1, // Opcode: FFINT_S_W -/* 10850 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 10863 -/* 10854 */ MCD_OPC_CheckPredicate, 8, 52, 11, // Skip to: 13726 -/* 10858 */ MCD_OPC_Decode, 223, 5, 187, 1, // Opcode: FFINT_S_D -/* 10863 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 10876 -/* 10867 */ MCD_OPC_CheckPredicate, 8, 39, 11, // Skip to: 13726 -/* 10871 */ MCD_OPC_Decode, 226, 5, 186, 1, // Opcode: FFINT_U_W -/* 10876 */ MCD_OPC_FilterValue, 31, 30, 11, // Skip to: 13726 -/* 10880 */ MCD_OPC_CheckPredicate, 8, 26, 11, // Skip to: 13726 -/* 10884 */ MCD_OPC_Decode, 225, 5, 187, 1, // Opcode: FFINT_U_D -/* 10889 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 10902 -/* 10893 */ MCD_OPC_CheckPredicate, 8, 13, 11, // Skip to: 13726 -/* 10897 */ MCD_OPC_Decode, 177, 7, 190, 1, // Opcode: LD_B -/* 10902 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 10915 -/* 10906 */ MCD_OPC_CheckPredicate, 8, 0, 11, // Skip to: 13726 -/* 10910 */ MCD_OPC_Decode, 179, 7, 190, 1, // Opcode: LD_H -/* 10915 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 10928 -/* 10919 */ MCD_OPC_CheckPredicate, 8, 243, 10, // Skip to: 13726 -/* 10923 */ MCD_OPC_Decode, 180, 7, 190, 1, // Opcode: LD_W -/* 10928 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 10941 -/* 10932 */ MCD_OPC_CheckPredicate, 8, 230, 10, // Skip to: 13726 -/* 10936 */ MCD_OPC_Decode, 178, 7, 190, 1, // Opcode: LD_D -/* 10941 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 10954 -/* 10945 */ MCD_OPC_CheckPredicate, 8, 217, 10, // Skip to: 13726 -/* 10949 */ MCD_OPC_Decode, 186, 12, 190, 1, // Opcode: ST_B -/* 10954 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 10967 -/* 10958 */ MCD_OPC_CheckPredicate, 8, 204, 10, // Skip to: 13726 -/* 10962 */ MCD_OPC_Decode, 188, 12, 190, 1, // Opcode: ST_H -/* 10967 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 10980 -/* 10971 */ MCD_OPC_CheckPredicate, 8, 191, 10, // Skip to: 13726 -/* 10975 */ MCD_OPC_Decode, 189, 12, 190, 1, // Opcode: ST_W -/* 10980 */ MCD_OPC_FilterValue, 39, 182, 10, // Skip to: 13726 -/* 10984 */ MCD_OPC_CheckPredicate, 8, 178, 10, // Skip to: 13726 -/* 10988 */ MCD_OPC_Decode, 187, 12, 190, 1, // Opcode: ST_D -/* 10993 */ MCD_OPC_FilterValue, 31, 113, 9, // Skip to: 13414 -/* 10997 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 11000 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11013 -/* 11004 */ MCD_OPC_CheckPredicate, 6, 158, 10, // Skip to: 13726 -/* 11008 */ MCD_OPC_Decode, 145, 5, 191, 1, // Opcode: EXT -/* 11013 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11026 -/* 11017 */ MCD_OPC_CheckPredicate, 6, 145, 10, // Skip to: 13726 -/* 11021 */ MCD_OPC_Decode, 228, 6, 192, 1, // Opcode: INS -/* 11026 */ MCD_OPC_FilterValue, 10, 42, 0, // Skip to: 11072 -/* 11030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11033 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11046 -/* 11037 */ MCD_OPC_CheckPredicate, 12, 125, 10, // Skip to: 13726 -/* 11041 */ MCD_OPC_Decode, 236, 7, 193, 1, // Opcode: LWX -/* 11046 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11059 -/* 11050 */ MCD_OPC_CheckPredicate, 12, 112, 10, // Skip to: 13726 -/* 11054 */ MCD_OPC_Decode, 187, 7, 193, 1, // Opcode: LHX -/* 11059 */ MCD_OPC_FilterValue, 6, 103, 10, // Skip to: 13726 -/* 11063 */ MCD_OPC_CheckPredicate, 12, 99, 10, // Skip to: 13726 -/* 11067 */ MCD_OPC_Decode, 156, 7, 193, 1, // Opcode: LBUX -/* 11072 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11091 -/* 11076 */ MCD_OPC_CheckPredicate, 12, 86, 10, // Skip to: 13726 -/* 11080 */ MCD_OPC_CheckField, 6, 10, 0, 80, 10, // Skip to: 13726 -/* 11086 */ MCD_OPC_Decode, 241, 6, 194, 1, // Opcode: INSV -/* 11091 */ MCD_OPC_FilterValue, 16, 51, 1, // Skip to: 11402 -/* 11095 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11098 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11110 -/* 11102 */ MCD_OPC_CheckPredicate, 12, 60, 10, // Skip to: 13726 -/* 11106 */ MCD_OPC_Decode, 56, 195, 1, // Opcode: ADDU_QB -/* 11110 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 11123 -/* 11114 */ MCD_OPC_CheckPredicate, 12, 48, 10, // Skip to: 13726 -/* 11118 */ MCD_OPC_Decode, 218, 12, 195, 1, // Opcode: SUBU_QB -/* 11123 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 11135 -/* 11127 */ MCD_OPC_CheckPredicate, 12, 35, 10, // Skip to: 13726 -/* 11131 */ MCD_OPC_Decode, 58, 195, 1, // Opcode: ADDU_S_QB -/* 11135 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11148 -/* 11139 */ MCD_OPC_CheckPredicate, 12, 23, 10, // Skip to: 13726 -/* 11143 */ MCD_OPC_Decode, 220, 12, 195, 1, // Opcode: SUBU_S_QB -/* 11148 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11161 -/* 11152 */ MCD_OPC_CheckPredicate, 12, 10, 10, // Skip to: 13726 -/* 11156 */ MCD_OPC_Decode, 196, 9, 195, 1, // Opcode: MULEU_S_PH_QBL -/* 11161 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 11174 -/* 11165 */ MCD_OPC_CheckPredicate, 12, 253, 9, // Skip to: 13726 -/* 11169 */ MCD_OPC_Decode, 197, 9, 195, 1, // Opcode: MULEU_S_PH_QBR -/* 11174 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 11186 -/* 11178 */ MCD_OPC_CheckPredicate, 30, 240, 9, // Skip to: 13726 -/* 11182 */ MCD_OPC_Decode, 55, 195, 1, // Opcode: ADDU_PH -/* 11186 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 11199 -/* 11190 */ MCD_OPC_CheckPredicate, 30, 228, 9, // Skip to: 13726 -/* 11194 */ MCD_OPC_Decode, 217, 12, 195, 1, // Opcode: SUBU_PH -/* 11199 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 11211 -/* 11203 */ MCD_OPC_CheckPredicate, 12, 215, 9, // Skip to: 13726 -/* 11207 */ MCD_OPC_Decode, 36, 195, 1, // Opcode: ADDQ_PH -/* 11211 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11224 -/* 11215 */ MCD_OPC_CheckPredicate, 12, 203, 9, // Skip to: 13726 -/* 11219 */ MCD_OPC_Decode, 195, 12, 195, 1, // Opcode: SUBQ_PH -/* 11224 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 11236 -/* 11228 */ MCD_OPC_CheckPredicate, 30, 190, 9, // Skip to: 13726 -/* 11232 */ MCD_OPC_Decode, 57, 195, 1, // Opcode: ADDU_S_PH -/* 11236 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11249 -/* 11240 */ MCD_OPC_CheckPredicate, 30, 178, 9, // Skip to: 13726 -/* 11244 */ MCD_OPC_Decode, 219, 12, 195, 1, // Opcode: SUBU_S_PH -/* 11249 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 11261 -/* 11253 */ MCD_OPC_CheckPredicate, 12, 165, 9, // Skip to: 13726 -/* 11257 */ MCD_OPC_Decode, 37, 195, 1, // Opcode: ADDQ_S_PH -/* 11261 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11274 -/* 11265 */ MCD_OPC_CheckPredicate, 12, 153, 9, // Skip to: 13726 -/* 11269 */ MCD_OPC_Decode, 196, 12, 195, 1, // Opcode: SUBQ_S_PH -/* 11274 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 11285 -/* 11278 */ MCD_OPC_CheckPredicate, 12, 140, 9, // Skip to: 13726 -/* 11282 */ MCD_OPC_Decode, 39, 35, // Opcode: ADDSC -/* 11285 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 11296 -/* 11289 */ MCD_OPC_CheckPredicate, 12, 129, 9, // Skip to: 13726 -/* 11293 */ MCD_OPC_Decode, 67, 35, // Opcode: ADDWC -/* 11296 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 11308 -/* 11300 */ MCD_OPC_CheckPredicate, 12, 118, 9, // Skip to: 13726 -/* 11304 */ MCD_OPC_Decode, 223, 8, 35, // Opcode: MODSUB -/* 11308 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 11327 -/* 11312 */ MCD_OPC_CheckPredicate, 12, 106, 9, // Skip to: 13726 -/* 11316 */ MCD_OPC_CheckField, 16, 5, 0, 100, 9, // Skip to: 13726 -/* 11322 */ MCD_OPC_Decode, 236, 10, 196, 1, // Opcode: RADDU_W_QB -/* 11327 */ MCD_OPC_FilterValue, 22, 7, 0, // Skip to: 11338 -/* 11331 */ MCD_OPC_CheckPredicate, 12, 87, 9, // Skip to: 13726 -/* 11335 */ MCD_OPC_Decode, 38, 35, // Opcode: ADDQ_S_W -/* 11338 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 11350 -/* 11342 */ MCD_OPC_CheckPredicate, 12, 76, 9, // Skip to: 13726 -/* 11346 */ MCD_OPC_Decode, 197, 12, 35, // Opcode: SUBQ_S_W -/* 11350 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 11363 -/* 11354 */ MCD_OPC_CheckPredicate, 12, 64, 9, // Skip to: 13726 -/* 11358 */ MCD_OPC_Decode, 194, 9, 197, 1, // Opcode: MULEQ_S_W_PHL -/* 11363 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 11376 -/* 11367 */ MCD_OPC_CheckPredicate, 12, 51, 9, // Skip to: 13726 -/* 11371 */ MCD_OPC_Decode, 195, 9, 197, 1, // Opcode: MULEQ_S_W_PHR -/* 11376 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11389 -/* 11380 */ MCD_OPC_CheckPredicate, 30, 38, 9, // Skip to: 13726 -/* 11384 */ MCD_OPC_Decode, 200, 9, 195, 1, // Opcode: MULQ_S_PH -/* 11389 */ MCD_OPC_FilterValue, 31, 29, 9, // Skip to: 13726 -/* 11393 */ MCD_OPC_CheckPredicate, 12, 25, 9, // Skip to: 13726 -/* 11397 */ MCD_OPC_Decode, 198, 9, 195, 1, // Opcode: MULQ_RS_PH -/* 11402 */ MCD_OPC_FilterValue, 17, 69, 1, // Skip to: 11731 -/* 11406 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11409 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11428 -/* 11413 */ MCD_OPC_CheckPredicate, 12, 5, 9, // Skip to: 13726 -/* 11417 */ MCD_OPC_CheckField, 11, 5, 0, 255, 8, // Skip to: 13726 -/* 11423 */ MCD_OPC_Decode, 161, 3, 198, 1, // Opcode: CMPU_EQ_QB -/* 11428 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11447 -/* 11432 */ MCD_OPC_CheckPredicate, 12, 242, 8, // Skip to: 13726 -/* 11436 */ MCD_OPC_CheckField, 11, 5, 0, 236, 8, // Skip to: 13726 -/* 11442 */ MCD_OPC_Decode, 163, 3, 198, 1, // Opcode: CMPU_LT_QB -/* 11447 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 11466 -/* 11451 */ MCD_OPC_CheckPredicate, 12, 223, 8, // Skip to: 13726 -/* 11455 */ MCD_OPC_CheckField, 11, 5, 0, 217, 8, // Skip to: 13726 -/* 11461 */ MCD_OPC_Decode, 162, 3, 198, 1, // Opcode: CMPU_LE_QB -/* 11466 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11479 -/* 11470 */ MCD_OPC_CheckPredicate, 12, 204, 8, // Skip to: 13726 -/* 11474 */ MCD_OPC_Decode, 162, 10, 195, 1, // Opcode: PICK_QB -/* 11479 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11492 -/* 11483 */ MCD_OPC_CheckPredicate, 12, 191, 8, // Skip to: 13726 -/* 11487 */ MCD_OPC_Decode, 158, 3, 197, 1, // Opcode: CMPGU_EQ_QB -/* 11492 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11505 -/* 11496 */ MCD_OPC_CheckPredicate, 12, 178, 8, // Skip to: 13726 -/* 11500 */ MCD_OPC_Decode, 160, 3, 197, 1, // Opcode: CMPGU_LT_QB -/* 11505 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11518 -/* 11509 */ MCD_OPC_CheckPredicate, 12, 165, 8, // Skip to: 13726 -/* 11513 */ MCD_OPC_Decode, 159, 3, 197, 1, // Opcode: CMPGU_LE_QB -/* 11518 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 11537 -/* 11522 */ MCD_OPC_CheckPredicate, 12, 152, 8, // Skip to: 13726 -/* 11526 */ MCD_OPC_CheckField, 11, 5, 0, 146, 8, // Skip to: 13726 -/* 11532 */ MCD_OPC_Decode, 165, 3, 198, 1, // Opcode: CMP_EQ_PH -/* 11537 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 11556 -/* 11541 */ MCD_OPC_CheckPredicate, 12, 133, 8, // Skip to: 13726 -/* 11545 */ MCD_OPC_CheckField, 11, 5, 0, 127, 8, // Skip to: 13726 -/* 11551 */ MCD_OPC_Decode, 173, 3, 198, 1, // Opcode: CMP_LT_PH -/* 11556 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 11575 -/* 11560 */ MCD_OPC_CheckPredicate, 12, 114, 8, // Skip to: 13726 -/* 11564 */ MCD_OPC_CheckField, 11, 5, 0, 108, 8, // Skip to: 13726 -/* 11570 */ MCD_OPC_Decode, 170, 3, 198, 1, // Opcode: CMP_LE_PH -/* 11575 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11588 -/* 11579 */ MCD_OPC_CheckPredicate, 12, 95, 8, // Skip to: 13726 -/* 11583 */ MCD_OPC_Decode, 161, 10, 195, 1, // Opcode: PICK_PH -/* 11588 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 11601 -/* 11592 */ MCD_OPC_CheckPredicate, 12, 82, 8, // Skip to: 13726 -/* 11596 */ MCD_OPC_Decode, 176, 10, 195, 1, // Opcode: PRECRQ_QB_PH -/* 11601 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11614 -/* 11605 */ MCD_OPC_CheckPredicate, 30, 69, 8, // Skip to: 13726 -/* 11609 */ MCD_OPC_Decode, 178, 10, 195, 1, // Opcode: PRECR_QB_PH -/* 11614 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 11627 -/* 11618 */ MCD_OPC_CheckPredicate, 12, 56, 8, // Skip to: 13726 -/* 11622 */ MCD_OPC_Decode, 146, 10, 195, 1, // Opcode: PACKRL_PH -/* 11627 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11640 -/* 11631 */ MCD_OPC_CheckPredicate, 12, 43, 8, // Skip to: 13726 -/* 11635 */ MCD_OPC_Decode, 174, 10, 195, 1, // Opcode: PRECRQU_S_QB_PH -/* 11640 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 11653 -/* 11644 */ MCD_OPC_CheckPredicate, 12, 30, 8, // Skip to: 13726 -/* 11648 */ MCD_OPC_Decode, 175, 10, 199, 1, // Opcode: PRECRQ_PH_W -/* 11653 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 11666 -/* 11657 */ MCD_OPC_CheckPredicate, 12, 17, 8, // Skip to: 13726 -/* 11661 */ MCD_OPC_Decode, 177, 10, 199, 1, // Opcode: PRECRQ_RS_PH_W -/* 11666 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 11679 -/* 11670 */ MCD_OPC_CheckPredicate, 30, 4, 8, // Skip to: 13726 -/* 11674 */ MCD_OPC_Decode, 155, 3, 197, 1, // Opcode: CMPGDU_EQ_QB -/* 11679 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 11692 -/* 11683 */ MCD_OPC_CheckPredicate, 30, 247, 7, // Skip to: 13726 -/* 11687 */ MCD_OPC_Decode, 157, 3, 197, 1, // Opcode: CMPGDU_LT_QB -/* 11692 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 11705 -/* 11696 */ MCD_OPC_CheckPredicate, 30, 234, 7, // Skip to: 13726 -/* 11700 */ MCD_OPC_Decode, 156, 3, 197, 1, // Opcode: CMPGDU_LE_QB -/* 11705 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11718 -/* 11709 */ MCD_OPC_CheckPredicate, 30, 221, 7, // Skip to: 13726 -/* 11713 */ MCD_OPC_Decode, 179, 10, 200, 1, // Opcode: PRECR_SRA_PH_W -/* 11718 */ MCD_OPC_FilterValue, 31, 212, 7, // Skip to: 13726 -/* 11722 */ MCD_OPC_CheckPredicate, 30, 208, 7, // Skip to: 13726 -/* 11726 */ MCD_OPC_Decode, 180, 10, 200, 1, // Opcode: PRECR_SRA_R_PH_W -/* 11731 */ MCD_OPC_FilterValue, 18, 74, 1, // Skip to: 12065 -/* 11735 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11738 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11756 -/* 11742 */ MCD_OPC_CheckPredicate, 30, 188, 7, // Skip to: 13726 -/* 11746 */ MCD_OPC_CheckField, 21, 5, 0, 182, 7, // Skip to: 13726 -/* 11752 */ MCD_OPC_Decode, 23, 201, 1, // Opcode: ABSQ_S_QB -/* 11756 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11769 -/* 11760 */ MCD_OPC_CheckPredicate, 12, 170, 7, // Skip to: 13726 -/* 11764 */ MCD_OPC_Decode, 244, 10, 202, 1, // Opcode: REPL_QB -/* 11769 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 11788 -/* 11773 */ MCD_OPC_CheckPredicate, 12, 157, 7, // Skip to: 13726 -/* 11777 */ MCD_OPC_CheckField, 21, 5, 0, 151, 7, // Skip to: 13726 -/* 11783 */ MCD_OPC_Decode, 242, 10, 203, 1, // Opcode: REPLV_QB -/* 11788 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 11807 -/* 11792 */ MCD_OPC_CheckPredicate, 12, 138, 7, // Skip to: 13726 -/* 11796 */ MCD_OPC_CheckField, 21, 5, 0, 132, 7, // Skip to: 13726 -/* 11802 */ MCD_OPC_Decode, 164, 10, 201, 1, // Opcode: PRECEQU_PH_QBL -/* 11807 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 11826 -/* 11811 */ MCD_OPC_CheckPredicate, 12, 119, 7, // Skip to: 13726 -/* 11815 */ MCD_OPC_CheckField, 21, 5, 0, 113, 7, // Skip to: 13726 -/* 11821 */ MCD_OPC_Decode, 166, 10, 201, 1, // Opcode: PRECEQU_PH_QBR -/* 11826 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 11845 -/* 11830 */ MCD_OPC_CheckPredicate, 12, 100, 7, // Skip to: 13726 -/* 11834 */ MCD_OPC_CheckField, 21, 5, 0, 94, 7, // Skip to: 13726 -/* 11840 */ MCD_OPC_Decode, 165, 10, 201, 1, // Opcode: PRECEQU_PH_QBLA -/* 11845 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 11864 -/* 11849 */ MCD_OPC_CheckPredicate, 12, 81, 7, // Skip to: 13726 -/* 11853 */ MCD_OPC_CheckField, 21, 5, 0, 75, 7, // Skip to: 13726 -/* 11859 */ MCD_OPC_Decode, 167, 10, 201, 1, // Opcode: PRECEQU_PH_QBRA -/* 11864 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 11882 -/* 11868 */ MCD_OPC_CheckPredicate, 12, 62, 7, // Skip to: 13726 -/* 11872 */ MCD_OPC_CheckField, 21, 5, 0, 56, 7, // Skip to: 13726 -/* 11878 */ MCD_OPC_Decode, 22, 201, 1, // Opcode: ABSQ_S_PH -/* 11882 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 11895 -/* 11886 */ MCD_OPC_CheckPredicate, 12, 44, 7, // Skip to: 13726 -/* 11890 */ MCD_OPC_Decode, 243, 10, 202, 1, // Opcode: REPL_PH -/* 11895 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 11914 -/* 11899 */ MCD_OPC_CheckPredicate, 12, 31, 7, // Skip to: 13726 -/* 11903 */ MCD_OPC_CheckField, 21, 5, 0, 25, 7, // Skip to: 13726 -/* 11909 */ MCD_OPC_Decode, 241, 10, 203, 1, // Opcode: REPLV_PH -/* 11914 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11933 -/* 11918 */ MCD_OPC_CheckPredicate, 12, 12, 7, // Skip to: 13726 -/* 11922 */ MCD_OPC_CheckField, 21, 5, 0, 6, 7, // Skip to: 13726 -/* 11928 */ MCD_OPC_Decode, 168, 10, 204, 1, // Opcode: PRECEQ_W_PHL -/* 11933 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 11952 -/* 11937 */ MCD_OPC_CheckPredicate, 12, 249, 6, // Skip to: 13726 -/* 11941 */ MCD_OPC_CheckField, 21, 5, 0, 243, 6, // Skip to: 13726 -/* 11947 */ MCD_OPC_Decode, 169, 10, 204, 1, // Opcode: PRECEQ_W_PHR -/* 11952 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 11970 -/* 11956 */ MCD_OPC_CheckPredicate, 12, 230, 6, // Skip to: 13726 -/* 11960 */ MCD_OPC_CheckField, 21, 5, 0, 224, 6, // Skip to: 13726 -/* 11966 */ MCD_OPC_Decode, 24, 205, 1, // Opcode: ABSQ_S_W -/* 11970 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 11989 -/* 11974 */ MCD_OPC_CheckPredicate, 12, 212, 6, // Skip to: 13726 -/* 11978 */ MCD_OPC_CheckField, 21, 5, 0, 206, 6, // Skip to: 13726 -/* 11984 */ MCD_OPC_Decode, 249, 1, 205, 1, // Opcode: BITREV -/* 11989 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 12008 -/* 11993 */ MCD_OPC_CheckPredicate, 12, 193, 6, // Skip to: 13726 -/* 11997 */ MCD_OPC_CheckField, 21, 5, 0, 187, 6, // Skip to: 13726 -/* 12003 */ MCD_OPC_Decode, 170, 10, 201, 1, // Opcode: PRECEU_PH_QBL -/* 12008 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 12027 -/* 12012 */ MCD_OPC_CheckPredicate, 12, 174, 6, // Skip to: 13726 -/* 12016 */ MCD_OPC_CheckField, 21, 5, 0, 168, 6, // Skip to: 13726 -/* 12022 */ MCD_OPC_Decode, 172, 10, 201, 1, // Opcode: PRECEU_PH_QBR -/* 12027 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 12046 -/* 12031 */ MCD_OPC_CheckPredicate, 12, 155, 6, // Skip to: 13726 -/* 12035 */ MCD_OPC_CheckField, 21, 5, 0, 149, 6, // Skip to: 13726 -/* 12041 */ MCD_OPC_Decode, 171, 10, 201, 1, // Opcode: PRECEU_PH_QBLA -/* 12046 */ MCD_OPC_FilterValue, 31, 140, 6, // Skip to: 13726 -/* 12050 */ MCD_OPC_CheckPredicate, 12, 136, 6, // Skip to: 13726 -/* 12054 */ MCD_OPC_CheckField, 21, 5, 0, 130, 6, // Skip to: 13726 -/* 12060 */ MCD_OPC_Decode, 173, 10, 201, 1, // Opcode: PRECEU_PH_QBRA -/* 12065 */ MCD_OPC_FilterValue, 19, 31, 1, // Skip to: 12356 -/* 12069 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12072 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12085 -/* 12076 */ MCD_OPC_CheckPredicate, 12, 110, 6, // Skip to: 13726 -/* 12080 */ MCD_OPC_Decode, 199, 11, 206, 1, // Opcode: SHLL_QB -/* 12085 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12098 -/* 12089 */ MCD_OPC_CheckPredicate, 12, 97, 6, // Skip to: 13726 -/* 12093 */ MCD_OPC_Decode, 215, 11, 206, 1, // Opcode: SHRL_QB -/* 12098 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12111 -/* 12102 */ MCD_OPC_CheckPredicate, 12, 84, 6, // Skip to: 13726 -/* 12106 */ MCD_OPC_Decode, 195, 11, 207, 1, // Opcode: SHLLV_QB -/* 12111 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12124 -/* 12115 */ MCD_OPC_CheckPredicate, 12, 71, 6, // Skip to: 13726 -/* 12119 */ MCD_OPC_Decode, 213, 11, 207, 1, // Opcode: SHRLV_QB -/* 12124 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12137 -/* 12128 */ MCD_OPC_CheckPredicate, 30, 58, 6, // Skip to: 13726 -/* 12132 */ MCD_OPC_Decode, 208, 11, 206, 1, // Opcode: SHRA_QB -/* 12137 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 12150 -/* 12141 */ MCD_OPC_CheckPredicate, 30, 45, 6, // Skip to: 13726 -/* 12145 */ MCD_OPC_Decode, 210, 11, 206, 1, // Opcode: SHRA_R_QB -/* 12150 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 12163 -/* 12154 */ MCD_OPC_CheckPredicate, 30, 32, 6, // Skip to: 13726 -/* 12158 */ MCD_OPC_Decode, 203, 11, 207, 1, // Opcode: SHRAV_QB -/* 12163 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 12176 -/* 12167 */ MCD_OPC_CheckPredicate, 30, 19, 6, // Skip to: 13726 -/* 12171 */ MCD_OPC_Decode, 205, 11, 207, 1, // Opcode: SHRAV_R_QB -/* 12176 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 12189 -/* 12180 */ MCD_OPC_CheckPredicate, 12, 6, 6, // Skip to: 13726 -/* 12184 */ MCD_OPC_Decode, 198, 11, 206, 1, // Opcode: SHLL_PH -/* 12189 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12202 -/* 12193 */ MCD_OPC_CheckPredicate, 12, 249, 5, // Skip to: 13726 -/* 12197 */ MCD_OPC_Decode, 207, 11, 206, 1, // Opcode: SHRA_PH -/* 12202 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 12215 -/* 12206 */ MCD_OPC_CheckPredicate, 12, 236, 5, // Skip to: 13726 -/* 12210 */ MCD_OPC_Decode, 194, 11, 207, 1, // Opcode: SHLLV_PH -/* 12215 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12228 -/* 12219 */ MCD_OPC_CheckPredicate, 12, 223, 5, // Skip to: 13726 -/* 12223 */ MCD_OPC_Decode, 202, 11, 207, 1, // Opcode: SHRAV_PH -/* 12228 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12241 -/* 12232 */ MCD_OPC_CheckPredicate, 12, 210, 5, // Skip to: 13726 -/* 12236 */ MCD_OPC_Decode, 200, 11, 206, 1, // Opcode: SHLL_S_PH -/* 12241 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 12254 -/* 12245 */ MCD_OPC_CheckPredicate, 12, 197, 5, // Skip to: 13726 -/* 12249 */ MCD_OPC_Decode, 209, 11, 206, 1, // Opcode: SHRA_R_PH -/* 12254 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12267 -/* 12258 */ MCD_OPC_CheckPredicate, 12, 184, 5, // Skip to: 13726 -/* 12262 */ MCD_OPC_Decode, 196, 11, 207, 1, // Opcode: SHLLV_S_PH -/* 12267 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 12280 -/* 12271 */ MCD_OPC_CheckPredicate, 12, 171, 5, // Skip to: 13726 -/* 12275 */ MCD_OPC_Decode, 204, 11, 207, 1, // Opcode: SHRAV_R_PH -/* 12280 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 12293 -/* 12284 */ MCD_OPC_CheckPredicate, 12, 158, 5, // Skip to: 13726 -/* 12288 */ MCD_OPC_Decode, 201, 11, 208, 1, // Opcode: SHLL_S_W -/* 12293 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 12306 -/* 12297 */ MCD_OPC_CheckPredicate, 12, 145, 5, // Skip to: 13726 -/* 12301 */ MCD_OPC_Decode, 211, 11, 208, 1, // Opcode: SHRA_R_W -/* 12306 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12318 -/* 12310 */ MCD_OPC_CheckPredicate, 12, 132, 5, // Skip to: 13726 -/* 12314 */ MCD_OPC_Decode, 197, 11, 36, // Opcode: SHLLV_S_W -/* 12318 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 12330 -/* 12322 */ MCD_OPC_CheckPredicate, 12, 120, 5, // Skip to: 13726 -/* 12326 */ MCD_OPC_Decode, 206, 11, 36, // Opcode: SHRAV_R_W -/* 12330 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 12343 -/* 12334 */ MCD_OPC_CheckPredicate, 30, 108, 5, // Skip to: 13726 -/* 12338 */ MCD_OPC_Decode, 214, 11, 206, 1, // Opcode: SHRL_PH -/* 12343 */ MCD_OPC_FilterValue, 27, 99, 5, // Skip to: 13726 -/* 12347 */ MCD_OPC_CheckPredicate, 30, 95, 5, // Skip to: 13726 -/* 12351 */ MCD_OPC_Decode, 212, 11, 207, 1, // Opcode: SHRLV_PH -/* 12356 */ MCD_OPC_FilterValue, 24, 199, 0, // Skip to: 12559 -/* 12360 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12363 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12375 -/* 12367 */ MCD_OPC_CheckPredicate, 30, 75, 5, // Skip to: 13726 -/* 12371 */ MCD_OPC_Decode, 53, 195, 1, // Opcode: ADDUH_QB -/* 12375 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12388 -/* 12379 */ MCD_OPC_CheckPredicate, 30, 63, 5, // Skip to: 13726 -/* 12383 */ MCD_OPC_Decode, 215, 12, 195, 1, // Opcode: SUBUH_QB -/* 12388 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 12400 -/* 12392 */ MCD_OPC_CheckPredicate, 30, 50, 5, // Skip to: 13726 -/* 12396 */ MCD_OPC_Decode, 54, 195, 1, // Opcode: ADDUH_R_QB -/* 12400 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12413 -/* 12404 */ MCD_OPC_CheckPredicate, 30, 38, 5, // Skip to: 13726 -/* 12408 */ MCD_OPC_Decode, 216, 12, 195, 1, // Opcode: SUBUH_R_QB -/* 12413 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 12425 -/* 12417 */ MCD_OPC_CheckPredicate, 30, 25, 5, // Skip to: 13726 -/* 12421 */ MCD_OPC_Decode, 32, 195, 1, // Opcode: ADDQH_PH -/* 12425 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12438 -/* 12429 */ MCD_OPC_CheckPredicate, 30, 13, 5, // Skip to: 13726 -/* 12433 */ MCD_OPC_Decode, 191, 12, 195, 1, // Opcode: SUBQH_PH -/* 12438 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 12450 -/* 12442 */ MCD_OPC_CheckPredicate, 30, 0, 5, // Skip to: 13726 -/* 12446 */ MCD_OPC_Decode, 33, 195, 1, // Opcode: ADDQH_R_PH -/* 12450 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12463 -/* 12454 */ MCD_OPC_CheckPredicate, 30, 244, 4, // Skip to: 13726 -/* 12458 */ MCD_OPC_Decode, 192, 12, 195, 1, // Opcode: SUBQH_R_PH -/* 12463 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12476 -/* 12467 */ MCD_OPC_CheckPredicate, 30, 231, 4, // Skip to: 13726 -/* 12471 */ MCD_OPC_Decode, 218, 9, 195, 1, // Opcode: MUL_PH -/* 12476 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12489 -/* 12480 */ MCD_OPC_CheckPredicate, 30, 218, 4, // Skip to: 13726 -/* 12484 */ MCD_OPC_Decode, 222, 9, 195, 1, // Opcode: MUL_S_PH -/* 12489 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 12500 -/* 12493 */ MCD_OPC_CheckPredicate, 30, 205, 4, // Skip to: 13726 -/* 12497 */ MCD_OPC_Decode, 35, 35, // Opcode: ADDQH_W -/* 12500 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 12512 -/* 12504 */ MCD_OPC_CheckPredicate, 30, 194, 4, // Skip to: 13726 -/* 12508 */ MCD_OPC_Decode, 194, 12, 35, // Opcode: SUBQH_W -/* 12512 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 12523 -/* 12516 */ MCD_OPC_CheckPredicate, 30, 182, 4, // Skip to: 13726 -/* 12520 */ MCD_OPC_Decode, 34, 35, // Opcode: ADDQH_R_W -/* 12523 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 12535 -/* 12527 */ MCD_OPC_CheckPredicate, 30, 171, 4, // Skip to: 13726 -/* 12531 */ MCD_OPC_Decode, 193, 12, 35, // Opcode: SUBQH_R_W -/* 12535 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12547 -/* 12539 */ MCD_OPC_CheckPredicate, 30, 159, 4, // Skip to: 13726 -/* 12543 */ MCD_OPC_Decode, 201, 9, 35, // Opcode: MULQ_S_W -/* 12547 */ MCD_OPC_FilterValue, 23, 151, 4, // Skip to: 13726 -/* 12551 */ MCD_OPC_CheckPredicate, 30, 147, 4, // Skip to: 13726 -/* 12555 */ MCD_OPC_Decode, 199, 9, 35, // Opcode: MULQ_RS_W -/* 12559 */ MCD_OPC_FilterValue, 32, 60, 0, // Skip to: 12623 -/* 12563 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12566 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 12585 -/* 12570 */ MCD_OPC_CheckPredicate, 6, 128, 4, // Skip to: 13726 -/* 12574 */ MCD_OPC_CheckField, 21, 5, 0, 122, 4, // Skip to: 13726 -/* 12580 */ MCD_OPC_Decode, 234, 13, 205, 1, // Opcode: WSBH -/* 12585 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 12604 -/* 12589 */ MCD_OPC_CheckPredicate, 6, 109, 4, // Skip to: 13726 -/* 12593 */ MCD_OPC_CheckField, 21, 5, 0, 103, 4, // Skip to: 13726 -/* 12599 */ MCD_OPC_Decode, 168, 11, 205, 1, // Opcode: SEB -/* 12604 */ MCD_OPC_FilterValue, 24, 94, 4, // Skip to: 13726 -/* 12608 */ MCD_OPC_CheckPredicate, 6, 90, 4, // Skip to: 13726 -/* 12612 */ MCD_OPC_CheckField, 21, 5, 0, 84, 4, // Skip to: 13726 -/* 12618 */ MCD_OPC_Decode, 171, 11, 205, 1, // Opcode: SEH -/* 12623 */ MCD_OPC_FilterValue, 48, 143, 1, // Skip to: 13026 -/* 12627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12630 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12648 -/* 12634 */ MCD_OPC_CheckPredicate, 30, 64, 4, // Skip to: 13726 -/* 12638 */ MCD_OPC_CheckField, 13, 3, 0, 58, 4, // Skip to: 13726 -/* 12644 */ MCD_OPC_Decode, 230, 4, 116, // Opcode: DPA_W_PH -/* 12648 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12666 -/* 12652 */ MCD_OPC_CheckPredicate, 30, 46, 4, // Skip to: 13726 -/* 12656 */ MCD_OPC_CheckField, 13, 3, 0, 40, 4, // Skip to: 13726 -/* 12662 */ MCD_OPC_Decode, 245, 4, 116, // Opcode: DPS_W_PH -/* 12666 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12684 -/* 12670 */ MCD_OPC_CheckPredicate, 30, 28, 4, // Skip to: 13726 -/* 12674 */ MCD_OPC_CheckField, 13, 3, 0, 22, 4, // Skip to: 13726 -/* 12680 */ MCD_OPC_Decode, 205, 9, 116, // Opcode: MULSA_W_PH -/* 12684 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 12702 -/* 12688 */ MCD_OPC_CheckPredicate, 12, 10, 4, // Skip to: 13726 -/* 12692 */ MCD_OPC_CheckField, 13, 3, 0, 4, 4, // Skip to: 13726 -/* 12698 */ MCD_OPC_Decode, 227, 4, 116, // Opcode: DPAU_H_QBL -/* 12702 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12720 -/* 12706 */ MCD_OPC_CheckPredicate, 12, 248, 3, // Skip to: 13726 -/* 12710 */ MCD_OPC_CheckField, 13, 3, 0, 242, 3, // Skip to: 13726 -/* 12716 */ MCD_OPC_Decode, 226, 4, 116, // Opcode: DPAQ_S_W_PH -/* 12720 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 12738 -/* 12724 */ MCD_OPC_CheckPredicate, 12, 230, 3, // Skip to: 13726 -/* 12728 */ MCD_OPC_CheckField, 13, 3, 0, 224, 3, // Skip to: 13726 -/* 12734 */ MCD_OPC_Decode, 235, 4, 116, // Opcode: DPSQ_S_W_PH -/* 12738 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 12756 -/* 12742 */ MCD_OPC_CheckPredicate, 12, 212, 3, // Skip to: 13726 -/* 12746 */ MCD_OPC_CheckField, 13, 3, 0, 206, 3, // Skip to: 13726 -/* 12752 */ MCD_OPC_Decode, 204, 9, 116, // Opcode: MULSAQ_S_W_PH -/* 12756 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 12774 -/* 12760 */ MCD_OPC_CheckPredicate, 12, 194, 3, // Skip to: 13726 -/* 12764 */ MCD_OPC_CheckField, 13, 3, 0, 188, 3, // Skip to: 13726 -/* 12770 */ MCD_OPC_Decode, 228, 4, 116, // Opcode: DPAU_H_QBR -/* 12774 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12792 -/* 12778 */ MCD_OPC_CheckPredicate, 30, 176, 3, // Skip to: 13726 -/* 12782 */ MCD_OPC_CheckField, 13, 3, 0, 170, 3, // Skip to: 13726 -/* 12788 */ MCD_OPC_Decode, 229, 4, 116, // Opcode: DPAX_W_PH -/* 12792 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 12810 -/* 12796 */ MCD_OPC_CheckPredicate, 30, 158, 3, // Skip to: 13726 -/* 12800 */ MCD_OPC_CheckField, 13, 3, 0, 152, 3, // Skip to: 13726 -/* 12806 */ MCD_OPC_Decode, 244, 4, 116, // Opcode: DPSX_W_PH -/* 12810 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12828 -/* 12814 */ MCD_OPC_CheckPredicate, 12, 140, 3, // Skip to: 13726 -/* 12818 */ MCD_OPC_CheckField, 13, 3, 0, 134, 3, // Skip to: 13726 -/* 12824 */ MCD_OPC_Decode, 242, 4, 116, // Opcode: DPSU_H_QBL -/* 12828 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 12846 -/* 12832 */ MCD_OPC_CheckPredicate, 12, 122, 3, // Skip to: 13726 -/* 12836 */ MCD_OPC_CheckField, 13, 3, 0, 116, 3, // Skip to: 13726 -/* 12842 */ MCD_OPC_Decode, 225, 4, 116, // Opcode: DPAQ_SA_L_W -/* 12846 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12864 -/* 12850 */ MCD_OPC_CheckPredicate, 12, 104, 3, // Skip to: 13726 -/* 12854 */ MCD_OPC_CheckField, 13, 3, 0, 98, 3, // Skip to: 13726 -/* 12860 */ MCD_OPC_Decode, 234, 4, 116, // Opcode: DPSQ_SA_L_W -/* 12864 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 12882 -/* 12868 */ MCD_OPC_CheckPredicate, 12, 86, 3, // Skip to: 13726 -/* 12872 */ MCD_OPC_CheckField, 13, 3, 0, 80, 3, // Skip to: 13726 -/* 12878 */ MCD_OPC_Decode, 243, 4, 116, // Opcode: DPSU_H_QBR -/* 12882 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 12900 -/* 12886 */ MCD_OPC_CheckPredicate, 12, 68, 3, // Skip to: 13726 -/* 12890 */ MCD_OPC_CheckField, 13, 3, 0, 62, 3, // Skip to: 13726 -/* 12896 */ MCD_OPC_Decode, 151, 8, 116, // Opcode: MAQ_SA_W_PHL -/* 12900 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 12918 -/* 12904 */ MCD_OPC_CheckPredicate, 12, 50, 3, // Skip to: 13726 -/* 12908 */ MCD_OPC_CheckField, 13, 3, 0, 44, 3, // Skip to: 13726 -/* 12914 */ MCD_OPC_Decode, 152, 8, 116, // Opcode: MAQ_SA_W_PHR -/* 12918 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 12936 -/* 12922 */ MCD_OPC_CheckPredicate, 12, 32, 3, // Skip to: 13726 -/* 12926 */ MCD_OPC_CheckField, 13, 3, 0, 26, 3, // Skip to: 13726 -/* 12932 */ MCD_OPC_Decode, 153, 8, 116, // Opcode: MAQ_S_W_PHL -/* 12936 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 12954 -/* 12940 */ MCD_OPC_CheckPredicate, 12, 14, 3, // Skip to: 13726 -/* 12944 */ MCD_OPC_CheckField, 13, 3, 0, 8, 3, // Skip to: 13726 -/* 12950 */ MCD_OPC_Decode, 154, 8, 116, // Opcode: MAQ_S_W_PHR -/* 12954 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 12972 -/* 12958 */ MCD_OPC_CheckPredicate, 30, 252, 2, // Skip to: 13726 -/* 12962 */ MCD_OPC_CheckField, 13, 3, 0, 246, 2, // Skip to: 13726 -/* 12968 */ MCD_OPC_Decode, 224, 4, 116, // Opcode: DPAQX_S_W_PH -/* 12972 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 12990 -/* 12976 */ MCD_OPC_CheckPredicate, 30, 234, 2, // Skip to: 13726 -/* 12980 */ MCD_OPC_CheckField, 13, 3, 0, 228, 2, // Skip to: 13726 -/* 12986 */ MCD_OPC_Decode, 233, 4, 116, // Opcode: DPSQX_S_W_PH -/* 12990 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 13008 -/* 12994 */ MCD_OPC_CheckPredicate, 30, 216, 2, // Skip to: 13726 -/* 12998 */ MCD_OPC_CheckField, 13, 3, 0, 210, 2, // Skip to: 13726 -/* 13004 */ MCD_OPC_Decode, 223, 4, 116, // Opcode: DPAQX_SA_W_PH -/* 13008 */ MCD_OPC_FilterValue, 27, 202, 2, // Skip to: 13726 -/* 13012 */ MCD_OPC_CheckPredicate, 30, 198, 2, // Skip to: 13726 -/* 13016 */ MCD_OPC_CheckField, 13, 3, 0, 192, 2, // Skip to: 13726 -/* 13022 */ MCD_OPC_Decode, 232, 4, 116, // Opcode: DPSQX_SA_W_PH -/* 13026 */ MCD_OPC_FilterValue, 49, 41, 0, // Skip to: 13071 -/* 13030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 13033 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13045 -/* 13037 */ MCD_OPC_CheckPredicate, 30, 173, 2, // Skip to: 13726 -/* 13041 */ MCD_OPC_Decode, 96, 209, 1, // Opcode: APPEND -/* 13045 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13058 -/* 13049 */ MCD_OPC_CheckPredicate, 30, 161, 2, // Skip to: 13726 -/* 13053 */ MCD_OPC_Decode, 184, 10, 209, 1, // Opcode: PREPEND -/* 13058 */ MCD_OPC_FilterValue, 16, 152, 2, // Skip to: 13726 -/* 13062 */ MCD_OPC_CheckPredicate, 30, 148, 2, // Skip to: 13726 -/* 13066 */ MCD_OPC_Decode, 169, 1, 209, 1, // Opcode: BALIGN -/* 13071 */ MCD_OPC_FilterValue, 56, 58, 1, // Skip to: 13389 -/* 13075 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 13078 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13097 -/* 13082 */ MCD_OPC_CheckPredicate, 12, 128, 2, // Skip to: 13726 -/* 13086 */ MCD_OPC_CheckField, 13, 3, 0, 122, 2, // Skip to: 13726 -/* 13092 */ MCD_OPC_Decode, 157, 5, 210, 1, // Opcode: EXTR_W -/* 13097 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 13116 -/* 13101 */ MCD_OPC_CheckPredicate, 12, 109, 2, // Skip to: 13726 -/* 13105 */ MCD_OPC_CheckField, 13, 3, 0, 103, 2, // Skip to: 13726 -/* 13111 */ MCD_OPC_Decode, 153, 5, 211, 1, // Opcode: EXTRV_W -/* 13116 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 13135 -/* 13120 */ MCD_OPC_CheckPredicate, 12, 90, 2, // Skip to: 13726 -/* 13124 */ MCD_OPC_CheckField, 13, 3, 0, 84, 2, // Skip to: 13726 -/* 13130 */ MCD_OPC_Decode, 146, 5, 210, 1, // Opcode: EXTP -/* 13135 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 13154 -/* 13139 */ MCD_OPC_CheckPredicate, 12, 71, 2, // Skip to: 13726 -/* 13143 */ MCD_OPC_CheckField, 13, 3, 0, 65, 2, // Skip to: 13726 -/* 13149 */ MCD_OPC_Decode, 149, 5, 211, 1, // Opcode: EXTPV -/* 13154 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 13173 -/* 13158 */ MCD_OPC_CheckPredicate, 12, 52, 2, // Skip to: 13726 -/* 13162 */ MCD_OPC_CheckField, 13, 3, 0, 46, 2, // Skip to: 13726 -/* 13168 */ MCD_OPC_Decode, 155, 5, 210, 1, // Opcode: EXTR_R_W -/* 13173 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 13192 -/* 13177 */ MCD_OPC_CheckPredicate, 12, 33, 2, // Skip to: 13726 -/* 13181 */ MCD_OPC_CheckField, 13, 3, 0, 27, 2, // Skip to: 13726 -/* 13187 */ MCD_OPC_Decode, 151, 5, 211, 1, // Opcode: EXTRV_R_W -/* 13192 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 13211 -/* 13196 */ MCD_OPC_CheckPredicate, 12, 14, 2, // Skip to: 13726 -/* 13200 */ MCD_OPC_CheckField, 13, 3, 0, 8, 2, // Skip to: 13726 -/* 13206 */ MCD_OPC_Decode, 154, 5, 210, 1, // Opcode: EXTR_RS_W -/* 13211 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 13230 -/* 13215 */ MCD_OPC_CheckPredicate, 12, 251, 1, // Skip to: 13726 -/* 13219 */ MCD_OPC_CheckField, 13, 3, 0, 245, 1, // Skip to: 13726 -/* 13225 */ MCD_OPC_Decode, 150, 5, 211, 1, // Opcode: EXTRV_RS_W -/* 13230 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 13249 -/* 13234 */ MCD_OPC_CheckPredicate, 12, 232, 1, // Skip to: 13726 -/* 13238 */ MCD_OPC_CheckField, 13, 3, 0, 226, 1, // Skip to: 13726 -/* 13244 */ MCD_OPC_Decode, 147, 5, 210, 1, // Opcode: EXTPDP -/* 13249 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 13268 -/* 13253 */ MCD_OPC_CheckPredicate, 12, 213, 1, // Skip to: 13726 -/* 13257 */ MCD_OPC_CheckField, 13, 3, 0, 207, 1, // Skip to: 13726 -/* 13263 */ MCD_OPC_Decode, 148, 5, 211, 1, // Opcode: EXTPDPV -/* 13268 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 13287 -/* 13272 */ MCD_OPC_CheckPredicate, 12, 194, 1, // Skip to: 13726 -/* 13276 */ MCD_OPC_CheckField, 13, 3, 0, 188, 1, // Skip to: 13726 -/* 13282 */ MCD_OPC_Decode, 156, 5, 210, 1, // Opcode: EXTR_S_H -/* 13287 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 13306 -/* 13291 */ MCD_OPC_CheckPredicate, 12, 175, 1, // Skip to: 13726 -/* 13295 */ MCD_OPC_CheckField, 13, 3, 0, 169, 1, // Skip to: 13726 -/* 13301 */ MCD_OPC_Decode, 152, 5, 211, 1, // Opcode: EXTRV_S_H -/* 13306 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 13319 -/* 13310 */ MCD_OPC_CheckPredicate, 12, 156, 1, // Skip to: 13726 -/* 13314 */ MCD_OPC_Decode, 237, 10, 212, 1, // Opcode: RDDSP -/* 13319 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 13332 -/* 13323 */ MCD_OPC_CheckPredicate, 12, 143, 1, // Skip to: 13726 -/* 13327 */ MCD_OPC_Decode, 233, 13, 213, 1, // Opcode: WRDSP -/* 13332 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 13351 -/* 13336 */ MCD_OPC_CheckPredicate, 12, 130, 1, // Skip to: 13726 -/* 13340 */ MCD_OPC_CheckField, 13, 7, 0, 124, 1, // Skip to: 13726 -/* 13346 */ MCD_OPC_Decode, 192, 11, 214, 1, // Opcode: SHILO -/* 13351 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 13370 -/* 13355 */ MCD_OPC_CheckPredicate, 12, 111, 1, // Skip to: 13726 -/* 13359 */ MCD_OPC_CheckField, 13, 8, 0, 105, 1, // Skip to: 13726 -/* 13365 */ MCD_OPC_Decode, 193, 11, 215, 1, // Opcode: SHILOV -/* 13370 */ MCD_OPC_FilterValue, 31, 96, 1, // Skip to: 13726 -/* 13374 */ MCD_OPC_CheckPredicate, 12, 92, 1, // Skip to: 13726 -/* 13378 */ MCD_OPC_CheckField, 13, 8, 0, 86, 1, // Skip to: 13726 -/* 13384 */ MCD_OPC_Decode, 180, 9, 215, 1, // Opcode: MTHLIP -/* 13389 */ MCD_OPC_FilterValue, 59, 77, 1, // Skip to: 13726 -/* 13393 */ MCD_OPC_CheckPredicate, 5, 73, 1, // Skip to: 13726 -/* 13397 */ MCD_OPC_CheckField, 21, 5, 0, 67, 1, // Skip to: 13726 -/* 13403 */ MCD_OPC_CheckField, 6, 5, 0, 61, 1, // Skip to: 13726 -/* 13409 */ MCD_OPC_Decode, 238, 10, 216, 1, // Opcode: RDHWR -/* 13414 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 13427 -/* 13418 */ MCD_OPC_CheckPredicate, 5, 48, 1, // Skip to: 13726 -/* 13422 */ MCD_OPC_Decode, 153, 7, 217, 1, // Opcode: LB -/* 13427 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 13440 -/* 13431 */ MCD_OPC_CheckPredicate, 5, 35, 1, // Skip to: 13726 -/* 13435 */ MCD_OPC_Decode, 184, 7, 217, 1, // Opcode: LH -/* 13440 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 13453 -/* 13444 */ MCD_OPC_CheckPredicate, 11, 22, 1, // Skip to: 13726 -/* 13448 */ MCD_OPC_Decode, 222, 7, 217, 1, // Opcode: LWL -/* 13453 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 13466 -/* 13457 */ MCD_OPC_CheckPredicate, 1, 9, 1, // Skip to: 13726 -/* 13461 */ MCD_OPC_Decode, 213, 7, 217, 1, // Opcode: LW -/* 13466 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 13479 -/* 13470 */ MCD_OPC_CheckPredicate, 5, 252, 0, // Skip to: 13726 -/* 13474 */ MCD_OPC_Decode, 158, 7, 217, 1, // Opcode: LBu -/* 13479 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 13492 -/* 13483 */ MCD_OPC_CheckPredicate, 5, 239, 0, // Skip to: 13726 -/* 13487 */ MCD_OPC_Decode, 189, 7, 217, 1, // Opcode: LHu -/* 13492 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 13505 -/* 13496 */ MCD_OPC_CheckPredicate, 11, 226, 0, // Skip to: 13726 -/* 13500 */ MCD_OPC_Decode, 230, 7, 217, 1, // Opcode: LWR -/* 13505 */ MCD_OPC_FilterValue, 40, 9, 0, // Skip to: 13518 -/* 13509 */ MCD_OPC_CheckPredicate, 5, 213, 0, // Skip to: 13726 -/* 13513 */ MCD_OPC_Decode, 142, 11, 217, 1, // Opcode: SB -/* 13518 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 13531 -/* 13522 */ MCD_OPC_CheckPredicate, 5, 200, 0, // Skip to: 13726 -/* 13526 */ MCD_OPC_Decode, 186, 11, 217, 1, // Opcode: SH -/* 13531 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 13544 -/* 13535 */ MCD_OPC_CheckPredicate, 11, 187, 0, // Skip to: 13726 -/* 13539 */ MCD_OPC_Decode, 243, 12, 217, 1, // Opcode: SWL -/* 13544 */ MCD_OPC_FilterValue, 43, 9, 0, // Skip to: 13557 -/* 13548 */ MCD_OPC_CheckPredicate, 1, 174, 0, // Skip to: 13726 -/* 13552 */ MCD_OPC_Decode, 235, 12, 217, 1, // Opcode: SW -/* 13557 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 13570 -/* 13561 */ MCD_OPC_CheckPredicate, 11, 161, 0, // Skip to: 13726 -/* 13565 */ MCD_OPC_Decode, 250, 12, 217, 1, // Opcode: SWR -/* 13570 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 13583 -/* 13574 */ MCD_OPC_CheckPredicate, 31, 148, 0, // Skip to: 13726 -/* 13578 */ MCD_OPC_Decode, 220, 2, 218, 1, // Opcode: CACHE -/* 13583 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 13596 -/* 13587 */ MCD_OPC_CheckPredicate, 32, 135, 0, // Skip to: 13726 -/* 13591 */ MCD_OPC_Decode, 193, 7, 217, 1, // Opcode: LL -/* 13596 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 13609 -/* 13600 */ MCD_OPC_CheckPredicate, 5, 122, 0, // Skip to: 13726 -/* 13604 */ MCD_OPC_Decode, 216, 7, 219, 1, // Opcode: LWC1 -/* 13609 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 13622 -/* 13613 */ MCD_OPC_CheckPredicate, 33, 109, 0, // Skip to: 13726 -/* 13617 */ MCD_OPC_Decode, 218, 7, 220, 1, // Opcode: LWC2 -/* 13622 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 13635 -/* 13626 */ MCD_OPC_CheckPredicate, 31, 96, 0, // Skip to: 13726 -/* 13630 */ MCD_OPC_Decode, 181, 10, 218, 1, // Opcode: PREF -/* 13635 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 13648 -/* 13639 */ MCD_OPC_CheckPredicate, 34, 83, 0, // Skip to: 13726 -/* 13643 */ MCD_OPC_Decode, 162, 7, 219, 1, // Opcode: LDC1 -/* 13648 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 13661 -/* 13652 */ MCD_OPC_CheckPredicate, 35, 70, 0, // Skip to: 13726 -/* 13656 */ MCD_OPC_Decode, 165, 7, 220, 1, // Opcode: LDC2 -/* 13661 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 13674 -/* 13665 */ MCD_OPC_CheckPredicate, 32, 57, 0, // Skip to: 13726 -/* 13669 */ MCD_OPC_Decode, 146, 11, 217, 1, // Opcode: SC -/* 13674 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 13687 -/* 13678 */ MCD_OPC_CheckPredicate, 5, 44, 0, // Skip to: 13726 -/* 13682 */ MCD_OPC_Decode, 238, 12, 219, 1, // Opcode: SWC1 -/* 13687 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 13700 -/* 13691 */ MCD_OPC_CheckPredicate, 33, 31, 0, // Skip to: 13726 -/* 13695 */ MCD_OPC_Decode, 240, 12, 220, 1, // Opcode: SWC2 -/* 13700 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 13713 -/* 13704 */ MCD_OPC_CheckPredicate, 34, 18, 0, // Skip to: 13726 -/* 13708 */ MCD_OPC_Decode, 156, 11, 219, 1, // Opcode: SDC1 -/* 13713 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 13726 -/* 13717 */ MCD_OPC_CheckPredicate, 35, 5, 0, // Skip to: 13726 -/* 13721 */ MCD_OPC_Decode, 159, 11, 220, 1, // Opcode: SDC2 -/* 13726 */ MCD_OPC_Fail, +/* 539 */ MCD_OPC_FilterValue, 0, 170, 64, 0, // Skip to: 17098 +/* 544 */ MCD_OPC_CheckPredicate, 31, 12, 0, 0, // Skip to: 561 +/* 549 */ MCD_OPC_CheckField, 11, 2, 0, 5, 0, 0, // Skip to: 561 +/* 556 */ MCD_OPC_Decode, 179, 18, 186, 1, // Opcode: MTHI +/* 561 */ MCD_OPC_CheckPredicate, 37, 148, 64, 0, // Skip to: 17098 +/* 566 */ MCD_OPC_Decode, 181, 18, 192, 1, // Opcode: MTHI_DSP +/* 571 */ MCD_OPC_FilterValue, 18, 51, 0, 0, // Skip to: 627 +/* 576 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 579 */ MCD_OPC_FilterValue, 0, 130, 64, 0, // Skip to: 17098 +/* 584 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 587 */ MCD_OPC_FilterValue, 0, 122, 64, 0, // Skip to: 17098 +/* 592 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 595 */ MCD_OPC_FilterValue, 0, 114, 64, 0, // Skip to: 17098 +/* 600 */ MCD_OPC_CheckPredicate, 31, 12, 0, 0, // Skip to: 617 +/* 605 */ MCD_OPC_CheckField, 21, 2, 0, 5, 0, 0, // Skip to: 617 +/* 612 */ MCD_OPC_Decode, 156, 17, 190, 1, // Opcode: MFLO +/* 617 */ MCD_OPC_CheckPredicate, 37, 92, 64, 0, // Skip to: 17098 +/* 622 */ MCD_OPC_Decode, 159, 17, 191, 1, // Opcode: MFLO_DSP +/* 627 */ MCD_OPC_FilterValue, 19, 43, 0, 0, // Skip to: 675 +/* 632 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 635 */ MCD_OPC_FilterValue, 0, 74, 64, 0, // Skip to: 17098 +/* 640 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... +/* 643 */ MCD_OPC_FilterValue, 0, 66, 64, 0, // Skip to: 17098 +/* 648 */ MCD_OPC_CheckPredicate, 31, 12, 0, 0, // Skip to: 665 +/* 653 */ MCD_OPC_CheckField, 11, 2, 0, 5, 0, 0, // Skip to: 665 +/* 660 */ MCD_OPC_Decode, 186, 18, 186, 1, // Opcode: MTLO +/* 665 */ MCD_OPC_CheckPredicate, 37, 44, 64, 0, // Skip to: 17098 +/* 670 */ MCD_OPC_Decode, 188, 18, 193, 1, // Opcode: MTLO_DSP +/* 675 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 697 +/* 680 */ MCD_OPC_CheckPredicate, 38, 29, 64, 0, // Skip to: 17098 +/* 685 */ MCD_OPC_CheckField, 8, 3, 0, 22, 64, 0, // Skip to: 17098 +/* 692 */ MCD_OPC_Decode, 235, 11, 194, 1, // Opcode: DLSA +/* 697 */ MCD_OPC_FilterValue, 24, 42, 0, 0, // Skip to: 744 +/* 702 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 705 */ MCD_OPC_FilterValue, 0, 4, 64, 0, // Skip to: 17098 +/* 710 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 713 */ MCD_OPC_FilterValue, 0, 252, 63, 0, // Skip to: 17098 +/* 718 */ MCD_OPC_CheckPredicate, 31, 11, 0, 0, // Skip to: 734 +/* 723 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 734 +/* 730 */ MCD_OPC_Decode, 230, 18, 80, // Opcode: MULT +/* 734 */ MCD_OPC_CheckPredicate, 37, 231, 63, 0, // Skip to: 17098 +/* 739 */ MCD_OPC_Decode, 233, 18, 195, 1, // Opcode: MULT_DSP +/* 744 */ MCD_OPC_FilterValue, 25, 42, 0, 0, // Skip to: 791 +/* 749 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 752 */ MCD_OPC_FilterValue, 0, 213, 63, 0, // Skip to: 17098 +/* 757 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 760 */ MCD_OPC_FilterValue, 0, 205, 63, 0, // Skip to: 17098 +/* 765 */ MCD_OPC_CheckPredicate, 31, 11, 0, 0, // Skip to: 781 +/* 770 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 781 +/* 777 */ MCD_OPC_Decode, 236, 18, 80, // Opcode: MULTu +/* 781 */ MCD_OPC_CheckPredicate, 37, 184, 63, 0, // Skip to: 17098 +/* 786 */ MCD_OPC_Decode, 231, 18, 195, 1, // Opcode: MULTU_DSP +/* 791 */ MCD_OPC_FilterValue, 26, 16, 0, 0, // Skip to: 812 +/* 796 */ MCD_OPC_CheckPredicate, 31, 169, 63, 0, // Skip to: 17098 +/* 801 */ MCD_OPC_CheckField, 6, 10, 0, 162, 63, 0, // Skip to: 17098 +/* 808 */ MCD_OPC_Decode, 236, 20, 80, // Opcode: SDIV +/* 812 */ MCD_OPC_FilterValue, 27, 16, 0, 0, // Skip to: 833 +/* 817 */ MCD_OPC_CheckPredicate, 31, 148, 63, 0, // Skip to: 17098 +/* 822 */ MCD_OPC_CheckField, 6, 10, 0, 141, 63, 0, // Skip to: 17098 +/* 829 */ MCD_OPC_Decode, 152, 24, 80, // Opcode: UDIV +/* 833 */ MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 854 +/* 838 */ MCD_OPC_CheckPredicate, 27, 127, 63, 0, // Skip to: 17098 +/* 843 */ MCD_OPC_CheckField, 6, 5, 0, 120, 63, 0, // Skip to: 17098 +/* 850 */ MCD_OPC_Decode, 251, 5, 61, // Opcode: ADD +/* 854 */ MCD_OPC_FilterValue, 33, 16, 0, 0, // Skip to: 875 +/* 859 */ MCD_OPC_CheckPredicate, 27, 106, 63, 0, // Skip to: 17098 +/* 864 */ MCD_OPC_CheckField, 6, 5, 0, 99, 63, 0, // Skip to: 17098 +/* 871 */ MCD_OPC_Decode, 206, 6, 61, // Opcode: ADDu +/* 875 */ MCD_OPC_FilterValue, 34, 16, 0, 0, // Skip to: 896 +/* 880 */ MCD_OPC_CheckPredicate, 27, 85, 63, 0, // Skip to: 17098 +/* 885 */ MCD_OPC_CheckField, 6, 5, 0, 78, 63, 0, // Skip to: 17098 +/* 892 */ MCD_OPC_Decode, 192, 22, 61, // Opcode: SUB +/* 896 */ MCD_OPC_FilterValue, 35, 16, 0, 0, // Skip to: 917 +/* 901 */ MCD_OPC_CheckPredicate, 27, 64, 63, 0, // Skip to: 17098 +/* 906 */ MCD_OPC_CheckField, 6, 5, 0, 57, 63, 0, // Skip to: 17098 +/* 913 */ MCD_OPC_Decode, 249, 22, 61, // Opcode: SUBu +/* 917 */ MCD_OPC_FilterValue, 36, 16, 0, 0, // Skip to: 938 +/* 922 */ MCD_OPC_CheckPredicate, 27, 43, 63, 0, // Skip to: 17098 +/* 927 */ MCD_OPC_CheckField, 6, 5, 0, 36, 63, 0, // Skip to: 17098 +/* 934 */ MCD_OPC_Decode, 216, 6, 61, // Opcode: AND +/* 938 */ MCD_OPC_FilterValue, 37, 16, 0, 0, // Skip to: 959 +/* 943 */ MCD_OPC_CheckPredicate, 27, 22, 63, 0, // Skip to: 17098 +/* 948 */ MCD_OPC_CheckField, 6, 5, 0, 15, 63, 0, // Skip to: 17098 +/* 955 */ MCD_OPC_Decode, 163, 19, 61, // Opcode: OR +/* 959 */ MCD_OPC_FilterValue, 38, 16, 0, 0, // Skip to: 980 +/* 964 */ MCD_OPC_CheckPredicate, 27, 1, 63, 0, // Skip to: 17098 +/* 969 */ MCD_OPC_CheckField, 6, 5, 0, 250, 62, 0, // Skip to: 17098 +/* 976 */ MCD_OPC_Decode, 172, 24, 61, // Opcode: XOR +/* 980 */ MCD_OPC_FilterValue, 39, 16, 0, 0, // Skip to: 1001 +/* 985 */ MCD_OPC_CheckPredicate, 27, 236, 62, 0, // Skip to: 17098 +/* 990 */ MCD_OPC_CheckField, 6, 5, 0, 229, 62, 0, // Skip to: 17098 +/* 997 */ MCD_OPC_Decode, 151, 19, 61, // Opcode: NOR +/* 1001 */ MCD_OPC_FilterValue, 42, 16, 0, 0, // Skip to: 1022 +/* 1006 */ MCD_OPC_CheckPredicate, 27, 215, 62, 0, // Skip to: 17098 +/* 1011 */ MCD_OPC_CheckField, 6, 5, 0, 208, 62, 0, // Skip to: 17098 +/* 1018 */ MCD_OPC_Decode, 239, 21, 61, // Opcode: SLT +/* 1022 */ MCD_OPC_FilterValue, 43, 16, 0, 0, // Skip to: 1043 +/* 1027 */ MCD_OPC_CheckPredicate, 27, 194, 62, 0, // Skip to: 17098 +/* 1032 */ MCD_OPC_CheckField, 6, 5, 0, 187, 62, 0, // Skip to: 17098 +/* 1039 */ MCD_OPC_Decode, 252, 21, 61, // Opcode: SLTu +/* 1043 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 1058 +/* 1048 */ MCD_OPC_CheckPredicate, 36, 173, 62, 0, // Skip to: 17098 +/* 1053 */ MCD_OPC_Decode, 212, 23, 196, 1, // Opcode: TGE +/* 1058 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 1073 +/* 1063 */ MCD_OPC_CheckPredicate, 36, 158, 62, 0, // Skip to: 17098 +/* 1068 */ MCD_OPC_Decode, 217, 23, 196, 1, // Opcode: TGEU +/* 1073 */ MCD_OPC_FilterValue, 50, 10, 0, 0, // Skip to: 1088 +/* 1078 */ MCD_OPC_CheckPredicate, 36, 143, 62, 0, // Skip to: 17098 +/* 1083 */ MCD_OPC_Decode, 250, 23, 196, 1, // Opcode: TLT +/* 1088 */ MCD_OPC_FilterValue, 51, 10, 0, 0, // Skip to: 1103 +/* 1093 */ MCD_OPC_CheckPredicate, 36, 128, 62, 0, // Skip to: 17098 +/* 1098 */ MCD_OPC_Decode, 254, 23, 196, 1, // Opcode: TLTU +/* 1103 */ MCD_OPC_FilterValue, 52, 10, 0, 0, // Skip to: 1118 +/* 1108 */ MCD_OPC_CheckPredicate, 36, 113, 62, 0, // Skip to: 17098 +/* 1113 */ MCD_OPC_Decode, 207, 23, 196, 1, // Opcode: TEQ +/* 1118 */ MCD_OPC_FilterValue, 54, 103, 62, 0, // Skip to: 17098 +/* 1123 */ MCD_OPC_CheckPredicate, 36, 98, 62, 0, // Skip to: 17098 +/* 1128 */ MCD_OPC_Decode, 129, 24, 196, 1, // Opcode: TNE +/* 1133 */ MCD_OPC_FilterValue, 1, 250, 0, 0, // Skip to: 1388 +/* 1138 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 1141 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1156 +/* 1146 */ MCD_OPC_CheckPredicate, 27, 75, 62, 0, // Skip to: 17098 +/* 1151 */ MCD_OPC_Decode, 153, 8, 197, 1, // Opcode: BLTZ +/* 1156 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1171 +/* 1161 */ MCD_OPC_CheckPredicate, 27, 60, 62, 0, // Skip to: 17098 +/* 1166 */ MCD_OPC_Decode, 219, 7, 197, 1, // Opcode: BGEZ +/* 1171 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1186 +/* 1176 */ MCD_OPC_CheckPredicate, 39, 45, 62, 0, // Skip to: 17098 +/* 1181 */ MCD_OPC_Decode, 164, 8, 197, 1, // Opcode: BLTZL +/* 1186 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1201 +/* 1191 */ MCD_OPC_CheckPredicate, 39, 30, 62, 0, // Skip to: 17098 +/* 1196 */ MCD_OPC_Decode, 230, 7, 197, 1, // Opcode: BGEZL +/* 1201 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1216 +/* 1206 */ MCD_OPC_CheckPredicate, 39, 15, 62, 0, // Skip to: 17098 +/* 1211 */ MCD_OPC_Decode, 213, 23, 175, 1, // Opcode: TGEI +/* 1216 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1231 +/* 1221 */ MCD_OPC_CheckPredicate, 39, 0, 62, 0, // Skip to: 17098 +/* 1226 */ MCD_OPC_Decode, 214, 23, 175, 1, // Opcode: TGEIU +/* 1231 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1246 +/* 1236 */ MCD_OPC_CheckPredicate, 39, 241, 61, 0, // Skip to: 17098 +/* 1241 */ MCD_OPC_Decode, 251, 23, 175, 1, // Opcode: TLTI +/* 1246 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1261 +/* 1251 */ MCD_OPC_CheckPredicate, 39, 226, 61, 0, // Skip to: 17098 +/* 1256 */ MCD_OPC_Decode, 145, 24, 175, 1, // Opcode: TTLTIU +/* 1261 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1276 +/* 1266 */ MCD_OPC_CheckPredicate, 39, 211, 61, 0, // Skip to: 17098 +/* 1271 */ MCD_OPC_Decode, 208, 23, 175, 1, // Opcode: TEQI +/* 1276 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1291 +/* 1281 */ MCD_OPC_CheckPredicate, 39, 196, 61, 0, // Skip to: 17098 +/* 1286 */ MCD_OPC_Decode, 130, 24, 175, 1, // Opcode: TNEI +/* 1291 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 1306 +/* 1296 */ MCD_OPC_CheckPredicate, 31, 181, 61, 0, // Skip to: 17098 +/* 1301 */ MCD_OPC_Decode, 155, 8, 197, 1, // Opcode: BLTZAL +/* 1306 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 1321 +/* 1311 */ MCD_OPC_CheckPredicate, 31, 166, 61, 0, // Skip to: 17098 +/* 1316 */ MCD_OPC_Decode, 221, 7, 197, 1, // Opcode: BGEZAL +/* 1321 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 1336 +/* 1326 */ MCD_OPC_CheckPredicate, 39, 151, 61, 0, // Skip to: 17098 +/* 1331 */ MCD_OPC_Decode, 158, 8, 197, 1, // Opcode: BLTZALL +/* 1336 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 1351 +/* 1341 */ MCD_OPC_CheckPredicate, 39, 136, 61, 0, // Skip to: 17098 +/* 1346 */ MCD_OPC_Decode, 224, 7, 197, 1, // Opcode: BGEZALL +/* 1351 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 1373 +/* 1356 */ MCD_OPC_CheckPredicate, 40, 121, 61, 0, // Skip to: 17098 +/* 1361 */ MCD_OPC_CheckField, 21, 5, 0, 114, 61, 0, // Skip to: 17098 +/* 1368 */ MCD_OPC_Decode, 208, 8, 198, 1, // Opcode: BPOSGE32 +/* 1373 */ MCD_OPC_FilterValue, 31, 104, 61, 0, // Skip to: 17098 +/* 1378 */ MCD_OPC_CheckPredicate, 28, 99, 61, 0, // Skip to: 17098 +/* 1383 */ MCD_OPC_Decode, 174, 23, 199, 1, // Opcode: SYNCI +/* 1388 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1403 +/* 1393 */ MCD_OPC_CheckPredicate, 27, 84, 61, 0, // Skip to: 17098 +/* 1398 */ MCD_OPC_Decode, 234, 14, 200, 1, // Opcode: J +/* 1403 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1418 +/* 1408 */ MCD_OPC_CheckPredicate, 27, 69, 61, 0, // Skip to: 17098 +/* 1413 */ MCD_OPC_Decode, 235, 14, 200, 1, // Opcode: JAL +/* 1418 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1433 +/* 1423 */ MCD_OPC_CheckPredicate, 27, 54, 61, 0, // Skip to: 17098 +/* 1428 */ MCD_OPC_Decode, 188, 7, 201, 1, // Opcode: BEQ +/* 1433 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1448 +/* 1438 */ MCD_OPC_CheckPredicate, 27, 39, 61, 0, // Skip to: 17098 +/* 1443 */ MCD_OPC_Decode, 170, 8, 201, 1, // Opcode: BNE +/* 1448 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 1470 +/* 1453 */ MCD_OPC_CheckPredicate, 27, 24, 61, 0, // Skip to: 17098 +/* 1458 */ MCD_OPC_CheckField, 16, 5, 0, 17, 61, 0, // Skip to: 17098 +/* 1465 */ MCD_OPC_Decode, 134, 8, 197, 1, // Opcode: BLEZ +/* 1470 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1492 +/* 1475 */ MCD_OPC_CheckPredicate, 27, 2, 61, 0, // Skip to: 17098 +/* 1480 */ MCD_OPC_CheckField, 16, 5, 0, 251, 60, 0, // Skip to: 17098 +/* 1487 */ MCD_OPC_Decode, 232, 7, 197, 1, // Opcode: BGTZ +/* 1492 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1507 +/* 1497 */ MCD_OPC_CheckPredicate, 31, 236, 60, 0, // Skip to: 17098 +/* 1502 */ MCD_OPC_Decode, 202, 6, 202, 1, // Opcode: ADDi +/* 1507 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1522 +/* 1512 */ MCD_OPC_CheckPredicate, 27, 221, 60, 0, // Skip to: 17098 +/* 1517 */ MCD_OPC_Decode, 204, 6, 202, 1, // Opcode: ADDiu +/* 1522 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1537 +/* 1527 */ MCD_OPC_CheckPredicate, 27, 206, 60, 0, // Skip to: 17098 +/* 1532 */ MCD_OPC_Decode, 246, 21, 202, 1, // Opcode: SLTi +/* 1537 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1552 +/* 1542 */ MCD_OPC_CheckPredicate, 27, 191, 60, 0, // Skip to: 17098 +/* 1547 */ MCD_OPC_Decode, 249, 21, 202, 1, // Opcode: SLTiu +/* 1552 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1567 +/* 1557 */ MCD_OPC_CheckPredicate, 27, 176, 60, 0, // Skip to: 17098 +/* 1562 */ MCD_OPC_Decode, 231, 6, 203, 1, // Opcode: ANDi +/* 1567 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1582 +/* 1572 */ MCD_OPC_CheckPredicate, 27, 161, 60, 0, // Skip to: 17098 +/* 1577 */ MCD_OPC_Decode, 175, 19, 203, 1, // Opcode: ORi +/* 1582 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1597 +/* 1587 */ MCD_OPC_CheckPredicate, 27, 146, 60, 0, // Skip to: 17098 +/* 1592 */ MCD_OPC_Decode, 184, 24, 203, 1, // Opcode: XORi +/* 1597 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 1618 +/* 1602 */ MCD_OPC_CheckPredicate, 27, 131, 60, 0, // Skip to: 17098 +/* 1607 */ MCD_OPC_CheckField, 21, 5, 0, 124, 60, 0, // Skip to: 17098 +/* 1614 */ MCD_OPC_Decode, 128, 16, 103, // Opcode: LUi +/* 1618 */ MCD_OPC_FilterValue, 16, 187, 2, 0, // Skip to: 2322 +/* 1623 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 1626 */ MCD_OPC_FilterValue, 0, 190, 1, 0, // Skip to: 2077 +/* 1631 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 1634 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1656 +/* 1639 */ MCD_OPC_CheckPredicate, 27, 94, 60, 0, // Skip to: 17098 +/* 1644 */ MCD_OPC_CheckField, 4, 7, 0, 87, 60, 0, // Skip to: 17098 +/* 1651 */ MCD_OPC_Decode, 128, 17, 204, 1, // Opcode: MFC0 +/* 1656 */ MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 1724 +/* 1661 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 1664 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1679 +/* 1669 */ MCD_OPC_CheckPredicate, 41, 64, 60, 0, // Skip to: 17098 +/* 1674 */ MCD_OPC_Decode, 138, 17, 204, 1, // Opcode: MFGC0 +/* 1679 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 1694 +/* 1684 */ MCD_OPC_CheckPredicate, 41, 49, 60, 0, // Skip to: 17098 +/* 1689 */ MCD_OPC_Decode, 167, 18, 205, 1, // Opcode: MTGC0 +/* 1694 */ MCD_OPC_FilterValue, 64, 10, 0, 0, // Skip to: 1709 +/* 1699 */ MCD_OPC_CheckPredicate, 41, 34, 60, 0, // Skip to: 17098 +/* 1704 */ MCD_OPC_Decode, 148, 17, 204, 1, // Opcode: MFHGC0 +/* 1709 */ MCD_OPC_FilterValue, 96, 24, 60, 0, // Skip to: 17098 +/* 1714 */ MCD_OPC_CheckPredicate, 41, 19, 60, 0, // Skip to: 17098 +/* 1719 */ MCD_OPC_Decode, 177, 18, 205, 1, // Opcode: MTHGC0 +/* 1724 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1746 +/* 1729 */ MCD_OPC_CheckPredicate, 27, 4, 60, 0, // Skip to: 17098 +/* 1734 */ MCD_OPC_CheckField, 4, 7, 0, 253, 59, 0, // Skip to: 17098 +/* 1741 */ MCD_OPC_Decode, 156, 18, 205, 1, // Opcode: MTC0 +/* 1746 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 1768 +/* 1751 */ MCD_OPC_CheckPredicate, 42, 238, 59, 0, // Skip to: 17098 +/* 1756 */ MCD_OPC_CheckField, 6, 5, 0, 231, 59, 0, // Skip to: 17098 +/* 1763 */ MCD_OPC_Decode, 162, 17, 206, 1, // Opcode: MFTR +/* 1768 */ MCD_OPC_FilterValue, 11, 133, 0, 0, // Skip to: 1906 +/* 1773 */ MCD_OPC_ExtractField, 4, 12, // Inst{15-4} ... +/* 1776 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1797 +/* 1781 */ MCD_OPC_CheckPredicate, 42, 208, 59, 0, // Skip to: 17098 +/* 1786 */ MCD_OPC_CheckField, 0, 3, 1, 201, 59, 0, // Skip to: 17098 +/* 1793 */ MCD_OPC_Decode, 201, 12, 92, // Opcode: DVPE +/* 1797 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 1818 +/* 1802 */ MCD_OPC_CheckPredicate, 42, 187, 59, 0, // Skip to: 17098 +/* 1807 */ MCD_OPC_CheckField, 0, 3, 1, 180, 59, 0, // Skip to: 17098 +/* 1814 */ MCD_OPC_Decode, 224, 12, 92, // Opcode: EVPE +/* 1818 */ MCD_OPC_FilterValue, 188, 1, 16, 0, 0, // Skip to: 1840 +/* 1824 */ MCD_OPC_CheckPredicate, 42, 165, 59, 0, // Skip to: 17098 +/* 1829 */ MCD_OPC_CheckField, 0, 3, 1, 158, 59, 0, // Skip to: 17098 +/* 1836 */ MCD_OPC_Decode, 244, 11, 92, // Opcode: DMT +/* 1840 */ MCD_OPC_FilterValue, 190, 1, 16, 0, 0, // Skip to: 1862 +/* 1846 */ MCD_OPC_CheckPredicate, 42, 143, 59, 0, // Skip to: 17098 +/* 1851 */ MCD_OPC_CheckField, 0, 3, 1, 136, 59, 0, // Skip to: 17098 +/* 1858 */ MCD_OPC_Decode, 214, 12, 92, // Opcode: EMT +/* 1862 */ MCD_OPC_FilterValue, 128, 12, 16, 0, 0, // Skip to: 1884 +/* 1868 */ MCD_OPC_CheckPredicate, 28, 121, 59, 0, // Skip to: 17098 +/* 1873 */ MCD_OPC_CheckField, 0, 3, 0, 114, 59, 0, // Skip to: 17098 +/* 1880 */ MCD_OPC_Decode, 214, 11, 92, // Opcode: DI +/* 1884 */ MCD_OPC_FilterValue, 130, 12, 104, 59, 0, // Skip to: 17098 +/* 1890 */ MCD_OPC_CheckPredicate, 28, 99, 59, 0, // Skip to: 17098 +/* 1895 */ MCD_OPC_CheckField, 0, 3, 0, 92, 59, 0, // Skip to: 17098 +/* 1902 */ MCD_OPC_Decode, 210, 12, 92, // Opcode: EI +/* 1906 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 1928 +/* 1911 */ MCD_OPC_CheckPredicate, 42, 78, 59, 0, // Skip to: 17098 +/* 1916 */ MCD_OPC_CheckField, 6, 5, 0, 71, 59, 0, // Skip to: 17098 +/* 1923 */ MCD_OPC_Decode, 197, 18, 206, 1, // Opcode: MTTR +/* 1928 */ MCD_OPC_FilterValue, 16, 61, 59, 0, // Skip to: 17098 +/* 1933 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 1936 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1972 +/* 1941 */ MCD_OPC_ExtractField, 4, 17, // Inst{20-4} ... +/* 1944 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1958 +/* 1949 */ MCD_OPC_CheckPredicate, 41, 40, 59, 0, // Skip to: 17098 +/* 1954 */ MCD_OPC_Decode, 224, 23, 10, // Opcode: TLBGP +/* 1958 */ MCD_OPC_FilterValue, 2, 31, 59, 0, // Skip to: 17098 +/* 1963 */ MCD_OPC_CheckPredicate, 43, 26, 59, 0, // Skip to: 17098 +/* 1968 */ MCD_OPC_Decode, 161, 24, 10, // Opcode: WAIT +/* 1972 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 1993 +/* 1977 */ MCD_OPC_CheckPredicate, 27, 12, 59, 0, // Skip to: 17098 +/* 1982 */ MCD_OPC_CheckField, 4, 17, 0, 5, 59, 0, // Skip to: 17098 +/* 1989 */ MCD_OPC_Decode, 241, 23, 10, // Opcode: TLBR +/* 1993 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2014 +/* 1998 */ MCD_OPC_CheckPredicate, 27, 247, 58, 0, // Skip to: 17098 +/* 2003 */ MCD_OPC_CheckField, 4, 17, 0, 240, 58, 0, // Skip to: 17098 +/* 2010 */ MCD_OPC_Decode, 244, 23, 10, // Opcode: TLBWI +/* 2014 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 2035 +/* 2019 */ MCD_OPC_CheckPredicate, 44, 226, 58, 0, // Skip to: 17098 +/* 2024 */ MCD_OPC_CheckField, 4, 17, 0, 219, 58, 0, // Skip to: 17098 +/* 2031 */ MCD_OPC_Decode, 232, 23, 10, // Opcode: TLBINV +/* 2035 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 2056 +/* 2040 */ MCD_OPC_CheckPredicate, 44, 205, 58, 0, // Skip to: 17098 +/* 2045 */ MCD_OPC_CheckField, 4, 17, 0, 198, 58, 0, // Skip to: 17098 +/* 2052 */ MCD_OPC_Decode, 233, 23, 10, // Opcode: TLBINVF +/* 2056 */ MCD_OPC_FilterValue, 6, 189, 58, 0, // Skip to: 17098 +/* 2061 */ MCD_OPC_CheckPredicate, 27, 184, 58, 0, // Skip to: 17098 +/* 2066 */ MCD_OPC_CheckField, 4, 17, 0, 177, 58, 0, // Skip to: 17098 +/* 2073 */ MCD_OPC_Decode, 247, 23, 10, // Opcode: TLBWR +/* 2077 */ MCD_OPC_FilterValue, 1, 168, 58, 0, // Skip to: 17098 +/* 2082 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 2085 */ MCD_OPC_FilterValue, 0, 88, 0, 0, // Skip to: 2178 +/* 2090 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 2093 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 2116 +/* 2098 */ MCD_OPC_CheckPredicate, 27, 147, 58, 0, // Skip to: 17098 +/* 2103 */ MCD_OPC_CheckField, 6, 20, 128, 128, 32, 138, 58, 0, // Skip to: 17098 +/* 2112 */ MCD_OPC_Decode, 238, 23, 10, // Opcode: TLBP +/* 2116 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 2156 +/* 2121 */ MCD_OPC_ExtractField, 6, 20, // Inst{25-6} ... +/* 2124 */ MCD_OPC_FilterValue, 128, 128, 32, 9, 0, 0, // Skip to: 2140 +/* 2131 */ MCD_OPC_CheckPredicate, 43, 114, 58, 0, // Skip to: 17098 +/* 2136 */ MCD_OPC_Decode, 216, 12, 10, // Opcode: ERET +/* 2140 */ MCD_OPC_FilterValue, 129, 128, 32, 103, 58, 0, // Skip to: 17098 +/* 2147 */ MCD_OPC_CheckPredicate, 45, 98, 58, 0, // Skip to: 17098 +/* 2152 */ MCD_OPC_Decode, 217, 12, 10, // Opcode: ERETNC +/* 2156 */ MCD_OPC_FilterValue, 2, 89, 58, 0, // Skip to: 17098 +/* 2161 */ MCD_OPC_CheckPredicate, 41, 84, 58, 0, // Skip to: 17098 +/* 2166 */ MCD_OPC_CheckField, 25, 1, 1, 77, 58, 0, // Skip to: 17098 +/* 2173 */ MCD_OPC_Decode, 202, 14, 207, 1, // Opcode: HYPCALL +/* 2178 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 2202 +/* 2183 */ MCD_OPC_CheckPredicate, 41, 62, 58, 0, // Skip to: 17098 +/* 2188 */ MCD_OPC_CheckField, 4, 22, 128, 128, 128, 1, 52, 58, 0, // Skip to: 17098 +/* 2198 */ MCD_OPC_Decode, 226, 23, 10, // Opcode: TLBGR +/* 2202 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2226 +/* 2207 */ MCD_OPC_CheckPredicate, 41, 38, 58, 0, // Skip to: 17098 +/* 2212 */ MCD_OPC_CheckField, 4, 22, 128, 128, 128, 1, 28, 58, 0, // Skip to: 17098 +/* 2222 */ MCD_OPC_Decode, 228, 23, 10, // Opcode: TLBGWI +/* 2226 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 2250 +/* 2231 */ MCD_OPC_CheckPredicate, 41, 14, 58, 0, // Skip to: 17098 +/* 2236 */ MCD_OPC_CheckField, 4, 22, 128, 128, 128, 1, 4, 58, 0, // Skip to: 17098 +/* 2246 */ MCD_OPC_Decode, 220, 23, 10, // Opcode: TLBGINV +/* 2250 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2274 +/* 2255 */ MCD_OPC_CheckPredicate, 41, 246, 57, 0, // Skip to: 17098 +/* 2260 */ MCD_OPC_CheckField, 4, 22, 128, 128, 128, 1, 236, 57, 0, // Skip to: 17098 +/* 2270 */ MCD_OPC_Decode, 221, 23, 10, // Opcode: TLBGINVF +/* 2274 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 2298 +/* 2279 */ MCD_OPC_CheckPredicate, 41, 222, 57, 0, // Skip to: 17098 +/* 2284 */ MCD_OPC_CheckField, 4, 22, 128, 128, 128, 1, 212, 57, 0, // Skip to: 17098 +/* 2294 */ MCD_OPC_Decode, 230, 23, 10, // Opcode: TLBGWR +/* 2298 */ MCD_OPC_FilterValue, 7, 203, 57, 0, // Skip to: 17098 +/* 2303 */ MCD_OPC_CheckPredicate, 46, 198, 57, 0, // Skip to: 17098 +/* 2308 */ MCD_OPC_CheckField, 4, 22, 129, 128, 128, 1, 188, 57, 0, // Skip to: 17098 +/* 2318 */ MCD_OPC_Decode, 206, 11, 10, // Opcode: DERET +/* 2322 */ MCD_OPC_FilterValue, 17, 205, 7, 0, // Skip to: 4324 +/* 2327 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 2330 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2352 +/* 2335 */ MCD_OPC_CheckPredicate, 47, 166, 57, 0, // Skip to: 17098 +/* 2340 */ MCD_OPC_CheckField, 0, 11, 0, 159, 57, 0, // Skip to: 17098 +/* 2347 */ MCD_OPC_Decode, 132, 17, 208, 1, // Opcode: MFC1 +/* 2352 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2374 +/* 2357 */ MCD_OPC_CheckPredicate, 48, 144, 57, 0, // Skip to: 17098 +/* 2362 */ MCD_OPC_CheckField, 0, 11, 0, 137, 57, 0, // Skip to: 17098 +/* 2369 */ MCD_OPC_Decode, 238, 11, 209, 1, // Opcode: DMFC1 +/* 2374 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 2396 +/* 2379 */ MCD_OPC_CheckPredicate, 47, 122, 57, 0, // Skip to: 17098 +/* 2384 */ MCD_OPC_CheckField, 0, 11, 0, 115, 57, 0, // Skip to: 17098 +/* 2391 */ MCD_OPC_Decode, 144, 9, 210, 1, // Opcode: CFC1 +/* 2396 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 2418 +/* 2401 */ MCD_OPC_CheckPredicate, 49, 100, 57, 0, // Skip to: 17098 +/* 2406 */ MCD_OPC_CheckField, 0, 11, 0, 93, 57, 0, // Skip to: 17098 +/* 2413 */ MCD_OPC_Decode, 143, 17, 211, 1, // Opcode: MFHC1_D32 +/* 2418 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2440 +/* 2423 */ MCD_OPC_CheckPredicate, 47, 78, 57, 0, // Skip to: 17098 +/* 2428 */ MCD_OPC_CheckField, 0, 11, 0, 71, 57, 0, // Skip to: 17098 +/* 2435 */ MCD_OPC_Decode, 160, 18, 212, 1, // Opcode: MTC1 +/* 2440 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2462 +/* 2445 */ MCD_OPC_CheckPredicate, 48, 56, 57, 0, // Skip to: 17098 +/* 2450 */ MCD_OPC_CheckField, 0, 11, 0, 49, 57, 0, // Skip to: 17098 +/* 2457 */ MCD_OPC_Decode, 246, 11, 213, 1, // Opcode: DMTC1 +/* 2462 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2484 +/* 2467 */ MCD_OPC_CheckPredicate, 47, 34, 57, 0, // Skip to: 17098 +/* 2472 */ MCD_OPC_CheckField, 0, 11, 0, 27, 57, 0, // Skip to: 17098 +/* 2479 */ MCD_OPC_Decode, 179, 10, 214, 1, // Opcode: CTC1 +/* 2484 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 2506 +/* 2489 */ MCD_OPC_CheckPredicate, 49, 12, 57, 0, // Skip to: 17098 +/* 2494 */ MCD_OPC_CheckField, 0, 11, 0, 5, 57, 0, // Skip to: 17098 +/* 2501 */ MCD_OPC_Decode, 172, 18, 215, 1, // Opcode: MTHC1_D32 +/* 2506 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 2574 +/* 2511 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 2514 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2529 +/* 2519 */ MCD_OPC_CheckPredicate, 50, 238, 56, 0, // Skip to: 17098 +/* 2524 */ MCD_OPC_Decode, 166, 7, 216, 1, // Opcode: BC1F +/* 2529 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2544 +/* 2534 */ MCD_OPC_CheckPredicate, 50, 223, 56, 0, // Skip to: 17098 +/* 2539 */ MCD_OPC_Decode, 171, 7, 216, 1, // Opcode: BC1T +/* 2544 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2559 +/* 2549 */ MCD_OPC_CheckPredicate, 51, 208, 56, 0, // Skip to: 17098 +/* 2554 */ MCD_OPC_Decode, 167, 7, 216, 1, // Opcode: BC1FL +/* 2559 */ MCD_OPC_FilterValue, 3, 198, 56, 0, // Skip to: 17098 +/* 2564 */ MCD_OPC_CheckPredicate, 51, 193, 56, 0, // Skip to: 17098 +/* 2569 */ MCD_OPC_Decode, 172, 7, 216, 1, // Opcode: BC1TL +/* 2574 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 2589 +/* 2579 */ MCD_OPC_CheckPredicate, 30, 178, 56, 0, // Skip to: 17098 +/* 2584 */ MCD_OPC_Decode, 233, 8, 217, 1, // Opcode: BZ_V +/* 2589 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2604 +/* 2594 */ MCD_OPC_CheckPredicate, 30, 163, 56, 0, // Skip to: 17098 +/* 2599 */ MCD_OPC_Decode, 204, 8, 217, 1, // Opcode: BNZ_V +/* 2604 */ MCD_OPC_FilterValue, 16, 1, 3, 0, // Skip to: 3378 +/* 2609 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 2612 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2627 +/* 2617 */ MCD_OPC_CheckPredicate, 47, 140, 56, 0, // Skip to: 17098 +/* 2622 */ MCD_OPC_Decode, 142, 13, 218, 1, // Opcode: FADD_S +/* 2627 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2642 +/* 2632 */ MCD_OPC_CheckPredicate, 47, 125, 56, 0, // Skip to: 17098 +/* 2637 */ MCD_OPC_Decode, 160, 14, 218, 1, // Opcode: FSUB_S +/* 2642 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2657 +/* 2647 */ MCD_OPC_CheckPredicate, 47, 110, 56, 0, // Skip to: 17098 +/* 2652 */ MCD_OPC_Decode, 243, 13, 218, 1, // Opcode: FMUL_S +/* 2657 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2672 +/* 2662 */ MCD_OPC_CheckPredicate, 47, 95, 56, 0, // Skip to: 17098 +/* 2667 */ MCD_OPC_Decode, 180, 13, 218, 1, // Opcode: FDIV_S +/* 2672 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2694 +/* 2677 */ MCD_OPC_CheckPredicate, 52, 80, 56, 0, // Skip to: 17098 +/* 2682 */ MCD_OPC_CheckField, 16, 5, 0, 73, 56, 0, // Skip to: 17098 +/* 2689 */ MCD_OPC_Decode, 151, 14, 219, 1, // Opcode: FSQRT_S +/* 2694 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2716 +/* 2699 */ MCD_OPC_CheckPredicate, 47, 58, 56, 0, // Skip to: 17098 +/* 2704 */ MCD_OPC_CheckField, 16, 5, 0, 51, 56, 0, // Skip to: 17098 +/* 2711 */ MCD_OPC_Decode, 134, 13, 219, 1, // Opcode: FABS_S +/* 2716 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2738 +/* 2721 */ MCD_OPC_CheckPredicate, 47, 36, 56, 0, // Skip to: 17098 +/* 2726 */ MCD_OPC_CheckField, 16, 5, 0, 29, 56, 0, // Skip to: 17098 +/* 2733 */ MCD_OPC_Decode, 232, 13, 219, 1, // Opcode: FMOV_S +/* 2738 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 2760 +/* 2743 */ MCD_OPC_CheckPredicate, 53, 14, 56, 0, // Skip to: 17098 +/* 2748 */ MCD_OPC_CheckField, 16, 5, 0, 7, 56, 0, // Skip to: 17098 +/* 2755 */ MCD_OPC_Decode, 251, 13, 219, 1, // Opcode: FNEG_S +/* 2760 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 2782 +/* 2765 */ MCD_OPC_CheckPredicate, 52, 248, 55, 0, // Skip to: 17098 +/* 2770 */ MCD_OPC_CheckField, 16, 5, 0, 241, 55, 0, // Skip to: 17098 +/* 2777 */ MCD_OPC_Decode, 170, 20, 219, 1, // Opcode: ROUND_W_S +/* 2782 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2804 +/* 2787 */ MCD_OPC_CheckPredicate, 52, 226, 55, 0, // Skip to: 17098 +/* 2792 */ MCD_OPC_CheckField, 16, 5, 0, 219, 55, 0, // Skip to: 17098 +/* 2799 */ MCD_OPC_Decode, 142, 24, 219, 1, // Opcode: TRUNC_W_S +/* 2804 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2826 +/* 2809 */ MCD_OPC_CheckPredicate, 52, 204, 55, 0, // Skip to: 17098 +/* 2814 */ MCD_OPC_CheckField, 16, 5, 0, 197, 55, 0, // Skip to: 17098 +/* 2821 */ MCD_OPC_Decode, 133, 9, 219, 1, // Opcode: CEIL_W_S +/* 2826 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2848 +/* 2831 */ MCD_OPC_CheckPredicate, 52, 182, 55, 0, // Skip to: 17098 +/* 2836 */ MCD_OPC_CheckField, 16, 5, 0, 175, 55, 0, // Skip to: 17098 +/* 2843 */ MCD_OPC_Decode, 214, 13, 219, 1, // Opcode: FLOOR_W_S +/* 2848 */ MCD_OPC_FilterValue, 17, 33, 0, 0, // Skip to: 2886 +/* 2853 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 2856 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2871 +/* 2861 */ MCD_OPC_CheckPredicate, 29, 152, 55, 0, // Skip to: 17098 +/* 2866 */ MCD_OPC_Decode, 223, 17, 220, 1, // Opcode: MOVF_S +/* 2871 */ MCD_OPC_FilterValue, 1, 142, 55, 0, // Skip to: 17098 +/* 2876 */ MCD_OPC_CheckPredicate, 29, 137, 55, 0, // Skip to: 17098 +/* 2881 */ MCD_OPC_Decode, 244, 17, 220, 1, // Opcode: MOVT_S +/* 2886 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 2901 +/* 2891 */ MCD_OPC_CheckPredicate, 29, 122, 55, 0, // Skip to: 17098 +/* 2896 */ MCD_OPC_Decode, 128, 18, 221, 1, // Opcode: MOVZ_I_S +/* 2901 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 2916 +/* 2906 */ MCD_OPC_CheckPredicate, 29, 107, 55, 0, // Skip to: 17098 +/* 2911 */ MCD_OPC_Decode, 235, 17, 221, 1, // Opcode: MOVN_I_S +/* 2916 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 2938 +/* 2921 */ MCD_OPC_CheckPredicate, 54, 92, 55, 0, // Skip to: 17098 +/* 2926 */ MCD_OPC_CheckField, 16, 5, 0, 85, 55, 0, // Skip to: 17098 +/* 2933 */ MCD_OPC_Decode, 138, 20, 219, 1, // Opcode: RECIP_S +/* 2938 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 2960 +/* 2943 */ MCD_OPC_CheckPredicate, 54, 70, 55, 0, // Skip to: 17098 +/* 2948 */ MCD_OPC_CheckField, 16, 5, 0, 63, 55, 0, // Skip to: 17098 +/* 2955 */ MCD_OPC_Decode, 177, 20, 219, 1, // Opcode: RSQRT_S +/* 2960 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 2982 +/* 2965 */ MCD_OPC_CheckPredicate, 55, 48, 55, 0, // Skip to: 17098 +/* 2970 */ MCD_OPC_CheckField, 16, 5, 0, 41, 55, 0, // Skip to: 17098 +/* 2977 */ MCD_OPC_Decode, 183, 10, 222, 1, // Opcode: CVT_D32_S +/* 2982 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 3004 +/* 2987 */ MCD_OPC_CheckPredicate, 47, 26, 55, 0, // Skip to: 17098 +/* 2992 */ MCD_OPC_CheckField, 16, 5, 0, 19, 55, 0, // Skip to: 17098 +/* 2999 */ MCD_OPC_Decode, 217, 10, 219, 1, // Opcode: CVT_W_S +/* 3004 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 3026 +/* 3009 */ MCD_OPC_CheckPredicate, 56, 4, 55, 0, // Skip to: 17098 +/* 3014 */ MCD_OPC_CheckField, 16, 5, 0, 253, 54, 0, // Skip to: 17098 +/* 3021 */ MCD_OPC_Decode, 196, 10, 223, 1, // Opcode: CVT_L_S +/* 3026 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 3048 +/* 3031 */ MCD_OPC_CheckPredicate, 50, 238, 54, 0, // Skip to: 17098 +/* 3036 */ MCD_OPC_CheckField, 6, 2, 0, 231, 54, 0, // Skip to: 17098 +/* 3043 */ MCD_OPC_Decode, 230, 10, 224, 1, // Opcode: C_F_S +/* 3048 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 3070 +/* 3053 */ MCD_OPC_CheckPredicate, 50, 216, 54, 0, // Skip to: 17098 +/* 3058 */ MCD_OPC_CheckField, 6, 2, 0, 209, 54, 0, // Skip to: 17098 +/* 3065 */ MCD_OPC_Decode, 186, 11, 224, 1, // Opcode: C_UN_S +/* 3070 */ MCD_OPC_FilterValue, 50, 17, 0, 0, // Skip to: 3092 +/* 3075 */ MCD_OPC_CheckPredicate, 50, 194, 54, 0, // Skip to: 17098 +/* 3080 */ MCD_OPC_CheckField, 6, 2, 0, 187, 54, 0, // Skip to: 17098 +/* 3087 */ MCD_OPC_Decode, 224, 10, 224, 1, // Opcode: C_EQ_S +/* 3092 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 3114 +/* 3097 */ MCD_OPC_CheckPredicate, 50, 172, 54, 0, // Skip to: 17098 +/* 3102 */ MCD_OPC_CheckField, 6, 2, 0, 165, 54, 0, // Skip to: 17098 +/* 3109 */ MCD_OPC_Decode, 168, 11, 224, 1, // Opcode: C_UEQ_S +/* 3114 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 3136 +/* 3119 */ MCD_OPC_CheckPredicate, 50, 150, 54, 0, // Skip to: 17098 +/* 3124 */ MCD_OPC_CheckField, 6, 2, 0, 143, 54, 0, // Skip to: 17098 +/* 3131 */ MCD_OPC_Decode, 150, 11, 224, 1, // Opcode: C_OLT_S +/* 3136 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 3158 +/* 3141 */ MCD_OPC_CheckPredicate, 50, 128, 54, 0, // Skip to: 17098 +/* 3146 */ MCD_OPC_CheckField, 6, 2, 0, 121, 54, 0, // Skip to: 17098 +/* 3153 */ MCD_OPC_Decode, 180, 11, 224, 1, // Opcode: C_ULT_S +/* 3158 */ MCD_OPC_FilterValue, 54, 17, 0, 0, // Skip to: 3180 +/* 3163 */ MCD_OPC_CheckPredicate, 50, 106, 54, 0, // Skip to: 17098 +/* 3168 */ MCD_OPC_CheckField, 6, 2, 0, 99, 54, 0, // Skip to: 17098 +/* 3175 */ MCD_OPC_Decode, 144, 11, 224, 1, // Opcode: C_OLE_S +/* 3180 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 3202 +/* 3185 */ MCD_OPC_CheckPredicate, 50, 84, 54, 0, // Skip to: 17098 +/* 3190 */ MCD_OPC_CheckField, 6, 2, 0, 77, 54, 0, // Skip to: 17098 +/* 3197 */ MCD_OPC_Decode, 174, 11, 224, 1, // Opcode: C_ULE_S +/* 3202 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 3224 +/* 3207 */ MCD_OPC_CheckPredicate, 50, 62, 54, 0, // Skip to: 17098 +/* 3212 */ MCD_OPC_CheckField, 6, 2, 0, 55, 54, 0, // Skip to: 17098 +/* 3219 */ MCD_OPC_Decode, 162, 11, 224, 1, // Opcode: C_SF_S +/* 3224 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 3246 +/* 3229 */ MCD_OPC_CheckPredicate, 50, 40, 54, 0, // Skip to: 17098 +/* 3234 */ MCD_OPC_CheckField, 6, 2, 0, 33, 54, 0, // Skip to: 17098 +/* 3241 */ MCD_OPC_Decode, 254, 10, 224, 1, // Opcode: C_NGLE_S +/* 3246 */ MCD_OPC_FilterValue, 58, 17, 0, 0, // Skip to: 3268 +/* 3251 */ MCD_OPC_CheckPredicate, 50, 18, 54, 0, // Skip to: 17098 +/* 3256 */ MCD_OPC_CheckField, 6, 2, 0, 11, 54, 0, // Skip to: 17098 +/* 3263 */ MCD_OPC_Decode, 156, 11, 224, 1, // Opcode: C_SEQ_S +/* 3268 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 3290 +/* 3273 */ MCD_OPC_CheckPredicate, 50, 252, 53, 0, // Skip to: 17098 +/* 3278 */ MCD_OPC_CheckField, 6, 2, 0, 245, 53, 0, // Skip to: 17098 +/* 3285 */ MCD_OPC_Decode, 132, 11, 224, 1, // Opcode: C_NGL_S +/* 3290 */ MCD_OPC_FilterValue, 60, 17, 0, 0, // Skip to: 3312 +/* 3295 */ MCD_OPC_CheckPredicate, 50, 230, 53, 0, // Skip to: 17098 +/* 3300 */ MCD_OPC_CheckField, 6, 2, 0, 223, 53, 0, // Skip to: 17098 +/* 3307 */ MCD_OPC_Decode, 242, 10, 224, 1, // Opcode: C_LT_S +/* 3312 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 3334 +/* 3317 */ MCD_OPC_CheckPredicate, 50, 208, 53, 0, // Skip to: 17098 +/* 3322 */ MCD_OPC_CheckField, 6, 2, 0, 201, 53, 0, // Skip to: 17098 +/* 3329 */ MCD_OPC_Decode, 248, 10, 224, 1, // Opcode: C_NGE_S +/* 3334 */ MCD_OPC_FilterValue, 62, 17, 0, 0, // Skip to: 3356 +/* 3339 */ MCD_OPC_CheckPredicate, 50, 186, 53, 0, // Skip to: 17098 +/* 3344 */ MCD_OPC_CheckField, 6, 2, 0, 179, 53, 0, // Skip to: 17098 +/* 3351 */ MCD_OPC_Decode, 236, 10, 224, 1, // Opcode: C_LE_S +/* 3356 */ MCD_OPC_FilterValue, 63, 169, 53, 0, // Skip to: 17098 +/* 3361 */ MCD_OPC_CheckPredicate, 50, 164, 53, 0, // Skip to: 17098 +/* 3366 */ MCD_OPC_CheckField, 6, 2, 0, 157, 53, 0, // Skip to: 17098 +/* 3373 */ MCD_OPC_Decode, 138, 11, 224, 1, // Opcode: C_NGT_S +/* 3378 */ MCD_OPC_FilterValue, 17, 1, 3, 0, // Skip to: 4152 +/* 3383 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 3386 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3401 +/* 3391 */ MCD_OPC_CheckPredicate, 55, 134, 53, 0, // Skip to: 17098 +/* 3396 */ MCD_OPC_Decode, 137, 13, 225, 1, // Opcode: FADD_D32 +/* 3401 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3416 +/* 3406 */ MCD_OPC_CheckPredicate, 55, 119, 53, 0, // Skip to: 17098 +/* 3411 */ MCD_OPC_Decode, 155, 14, 225, 1, // Opcode: FSUB_D32 +/* 3416 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 3431 +/* 3421 */ MCD_OPC_CheckPredicate, 55, 104, 53, 0, // Skip to: 17098 +/* 3426 */ MCD_OPC_Decode, 238, 13, 225, 1, // Opcode: FMUL_D32 +/* 3431 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 3446 +/* 3436 */ MCD_OPC_CheckPredicate, 55, 89, 53, 0, // Skip to: 17098 +/* 3441 */ MCD_OPC_Decode, 176, 13, 225, 1, // Opcode: FDIV_D32 +/* 3446 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3468 +/* 3451 */ MCD_OPC_CheckPredicate, 57, 74, 53, 0, // Skip to: 17098 +/* 3456 */ MCD_OPC_CheckField, 16, 5, 0, 67, 53, 0, // Skip to: 17098 +/* 3463 */ MCD_OPC_Decode, 147, 14, 226, 1, // Opcode: FSQRT_D32 +/* 3468 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3490 +/* 3473 */ MCD_OPC_CheckPredicate, 55, 52, 53, 0, // Skip to: 17098 +/* 3478 */ MCD_OPC_CheckField, 16, 5, 0, 45, 53, 0, // Skip to: 17098 +/* 3485 */ MCD_OPC_Decode, 130, 13, 226, 1, // Opcode: FABS_D32 +/* 3490 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3512 +/* 3495 */ MCD_OPC_CheckPredicate, 55, 30, 53, 0, // Skip to: 17098 +/* 3500 */ MCD_OPC_CheckField, 16, 5, 0, 23, 53, 0, // Skip to: 17098 +/* 3507 */ MCD_OPC_Decode, 227, 13, 226, 1, // Opcode: FMOV_D32 +/* 3512 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3534 +/* 3517 */ MCD_OPC_CheckPredicate, 55, 8, 53, 0, // Skip to: 17098 +/* 3522 */ MCD_OPC_CheckField, 16, 5, 0, 1, 53, 0, // Skip to: 17098 +/* 3529 */ MCD_OPC_Decode, 247, 13, 226, 1, // Opcode: FNEG_D32 +/* 3534 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3556 +/* 3539 */ MCD_OPC_CheckPredicate, 57, 242, 52, 0, // Skip to: 17098 +/* 3544 */ MCD_OPC_CheckField, 16, 5, 0, 235, 52, 0, // Skip to: 17098 +/* 3551 */ MCD_OPC_Decode, 166, 20, 227, 1, // Opcode: ROUND_W_D32 +/* 3556 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3578 +/* 3561 */ MCD_OPC_CheckPredicate, 57, 220, 52, 0, // Skip to: 17098 +/* 3566 */ MCD_OPC_CheckField, 16, 5, 0, 213, 52, 0, // Skip to: 17098 +/* 3573 */ MCD_OPC_Decode, 138, 24, 227, 1, // Opcode: TRUNC_W_D32 +/* 3578 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3600 +/* 3583 */ MCD_OPC_CheckPredicate, 57, 198, 52, 0, // Skip to: 17098 +/* 3588 */ MCD_OPC_CheckField, 16, 5, 0, 191, 52, 0, // Skip to: 17098 +/* 3595 */ MCD_OPC_Decode, 129, 9, 227, 1, // Opcode: CEIL_W_D32 +/* 3600 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 3622 +/* 3605 */ MCD_OPC_CheckPredicate, 57, 176, 52, 0, // Skip to: 17098 +/* 3610 */ MCD_OPC_CheckField, 16, 5, 0, 169, 52, 0, // Skip to: 17098 +/* 3617 */ MCD_OPC_Decode, 210, 13, 227, 1, // Opcode: FLOOR_W_D32 +/* 3622 */ MCD_OPC_FilterValue, 17, 33, 0, 0, // Skip to: 3660 +/* 3627 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 3630 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3645 +/* 3635 */ MCD_OPC_CheckPredicate, 58, 146, 52, 0, // Skip to: 17098 +/* 3640 */ MCD_OPC_Decode, 217, 17, 228, 1, // Opcode: MOVF_D32 +/* 3645 */ MCD_OPC_FilterValue, 1, 136, 52, 0, // Skip to: 17098 +/* 3650 */ MCD_OPC_CheckPredicate, 58, 131, 52, 0, // Skip to: 17098 +/* 3655 */ MCD_OPC_Decode, 238, 17, 228, 1, // Opcode: MOVT_D32 +/* 3660 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 3675 +/* 3665 */ MCD_OPC_CheckPredicate, 58, 116, 52, 0, // Skip to: 17098 +/* 3670 */ MCD_OPC_Decode, 250, 17, 229, 1, // Opcode: MOVZ_I_D32 +/* 3675 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 3690 +/* 3680 */ MCD_OPC_CheckPredicate, 58, 101, 52, 0, // Skip to: 17098 +/* 3685 */ MCD_OPC_Decode, 229, 17, 229, 1, // Opcode: MOVN_I_D32 +/* 3690 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 3712 +/* 3695 */ MCD_OPC_CheckPredicate, 59, 86, 52, 0, // Skip to: 17098 +/* 3700 */ MCD_OPC_CheckField, 16, 5, 0, 79, 52, 0, // Skip to: 17098 +/* 3707 */ MCD_OPC_Decode, 134, 20, 226, 1, // Opcode: RECIP_D32 +/* 3712 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 3734 +/* 3717 */ MCD_OPC_CheckPredicate, 59, 64, 52, 0, // Skip to: 17098 +/* 3722 */ MCD_OPC_CheckField, 16, 5, 0, 57, 52, 0, // Skip to: 17098 +/* 3729 */ MCD_OPC_Decode, 173, 20, 226, 1, // Opcode: RSQRT_D32 +/* 3734 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 3756 +/* 3739 */ MCD_OPC_CheckPredicate, 55, 42, 52, 0, // Skip to: 17098 +/* 3744 */ MCD_OPC_CheckField, 16, 5, 0, 35, 52, 0, // Skip to: 17098 +/* 3751 */ MCD_OPC_Decode, 202, 10, 227, 1, // Opcode: CVT_S_D32 +/* 3756 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 3778 +/* 3761 */ MCD_OPC_CheckPredicate, 55, 20, 52, 0, // Skip to: 17098 +/* 3766 */ MCD_OPC_CheckField, 16, 5, 0, 13, 52, 0, // Skip to: 17098 +/* 3773 */ MCD_OPC_Decode, 213, 10, 227, 1, // Opcode: CVT_W_D32 +/* 3778 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 3800 +/* 3783 */ MCD_OPC_CheckPredicate, 56, 254, 51, 0, // Skip to: 17098 +/* 3788 */ MCD_OPC_CheckField, 16, 5, 0, 247, 51, 0, // Skip to: 17098 +/* 3795 */ MCD_OPC_Decode, 193, 10, 230, 1, // Opcode: CVT_L_D64 +/* 3800 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 3822 +/* 3805 */ MCD_OPC_CheckPredicate, 60, 232, 51, 0, // Skip to: 17098 +/* 3810 */ MCD_OPC_CheckField, 6, 2, 0, 225, 51, 0, // Skip to: 17098 +/* 3817 */ MCD_OPC_Decode, 226, 10, 231, 1, // Opcode: C_F_D32 +/* 3822 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 3844 +/* 3827 */ MCD_OPC_CheckPredicate, 60, 210, 51, 0, // Skip to: 17098 +/* 3832 */ MCD_OPC_CheckField, 6, 2, 0, 203, 51, 0, // Skip to: 17098 +/* 3839 */ MCD_OPC_Decode, 182, 11, 231, 1, // Opcode: C_UN_D32 +/* 3844 */ MCD_OPC_FilterValue, 50, 17, 0, 0, // Skip to: 3866 +/* 3849 */ MCD_OPC_CheckPredicate, 60, 188, 51, 0, // Skip to: 17098 +/* 3854 */ MCD_OPC_CheckField, 6, 2, 0, 181, 51, 0, // Skip to: 17098 +/* 3861 */ MCD_OPC_Decode, 220, 10, 231, 1, // Opcode: C_EQ_D32 +/* 3866 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 3888 +/* 3871 */ MCD_OPC_CheckPredicate, 60, 166, 51, 0, // Skip to: 17098 +/* 3876 */ MCD_OPC_CheckField, 6, 2, 0, 159, 51, 0, // Skip to: 17098 +/* 3883 */ MCD_OPC_Decode, 164, 11, 231, 1, // Opcode: C_UEQ_D32 +/* 3888 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 3910 +/* 3893 */ MCD_OPC_CheckPredicate, 60, 144, 51, 0, // Skip to: 17098 +/* 3898 */ MCD_OPC_CheckField, 6, 2, 0, 137, 51, 0, // Skip to: 17098 +/* 3905 */ MCD_OPC_Decode, 146, 11, 231, 1, // Opcode: C_OLT_D32 +/* 3910 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 3932 +/* 3915 */ MCD_OPC_CheckPredicate, 60, 122, 51, 0, // Skip to: 17098 +/* 3920 */ MCD_OPC_CheckField, 6, 2, 0, 115, 51, 0, // Skip to: 17098 +/* 3927 */ MCD_OPC_Decode, 176, 11, 231, 1, // Opcode: C_ULT_D32 +/* 3932 */ MCD_OPC_FilterValue, 54, 17, 0, 0, // Skip to: 3954 +/* 3937 */ MCD_OPC_CheckPredicate, 60, 100, 51, 0, // Skip to: 17098 +/* 3942 */ MCD_OPC_CheckField, 6, 2, 0, 93, 51, 0, // Skip to: 17098 +/* 3949 */ MCD_OPC_Decode, 140, 11, 231, 1, // Opcode: C_OLE_D32 +/* 3954 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 3976 +/* 3959 */ MCD_OPC_CheckPredicate, 60, 78, 51, 0, // Skip to: 17098 +/* 3964 */ MCD_OPC_CheckField, 6, 2, 0, 71, 51, 0, // Skip to: 17098 +/* 3971 */ MCD_OPC_Decode, 170, 11, 231, 1, // Opcode: C_ULE_D32 +/* 3976 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 3998 +/* 3981 */ MCD_OPC_CheckPredicate, 60, 56, 51, 0, // Skip to: 17098 +/* 3986 */ MCD_OPC_CheckField, 6, 2, 0, 49, 51, 0, // Skip to: 17098 +/* 3993 */ MCD_OPC_Decode, 158, 11, 231, 1, // Opcode: C_SF_D32 +/* 3998 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 4020 +/* 4003 */ MCD_OPC_CheckPredicate, 60, 34, 51, 0, // Skip to: 17098 +/* 4008 */ MCD_OPC_CheckField, 6, 2, 0, 27, 51, 0, // Skip to: 17098 +/* 4015 */ MCD_OPC_Decode, 250, 10, 231, 1, // Opcode: C_NGLE_D32 +/* 4020 */ MCD_OPC_FilterValue, 58, 17, 0, 0, // Skip to: 4042 +/* 4025 */ MCD_OPC_CheckPredicate, 60, 12, 51, 0, // Skip to: 17098 +/* 4030 */ MCD_OPC_CheckField, 6, 2, 0, 5, 51, 0, // Skip to: 17098 +/* 4037 */ MCD_OPC_Decode, 152, 11, 231, 1, // Opcode: C_SEQ_D32 +/* 4042 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 4064 +/* 4047 */ MCD_OPC_CheckPredicate, 60, 246, 50, 0, // Skip to: 17098 +/* 4052 */ MCD_OPC_CheckField, 6, 2, 0, 239, 50, 0, // Skip to: 17098 +/* 4059 */ MCD_OPC_Decode, 128, 11, 231, 1, // Opcode: C_NGL_D32 +/* 4064 */ MCD_OPC_FilterValue, 60, 17, 0, 0, // Skip to: 4086 +/* 4069 */ MCD_OPC_CheckPredicate, 60, 224, 50, 0, // Skip to: 17098 +/* 4074 */ MCD_OPC_CheckField, 6, 2, 0, 217, 50, 0, // Skip to: 17098 +/* 4081 */ MCD_OPC_Decode, 238, 10, 231, 1, // Opcode: C_LT_D32 +/* 4086 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 4108 +/* 4091 */ MCD_OPC_CheckPredicate, 60, 202, 50, 0, // Skip to: 17098 +/* 4096 */ MCD_OPC_CheckField, 6, 2, 0, 195, 50, 0, // Skip to: 17098 +/* 4103 */ MCD_OPC_Decode, 244, 10, 231, 1, // Opcode: C_NGE_D32 +/* 4108 */ MCD_OPC_FilterValue, 62, 17, 0, 0, // Skip to: 4130 +/* 4113 */ MCD_OPC_CheckPredicate, 60, 180, 50, 0, // Skip to: 17098 +/* 4118 */ MCD_OPC_CheckField, 6, 2, 0, 173, 50, 0, // Skip to: 17098 +/* 4125 */ MCD_OPC_Decode, 232, 10, 231, 1, // Opcode: C_LE_D32 +/* 4130 */ MCD_OPC_FilterValue, 63, 163, 50, 0, // Skip to: 17098 +/* 4135 */ MCD_OPC_CheckPredicate, 60, 158, 50, 0, // Skip to: 17098 +/* 4140 */ MCD_OPC_CheckField, 6, 2, 0, 151, 50, 0, // Skip to: 17098 +/* 4147 */ MCD_OPC_Decode, 134, 11, 231, 1, // Opcode: C_NGT_D32 +/* 4152 */ MCD_OPC_FilterValue, 20, 47, 0, 0, // Skip to: 4204 +/* 4157 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 4160 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 4182 +/* 4165 */ MCD_OPC_CheckPredicate, 47, 128, 50, 0, // Skip to: 17098 +/* 4170 */ MCD_OPC_CheckField, 16, 5, 0, 121, 50, 0, // Skip to: 17098 +/* 4177 */ MCD_OPC_Decode, 210, 10, 219, 1, // Opcode: CVT_S_W +/* 4182 */ MCD_OPC_FilterValue, 33, 111, 50, 0, // Skip to: 17098 +/* 4187 */ MCD_OPC_CheckPredicate, 55, 106, 50, 0, // Skip to: 17098 +/* 4192 */ MCD_OPC_CheckField, 16, 5, 0, 99, 50, 0, // Skip to: 17098 +/* 4199 */ MCD_OPC_Decode, 185, 10, 222, 1, // Opcode: CVT_D32_W +/* 4204 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 4219 +/* 4209 */ MCD_OPC_CheckPredicate, 30, 84, 50, 0, // Skip to: 17098 +/* 4214 */ MCD_OPC_Decode, 230, 8, 217, 1, // Opcode: BZ_B +/* 4219 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 4234 +/* 4224 */ MCD_OPC_CheckPredicate, 30, 69, 50, 0, // Skip to: 17098 +/* 4229 */ MCD_OPC_Decode, 232, 8, 232, 1, // Opcode: BZ_H +/* 4234 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 4249 +/* 4239 */ MCD_OPC_CheckPredicate, 30, 54, 50, 0, // Skip to: 17098 +/* 4244 */ MCD_OPC_Decode, 234, 8, 233, 1, // Opcode: BZ_W +/* 4249 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 4264 +/* 4254 */ MCD_OPC_CheckPredicate, 30, 39, 50, 0, // Skip to: 17098 +/* 4259 */ MCD_OPC_Decode, 231, 8, 234, 1, // Opcode: BZ_D +/* 4264 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 4279 +/* 4269 */ MCD_OPC_CheckPredicate, 30, 24, 50, 0, // Skip to: 17098 +/* 4274 */ MCD_OPC_Decode, 201, 8, 217, 1, // Opcode: BNZ_B +/* 4279 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 4294 +/* 4284 */ MCD_OPC_CheckPredicate, 30, 9, 50, 0, // Skip to: 17098 +/* 4289 */ MCD_OPC_Decode, 203, 8, 232, 1, // Opcode: BNZ_H +/* 4294 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 4309 +/* 4299 */ MCD_OPC_CheckPredicate, 30, 250, 49, 0, // Skip to: 17098 +/* 4304 */ MCD_OPC_Decode, 205, 8, 233, 1, // Opcode: BNZ_W +/* 4309 */ MCD_OPC_FilterValue, 31, 240, 49, 0, // Skip to: 17098 +/* 4314 */ MCD_OPC_CheckPredicate, 30, 235, 49, 0, // Skip to: 17098 +/* 4319 */ MCD_OPC_Decode, 202, 8, 234, 1, // Opcode: BNZ_D +/* 4324 */ MCD_OPC_FilterValue, 18, 47, 0, 0, // Skip to: 4376 +/* 4329 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 4332 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4354 +/* 4337 */ MCD_OPC_CheckPredicate, 27, 212, 49, 0, // Skip to: 17098 +/* 4342 */ MCD_OPC_CheckField, 3, 8, 0, 205, 49, 0, // Skip to: 17098 +/* 4349 */ MCD_OPC_Decode, 136, 17, 235, 1, // Opcode: MFC2 +/* 4354 */ MCD_OPC_FilterValue, 4, 195, 49, 0, // Skip to: 17098 +/* 4359 */ MCD_OPC_CheckPredicate, 27, 190, 49, 0, // Skip to: 17098 +/* 4364 */ MCD_OPC_CheckField, 3, 8, 0, 183, 49, 0, // Skip to: 17098 +/* 4371 */ MCD_OPC_Decode, 165, 18, 236, 1, // Opcode: MTC2 +/* 4376 */ MCD_OPC_FilterValue, 19, 255, 0, 0, // Skip to: 4636 +/* 4381 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 4384 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4406 +/* 4389 */ MCD_OPC_CheckPredicate, 61, 160, 49, 0, // Skip to: 17098 +/* 4394 */ MCD_OPC_CheckField, 11, 5, 0, 153, 49, 0, // Skip to: 17098 +/* 4401 */ MCD_OPC_Decode, 172, 16, 237, 1, // Opcode: LWXC1 +/* 4406 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4428 +/* 4411 */ MCD_OPC_CheckPredicate, 62, 138, 49, 0, // Skip to: 17098 +/* 4416 */ MCD_OPC_CheckField, 11, 5, 0, 131, 49, 0, // Skip to: 17098 +/* 4423 */ MCD_OPC_Decode, 196, 15, 238, 1, // Opcode: LDXC1 +/* 4428 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4450 +/* 4433 */ MCD_OPC_CheckPredicate, 63, 116, 49, 0, // Skip to: 17098 +/* 4438 */ MCD_OPC_CheckField, 11, 5, 0, 109, 49, 0, // Skip to: 17098 +/* 4445 */ MCD_OPC_Decode, 253, 15, 238, 1, // Opcode: LUXC1 +/* 4450 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4472 +/* 4455 */ MCD_OPC_CheckPredicate, 61, 94, 49, 0, // Skip to: 17098 +/* 4460 */ MCD_OPC_CheckField, 6, 5, 0, 87, 49, 0, // Skip to: 17098 +/* 4467 */ MCD_OPC_Decode, 165, 23, 239, 1, // Opcode: SWXC1 +/* 4472 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4494 +/* 4477 */ MCD_OPC_CheckPredicate, 62, 72, 49, 0, // Skip to: 17098 +/* 4482 */ MCD_OPC_CheckField, 6, 5, 0, 65, 49, 0, // Skip to: 17098 +/* 4489 */ MCD_OPC_Decode, 240, 20, 240, 1, // Opcode: SDXC1 +/* 4494 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4516 +/* 4499 */ MCD_OPC_CheckPredicate, 63, 50, 49, 0, // Skip to: 17098 +/* 4504 */ MCD_OPC_CheckField, 6, 5, 0, 43, 49, 0, // Skip to: 17098 +/* 4511 */ MCD_OPC_Decode, 253, 22, 240, 1, // Opcode: SUXC1 +/* 4516 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 4531 +/* 4521 */ MCD_OPC_CheckPredicate, 64, 28, 49, 0, // Skip to: 17098 +/* 4526 */ MCD_OPC_Decode, 218, 16, 241, 1, // Opcode: MADD_S +/* 4531 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 4546 +/* 4536 */ MCD_OPC_CheckPredicate, 65, 13, 49, 0, // Skip to: 17098 +/* 4541 */ MCD_OPC_Decode, 210, 16, 242, 1, // Opcode: MADD_D32 +/* 4546 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 4561 +/* 4551 */ MCD_OPC_CheckPredicate, 64, 254, 48, 0, // Skip to: 17098 +/* 4556 */ MCD_OPC_Decode, 154, 18, 241, 1, // Opcode: MSUB_S +/* 4561 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 4576 +/* 4566 */ MCD_OPC_CheckPredicate, 65, 239, 48, 0, // Skip to: 17098 +/* 4571 */ MCD_OPC_Decode, 146, 18, 242, 1, // Opcode: MSUB_D32 +/* 4576 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 4591 +/* 4581 */ MCD_OPC_CheckPredicate, 66, 224, 48, 0, // Skip to: 17098 +/* 4586 */ MCD_OPC_Decode, 142, 19, 241, 1, // Opcode: NMADD_S +/* 4591 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 4606 +/* 4596 */ MCD_OPC_CheckPredicate, 67, 209, 48, 0, // Skip to: 17098 +/* 4601 */ MCD_OPC_Decode, 139, 19, 242, 1, // Opcode: NMADD_D32 +/* 4606 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 4621 +/* 4611 */ MCD_OPC_CheckPredicate, 66, 194, 48, 0, // Skip to: 17098 +/* 4616 */ MCD_OPC_Decode, 147, 19, 241, 1, // Opcode: NMSUB_S +/* 4621 */ MCD_OPC_FilterValue, 57, 184, 48, 0, // Skip to: 17098 +/* 4626 */ MCD_OPC_CheckPredicate, 67, 179, 48, 0, // Skip to: 17098 +/* 4631 */ MCD_OPC_Decode, 144, 19, 242, 1, // Opcode: NMSUB_D32 +/* 4636 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 4651 +/* 4641 */ MCD_OPC_CheckPredicate, 39, 164, 48, 0, // Skip to: 17098 +/* 4646 */ MCD_OPC_Decode, 197, 7, 201, 1, // Opcode: BEQL +/* 4651 */ MCD_OPC_FilterValue, 21, 107, 0, 0, // Skip to: 4763 +/* 4656 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... +/* 4659 */ MCD_OPC_FilterValue, 123, 9, 0, 0, // Skip to: 4673 +/* 4664 */ MCD_OPC_CheckPredicate, 19, 19, 0, 0, // Skip to: 4688 +/* 4669 */ MCD_OPC_Decode, 233, 13, 124, // Opcode: FMOV_S_MM +/* 4673 */ MCD_OPC_FilterValue, 251, 22, 9, 0, 0, // Skip to: 4688 +/* 4679 */ MCD_OPC_CheckPredicate, 19, 4, 0, 0, // Skip to: 4688 +/* 4684 */ MCD_OPC_Decode, 252, 13, 124, // Opcode: FNEG_S_MM +/* 4688 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 4691 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 4706 +/* 4696 */ MCD_OPC_CheckPredicate, 19, 52, 0, 0, // Skip to: 4753 +/* 4701 */ MCD_OPC_Decode, 143, 13, 164, 1, // Opcode: FADD_S_MM +/* 4706 */ MCD_OPC_FilterValue, 112, 10, 0, 0, // Skip to: 4721 +/* 4711 */ MCD_OPC_CheckPredicate, 19, 37, 0, 0, // Skip to: 4753 +/* 4716 */ MCD_OPC_Decode, 161, 14, 164, 1, // Opcode: FSUB_S_MM +/* 4721 */ MCD_OPC_FilterValue, 176, 1, 10, 0, 0, // Skip to: 4737 +/* 4727 */ MCD_OPC_CheckPredicate, 19, 21, 0, 0, // Skip to: 4753 +/* 4732 */ MCD_OPC_Decode, 244, 13, 164, 1, // Opcode: FMUL_S_MM +/* 4737 */ MCD_OPC_FilterValue, 240, 1, 10, 0, 0, // Skip to: 4753 +/* 4743 */ MCD_OPC_CheckPredicate, 19, 5, 0, 0, // Skip to: 4753 +/* 4748 */ MCD_OPC_Decode, 181, 13, 164, 1, // Opcode: FDIV_S_MM +/* 4753 */ MCD_OPC_CheckPredicate, 39, 52, 48, 0, // Skip to: 17098 +/* 4758 */ MCD_OPC_Decode, 187, 8, 201, 1, // Opcode: BNEL +/* 4763 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 4785 +/* 4768 */ MCD_OPC_CheckPredicate, 39, 37, 48, 0, // Skip to: 17098 +/* 4773 */ MCD_OPC_CheckField, 16, 5, 0, 30, 48, 0, // Skip to: 17098 +/* 4780 */ MCD_OPC_Decode, 141, 8, 197, 1, // Opcode: BLEZL +/* 4785 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 4807 +/* 4790 */ MCD_OPC_CheckPredicate, 39, 15, 48, 0, // Skip to: 17098 +/* 4795 */ MCD_OPC_CheckField, 16, 5, 0, 8, 48, 0, // Skip to: 17098 +/* 4802 */ MCD_OPC_Decode, 239, 7, 197, 1, // Opcode: BGTZL +/* 4807 */ MCD_OPC_FilterValue, 28, 15, 1, 0, // Skip to: 5083 +/* 4812 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 4815 */ MCD_OPC_FilterValue, 0, 42, 0, 0, // Skip to: 4862 +/* 4820 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4823 */ MCD_OPC_FilterValue, 0, 238, 47, 0, // Skip to: 17098 +/* 4828 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4831 */ MCD_OPC_FilterValue, 0, 230, 47, 0, // Skip to: 17098 +/* 4836 */ MCD_OPC_CheckPredicate, 68, 11, 0, 0, // Skip to: 4852 +/* 4841 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4852 +/* 4848 */ MCD_OPC_Decode, 195, 16, 80, // Opcode: MADD +/* 4852 */ MCD_OPC_CheckPredicate, 37, 209, 47, 0, // Skip to: 17098 +/* 4857 */ MCD_OPC_Decode, 213, 16, 243, 1, // Opcode: MADD_DSP +/* 4862 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 4909 +/* 4867 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4870 */ MCD_OPC_FilterValue, 0, 191, 47, 0, // Skip to: 17098 +/* 4875 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4878 */ MCD_OPC_FilterValue, 0, 183, 47, 0, // Skip to: 17098 +/* 4883 */ MCD_OPC_CheckPredicate, 68, 11, 0, 0, // Skip to: 4899 +/* 4888 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4899 +/* 4895 */ MCD_OPC_Decode, 202, 16, 80, // Opcode: MADDU +/* 4899 */ MCD_OPC_CheckPredicate, 37, 162, 47, 0, // Skip to: 17098 +/* 4904 */ MCD_OPC_Decode, 203, 16, 243, 1, // Opcode: MADDU_DSP +/* 4909 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 4930 +/* 4914 */ MCD_OPC_CheckPredicate, 68, 147, 47, 0, // Skip to: 17098 +/* 4919 */ MCD_OPC_CheckField, 6, 5, 0, 140, 47, 0, // Skip to: 17098 +/* 4926 */ MCD_OPC_Decode, 205, 18, 61, // Opcode: MUL +/* 4930 */ MCD_OPC_FilterValue, 4, 42, 0, 0, // Skip to: 4977 +/* 4935 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4938 */ MCD_OPC_FilterValue, 0, 123, 47, 0, // Skip to: 17098 +/* 4943 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4946 */ MCD_OPC_FilterValue, 0, 115, 47, 0, // Skip to: 17098 +/* 4951 */ MCD_OPC_CheckPredicate, 68, 11, 0, 0, // Skip to: 4967 +/* 4956 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4967 +/* 4963 */ MCD_OPC_Decode, 131, 18, 80, // Opcode: MSUB +/* 4967 */ MCD_OPC_CheckPredicate, 37, 94, 47, 0, // Skip to: 17098 +/* 4972 */ MCD_OPC_Decode, 149, 18, 243, 1, // Opcode: MSUB_DSP +/* 4977 */ MCD_OPC_FilterValue, 5, 42, 0, 0, // Skip to: 5024 +/* 4982 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4985 */ MCD_OPC_FilterValue, 0, 76, 47, 0, // Skip to: 17098 +/* 4990 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4993 */ MCD_OPC_FilterValue, 0, 68, 47, 0, // Skip to: 17098 +/* 4998 */ MCD_OPC_CheckPredicate, 68, 11, 0, 0, // Skip to: 5014 +/* 5003 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 5014 +/* 5010 */ MCD_OPC_Decode, 138, 18, 80, // Opcode: MSUBU +/* 5014 */ MCD_OPC_CheckPredicate, 37, 47, 47, 0, // Skip to: 17098 +/* 5019 */ MCD_OPC_Decode, 139, 18, 243, 1, // Opcode: MSUBU_DSP +/* 5024 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 5046 +/* 5029 */ MCD_OPC_CheckPredicate, 68, 32, 47, 0, // Skip to: 17098 +/* 5034 */ MCD_OPC_CheckField, 6, 5, 0, 25, 47, 0, // Skip to: 17098 +/* 5041 */ MCD_OPC_Decode, 193, 9, 244, 1, // Opcode: CLZ +/* 5046 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 5068 +/* 5051 */ MCD_OPC_CheckPredicate, 68, 10, 47, 0, // Skip to: 17098 +/* 5056 */ MCD_OPC_CheckField, 6, 5, 0, 3, 47, 0, // Skip to: 17098 +/* 5063 */ MCD_OPC_Decode, 172, 9, 244, 1, // Opcode: CLO +/* 5068 */ MCD_OPC_FilterValue, 63, 249, 46, 0, // Skip to: 17098 +/* 5073 */ MCD_OPC_CheckPredicate, 68, 244, 46, 0, // Skip to: 17098 +/* 5078 */ MCD_OPC_Decode, 219, 20, 188, 1, // Opcode: SDBBP +/* 5083 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 5098 +/* 5088 */ MCD_OPC_CheckPredicate, 68, 229, 46, 0, // Skip to: 17098 +/* 5093 */ MCD_OPC_Decode, 251, 14, 200, 1, // Opcode: JALX +/* 5098 */ MCD_OPC_FilterValue, 30, 201, 32, 0, // Skip to: 13496 +/* 5103 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 5106 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 5174 +/* 5111 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 5114 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5129 +/* 5119 */ MCD_OPC_CheckPredicate, 30, 198, 46, 0, // Skip to: 17098 +/* 5124 */ MCD_OPC_Decode, 224, 6, 245, 1, // Opcode: ANDI_B +/* 5129 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5144 +/* 5134 */ MCD_OPC_CheckPredicate, 30, 183, 46, 0, // Skip to: 17098 +/* 5139 */ MCD_OPC_Decode, 168, 19, 245, 1, // Opcode: ORI_B +/* 5144 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5159 +/* 5149 */ MCD_OPC_CheckPredicate, 30, 168, 46, 0, // Skip to: 17098 +/* 5154 */ MCD_OPC_Decode, 153, 19, 245, 1, // Opcode: NORI_B +/* 5159 */ MCD_OPC_FilterValue, 3, 158, 46, 0, // Skip to: 17098 +/* 5164 */ MCD_OPC_CheckPredicate, 30, 153, 46, 0, // Skip to: 17098 +/* 5169 */ MCD_OPC_Decode, 177, 24, 245, 1, // Opcode: XORI_B +/* 5174 */ MCD_OPC_FilterValue, 1, 48, 0, 0, // Skip to: 5227 +/* 5179 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 5182 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5197 +/* 5187 */ MCD_OPC_CheckPredicate, 30, 130, 46, 0, // Skip to: 17098 +/* 5192 */ MCD_OPC_Decode, 166, 8, 246, 1, // Opcode: BMNZI_B +/* 5197 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5212 +/* 5202 */ MCD_OPC_CheckPredicate, 30, 115, 46, 0, // Skip to: 17098 +/* 5207 */ MCD_OPC_Decode, 168, 8, 246, 1, // Opcode: BMZI_B +/* 5212 */ MCD_OPC_FilterValue, 2, 105, 46, 0, // Skip to: 17098 +/* 5217 */ MCD_OPC_CheckPredicate, 30, 100, 46, 0, // Skip to: 17098 +/* 5222 */ MCD_OPC_Decode, 219, 8, 246, 1, // Opcode: BSELI_B +/* 5227 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 5280 +/* 5232 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 5235 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5250 +/* 5240 */ MCD_OPC_CheckPredicate, 30, 77, 46, 0, // Skip to: 17098 +/* 5245 */ MCD_OPC_Decode, 150, 21, 245, 1, // Opcode: SHF_B +/* 5250 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5265 +/* 5255 */ MCD_OPC_CheckPredicate, 30, 62, 46, 0, // Skip to: 17098 +/* 5260 */ MCD_OPC_Decode, 151, 21, 247, 1, // Opcode: SHF_H +/* 5265 */ MCD_OPC_FilterValue, 2, 52, 46, 0, // Skip to: 17098 +/* 5270 */ MCD_OPC_CheckPredicate, 30, 47, 46, 0, // Skip to: 17098 +/* 5275 */ MCD_OPC_Decode, 152, 21, 248, 1, // Opcode: SHF_W +/* 5280 */ MCD_OPC_FilterValue, 6, 107, 1, 0, // Skip to: 5648 +/* 5285 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 5288 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5303 +/* 5293 */ MCD_OPC_CheckPredicate, 30, 24, 46, 0, // Skip to: 17098 +/* 5298 */ MCD_OPC_Decode, 185, 6, 249, 1, // Opcode: ADDVI_B +/* 5303 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5318 +/* 5308 */ MCD_OPC_CheckPredicate, 30, 9, 46, 0, // Skip to: 17098 +/* 5313 */ MCD_OPC_Decode, 187, 6, 250, 1, // Opcode: ADDVI_H +/* 5318 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5333 +/* 5323 */ MCD_OPC_CheckPredicate, 30, 250, 45, 0, // Skip to: 17098 +/* 5328 */ MCD_OPC_Decode, 188, 6, 251, 1, // Opcode: ADDVI_W +/* 5333 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5348 +/* 5338 */ MCD_OPC_CheckPredicate, 30, 235, 45, 0, // Skip to: 17098 +/* 5343 */ MCD_OPC_Decode, 186, 6, 252, 1, // Opcode: ADDVI_D +/* 5348 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 5363 +/* 5353 */ MCD_OPC_CheckPredicate, 30, 220, 45, 0, // Skip to: 17098 +/* 5358 */ MCD_OPC_Decode, 238, 22, 249, 1, // Opcode: SUBVI_B +/* 5363 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 5378 +/* 5368 */ MCD_OPC_CheckPredicate, 30, 205, 45, 0, // Skip to: 17098 +/* 5373 */ MCD_OPC_Decode, 240, 22, 250, 1, // Opcode: SUBVI_H +/* 5378 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 5393 +/* 5383 */ MCD_OPC_CheckPredicate, 30, 190, 45, 0, // Skip to: 17098 +/* 5388 */ MCD_OPC_Decode, 241, 22, 251, 1, // Opcode: SUBVI_W +/* 5393 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 5408 +/* 5398 */ MCD_OPC_CheckPredicate, 30, 175, 45, 0, // Skip to: 17098 +/* 5403 */ MCD_OPC_Decode, 239, 22, 252, 1, // Opcode: SUBVI_D +/* 5408 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 5423 +/* 5413 */ MCD_OPC_CheckPredicate, 30, 160, 45, 0, // Skip to: 17098 +/* 5418 */ MCD_OPC_Decode, 232, 16, 249, 1, // Opcode: MAXI_S_B +/* 5423 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 5438 +/* 5428 */ MCD_OPC_CheckPredicate, 30, 145, 45, 0, // Skip to: 17098 +/* 5433 */ MCD_OPC_Decode, 234, 16, 250, 1, // Opcode: MAXI_S_H +/* 5438 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 5453 +/* 5443 */ MCD_OPC_CheckPredicate, 30, 130, 45, 0, // Skip to: 17098 +/* 5448 */ MCD_OPC_Decode, 235, 16, 251, 1, // Opcode: MAXI_S_W +/* 5453 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 5468 +/* 5458 */ MCD_OPC_CheckPredicate, 30, 115, 45, 0, // Skip to: 17098 +/* 5463 */ MCD_OPC_Decode, 233, 16, 252, 1, // Opcode: MAXI_S_D +/* 5468 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 5483 +/* 5473 */ MCD_OPC_CheckPredicate, 30, 100, 45, 0, // Skip to: 17098 +/* 5478 */ MCD_OPC_Decode, 236, 16, 249, 1, // Opcode: MAXI_U_B +/* 5483 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5498 +/* 5488 */ MCD_OPC_CheckPredicate, 30, 85, 45, 0, // Skip to: 17098 +/* 5493 */ MCD_OPC_Decode, 238, 16, 250, 1, // Opcode: MAXI_U_H +/* 5498 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 5513 +/* 5503 */ MCD_OPC_CheckPredicate, 30, 70, 45, 0, // Skip to: 17098 +/* 5508 */ MCD_OPC_Decode, 239, 16, 251, 1, // Opcode: MAXI_U_W +/* 5513 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5528 +/* 5518 */ MCD_OPC_CheckPredicate, 30, 55, 45, 0, // Skip to: 17098 +/* 5523 */ MCD_OPC_Decode, 237, 16, 252, 1, // Opcode: MAXI_U_D +/* 5528 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 5543 +/* 5533 */ MCD_OPC_CheckPredicate, 30, 40, 45, 0, // Skip to: 17098 +/* 5538 */ MCD_OPC_Decode, 168, 17, 249, 1, // Opcode: MINI_S_B +/* 5543 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 5558 +/* 5548 */ MCD_OPC_CheckPredicate, 30, 25, 45, 0, // Skip to: 17098 +/* 5553 */ MCD_OPC_Decode, 170, 17, 250, 1, // Opcode: MINI_S_H +/* 5558 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 5573 +/* 5563 */ MCD_OPC_CheckPredicate, 30, 10, 45, 0, // Skip to: 17098 +/* 5568 */ MCD_OPC_Decode, 171, 17, 251, 1, // Opcode: MINI_S_W +/* 5573 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 5588 +/* 5578 */ MCD_OPC_CheckPredicate, 30, 251, 44, 0, // Skip to: 17098 +/* 5583 */ MCD_OPC_Decode, 169, 17, 252, 1, // Opcode: MINI_S_D +/* 5588 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 5603 +/* 5593 */ MCD_OPC_CheckPredicate, 30, 236, 44, 0, // Skip to: 17098 +/* 5598 */ MCD_OPC_Decode, 172, 17, 249, 1, // Opcode: MINI_U_B +/* 5603 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 5618 +/* 5608 */ MCD_OPC_CheckPredicate, 30, 221, 44, 0, // Skip to: 17098 +/* 5613 */ MCD_OPC_Decode, 174, 17, 250, 1, // Opcode: MINI_U_H +/* 5618 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 5633 +/* 5623 */ MCD_OPC_CheckPredicate, 30, 206, 44, 0, // Skip to: 17098 +/* 5628 */ MCD_OPC_Decode, 175, 17, 251, 1, // Opcode: MINI_U_W +/* 5633 */ MCD_OPC_FilterValue, 23, 196, 44, 0, // Skip to: 17098 +/* 5638 */ MCD_OPC_CheckPredicate, 30, 191, 44, 0, // Skip to: 17098 +/* 5643 */ MCD_OPC_Decode, 173, 17, 252, 1, // Opcode: MINI_U_D +/* 5648 */ MCD_OPC_FilterValue, 7, 107, 1, 0, // Skip to: 6016 +/* 5653 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 5656 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5671 +/* 5661 */ MCD_OPC_CheckPredicate, 30, 168, 44, 0, // Skip to: 17098 +/* 5666 */ MCD_OPC_Decode, 136, 9, 249, 1, // Opcode: CEQI_B +/* 5671 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5686 +/* 5676 */ MCD_OPC_CheckPredicate, 30, 153, 44, 0, // Skip to: 17098 +/* 5681 */ MCD_OPC_Decode, 138, 9, 250, 1, // Opcode: CEQI_H +/* 5686 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5701 +/* 5691 */ MCD_OPC_CheckPredicate, 30, 138, 44, 0, // Skip to: 17098 +/* 5696 */ MCD_OPC_Decode, 139, 9, 251, 1, // Opcode: CEQI_W +/* 5701 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5716 +/* 5706 */ MCD_OPC_CheckPredicate, 30, 123, 44, 0, // Skip to: 17098 +/* 5711 */ MCD_OPC_Decode, 137, 9, 252, 1, // Opcode: CEQI_D +/* 5716 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 5731 +/* 5721 */ MCD_OPC_CheckPredicate, 30, 108, 44, 0, // Skip to: 17098 +/* 5726 */ MCD_OPC_Decode, 177, 9, 249, 1, // Opcode: CLTI_S_B +/* 5731 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 5746 +/* 5736 */ MCD_OPC_CheckPredicate, 30, 93, 44, 0, // Skip to: 17098 +/* 5741 */ MCD_OPC_Decode, 179, 9, 250, 1, // Opcode: CLTI_S_H +/* 5746 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 5761 +/* 5751 */ MCD_OPC_CheckPredicate, 30, 78, 44, 0, // Skip to: 17098 +/* 5756 */ MCD_OPC_Decode, 180, 9, 251, 1, // Opcode: CLTI_S_W +/* 5761 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 5776 +/* 5766 */ MCD_OPC_CheckPredicate, 30, 63, 44, 0, // Skip to: 17098 +/* 5771 */ MCD_OPC_Decode, 178, 9, 252, 1, // Opcode: CLTI_S_D +/* 5776 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 5791 +/* 5781 */ MCD_OPC_CheckPredicate, 30, 48, 44, 0, // Skip to: 17098 +/* 5786 */ MCD_OPC_Decode, 181, 9, 249, 1, // Opcode: CLTI_U_B +/* 5791 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5806 +/* 5796 */ MCD_OPC_CheckPredicate, 30, 33, 44, 0, // Skip to: 17098 +/* 5801 */ MCD_OPC_Decode, 183, 9, 250, 1, // Opcode: CLTI_U_H +/* 5806 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 5821 +/* 5811 */ MCD_OPC_CheckPredicate, 30, 18, 44, 0, // Skip to: 17098 +/* 5816 */ MCD_OPC_Decode, 184, 9, 251, 1, // Opcode: CLTI_U_W +/* 5821 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5836 +/* 5826 */ MCD_OPC_CheckPredicate, 30, 3, 44, 0, // Skip to: 17098 +/* 5831 */ MCD_OPC_Decode, 182, 9, 252, 1, // Opcode: CLTI_U_D +/* 5836 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 5851 +/* 5841 */ MCD_OPC_CheckPredicate, 30, 244, 43, 0, // Skip to: 17098 +/* 5846 */ MCD_OPC_Decode, 156, 9, 249, 1, // Opcode: CLEI_S_B +/* 5851 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 5866 +/* 5856 */ MCD_OPC_CheckPredicate, 30, 229, 43, 0, // Skip to: 17098 +/* 5861 */ MCD_OPC_Decode, 158, 9, 250, 1, // Opcode: CLEI_S_H +/* 5866 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 5881 +/* 5871 */ MCD_OPC_CheckPredicate, 30, 214, 43, 0, // Skip to: 17098 +/* 5876 */ MCD_OPC_Decode, 159, 9, 251, 1, // Opcode: CLEI_S_W +/* 5881 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 5896 +/* 5886 */ MCD_OPC_CheckPredicate, 30, 199, 43, 0, // Skip to: 17098 +/* 5891 */ MCD_OPC_Decode, 157, 9, 252, 1, // Opcode: CLEI_S_D +/* 5896 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 5911 +/* 5901 */ MCD_OPC_CheckPredicate, 30, 184, 43, 0, // Skip to: 17098 +/* 5906 */ MCD_OPC_Decode, 160, 9, 249, 1, // Opcode: CLEI_U_B +/* 5911 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 5926 +/* 5916 */ MCD_OPC_CheckPredicate, 30, 169, 43, 0, // Skip to: 17098 +/* 5921 */ MCD_OPC_Decode, 162, 9, 250, 1, // Opcode: CLEI_U_H +/* 5926 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 5941 +/* 5931 */ MCD_OPC_CheckPredicate, 30, 154, 43, 0, // Skip to: 17098 +/* 5936 */ MCD_OPC_Decode, 163, 9, 251, 1, // Opcode: CLEI_U_W +/* 5941 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 5956 +/* 5946 */ MCD_OPC_CheckPredicate, 30, 139, 43, 0, // Skip to: 17098 +/* 5951 */ MCD_OPC_Decode, 161, 9, 252, 1, // Opcode: CLEI_U_D +/* 5956 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 5971 +/* 5961 */ MCD_OPC_CheckPredicate, 30, 124, 43, 0, // Skip to: 17098 +/* 5966 */ MCD_OPC_Decode, 189, 15, 253, 1, // Opcode: LDI_B +/* 5971 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 5986 +/* 5976 */ MCD_OPC_CheckPredicate, 30, 109, 43, 0, // Skip to: 17098 +/* 5981 */ MCD_OPC_Decode, 191, 15, 254, 1, // Opcode: LDI_H +/* 5986 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 6001 +/* 5991 */ MCD_OPC_CheckPredicate, 30, 94, 43, 0, // Skip to: 17098 +/* 5996 */ MCD_OPC_Decode, 192, 15, 255, 1, // Opcode: LDI_W +/* 6001 */ MCD_OPC_FilterValue, 27, 84, 43, 0, // Skip to: 17098 +/* 6006 */ MCD_OPC_CheckPredicate, 30, 79, 43, 0, // Skip to: 17098 +/* 6011 */ MCD_OPC_Decode, 190, 15, 128, 2, // Opcode: LDI_D +/* 6016 */ MCD_OPC_FilterValue, 9, 155, 2, 0, // Skip to: 6688 +/* 6021 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 6024 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6039 +/* 6029 */ MCD_OPC_CheckPredicate, 30, 56, 43, 0, // Skip to: 17098 +/* 6034 */ MCD_OPC_Decode, 226, 21, 129, 2, // Opcode: SLLI_D +/* 6039 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 6107 +/* 6044 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6047 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6062 +/* 6052 */ MCD_OPC_CheckPredicate, 30, 33, 43, 0, // Skip to: 17098 +/* 6057 */ MCD_OPC_Decode, 228, 21, 251, 1, // Opcode: SLLI_W +/* 6062 */ MCD_OPC_FilterValue, 1, 23, 43, 0, // Skip to: 17098 +/* 6067 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6070 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6085 +/* 6075 */ MCD_OPC_CheckPredicate, 30, 10, 43, 0, // Skip to: 17098 +/* 6080 */ MCD_OPC_Decode, 227, 21, 130, 2, // Opcode: SLLI_H +/* 6085 */ MCD_OPC_FilterValue, 1, 0, 43, 0, // Skip to: 17098 +/* 6090 */ MCD_OPC_CheckPredicate, 30, 251, 42, 0, // Skip to: 17098 +/* 6095 */ MCD_OPC_CheckField, 19, 1, 0, 244, 42, 0, // Skip to: 17098 +/* 6102 */ MCD_OPC_Decode, 225, 21, 131, 2, // Opcode: SLLI_B +/* 6107 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6122 +/* 6112 */ MCD_OPC_CheckPredicate, 30, 229, 42, 0, // Skip to: 17098 +/* 6117 */ MCD_OPC_Decode, 140, 22, 129, 2, // Opcode: SRAI_D +/* 6122 */ MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 6190 +/* 6127 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6130 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6145 +/* 6135 */ MCD_OPC_CheckPredicate, 30, 206, 42, 0, // Skip to: 17098 +/* 6140 */ MCD_OPC_Decode, 142, 22, 251, 1, // Opcode: SRAI_W +/* 6145 */ MCD_OPC_FilterValue, 1, 196, 42, 0, // Skip to: 17098 +/* 6150 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6153 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6168 +/* 6158 */ MCD_OPC_CheckPredicate, 30, 183, 42, 0, // Skip to: 17098 +/* 6163 */ MCD_OPC_Decode, 141, 22, 130, 2, // Opcode: SRAI_H +/* 6168 */ MCD_OPC_FilterValue, 1, 173, 42, 0, // Skip to: 17098 +/* 6173 */ MCD_OPC_CheckPredicate, 30, 168, 42, 0, // Skip to: 17098 +/* 6178 */ MCD_OPC_CheckField, 19, 1, 0, 161, 42, 0, // Skip to: 17098 +/* 6185 */ MCD_OPC_Decode, 139, 22, 131, 2, // Opcode: SRAI_B +/* 6190 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 6205 +/* 6195 */ MCD_OPC_CheckPredicate, 30, 146, 42, 0, // Skip to: 17098 +/* 6200 */ MCD_OPC_Decode, 165, 22, 129, 2, // Opcode: SRLI_D +/* 6205 */ MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 6273 +/* 6210 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6213 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6228 +/* 6218 */ MCD_OPC_CheckPredicate, 30, 123, 42, 0, // Skip to: 17098 +/* 6223 */ MCD_OPC_Decode, 167, 22, 251, 1, // Opcode: SRLI_W +/* 6228 */ MCD_OPC_FilterValue, 1, 113, 42, 0, // Skip to: 17098 +/* 6233 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6236 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6251 +/* 6241 */ MCD_OPC_CheckPredicate, 30, 100, 42, 0, // Skip to: 17098 +/* 6246 */ MCD_OPC_Decode, 166, 22, 130, 2, // Opcode: SRLI_H +/* 6251 */ MCD_OPC_FilterValue, 1, 90, 42, 0, // Skip to: 17098 +/* 6256 */ MCD_OPC_CheckPredicate, 30, 85, 42, 0, // Skip to: 17098 +/* 6261 */ MCD_OPC_CheckField, 19, 1, 0, 78, 42, 0, // Skip to: 17098 +/* 6268 */ MCD_OPC_Decode, 164, 22, 131, 2, // Opcode: SRLI_B +/* 6273 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 6288 +/* 6278 */ MCD_OPC_CheckPredicate, 30, 63, 42, 0, // Skip to: 17098 +/* 6283 */ MCD_OPC_Decode, 179, 7, 129, 2, // Opcode: BCLRI_D +/* 6288 */ MCD_OPC_FilterValue, 7, 63, 0, 0, // Skip to: 6356 +/* 6293 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6296 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6311 +/* 6301 */ MCD_OPC_CheckPredicate, 30, 40, 42, 0, // Skip to: 17098 +/* 6306 */ MCD_OPC_Decode, 181, 7, 251, 1, // Opcode: BCLRI_W +/* 6311 */ MCD_OPC_FilterValue, 1, 30, 42, 0, // Skip to: 17098 +/* 6316 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6319 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6334 +/* 6324 */ MCD_OPC_CheckPredicate, 30, 17, 42, 0, // Skip to: 17098 +/* 6329 */ MCD_OPC_Decode, 180, 7, 130, 2, // Opcode: BCLRI_H +/* 6334 */ MCD_OPC_FilterValue, 1, 7, 42, 0, // Skip to: 17098 +/* 6339 */ MCD_OPC_CheckPredicate, 30, 2, 42, 0, // Skip to: 17098 +/* 6344 */ MCD_OPC_CheckField, 19, 1, 0, 251, 41, 0, // Skip to: 17098 +/* 6351 */ MCD_OPC_Decode, 178, 7, 131, 2, // Opcode: BCLRI_B +/* 6356 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 6371 +/* 6361 */ MCD_OPC_CheckPredicate, 30, 236, 41, 0, // Skip to: 17098 +/* 6366 */ MCD_OPC_Decode, 222, 8, 129, 2, // Opcode: BSETI_D +/* 6371 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 6439 +/* 6376 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6379 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6394 +/* 6384 */ MCD_OPC_CheckPredicate, 30, 213, 41, 0, // Skip to: 17098 +/* 6389 */ MCD_OPC_Decode, 224, 8, 251, 1, // Opcode: BSETI_W +/* 6394 */ MCD_OPC_FilterValue, 1, 203, 41, 0, // Skip to: 17098 +/* 6399 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6402 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6417 +/* 6407 */ MCD_OPC_CheckPredicate, 30, 190, 41, 0, // Skip to: 17098 +/* 6412 */ MCD_OPC_Decode, 223, 8, 130, 2, // Opcode: BSETI_H +/* 6417 */ MCD_OPC_FilterValue, 1, 180, 41, 0, // Skip to: 17098 +/* 6422 */ MCD_OPC_CheckPredicate, 30, 175, 41, 0, // Skip to: 17098 +/* 6427 */ MCD_OPC_CheckField, 19, 1, 0, 168, 41, 0, // Skip to: 17098 +/* 6434 */ MCD_OPC_Decode, 221, 8, 131, 2, // Opcode: BSETI_B +/* 6439 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 6454 +/* 6444 */ MCD_OPC_CheckPredicate, 30, 153, 41, 0, // Skip to: 17098 +/* 6449 */ MCD_OPC_Decode, 179, 8, 129, 2, // Opcode: BNEGI_D +/* 6454 */ MCD_OPC_FilterValue, 11, 63, 0, 0, // Skip to: 6522 +/* 6459 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6462 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6477 +/* 6467 */ MCD_OPC_CheckPredicate, 30, 130, 41, 0, // Skip to: 17098 +/* 6472 */ MCD_OPC_Decode, 181, 8, 251, 1, // Opcode: BNEGI_W +/* 6477 */ MCD_OPC_FilterValue, 1, 120, 41, 0, // Skip to: 17098 +/* 6482 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6485 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6500 +/* 6490 */ MCD_OPC_CheckPredicate, 30, 107, 41, 0, // Skip to: 17098 +/* 6495 */ MCD_OPC_Decode, 180, 8, 130, 2, // Opcode: BNEGI_H +/* 6500 */ MCD_OPC_FilterValue, 1, 97, 41, 0, // Skip to: 17098 +/* 6505 */ MCD_OPC_CheckPredicate, 30, 92, 41, 0, // Skip to: 17098 +/* 6510 */ MCD_OPC_CheckField, 19, 1, 0, 85, 41, 0, // Skip to: 17098 +/* 6517 */ MCD_OPC_Decode, 178, 8, 131, 2, // Opcode: BNEGI_B +/* 6522 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 6537 +/* 6527 */ MCD_OPC_CheckPredicate, 30, 70, 41, 0, // Skip to: 17098 +/* 6532 */ MCD_OPC_Decode, 242, 7, 132, 2, // Opcode: BINSLI_D +/* 6537 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 6605 +/* 6542 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6545 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6560 +/* 6550 */ MCD_OPC_CheckPredicate, 30, 47, 41, 0, // Skip to: 17098 +/* 6555 */ MCD_OPC_Decode, 244, 7, 133, 2, // Opcode: BINSLI_W +/* 6560 */ MCD_OPC_FilterValue, 1, 37, 41, 0, // Skip to: 17098 +/* 6565 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6568 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6583 +/* 6573 */ MCD_OPC_CheckPredicate, 30, 24, 41, 0, // Skip to: 17098 +/* 6578 */ MCD_OPC_Decode, 243, 7, 134, 2, // Opcode: BINSLI_H +/* 6583 */ MCD_OPC_FilterValue, 1, 14, 41, 0, // Skip to: 17098 +/* 6588 */ MCD_OPC_CheckPredicate, 30, 9, 41, 0, // Skip to: 17098 +/* 6593 */ MCD_OPC_CheckField, 19, 1, 0, 2, 41, 0, // Skip to: 17098 +/* 6600 */ MCD_OPC_Decode, 241, 7, 135, 2, // Opcode: BINSLI_B +/* 6605 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 6620 +/* 6610 */ MCD_OPC_CheckPredicate, 30, 243, 40, 0, // Skip to: 17098 +/* 6615 */ MCD_OPC_Decode, 250, 7, 132, 2, // Opcode: BINSRI_D +/* 6620 */ MCD_OPC_FilterValue, 15, 233, 40, 0, // Skip to: 17098 +/* 6625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6628 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6643 +/* 6633 */ MCD_OPC_CheckPredicate, 30, 220, 40, 0, // Skip to: 17098 +/* 6638 */ MCD_OPC_Decode, 252, 7, 133, 2, // Opcode: BINSRI_W +/* 6643 */ MCD_OPC_FilterValue, 1, 210, 40, 0, // Skip to: 17098 +/* 6648 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6651 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6666 +/* 6656 */ MCD_OPC_CheckPredicate, 30, 197, 40, 0, // Skip to: 17098 +/* 6661 */ MCD_OPC_Decode, 251, 7, 134, 2, // Opcode: BINSRI_H +/* 6666 */ MCD_OPC_FilterValue, 1, 187, 40, 0, // Skip to: 17098 +/* 6671 */ MCD_OPC_CheckPredicate, 30, 182, 40, 0, // Skip to: 17098 +/* 6676 */ MCD_OPC_CheckField, 19, 1, 0, 175, 40, 0, // Skip to: 17098 +/* 6683 */ MCD_OPC_Decode, 249, 7, 135, 2, // Opcode: BINSRI_B +/* 6688 */ MCD_OPC_FilterValue, 10, 79, 1, 0, // Skip to: 7028 +/* 6693 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 6696 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6711 +/* 6701 */ MCD_OPC_CheckPredicate, 30, 152, 40, 0, // Skip to: 17098 +/* 6706 */ MCD_OPC_Decode, 184, 20, 129, 2, // Opcode: SAT_S_D +/* 6711 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 6779 +/* 6716 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6719 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6734 +/* 6724 */ MCD_OPC_CheckPredicate, 30, 129, 40, 0, // Skip to: 17098 +/* 6729 */ MCD_OPC_Decode, 186, 20, 251, 1, // Opcode: SAT_S_W +/* 6734 */ MCD_OPC_FilterValue, 1, 119, 40, 0, // Skip to: 17098 +/* 6739 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6742 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6757 +/* 6747 */ MCD_OPC_CheckPredicate, 30, 106, 40, 0, // Skip to: 17098 +/* 6752 */ MCD_OPC_Decode, 185, 20, 130, 2, // Opcode: SAT_S_H +/* 6757 */ MCD_OPC_FilterValue, 1, 96, 40, 0, // Skip to: 17098 +/* 6762 */ MCD_OPC_CheckPredicate, 30, 91, 40, 0, // Skip to: 17098 +/* 6767 */ MCD_OPC_CheckField, 19, 1, 0, 84, 40, 0, // Skip to: 17098 +/* 6774 */ MCD_OPC_Decode, 183, 20, 131, 2, // Opcode: SAT_S_B +/* 6779 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6794 +/* 6784 */ MCD_OPC_CheckPredicate, 30, 69, 40, 0, // Skip to: 17098 +/* 6789 */ MCD_OPC_Decode, 188, 20, 129, 2, // Opcode: SAT_U_D +/* 6794 */ MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 6862 +/* 6799 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6802 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6817 +/* 6807 */ MCD_OPC_CheckPredicate, 30, 46, 40, 0, // Skip to: 17098 +/* 6812 */ MCD_OPC_Decode, 190, 20, 251, 1, // Opcode: SAT_U_W +/* 6817 */ MCD_OPC_FilterValue, 1, 36, 40, 0, // Skip to: 17098 +/* 6822 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6825 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6840 +/* 6830 */ MCD_OPC_CheckPredicate, 30, 23, 40, 0, // Skip to: 17098 +/* 6835 */ MCD_OPC_Decode, 189, 20, 130, 2, // Opcode: SAT_U_H +/* 6840 */ MCD_OPC_FilterValue, 1, 13, 40, 0, // Skip to: 17098 +/* 6845 */ MCD_OPC_CheckPredicate, 30, 8, 40, 0, // Skip to: 17098 +/* 6850 */ MCD_OPC_CheckField, 19, 1, 0, 1, 40, 0, // Skip to: 17098 +/* 6857 */ MCD_OPC_Decode, 187, 20, 131, 2, // Opcode: SAT_U_B +/* 6862 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 6877 +/* 6867 */ MCD_OPC_CheckPredicate, 30, 242, 39, 0, // Skip to: 17098 +/* 6872 */ MCD_OPC_Decode, 144, 22, 129, 2, // Opcode: SRARI_D +/* 6877 */ MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 6945 +/* 6882 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6885 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6900 +/* 6890 */ MCD_OPC_CheckPredicate, 30, 219, 39, 0, // Skip to: 17098 +/* 6895 */ MCD_OPC_Decode, 146, 22, 251, 1, // Opcode: SRARI_W +/* 6900 */ MCD_OPC_FilterValue, 1, 209, 39, 0, // Skip to: 17098 +/* 6905 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6908 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6923 +/* 6913 */ MCD_OPC_CheckPredicate, 30, 196, 39, 0, // Skip to: 17098 +/* 6918 */ MCD_OPC_Decode, 145, 22, 130, 2, // Opcode: SRARI_H +/* 6923 */ MCD_OPC_FilterValue, 1, 186, 39, 0, // Skip to: 17098 +/* 6928 */ MCD_OPC_CheckPredicate, 30, 181, 39, 0, // Skip to: 17098 +/* 6933 */ MCD_OPC_CheckField, 19, 1, 0, 174, 39, 0, // Skip to: 17098 +/* 6940 */ MCD_OPC_Decode, 143, 22, 131, 2, // Opcode: SRARI_B +/* 6945 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 6960 +/* 6950 */ MCD_OPC_CheckPredicate, 30, 159, 39, 0, // Skip to: 17098 +/* 6955 */ MCD_OPC_Decode, 169, 22, 129, 2, // Opcode: SRLRI_D +/* 6960 */ MCD_OPC_FilterValue, 7, 149, 39, 0, // Skip to: 17098 +/* 6965 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6968 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6983 +/* 6973 */ MCD_OPC_CheckPredicate, 30, 136, 39, 0, // Skip to: 17098 +/* 6978 */ MCD_OPC_Decode, 171, 22, 251, 1, // Opcode: SRLRI_W +/* 6983 */ MCD_OPC_FilterValue, 1, 126, 39, 0, // Skip to: 17098 +/* 6988 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6991 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7006 +/* 6996 */ MCD_OPC_CheckPredicate, 30, 113, 39, 0, // Skip to: 17098 +/* 7001 */ MCD_OPC_Decode, 170, 22, 130, 2, // Opcode: SRLRI_H +/* 7006 */ MCD_OPC_FilterValue, 1, 103, 39, 0, // Skip to: 17098 +/* 7011 */ MCD_OPC_CheckPredicate, 30, 98, 39, 0, // Skip to: 17098 +/* 7016 */ MCD_OPC_CheckField, 19, 1, 0, 91, 39, 0, // Skip to: 17098 +/* 7023 */ MCD_OPC_Decode, 168, 22, 131, 2, // Opcode: SRLRI_B +/* 7028 */ MCD_OPC_FilterValue, 13, 227, 1, 0, // Skip to: 7516 +/* 7033 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 7036 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7051 +/* 7041 */ MCD_OPC_CheckPredicate, 30, 68, 39, 0, // Skip to: 17098 +/* 7046 */ MCD_OPC_Decode, 232, 21, 136, 2, // Opcode: SLL_B +/* 7051 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7066 +/* 7056 */ MCD_OPC_CheckPredicate, 30, 53, 39, 0, // Skip to: 17098 +/* 7061 */ MCD_OPC_Decode, 234, 21, 137, 2, // Opcode: SLL_H +/* 7066 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7081 +/* 7071 */ MCD_OPC_CheckPredicate, 30, 38, 39, 0, // Skip to: 17098 +/* 7076 */ MCD_OPC_Decode, 238, 21, 138, 2, // Opcode: SLL_W +/* 7081 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7096 +/* 7086 */ MCD_OPC_CheckPredicate, 30, 23, 39, 0, // Skip to: 17098 +/* 7091 */ MCD_OPC_Decode, 233, 21, 139, 2, // Opcode: SLL_D +/* 7096 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 7111 +/* 7101 */ MCD_OPC_CheckPredicate, 30, 8, 39, 0, // Skip to: 17098 +/* 7106 */ MCD_OPC_Decode, 154, 22, 136, 2, // Opcode: SRA_B +/* 7111 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 7126 +/* 7116 */ MCD_OPC_CheckPredicate, 30, 249, 38, 0, // Skip to: 17098 +/* 7121 */ MCD_OPC_Decode, 156, 22, 137, 2, // Opcode: SRA_H +/* 7126 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 7141 +/* 7131 */ MCD_OPC_CheckPredicate, 30, 234, 38, 0, // Skip to: 17098 +/* 7136 */ MCD_OPC_Decode, 159, 22, 138, 2, // Opcode: SRA_W +/* 7141 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 7156 +/* 7146 */ MCD_OPC_CheckPredicate, 30, 219, 38, 0, // Skip to: 17098 +/* 7151 */ MCD_OPC_Decode, 155, 22, 139, 2, // Opcode: SRA_D +/* 7156 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 7171 +/* 7161 */ MCD_OPC_CheckPredicate, 30, 204, 38, 0, // Skip to: 17098 +/* 7166 */ MCD_OPC_Decode, 179, 22, 136, 2, // Opcode: SRL_B +/* 7171 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 7186 +/* 7176 */ MCD_OPC_CheckPredicate, 30, 189, 38, 0, // Skip to: 17098 +/* 7181 */ MCD_OPC_Decode, 181, 22, 137, 2, // Opcode: SRL_H +/* 7186 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 7201 +/* 7191 */ MCD_OPC_CheckPredicate, 30, 174, 38, 0, // Skip to: 17098 +/* 7196 */ MCD_OPC_Decode, 184, 22, 138, 2, // Opcode: SRL_W +/* 7201 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 7216 +/* 7206 */ MCD_OPC_CheckPredicate, 30, 159, 38, 0, // Skip to: 17098 +/* 7211 */ MCD_OPC_Decode, 180, 22, 139, 2, // Opcode: SRL_D +/* 7216 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 7231 +/* 7221 */ MCD_OPC_CheckPredicate, 30, 144, 38, 0, // Skip to: 17098 +/* 7226 */ MCD_OPC_Decode, 182, 7, 136, 2, // Opcode: BCLR_B +/* 7231 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 7246 +/* 7236 */ MCD_OPC_CheckPredicate, 30, 129, 38, 0, // Skip to: 17098 +/* 7241 */ MCD_OPC_Decode, 184, 7, 137, 2, // Opcode: BCLR_H +/* 7246 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 7261 +/* 7251 */ MCD_OPC_CheckPredicate, 30, 114, 38, 0, // Skip to: 17098 +/* 7256 */ MCD_OPC_Decode, 185, 7, 138, 2, // Opcode: BCLR_W +/* 7261 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 7276 +/* 7266 */ MCD_OPC_CheckPredicate, 30, 99, 38, 0, // Skip to: 17098 +/* 7271 */ MCD_OPC_Decode, 183, 7, 139, 2, // Opcode: BCLR_D +/* 7276 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 7291 +/* 7281 */ MCD_OPC_CheckPredicate, 30, 84, 38, 0, // Skip to: 17098 +/* 7286 */ MCD_OPC_Decode, 225, 8, 136, 2, // Opcode: BSET_B +/* 7291 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 7306 +/* 7296 */ MCD_OPC_CheckPredicate, 30, 69, 38, 0, // Skip to: 17098 +/* 7301 */ MCD_OPC_Decode, 227, 8, 137, 2, // Opcode: BSET_H +/* 7306 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 7321 +/* 7311 */ MCD_OPC_CheckPredicate, 30, 54, 38, 0, // Skip to: 17098 +/* 7316 */ MCD_OPC_Decode, 228, 8, 138, 2, // Opcode: BSET_W +/* 7321 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 7336 +/* 7326 */ MCD_OPC_CheckPredicate, 30, 39, 38, 0, // Skip to: 17098 +/* 7331 */ MCD_OPC_Decode, 226, 8, 139, 2, // Opcode: BSET_D +/* 7336 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 7351 +/* 7341 */ MCD_OPC_CheckPredicate, 30, 24, 38, 0, // Skip to: 17098 +/* 7346 */ MCD_OPC_Decode, 182, 8, 136, 2, // Opcode: BNEG_B +/* 7351 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 7366 +/* 7356 */ MCD_OPC_CheckPredicate, 30, 9, 38, 0, // Skip to: 17098 +/* 7361 */ MCD_OPC_Decode, 184, 8, 137, 2, // Opcode: BNEG_H +/* 7366 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 7381 +/* 7371 */ MCD_OPC_CheckPredicate, 30, 250, 37, 0, // Skip to: 17098 +/* 7376 */ MCD_OPC_Decode, 185, 8, 138, 2, // Opcode: BNEG_W +/* 7381 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 7396 +/* 7386 */ MCD_OPC_CheckPredicate, 30, 235, 37, 0, // Skip to: 17098 +/* 7391 */ MCD_OPC_Decode, 183, 8, 139, 2, // Opcode: BNEG_D +/* 7396 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 7411 +/* 7401 */ MCD_OPC_CheckPredicate, 30, 220, 37, 0, // Skip to: 17098 +/* 7406 */ MCD_OPC_Decode, 245, 7, 140, 2, // Opcode: BINSL_B +/* 7411 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 7426 +/* 7416 */ MCD_OPC_CheckPredicate, 30, 205, 37, 0, // Skip to: 17098 +/* 7421 */ MCD_OPC_Decode, 247, 7, 141, 2, // Opcode: BINSL_H +/* 7426 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 7441 +/* 7431 */ MCD_OPC_CheckPredicate, 30, 190, 37, 0, // Skip to: 17098 +/* 7436 */ MCD_OPC_Decode, 248, 7, 142, 2, // Opcode: BINSL_W +/* 7441 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 7456 +/* 7446 */ MCD_OPC_CheckPredicate, 30, 175, 37, 0, // Skip to: 17098 +/* 7451 */ MCD_OPC_Decode, 246, 7, 143, 2, // Opcode: BINSL_D +/* 7456 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 7471 +/* 7461 */ MCD_OPC_CheckPredicate, 30, 160, 37, 0, // Skip to: 17098 +/* 7466 */ MCD_OPC_Decode, 253, 7, 140, 2, // Opcode: BINSR_B +/* 7471 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 7486 +/* 7476 */ MCD_OPC_CheckPredicate, 30, 145, 37, 0, // Skip to: 17098 +/* 7481 */ MCD_OPC_Decode, 255, 7, 141, 2, // Opcode: BINSR_H +/* 7486 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 7501 +/* 7491 */ MCD_OPC_CheckPredicate, 30, 130, 37, 0, // Skip to: 17098 +/* 7496 */ MCD_OPC_Decode, 128, 8, 142, 2, // Opcode: BINSR_W +/* 7501 */ MCD_OPC_FilterValue, 31, 120, 37, 0, // Skip to: 17098 +/* 7506 */ MCD_OPC_CheckPredicate, 30, 115, 37, 0, // Skip to: 17098 +/* 7511 */ MCD_OPC_Decode, 254, 7, 143, 2, // Opcode: BINSR_D +/* 7516 */ MCD_OPC_FilterValue, 14, 227, 1, 0, // Skip to: 8004 +/* 7521 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 7524 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7539 +/* 7529 */ MCD_OPC_CheckPredicate, 30, 92, 37, 0, // Skip to: 17098 +/* 7534 */ MCD_OPC_Decode, 189, 6, 136, 2, // Opcode: ADDV_B +/* 7539 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7554 +/* 7544 */ MCD_OPC_CheckPredicate, 30, 77, 37, 0, // Skip to: 17098 +/* 7549 */ MCD_OPC_Decode, 191, 6, 137, 2, // Opcode: ADDV_H +/* 7554 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7569 +/* 7559 */ MCD_OPC_CheckPredicate, 30, 62, 37, 0, // Skip to: 17098 +/* 7564 */ MCD_OPC_Decode, 192, 6, 138, 2, // Opcode: ADDV_W +/* 7569 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7584 +/* 7574 */ MCD_OPC_CheckPredicate, 30, 47, 37, 0, // Skip to: 17098 +/* 7579 */ MCD_OPC_Decode, 190, 6, 139, 2, // Opcode: ADDV_D +/* 7584 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 7599 +/* 7589 */ MCD_OPC_CheckPredicate, 30, 32, 37, 0, // Skip to: 17098 +/* 7594 */ MCD_OPC_Decode, 242, 22, 136, 2, // Opcode: SUBV_B +/* 7599 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 7614 +/* 7604 */ MCD_OPC_CheckPredicate, 30, 17, 37, 0, // Skip to: 17098 +/* 7609 */ MCD_OPC_Decode, 244, 22, 137, 2, // Opcode: SUBV_H +/* 7614 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 7629 +/* 7619 */ MCD_OPC_CheckPredicate, 30, 2, 37, 0, // Skip to: 17098 +/* 7624 */ MCD_OPC_Decode, 245, 22, 138, 2, // Opcode: SUBV_W +/* 7629 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 7644 +/* 7634 */ MCD_OPC_CheckPredicate, 30, 243, 36, 0, // Skip to: 17098 +/* 7639 */ MCD_OPC_Decode, 243, 22, 139, 2, // Opcode: SUBV_D +/* 7644 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 7659 +/* 7649 */ MCD_OPC_CheckPredicate, 30, 228, 36, 0, // Skip to: 17098 +/* 7654 */ MCD_OPC_Decode, 247, 16, 136, 2, // Opcode: MAX_S_B +/* 7659 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 7674 +/* 7664 */ MCD_OPC_CheckPredicate, 30, 213, 36, 0, // Skip to: 17098 +/* 7669 */ MCD_OPC_Decode, 249, 16, 137, 2, // Opcode: MAX_S_H +/* 7674 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 7689 +/* 7679 */ MCD_OPC_CheckPredicate, 30, 198, 36, 0, // Skip to: 17098 +/* 7684 */ MCD_OPC_Decode, 251, 16, 138, 2, // Opcode: MAX_S_W +/* 7689 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 7704 +/* 7694 */ MCD_OPC_CheckPredicate, 30, 183, 36, 0, // Skip to: 17098 +/* 7699 */ MCD_OPC_Decode, 248, 16, 139, 2, // Opcode: MAX_S_D +/* 7704 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 7719 +/* 7709 */ MCD_OPC_CheckPredicate, 30, 168, 36, 0, // Skip to: 17098 +/* 7714 */ MCD_OPC_Decode, 252, 16, 136, 2, // Opcode: MAX_U_B +/* 7719 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 7734 +/* 7724 */ MCD_OPC_CheckPredicate, 30, 153, 36, 0, // Skip to: 17098 +/* 7729 */ MCD_OPC_Decode, 254, 16, 137, 2, // Opcode: MAX_U_H +/* 7734 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 7749 +/* 7739 */ MCD_OPC_CheckPredicate, 30, 138, 36, 0, // Skip to: 17098 +/* 7744 */ MCD_OPC_Decode, 255, 16, 138, 2, // Opcode: MAX_U_W +/* 7749 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 7764 +/* 7754 */ MCD_OPC_CheckPredicate, 30, 123, 36, 0, // Skip to: 17098 +/* 7759 */ MCD_OPC_Decode, 253, 16, 139, 2, // Opcode: MAX_U_D +/* 7764 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 7779 +/* 7769 */ MCD_OPC_CheckPredicate, 30, 108, 36, 0, // Skip to: 17098 +/* 7774 */ MCD_OPC_Decode, 183, 17, 136, 2, // Opcode: MIN_S_B +/* 7779 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 7794 +/* 7784 */ MCD_OPC_CheckPredicate, 30, 93, 36, 0, // Skip to: 17098 +/* 7789 */ MCD_OPC_Decode, 185, 17, 137, 2, // Opcode: MIN_S_H +/* 7794 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 7809 +/* 7799 */ MCD_OPC_CheckPredicate, 30, 78, 36, 0, // Skip to: 17098 +/* 7804 */ MCD_OPC_Decode, 187, 17, 138, 2, // Opcode: MIN_S_W +/* 7809 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 7824 +/* 7814 */ MCD_OPC_CheckPredicate, 30, 63, 36, 0, // Skip to: 17098 +/* 7819 */ MCD_OPC_Decode, 184, 17, 139, 2, // Opcode: MIN_S_D +/* 7824 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 7839 +/* 7829 */ MCD_OPC_CheckPredicate, 30, 48, 36, 0, // Skip to: 17098 +/* 7834 */ MCD_OPC_Decode, 188, 17, 136, 2, // Opcode: MIN_U_B +/* 7839 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 7854 +/* 7844 */ MCD_OPC_CheckPredicate, 30, 33, 36, 0, // Skip to: 17098 +/* 7849 */ MCD_OPC_Decode, 190, 17, 137, 2, // Opcode: MIN_U_H +/* 7854 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 7869 +/* 7859 */ MCD_OPC_CheckPredicate, 30, 18, 36, 0, // Skip to: 17098 +/* 7864 */ MCD_OPC_Decode, 191, 17, 138, 2, // Opcode: MIN_U_W +/* 7869 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 7884 +/* 7874 */ MCD_OPC_CheckPredicate, 30, 3, 36, 0, // Skip to: 17098 +/* 7879 */ MCD_OPC_Decode, 189, 17, 139, 2, // Opcode: MIN_U_D +/* 7884 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 7899 +/* 7889 */ MCD_OPC_CheckPredicate, 30, 244, 35, 0, // Skip to: 17098 +/* 7894 */ MCD_OPC_Decode, 240, 16, 136, 2, // Opcode: MAX_A_B +/* 7899 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 7914 +/* 7904 */ MCD_OPC_CheckPredicate, 30, 229, 35, 0, // Skip to: 17098 +/* 7909 */ MCD_OPC_Decode, 242, 16, 137, 2, // Opcode: MAX_A_H +/* 7914 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 7929 +/* 7919 */ MCD_OPC_CheckPredicate, 30, 214, 35, 0, // Skip to: 17098 +/* 7924 */ MCD_OPC_Decode, 243, 16, 138, 2, // Opcode: MAX_A_W +/* 7929 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 7944 +/* 7934 */ MCD_OPC_CheckPredicate, 30, 199, 35, 0, // Skip to: 17098 +/* 7939 */ MCD_OPC_Decode, 241, 16, 139, 2, // Opcode: MAX_A_D +/* 7944 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 7959 +/* 7949 */ MCD_OPC_CheckPredicate, 30, 184, 35, 0, // Skip to: 17098 +/* 7954 */ MCD_OPC_Decode, 176, 17, 136, 2, // Opcode: MIN_A_B +/* 7959 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 7974 +/* 7964 */ MCD_OPC_CheckPredicate, 30, 169, 35, 0, // Skip to: 17098 +/* 7969 */ MCD_OPC_Decode, 178, 17, 137, 2, // Opcode: MIN_A_H +/* 7974 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 7989 +/* 7979 */ MCD_OPC_CheckPredicate, 30, 154, 35, 0, // Skip to: 17098 +/* 7984 */ MCD_OPC_Decode, 179, 17, 138, 2, // Opcode: MIN_A_W +/* 7989 */ MCD_OPC_FilterValue, 31, 144, 35, 0, // Skip to: 17098 +/* 7994 */ MCD_OPC_CheckPredicate, 30, 139, 35, 0, // Skip to: 17098 +/* 7999 */ MCD_OPC_Decode, 177, 17, 139, 2, // Opcode: MIN_A_D +/* 8004 */ MCD_OPC_FilterValue, 15, 47, 1, 0, // Skip to: 8312 +/* 8009 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 8012 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8027 +/* 8017 */ MCD_OPC_CheckPredicate, 30, 116, 35, 0, // Skip to: 17098 +/* 8022 */ MCD_OPC_Decode, 140, 9, 136, 2, // Opcode: CEQ_B +/* 8027 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8042 +/* 8032 */ MCD_OPC_CheckPredicate, 30, 101, 35, 0, // Skip to: 17098 +/* 8037 */ MCD_OPC_Decode, 142, 9, 137, 2, // Opcode: CEQ_H +/* 8042 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8057 +/* 8047 */ MCD_OPC_CheckPredicate, 30, 86, 35, 0, // Skip to: 17098 +/* 8052 */ MCD_OPC_Decode, 143, 9, 138, 2, // Opcode: CEQ_W +/* 8057 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8072 +/* 8062 */ MCD_OPC_CheckPredicate, 30, 71, 35, 0, // Skip to: 17098 +/* 8067 */ MCD_OPC_Decode, 141, 9, 139, 2, // Opcode: CEQ_D +/* 8072 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 8087 +/* 8077 */ MCD_OPC_CheckPredicate, 30, 56, 35, 0, // Skip to: 17098 +/* 8082 */ MCD_OPC_Decode, 185, 9, 136, 2, // Opcode: CLT_S_B +/* 8087 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 8102 +/* 8092 */ MCD_OPC_CheckPredicate, 30, 41, 35, 0, // Skip to: 17098 +/* 8097 */ MCD_OPC_Decode, 187, 9, 137, 2, // Opcode: CLT_S_H +/* 8102 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 8117 +/* 8107 */ MCD_OPC_CheckPredicate, 30, 26, 35, 0, // Skip to: 17098 +/* 8112 */ MCD_OPC_Decode, 188, 9, 138, 2, // Opcode: CLT_S_W +/* 8117 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 8132 +/* 8122 */ MCD_OPC_CheckPredicate, 30, 11, 35, 0, // Skip to: 17098 +/* 8127 */ MCD_OPC_Decode, 186, 9, 139, 2, // Opcode: CLT_S_D +/* 8132 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 8147 +/* 8137 */ MCD_OPC_CheckPredicate, 30, 252, 34, 0, // Skip to: 17098 +/* 8142 */ MCD_OPC_Decode, 189, 9, 136, 2, // Opcode: CLT_U_B +/* 8147 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 8162 +/* 8152 */ MCD_OPC_CheckPredicate, 30, 237, 34, 0, // Skip to: 17098 +/* 8157 */ MCD_OPC_Decode, 191, 9, 137, 2, // Opcode: CLT_U_H +/* 8162 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 8177 +/* 8167 */ MCD_OPC_CheckPredicate, 30, 222, 34, 0, // Skip to: 17098 +/* 8172 */ MCD_OPC_Decode, 192, 9, 138, 2, // Opcode: CLT_U_W +/* 8177 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 8192 +/* 8182 */ MCD_OPC_CheckPredicate, 30, 207, 34, 0, // Skip to: 17098 +/* 8187 */ MCD_OPC_Decode, 190, 9, 139, 2, // Opcode: CLT_U_D +/* 8192 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 8207 +/* 8197 */ MCD_OPC_CheckPredicate, 30, 192, 34, 0, // Skip to: 17098 +/* 8202 */ MCD_OPC_Decode, 164, 9, 136, 2, // Opcode: CLE_S_B +/* 8207 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 8222 +/* 8212 */ MCD_OPC_CheckPredicate, 30, 177, 34, 0, // Skip to: 17098 +/* 8217 */ MCD_OPC_Decode, 166, 9, 137, 2, // Opcode: CLE_S_H +/* 8222 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 8237 +/* 8227 */ MCD_OPC_CheckPredicate, 30, 162, 34, 0, // Skip to: 17098 +/* 8232 */ MCD_OPC_Decode, 167, 9, 138, 2, // Opcode: CLE_S_W +/* 8237 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 8252 +/* 8242 */ MCD_OPC_CheckPredicate, 30, 147, 34, 0, // Skip to: 17098 +/* 8247 */ MCD_OPC_Decode, 165, 9, 139, 2, // Opcode: CLE_S_D +/* 8252 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 8267 +/* 8257 */ MCD_OPC_CheckPredicate, 30, 132, 34, 0, // Skip to: 17098 +/* 8262 */ MCD_OPC_Decode, 168, 9, 136, 2, // Opcode: CLE_U_B +/* 8267 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 8282 +/* 8272 */ MCD_OPC_CheckPredicate, 30, 117, 34, 0, // Skip to: 17098 +/* 8277 */ MCD_OPC_Decode, 170, 9, 137, 2, // Opcode: CLE_U_H +/* 8282 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 8297 +/* 8287 */ MCD_OPC_CheckPredicate, 30, 102, 34, 0, // Skip to: 17098 +/* 8292 */ MCD_OPC_Decode, 171, 9, 138, 2, // Opcode: CLE_U_W +/* 8297 */ MCD_OPC_FilterValue, 23, 92, 34, 0, // Skip to: 17098 +/* 8302 */ MCD_OPC_CheckPredicate, 30, 87, 34, 0, // Skip to: 17098 +/* 8307 */ MCD_OPC_Decode, 169, 9, 139, 2, // Opcode: CLE_U_D +/* 8312 */ MCD_OPC_FilterValue, 16, 227, 1, 0, // Skip to: 8800 +/* 8317 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 8320 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8335 +/* 8325 */ MCD_OPC_CheckPredicate, 30, 64, 34, 0, // Skip to: 17098 +/* 8330 */ MCD_OPC_Decode, 195, 6, 136, 2, // Opcode: ADD_A_B +/* 8335 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8350 +/* 8340 */ MCD_OPC_CheckPredicate, 30, 49, 34, 0, // Skip to: 17098 +/* 8345 */ MCD_OPC_Decode, 197, 6, 137, 2, // Opcode: ADD_A_H +/* 8350 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8365 +/* 8355 */ MCD_OPC_CheckPredicate, 30, 34, 34, 0, // Skip to: 17098 +/* 8360 */ MCD_OPC_Decode, 198, 6, 138, 2, // Opcode: ADD_A_W +/* 8365 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8380 +/* 8370 */ MCD_OPC_CheckPredicate, 30, 19, 34, 0, // Skip to: 17098 +/* 8375 */ MCD_OPC_Decode, 196, 6, 139, 2, // Opcode: ADD_A_D +/* 8380 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 8395 +/* 8385 */ MCD_OPC_CheckPredicate, 30, 4, 34, 0, // Skip to: 17098 +/* 8390 */ MCD_OPC_Decode, 158, 6, 136, 2, // Opcode: ADDS_A_B +/* 8395 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 8410 +/* 8400 */ MCD_OPC_CheckPredicate, 30, 245, 33, 0, // Skip to: 17098 +/* 8405 */ MCD_OPC_Decode, 160, 6, 137, 2, // Opcode: ADDS_A_H +/* 8410 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 8425 +/* 8415 */ MCD_OPC_CheckPredicate, 30, 230, 33, 0, // Skip to: 17098 +/* 8420 */ MCD_OPC_Decode, 161, 6, 138, 2, // Opcode: ADDS_A_W +/* 8425 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 8440 +/* 8430 */ MCD_OPC_CheckPredicate, 30, 215, 33, 0, // Skip to: 17098 +/* 8435 */ MCD_OPC_Decode, 159, 6, 139, 2, // Opcode: ADDS_A_D +/* 8440 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 8455 +/* 8445 */ MCD_OPC_CheckPredicate, 30, 200, 33, 0, // Skip to: 17098 +/* 8450 */ MCD_OPC_Decode, 162, 6, 136, 2, // Opcode: ADDS_S_B +/* 8455 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 8470 +/* 8460 */ MCD_OPC_CheckPredicate, 30, 185, 33, 0, // Skip to: 17098 +/* 8465 */ MCD_OPC_Decode, 164, 6, 137, 2, // Opcode: ADDS_S_H +/* 8470 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 8485 +/* 8475 */ MCD_OPC_CheckPredicate, 30, 170, 33, 0, // Skip to: 17098 +/* 8480 */ MCD_OPC_Decode, 165, 6, 138, 2, // Opcode: ADDS_S_W +/* 8485 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 8500 +/* 8490 */ MCD_OPC_CheckPredicate, 30, 155, 33, 0, // Skip to: 17098 +/* 8495 */ MCD_OPC_Decode, 163, 6, 139, 2, // Opcode: ADDS_S_D +/* 8500 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 8515 +/* 8505 */ MCD_OPC_CheckPredicate, 30, 140, 33, 0, // Skip to: 17098 +/* 8510 */ MCD_OPC_Decode, 166, 6, 136, 2, // Opcode: ADDS_U_B +/* 8515 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 8530 +/* 8520 */ MCD_OPC_CheckPredicate, 30, 125, 33, 0, // Skip to: 17098 +/* 8525 */ MCD_OPC_Decode, 168, 6, 137, 2, // Opcode: ADDS_U_H +/* 8530 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 8545 +/* 8535 */ MCD_OPC_CheckPredicate, 30, 110, 33, 0, // Skip to: 17098 +/* 8540 */ MCD_OPC_Decode, 169, 6, 138, 2, // Opcode: ADDS_U_W +/* 8545 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 8560 +/* 8550 */ MCD_OPC_CheckPredicate, 30, 95, 33, 0, // Skip to: 17098 +/* 8555 */ MCD_OPC_Decode, 167, 6, 139, 2, // Opcode: ADDS_U_D +/* 8560 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 8575 +/* 8565 */ MCD_OPC_CheckPredicate, 30, 80, 33, 0, // Skip to: 17098 +/* 8570 */ MCD_OPC_Decode, 128, 7, 136, 2, // Opcode: AVE_S_B +/* 8575 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 8590 +/* 8580 */ MCD_OPC_CheckPredicate, 30, 65, 33, 0, // Skip to: 17098 +/* 8585 */ MCD_OPC_Decode, 130, 7, 137, 2, // Opcode: AVE_S_H +/* 8590 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 8605 +/* 8595 */ MCD_OPC_CheckPredicate, 30, 50, 33, 0, // Skip to: 17098 +/* 8600 */ MCD_OPC_Decode, 131, 7, 138, 2, // Opcode: AVE_S_W +/* 8605 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 8620 +/* 8610 */ MCD_OPC_CheckPredicate, 30, 35, 33, 0, // Skip to: 17098 +/* 8615 */ MCD_OPC_Decode, 129, 7, 139, 2, // Opcode: AVE_S_D +/* 8620 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 8635 +/* 8625 */ MCD_OPC_CheckPredicate, 30, 20, 33, 0, // Skip to: 17098 +/* 8630 */ MCD_OPC_Decode, 132, 7, 136, 2, // Opcode: AVE_U_B +/* 8635 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 8650 +/* 8640 */ MCD_OPC_CheckPredicate, 30, 5, 33, 0, // Skip to: 17098 +/* 8645 */ MCD_OPC_Decode, 134, 7, 137, 2, // Opcode: AVE_U_H +/* 8650 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 8665 +/* 8655 */ MCD_OPC_CheckPredicate, 30, 246, 32, 0, // Skip to: 17098 +/* 8660 */ MCD_OPC_Decode, 135, 7, 138, 2, // Opcode: AVE_U_W +/* 8665 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 8680 +/* 8670 */ MCD_OPC_CheckPredicate, 30, 231, 32, 0, // Skip to: 17098 +/* 8675 */ MCD_OPC_Decode, 133, 7, 139, 2, // Opcode: AVE_U_D +/* 8680 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 8695 +/* 8685 */ MCD_OPC_CheckPredicate, 30, 216, 32, 0, // Skip to: 17098 +/* 8690 */ MCD_OPC_Decode, 248, 6, 136, 2, // Opcode: AVER_S_B +/* 8695 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 8710 +/* 8700 */ MCD_OPC_CheckPredicate, 30, 201, 32, 0, // Skip to: 17098 +/* 8705 */ MCD_OPC_Decode, 250, 6, 137, 2, // Opcode: AVER_S_H +/* 8710 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 8725 +/* 8715 */ MCD_OPC_CheckPredicate, 30, 186, 32, 0, // Skip to: 17098 +/* 8720 */ MCD_OPC_Decode, 251, 6, 138, 2, // Opcode: AVER_S_W +/* 8725 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 8740 +/* 8730 */ MCD_OPC_CheckPredicate, 30, 171, 32, 0, // Skip to: 17098 +/* 8735 */ MCD_OPC_Decode, 249, 6, 139, 2, // Opcode: AVER_S_D +/* 8740 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 8755 +/* 8745 */ MCD_OPC_CheckPredicate, 30, 156, 32, 0, // Skip to: 17098 +/* 8750 */ MCD_OPC_Decode, 252, 6, 136, 2, // Opcode: AVER_U_B +/* 8755 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 8770 +/* 8760 */ MCD_OPC_CheckPredicate, 30, 141, 32, 0, // Skip to: 17098 +/* 8765 */ MCD_OPC_Decode, 254, 6, 137, 2, // Opcode: AVER_U_H +/* 8770 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 8785 +/* 8775 */ MCD_OPC_CheckPredicate, 30, 126, 32, 0, // Skip to: 17098 +/* 8780 */ MCD_OPC_Decode, 255, 6, 138, 2, // Opcode: AVER_U_W +/* 8785 */ MCD_OPC_FilterValue, 31, 116, 32, 0, // Skip to: 17098 +/* 8790 */ MCD_OPC_CheckPredicate, 30, 111, 32, 0, // Skip to: 17098 +/* 8795 */ MCD_OPC_Decode, 253, 6, 139, 2, // Opcode: AVER_U_D +/* 8800 */ MCD_OPC_FilterValue, 17, 107, 1, 0, // Skip to: 9168 +/* 8805 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 8808 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8823 +/* 8813 */ MCD_OPC_CheckPredicate, 30, 88, 32, 0, // Skip to: 17098 +/* 8818 */ MCD_OPC_Decode, 215, 22, 136, 2, // Opcode: SUBS_S_B +/* 8823 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8838 +/* 8828 */ MCD_OPC_CheckPredicate, 30, 73, 32, 0, // Skip to: 17098 +/* 8833 */ MCD_OPC_Decode, 217, 22, 137, 2, // Opcode: SUBS_S_H +/* 8838 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8853 +/* 8843 */ MCD_OPC_CheckPredicate, 30, 58, 32, 0, // Skip to: 17098 +/* 8848 */ MCD_OPC_Decode, 218, 22, 138, 2, // Opcode: SUBS_S_W +/* 8853 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8868 +/* 8858 */ MCD_OPC_CheckPredicate, 30, 43, 32, 0, // Skip to: 17098 +/* 8863 */ MCD_OPC_Decode, 216, 22, 139, 2, // Opcode: SUBS_S_D +/* 8868 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 8883 +/* 8873 */ MCD_OPC_CheckPredicate, 30, 28, 32, 0, // Skip to: 17098 +/* 8878 */ MCD_OPC_Decode, 219, 22, 136, 2, // Opcode: SUBS_U_B +/* 8883 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 8898 +/* 8888 */ MCD_OPC_CheckPredicate, 30, 13, 32, 0, // Skip to: 17098 +/* 8893 */ MCD_OPC_Decode, 221, 22, 137, 2, // Opcode: SUBS_U_H +/* 8898 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 8913 +/* 8903 */ MCD_OPC_CheckPredicate, 30, 254, 31, 0, // Skip to: 17098 +/* 8908 */ MCD_OPC_Decode, 222, 22, 138, 2, // Opcode: SUBS_U_W +/* 8913 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 8928 +/* 8918 */ MCD_OPC_CheckPredicate, 30, 239, 31, 0, // Skip to: 17098 +/* 8923 */ MCD_OPC_Decode, 220, 22, 139, 2, // Opcode: SUBS_U_D +/* 8928 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 8943 +/* 8933 */ MCD_OPC_CheckPredicate, 30, 224, 31, 0, // Skip to: 17098 +/* 8938 */ MCD_OPC_Decode, 207, 22, 136, 2, // Opcode: SUBSUS_U_B +/* 8943 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 8958 +/* 8948 */ MCD_OPC_CheckPredicate, 30, 209, 31, 0, // Skip to: 17098 +/* 8953 */ MCD_OPC_Decode, 209, 22, 137, 2, // Opcode: SUBSUS_U_H +/* 8958 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 8973 +/* 8963 */ MCD_OPC_CheckPredicate, 30, 194, 31, 0, // Skip to: 17098 +/* 8968 */ MCD_OPC_Decode, 210, 22, 138, 2, // Opcode: SUBSUS_U_W +/* 8973 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 8988 +/* 8978 */ MCD_OPC_CheckPredicate, 30, 179, 31, 0, // Skip to: 17098 +/* 8983 */ MCD_OPC_Decode, 208, 22, 139, 2, // Opcode: SUBSUS_U_D +/* 8988 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 9003 +/* 8993 */ MCD_OPC_CheckPredicate, 30, 164, 31, 0, // Skip to: 17098 +/* 8998 */ MCD_OPC_Decode, 211, 22, 136, 2, // Opcode: SUBSUU_S_B +/* 9003 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 9018 +/* 9008 */ MCD_OPC_CheckPredicate, 30, 149, 31, 0, // Skip to: 17098 +/* 9013 */ MCD_OPC_Decode, 213, 22, 137, 2, // Opcode: SUBSUU_S_H +/* 9018 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9033 +/* 9023 */ MCD_OPC_CheckPredicate, 30, 134, 31, 0, // Skip to: 17098 +/* 9028 */ MCD_OPC_Decode, 214, 22, 138, 2, // Opcode: SUBSUU_S_W +/* 9033 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 9048 +/* 9038 */ MCD_OPC_CheckPredicate, 30, 119, 31, 0, // Skip to: 17098 +/* 9043 */ MCD_OPC_Decode, 212, 22, 139, 2, // Opcode: SUBSUU_S_D +/* 9048 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 9063 +/* 9053 */ MCD_OPC_CheckPredicate, 30, 104, 31, 0, // Skip to: 17098 +/* 9058 */ MCD_OPC_Decode, 236, 6, 136, 2, // Opcode: ASUB_S_B +/* 9063 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 9078 +/* 9068 */ MCD_OPC_CheckPredicate, 30, 89, 31, 0, // Skip to: 17098 +/* 9073 */ MCD_OPC_Decode, 238, 6, 137, 2, // Opcode: ASUB_S_H +/* 9078 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 9093 +/* 9083 */ MCD_OPC_CheckPredicate, 30, 74, 31, 0, // Skip to: 17098 +/* 9088 */ MCD_OPC_Decode, 239, 6, 138, 2, // Opcode: ASUB_S_W +/* 9093 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 9108 +/* 9098 */ MCD_OPC_CheckPredicate, 30, 59, 31, 0, // Skip to: 17098 +/* 9103 */ MCD_OPC_Decode, 237, 6, 139, 2, // Opcode: ASUB_S_D +/* 9108 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 9123 +/* 9113 */ MCD_OPC_CheckPredicate, 30, 44, 31, 0, // Skip to: 17098 +/* 9118 */ MCD_OPC_Decode, 240, 6, 136, 2, // Opcode: ASUB_U_B +/* 9123 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 9138 +/* 9128 */ MCD_OPC_CheckPredicate, 30, 29, 31, 0, // Skip to: 17098 +/* 9133 */ MCD_OPC_Decode, 242, 6, 137, 2, // Opcode: ASUB_U_H +/* 9138 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 9153 +/* 9143 */ MCD_OPC_CheckPredicate, 30, 14, 31, 0, // Skip to: 17098 +/* 9148 */ MCD_OPC_Decode, 243, 6, 138, 2, // Opcode: ASUB_U_W +/* 9153 */ MCD_OPC_FilterValue, 23, 4, 31, 0, // Skip to: 17098 +/* 9158 */ MCD_OPC_CheckPredicate, 30, 255, 30, 0, // Skip to: 17098 +/* 9163 */ MCD_OPC_Decode, 241, 6, 139, 2, // Opcode: ASUB_U_D +/* 9168 */ MCD_OPC_FilterValue, 18, 167, 1, 0, // Skip to: 9596 +/* 9173 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 9176 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9191 +/* 9181 */ MCD_OPC_CheckPredicate, 30, 232, 30, 0, // Skip to: 17098 +/* 9186 */ MCD_OPC_Decode, 241, 18, 136, 2, // Opcode: MULV_B +/* 9191 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9206 +/* 9196 */ MCD_OPC_CheckPredicate, 30, 217, 30, 0, // Skip to: 17098 +/* 9201 */ MCD_OPC_Decode, 243, 18, 137, 2, // Opcode: MULV_H +/* 9206 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9221 +/* 9211 */ MCD_OPC_CheckPredicate, 30, 202, 30, 0, // Skip to: 17098 +/* 9216 */ MCD_OPC_Decode, 244, 18, 138, 2, // Opcode: MULV_W +/* 9221 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9236 +/* 9226 */ MCD_OPC_CheckPredicate, 30, 187, 30, 0, // Skip to: 17098 +/* 9231 */ MCD_OPC_Decode, 242, 18, 139, 2, // Opcode: MULV_D +/* 9236 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 9251 +/* 9241 */ MCD_OPC_CheckPredicate, 30, 172, 30, 0, // Skip to: 17098 +/* 9246 */ MCD_OPC_Decode, 206, 16, 140, 2, // Opcode: MADDV_B +/* 9251 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 9266 +/* 9256 */ MCD_OPC_CheckPredicate, 30, 157, 30, 0, // Skip to: 17098 +/* 9261 */ MCD_OPC_Decode, 208, 16, 141, 2, // Opcode: MADDV_H +/* 9266 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 9281 +/* 9271 */ MCD_OPC_CheckPredicate, 30, 142, 30, 0, // Skip to: 17098 +/* 9276 */ MCD_OPC_Decode, 209, 16, 142, 2, // Opcode: MADDV_W +/* 9281 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 9296 +/* 9286 */ MCD_OPC_CheckPredicate, 30, 127, 30, 0, // Skip to: 17098 +/* 9291 */ MCD_OPC_Decode, 207, 16, 143, 2, // Opcode: MADDV_D +/* 9296 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 9311 +/* 9301 */ MCD_OPC_CheckPredicate, 30, 112, 30, 0, // Skip to: 17098 +/* 9306 */ MCD_OPC_Decode, 142, 18, 140, 2, // Opcode: MSUBV_B +/* 9311 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 9326 +/* 9316 */ MCD_OPC_CheckPredicate, 30, 97, 30, 0, // Skip to: 17098 +/* 9321 */ MCD_OPC_Decode, 144, 18, 141, 2, // Opcode: MSUBV_H +/* 9326 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 9341 +/* 9331 */ MCD_OPC_CheckPredicate, 30, 82, 30, 0, // Skip to: 17098 +/* 9336 */ MCD_OPC_Decode, 145, 18, 142, 2, // Opcode: MSUBV_W +/* 9341 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 9356 +/* 9346 */ MCD_OPC_CheckPredicate, 30, 67, 30, 0, // Skip to: 17098 +/* 9351 */ MCD_OPC_Decode, 143, 18, 143, 2, // Opcode: MSUBV_D +/* 9356 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 9371 +/* 9361 */ MCD_OPC_CheckPredicate, 30, 52, 30, 0, // Skip to: 17098 +/* 9366 */ MCD_OPC_Decode, 224, 11, 136, 2, // Opcode: DIV_S_B +/* 9371 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 9386 +/* 9376 */ MCD_OPC_CheckPredicate, 30, 37, 30, 0, // Skip to: 17098 +/* 9381 */ MCD_OPC_Decode, 226, 11, 137, 2, // Opcode: DIV_S_H +/* 9386 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 9401 +/* 9391 */ MCD_OPC_CheckPredicate, 30, 22, 30, 0, // Skip to: 17098 +/* 9396 */ MCD_OPC_Decode, 227, 11, 138, 2, // Opcode: DIV_S_W +/* 9401 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 9416 +/* 9406 */ MCD_OPC_CheckPredicate, 30, 7, 30, 0, // Skip to: 17098 +/* 9411 */ MCD_OPC_Decode, 225, 11, 139, 2, // Opcode: DIV_S_D +/* 9416 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 9431 +/* 9421 */ MCD_OPC_CheckPredicate, 30, 248, 29, 0, // Skip to: 17098 +/* 9426 */ MCD_OPC_Decode, 228, 11, 136, 2, // Opcode: DIV_U_B +/* 9431 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 9446 +/* 9436 */ MCD_OPC_CheckPredicate, 30, 233, 29, 0, // Skip to: 17098 +/* 9441 */ MCD_OPC_Decode, 230, 11, 137, 2, // Opcode: DIV_U_H +/* 9446 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 9461 +/* 9451 */ MCD_OPC_CheckPredicate, 30, 218, 29, 0, // Skip to: 17098 +/* 9456 */ MCD_OPC_Decode, 231, 11, 138, 2, // Opcode: DIV_U_W +/* 9461 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 9476 +/* 9466 */ MCD_OPC_CheckPredicate, 30, 203, 29, 0, // Skip to: 17098 +/* 9471 */ MCD_OPC_Decode, 229, 11, 139, 2, // Opcode: DIV_U_D +/* 9476 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 9491 +/* 9481 */ MCD_OPC_CheckPredicate, 30, 188, 29, 0, // Skip to: 17098 +/* 9486 */ MCD_OPC_Decode, 200, 17, 136, 2, // Opcode: MOD_S_B +/* 9491 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 9506 +/* 9496 */ MCD_OPC_CheckPredicate, 30, 173, 29, 0, // Skip to: 17098 +/* 9501 */ MCD_OPC_Decode, 202, 17, 137, 2, // Opcode: MOD_S_H +/* 9506 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 9521 +/* 9511 */ MCD_OPC_CheckPredicate, 30, 158, 29, 0, // Skip to: 17098 +/* 9516 */ MCD_OPC_Decode, 203, 17, 138, 2, // Opcode: MOD_S_W +/* 9521 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 9536 +/* 9526 */ MCD_OPC_CheckPredicate, 30, 143, 29, 0, // Skip to: 17098 +/* 9531 */ MCD_OPC_Decode, 201, 17, 139, 2, // Opcode: MOD_S_D +/* 9536 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 9551 +/* 9541 */ MCD_OPC_CheckPredicate, 30, 128, 29, 0, // Skip to: 17098 +/* 9546 */ MCD_OPC_Decode, 204, 17, 136, 2, // Opcode: MOD_U_B +/* 9551 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 9566 +/* 9556 */ MCD_OPC_CheckPredicate, 30, 113, 29, 0, // Skip to: 17098 +/* 9561 */ MCD_OPC_Decode, 206, 17, 137, 2, // Opcode: MOD_U_H +/* 9566 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 9581 +/* 9571 */ MCD_OPC_CheckPredicate, 30, 98, 29, 0, // Skip to: 17098 +/* 9576 */ MCD_OPC_Decode, 207, 17, 138, 2, // Opcode: MOD_U_W +/* 9581 */ MCD_OPC_FilterValue, 31, 88, 29, 0, // Skip to: 17098 +/* 9586 */ MCD_OPC_CheckPredicate, 30, 83, 29, 0, // Skip to: 17098 +/* 9591 */ MCD_OPC_Decode, 205, 17, 139, 2, // Opcode: MOD_U_D +/* 9596 */ MCD_OPC_FilterValue, 19, 17, 1, 0, // Skip to: 9874 +/* 9601 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 9604 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9619 +/* 9609 */ MCD_OPC_CheckPredicate, 30, 60, 29, 0, // Skip to: 17098 +/* 9614 */ MCD_OPC_Decode, 131, 12, 144, 2, // Opcode: DOTP_S_H +/* 9619 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9634 +/* 9624 */ MCD_OPC_CheckPredicate, 30, 45, 29, 0, // Skip to: 17098 +/* 9629 */ MCD_OPC_Decode, 132, 12, 145, 2, // Opcode: DOTP_S_W +/* 9634 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9649 +/* 9639 */ MCD_OPC_CheckPredicate, 30, 30, 29, 0, // Skip to: 17098 +/* 9644 */ MCD_OPC_Decode, 130, 12, 146, 2, // Opcode: DOTP_S_D +/* 9649 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 9664 +/* 9654 */ MCD_OPC_CheckPredicate, 30, 15, 29, 0, // Skip to: 17098 +/* 9659 */ MCD_OPC_Decode, 134, 12, 144, 2, // Opcode: DOTP_U_H +/* 9664 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 9679 +/* 9669 */ MCD_OPC_CheckPredicate, 30, 0, 29, 0, // Skip to: 17098 +/* 9674 */ MCD_OPC_Decode, 135, 12, 145, 2, // Opcode: DOTP_U_W +/* 9679 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 9694 +/* 9684 */ MCD_OPC_CheckPredicate, 30, 241, 28, 0, // Skip to: 17098 +/* 9689 */ MCD_OPC_Decode, 133, 12, 146, 2, // Opcode: DOTP_U_D +/* 9694 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 9709 +/* 9699 */ MCD_OPC_CheckPredicate, 30, 226, 28, 0, // Skip to: 17098 +/* 9704 */ MCD_OPC_Decode, 137, 12, 147, 2, // Opcode: DPADD_S_H +/* 9709 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 9724 +/* 9714 */ MCD_OPC_CheckPredicate, 30, 211, 28, 0, // Skip to: 17098 +/* 9719 */ MCD_OPC_Decode, 138, 12, 148, 2, // Opcode: DPADD_S_W +/* 9724 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 9739 +/* 9729 */ MCD_OPC_CheckPredicate, 30, 196, 28, 0, // Skip to: 17098 +/* 9734 */ MCD_OPC_Decode, 136, 12, 149, 2, // Opcode: DPADD_S_D +/* 9739 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 9754 +/* 9744 */ MCD_OPC_CheckPredicate, 30, 181, 28, 0, // Skip to: 17098 +/* 9749 */ MCD_OPC_Decode, 140, 12, 147, 2, // Opcode: DPADD_U_H +/* 9754 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9769 +/* 9759 */ MCD_OPC_CheckPredicate, 30, 166, 28, 0, // Skip to: 17098 +/* 9764 */ MCD_OPC_Decode, 141, 12, 148, 2, // Opcode: DPADD_U_W +/* 9769 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 9784 +/* 9774 */ MCD_OPC_CheckPredicate, 30, 151, 28, 0, // Skip to: 17098 +/* 9779 */ MCD_OPC_Decode, 139, 12, 149, 2, // Opcode: DPADD_U_D +/* 9784 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 9799 +/* 9789 */ MCD_OPC_CheckPredicate, 30, 136, 28, 0, // Skip to: 17098 +/* 9794 */ MCD_OPC_Decode, 168, 12, 147, 2, // Opcode: DPSUB_S_H +/* 9799 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 9814 +/* 9804 */ MCD_OPC_CheckPredicate, 30, 121, 28, 0, // Skip to: 17098 +/* 9809 */ MCD_OPC_Decode, 169, 12, 148, 2, // Opcode: DPSUB_S_W +/* 9814 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 9829 +/* 9819 */ MCD_OPC_CheckPredicate, 30, 106, 28, 0, // Skip to: 17098 +/* 9824 */ MCD_OPC_Decode, 167, 12, 149, 2, // Opcode: DPSUB_S_D +/* 9829 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 9844 +/* 9834 */ MCD_OPC_CheckPredicate, 30, 91, 28, 0, // Skip to: 17098 +/* 9839 */ MCD_OPC_Decode, 171, 12, 147, 2, // Opcode: DPSUB_U_H +/* 9844 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 9859 +/* 9849 */ MCD_OPC_CheckPredicate, 30, 76, 28, 0, // Skip to: 17098 +/* 9854 */ MCD_OPC_Decode, 172, 12, 148, 2, // Opcode: DPSUB_U_W +/* 9859 */ MCD_OPC_FilterValue, 23, 66, 28, 0, // Skip to: 17098 +/* 9864 */ MCD_OPC_CheckPredicate, 30, 61, 28, 0, // Skip to: 17098 +/* 9869 */ MCD_OPC_Decode, 170, 12, 149, 2, // Opcode: DPSUB_U_D +/* 9874 */ MCD_OPC_FilterValue, 20, 227, 1, 0, // Skip to: 10362 +/* 9879 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 9882 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9897 +/* 9887 */ MCD_OPC_CheckPredicate, 30, 38, 28, 0, // Skip to: 17098 +/* 9892 */ MCD_OPC_Decode, 215, 21, 150, 2, // Opcode: SLD_B +/* 9897 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9912 +/* 9902 */ MCD_OPC_CheckPredicate, 30, 23, 28, 0, // Skip to: 17098 +/* 9907 */ MCD_OPC_Decode, 217, 21, 151, 2, // Opcode: SLD_H +/* 9912 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9927 +/* 9917 */ MCD_OPC_CheckPredicate, 30, 8, 28, 0, // Skip to: 17098 +/* 9922 */ MCD_OPC_Decode, 218, 21, 152, 2, // Opcode: SLD_W +/* 9927 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9942 +/* 9932 */ MCD_OPC_CheckPredicate, 30, 249, 27, 0, // Skip to: 17098 +/* 9937 */ MCD_OPC_Decode, 216, 21, 153, 2, // Opcode: SLD_D +/* 9942 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 9957 +/* 9947 */ MCD_OPC_CheckPredicate, 30, 234, 27, 0, // Skip to: 17098 +/* 9952 */ MCD_OPC_Decode, 134, 22, 154, 2, // Opcode: SPLAT_B +/* 9957 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 9972 +/* 9962 */ MCD_OPC_CheckPredicate, 30, 219, 27, 0, // Skip to: 17098 +/* 9967 */ MCD_OPC_Decode, 136, 22, 155, 2, // Opcode: SPLAT_H +/* 9972 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 9987 +/* 9977 */ MCD_OPC_CheckPredicate, 30, 204, 27, 0, // Skip to: 17098 +/* 9982 */ MCD_OPC_Decode, 137, 22, 156, 2, // Opcode: SPLAT_W +/* 9987 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 10002 +/* 9992 */ MCD_OPC_CheckPredicate, 30, 189, 27, 0, // Skip to: 17098 +/* 9997 */ MCD_OPC_Decode, 135, 22, 157, 2, // Opcode: SPLAT_D +/* 10002 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 10017 +/* 10007 */ MCD_OPC_CheckPredicate, 30, 174, 27, 0, // Skip to: 17098 +/* 10012 */ MCD_OPC_Decode, 185, 19, 136, 2, // Opcode: PCKEV_B +/* 10017 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 10032 +/* 10022 */ MCD_OPC_CheckPredicate, 30, 159, 27, 0, // Skip to: 17098 +/* 10027 */ MCD_OPC_Decode, 187, 19, 137, 2, // Opcode: PCKEV_H +/* 10032 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 10047 +/* 10037 */ MCD_OPC_CheckPredicate, 30, 144, 27, 0, // Skip to: 17098 +/* 10042 */ MCD_OPC_Decode, 188, 19, 138, 2, // Opcode: PCKEV_W +/* 10047 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 10062 +/* 10052 */ MCD_OPC_CheckPredicate, 30, 129, 27, 0, // Skip to: 17098 +/* 10057 */ MCD_OPC_Decode, 186, 19, 139, 2, // Opcode: PCKEV_D +/* 10062 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 10077 +/* 10067 */ MCD_OPC_CheckPredicate, 30, 114, 27, 0, // Skip to: 17098 +/* 10072 */ MCD_OPC_Decode, 189, 19, 136, 2, // Opcode: PCKOD_B +/* 10077 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 10092 +/* 10082 */ MCD_OPC_CheckPredicate, 30, 99, 27, 0, // Skip to: 17098 +/* 10087 */ MCD_OPC_Decode, 191, 19, 137, 2, // Opcode: PCKOD_H +/* 10092 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 10107 +/* 10097 */ MCD_OPC_CheckPredicate, 30, 84, 27, 0, // Skip to: 17098 +/* 10102 */ MCD_OPC_Decode, 192, 19, 138, 2, // Opcode: PCKOD_W +/* 10107 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 10122 +/* 10112 */ MCD_OPC_CheckPredicate, 30, 69, 27, 0, // Skip to: 17098 +/* 10117 */ MCD_OPC_Decode, 190, 19, 139, 2, // Opcode: PCKOD_D +/* 10122 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 10137 +/* 10127 */ MCD_OPC_CheckPredicate, 30, 54, 27, 0, // Skip to: 17098 +/* 10132 */ MCD_OPC_Decode, 208, 14, 136, 2, // Opcode: ILVL_B +/* 10137 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 10152 +/* 10142 */ MCD_OPC_CheckPredicate, 30, 39, 27, 0, // Skip to: 17098 +/* 10147 */ MCD_OPC_Decode, 210, 14, 137, 2, // Opcode: ILVL_H +/* 10152 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 10167 +/* 10157 */ MCD_OPC_CheckPredicate, 30, 24, 27, 0, // Skip to: 17098 +/* 10162 */ MCD_OPC_Decode, 211, 14, 138, 2, // Opcode: ILVL_W +/* 10167 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 10182 +/* 10172 */ MCD_OPC_CheckPredicate, 30, 9, 27, 0, // Skip to: 17098 +/* 10177 */ MCD_OPC_Decode, 209, 14, 139, 2, // Opcode: ILVL_D +/* 10182 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 10197 +/* 10187 */ MCD_OPC_CheckPredicate, 30, 250, 26, 0, // Skip to: 17098 +/* 10192 */ MCD_OPC_Decode, 216, 14, 136, 2, // Opcode: ILVR_B +/* 10197 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 10212 +/* 10202 */ MCD_OPC_CheckPredicate, 30, 235, 26, 0, // Skip to: 17098 +/* 10207 */ MCD_OPC_Decode, 218, 14, 137, 2, // Opcode: ILVR_H +/* 10212 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 10227 +/* 10217 */ MCD_OPC_CheckPredicate, 30, 220, 26, 0, // Skip to: 17098 +/* 10222 */ MCD_OPC_Decode, 219, 14, 138, 2, // Opcode: ILVR_W +/* 10227 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 10242 +/* 10232 */ MCD_OPC_CheckPredicate, 30, 205, 26, 0, // Skip to: 17098 +/* 10237 */ MCD_OPC_Decode, 217, 14, 139, 2, // Opcode: ILVR_D +/* 10242 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 10257 +/* 10247 */ MCD_OPC_CheckPredicate, 30, 190, 26, 0, // Skip to: 17098 +/* 10252 */ MCD_OPC_Decode, 204, 14, 136, 2, // Opcode: ILVEV_B +/* 10257 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 10272 +/* 10262 */ MCD_OPC_CheckPredicate, 30, 175, 26, 0, // Skip to: 17098 +/* 10267 */ MCD_OPC_Decode, 206, 14, 137, 2, // Opcode: ILVEV_H +/* 10272 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 10287 +/* 10277 */ MCD_OPC_CheckPredicate, 30, 160, 26, 0, // Skip to: 17098 +/* 10282 */ MCD_OPC_Decode, 207, 14, 138, 2, // Opcode: ILVEV_W +/* 10287 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 10302 +/* 10292 */ MCD_OPC_CheckPredicate, 30, 145, 26, 0, // Skip to: 17098 +/* 10297 */ MCD_OPC_Decode, 205, 14, 139, 2, // Opcode: ILVEV_D +/* 10302 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 10317 +/* 10307 */ MCD_OPC_CheckPredicate, 30, 130, 26, 0, // Skip to: 17098 +/* 10312 */ MCD_OPC_Decode, 212, 14, 136, 2, // Opcode: ILVOD_B +/* 10317 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 10332 +/* 10322 */ MCD_OPC_CheckPredicate, 30, 115, 26, 0, // Skip to: 17098 +/* 10327 */ MCD_OPC_Decode, 214, 14, 137, 2, // Opcode: ILVOD_H +/* 10332 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 10347 +/* 10337 */ MCD_OPC_CheckPredicate, 30, 100, 26, 0, // Skip to: 17098 +/* 10342 */ MCD_OPC_Decode, 215, 14, 138, 2, // Opcode: ILVOD_W +/* 10347 */ MCD_OPC_FilterValue, 31, 90, 26, 0, // Skip to: 17098 +/* 10352 */ MCD_OPC_CheckPredicate, 30, 85, 26, 0, // Skip to: 17098 +/* 10357 */ MCD_OPC_Decode, 213, 14, 139, 2, // Opcode: ILVOD_D +/* 10362 */ MCD_OPC_FilterValue, 21, 107, 1, 0, // Skip to: 10730 +/* 10367 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 10370 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10385 +/* 10375 */ MCD_OPC_CheckPredicate, 30, 62, 26, 0, // Skip to: 17098 +/* 10380 */ MCD_OPC_Decode, 157, 24, 140, 2, // Opcode: VSHF_B +/* 10385 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10400 +/* 10390 */ MCD_OPC_CheckPredicate, 30, 47, 26, 0, // Skip to: 17098 +/* 10395 */ MCD_OPC_Decode, 159, 24, 141, 2, // Opcode: VSHF_H +/* 10400 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10415 +/* 10405 */ MCD_OPC_CheckPredicate, 30, 32, 26, 0, // Skip to: 17098 +/* 10410 */ MCD_OPC_Decode, 160, 24, 142, 2, // Opcode: VSHF_W +/* 10415 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 10430 +/* 10420 */ MCD_OPC_CheckPredicate, 30, 17, 26, 0, // Skip to: 17098 +/* 10425 */ MCD_OPC_Decode, 158, 24, 143, 2, // Opcode: VSHF_D +/* 10430 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 10445 +/* 10435 */ MCD_OPC_CheckPredicate, 30, 2, 26, 0, // Skip to: 17098 +/* 10440 */ MCD_OPC_Decode, 147, 22, 136, 2, // Opcode: SRAR_B +/* 10445 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 10460 +/* 10450 */ MCD_OPC_CheckPredicate, 30, 243, 25, 0, // Skip to: 17098 +/* 10455 */ MCD_OPC_Decode, 149, 22, 137, 2, // Opcode: SRAR_H +/* 10460 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 10475 +/* 10465 */ MCD_OPC_CheckPredicate, 30, 228, 25, 0, // Skip to: 17098 +/* 10470 */ MCD_OPC_Decode, 150, 22, 138, 2, // Opcode: SRAR_W +/* 10475 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 10490 +/* 10480 */ MCD_OPC_CheckPredicate, 30, 213, 25, 0, // Skip to: 17098 +/* 10485 */ MCD_OPC_Decode, 148, 22, 139, 2, // Opcode: SRAR_D +/* 10490 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 10505 +/* 10495 */ MCD_OPC_CheckPredicate, 30, 198, 25, 0, // Skip to: 17098 +/* 10500 */ MCD_OPC_Decode, 172, 22, 136, 2, // Opcode: SRLR_B +/* 10505 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 10520 +/* 10510 */ MCD_OPC_CheckPredicate, 30, 183, 25, 0, // Skip to: 17098 +/* 10515 */ MCD_OPC_Decode, 174, 22, 137, 2, // Opcode: SRLR_H +/* 10520 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 10535 +/* 10525 */ MCD_OPC_CheckPredicate, 30, 168, 25, 0, // Skip to: 17098 +/* 10530 */ MCD_OPC_Decode, 175, 22, 138, 2, // Opcode: SRLR_W +/* 10535 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 10550 +/* 10540 */ MCD_OPC_CheckPredicate, 30, 153, 25, 0, // Skip to: 17098 +/* 10545 */ MCD_OPC_Decode, 173, 22, 139, 2, // Opcode: SRLR_D +/* 10550 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 10565 +/* 10555 */ MCD_OPC_CheckPredicate, 30, 138, 25, 0, // Skip to: 17098 +/* 10560 */ MCD_OPC_Decode, 191, 14, 144, 2, // Opcode: HADD_S_H +/* 10565 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 10580 +/* 10570 */ MCD_OPC_CheckPredicate, 30, 123, 25, 0, // Skip to: 17098 +/* 10575 */ MCD_OPC_Decode, 192, 14, 145, 2, // Opcode: HADD_S_W +/* 10580 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 10595 +/* 10585 */ MCD_OPC_CheckPredicate, 30, 108, 25, 0, // Skip to: 17098 +/* 10590 */ MCD_OPC_Decode, 190, 14, 146, 2, // Opcode: HADD_S_D +/* 10595 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 10610 +/* 10600 */ MCD_OPC_CheckPredicate, 30, 93, 25, 0, // Skip to: 17098 +/* 10605 */ MCD_OPC_Decode, 194, 14, 144, 2, // Opcode: HADD_U_H +/* 10610 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 10625 +/* 10615 */ MCD_OPC_CheckPredicate, 30, 78, 25, 0, // Skip to: 17098 +/* 10620 */ MCD_OPC_Decode, 195, 14, 145, 2, // Opcode: HADD_U_W +/* 10625 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 10640 +/* 10630 */ MCD_OPC_CheckPredicate, 30, 63, 25, 0, // Skip to: 17098 +/* 10635 */ MCD_OPC_Decode, 193, 14, 146, 2, // Opcode: HADD_U_D +/* 10640 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 10655 +/* 10645 */ MCD_OPC_CheckPredicate, 30, 48, 25, 0, // Skip to: 17098 +/* 10650 */ MCD_OPC_Decode, 197, 14, 144, 2, // Opcode: HSUB_S_H +/* 10655 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 10670 +/* 10660 */ MCD_OPC_CheckPredicate, 30, 33, 25, 0, // Skip to: 17098 +/* 10665 */ MCD_OPC_Decode, 198, 14, 145, 2, // Opcode: HSUB_S_W +/* 10670 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 10685 +/* 10675 */ MCD_OPC_CheckPredicate, 30, 18, 25, 0, // Skip to: 17098 +/* 10680 */ MCD_OPC_Decode, 196, 14, 146, 2, // Opcode: HSUB_S_D +/* 10685 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 10700 +/* 10690 */ MCD_OPC_CheckPredicate, 30, 3, 25, 0, // Skip to: 17098 +/* 10695 */ MCD_OPC_Decode, 200, 14, 144, 2, // Opcode: HSUB_U_H +/* 10700 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 10715 +/* 10705 */ MCD_OPC_CheckPredicate, 30, 244, 24, 0, // Skip to: 17098 +/* 10710 */ MCD_OPC_Decode, 201, 14, 145, 2, // Opcode: HSUB_U_W +/* 10715 */ MCD_OPC_FilterValue, 31, 234, 24, 0, // Skip to: 17098 +/* 10720 */ MCD_OPC_CheckPredicate, 30, 229, 24, 0, // Skip to: 17098 +/* 10725 */ MCD_OPC_Decode, 199, 14, 146, 2, // Opcode: HSUB_U_D +/* 10730 */ MCD_OPC_FilterValue, 25, 26, 2, 0, // Skip to: 11273 +/* 10735 */ MCD_OPC_ExtractField, 20, 6, // Inst{25-20} ... +/* 10738 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10753 +/* 10743 */ MCD_OPC_CheckPredicate, 30, 206, 24, 0, // Skip to: 17098 +/* 10748 */ MCD_OPC_Decode, 211, 21, 158, 2, // Opcode: SLDI_B +/* 10753 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 10775 +/* 10758 */ MCD_OPC_CheckPredicate, 30, 191, 24, 0, // Skip to: 17098 +/* 10763 */ MCD_OPC_CheckField, 19, 1, 0, 184, 24, 0, // Skip to: 17098 +/* 10770 */ MCD_OPC_Decode, 213, 21, 159, 2, // Opcode: SLDI_H +/* 10775 */ MCD_OPC_FilterValue, 3, 62, 0, 0, // Skip to: 10842 +/* 10780 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 10783 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10798 +/* 10788 */ MCD_OPC_CheckPredicate, 30, 161, 24, 0, // Skip to: 17098 +/* 10793 */ MCD_OPC_Decode, 214, 21, 160, 2, // Opcode: SLDI_W +/* 10798 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 10820 +/* 10803 */ MCD_OPC_CheckPredicate, 30, 146, 24, 0, // Skip to: 17098 +/* 10808 */ MCD_OPC_CheckField, 17, 1, 0, 139, 24, 0, // Skip to: 17098 +/* 10815 */ MCD_OPC_Decode, 212, 21, 161, 2, // Opcode: SLDI_D +/* 10820 */ MCD_OPC_FilterValue, 3, 129, 24, 0, // Skip to: 17098 +/* 10825 */ MCD_OPC_CheckPredicate, 30, 124, 24, 0, // Skip to: 17098 +/* 10830 */ MCD_OPC_CheckField, 16, 2, 2, 117, 24, 0, // Skip to: 17098 +/* 10837 */ MCD_OPC_Decode, 182, 10, 162, 2, // Opcode: CTCMSA +/* 10842 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 10857 +/* 10847 */ MCD_OPC_CheckPredicate, 30, 102, 24, 0, // Skip to: 17098 +/* 10852 */ MCD_OPC_Decode, 130, 22, 163, 2, // Opcode: SPLATI_B +/* 10857 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 10879 +/* 10862 */ MCD_OPC_CheckPredicate, 30, 87, 24, 0, // Skip to: 17098 +/* 10867 */ MCD_OPC_CheckField, 19, 1, 0, 80, 24, 0, // Skip to: 17098 +/* 10874 */ MCD_OPC_Decode, 132, 22, 164, 2, // Opcode: SPLATI_H +/* 10879 */ MCD_OPC_FilterValue, 7, 62, 0, 0, // Skip to: 10946 +/* 10884 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 10887 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10902 +/* 10892 */ MCD_OPC_CheckPredicate, 30, 57, 24, 0, // Skip to: 17098 +/* 10897 */ MCD_OPC_Decode, 133, 22, 165, 2, // Opcode: SPLATI_W +/* 10902 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 10924 +/* 10907 */ MCD_OPC_CheckPredicate, 30, 42, 24, 0, // Skip to: 17098 +/* 10912 */ MCD_OPC_CheckField, 17, 1, 0, 35, 24, 0, // Skip to: 17098 +/* 10919 */ MCD_OPC_Decode, 131, 22, 166, 2, // Opcode: SPLATI_D +/* 10924 */ MCD_OPC_FilterValue, 3, 25, 24, 0, // Skip to: 17098 +/* 10929 */ MCD_OPC_CheckPredicate, 30, 20, 24, 0, // Skip to: 17098 +/* 10934 */ MCD_OPC_CheckField, 16, 2, 2, 13, 24, 0, // Skip to: 17098 +/* 10941 */ MCD_OPC_Decode, 147, 9, 167, 2, // Opcode: CFCMSA +/* 10946 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 10961 +/* 10951 */ MCD_OPC_CheckPredicate, 30, 254, 23, 0, // Skip to: 17098 +/* 10956 */ MCD_OPC_Decode, 158, 10, 168, 2, // Opcode: COPY_S_B +/* 10961 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 10983 +/* 10966 */ MCD_OPC_CheckPredicate, 30, 239, 23, 0, // Skip to: 17098 +/* 10971 */ MCD_OPC_CheckField, 19, 1, 0, 232, 23, 0, // Skip to: 17098 +/* 10978 */ MCD_OPC_Decode, 160, 10, 169, 2, // Opcode: COPY_S_H +/* 10983 */ MCD_OPC_FilterValue, 11, 62, 0, 0, // Skip to: 11050 +/* 10988 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 10991 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11006 +/* 10996 */ MCD_OPC_CheckPredicate, 30, 209, 23, 0, // Skip to: 17098 +/* 11001 */ MCD_OPC_Decode, 161, 10, 170, 2, // Opcode: COPY_S_W +/* 11006 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 11028 +/* 11011 */ MCD_OPC_CheckPredicate, 38, 194, 23, 0, // Skip to: 17098 +/* 11016 */ MCD_OPC_CheckField, 17, 1, 0, 187, 23, 0, // Skip to: 17098 +/* 11023 */ MCD_OPC_Decode, 159, 10, 171, 2, // Opcode: COPY_S_D +/* 11028 */ MCD_OPC_FilterValue, 3, 177, 23, 0, // Skip to: 17098 +/* 11033 */ MCD_OPC_CheckPredicate, 30, 172, 23, 0, // Skip to: 17098 +/* 11038 */ MCD_OPC_CheckField, 16, 2, 2, 165, 23, 0, // Skip to: 17098 +/* 11045 */ MCD_OPC_Decode, 216, 17, 172, 2, // Opcode: MOVE_V +/* 11050 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 11065 +/* 11055 */ MCD_OPC_CheckPredicate, 30, 150, 23, 0, // Skip to: 17098 +/* 11060 */ MCD_OPC_Decode, 162, 10, 168, 2, // Opcode: COPY_U_B +/* 11065 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 11087 +/* 11070 */ MCD_OPC_CheckPredicate, 30, 135, 23, 0, // Skip to: 17098 +/* 11075 */ MCD_OPC_CheckField, 19, 1, 0, 128, 23, 0, // Skip to: 17098 +/* 11082 */ MCD_OPC_Decode, 163, 10, 169, 2, // Opcode: COPY_U_H +/* 11087 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 11109 +/* 11092 */ MCD_OPC_CheckPredicate, 38, 113, 23, 0, // Skip to: 17098 +/* 11097 */ MCD_OPC_CheckField, 18, 2, 0, 106, 23, 0, // Skip to: 17098 +/* 11104 */ MCD_OPC_Decode, 164, 10, 170, 2, // Opcode: COPY_U_W +/* 11109 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 11124 +/* 11114 */ MCD_OPC_CheckPredicate, 30, 91, 23, 0, // Skip to: 17098 +/* 11119 */ MCD_OPC_Decode, 221, 14, 173, 2, // Opcode: INSERT_B +/* 11124 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 11146 +/* 11129 */ MCD_OPC_CheckPredicate, 30, 76, 23, 0, // Skip to: 17098 +/* 11134 */ MCD_OPC_CheckField, 19, 1, 0, 69, 23, 0, // Skip to: 17098 +/* 11141 */ MCD_OPC_Decode, 223, 14, 174, 2, // Opcode: INSERT_H +/* 11146 */ MCD_OPC_FilterValue, 19, 40, 0, 0, // Skip to: 11191 +/* 11151 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 11154 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11169 +/* 11159 */ MCD_OPC_CheckPredicate, 30, 46, 23, 0, // Skip to: 17098 +/* 11164 */ MCD_OPC_Decode, 224, 14, 175, 2, // Opcode: INSERT_W +/* 11169 */ MCD_OPC_FilterValue, 2, 36, 23, 0, // Skip to: 17098 +/* 11174 */ MCD_OPC_CheckPredicate, 38, 31, 23, 0, // Skip to: 17098 +/* 11179 */ MCD_OPC_CheckField, 17, 1, 0, 24, 23, 0, // Skip to: 17098 +/* 11186 */ MCD_OPC_Decode, 222, 14, 176, 2, // Opcode: INSERT_D +/* 11191 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 11206 +/* 11196 */ MCD_OPC_CheckPredicate, 30, 9, 23, 0, // Skip to: 17098 +/* 11201 */ MCD_OPC_Decode, 226, 14, 177, 2, // Opcode: INSVE_B +/* 11206 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 11228 +/* 11211 */ MCD_OPC_CheckPredicate, 30, 250, 22, 0, // Skip to: 17098 +/* 11216 */ MCD_OPC_CheckField, 19, 1, 0, 243, 22, 0, // Skip to: 17098 +/* 11223 */ MCD_OPC_Decode, 228, 14, 177, 2, // Opcode: INSVE_H +/* 11228 */ MCD_OPC_FilterValue, 23, 233, 22, 0, // Skip to: 17098 +/* 11233 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 11236 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11251 +/* 11241 */ MCD_OPC_CheckPredicate, 30, 220, 22, 0, // Skip to: 17098 +/* 11246 */ MCD_OPC_Decode, 229, 14, 177, 2, // Opcode: INSVE_W +/* 11251 */ MCD_OPC_FilterValue, 2, 210, 22, 0, // Skip to: 17098 +/* 11256 */ MCD_OPC_CheckPredicate, 30, 205, 22, 0, // Skip to: 17098 +/* 11261 */ MCD_OPC_CheckField, 17, 1, 0, 198, 22, 0, // Skip to: 17098 +/* 11268 */ MCD_OPC_Decode, 227, 14, 177, 2, // Opcode: INSVE_D +/* 11273 */ MCD_OPC_FilterValue, 26, 227, 1, 0, // Skip to: 11761 +/* 11278 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 11281 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11296 +/* 11286 */ MCD_OPC_CheckPredicate, 30, 175, 22, 0, // Skip to: 17098 +/* 11291 */ MCD_OPC_Decode, 147, 13, 138, 2, // Opcode: FCAF_W +/* 11296 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11311 +/* 11301 */ MCD_OPC_CheckPredicate, 30, 160, 22, 0, // Skip to: 17098 +/* 11306 */ MCD_OPC_Decode, 146, 13, 139, 2, // Opcode: FCAF_D +/* 11311 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11326 +/* 11316 */ MCD_OPC_CheckPredicate, 30, 145, 22, 0, // Skip to: 17098 +/* 11321 */ MCD_OPC_Decode, 174, 13, 138, 2, // Opcode: FCUN_W +/* 11326 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 11341 +/* 11331 */ MCD_OPC_CheckPredicate, 30, 130, 22, 0, // Skip to: 17098 +/* 11336 */ MCD_OPC_Decode, 173, 13, 139, 2, // Opcode: FCUN_D +/* 11341 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 11356 +/* 11346 */ MCD_OPC_CheckPredicate, 30, 115, 22, 0, // Skip to: 17098 +/* 11351 */ MCD_OPC_Decode, 149, 13, 138, 2, // Opcode: FCEQ_W +/* 11356 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 11371 +/* 11361 */ MCD_OPC_CheckPredicate, 30, 100, 22, 0, // Skip to: 17098 +/* 11366 */ MCD_OPC_Decode, 148, 13, 139, 2, // Opcode: FCEQ_D +/* 11371 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 11386 +/* 11376 */ MCD_OPC_CheckPredicate, 30, 85, 22, 0, // Skip to: 17098 +/* 11381 */ MCD_OPC_Decode, 166, 13, 138, 2, // Opcode: FCUEQ_W +/* 11386 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 11401 +/* 11391 */ MCD_OPC_CheckPredicate, 30, 70, 22, 0, // Skip to: 17098 +/* 11396 */ MCD_OPC_Decode, 165, 13, 139, 2, // Opcode: FCUEQ_D +/* 11401 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 11416 +/* 11406 */ MCD_OPC_CheckPredicate, 30, 55, 22, 0, // Skip to: 17098 +/* 11411 */ MCD_OPC_Decode, 155, 13, 138, 2, // Opcode: FCLT_W +/* 11416 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 11431 +/* 11421 */ MCD_OPC_CheckPredicate, 30, 40, 22, 0, // Skip to: 17098 +/* 11426 */ MCD_OPC_Decode, 154, 13, 139, 2, // Opcode: FCLT_D +/* 11431 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 11446 +/* 11436 */ MCD_OPC_CheckPredicate, 30, 25, 22, 0, // Skip to: 17098 +/* 11441 */ MCD_OPC_Decode, 170, 13, 138, 2, // Opcode: FCULT_W +/* 11446 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 11461 +/* 11451 */ MCD_OPC_CheckPredicate, 30, 10, 22, 0, // Skip to: 17098 +/* 11456 */ MCD_OPC_Decode, 169, 13, 139, 2, // Opcode: FCULT_D +/* 11461 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 11476 +/* 11466 */ MCD_OPC_CheckPredicate, 30, 251, 21, 0, // Skip to: 17098 +/* 11471 */ MCD_OPC_Decode, 153, 13, 138, 2, // Opcode: FCLE_W +/* 11476 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 11491 +/* 11481 */ MCD_OPC_CheckPredicate, 30, 236, 21, 0, // Skip to: 17098 +/* 11486 */ MCD_OPC_Decode, 152, 13, 139, 2, // Opcode: FCLE_D +/* 11491 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11506 +/* 11496 */ MCD_OPC_CheckPredicate, 30, 221, 21, 0, // Skip to: 17098 +/* 11501 */ MCD_OPC_Decode, 168, 13, 138, 2, // Opcode: FCULE_W +/* 11506 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 11521 +/* 11511 */ MCD_OPC_CheckPredicate, 30, 206, 21, 0, // Skip to: 17098 +/* 11516 */ MCD_OPC_Decode, 167, 13, 139, 2, // Opcode: FCULE_D +/* 11521 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 11536 +/* 11526 */ MCD_OPC_CheckPredicate, 30, 191, 21, 0, // Skip to: 17098 +/* 11531 */ MCD_OPC_Decode, 135, 14, 138, 2, // Opcode: FSAF_W +/* 11536 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 11551 +/* 11541 */ MCD_OPC_CheckPredicate, 30, 176, 21, 0, // Skip to: 17098 +/* 11546 */ MCD_OPC_Decode, 134, 14, 139, 2, // Opcode: FSAF_D +/* 11551 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 11566 +/* 11556 */ MCD_OPC_CheckPredicate, 30, 161, 21, 0, // Skip to: 17098 +/* 11561 */ MCD_OPC_Decode, 173, 14, 138, 2, // Opcode: FSUN_W +/* 11566 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 11581 +/* 11571 */ MCD_OPC_CheckPredicate, 30, 146, 21, 0, // Skip to: 17098 +/* 11576 */ MCD_OPC_Decode, 172, 14, 139, 2, // Opcode: FSUN_D +/* 11581 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 11596 +/* 11586 */ MCD_OPC_CheckPredicate, 30, 131, 21, 0, // Skip to: 17098 +/* 11591 */ MCD_OPC_Decode, 137, 14, 138, 2, // Opcode: FSEQ_W +/* 11596 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 11611 +/* 11601 */ MCD_OPC_CheckPredicate, 30, 116, 21, 0, // Skip to: 17098 +/* 11606 */ MCD_OPC_Decode, 136, 14, 139, 2, // Opcode: FSEQ_D +/* 11611 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 11626 +/* 11616 */ MCD_OPC_CheckPredicate, 30, 101, 21, 0, // Skip to: 17098 +/* 11621 */ MCD_OPC_Decode, 165, 14, 138, 2, // Opcode: FSUEQ_W +/* 11626 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 11641 +/* 11631 */ MCD_OPC_CheckPredicate, 30, 86, 21, 0, // Skip to: 17098 +/* 11636 */ MCD_OPC_Decode, 164, 14, 139, 2, // Opcode: FSUEQ_D +/* 11641 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 11656 +/* 11646 */ MCD_OPC_CheckPredicate, 30, 71, 21, 0, // Skip to: 17098 +/* 11651 */ MCD_OPC_Decode, 141, 14, 138, 2, // Opcode: FSLT_W +/* 11656 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 11671 +/* 11661 */ MCD_OPC_CheckPredicate, 30, 56, 21, 0, // Skip to: 17098 +/* 11666 */ MCD_OPC_Decode, 140, 14, 139, 2, // Opcode: FSLT_D +/* 11671 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 11686 +/* 11676 */ MCD_OPC_CheckPredicate, 30, 41, 21, 0, // Skip to: 17098 +/* 11681 */ MCD_OPC_Decode, 169, 14, 138, 2, // Opcode: FSULT_W +/* 11686 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 11701 +/* 11691 */ MCD_OPC_CheckPredicate, 30, 26, 21, 0, // Skip to: 17098 +/* 11696 */ MCD_OPC_Decode, 168, 14, 139, 2, // Opcode: FSULT_D +/* 11701 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 11716 +/* 11706 */ MCD_OPC_CheckPredicate, 30, 11, 21, 0, // Skip to: 17098 +/* 11711 */ MCD_OPC_Decode, 139, 14, 138, 2, // Opcode: FSLE_W +/* 11716 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 11731 +/* 11721 */ MCD_OPC_CheckPredicate, 30, 252, 20, 0, // Skip to: 17098 +/* 11726 */ MCD_OPC_Decode, 138, 14, 139, 2, // Opcode: FSLE_D +/* 11731 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 11746 +/* 11736 */ MCD_OPC_CheckPredicate, 30, 237, 20, 0, // Skip to: 17098 +/* 11741 */ MCD_OPC_Decode, 167, 14, 138, 2, // Opcode: FSULE_W +/* 11746 */ MCD_OPC_FilterValue, 31, 227, 20, 0, // Skip to: 17098 +/* 11751 */ MCD_OPC_CheckPredicate, 30, 222, 20, 0, // Skip to: 17098 +/* 11756 */ MCD_OPC_Decode, 166, 14, 139, 2, // Opcode: FSULE_D +/* 11761 */ MCD_OPC_FilterValue, 27, 137, 1, 0, // Skip to: 12159 +/* 11766 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 11769 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11784 +/* 11774 */ MCD_OPC_CheckPredicate, 30, 199, 20, 0, // Skip to: 17098 +/* 11779 */ MCD_OPC_Decode, 145, 13, 138, 2, // Opcode: FADD_W +/* 11784 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11799 +/* 11789 */ MCD_OPC_CheckPredicate, 30, 184, 20, 0, // Skip to: 17098 +/* 11794 */ MCD_OPC_Decode, 136, 13, 139, 2, // Opcode: FADD_D +/* 11799 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11814 +/* 11804 */ MCD_OPC_CheckPredicate, 30, 169, 20, 0, // Skip to: 17098 +/* 11809 */ MCD_OPC_Decode, 163, 14, 138, 2, // Opcode: FSUB_W +/* 11814 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 11829 +/* 11819 */ MCD_OPC_CheckPredicate, 30, 154, 20, 0, // Skip to: 17098 +/* 11824 */ MCD_OPC_Decode, 154, 14, 139, 2, // Opcode: FSUB_D +/* 11829 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 11844 +/* 11834 */ MCD_OPC_CheckPredicate, 30, 139, 20, 0, // Skip to: 17098 +/* 11839 */ MCD_OPC_Decode, 246, 13, 138, 2, // Opcode: FMUL_W +/* 11844 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 11859 +/* 11849 */ MCD_OPC_CheckPredicate, 30, 124, 20, 0, // Skip to: 17098 +/* 11854 */ MCD_OPC_Decode, 237, 13, 139, 2, // Opcode: FMUL_D +/* 11859 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 11874 +/* 11864 */ MCD_OPC_CheckPredicate, 30, 109, 20, 0, // Skip to: 17098 +/* 11869 */ MCD_OPC_Decode, 183, 13, 138, 2, // Opcode: FDIV_W +/* 11874 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 11889 +/* 11879 */ MCD_OPC_CheckPredicate, 30, 94, 20, 0, // Skip to: 17098 +/* 11884 */ MCD_OPC_Decode, 175, 13, 139, 2, // Opcode: FDIV_D +/* 11889 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 11904 +/* 11894 */ MCD_OPC_CheckPredicate, 30, 79, 20, 0, // Skip to: 17098 +/* 11899 */ MCD_OPC_Decode, 218, 13, 142, 2, // Opcode: FMADD_W +/* 11904 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 11919 +/* 11909 */ MCD_OPC_CheckPredicate, 30, 64, 20, 0, // Skip to: 17098 +/* 11914 */ MCD_OPC_Decode, 217, 13, 143, 2, // Opcode: FMADD_D +/* 11919 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 11934 +/* 11924 */ MCD_OPC_CheckPredicate, 30, 49, 20, 0, // Skip to: 17098 +/* 11929 */ MCD_OPC_Decode, 236, 13, 142, 2, // Opcode: FMSUB_W +/* 11934 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 11949 +/* 11939 */ MCD_OPC_CheckPredicate, 30, 34, 20, 0, // Skip to: 17098 +/* 11944 */ MCD_OPC_Decode, 235, 13, 143, 2, // Opcode: FMSUB_D +/* 11949 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11964 +/* 11954 */ MCD_OPC_CheckPredicate, 30, 19, 20, 0, // Skip to: 17098 +/* 11959 */ MCD_OPC_Decode, 187, 13, 138, 2, // Opcode: FEXP2_W +/* 11964 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 11979 +/* 11969 */ MCD_OPC_CheckPredicate, 30, 4, 20, 0, // Skip to: 17098 +/* 11974 */ MCD_OPC_Decode, 186, 13, 139, 2, // Opcode: FEXP2_D +/* 11979 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 11994 +/* 11984 */ MCD_OPC_CheckPredicate, 30, 245, 19, 0, // Skip to: 17098 +/* 11989 */ MCD_OPC_Decode, 184, 13, 178, 2, // Opcode: FEXDO_H +/* 11994 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 12009 +/* 11999 */ MCD_OPC_CheckPredicate, 30, 230, 19, 0, // Skip to: 17098 +/* 12004 */ MCD_OPC_Decode, 185, 13, 179, 2, // Opcode: FEXDO_W +/* 12009 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 12024 +/* 12014 */ MCD_OPC_CheckPredicate, 30, 215, 19, 0, // Skip to: 17098 +/* 12019 */ MCD_OPC_Decode, 178, 14, 178, 2, // Opcode: FTQ_H +/* 12024 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 12039 +/* 12029 */ MCD_OPC_CheckPredicate, 30, 200, 19, 0, // Skip to: 17098 +/* 12034 */ MCD_OPC_Decode, 179, 14, 179, 2, // Opcode: FTQ_W +/* 12039 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 12054 +/* 12044 */ MCD_OPC_CheckPredicate, 30, 185, 19, 0, // Skip to: 17098 +/* 12049 */ MCD_OPC_Decode, 226, 13, 138, 2, // Opcode: FMIN_W +/* 12054 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 12069 +/* 12059 */ MCD_OPC_CheckPredicate, 30, 170, 19, 0, // Skip to: 17098 +/* 12064 */ MCD_OPC_Decode, 225, 13, 139, 2, // Opcode: FMIN_D +/* 12069 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 12084 +/* 12074 */ MCD_OPC_CheckPredicate, 30, 155, 19, 0, // Skip to: 17098 +/* 12079 */ MCD_OPC_Decode, 224, 13, 138, 2, // Opcode: FMIN_A_W +/* 12084 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 12099 +/* 12089 */ MCD_OPC_CheckPredicate, 30, 140, 19, 0, // Skip to: 17098 +/* 12094 */ MCD_OPC_Decode, 223, 13, 139, 2, // Opcode: FMIN_A_D +/* 12099 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 12114 +/* 12104 */ MCD_OPC_CheckPredicate, 30, 125, 19, 0, // Skip to: 17098 +/* 12109 */ MCD_OPC_Decode, 222, 13, 138, 2, // Opcode: FMAX_W +/* 12114 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 12129 +/* 12119 */ MCD_OPC_CheckPredicate, 30, 110, 19, 0, // Skip to: 17098 +/* 12124 */ MCD_OPC_Decode, 221, 13, 139, 2, // Opcode: FMAX_D +/* 12129 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 12144 +/* 12134 */ MCD_OPC_CheckPredicate, 30, 95, 19, 0, // Skip to: 17098 +/* 12139 */ MCD_OPC_Decode, 220, 13, 138, 2, // Opcode: FMAX_A_W +/* 12144 */ MCD_OPC_FilterValue, 31, 85, 19, 0, // Skip to: 17098 +/* 12149 */ MCD_OPC_CheckPredicate, 30, 80, 19, 0, // Skip to: 17098 +/* 12154 */ MCD_OPC_Decode, 219, 13, 139, 2, // Opcode: FMAX_A_D +/* 12159 */ MCD_OPC_FilterValue, 28, 107, 1, 0, // Skip to: 12527 +/* 12164 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 12167 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12182 +/* 12172 */ MCD_OPC_CheckPredicate, 30, 57, 19, 0, // Skip to: 17098 +/* 12177 */ MCD_OPC_Decode, 164, 13, 138, 2, // Opcode: FCOR_W +/* 12182 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12197 +/* 12187 */ MCD_OPC_CheckPredicate, 30, 42, 19, 0, // Skip to: 17098 +/* 12192 */ MCD_OPC_Decode, 163, 13, 139, 2, // Opcode: FCOR_D +/* 12197 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12212 +/* 12202 */ MCD_OPC_CheckPredicate, 30, 27, 19, 0, // Skip to: 17098 +/* 12207 */ MCD_OPC_Decode, 172, 13, 138, 2, // Opcode: FCUNE_W +/* 12212 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 12227 +/* 12217 */ MCD_OPC_CheckPredicate, 30, 12, 19, 0, // Skip to: 17098 +/* 12222 */ MCD_OPC_Decode, 171, 13, 139, 2, // Opcode: FCUNE_D +/* 12227 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 12242 +/* 12232 */ MCD_OPC_CheckPredicate, 30, 253, 18, 0, // Skip to: 17098 +/* 12237 */ MCD_OPC_Decode, 162, 13, 138, 2, // Opcode: FCNE_W +/* 12242 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 12257 +/* 12247 */ MCD_OPC_CheckPredicate, 30, 238, 18, 0, // Skip to: 17098 +/* 12252 */ MCD_OPC_Decode, 161, 13, 139, 2, // Opcode: FCNE_D +/* 12257 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 12272 +/* 12262 */ MCD_OPC_CheckPredicate, 30, 223, 18, 0, // Skip to: 17098 +/* 12267 */ MCD_OPC_Decode, 250, 18, 137, 2, // Opcode: MUL_Q_H +/* 12272 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 12287 +/* 12277 */ MCD_OPC_CheckPredicate, 30, 208, 18, 0, // Skip to: 17098 +/* 12282 */ MCD_OPC_Decode, 251, 18, 138, 2, // Opcode: MUL_Q_W +/* 12287 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 12302 +/* 12292 */ MCD_OPC_CheckPredicate, 30, 193, 18, 0, // Skip to: 17098 +/* 12297 */ MCD_OPC_Decode, 216, 16, 141, 2, // Opcode: MADD_Q_H +/* 12302 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 12317 +/* 12307 */ MCD_OPC_CheckPredicate, 30, 178, 18, 0, // Skip to: 17098 +/* 12312 */ MCD_OPC_Decode, 217, 16, 142, 2, // Opcode: MADD_Q_W +/* 12317 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 12332 +/* 12322 */ MCD_OPC_CheckPredicate, 30, 163, 18, 0, // Skip to: 17098 +/* 12327 */ MCD_OPC_Decode, 152, 18, 141, 2, // Opcode: MSUB_Q_H +/* 12332 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 12347 +/* 12337 */ MCD_OPC_CheckPredicate, 30, 148, 18, 0, // Skip to: 17098 +/* 12342 */ MCD_OPC_Decode, 153, 18, 142, 2, // Opcode: MSUB_Q_W +/* 12347 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 12362 +/* 12352 */ MCD_OPC_CheckPredicate, 30, 133, 18, 0, // Skip to: 17098 +/* 12357 */ MCD_OPC_Decode, 145, 14, 138, 2, // Opcode: FSOR_W +/* 12362 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 12377 +/* 12367 */ MCD_OPC_CheckPredicate, 30, 118, 18, 0, // Skip to: 17098 +/* 12372 */ MCD_OPC_Decode, 144, 14, 139, 2, // Opcode: FSOR_D +/* 12377 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 12392 +/* 12382 */ MCD_OPC_CheckPredicate, 30, 103, 18, 0, // Skip to: 17098 +/* 12387 */ MCD_OPC_Decode, 171, 14, 138, 2, // Opcode: FSUNE_W +/* 12392 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 12407 +/* 12397 */ MCD_OPC_CheckPredicate, 30, 88, 18, 0, // Skip to: 17098 +/* 12402 */ MCD_OPC_Decode, 170, 14, 139, 2, // Opcode: FSUNE_D +/* 12407 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 12422 +/* 12412 */ MCD_OPC_CheckPredicate, 30, 73, 18, 0, // Skip to: 17098 +/* 12417 */ MCD_OPC_Decode, 143, 14, 138, 2, // Opcode: FSNE_W +/* 12422 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 12437 +/* 12427 */ MCD_OPC_CheckPredicate, 30, 58, 18, 0, // Skip to: 17098 +/* 12432 */ MCD_OPC_Decode, 142, 14, 139, 2, // Opcode: FSNE_D +/* 12437 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 12452 +/* 12442 */ MCD_OPC_CheckPredicate, 30, 43, 18, 0, // Skip to: 17098 +/* 12447 */ MCD_OPC_Decode, 224, 18, 137, 2, // Opcode: MULR_Q_H +/* 12452 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 12467 +/* 12457 */ MCD_OPC_CheckPredicate, 30, 28, 18, 0, // Skip to: 17098 +/* 12462 */ MCD_OPC_Decode, 225, 18, 138, 2, // Opcode: MULR_Q_W +/* 12467 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 12482 +/* 12472 */ MCD_OPC_CheckPredicate, 30, 13, 18, 0, // Skip to: 17098 +/* 12477 */ MCD_OPC_Decode, 200, 16, 141, 2, // Opcode: MADDR_Q_H +/* 12482 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 12497 +/* 12487 */ MCD_OPC_CheckPredicate, 30, 254, 17, 0, // Skip to: 17098 +/* 12492 */ MCD_OPC_Decode, 201, 16, 142, 2, // Opcode: MADDR_Q_W +/* 12497 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 12512 +/* 12502 */ MCD_OPC_CheckPredicate, 30, 239, 17, 0, // Skip to: 17098 +/* 12507 */ MCD_OPC_Decode, 136, 18, 141, 2, // Opcode: MSUBR_Q_H +/* 12512 */ MCD_OPC_FilterValue, 29, 229, 17, 0, // Skip to: 17098 +/* 12517 */ MCD_OPC_CheckPredicate, 30, 224, 17, 0, // Skip to: 17098 +/* 12522 */ MCD_OPC_Decode, 137, 18, 142, 2, // Opcode: MSUBR_Q_W +/* 12527 */ MCD_OPC_FilterValue, 30, 76, 3, 0, // Skip to: 13376 +/* 12532 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 12535 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12550 +/* 12540 */ MCD_OPC_CheckPredicate, 30, 201, 17, 0, // Skip to: 17098 +/* 12545 */ MCD_OPC_Decode, 230, 6, 136, 2, // Opcode: AND_V +/* 12550 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 12565 +/* 12555 */ MCD_OPC_CheckPredicate, 30, 186, 17, 0, // Skip to: 17098 +/* 12560 */ MCD_OPC_Decode, 174, 19, 136, 2, // Opcode: OR_V +/* 12565 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12580 +/* 12570 */ MCD_OPC_CheckPredicate, 30, 171, 17, 0, // Skip to: 17098 +/* 12575 */ MCD_OPC_Decode, 157, 19, 136, 2, // Opcode: NOR_V +/* 12580 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12595 +/* 12585 */ MCD_OPC_CheckPredicate, 30, 156, 17, 0, // Skip to: 17098 +/* 12590 */ MCD_OPC_Decode, 183, 24, 136, 2, // Opcode: XOR_V +/* 12595 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12610 +/* 12600 */ MCD_OPC_CheckPredicate, 30, 141, 17, 0, // Skip to: 17098 +/* 12605 */ MCD_OPC_Decode, 167, 8, 140, 2, // Opcode: BMNZ_V +/* 12610 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 12625 +/* 12615 */ MCD_OPC_CheckPredicate, 30, 126, 17, 0, // Skip to: 17098 +/* 12620 */ MCD_OPC_Decode, 169, 8, 140, 2, // Opcode: BMZ_V +/* 12625 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 12640 +/* 12630 */ MCD_OPC_CheckPredicate, 30, 111, 17, 0, // Skip to: 17098 +/* 12635 */ MCD_OPC_Decode, 220, 8, 140, 2, // Opcode: BSEL_V +/* 12640 */ MCD_OPC_FilterValue, 24, 243, 0, 0, // Skip to: 12888 +/* 12645 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 12648 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12663 +/* 12653 */ MCD_OPC_CheckPredicate, 30, 88, 17, 0, // Skip to: 17098 +/* 12658 */ MCD_OPC_Decode, 200, 13, 180, 2, // Opcode: FILL_B +/* 12663 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 12678 +/* 12668 */ MCD_OPC_CheckPredicate, 30, 73, 17, 0, // Skip to: 17098 +/* 12673 */ MCD_OPC_Decode, 202, 13, 181, 2, // Opcode: FILL_H +/* 12678 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12693 +/* 12683 */ MCD_OPC_CheckPredicate, 30, 58, 17, 0, // Skip to: 17098 +/* 12688 */ MCD_OPC_Decode, 203, 13, 182, 2, // Opcode: FILL_W +/* 12693 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12708 +/* 12698 */ MCD_OPC_CheckPredicate, 38, 43, 17, 0, // Skip to: 17098 +/* 12703 */ MCD_OPC_Decode, 201, 13, 183, 2, // Opcode: FILL_D +/* 12708 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12723 +/* 12713 */ MCD_OPC_CheckPredicate, 30, 28, 17, 0, // Skip to: 17098 +/* 12718 */ MCD_OPC_Decode, 193, 19, 172, 2, // Opcode: PCNT_B +/* 12723 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 12738 +/* 12728 */ MCD_OPC_CheckPredicate, 30, 13, 17, 0, // Skip to: 17098 +/* 12733 */ MCD_OPC_Decode, 195, 19, 184, 2, // Opcode: PCNT_H +/* 12738 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 12753 +/* 12743 */ MCD_OPC_CheckPredicate, 30, 254, 16, 0, // Skip to: 17098 +/* 12748 */ MCD_OPC_Decode, 196, 19, 185, 2, // Opcode: PCNT_W +/* 12753 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 12768 +/* 12758 */ MCD_OPC_CheckPredicate, 30, 239, 16, 0, // Skip to: 17098 +/* 12763 */ MCD_OPC_Decode, 194, 19, 186, 2, // Opcode: PCNT_D +/* 12768 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 12783 +/* 12773 */ MCD_OPC_CheckPredicate, 30, 224, 16, 0, // Skip to: 17098 +/* 12778 */ MCD_OPC_Decode, 131, 19, 172, 2, // Opcode: NLOC_B +/* 12783 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 12798 +/* 12788 */ MCD_OPC_CheckPredicate, 30, 209, 16, 0, // Skip to: 17098 +/* 12793 */ MCD_OPC_Decode, 133, 19, 184, 2, // Opcode: NLOC_H +/* 12798 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 12813 +/* 12803 */ MCD_OPC_CheckPredicate, 30, 194, 16, 0, // Skip to: 17098 +/* 12808 */ MCD_OPC_Decode, 134, 19, 185, 2, // Opcode: NLOC_W +/* 12813 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 12828 +/* 12818 */ MCD_OPC_CheckPredicate, 30, 179, 16, 0, // Skip to: 17098 +/* 12823 */ MCD_OPC_Decode, 132, 19, 186, 2, // Opcode: NLOC_D +/* 12828 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 12843 +/* 12833 */ MCD_OPC_CheckPredicate, 30, 164, 16, 0, // Skip to: 17098 +/* 12838 */ MCD_OPC_Decode, 135, 19, 172, 2, // Opcode: NLZC_B +/* 12843 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 12858 +/* 12848 */ MCD_OPC_CheckPredicate, 30, 149, 16, 0, // Skip to: 17098 +/* 12853 */ MCD_OPC_Decode, 137, 19, 184, 2, // Opcode: NLZC_H +/* 12858 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 12873 +/* 12863 */ MCD_OPC_CheckPredicate, 30, 134, 16, 0, // Skip to: 17098 +/* 12868 */ MCD_OPC_Decode, 138, 19, 185, 2, // Opcode: NLZC_W +/* 12873 */ MCD_OPC_FilterValue, 15, 124, 16, 0, // Skip to: 17098 +/* 12878 */ MCD_OPC_CheckPredicate, 30, 119, 16, 0, // Skip to: 17098 +/* 12883 */ MCD_OPC_Decode, 136, 19, 186, 2, // Opcode: NLZC_D +/* 12888 */ MCD_OPC_FilterValue, 25, 109, 16, 0, // Skip to: 17098 +/* 12893 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 12896 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12911 +/* 12901 */ MCD_OPC_CheckPredicate, 30, 96, 16, 0, // Skip to: 17098 +/* 12906 */ MCD_OPC_Decode, 151, 13, 185, 2, // Opcode: FCLASS_W +/* 12911 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 12926 +/* 12916 */ MCD_OPC_CheckPredicate, 30, 81, 16, 0, // Skip to: 17098 +/* 12921 */ MCD_OPC_Decode, 150, 13, 186, 2, // Opcode: FCLASS_D +/* 12926 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12941 +/* 12931 */ MCD_OPC_CheckPredicate, 30, 66, 16, 0, // Skip to: 17098 +/* 12936 */ MCD_OPC_Decode, 181, 14, 185, 2, // Opcode: FTRUNC_S_W +/* 12941 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12956 +/* 12946 */ MCD_OPC_CheckPredicate, 30, 51, 16, 0, // Skip to: 17098 +/* 12951 */ MCD_OPC_Decode, 180, 14, 186, 2, // Opcode: FTRUNC_S_D +/* 12956 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12971 +/* 12961 */ MCD_OPC_CheckPredicate, 30, 36, 16, 0, // Skip to: 17098 +/* 12966 */ MCD_OPC_Decode, 183, 14, 185, 2, // Opcode: FTRUNC_U_W +/* 12971 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 12986 +/* 12976 */ MCD_OPC_CheckPredicate, 30, 21, 16, 0, // Skip to: 17098 +/* 12981 */ MCD_OPC_Decode, 182, 14, 186, 2, // Opcode: FTRUNC_U_D +/* 12986 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 13001 +/* 12991 */ MCD_OPC_CheckPredicate, 30, 6, 16, 0, // Skip to: 17098 +/* 12996 */ MCD_OPC_Decode, 153, 14, 185, 2, // Opcode: FSQRT_W +/* 13001 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 13016 +/* 13006 */ MCD_OPC_CheckPredicate, 30, 247, 15, 0, // Skip to: 17098 +/* 13011 */ MCD_OPC_Decode, 146, 14, 186, 2, // Opcode: FSQRT_D +/* 13016 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 13031 +/* 13021 */ MCD_OPC_CheckPredicate, 30, 232, 15, 0, // Skip to: 17098 +/* 13026 */ MCD_OPC_Decode, 133, 14, 185, 2, // Opcode: FRSQRT_W +/* 13031 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 13046 +/* 13036 */ MCD_OPC_CheckPredicate, 30, 217, 15, 0, // Skip to: 17098 +/* 13041 */ MCD_OPC_Decode, 132, 14, 186, 2, // Opcode: FRSQRT_D +/* 13046 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 13061 +/* 13051 */ MCD_OPC_CheckPredicate, 30, 202, 15, 0, // Skip to: 17098 +/* 13056 */ MCD_OPC_Decode, 129, 14, 185, 2, // Opcode: FRCP_W +/* 13061 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 13076 +/* 13066 */ MCD_OPC_CheckPredicate, 30, 187, 15, 0, // Skip to: 17098 +/* 13071 */ MCD_OPC_Decode, 128, 14, 186, 2, // Opcode: FRCP_D +/* 13076 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 13091 +/* 13081 */ MCD_OPC_CheckPredicate, 30, 172, 15, 0, // Skip to: 17098 +/* 13086 */ MCD_OPC_Decode, 131, 14, 185, 2, // Opcode: FRINT_W +/* 13091 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 13106 +/* 13096 */ MCD_OPC_CheckPredicate, 30, 157, 15, 0, // Skip to: 17098 +/* 13101 */ MCD_OPC_Decode, 130, 14, 186, 2, // Opcode: FRINT_D +/* 13106 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 13121 +/* 13111 */ MCD_OPC_CheckPredicate, 30, 142, 15, 0, // Skip to: 17098 +/* 13116 */ MCD_OPC_Decode, 205, 13, 185, 2, // Opcode: FLOG2_W +/* 13121 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 13136 +/* 13126 */ MCD_OPC_CheckPredicate, 30, 127, 15, 0, // Skip to: 17098 +/* 13131 */ MCD_OPC_Decode, 204, 13, 186, 2, // Opcode: FLOG2_D +/* 13136 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 13151 +/* 13141 */ MCD_OPC_CheckPredicate, 30, 112, 15, 0, // Skip to: 17098 +/* 13146 */ MCD_OPC_Decode, 189, 13, 187, 2, // Opcode: FEXUPL_W +/* 13151 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 13166 +/* 13156 */ MCD_OPC_CheckPredicate, 30, 97, 15, 0, // Skip to: 17098 +/* 13161 */ MCD_OPC_Decode, 188, 13, 188, 2, // Opcode: FEXUPL_D +/* 13166 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 13181 +/* 13171 */ MCD_OPC_CheckPredicate, 30, 82, 15, 0, // Skip to: 17098 +/* 13176 */ MCD_OPC_Decode, 191, 13, 187, 2, // Opcode: FEXUPR_W +/* 13181 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 13196 +/* 13186 */ MCD_OPC_CheckPredicate, 30, 67, 15, 0, // Skip to: 17098 +/* 13191 */ MCD_OPC_Decode, 190, 13, 188, 2, // Opcode: FEXUPR_D +/* 13196 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 13211 +/* 13201 */ MCD_OPC_CheckPredicate, 30, 52, 15, 0, // Skip to: 17098 +/* 13206 */ MCD_OPC_Decode, 197, 13, 187, 2, // Opcode: FFQL_W +/* 13211 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 13226 +/* 13216 */ MCD_OPC_CheckPredicate, 30, 37, 15, 0, // Skip to: 17098 +/* 13221 */ MCD_OPC_Decode, 196, 13, 188, 2, // Opcode: FFQL_D +/* 13226 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 13241 +/* 13231 */ MCD_OPC_CheckPredicate, 30, 22, 15, 0, // Skip to: 17098 +/* 13236 */ MCD_OPC_Decode, 199, 13, 187, 2, // Opcode: FFQR_W +/* 13241 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 13256 +/* 13246 */ MCD_OPC_CheckPredicate, 30, 7, 15, 0, // Skip to: 17098 +/* 13251 */ MCD_OPC_Decode, 198, 13, 188, 2, // Opcode: FFQR_D +/* 13256 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 13271 +/* 13261 */ MCD_OPC_CheckPredicate, 30, 248, 14, 0, // Skip to: 17098 +/* 13266 */ MCD_OPC_Decode, 175, 14, 185, 2, // Opcode: FTINT_S_W +/* 13271 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 13286 +/* 13276 */ MCD_OPC_CheckPredicate, 30, 233, 14, 0, // Skip to: 17098 +/* 13281 */ MCD_OPC_Decode, 174, 14, 186, 2, // Opcode: FTINT_S_D +/* 13286 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 13301 +/* 13291 */ MCD_OPC_CheckPredicate, 30, 218, 14, 0, // Skip to: 17098 +/* 13296 */ MCD_OPC_Decode, 177, 14, 185, 2, // Opcode: FTINT_U_W +/* 13301 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 13316 +/* 13306 */ MCD_OPC_CheckPredicate, 30, 203, 14, 0, // Skip to: 17098 +/* 13311 */ MCD_OPC_Decode, 176, 14, 186, 2, // Opcode: FTINT_U_D +/* 13316 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 13331 +/* 13321 */ MCD_OPC_CheckPredicate, 30, 188, 14, 0, // Skip to: 17098 +/* 13326 */ MCD_OPC_Decode, 193, 13, 185, 2, // Opcode: FFINT_S_W +/* 13331 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 13346 +/* 13336 */ MCD_OPC_CheckPredicate, 30, 173, 14, 0, // Skip to: 17098 +/* 13341 */ MCD_OPC_Decode, 192, 13, 186, 2, // Opcode: FFINT_S_D +/* 13346 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 13361 +/* 13351 */ MCD_OPC_CheckPredicate, 30, 158, 14, 0, // Skip to: 17098 +/* 13356 */ MCD_OPC_Decode, 195, 13, 185, 2, // Opcode: FFINT_U_W +/* 13361 */ MCD_OPC_FilterValue, 31, 148, 14, 0, // Skip to: 17098 +/* 13366 */ MCD_OPC_CheckPredicate, 30, 143, 14, 0, // Skip to: 17098 +/* 13371 */ MCD_OPC_Decode, 194, 13, 186, 2, // Opcode: FFINT_U_D +/* 13376 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 13391 +/* 13381 */ MCD_OPC_CheckPredicate, 30, 128, 14, 0, // Skip to: 17098 +/* 13386 */ MCD_OPC_Decode, 198, 15, 189, 2, // Opcode: LD_B +/* 13391 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 13406 +/* 13396 */ MCD_OPC_CheckPredicate, 30, 113, 14, 0, // Skip to: 17098 +/* 13401 */ MCD_OPC_Decode, 200, 15, 189, 2, // Opcode: LD_H +/* 13406 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 13421 +/* 13411 */ MCD_OPC_CheckPredicate, 30, 98, 14, 0, // Skip to: 17098 +/* 13416 */ MCD_OPC_Decode, 201, 15, 189, 2, // Opcode: LD_W +/* 13421 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 13436 +/* 13426 */ MCD_OPC_CheckPredicate, 30, 83, 14, 0, // Skip to: 17098 +/* 13431 */ MCD_OPC_Decode, 199, 15, 189, 2, // Opcode: LD_D +/* 13436 */ MCD_OPC_FilterValue, 36, 10, 0, 0, // Skip to: 13451 +/* 13441 */ MCD_OPC_CheckPredicate, 30, 68, 14, 0, // Skip to: 17098 +/* 13446 */ MCD_OPC_Decode, 188, 22, 189, 2, // Opcode: ST_B +/* 13451 */ MCD_OPC_FilterValue, 37, 10, 0, 0, // Skip to: 13466 +/* 13456 */ MCD_OPC_CheckPredicate, 30, 53, 14, 0, // Skip to: 17098 +/* 13461 */ MCD_OPC_Decode, 190, 22, 189, 2, // Opcode: ST_H +/* 13466 */ MCD_OPC_FilterValue, 38, 10, 0, 0, // Skip to: 13481 +/* 13471 */ MCD_OPC_CheckPredicate, 30, 38, 14, 0, // Skip to: 17098 +/* 13476 */ MCD_OPC_Decode, 191, 22, 189, 2, // Opcode: ST_W +/* 13481 */ MCD_OPC_FilterValue, 39, 28, 14, 0, // Skip to: 17098 +/* 13486 */ MCD_OPC_CheckPredicate, 30, 23, 14, 0, // Skip to: 17098 +/* 13491 */ MCD_OPC_Decode, 189, 22, 189, 2, // Opcode: ST_D +/* 13496 */ MCD_OPC_FilterValue, 31, 165, 12, 0, // Skip to: 16738 +/* 13501 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 13504 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13519 +/* 13509 */ MCD_OPC_CheckPredicate, 28, 0, 14, 0, // Skip to: 17098 +/* 13514 */ MCD_OPC_Decode, 227, 12, 190, 2, // Opcode: EXT +/* 13519 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 13534 +/* 13524 */ MCD_OPC_CheckPredicate, 28, 241, 13, 0, // Skip to: 17098 +/* 13529 */ MCD_OPC_Decode, 220, 14, 191, 2, // Opcode: INS +/* 13534 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 13556 +/* 13539 */ MCD_OPC_CheckPredicate, 42, 226, 13, 0, // Skip to: 17098 +/* 13544 */ MCD_OPC_CheckField, 6, 5, 0, 219, 13, 0, // Skip to: 17098 +/* 13551 */ MCD_OPC_Decode, 254, 13, 192, 2, // Opcode: FORK +/* 13556 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 13584 +/* 13561 */ MCD_OPC_CheckPredicate, 42, 204, 13, 0, // Skip to: 17098 +/* 13566 */ MCD_OPC_CheckField, 16, 5, 0, 197, 13, 0, // Skip to: 17098 +/* 13573 */ MCD_OPC_CheckField, 6, 5, 0, 190, 13, 0, // Skip to: 17098 +/* 13580 */ MCD_OPC_Decode, 188, 24, 25, // Opcode: YIELD +/* 13584 */ MCD_OPC_FilterValue, 10, 48, 0, 0, // Skip to: 13637 +/* 13589 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 13592 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13607 +/* 13597 */ MCD_OPC_CheckPredicate, 37, 168, 13, 0, // Skip to: 17098 +/* 13602 */ MCD_OPC_Decode, 171, 16, 193, 2, // Opcode: LWX +/* 13607 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 13622 +/* 13612 */ MCD_OPC_CheckPredicate, 37, 153, 13, 0, // Skip to: 17098 +/* 13617 */ MCD_OPC_Decode, 219, 15, 193, 2, // Opcode: LHX +/* 13622 */ MCD_OPC_FilterValue, 6, 143, 13, 0, // Skip to: 17098 +/* 13627 */ MCD_OPC_CheckPredicate, 37, 138, 13, 0, // Skip to: 17098 +/* 13632 */ MCD_OPC_Decode, 163, 15, 193, 2, // Opcode: LBUX +/* 13637 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 13659 +/* 13642 */ MCD_OPC_CheckPredicate, 37, 123, 13, 0, // Skip to: 17098 +/* 13647 */ MCD_OPC_CheckField, 6, 10, 0, 116, 13, 0, // Skip to: 17098 +/* 13654 */ MCD_OPC_Decode, 225, 14, 194, 2, // Opcode: INSV +/* 13659 */ MCD_OPC_FilterValue, 16, 109, 1, 0, // Skip to: 14029 +/* 13664 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 13667 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13682 +/* 13672 */ MCD_OPC_CheckPredicate, 37, 93, 13, 0, // Skip to: 17098 +/* 13677 */ MCD_OPC_Decode, 179, 6, 195, 2, // Opcode: ADDU_QB +/* 13682 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 13697 +/* 13687 */ MCD_OPC_CheckPredicate, 37, 78, 13, 0, // Skip to: 17098 +/* 13692 */ MCD_OPC_Decode, 232, 22, 195, 2, // Opcode: SUBU_QB +/* 13697 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 13712 +/* 13702 */ MCD_OPC_CheckPredicate, 37, 63, 13, 0, // Skip to: 17098 +/* 13707 */ MCD_OPC_Decode, 183, 6, 195, 2, // Opcode: ADDU_S_QB +/* 13712 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 13727 +/* 13717 */ MCD_OPC_CheckPredicate, 37, 48, 13, 0, // Skip to: 17098 +/* 13722 */ MCD_OPC_Decode, 236, 22, 195, 2, // Opcode: SUBU_S_QB +/* 13727 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 13742 +/* 13732 */ MCD_OPC_CheckPredicate, 37, 33, 13, 0, // Skip to: 17098 +/* 13737 */ MCD_OPC_Decode, 211, 18, 195, 2, // Opcode: MULEU_S_PH_QBL +/* 13742 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 13757 +/* 13747 */ MCD_OPC_CheckPredicate, 37, 18, 13, 0, // Skip to: 17098 +/* 13752 */ MCD_OPC_Decode, 213, 18, 195, 2, // Opcode: MULEU_S_PH_QBR +/* 13757 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 13772 +/* 13762 */ MCD_OPC_CheckPredicate, 69, 3, 13, 0, // Skip to: 17098 +/* 13767 */ MCD_OPC_Decode, 177, 6, 195, 2, // Opcode: ADDU_PH +/* 13772 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 13787 +/* 13777 */ MCD_OPC_CheckPredicate, 69, 244, 12, 0, // Skip to: 17098 +/* 13782 */ MCD_OPC_Decode, 230, 22, 195, 2, // Opcode: SUBU_PH +/* 13787 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 13802 +/* 13792 */ MCD_OPC_CheckPredicate, 37, 229, 12, 0, // Skip to: 17098 +/* 13797 */ MCD_OPC_Decode, 149, 6, 195, 2, // Opcode: ADDQ_PH +/* 13802 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 13817 +/* 13807 */ MCD_OPC_CheckPredicate, 37, 214, 12, 0, // Skip to: 17098 +/* 13812 */ MCD_OPC_Decode, 201, 22, 195, 2, // Opcode: SUBQ_PH +/* 13817 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 13832 +/* 13822 */ MCD_OPC_CheckPredicate, 69, 199, 12, 0, // Skip to: 17098 +/* 13827 */ MCD_OPC_Decode, 181, 6, 195, 2, // Opcode: ADDU_S_PH +/* 13832 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 13847 +/* 13837 */ MCD_OPC_CheckPredicate, 69, 184, 12, 0, // Skip to: 17098 +/* 13842 */ MCD_OPC_Decode, 234, 22, 195, 2, // Opcode: SUBU_S_PH +/* 13847 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 13862 +/* 13852 */ MCD_OPC_CheckPredicate, 37, 169, 12, 0, // Skip to: 17098 +/* 13857 */ MCD_OPC_Decode, 151, 6, 195, 2, // Opcode: ADDQ_S_PH +/* 13862 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 13877 +/* 13867 */ MCD_OPC_CheckPredicate, 37, 154, 12, 0, // Skip to: 17098 +/* 13872 */ MCD_OPC_Decode, 203, 22, 195, 2, // Opcode: SUBQ_S_PH +/* 13877 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 13891 +/* 13882 */ MCD_OPC_CheckPredicate, 37, 139, 12, 0, // Skip to: 17098 +/* 13887 */ MCD_OPC_Decode, 156, 6, 61, // Opcode: ADDSC +/* 13891 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 13905 +/* 13896 */ MCD_OPC_CheckPredicate, 37, 125, 12, 0, // Skip to: 17098 +/* 13901 */ MCD_OPC_Decode, 193, 6, 61, // Opcode: ADDWC +/* 13905 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 13919 +/* 13910 */ MCD_OPC_CheckPredicate, 37, 111, 12, 0, // Skip to: 17098 +/* 13915 */ MCD_OPC_Decode, 193, 17, 61, // Opcode: MODSUB +/* 13919 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 13941 +/* 13924 */ MCD_OPC_CheckPredicate, 37, 97, 12, 0, // Skip to: 17098 +/* 13929 */ MCD_OPC_CheckField, 16, 5, 0, 90, 12, 0, // Skip to: 17098 +/* 13936 */ MCD_OPC_Decode, 251, 19, 196, 2, // Opcode: RADDU_W_QB +/* 13941 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 13955 +/* 13946 */ MCD_OPC_CheckPredicate, 37, 75, 12, 0, // Skip to: 17098 +/* 13951 */ MCD_OPC_Decode, 153, 6, 61, // Opcode: ADDQ_S_W +/* 13955 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 13969 +/* 13960 */ MCD_OPC_CheckPredicate, 37, 61, 12, 0, // Skip to: 17098 +/* 13965 */ MCD_OPC_Decode, 205, 22, 61, // Opcode: SUBQ_S_W +/* 13969 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 13984 +/* 13974 */ MCD_OPC_CheckPredicate, 37, 47, 12, 0, // Skip to: 17098 +/* 13979 */ MCD_OPC_Decode, 207, 18, 197, 2, // Opcode: MULEQ_S_W_PHL +/* 13984 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 13999 +/* 13989 */ MCD_OPC_CheckPredicate, 37, 32, 12, 0, // Skip to: 17098 +/* 13994 */ MCD_OPC_Decode, 209, 18, 197, 2, // Opcode: MULEQ_S_W_PHR +/* 13999 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 14014 +/* 14004 */ MCD_OPC_CheckPredicate, 69, 17, 12, 0, // Skip to: 17098 +/* 14009 */ MCD_OPC_Decode, 219, 18, 195, 2, // Opcode: MULQ_S_PH +/* 14014 */ MCD_OPC_FilterValue, 31, 7, 12, 0, // Skip to: 17098 +/* 14019 */ MCD_OPC_CheckPredicate, 37, 2, 12, 0, // Skip to: 17098 +/* 14024 */ MCD_OPC_Decode, 215, 18, 195, 2, // Opcode: MULQ_RS_PH +/* 14029 */ MCD_OPC_FilterValue, 17, 113, 1, 0, // Skip to: 14403 +/* 14034 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 14037 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 14058 +/* 14042 */ MCD_OPC_CheckPredicate, 37, 235, 11, 0, // Skip to: 17098 +/* 14047 */ MCD_OPC_CheckField, 11, 5, 0, 228, 11, 0, // Skip to: 17098 +/* 14054 */ MCD_OPC_Decode, 210, 9, 79, // Opcode: CMPU_EQ_QB +/* 14058 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 14079 +/* 14063 */ MCD_OPC_CheckPredicate, 37, 214, 11, 0, // Skip to: 17098 +/* 14068 */ MCD_OPC_CheckField, 11, 5, 0, 207, 11, 0, // Skip to: 17098 +/* 14075 */ MCD_OPC_Decode, 214, 9, 79, // Opcode: CMPU_LT_QB +/* 14079 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 14100 +/* 14084 */ MCD_OPC_CheckPredicate, 37, 193, 11, 0, // Skip to: 17098 +/* 14089 */ MCD_OPC_CheckField, 11, 5, 0, 186, 11, 0, // Skip to: 17098 +/* 14096 */ MCD_OPC_Decode, 212, 9, 79, // Opcode: CMPU_LE_QB +/* 14100 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 14115 +/* 14105 */ MCD_OPC_CheckPredicate, 37, 172, 11, 0, // Skip to: 17098 +/* 14110 */ MCD_OPC_Decode, 199, 19, 195, 2, // Opcode: PICK_QB +/* 14115 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 14130 +/* 14120 */ MCD_OPC_CheckPredicate, 37, 157, 11, 0, // Skip to: 17098 +/* 14125 */ MCD_OPC_Decode, 204, 9, 197, 2, // Opcode: CMPGU_EQ_QB +/* 14130 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 14145 +/* 14135 */ MCD_OPC_CheckPredicate, 37, 142, 11, 0, // Skip to: 17098 +/* 14140 */ MCD_OPC_Decode, 208, 9, 197, 2, // Opcode: CMPGU_LT_QB +/* 14145 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 14160 +/* 14150 */ MCD_OPC_CheckPredicate, 37, 127, 11, 0, // Skip to: 17098 +/* 14155 */ MCD_OPC_Decode, 206, 9, 197, 2, // Opcode: CMPGU_LE_QB +/* 14160 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 14181 +/* 14165 */ MCD_OPC_CheckPredicate, 37, 112, 11, 0, // Skip to: 17098 +/* 14170 */ MCD_OPC_CheckField, 11, 5, 0, 105, 11, 0, // Skip to: 17098 +/* 14177 */ MCD_OPC_Decode, 220, 9, 79, // Opcode: CMP_EQ_PH +/* 14181 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 14202 +/* 14186 */ MCD_OPC_CheckPredicate, 37, 91, 11, 0, // Skip to: 17098 +/* 14191 */ MCD_OPC_CheckField, 11, 5, 0, 84, 11, 0, // Skip to: 17098 +/* 14198 */ MCD_OPC_Decode, 234, 9, 79, // Opcode: CMP_LT_PH +/* 14202 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 14223 +/* 14207 */ MCD_OPC_CheckPredicate, 37, 70, 11, 0, // Skip to: 17098 +/* 14212 */ MCD_OPC_CheckField, 11, 5, 0, 63, 11, 0, // Skip to: 17098 +/* 14219 */ MCD_OPC_Decode, 228, 9, 79, // Opcode: CMP_LE_PH +/* 14223 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 14238 +/* 14228 */ MCD_OPC_CheckPredicate, 37, 49, 11, 0, // Skip to: 17098 +/* 14233 */ MCD_OPC_Decode, 197, 19, 195, 2, // Opcode: PICK_PH +/* 14238 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 14253 +/* 14243 */ MCD_OPC_CheckPredicate, 37, 34, 11, 0, // Skip to: 17098 +/* 14248 */ MCD_OPC_Decode, 228, 19, 195, 2, // Opcode: PRECRQ_QB_PH +/* 14253 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 14268 +/* 14258 */ MCD_OPC_CheckPredicate, 69, 19, 11, 0, // Skip to: 17098 +/* 14263 */ MCD_OPC_Decode, 232, 19, 195, 2, // Opcode: PRECR_QB_PH +/* 14268 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 14283 +/* 14273 */ MCD_OPC_CheckPredicate, 37, 4, 11, 0, // Skip to: 17098 +/* 14278 */ MCD_OPC_Decode, 179, 19, 195, 2, // Opcode: PACKRL_PH +/* 14283 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 14298 +/* 14288 */ MCD_OPC_CheckPredicate, 37, 245, 10, 0, // Skip to: 17098 +/* 14293 */ MCD_OPC_Decode, 224, 19, 195, 2, // Opcode: PRECRQU_S_QB_PH +/* 14298 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 14313 +/* 14303 */ MCD_OPC_CheckPredicate, 37, 230, 10, 0, // Skip to: 17098 +/* 14308 */ MCD_OPC_Decode, 226, 19, 198, 2, // Opcode: PRECRQ_PH_W +/* 14313 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 14328 +/* 14318 */ MCD_OPC_CheckPredicate, 37, 215, 10, 0, // Skip to: 17098 +/* 14323 */ MCD_OPC_Decode, 230, 19, 198, 2, // Opcode: PRECRQ_RS_PH_W +/* 14328 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 14343 +/* 14333 */ MCD_OPC_CheckPredicate, 69, 200, 10, 0, // Skip to: 17098 +/* 14338 */ MCD_OPC_Decode, 198, 9, 197, 2, // Opcode: CMPGDU_EQ_QB +/* 14343 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 14358 +/* 14348 */ MCD_OPC_CheckPredicate, 69, 185, 10, 0, // Skip to: 17098 +/* 14353 */ MCD_OPC_Decode, 202, 9, 197, 2, // Opcode: CMPGDU_LT_QB +/* 14358 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 14373 +/* 14363 */ MCD_OPC_CheckPredicate, 69, 170, 10, 0, // Skip to: 17098 +/* 14368 */ MCD_OPC_Decode, 200, 9, 197, 2, // Opcode: CMPGDU_LE_QB +/* 14373 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 14388 +/* 14378 */ MCD_OPC_CheckPredicate, 69, 155, 10, 0, // Skip to: 17098 +/* 14383 */ MCD_OPC_Decode, 234, 19, 199, 2, // Opcode: PRECR_SRA_PH_W +/* 14388 */ MCD_OPC_FilterValue, 31, 145, 10, 0, // Skip to: 17098 +/* 14393 */ MCD_OPC_CheckPredicate, 69, 140, 10, 0, // Skip to: 17098 +/* 14398 */ MCD_OPC_Decode, 236, 19, 199, 2, // Opcode: PRECR_SRA_R_PH_W +/* 14403 */ MCD_OPC_FilterValue, 18, 128, 1, 0, // Skip to: 14792 +/* 14408 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 14411 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14433 +/* 14416 */ MCD_OPC_CheckPredicate, 69, 117, 10, 0, // Skip to: 17098 +/* 14421 */ MCD_OPC_CheckField, 21, 5, 0, 110, 10, 0, // Skip to: 17098 +/* 14428 */ MCD_OPC_Decode, 247, 5, 200, 2, // Opcode: ABSQ_S_QB +/* 14433 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 14448 +/* 14438 */ MCD_OPC_CheckPredicate, 37, 95, 10, 0, // Skip to: 17098 +/* 14443 */ MCD_OPC_Decode, 146, 20, 201, 2, // Opcode: REPL_QB +/* 14448 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 14470 +/* 14453 */ MCD_OPC_CheckPredicate, 37, 80, 10, 0, // Skip to: 17098 +/* 14458 */ MCD_OPC_CheckField, 21, 5, 0, 73, 10, 0, // Skip to: 17098 +/* 14465 */ MCD_OPC_Decode, 142, 20, 202, 2, // Opcode: REPLV_QB +/* 14470 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 14492 +/* 14475 */ MCD_OPC_CheckPredicate, 37, 58, 10, 0, // Skip to: 17098 +/* 14480 */ MCD_OPC_CheckField, 21, 5, 0, 51, 10, 0, // Skip to: 17098 +/* 14487 */ MCD_OPC_Decode, 204, 19, 200, 2, // Opcode: PRECEQU_PH_QBL +/* 14492 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 14514 +/* 14497 */ MCD_OPC_CheckPredicate, 37, 36, 10, 0, // Skip to: 17098 +/* 14502 */ MCD_OPC_CheckField, 21, 5, 0, 29, 10, 0, // Skip to: 17098 +/* 14509 */ MCD_OPC_Decode, 208, 19, 200, 2, // Opcode: PRECEQU_PH_QBR +/* 14514 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 14536 +/* 14519 */ MCD_OPC_CheckPredicate, 37, 14, 10, 0, // Skip to: 17098 +/* 14524 */ MCD_OPC_CheckField, 21, 5, 0, 7, 10, 0, // Skip to: 17098 +/* 14531 */ MCD_OPC_Decode, 205, 19, 200, 2, // Opcode: PRECEQU_PH_QBLA +/* 14536 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 14558 +/* 14541 */ MCD_OPC_CheckPredicate, 37, 248, 9, 0, // Skip to: 17098 +/* 14546 */ MCD_OPC_CheckField, 21, 5, 0, 241, 9, 0, // Skip to: 17098 +/* 14553 */ MCD_OPC_Decode, 209, 19, 200, 2, // Opcode: PRECEQU_PH_QBRA +/* 14558 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 14580 +/* 14563 */ MCD_OPC_CheckPredicate, 37, 226, 9, 0, // Skip to: 17098 +/* 14568 */ MCD_OPC_CheckField, 21, 5, 0, 219, 9, 0, // Skip to: 17098 +/* 14575 */ MCD_OPC_Decode, 245, 5, 200, 2, // Opcode: ABSQ_S_PH +/* 14580 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 14594 +/* 14585 */ MCD_OPC_CheckPredicate, 37, 204, 9, 0, // Skip to: 17098 +/* 14590 */ MCD_OPC_Decode, 144, 20, 96, // Opcode: REPL_PH +/* 14594 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 14616 +/* 14599 */ MCD_OPC_CheckPredicate, 37, 190, 9, 0, // Skip to: 17098 +/* 14604 */ MCD_OPC_CheckField, 21, 5, 0, 183, 9, 0, // Skip to: 17098 +/* 14611 */ MCD_OPC_Decode, 140, 20, 202, 2, // Opcode: REPLV_PH +/* 14616 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 14638 +/* 14621 */ MCD_OPC_CheckPredicate, 37, 168, 9, 0, // Skip to: 17098 +/* 14626 */ MCD_OPC_CheckField, 21, 5, 0, 161, 9, 0, // Skip to: 17098 +/* 14633 */ MCD_OPC_Decode, 212, 19, 203, 2, // Opcode: PRECEQ_W_PHL +/* 14638 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 14660 +/* 14643 */ MCD_OPC_CheckPredicate, 37, 146, 9, 0, // Skip to: 17098 +/* 14648 */ MCD_OPC_CheckField, 21, 5, 0, 139, 9, 0, // Skip to: 17098 +/* 14655 */ MCD_OPC_Decode, 214, 19, 203, 2, // Opcode: PRECEQ_W_PHR +/* 14660 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 14682 +/* 14665 */ MCD_OPC_CheckPredicate, 37, 124, 9, 0, // Skip to: 17098 +/* 14670 */ MCD_OPC_CheckField, 21, 5, 0, 117, 9, 0, // Skip to: 17098 +/* 14677 */ MCD_OPC_Decode, 249, 5, 204, 2, // Opcode: ABSQ_S_W +/* 14682 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 14704 +/* 14687 */ MCD_OPC_CheckPredicate, 37, 102, 9, 0, // Skip to: 17098 +/* 14692 */ MCD_OPC_CheckField, 21, 5, 0, 95, 9, 0, // Skip to: 17098 +/* 14699 */ MCD_OPC_Decode, 129, 8, 204, 2, // Opcode: BITREV +/* 14704 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 14726 +/* 14709 */ MCD_OPC_CheckPredicate, 37, 80, 9, 0, // Skip to: 17098 +/* 14714 */ MCD_OPC_CheckField, 21, 5, 0, 73, 9, 0, // Skip to: 17098 +/* 14721 */ MCD_OPC_Decode, 216, 19, 200, 2, // Opcode: PRECEU_PH_QBL +/* 14726 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 14748 +/* 14731 */ MCD_OPC_CheckPredicate, 37, 58, 9, 0, // Skip to: 17098 +/* 14736 */ MCD_OPC_CheckField, 21, 5, 0, 51, 9, 0, // Skip to: 17098 +/* 14743 */ MCD_OPC_Decode, 220, 19, 200, 2, // Opcode: PRECEU_PH_QBR +/* 14748 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 14770 +/* 14753 */ MCD_OPC_CheckPredicate, 37, 36, 9, 0, // Skip to: 17098 +/* 14758 */ MCD_OPC_CheckField, 21, 5, 0, 29, 9, 0, // Skip to: 17098 +/* 14765 */ MCD_OPC_Decode, 217, 19, 200, 2, // Opcode: PRECEU_PH_QBLA +/* 14770 */ MCD_OPC_FilterValue, 31, 19, 9, 0, // Skip to: 17098 +/* 14775 */ MCD_OPC_CheckPredicate, 37, 14, 9, 0, // Skip to: 17098 +/* 14780 */ MCD_OPC_CheckField, 21, 5, 0, 7, 9, 0, // Skip to: 17098 +/* 14787 */ MCD_OPC_Decode, 221, 19, 200, 2, // Opcode: PRECEU_PH_QBRA +/* 14792 */ MCD_OPC_FilterValue, 19, 75, 1, 0, // Skip to: 15128 +/* 14797 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 14800 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14815 +/* 14805 */ MCD_OPC_CheckPredicate, 37, 240, 8, 0, // Skip to: 17098 +/* 14810 */ MCD_OPC_Decode, 168, 21, 205, 2, // Opcode: SHLL_QB +/* 14815 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 14830 +/* 14820 */ MCD_OPC_CheckPredicate, 37, 225, 8, 0, // Skip to: 17098 +/* 14825 */ MCD_OPC_Decode, 200, 21, 205, 2, // Opcode: SHRL_QB +/* 14830 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 14845 +/* 14835 */ MCD_OPC_CheckPredicate, 37, 210, 8, 0, // Skip to: 17098 +/* 14840 */ MCD_OPC_Decode, 160, 21, 206, 2, // Opcode: SHLLV_QB +/* 14845 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 14860 +/* 14850 */ MCD_OPC_CheckPredicate, 37, 195, 8, 0, // Skip to: 17098 +/* 14855 */ MCD_OPC_Decode, 196, 21, 206, 2, // Opcode: SHRLV_QB +/* 14860 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 14875 +/* 14865 */ MCD_OPC_CheckPredicate, 69, 180, 8, 0, // Skip to: 17098 +/* 14870 */ MCD_OPC_Decode, 186, 21, 205, 2, // Opcode: SHRA_QB +/* 14875 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 14890 +/* 14880 */ MCD_OPC_CheckPredicate, 69, 165, 8, 0, // Skip to: 17098 +/* 14885 */ MCD_OPC_Decode, 190, 21, 205, 2, // Opcode: SHRA_R_QB +/* 14890 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 14905 +/* 14895 */ MCD_OPC_CheckPredicate, 69, 150, 8, 0, // Skip to: 17098 +/* 14900 */ MCD_OPC_Decode, 176, 21, 206, 2, // Opcode: SHRAV_QB +/* 14905 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 14920 +/* 14910 */ MCD_OPC_CheckPredicate, 69, 135, 8, 0, // Skip to: 17098 +/* 14915 */ MCD_OPC_Decode, 180, 21, 206, 2, // Opcode: SHRAV_R_QB +/* 14920 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 14935 +/* 14925 */ MCD_OPC_CheckPredicate, 37, 120, 8, 0, // Skip to: 17098 +/* 14930 */ MCD_OPC_Decode, 166, 21, 205, 2, // Opcode: SHLL_PH +/* 14935 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 14950 +/* 14940 */ MCD_OPC_CheckPredicate, 37, 105, 8, 0, // Skip to: 17098 +/* 14945 */ MCD_OPC_Decode, 184, 21, 205, 2, // Opcode: SHRA_PH +/* 14950 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 14965 +/* 14955 */ MCD_OPC_CheckPredicate, 37, 90, 8, 0, // Skip to: 17098 +/* 14960 */ MCD_OPC_Decode, 158, 21, 206, 2, // Opcode: SHLLV_PH +/* 14965 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 14980 +/* 14970 */ MCD_OPC_CheckPredicate, 37, 75, 8, 0, // Skip to: 17098 +/* 14975 */ MCD_OPC_Decode, 174, 21, 206, 2, // Opcode: SHRAV_PH +/* 14980 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 14995 +/* 14985 */ MCD_OPC_CheckPredicate, 37, 60, 8, 0, // Skip to: 17098 +/* 14990 */ MCD_OPC_Decode, 170, 21, 205, 2, // Opcode: SHLL_S_PH +/* 14995 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 15010 +/* 15000 */ MCD_OPC_CheckPredicate, 37, 45, 8, 0, // Skip to: 17098 +/* 15005 */ MCD_OPC_Decode, 188, 21, 205, 2, // Opcode: SHRA_R_PH +/* 15010 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 15025 +/* 15015 */ MCD_OPC_CheckPredicate, 37, 30, 8, 0, // Skip to: 17098 +/* 15020 */ MCD_OPC_Decode, 162, 21, 206, 2, // Opcode: SHLLV_S_PH +/* 15025 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 15040 +/* 15030 */ MCD_OPC_CheckPredicate, 37, 15, 8, 0, // Skip to: 17098 +/* 15035 */ MCD_OPC_Decode, 178, 21, 206, 2, // Opcode: SHRAV_R_PH +/* 15040 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 15055 +/* 15045 */ MCD_OPC_CheckPredicate, 37, 0, 8, 0, // Skip to: 17098 +/* 15050 */ MCD_OPC_Decode, 172, 21, 207, 2, // Opcode: SHLL_S_W +/* 15055 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 15070 +/* 15060 */ MCD_OPC_CheckPredicate, 37, 241, 7, 0, // Skip to: 17098 +/* 15065 */ MCD_OPC_Decode, 192, 21, 207, 2, // Opcode: SHRA_R_W +/* 15070 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 15084 +/* 15075 */ MCD_OPC_CheckPredicate, 37, 226, 7, 0, // Skip to: 17098 +/* 15080 */ MCD_OPC_Decode, 164, 21, 55, // Opcode: SHLLV_S_W +/* 15084 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 15098 +/* 15089 */ MCD_OPC_CheckPredicate, 37, 212, 7, 0, // Skip to: 17098 +/* 15094 */ MCD_OPC_Decode, 182, 21, 55, // Opcode: SHRAV_R_W +/* 15098 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 15113 +/* 15103 */ MCD_OPC_CheckPredicate, 69, 198, 7, 0, // Skip to: 17098 +/* 15108 */ MCD_OPC_Decode, 198, 21, 205, 2, // Opcode: SHRL_PH +/* 15113 */ MCD_OPC_FilterValue, 27, 188, 7, 0, // Skip to: 17098 +/* 15118 */ MCD_OPC_CheckPredicate, 69, 183, 7, 0, // Skip to: 17098 +/* 15123 */ MCD_OPC_Decode, 194, 21, 206, 2, // Opcode: SHRLV_PH +/* 15128 */ MCD_OPC_FilterValue, 24, 237, 0, 0, // Skip to: 15370 +/* 15133 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 15136 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 15151 +/* 15141 */ MCD_OPC_CheckPredicate, 69, 160, 7, 0, // Skip to: 17098 +/* 15146 */ MCD_OPC_Decode, 172, 6, 195, 2, // Opcode: ADDUH_QB +/* 15151 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 15166 +/* 15156 */ MCD_OPC_CheckPredicate, 69, 145, 7, 0, // Skip to: 17098 +/* 15161 */ MCD_OPC_Decode, 225, 22, 195, 2, // Opcode: SUBUH_QB +/* 15166 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 15181 +/* 15171 */ MCD_OPC_CheckPredicate, 69, 130, 7, 0, // Skip to: 17098 +/* 15176 */ MCD_OPC_Decode, 174, 6, 195, 2, // Opcode: ADDUH_R_QB +/* 15181 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 15196 +/* 15186 */ MCD_OPC_CheckPredicate, 69, 115, 7, 0, // Skip to: 17098 +/* 15191 */ MCD_OPC_Decode, 227, 22, 195, 2, // Opcode: SUBUH_R_QB +/* 15196 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 15211 +/* 15201 */ MCD_OPC_CheckPredicate, 69, 100, 7, 0, // Skip to: 17098 +/* 15206 */ MCD_OPC_Decode, 141, 6, 195, 2, // Opcode: ADDQH_PH +/* 15211 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 15226 +/* 15216 */ MCD_OPC_CheckPredicate, 69, 85, 7, 0, // Skip to: 17098 +/* 15221 */ MCD_OPC_Decode, 193, 22, 195, 2, // Opcode: SUBQH_PH +/* 15226 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 15241 +/* 15231 */ MCD_OPC_CheckPredicate, 69, 70, 7, 0, // Skip to: 17098 +/* 15236 */ MCD_OPC_Decode, 143, 6, 195, 2, // Opcode: ADDQH_R_PH +/* 15241 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 15256 +/* 15246 */ MCD_OPC_CheckPredicate, 69, 55, 7, 0, // Skip to: 17098 +/* 15251 */ MCD_OPC_Decode, 195, 22, 195, 2, // Opcode: SUBQH_R_PH +/* 15256 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 15271 +/* 15261 */ MCD_OPC_CheckPredicate, 69, 40, 7, 0, // Skip to: 17098 +/* 15266 */ MCD_OPC_Decode, 248, 18, 195, 2, // Opcode: MUL_PH +/* 15271 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 15286 +/* 15276 */ MCD_OPC_CheckPredicate, 69, 25, 7, 0, // Skip to: 17098 +/* 15281 */ MCD_OPC_Decode, 253, 18, 195, 2, // Opcode: MUL_S_PH +/* 15286 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 15300 +/* 15291 */ MCD_OPC_CheckPredicate, 69, 10, 7, 0, // Skip to: 17098 +/* 15296 */ MCD_OPC_Decode, 147, 6, 61, // Opcode: ADDQH_W +/* 15300 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 15314 +/* 15305 */ MCD_OPC_CheckPredicate, 69, 252, 6, 0, // Skip to: 17098 +/* 15310 */ MCD_OPC_Decode, 199, 22, 61, // Opcode: SUBQH_W +/* 15314 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 15328 +/* 15319 */ MCD_OPC_CheckPredicate, 69, 238, 6, 0, // Skip to: 17098 +/* 15324 */ MCD_OPC_Decode, 145, 6, 61, // Opcode: ADDQH_R_W +/* 15328 */ MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 15342 +/* 15333 */ MCD_OPC_CheckPredicate, 69, 224, 6, 0, // Skip to: 17098 +/* 15338 */ MCD_OPC_Decode, 197, 22, 61, // Opcode: SUBQH_R_W +/* 15342 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 15356 +/* 15347 */ MCD_OPC_CheckPredicate, 69, 210, 6, 0, // Skip to: 17098 +/* 15352 */ MCD_OPC_Decode, 221, 18, 61, // Opcode: MULQ_S_W +/* 15356 */ MCD_OPC_FilterValue, 23, 201, 6, 0, // Skip to: 17098 +/* 15361 */ MCD_OPC_CheckPredicate, 69, 196, 6, 0, // Skip to: 17098 +/* 15366 */ MCD_OPC_Decode, 217, 18, 61, // Opcode: MULQ_RS_W +/* 15370 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 15392 +/* 15375 */ MCD_OPC_CheckPredicate, 70, 182, 6, 0, // Skip to: 17098 +/* 15380 */ MCD_OPC_CheckField, 6, 1, 0, 175, 6, 0, // Skip to: 17098 +/* 15387 */ MCD_OPC_Decode, 151, 16, 208, 2, // Opcode: LWLE +/* 15392 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 15414 +/* 15397 */ MCD_OPC_CheckPredicate, 70, 160, 6, 0, // Skip to: 17098 +/* 15402 */ MCD_OPC_CheckField, 6, 1, 0, 153, 6, 0, // Skip to: 17098 +/* 15409 */ MCD_OPC_Decode, 164, 16, 208, 2, // Opcode: LWRE +/* 15414 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 15436 +/* 15419 */ MCD_OPC_CheckPredicate, 44, 138, 6, 0, // Skip to: 17098 +/* 15424 */ MCD_OPC_CheckField, 6, 1, 0, 131, 6, 0, // Skip to: 17098 +/* 15431 */ MCD_OPC_Decode, 247, 8, 209, 2, // Opcode: CACHEE +/* 15436 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 15458 +/* 15441 */ MCD_OPC_CheckPredicate, 44, 116, 6, 0, // Skip to: 17098 +/* 15446 */ MCD_OPC_CheckField, 6, 1, 0, 109, 6, 0, // Skip to: 17098 +/* 15453 */ MCD_OPC_Decode, 198, 20, 208, 2, // Opcode: SBE +/* 15458 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 15480 +/* 15463 */ MCD_OPC_CheckPredicate, 44, 94, 6, 0, // Skip to: 17098 +/* 15468 */ MCD_OPC_CheckField, 6, 1, 0, 87, 6, 0, // Skip to: 17098 +/* 15475 */ MCD_OPC_Decode, 148, 21, 208, 2, // Opcode: SHE +/* 15480 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 15502 +/* 15485 */ MCD_OPC_CheckPredicate, 44, 72, 6, 0, // Skip to: 17098 +/* 15490 */ MCD_OPC_CheckField, 6, 1, 0, 65, 6, 0, // Skip to: 17098 +/* 15497 */ MCD_OPC_Decode, 211, 20, 208, 2, // Opcode: SCE +/* 15502 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 15524 +/* 15507 */ MCD_OPC_CheckPredicate, 44, 50, 6, 0, // Skip to: 17098 +/* 15512 */ MCD_OPC_CheckField, 6, 1, 0, 43, 6, 0, // Skip to: 17098 +/* 15519 */ MCD_OPC_Decode, 142, 23, 208, 2, // Opcode: SWE +/* 15524 */ MCD_OPC_FilterValue, 32, 69, 0, 0, // Skip to: 15598 +/* 15529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 15532 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 15554 +/* 15537 */ MCD_OPC_CheckPredicate, 28, 20, 6, 0, // Skip to: 17098 +/* 15542 */ MCD_OPC_CheckField, 21, 5, 0, 13, 6, 0, // Skip to: 17098 +/* 15549 */ MCD_OPC_Decode, 169, 24, 204, 2, // Opcode: WSBH +/* 15554 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 15576 +/* 15559 */ MCD_OPC_CheckPredicate, 28, 254, 5, 0, // Skip to: 17098 +/* 15564 */ MCD_OPC_CheckField, 21, 5, 0, 247, 5, 0, // Skip to: 17098 +/* 15571 */ MCD_OPC_Decode, 242, 20, 204, 2, // Opcode: SEB +/* 15576 */ MCD_OPC_FilterValue, 24, 237, 5, 0, // Skip to: 17098 +/* 15581 */ MCD_OPC_CheckPredicate, 28, 232, 5, 0, // Skip to: 17098 +/* 15586 */ MCD_OPC_CheckField, 21, 5, 0, 225, 5, 0, // Skip to: 17098 +/* 15593 */ MCD_OPC_Decode, 246, 20, 204, 2, // Opcode: SEH +/* 15598 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 15620 +/* 15603 */ MCD_OPC_CheckPredicate, 70, 210, 5, 0, // Skip to: 17098 +/* 15608 */ MCD_OPC_CheckField, 6, 1, 0, 203, 5, 0, // Skip to: 17098 +/* 15615 */ MCD_OPC_Decode, 148, 23, 208, 2, // Opcode: SWLE +/* 15620 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 15642 +/* 15625 */ MCD_OPC_CheckPredicate, 70, 188, 5, 0, // Skip to: 17098 +/* 15630 */ MCD_OPC_CheckField, 6, 1, 0, 181, 5, 0, // Skip to: 17098 +/* 15637 */ MCD_OPC_Decode, 159, 23, 208, 2, // Opcode: SWRE +/* 15642 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 15664 +/* 15647 */ MCD_OPC_CheckPredicate, 44, 166, 5, 0, // Skip to: 17098 +/* 15652 */ MCD_OPC_CheckField, 6, 1, 0, 159, 5, 0, // Skip to: 17098 +/* 15659 */ MCD_OPC_Decode, 239, 19, 209, 2, // Opcode: PREFE +/* 15664 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 15686 +/* 15669 */ MCD_OPC_CheckPredicate, 44, 144, 5, 0, // Skip to: 17098 +/* 15674 */ MCD_OPC_CheckField, 6, 1, 0, 137, 5, 0, // Skip to: 17098 +/* 15681 */ MCD_OPC_Decode, 176, 15, 208, 2, // Opcode: LBuE +/* 15686 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 15708 +/* 15691 */ MCD_OPC_CheckPredicate, 44, 122, 5, 0, // Skip to: 17098 +/* 15696 */ MCD_OPC_CheckField, 6, 1, 0, 115, 5, 0, // Skip to: 17098 +/* 15703 */ MCD_OPC_Decode, 228, 15, 208, 2, // Opcode: LHuE +/* 15708 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 15730 +/* 15713 */ MCD_OPC_CheckPredicate, 44, 100, 5, 0, // Skip to: 17098 +/* 15718 */ MCD_OPC_CheckField, 6, 1, 0, 93, 5, 0, // Skip to: 17098 +/* 15725 */ MCD_OPC_Decode, 157, 15, 208, 2, // Opcode: LBE +/* 15730 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 15752 +/* 15735 */ MCD_OPC_CheckPredicate, 44, 78, 5, 0, // Skip to: 17098 +/* 15740 */ MCD_OPC_CheckField, 6, 1, 0, 71, 5, 0, // Skip to: 17098 +/* 15747 */ MCD_OPC_Decode, 209, 15, 208, 2, // Opcode: LHE +/* 15752 */ MCD_OPC_FilterValue, 46, 17, 0, 0, // Skip to: 15774 +/* 15757 */ MCD_OPC_CheckPredicate, 44, 56, 5, 0, // Skip to: 17098 +/* 15762 */ MCD_OPC_CheckField, 6, 1, 0, 49, 5, 0, // Skip to: 17098 +/* 15769 */ MCD_OPC_Decode, 240, 15, 208, 2, // Opcode: LLE +/* 15774 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 15796 +/* 15779 */ MCD_OPC_CheckPredicate, 44, 34, 5, 0, // Skip to: 17098 +/* 15784 */ MCD_OPC_CheckField, 6, 1, 0, 27, 5, 0, // Skip to: 17098 +/* 15791 */ MCD_OPC_Decode, 144, 16, 208, 2, // Opcode: LWE +/* 15796 */ MCD_OPC_FilterValue, 48, 231, 1, 0, // Skip to: 16288 +/* 15801 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 15804 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 15826 +/* 15809 */ MCD_OPC_CheckPredicate, 69, 4, 5, 0, // Skip to: 17098 +/* 15814 */ MCD_OPC_CheckField, 13, 3, 0, 253, 4, 0, // Skip to: 17098 +/* 15821 */ MCD_OPC_Decode, 156, 12, 243, 1, // Opcode: DPA_W_PH +/* 15826 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 15848 +/* 15831 */ MCD_OPC_CheckPredicate, 69, 238, 4, 0, // Skip to: 17098 +/* 15836 */ MCD_OPC_CheckField, 13, 3, 0, 231, 4, 0, // Skip to: 17098 +/* 15843 */ MCD_OPC_Decode, 179, 12, 243, 1, // Opcode: DPS_W_PH +/* 15848 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 15870 +/* 15853 */ MCD_OPC_CheckPredicate, 69, 216, 4, 0, // Skip to: 17098 +/* 15858 */ MCD_OPC_CheckField, 13, 3, 0, 209, 4, 0, // Skip to: 17098 +/* 15865 */ MCD_OPC_Decode, 228, 18, 243, 1, // Opcode: MULSA_W_PH +/* 15870 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 15892 +/* 15875 */ MCD_OPC_CheckPredicate, 37, 194, 4, 0, // Skip to: 17098 +/* 15880 */ MCD_OPC_CheckField, 13, 3, 0, 187, 4, 0, // Skip to: 17098 +/* 15887 */ MCD_OPC_Decode, 150, 12, 243, 1, // Opcode: DPAU_H_QBL +/* 15892 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 15914 +/* 15897 */ MCD_OPC_CheckPredicate, 37, 172, 4, 0, // Skip to: 17098 +/* 15902 */ MCD_OPC_CheckField, 13, 3, 0, 165, 4, 0, // Skip to: 17098 +/* 15909 */ MCD_OPC_Decode, 148, 12, 243, 1, // Opcode: DPAQ_S_W_PH +/* 15914 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 15936 +/* 15919 */ MCD_OPC_CheckPredicate, 37, 150, 4, 0, // Skip to: 17098 +/* 15924 */ MCD_OPC_CheckField, 13, 3, 0, 143, 4, 0, // Skip to: 17098 +/* 15931 */ MCD_OPC_Decode, 165, 12, 243, 1, // Opcode: DPSQ_S_W_PH +/* 15936 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 15958 +/* 15941 */ MCD_OPC_CheckPredicate, 37, 128, 4, 0, // Skip to: 17098 +/* 15946 */ MCD_OPC_CheckField, 13, 3, 0, 121, 4, 0, // Skip to: 17098 +/* 15953 */ MCD_OPC_Decode, 226, 18, 243, 1, // Opcode: MULSAQ_S_W_PH +/* 15958 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 15980 +/* 15963 */ MCD_OPC_CheckPredicate, 37, 106, 4, 0, // Skip to: 17098 +/* 15968 */ MCD_OPC_CheckField, 13, 3, 0, 99, 4, 0, // Skip to: 17098 +/* 15975 */ MCD_OPC_Decode, 152, 12, 243, 1, // Opcode: DPAU_H_QBR +/* 15980 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 16002 +/* 15985 */ MCD_OPC_CheckPredicate, 69, 84, 4, 0, // Skip to: 17098 +/* 15990 */ MCD_OPC_CheckField, 13, 3, 0, 77, 4, 0, // Skip to: 17098 +/* 15997 */ MCD_OPC_Decode, 154, 12, 243, 1, // Opcode: DPAX_W_PH +/* 16002 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 16024 +/* 16007 */ MCD_OPC_CheckPredicate, 69, 62, 4, 0, // Skip to: 17098 +/* 16012 */ MCD_OPC_CheckField, 13, 3, 0, 55, 4, 0, // Skip to: 17098 +/* 16019 */ MCD_OPC_Decode, 177, 12, 243, 1, // Opcode: DPSX_W_PH +/* 16024 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 16046 +/* 16029 */ MCD_OPC_CheckPredicate, 37, 40, 4, 0, // Skip to: 17098 +/* 16034 */ MCD_OPC_CheckField, 13, 3, 0, 33, 4, 0, // Skip to: 17098 +/* 16041 */ MCD_OPC_Decode, 173, 12, 243, 1, // Opcode: DPSU_H_QBL +/* 16046 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 16068 +/* 16051 */ MCD_OPC_CheckPredicate, 37, 18, 4, 0, // Skip to: 17098 +/* 16056 */ MCD_OPC_CheckField, 13, 3, 0, 11, 4, 0, // Skip to: 17098 +/* 16063 */ MCD_OPC_Decode, 146, 12, 243, 1, // Opcode: DPAQ_SA_L_W +/* 16068 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 16090 +/* 16073 */ MCD_OPC_CheckPredicate, 37, 252, 3, 0, // Skip to: 17098 +/* 16078 */ MCD_OPC_CheckField, 13, 3, 0, 245, 3, 0, // Skip to: 17098 +/* 16085 */ MCD_OPC_Decode, 163, 12, 243, 1, // Opcode: DPSQ_SA_L_W +/* 16090 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 16112 +/* 16095 */ MCD_OPC_CheckPredicate, 37, 230, 3, 0, // Skip to: 17098 +/* 16100 */ MCD_OPC_CheckField, 13, 3, 0, 223, 3, 0, // Skip to: 17098 +/* 16107 */ MCD_OPC_Decode, 175, 12, 243, 1, // Opcode: DPSU_H_QBR +/* 16112 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 16134 +/* 16117 */ MCD_OPC_CheckPredicate, 37, 208, 3, 0, // Skip to: 17098 +/* 16122 */ MCD_OPC_CheckField, 13, 3, 0, 201, 3, 0, // Skip to: 17098 +/* 16129 */ MCD_OPC_Decode, 220, 16, 243, 1, // Opcode: MAQ_SA_W_PHL +/* 16134 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 16156 +/* 16139 */ MCD_OPC_CheckPredicate, 37, 186, 3, 0, // Skip to: 17098 +/* 16144 */ MCD_OPC_CheckField, 13, 3, 0, 179, 3, 0, // Skip to: 17098 +/* 16151 */ MCD_OPC_Decode, 222, 16, 243, 1, // Opcode: MAQ_SA_W_PHR +/* 16156 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 16178 +/* 16161 */ MCD_OPC_CheckPredicate, 37, 164, 3, 0, // Skip to: 17098 +/* 16166 */ MCD_OPC_CheckField, 13, 3, 0, 157, 3, 0, // Skip to: 17098 +/* 16173 */ MCD_OPC_Decode, 224, 16, 243, 1, // Opcode: MAQ_S_W_PHL +/* 16178 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 16200 +/* 16183 */ MCD_OPC_CheckPredicate, 37, 142, 3, 0, // Skip to: 17098 +/* 16188 */ MCD_OPC_CheckField, 13, 3, 0, 135, 3, 0, // Skip to: 17098 +/* 16195 */ MCD_OPC_Decode, 226, 16, 243, 1, // Opcode: MAQ_S_W_PHR +/* 16200 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 16222 +/* 16205 */ MCD_OPC_CheckPredicate, 69, 120, 3, 0, // Skip to: 17098 +/* 16210 */ MCD_OPC_CheckField, 13, 3, 0, 113, 3, 0, // Skip to: 17098 +/* 16217 */ MCD_OPC_Decode, 144, 12, 243, 1, // Opcode: DPAQX_S_W_PH +/* 16222 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 16244 +/* 16227 */ MCD_OPC_CheckPredicate, 69, 98, 3, 0, // Skip to: 17098 +/* 16232 */ MCD_OPC_CheckField, 13, 3, 0, 91, 3, 0, // Skip to: 17098 +/* 16239 */ MCD_OPC_Decode, 161, 12, 243, 1, // Opcode: DPSQX_S_W_PH +/* 16244 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 16266 +/* 16249 */ MCD_OPC_CheckPredicate, 69, 76, 3, 0, // Skip to: 17098 +/* 16254 */ MCD_OPC_CheckField, 13, 3, 0, 69, 3, 0, // Skip to: 17098 +/* 16261 */ MCD_OPC_Decode, 142, 12, 243, 1, // Opcode: DPAQX_SA_W_PH +/* 16266 */ MCD_OPC_FilterValue, 27, 59, 3, 0, // Skip to: 17098 +/* 16271 */ MCD_OPC_CheckPredicate, 69, 54, 3, 0, // Skip to: 17098 +/* 16276 */ MCD_OPC_CheckField, 13, 3, 0, 47, 3, 0, // Skip to: 17098 +/* 16283 */ MCD_OPC_Decode, 159, 12, 243, 1, // Opcode: DPSQX_SA_W_PH +/* 16288 */ MCD_OPC_FilterValue, 49, 48, 0, 0, // Skip to: 16341 +/* 16293 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 16296 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16311 +/* 16301 */ MCD_OPC_CheckPredicate, 69, 24, 3, 0, // Skip to: 17098 +/* 16306 */ MCD_OPC_Decode, 234, 6, 210, 2, // Opcode: APPEND +/* 16311 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 16326 +/* 16316 */ MCD_OPC_CheckPredicate, 69, 9, 3, 0, // Skip to: 17098 +/* 16321 */ MCD_OPC_Decode, 247, 19, 210, 2, // Opcode: PREPEND +/* 16326 */ MCD_OPC_FilterValue, 16, 255, 2, 0, // Skip to: 17098 +/* 16331 */ MCD_OPC_CheckPredicate, 69, 250, 2, 0, // Skip to: 17098 +/* 16336 */ MCD_OPC_Decode, 152, 7, 210, 2, // Opcode: BALIGN +/* 16341 */ MCD_OPC_FilterValue, 56, 107, 1, 0, // Skip to: 16709 +/* 16346 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 16349 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16371 +/* 16354 */ MCD_OPC_CheckPredicate, 37, 227, 2, 0, // Skip to: 17098 +/* 16359 */ MCD_OPC_CheckField, 13, 3, 0, 220, 2, 0, // Skip to: 17098 +/* 16366 */ MCD_OPC_Decode, 250, 12, 211, 2, // Opcode: EXTR_W +/* 16371 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16393 +/* 16376 */ MCD_OPC_CheckPredicate, 37, 205, 2, 0, // Skip to: 17098 +/* 16381 */ MCD_OPC_CheckField, 13, 3, 0, 198, 2, 0, // Skip to: 17098 +/* 16388 */ MCD_OPC_Decode, 242, 12, 212, 2, // Opcode: EXTRV_W +/* 16393 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16415 +/* 16398 */ MCD_OPC_CheckPredicate, 37, 183, 2, 0, // Skip to: 17098 +/* 16403 */ MCD_OPC_CheckField, 13, 3, 0, 176, 2, 0, // Skip to: 17098 +/* 16410 */ MCD_OPC_Decode, 228, 12, 211, 2, // Opcode: EXTP +/* 16415 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 16437 +/* 16420 */ MCD_OPC_CheckPredicate, 37, 161, 2, 0, // Skip to: 17098 +/* 16425 */ MCD_OPC_CheckField, 13, 3, 0, 154, 2, 0, // Skip to: 17098 +/* 16432 */ MCD_OPC_Decode, 233, 12, 212, 2, // Opcode: EXTPV +/* 16437 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 16459 +/* 16442 */ MCD_OPC_CheckPredicate, 37, 139, 2, 0, // Skip to: 17098 +/* 16447 */ MCD_OPC_CheckField, 13, 3, 0, 132, 2, 0, // Skip to: 17098 +/* 16454 */ MCD_OPC_Decode, 246, 12, 211, 2, // Opcode: EXTR_R_W +/* 16459 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 16481 +/* 16464 */ MCD_OPC_CheckPredicate, 37, 117, 2, 0, // Skip to: 17098 +/* 16469 */ MCD_OPC_CheckField, 13, 3, 0, 110, 2, 0, // Skip to: 17098 +/* 16476 */ MCD_OPC_Decode, 238, 12, 212, 2, // Opcode: EXTRV_R_W +/* 16481 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 16503 +/* 16486 */ MCD_OPC_CheckPredicate, 37, 95, 2, 0, // Skip to: 17098 +/* 16491 */ MCD_OPC_CheckField, 13, 3, 0, 88, 2, 0, // Skip to: 17098 +/* 16498 */ MCD_OPC_Decode, 244, 12, 211, 2, // Opcode: EXTR_RS_W +/* 16503 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 16525 +/* 16508 */ MCD_OPC_CheckPredicate, 37, 73, 2, 0, // Skip to: 17098 +/* 16513 */ MCD_OPC_CheckField, 13, 3, 0, 66, 2, 0, // Skip to: 17098 +/* 16520 */ MCD_OPC_Decode, 236, 12, 212, 2, // Opcode: EXTRV_RS_W +/* 16525 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 16547 +/* 16530 */ MCD_OPC_CheckPredicate, 37, 51, 2, 0, // Skip to: 17098 +/* 16535 */ MCD_OPC_CheckField, 13, 3, 0, 44, 2, 0, // Skip to: 17098 +/* 16542 */ MCD_OPC_Decode, 229, 12, 211, 2, // Opcode: EXTPDP +/* 16547 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 16569 +/* 16552 */ MCD_OPC_CheckPredicate, 37, 29, 2, 0, // Skip to: 17098 +/* 16557 */ MCD_OPC_CheckField, 13, 3, 0, 22, 2, 0, // Skip to: 17098 +/* 16564 */ MCD_OPC_Decode, 230, 12, 212, 2, // Opcode: EXTPDPV +/* 16569 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 16591 +/* 16574 */ MCD_OPC_CheckPredicate, 37, 7, 2, 0, // Skip to: 17098 +/* 16579 */ MCD_OPC_CheckField, 13, 3, 0, 0, 2, 0, // Skip to: 17098 +/* 16586 */ MCD_OPC_Decode, 248, 12, 211, 2, // Opcode: EXTR_S_H +/* 16591 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 16613 +/* 16596 */ MCD_OPC_CheckPredicate, 37, 241, 1, 0, // Skip to: 17098 +/* 16601 */ MCD_OPC_CheckField, 13, 3, 0, 234, 1, 0, // Skip to: 17098 +/* 16608 */ MCD_OPC_Decode, 240, 12, 212, 2, // Opcode: EXTRV_S_H +/* 16613 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 16628 +/* 16618 */ MCD_OPC_CheckPredicate, 37, 219, 1, 0, // Skip to: 17098 +/* 16623 */ MCD_OPC_Decode, 253, 19, 213, 2, // Opcode: RDDSP +/* 16628 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 16643 +/* 16633 */ MCD_OPC_CheckPredicate, 40, 204, 1, 0, // Skip to: 17098 +/* 16638 */ MCD_OPC_Decode, 165, 24, 214, 2, // Opcode: WRDSP +/* 16643 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 16665 +/* 16648 */ MCD_OPC_CheckPredicate, 37, 189, 1, 0, // Skip to: 17098 +/* 16653 */ MCD_OPC_CheckField, 13, 7, 0, 182, 1, 0, // Skip to: 17098 +/* 16660 */ MCD_OPC_Decode, 154, 21, 215, 2, // Opcode: SHILO +/* 16665 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 16687 +/* 16670 */ MCD_OPC_CheckPredicate, 37, 167, 1, 0, // Skip to: 17098 +/* 16675 */ MCD_OPC_CheckField, 13, 8, 0, 160, 1, 0, // Skip to: 17098 +/* 16682 */ MCD_OPC_Decode, 155, 21, 216, 2, // Opcode: SHILOV +/* 16687 */ MCD_OPC_FilterValue, 31, 150, 1, 0, // Skip to: 17098 +/* 16692 */ MCD_OPC_CheckPredicate, 37, 145, 1, 0, // Skip to: 17098 +/* 16697 */ MCD_OPC_CheckField, 13, 8, 0, 138, 1, 0, // Skip to: 17098 +/* 16704 */ MCD_OPC_Decode, 184, 18, 216, 2, // Opcode: MTHLIP +/* 16709 */ MCD_OPC_FilterValue, 59, 128, 1, 0, // Skip to: 17098 +/* 16714 */ MCD_OPC_CheckPredicate, 27, 123, 1, 0, // Skip to: 17098 +/* 16719 */ MCD_OPC_CheckField, 21, 5, 0, 116, 1, 0, // Skip to: 17098 +/* 16726 */ MCD_OPC_CheckField, 9, 2, 0, 109, 1, 0, // Skip to: 17098 +/* 16733 */ MCD_OPC_Decode, 255, 19, 217, 2, // Opcode: RDHWR +/* 16738 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 16753 +/* 16743 */ MCD_OPC_CheckPredicate, 27, 94, 1, 0, // Skip to: 17098 +/* 16748 */ MCD_OPC_Decode, 154, 15, 141, 1, // Opcode: LB +/* 16753 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 16768 +/* 16758 */ MCD_OPC_CheckPredicate, 27, 79, 1, 0, // Skip to: 17098 +/* 16763 */ MCD_OPC_Decode, 206, 15, 141, 1, // Opcode: LH +/* 16768 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 16783 +/* 16773 */ MCD_OPC_CheckPredicate, 31, 64, 1, 0, // Skip to: 17098 +/* 16778 */ MCD_OPC_Decode, 149, 16, 141, 1, // Opcode: LWL +/* 16783 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 16798 +/* 16788 */ MCD_OPC_CheckPredicate, 27, 49, 1, 0, // Skip to: 17098 +/* 16793 */ MCD_OPC_Decode, 131, 16, 141, 1, // Opcode: LW +/* 16798 */ MCD_OPC_FilterValue, 36, 10, 0, 0, // Skip to: 16813 +/* 16803 */ MCD_OPC_CheckPredicate, 27, 34, 1, 0, // Skip to: 17098 +/* 16808 */ MCD_OPC_Decode, 174, 15, 141, 1, // Opcode: LBu +/* 16813 */ MCD_OPC_FilterValue, 37, 10, 0, 0, // Skip to: 16828 +/* 16818 */ MCD_OPC_CheckPredicate, 27, 19, 1, 0, // Skip to: 17098 +/* 16823 */ MCD_OPC_Decode, 226, 15, 141, 1, // Opcode: LHu +/* 16828 */ MCD_OPC_FilterValue, 38, 10, 0, 0, // Skip to: 16843 +/* 16833 */ MCD_OPC_CheckPredicate, 31, 4, 1, 0, // Skip to: 17098 +/* 16838 */ MCD_OPC_Decode, 162, 16, 141, 1, // Opcode: LWR +/* 16843 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 16858 +/* 16848 */ MCD_OPC_CheckPredicate, 27, 245, 0, 0, // Skip to: 17098 +/* 16853 */ MCD_OPC_Decode, 193, 20, 141, 1, // Opcode: SB +/* 16858 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 16873 +/* 16863 */ MCD_OPC_CheckPredicate, 27, 230, 0, 0, // Skip to: 17098 +/* 16868 */ MCD_OPC_Decode, 143, 21, 141, 1, // Opcode: SH +/* 16873 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 16888 +/* 16878 */ MCD_OPC_CheckPredicate, 31, 215, 0, 0, // Skip to: 17098 +/* 16883 */ MCD_OPC_Decode, 146, 23, 141, 1, // Opcode: SWL +/* 16888 */ MCD_OPC_FilterValue, 43, 10, 0, 0, // Skip to: 16903 +/* 16893 */ MCD_OPC_CheckPredicate, 27, 200, 0, 0, // Skip to: 17098 +/* 16898 */ MCD_OPC_Decode, 128, 23, 141, 1, // Opcode: SW +/* 16903 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 16918 +/* 16908 */ MCD_OPC_CheckPredicate, 31, 185, 0, 0, // Skip to: 17098 +/* 16913 */ MCD_OPC_Decode, 157, 23, 141, 1, // Opcode: SWR +/* 16918 */ MCD_OPC_FilterValue, 47, 10, 0, 0, // Skip to: 16933 +/* 16923 */ MCD_OPC_CheckPredicate, 71, 170, 0, 0, // Skip to: 17098 +/* 16928 */ MCD_OPC_Decode, 246, 8, 218, 2, // Opcode: CACHE +/* 16933 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 16948 +/* 16938 */ MCD_OPC_CheckPredicate, 72, 155, 0, 0, // Skip to: 17098 +/* 16943 */ MCD_OPC_Decode, 235, 15, 141, 1, // Opcode: LL +/* 16948 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 16963 +/* 16953 */ MCD_OPC_CheckPredicate, 47, 140, 0, 0, // Skip to: 17098 +/* 16958 */ MCD_OPC_Decode, 136, 16, 219, 2, // Opcode: LWC1 +/* 16963 */ MCD_OPC_FilterValue, 50, 10, 0, 0, // Skip to: 16978 +/* 16968 */ MCD_OPC_CheckPredicate, 31, 125, 0, 0, // Skip to: 17098 +/* 16973 */ MCD_OPC_Decode, 138, 16, 220, 2, // Opcode: LWC2 +/* 16978 */ MCD_OPC_FilterValue, 51, 10, 0, 0, // Skip to: 16993 +/* 16983 */ MCD_OPC_CheckPredicate, 71, 110, 0, 0, // Skip to: 17098 +/* 16988 */ MCD_OPC_Decode, 238, 19, 218, 2, // Opcode: PREF +/* 16993 */ MCD_OPC_FilterValue, 53, 10, 0, 0, // Skip to: 17008 +/* 16998 */ MCD_OPC_CheckPredicate, 57, 95, 0, 0, // Skip to: 17098 +/* 17003 */ MCD_OPC_Decode, 180, 15, 219, 2, // Opcode: LDC1 +/* 17008 */ MCD_OPC_FilterValue, 54, 10, 0, 0, // Skip to: 17023 +/* 17013 */ MCD_OPC_CheckPredicate, 39, 80, 0, 0, // Skip to: 17098 +/* 17018 */ MCD_OPC_Decode, 185, 15, 220, 2, // Opcode: LDC2 +/* 17023 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 17038 +/* 17028 */ MCD_OPC_CheckPredicate, 72, 65, 0, 0, // Skip to: 17098 +/* 17033 */ MCD_OPC_Decode, 206, 20, 141, 1, // Opcode: SC +/* 17038 */ MCD_OPC_FilterValue, 57, 10, 0, 0, // Skip to: 17053 +/* 17043 */ MCD_OPC_CheckPredicate, 47, 50, 0, 0, // Skip to: 17098 +/* 17048 */ MCD_OPC_Decode, 134, 23, 219, 2, // Opcode: SWC1 +/* 17053 */ MCD_OPC_FilterValue, 58, 10, 0, 0, // Skip to: 17068 +/* 17058 */ MCD_OPC_CheckPredicate, 31, 35, 0, 0, // Skip to: 17098 +/* 17063 */ MCD_OPC_Decode, 136, 23, 220, 2, // Opcode: SWC2 +/* 17068 */ MCD_OPC_FilterValue, 61, 10, 0, 0, // Skip to: 17083 +/* 17073 */ MCD_OPC_CheckPredicate, 57, 20, 0, 0, // Skip to: 17098 +/* 17078 */ MCD_OPC_Decode, 227, 20, 219, 2, // Opcode: SDC1 +/* 17083 */ MCD_OPC_FilterValue, 62, 10, 0, 0, // Skip to: 17098 +/* 17088 */ MCD_OPC_CheckPredicate, 39, 5, 0, 0, // Skip to: 17098 +/* 17093 */ MCD_OPC_Decode, 232, 20, 220, 2, // Opcode: SDC2 +/* 17098 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMips32_64_PTR6432[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 24 +/* 8 */ MCD_OPC_CheckPredicate, 73, 41, 0, 0, // Skip to: 54 +/* 13 */ MCD_OPC_CheckField, 0, 21, 8, 34, 0, 0, // Skip to: 54 +/* 20 */ MCD_OPC_Decode, 134, 15, 24, // Opcode: JR64 +/* 24 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 39 +/* 29 */ MCD_OPC_CheckPredicate, 74, 20, 0, 0, // Skip to: 54 +/* 34 */ MCD_OPC_Decode, 236, 15, 141, 1, // Opcode: LL64 +/* 39 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 54 +/* 44 */ MCD_OPC_CheckPredicate, 74, 5, 0, 0, // Skip to: 54 +/* 49 */ MCD_OPC_Decode, 207, 20, 141, 1, // Opcode: SC64 +/* 54 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMips32r6_64r632[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 205, 1, // Skip to: 468 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 29 -/* 14 */ MCD_OPC_CheckPredicate, 36, 37, 7, // Skip to: 1847 -/* 18 */ MCD_OPC_CheckField, 8, 3, 0, 31, 7, // Skip to: 1847 -/* 24 */ MCD_OPC_Decode, 206, 7, 221, 1, // Opcode: LSA_R6 -/* 29 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 47 -/* 33 */ MCD_OPC_CheckPredicate, 36, 18, 7, // Skip to: 1847 -/* 37 */ MCD_OPC_CheckField, 6, 15, 16, 12, 7, // Skip to: 1847 -/* 43 */ MCD_OPC_Decode, 142, 7, 61, // Opcode: JR_HB_R6 -/* 47 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 59 -/* 51 */ MCD_OPC_CheckPredicate, 36, 0, 7, // Skip to: 1847 -/* 55 */ MCD_OPC_Decode, 155, 11, 64, // Opcode: SDBBP_R6 -/* 59 */ MCD_OPC_FilterValue, 16, 20, 0, // Skip to: 83 -/* 63 */ MCD_OPC_CheckPredicate, 36, 244, 6, // Skip to: 1847 -/* 67 */ MCD_OPC_CheckField, 16, 5, 0, 238, 6, // Skip to: 1847 -/* 73 */ MCD_OPC_CheckField, 6, 5, 1, 232, 6, // Skip to: 1847 -/* 79 */ MCD_OPC_Decode, 154, 3, 62, // Opcode: CLZ_R6 -/* 83 */ MCD_OPC_FilterValue, 17, 20, 0, // Skip to: 107 -/* 87 */ MCD_OPC_CheckPredicate, 36, 220, 6, // Skip to: 1847 -/* 91 */ MCD_OPC_CheckField, 16, 5, 0, 214, 6, // Skip to: 1847 -/* 97 */ MCD_OPC_CheckField, 6, 5, 1, 208, 6, // Skip to: 1847 -/* 103 */ MCD_OPC_Decode, 135, 3, 62, // Opcode: CLO_R6 -/* 107 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 132 -/* 111 */ MCD_OPC_CheckPredicate, 37, 196, 6, // Skip to: 1847 -/* 115 */ MCD_OPC_CheckField, 16, 5, 0, 190, 6, // Skip to: 1847 -/* 121 */ MCD_OPC_CheckField, 6, 5, 1, 184, 6, // Skip to: 1847 -/* 127 */ MCD_OPC_Decode, 171, 4, 222, 1, // Opcode: DCLZ_R6 -/* 132 */ MCD_OPC_FilterValue, 19, 21, 0, // Skip to: 157 -/* 136 */ MCD_OPC_CheckPredicate, 37, 171, 6, // Skip to: 1847 -/* 140 */ MCD_OPC_CheckField, 16, 5, 0, 165, 6, // Skip to: 1847 -/* 146 */ MCD_OPC_CheckField, 6, 5, 1, 159, 6, // Skip to: 1847 -/* 152 */ MCD_OPC_Decode, 169, 4, 222, 1, // Opcode: DCLO_R6 -/* 157 */ MCD_OPC_FilterValue, 21, 15, 0, // Skip to: 176 -/* 161 */ MCD_OPC_CheckPredicate, 37, 146, 6, // Skip to: 1847 -/* 165 */ MCD_OPC_CheckField, 8, 3, 0, 140, 6, // Skip to: 1847 -/* 171 */ MCD_OPC_Decode, 195, 4, 223, 1, // Opcode: DLSA_R6 -/* 176 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 207 -/* 180 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 183 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 195 -/* 187 */ MCD_OPC_CheckPredicate, 36, 120, 6, // Skip to: 1847 -/* 191 */ MCD_OPC_Decode, 221, 9, 35, // Opcode: MUL_R6 -/* 195 */ MCD_OPC_FilterValue, 3, 112, 6, // Skip to: 1847 -/* 199 */ MCD_OPC_CheckPredicate, 36, 108, 6, // Skip to: 1847 -/* 203 */ MCD_OPC_Decode, 191, 9, 35, // Opcode: MUH -/* 207 */ MCD_OPC_FilterValue, 25, 27, 0, // Skip to: 238 -/* 211 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 214 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 226 -/* 218 */ MCD_OPC_CheckPredicate, 36, 89, 6, // Skip to: 1847 -/* 222 */ MCD_OPC_Decode, 212, 9, 35, // Opcode: MULU -/* 226 */ MCD_OPC_FilterValue, 3, 81, 6, // Skip to: 1847 -/* 230 */ MCD_OPC_CheckPredicate, 36, 77, 6, // Skip to: 1847 -/* 234 */ MCD_OPC_Decode, 192, 9, 35, // Opcode: MUHU -/* 238 */ MCD_OPC_FilterValue, 26, 27, 0, // Skip to: 269 -/* 242 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 245 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 257 -/* 249 */ MCD_OPC_CheckPredicate, 36, 58, 6, // Skip to: 1847 -/* 253 */ MCD_OPC_Decode, 183, 4, 35, // Opcode: DIV -/* 257 */ MCD_OPC_FilterValue, 3, 50, 6, // Skip to: 1847 -/* 261 */ MCD_OPC_CheckPredicate, 36, 46, 6, // Skip to: 1847 -/* 265 */ MCD_OPC_Decode, 222, 8, 35, // Opcode: MOD -/* 269 */ MCD_OPC_FilterValue, 27, 27, 0, // Skip to: 300 -/* 273 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 276 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 288 -/* 280 */ MCD_OPC_CheckPredicate, 36, 27, 6, // Skip to: 1847 -/* 284 */ MCD_OPC_Decode, 184, 4, 35, // Opcode: DIVU -/* 288 */ MCD_OPC_FilterValue, 3, 19, 6, // Skip to: 1847 -/* 292 */ MCD_OPC_CheckPredicate, 36, 15, 6, // Skip to: 1847 -/* 296 */ MCD_OPC_Decode, 224, 8, 35, // Opcode: MODU -/* 300 */ MCD_OPC_FilterValue, 28, 29, 0, // Skip to: 333 -/* 304 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 307 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 320 -/* 311 */ MCD_OPC_CheckPredicate, 37, 252, 5, // Skip to: 1847 -/* 315 */ MCD_OPC_Decode, 210, 4, 224, 1, // Opcode: DMUL_R6 -/* 320 */ MCD_OPC_FilterValue, 3, 243, 5, // Skip to: 1847 -/* 324 */ MCD_OPC_CheckPredicate, 37, 239, 5, // Skip to: 1847 -/* 328 */ MCD_OPC_Decode, 204, 4, 224, 1, // Opcode: DMUH -/* 333 */ MCD_OPC_FilterValue, 29, 29, 0, // Skip to: 366 -/* 337 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 353 -/* 344 */ MCD_OPC_CheckPredicate, 37, 219, 5, // Skip to: 1847 -/* 348 */ MCD_OPC_Decode, 209, 4, 224, 1, // Opcode: DMULU -/* 353 */ MCD_OPC_FilterValue, 3, 210, 5, // Skip to: 1847 -/* 357 */ MCD_OPC_CheckPredicate, 37, 206, 5, // Skip to: 1847 -/* 361 */ MCD_OPC_Decode, 205, 4, 224, 1, // Opcode: DMUHU -/* 366 */ MCD_OPC_FilterValue, 30, 29, 0, // Skip to: 399 -/* 370 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 373 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 386 -/* 377 */ MCD_OPC_CheckPredicate, 37, 186, 5, // Skip to: 1847 -/* 381 */ MCD_OPC_Decode, 172, 4, 224, 1, // Opcode: DDIV -/* 386 */ MCD_OPC_FilterValue, 3, 177, 5, // Skip to: 1847 -/* 390 */ MCD_OPC_CheckPredicate, 37, 173, 5, // Skip to: 1847 -/* 394 */ MCD_OPC_Decode, 199, 4, 224, 1, // Opcode: DMOD -/* 399 */ MCD_OPC_FilterValue, 31, 29, 0, // Skip to: 432 -/* 403 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 406 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 419 -/* 410 */ MCD_OPC_CheckPredicate, 37, 153, 5, // Skip to: 1847 -/* 414 */ MCD_OPC_Decode, 173, 4, 224, 1, // Opcode: DDIVU -/* 419 */ MCD_OPC_FilterValue, 3, 144, 5, // Skip to: 1847 -/* 423 */ MCD_OPC_CheckPredicate, 37, 140, 5, // Skip to: 1847 -/* 427 */ MCD_OPC_Decode, 200, 4, 224, 1, // Opcode: DMODU -/* 432 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 450 -/* 436 */ MCD_OPC_CheckPredicate, 38, 127, 5, // Skip to: 1847 -/* 440 */ MCD_OPC_CheckField, 6, 5, 0, 121, 5, // Skip to: 1847 -/* 446 */ MCD_OPC_Decode, 174, 11, 35, // Opcode: SELEQZ -/* 450 */ MCD_OPC_FilterValue, 55, 113, 5, // Skip to: 1847 -/* 454 */ MCD_OPC_CheckPredicate, 38, 109, 5, // Skip to: 1847 -/* 458 */ MCD_OPC_CheckField, 6, 5, 0, 103, 5, // Skip to: 1847 -/* 464 */ MCD_OPC_Decode, 178, 11, 35, // Opcode: SELNEZ -/* 468 */ MCD_OPC_FilterValue, 1, 47, 0, // Skip to: 519 -/* 472 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 475 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 488 -/* 479 */ MCD_OPC_CheckPredicate, 37, 84, 5, // Skip to: 1847 -/* 483 */ MCD_OPC_Decode, 163, 4, 225, 1, // Opcode: DAHI -/* 488 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 506 -/* 492 */ MCD_OPC_CheckPredicate, 36, 71, 5, // Skip to: 1847 -/* 496 */ MCD_OPC_CheckField, 21, 5, 0, 65, 5, // Skip to: 1847 -/* 502 */ MCD_OPC_Decode, 167, 1, 75, // Opcode: BAL -/* 506 */ MCD_OPC_FilterValue, 30, 57, 5, // Skip to: 1847 -/* 510 */ MCD_OPC_CheckPredicate, 37, 53, 5, // Skip to: 1847 -/* 514 */ MCD_OPC_Decode, 165, 4, 225, 1, // Opcode: DATI -/* 519 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 532 -/* 523 */ MCD_OPC_CheckPredicate, 36, 40, 5, // Skip to: 1847 -/* 527 */ MCD_OPC_Decode, 220, 1, 226, 1, // Opcode: BGEZALC -/* 532 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 545 -/* 536 */ MCD_OPC_CheckPredicate, 36, 27, 5, // Skip to: 1847 -/* 540 */ MCD_OPC_Decode, 134, 2, 227, 1, // Opcode: BLTZALC -/* 545 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 558 -/* 549 */ MCD_OPC_CheckPredicate, 36, 14, 5, // Skip to: 1847 -/* 553 */ MCD_OPC_Decode, 208, 1, 228, 1, // Opcode: BEQC -/* 558 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 570 -/* 562 */ MCD_OPC_CheckPredicate, 36, 1, 5, // Skip to: 1847 -/* 566 */ MCD_OPC_Decode, 137, 1, 47, // Opcode: AUI -/* 570 */ MCD_OPC_FilterValue, 17, 5, 3, // Skip to: 1347 -/* 574 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 577 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 590 -/* 581 */ MCD_OPC_CheckPredicate, 36, 238, 4, // Skip to: 1847 -/* 585 */ MCD_OPC_Decode, 180, 1, 229, 1, // Opcode: BC1EQZ -/* 590 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 603 -/* 594 */ MCD_OPC_CheckPredicate, 36, 225, 4, // Skip to: 1847 -/* 598 */ MCD_OPC_Decode, 184, 1, 229, 1, // Opcode: BC1NEZ -/* 603 */ MCD_OPC_FilterValue, 16, 150, 0, // Skip to: 757 -/* 607 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 610 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 623 -/* 614 */ MCD_OPC_CheckPredicate, 36, 205, 4, // Skip to: 1847 -/* 618 */ MCD_OPC_Decode, 183, 11, 230, 1, // Opcode: SEL_S -/* 623 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 635 -/* 627 */ MCD_OPC_CheckPredicate, 36, 192, 4, // Skip to: 1847 -/* 631 */ MCD_OPC_Decode, 177, 11, 93, // Opcode: SELEQZ_S -/* 635 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 647 -/* 639 */ MCD_OPC_CheckPredicate, 36, 180, 4, // Skip to: 1847 -/* 643 */ MCD_OPC_Decode, 181, 11, 93, // Opcode: SELNEZ_S -/* 647 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 660 -/* 651 */ MCD_OPC_CheckPredicate, 36, 168, 4, // Skip to: 1847 -/* 655 */ MCD_OPC_Decode, 132, 8, 231, 1, // Opcode: MADDF_S -/* 660 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 673 -/* 664 */ MCD_OPC_CheckPredicate, 36, 155, 4, // Skip to: 1847 -/* 668 */ MCD_OPC_Decode, 150, 9, 231, 1, // Opcode: MSUBF_S -/* 673 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 691 -/* 677 */ MCD_OPC_CheckPredicate, 36, 142, 4, // Skip to: 1847 -/* 681 */ MCD_OPC_CheckField, 16, 5, 0, 136, 4, // Skip to: 1847 -/* 687 */ MCD_OPC_Decode, 246, 10, 94, // Opcode: RINT_S -/* 691 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 709 -/* 695 */ MCD_OPC_CheckPredicate, 36, 124, 4, // Skip to: 1847 -/* 699 */ MCD_OPC_CheckField, 16, 5, 0, 118, 4, // Skip to: 1847 -/* 705 */ MCD_OPC_Decode, 244, 2, 94, // Opcode: CLASS_S -/* 709 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 721 -/* 713 */ MCD_OPC_CheckPredicate, 36, 106, 4, // Skip to: 1847 -/* 717 */ MCD_OPC_Decode, 211, 8, 93, // Opcode: MIN_S -/* 721 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 733 -/* 725 */ MCD_OPC_CheckPredicate, 36, 94, 4, // Skip to: 1847 -/* 729 */ MCD_OPC_Decode, 170, 8, 93, // Opcode: MAX_S -/* 733 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 745 -/* 737 */ MCD_OPC_CheckPredicate, 36, 82, 4, // Skip to: 1847 -/* 741 */ MCD_OPC_Decode, 197, 8, 93, // Opcode: MINA_S -/* 745 */ MCD_OPC_FilterValue, 31, 74, 4, // Skip to: 1847 -/* 749 */ MCD_OPC_CheckPredicate, 36, 70, 4, // Skip to: 1847 -/* 753 */ MCD_OPC_Decode, 156, 8, 93, // Opcode: MAXA_S -/* 757 */ MCD_OPC_FilterValue, 17, 156, 0, // Skip to: 917 -/* 761 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 764 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 777 -/* 768 */ MCD_OPC_CheckPredicate, 36, 51, 4, // Skip to: 1847 -/* 772 */ MCD_OPC_Decode, 182, 11, 232, 1, // Opcode: SEL_D -/* 777 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 790 -/* 781 */ MCD_OPC_CheckPredicate, 36, 38, 4, // Skip to: 1847 -/* 785 */ MCD_OPC_Decode, 176, 11, 233, 1, // Opcode: SELEQZ_D -/* 790 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 803 -/* 794 */ MCD_OPC_CheckPredicate, 36, 25, 4, // Skip to: 1847 -/* 798 */ MCD_OPC_Decode, 180, 11, 233, 1, // Opcode: SELNEZ_D -/* 803 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 816 -/* 807 */ MCD_OPC_CheckPredicate, 36, 12, 4, // Skip to: 1847 -/* 811 */ MCD_OPC_Decode, 131, 8, 234, 1, // Opcode: MADDF_D -/* 816 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 829 -/* 820 */ MCD_OPC_CheckPredicate, 36, 255, 3, // Skip to: 1847 -/* 824 */ MCD_OPC_Decode, 149, 9, 234, 1, // Opcode: MSUBF_D -/* 829 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 847 -/* 833 */ MCD_OPC_CheckPredicate, 36, 242, 3, // Skip to: 1847 -/* 837 */ MCD_OPC_CheckField, 16, 5, 0, 236, 3, // Skip to: 1847 -/* 843 */ MCD_OPC_Decode, 245, 10, 105, // Opcode: RINT_D -/* 847 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 865 -/* 851 */ MCD_OPC_CheckPredicate, 36, 224, 3, // Skip to: 1847 -/* 855 */ MCD_OPC_CheckField, 16, 5, 0, 218, 3, // Skip to: 1847 -/* 861 */ MCD_OPC_Decode, 243, 2, 105, // Opcode: CLASS_D -/* 865 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 878 -/* 869 */ MCD_OPC_CheckPredicate, 36, 206, 3, // Skip to: 1847 -/* 873 */ MCD_OPC_Decode, 210, 8, 233, 1, // Opcode: MIN_D -/* 878 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 891 -/* 882 */ MCD_OPC_CheckPredicate, 36, 193, 3, // Skip to: 1847 -/* 886 */ MCD_OPC_Decode, 169, 8, 233, 1, // Opcode: MAX_D -/* 891 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 904 -/* 895 */ MCD_OPC_CheckPredicate, 36, 180, 3, // Skip to: 1847 -/* 899 */ MCD_OPC_Decode, 196, 8, 233, 1, // Opcode: MINA_D -/* 904 */ MCD_OPC_FilterValue, 31, 171, 3, // Skip to: 1847 -/* 908 */ MCD_OPC_CheckPredicate, 36, 167, 3, // Skip to: 1847 -/* 912 */ MCD_OPC_Decode, 155, 8, 233, 1, // Opcode: MAXA_D -/* 917 */ MCD_OPC_FilterValue, 20, 211, 0, // Skip to: 1132 -/* 921 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 924 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 937 -/* 928 */ MCD_OPC_CheckPredicate, 36, 147, 3, // Skip to: 1847 -/* 932 */ MCD_OPC_Decode, 168, 3, 235, 1, // Opcode: CMP_F_S -/* 937 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 950 -/* 941 */ MCD_OPC_CheckPredicate, 36, 134, 3, // Skip to: 1847 -/* 945 */ MCD_OPC_Decode, 198, 3, 235, 1, // Opcode: CMP_UN_S -/* 950 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 963 -/* 954 */ MCD_OPC_CheckPredicate, 36, 121, 3, // Skip to: 1847 -/* 958 */ MCD_OPC_Decode, 166, 3, 235, 1, // Opcode: CMP_EQ_S -/* 963 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 976 -/* 967 */ MCD_OPC_CheckPredicate, 36, 108, 3, // Skip to: 1847 -/* 971 */ MCD_OPC_Decode, 192, 3, 235, 1, // Opcode: CMP_UEQ_S -/* 976 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 989 -/* 980 */ MCD_OPC_CheckPredicate, 36, 95, 3, // Skip to: 1847 -/* 984 */ MCD_OPC_Decode, 174, 3, 235, 1, // Opcode: CMP_LT_S -/* 989 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1002 -/* 993 */ MCD_OPC_CheckPredicate, 36, 82, 3, // Skip to: 1847 -/* 997 */ MCD_OPC_Decode, 196, 3, 235, 1, // Opcode: CMP_ULT_S -/* 1002 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1015 -/* 1006 */ MCD_OPC_CheckPredicate, 36, 69, 3, // Skip to: 1847 -/* 1010 */ MCD_OPC_Decode, 171, 3, 235, 1, // Opcode: CMP_LE_S -/* 1015 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1028 -/* 1019 */ MCD_OPC_CheckPredicate, 36, 56, 3, // Skip to: 1847 -/* 1023 */ MCD_OPC_Decode, 194, 3, 235, 1, // Opcode: CMP_ULE_S -/* 1028 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1041 -/* 1032 */ MCD_OPC_CheckPredicate, 36, 43, 3, // Skip to: 1847 -/* 1036 */ MCD_OPC_Decode, 176, 3, 235, 1, // Opcode: CMP_SAF_S -/* 1041 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1054 -/* 1045 */ MCD_OPC_CheckPredicate, 36, 30, 3, // Skip to: 1847 -/* 1049 */ MCD_OPC_Decode, 190, 3, 235, 1, // Opcode: CMP_SUN_S -/* 1054 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1067 -/* 1058 */ MCD_OPC_CheckPredicate, 36, 17, 3, // Skip to: 1847 -/* 1062 */ MCD_OPC_Decode, 178, 3, 235, 1, // Opcode: CMP_SEQ_S -/* 1067 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1080 -/* 1071 */ MCD_OPC_CheckPredicate, 36, 4, 3, // Skip to: 1847 -/* 1075 */ MCD_OPC_Decode, 184, 3, 235, 1, // Opcode: CMP_SUEQ_S -/* 1080 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1093 -/* 1084 */ MCD_OPC_CheckPredicate, 36, 247, 2, // Skip to: 1847 -/* 1088 */ MCD_OPC_Decode, 182, 3, 235, 1, // Opcode: CMP_SLT_S -/* 1093 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1106 -/* 1097 */ MCD_OPC_CheckPredicate, 36, 234, 2, // Skip to: 1847 -/* 1101 */ MCD_OPC_Decode, 188, 3, 235, 1, // Opcode: CMP_SULT_S -/* 1106 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1119 -/* 1110 */ MCD_OPC_CheckPredicate, 36, 221, 2, // Skip to: 1847 -/* 1114 */ MCD_OPC_Decode, 180, 3, 235, 1, // Opcode: CMP_SLE_S -/* 1119 */ MCD_OPC_FilterValue, 15, 212, 2, // Skip to: 1847 -/* 1123 */ MCD_OPC_CheckPredicate, 36, 208, 2, // Skip to: 1847 -/* 1127 */ MCD_OPC_Decode, 186, 3, 235, 1, // Opcode: CMP_SULE_S -/* 1132 */ MCD_OPC_FilterValue, 21, 199, 2, // Skip to: 1847 -/* 1136 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1139 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1152 -/* 1143 */ MCD_OPC_CheckPredicate, 36, 188, 2, // Skip to: 1847 -/* 1147 */ MCD_OPC_Decode, 167, 3, 236, 1, // Opcode: CMP_F_D -/* 1152 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1165 -/* 1156 */ MCD_OPC_CheckPredicate, 36, 175, 2, // Skip to: 1847 -/* 1160 */ MCD_OPC_Decode, 197, 3, 236, 1, // Opcode: CMP_UN_D -/* 1165 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1178 -/* 1169 */ MCD_OPC_CheckPredicate, 36, 162, 2, // Skip to: 1847 -/* 1173 */ MCD_OPC_Decode, 164, 3, 236, 1, // Opcode: CMP_EQ_D -/* 1178 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1191 -/* 1182 */ MCD_OPC_CheckPredicate, 36, 149, 2, // Skip to: 1847 -/* 1186 */ MCD_OPC_Decode, 191, 3, 236, 1, // Opcode: CMP_UEQ_D -/* 1191 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1204 -/* 1195 */ MCD_OPC_CheckPredicate, 36, 136, 2, // Skip to: 1847 -/* 1199 */ MCD_OPC_Decode, 172, 3, 236, 1, // Opcode: CMP_LT_D -/* 1204 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1217 -/* 1208 */ MCD_OPC_CheckPredicate, 36, 123, 2, // Skip to: 1847 -/* 1212 */ MCD_OPC_Decode, 195, 3, 236, 1, // Opcode: CMP_ULT_D -/* 1217 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1230 -/* 1221 */ MCD_OPC_CheckPredicate, 36, 110, 2, // Skip to: 1847 -/* 1225 */ MCD_OPC_Decode, 169, 3, 236, 1, // Opcode: CMP_LE_D -/* 1230 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1243 -/* 1234 */ MCD_OPC_CheckPredicate, 36, 97, 2, // Skip to: 1847 -/* 1238 */ MCD_OPC_Decode, 193, 3, 236, 1, // Opcode: CMP_ULE_D -/* 1243 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1256 -/* 1247 */ MCD_OPC_CheckPredicate, 36, 84, 2, // Skip to: 1847 -/* 1251 */ MCD_OPC_Decode, 175, 3, 236, 1, // Opcode: CMP_SAF_D -/* 1256 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1269 -/* 1260 */ MCD_OPC_CheckPredicate, 36, 71, 2, // Skip to: 1847 -/* 1264 */ MCD_OPC_Decode, 189, 3, 236, 1, // Opcode: CMP_SUN_D -/* 1269 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1282 -/* 1273 */ MCD_OPC_CheckPredicate, 36, 58, 2, // Skip to: 1847 -/* 1277 */ MCD_OPC_Decode, 177, 3, 236, 1, // Opcode: CMP_SEQ_D -/* 1282 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1295 -/* 1286 */ MCD_OPC_CheckPredicate, 36, 45, 2, // Skip to: 1847 -/* 1290 */ MCD_OPC_Decode, 183, 3, 236, 1, // Opcode: CMP_SUEQ_D -/* 1295 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1308 -/* 1299 */ MCD_OPC_CheckPredicate, 36, 32, 2, // Skip to: 1847 -/* 1303 */ MCD_OPC_Decode, 181, 3, 236, 1, // Opcode: CMP_SLT_D -/* 1308 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1321 -/* 1312 */ MCD_OPC_CheckPredicate, 36, 19, 2, // Skip to: 1847 -/* 1316 */ MCD_OPC_Decode, 187, 3, 236, 1, // Opcode: CMP_SULT_D -/* 1321 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1334 -/* 1325 */ MCD_OPC_CheckPredicate, 36, 6, 2, // Skip to: 1847 -/* 1329 */ MCD_OPC_Decode, 179, 3, 236, 1, // Opcode: CMP_SLE_D -/* 1334 */ MCD_OPC_FilterValue, 15, 253, 1, // Skip to: 1847 -/* 1338 */ MCD_OPC_CheckPredicate, 36, 249, 1, // Skip to: 1847 -/* 1342 */ MCD_OPC_Decode, 185, 3, 236, 1, // Opcode: CMP_SULE_D -/* 1347 */ MCD_OPC_FilterValue, 18, 81, 0, // Skip to: 1432 -/* 1351 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1354 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1367 -/* 1358 */ MCD_OPC_CheckPredicate, 36, 229, 1, // Skip to: 1847 -/* 1362 */ MCD_OPC_Decode, 188, 1, 237, 1, // Opcode: BC2EQZ -/* 1367 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1380 -/* 1371 */ MCD_OPC_CheckPredicate, 36, 216, 1, // Skip to: 1847 -/* 1375 */ MCD_OPC_Decode, 219, 7, 238, 1, // Opcode: LWC2_R6 -/* 1380 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1393 -/* 1384 */ MCD_OPC_CheckPredicate, 36, 203, 1, // Skip to: 1847 -/* 1388 */ MCD_OPC_Decode, 241, 12, 238, 1, // Opcode: SWC2_R6 -/* 1393 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1406 -/* 1397 */ MCD_OPC_CheckPredicate, 36, 190, 1, // Skip to: 1847 -/* 1401 */ MCD_OPC_Decode, 191, 1, 237, 1, // Opcode: BC2NEZ -/* 1406 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1419 -/* 1410 */ MCD_OPC_CheckPredicate, 36, 177, 1, // Skip to: 1847 -/* 1414 */ MCD_OPC_Decode, 166, 7, 238, 1, // Opcode: LDC2_R6 -/* 1419 */ MCD_OPC_FilterValue, 15, 168, 1, // Skip to: 1847 -/* 1423 */ MCD_OPC_CheckPredicate, 36, 164, 1, // Skip to: 1847 -/* 1427 */ MCD_OPC_Decode, 160, 11, 238, 1, // Opcode: SDC2_R6 -/* 1432 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 1445 -/* 1436 */ MCD_OPC_CheckPredicate, 36, 151, 1, // Skip to: 1847 -/* 1440 */ MCD_OPC_Decode, 224, 1, 239, 1, // Opcode: BGEZC -/* 1445 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 1458 -/* 1449 */ MCD_OPC_CheckPredicate, 36, 138, 1, // Skip to: 1847 -/* 1453 */ MCD_OPC_Decode, 138, 2, 240, 1, // Opcode: BLTZC -/* 1458 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1471 -/* 1462 */ MCD_OPC_CheckPredicate, 36, 125, 1, // Skip to: 1847 -/* 1466 */ MCD_OPC_Decode, 147, 2, 241, 1, // Opcode: BNEC -/* 1471 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 1484 -/* 1475 */ MCD_OPC_CheckPredicate, 37, 112, 1, // Skip to: 1847 -/* 1479 */ MCD_OPC_Decode, 166, 4, 242, 1, // Opcode: DAUI -/* 1484 */ MCD_OPC_FilterValue, 31, 182, 0, // Skip to: 1670 -/* 1488 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1491 */ MCD_OPC_FilterValue, 32, 40, 0, // Skip to: 1535 -/* 1495 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 1498 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1523 -/* 1502 */ MCD_OPC_CheckPredicate, 36, 85, 1, // Skip to: 1847 -/* 1506 */ MCD_OPC_CheckField, 21, 5, 0, 79, 1, // Skip to: 1847 -/* 1512 */ MCD_OPC_CheckField, 6, 2, 0, 73, 1, // Skip to: 1847 -/* 1518 */ MCD_OPC_Decode, 250, 1, 205, 1, // Opcode: BITSWAP -/* 1523 */ MCD_OPC_FilterValue, 2, 64, 1, // Skip to: 1847 -/* 1527 */ MCD_OPC_CheckPredicate, 36, 60, 1, // Skip to: 1847 -/* 1531 */ MCD_OPC_Decode, 81, 221, 1, // Opcode: ALIGN -/* 1535 */ MCD_OPC_FilterValue, 36, 41, 0, // Skip to: 1580 -/* 1539 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... -/* 1542 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1567 -/* 1546 */ MCD_OPC_CheckPredicate, 37, 41, 1, // Skip to: 1847 -/* 1550 */ MCD_OPC_CheckField, 21, 5, 0, 35, 1, // Skip to: 1847 -/* 1556 */ MCD_OPC_CheckField, 6, 3, 0, 29, 1, // Skip to: 1847 -/* 1562 */ MCD_OPC_Decode, 167, 4, 243, 1, // Opcode: DBITSWAP -/* 1567 */ MCD_OPC_FilterValue, 1, 20, 1, // Skip to: 1847 -/* 1571 */ MCD_OPC_CheckPredicate, 37, 16, 1, // Skip to: 1847 -/* 1575 */ MCD_OPC_Decode, 164, 4, 244, 1, // Opcode: DALIGN -/* 1580 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1599 -/* 1584 */ MCD_OPC_CheckPredicate, 36, 3, 1, // Skip to: 1847 -/* 1588 */ MCD_OPC_CheckField, 6, 1, 0, 253, 0, // Skip to: 1847 -/* 1594 */ MCD_OPC_Decode, 222, 2, 245, 1, // Opcode: CACHE_R6 -/* 1599 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 1612 -/* 1603 */ MCD_OPC_CheckPredicate, 36, 240, 0, // Skip to: 1847 -/* 1607 */ MCD_OPC_Decode, 150, 11, 246, 1, // Opcode: SC_R6 -/* 1612 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 1625 -/* 1616 */ MCD_OPC_CheckPredicate, 36, 227, 0, // Skip to: 1847 -/* 1620 */ MCD_OPC_Decode, 148, 11, 246, 1, // Opcode: SCD_R6 -/* 1625 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 1644 -/* 1629 */ MCD_OPC_CheckPredicate, 36, 214, 0, // Skip to: 1847 -/* 1633 */ MCD_OPC_CheckField, 6, 1, 0, 208, 0, // Skip to: 1847 -/* 1639 */ MCD_OPC_Decode, 183, 10, 245, 1, // Opcode: PREF_R6 -/* 1644 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 1657 -/* 1648 */ MCD_OPC_CheckPredicate, 36, 195, 0, // Skip to: 1847 -/* 1652 */ MCD_OPC_Decode, 197, 7, 246, 1, // Opcode: LL_R6 -/* 1657 */ MCD_OPC_FilterValue, 55, 186, 0, // Skip to: 1847 -/* 1661 */ MCD_OPC_CheckPredicate, 36, 182, 0, // Skip to: 1847 -/* 1665 */ MCD_OPC_Decode, 195, 7, 246, 1, // Opcode: LLD_R6 -/* 1670 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 1683 -/* 1674 */ MCD_OPC_CheckPredicate, 36, 169, 0, // Skip to: 1847 -/* 1678 */ MCD_OPC_Decode, 175, 1, 247, 1, // Opcode: BC -/* 1683 */ MCD_OPC_FilterValue, 54, 23, 0, // Skip to: 1710 -/* 1687 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1701 -/* 1691 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1701 -/* 1697 */ MCD_OPC_Decode, 135, 7, 52, // Opcode: JIC -/* 1701 */ MCD_OPC_CheckPredicate, 36, 142, 0, // Skip to: 1847 -/* 1705 */ MCD_OPC_Decode, 212, 1, 248, 1, // Opcode: BEQZC -/* 1710 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1723 -/* 1714 */ MCD_OPC_CheckPredicate, 36, 129, 0, // Skip to: 1847 -/* 1718 */ MCD_OPC_Decode, 168, 1, 247, 1, // Opcode: BALC -/* 1723 */ MCD_OPC_FilterValue, 59, 93, 0, // Skip to: 1820 -/* 1727 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... -/* 1730 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1742 -/* 1734 */ MCD_OPC_CheckPredicate, 36, 109, 0, // Skip to: 1847 -/* 1738 */ MCD_OPC_Decode, 26, 249, 1, // Opcode: ADDIUPC -/* 1742 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1755 -/* 1746 */ MCD_OPC_CheckPredicate, 36, 97, 0, // Skip to: 1847 -/* 1750 */ MCD_OPC_Decode, 228, 7, 249, 1, // Opcode: LWPC -/* 1755 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1768 -/* 1759 */ MCD_OPC_CheckPredicate, 36, 84, 0, // Skip to: 1847 -/* 1763 */ MCD_OPC_Decode, 234, 7, 249, 1, // Opcode: LWUPC -/* 1768 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 1847 -/* 1772 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 1775 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1788 -/* 1779 */ MCD_OPC_CheckPredicate, 37, 64, 0, // Skip to: 1847 -/* 1783 */ MCD_OPC_Decode, 173, 7, 250, 1, // Opcode: LDPC -/* 1788 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 1847 -/* 1792 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1808 -/* 1799 */ MCD_OPC_CheckPredicate, 36, 44, 0, // Skip to: 1847 -/* 1803 */ MCD_OPC_Decode, 138, 1, 251, 1, // Opcode: AUIPC -/* 1808 */ MCD_OPC_FilterValue, 3, 35, 0, // Skip to: 1847 -/* 1812 */ MCD_OPC_CheckPredicate, 36, 31, 0, // Skip to: 1847 -/* 1816 */ MCD_OPC_Decode, 82, 251, 1, // Opcode: ALUIPC -/* 1820 */ MCD_OPC_FilterValue, 62, 23, 0, // Skip to: 1847 -/* 1824 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1838 -/* 1828 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1838 -/* 1834 */ MCD_OPC_Decode, 134, 7, 52, // Opcode: JIALC -/* 1838 */ MCD_OPC_CheckPredicate, 36, 5, 0, // Skip to: 1847 -/* 1842 */ MCD_OPC_Decode, 159, 2, 248, 1, // Opcode: BNEZC -/* 1847 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 0, 14, 2, 0, // Skip to: 534 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 33 +/* 16 */ MCD_OPC_CheckPredicate, 75, 133, 9, 0, // Skip to: 2458 +/* 21 */ MCD_OPC_CheckField, 8, 3, 0, 126, 9, 0, // Skip to: 2458 +/* 28 */ MCD_OPC_Decode, 250, 15, 185, 1, // Opcode: LSA_R6 +/* 33 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 55 +/* 38 */ MCD_OPC_CheckPredicate, 75, 111, 9, 0, // Skip to: 2458 +/* 43 */ MCD_OPC_CheckField, 6, 15, 16, 104, 9, 0, // Skip to: 2458 +/* 50 */ MCD_OPC_Decode, 143, 15, 186, 1, // Opcode: JR_HB_R6 +/* 55 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 70 +/* 60 */ MCD_OPC_CheckPredicate, 76, 89, 9, 0, // Skip to: 2458 +/* 65 */ MCD_OPC_Decode, 226, 20, 188, 1, // Opcode: SDBBP_R6 +/* 70 */ MCD_OPC_FilterValue, 16, 23, 0, 0, // Skip to: 98 +/* 75 */ MCD_OPC_CheckPredicate, 75, 74, 9, 0, // Skip to: 2458 +/* 80 */ MCD_OPC_CheckField, 16, 5, 0, 67, 9, 0, // Skip to: 2458 +/* 87 */ MCD_OPC_CheckField, 6, 5, 1, 60, 9, 0, // Skip to: 2458 +/* 94 */ MCD_OPC_Decode, 197, 9, 25, // Opcode: CLZ_R6 +/* 98 */ MCD_OPC_FilterValue, 17, 23, 0, 0, // Skip to: 126 +/* 103 */ MCD_OPC_CheckPredicate, 75, 46, 9, 0, // Skip to: 2458 +/* 108 */ MCD_OPC_CheckField, 16, 5, 0, 39, 9, 0, // Skip to: 2458 +/* 115 */ MCD_OPC_CheckField, 6, 5, 1, 32, 9, 0, // Skip to: 2458 +/* 122 */ MCD_OPC_Decode, 176, 9, 25, // Opcode: CLO_R6 +/* 126 */ MCD_OPC_FilterValue, 18, 23, 0, 0, // Skip to: 154 +/* 131 */ MCD_OPC_CheckPredicate, 77, 18, 9, 0, // Skip to: 2458 +/* 136 */ MCD_OPC_CheckField, 16, 5, 0, 11, 9, 0, // Skip to: 2458 +/* 143 */ MCD_OPC_CheckField, 6, 5, 1, 4, 9, 0, // Skip to: 2458 +/* 150 */ MCD_OPC_Decode, 203, 11, 26, // Opcode: DCLZ_R6 +/* 154 */ MCD_OPC_FilterValue, 19, 23, 0, 0, // Skip to: 182 +/* 159 */ MCD_OPC_CheckPredicate, 77, 246, 8, 0, // Skip to: 2458 +/* 164 */ MCD_OPC_CheckField, 16, 5, 0, 239, 8, 0, // Skip to: 2458 +/* 171 */ MCD_OPC_CheckField, 6, 5, 1, 232, 8, 0, // Skip to: 2458 +/* 178 */ MCD_OPC_Decode, 201, 11, 26, // Opcode: DCLO_R6 +/* 182 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 204 +/* 187 */ MCD_OPC_CheckPredicate, 77, 218, 8, 0, // Skip to: 2458 +/* 192 */ MCD_OPC_CheckField, 8, 3, 0, 211, 8, 0, // Skip to: 2458 +/* 199 */ MCD_OPC_Decode, 236, 11, 194, 1, // Opcode: DLSA_R6 +/* 204 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 240 +/* 209 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 212 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 226 +/* 217 */ MCD_OPC_CheckPredicate, 76, 188, 8, 0, // Skip to: 2458 +/* 222 */ MCD_OPC_Decode, 252, 18, 61, // Opcode: MUL_R6 +/* 226 */ MCD_OPC_FilterValue, 3, 179, 8, 0, // Skip to: 2458 +/* 231 */ MCD_OPC_CheckPredicate, 76, 174, 8, 0, // Skip to: 2458 +/* 236 */ MCD_OPC_Decode, 199, 18, 61, // Opcode: MUH +/* 240 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 276 +/* 245 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 248 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 262 +/* 253 */ MCD_OPC_CheckPredicate, 76, 152, 8, 0, // Skip to: 2458 +/* 258 */ MCD_OPC_Decode, 238, 18, 61, // Opcode: MULU +/* 262 */ MCD_OPC_FilterValue, 3, 143, 8, 0, // Skip to: 2458 +/* 267 */ MCD_OPC_CheckPredicate, 76, 138, 8, 0, // Skip to: 2458 +/* 272 */ MCD_OPC_Decode, 200, 18, 61, // Opcode: MUHU +/* 276 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 312 +/* 281 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 284 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 298 +/* 289 */ MCD_OPC_CheckPredicate, 76, 116, 8, 0, // Skip to: 2458 +/* 294 */ MCD_OPC_Decode, 218, 11, 61, // Opcode: DIV +/* 298 */ MCD_OPC_FilterValue, 3, 107, 8, 0, // Skip to: 2458 +/* 303 */ MCD_OPC_CheckPredicate, 76, 102, 8, 0, // Skip to: 2458 +/* 308 */ MCD_OPC_Decode, 192, 17, 61, // Opcode: MOD +/* 312 */ MCD_OPC_FilterValue, 27, 31, 0, 0, // Skip to: 348 +/* 317 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 320 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 334 +/* 325 */ MCD_OPC_CheckPredicate, 76, 80, 8, 0, // Skip to: 2458 +/* 330 */ MCD_OPC_Decode, 219, 11, 61, // Opcode: DIVU +/* 334 */ MCD_OPC_FilterValue, 3, 71, 8, 0, // Skip to: 2458 +/* 339 */ MCD_OPC_CheckPredicate, 76, 66, 8, 0, // Skip to: 2458 +/* 344 */ MCD_OPC_Decode, 195, 17, 61, // Opcode: MODU +/* 348 */ MCD_OPC_FilterValue, 28, 31, 0, 0, // Skip to: 384 +/* 353 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 356 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 370 +/* 361 */ MCD_OPC_CheckPredicate, 77, 44, 8, 0, // Skip to: 2458 +/* 366 */ MCD_OPC_Decode, 129, 12, 23, // Opcode: DMUL_R6 +/* 370 */ MCD_OPC_FilterValue, 3, 35, 8, 0, // Skip to: 2458 +/* 375 */ MCD_OPC_CheckPredicate, 77, 30, 8, 0, // Skip to: 2458 +/* 380 */ MCD_OPC_Decode, 251, 11, 23, // Opcode: DMUH +/* 384 */ MCD_OPC_FilterValue, 29, 31, 0, 0, // Skip to: 420 +/* 389 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 392 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 406 +/* 397 */ MCD_OPC_CheckPredicate, 77, 8, 8, 0, // Skip to: 2458 +/* 402 */ MCD_OPC_Decode, 128, 12, 23, // Opcode: DMULU +/* 406 */ MCD_OPC_FilterValue, 3, 255, 7, 0, // Skip to: 2458 +/* 411 */ MCD_OPC_CheckPredicate, 77, 250, 7, 0, // Skip to: 2458 +/* 416 */ MCD_OPC_Decode, 252, 11, 23, // Opcode: DMUHU +/* 420 */ MCD_OPC_FilterValue, 30, 31, 0, 0, // Skip to: 456 +/* 425 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 428 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 442 +/* 433 */ MCD_OPC_CheckPredicate, 77, 228, 7, 0, // Skip to: 2458 +/* 438 */ MCD_OPC_Decode, 204, 11, 23, // Opcode: DDIV +/* 442 */ MCD_OPC_FilterValue, 3, 219, 7, 0, // Skip to: 2458 +/* 447 */ MCD_OPC_CheckPredicate, 77, 214, 7, 0, // Skip to: 2458 +/* 452 */ MCD_OPC_Decode, 242, 11, 23, // Opcode: DMOD +/* 456 */ MCD_OPC_FilterValue, 31, 31, 0, 0, // Skip to: 492 +/* 461 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 464 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 478 +/* 469 */ MCD_OPC_CheckPredicate, 77, 192, 7, 0, // Skip to: 2458 +/* 474 */ MCD_OPC_Decode, 205, 11, 23, // Opcode: DDIVU +/* 478 */ MCD_OPC_FilterValue, 3, 183, 7, 0, // Skip to: 2458 +/* 483 */ MCD_OPC_CheckPredicate, 77, 178, 7, 0, // Skip to: 2458 +/* 488 */ MCD_OPC_Decode, 243, 11, 23, // Opcode: DMODU +/* 492 */ MCD_OPC_FilterValue, 53, 16, 0, 0, // Skip to: 513 +/* 497 */ MCD_OPC_CheckPredicate, 78, 164, 7, 0, // Skip to: 2458 +/* 502 */ MCD_OPC_CheckField, 6, 5, 0, 157, 7, 0, // Skip to: 2458 +/* 509 */ MCD_OPC_Decode, 250, 20, 61, // Opcode: SELEQZ +/* 513 */ MCD_OPC_FilterValue, 55, 148, 7, 0, // Skip to: 2458 +/* 518 */ MCD_OPC_CheckPredicate, 78, 143, 7, 0, // Skip to: 2458 +/* 523 */ MCD_OPC_CheckField, 6, 5, 0, 136, 7, 0, // Skip to: 2458 +/* 530 */ MCD_OPC_Decode, 129, 21, 61, // Opcode: SELNEZ +/* 534 */ MCD_OPC_FilterValue, 1, 77, 0, 0, // Skip to: 616 +/* 539 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 542 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 557 +/* 547 */ MCD_OPC_CheckPredicate, 77, 114, 7, 0, // Skip to: 2458 +/* 552 */ MCD_OPC_Decode, 195, 11, 221, 2, // Opcode: DAHI +/* 557 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 579 +/* 562 */ MCD_OPC_CheckPredicate, 75, 99, 7, 0, // Skip to: 2458 +/* 567 */ MCD_OPC_CheckField, 21, 5, 0, 92, 7, 0, // Skip to: 2458 +/* 574 */ MCD_OPC_Decode, 147, 7, 198, 1, // Opcode: BAL +/* 579 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 601 +/* 584 */ MCD_OPC_CheckPredicate, 76, 77, 7, 0, // Skip to: 2458 +/* 589 */ MCD_OPC_CheckField, 21, 5, 0, 70, 7, 0, // Skip to: 2458 +/* 596 */ MCD_OPC_Decode, 208, 21, 222, 2, // Opcode: SIGRIE +/* 601 */ MCD_OPC_FilterValue, 30, 60, 7, 0, // Skip to: 2458 +/* 606 */ MCD_OPC_CheckPredicate, 77, 55, 7, 0, // Skip to: 2458 +/* 611 */ MCD_OPC_Decode, 197, 11, 221, 2, // Opcode: DATI +/* 616 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 631 +/* 621 */ MCD_OPC_CheckPredicate, 76, 40, 7, 0, // Skip to: 2458 +/* 626 */ MCD_OPC_Decode, 222, 7, 223, 2, // Opcode: BGEZALC +/* 631 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 646 +/* 636 */ MCD_OPC_CheckPredicate, 76, 25, 7, 0, // Skip to: 2458 +/* 641 */ MCD_OPC_Decode, 156, 8, 224, 2, // Opcode: BLTZALC +/* 646 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 661 +/* 651 */ MCD_OPC_CheckPredicate, 76, 10, 7, 0, // Skip to: 2458 +/* 656 */ MCD_OPC_Decode, 190, 7, 225, 2, // Opcode: BEQC +/* 661 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 676 +/* 666 */ MCD_OPC_CheckPredicate, 75, 251, 6, 0, // Skip to: 2458 +/* 671 */ MCD_OPC_Decode, 244, 6, 203, 1, // Opcode: AUI +/* 676 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 726 +/* 681 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... +/* 684 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 705 +/* 689 */ MCD_OPC_CheckPredicate, 75, 228, 6, 0, // Skip to: 2458 +/* 694 */ MCD_OPC_CheckField, 21, 5, 11, 221, 6, 0, // Skip to: 2458 +/* 701 */ MCD_OPC_Decode, 223, 12, 92, // Opcode: EVP +/* 705 */ MCD_OPC_FilterValue, 36, 212, 6, 0, // Skip to: 2458 +/* 710 */ MCD_OPC_CheckPredicate, 75, 207, 6, 0, // Skip to: 2458 +/* 715 */ MCD_OPC_CheckField, 21, 5, 11, 200, 6, 0, // Skip to: 2458 +/* 722 */ MCD_OPC_Decode, 200, 12, 92, // Opcode: DVP +/* 726 */ MCD_OPC_FilterValue, 17, 135, 3, 0, // Skip to: 1634 +/* 731 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 734 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 749 +/* 739 */ MCD_OPC_CheckPredicate, 79, 178, 6, 0, // Skip to: 2458 +/* 744 */ MCD_OPC_Decode, 164, 7, 226, 2, // Opcode: BC1EQZ +/* 749 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 764 +/* 754 */ MCD_OPC_CheckPredicate, 79, 163, 6, 0, // Skip to: 2458 +/* 759 */ MCD_OPC_Decode, 169, 7, 226, 2, // Opcode: BC1NEZ +/* 764 */ MCD_OPC_FilterValue, 16, 182, 0, 0, // Skip to: 951 +/* 769 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 772 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 787 +/* 777 */ MCD_OPC_CheckPredicate, 79, 140, 6, 0, // Skip to: 2458 +/* 782 */ MCD_OPC_Decode, 138, 21, 227, 2, // Opcode: SEL_S +/* 787 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 802 +/* 792 */ MCD_OPC_CheckPredicate, 79, 125, 6, 0, // Skip to: 2458 +/* 797 */ MCD_OPC_Decode, 255, 20, 218, 1, // Opcode: SELEQZ_S +/* 802 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 817 +/* 807 */ MCD_OPC_CheckPredicate, 79, 110, 6, 0, // Skip to: 2458 +/* 812 */ MCD_OPC_Decode, 134, 21, 218, 1, // Opcode: SELNEZ_S +/* 817 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 832 +/* 822 */ MCD_OPC_CheckPredicate, 79, 95, 6, 0, // Skip to: 2458 +/* 827 */ MCD_OPC_Decode, 198, 16, 228, 2, // Opcode: MADDF_S +/* 832 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 847 +/* 837 */ MCD_OPC_CheckPredicate, 79, 80, 6, 0, // Skip to: 2458 +/* 842 */ MCD_OPC_Decode, 134, 18, 228, 2, // Opcode: MSUBF_S +/* 847 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 869 +/* 852 */ MCD_OPC_CheckPredicate, 79, 65, 6, 0, // Skip to: 2458 +/* 857 */ MCD_OPC_CheckField, 16, 5, 0, 58, 6, 0, // Skip to: 2458 +/* 864 */ MCD_OPC_Decode, 153, 20, 219, 1, // Opcode: RINT_S +/* 869 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 891 +/* 874 */ MCD_OPC_CheckPredicate, 79, 43, 6, 0, // Skip to: 2458 +/* 879 */ MCD_OPC_CheckField, 16, 5, 0, 36, 6, 0, // Skip to: 2458 +/* 886 */ MCD_OPC_Decode, 154, 9, 219, 1, // Opcode: CLASS_S +/* 891 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 906 +/* 896 */ MCD_OPC_CheckPredicate, 79, 21, 6, 0, // Skip to: 2458 +/* 901 */ MCD_OPC_Decode, 182, 17, 218, 1, // Opcode: MIN_S +/* 906 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 921 +/* 911 */ MCD_OPC_CheckPredicate, 79, 6, 6, 0, // Skip to: 2458 +/* 916 */ MCD_OPC_Decode, 246, 16, 218, 1, // Opcode: MAX_S +/* 921 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 936 +/* 926 */ MCD_OPC_CheckPredicate, 79, 247, 5, 0, // Skip to: 2458 +/* 931 */ MCD_OPC_Decode, 166, 17, 218, 1, // Opcode: MINA_S +/* 936 */ MCD_OPC_FilterValue, 31, 237, 5, 0, // Skip to: 2458 +/* 941 */ MCD_OPC_CheckPredicate, 79, 232, 5, 0, // Skip to: 2458 +/* 946 */ MCD_OPC_Decode, 230, 16, 218, 1, // Opcode: MAXA_S +/* 951 */ MCD_OPC_FilterValue, 17, 182, 0, 0, // Skip to: 1138 +/* 956 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 959 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 974 +/* 964 */ MCD_OPC_CheckPredicate, 79, 209, 5, 0, // Skip to: 2458 +/* 969 */ MCD_OPC_Decode, 136, 21, 229, 2, // Opcode: SEL_D +/* 974 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 989 +/* 979 */ MCD_OPC_CheckPredicate, 79, 194, 5, 0, // Skip to: 2458 +/* 984 */ MCD_OPC_Decode, 252, 20, 230, 2, // Opcode: SELEQZ_D +/* 989 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 1004 +/* 994 */ MCD_OPC_CheckPredicate, 79, 179, 5, 0, // Skip to: 2458 +/* 999 */ MCD_OPC_Decode, 131, 21, 230, 2, // Opcode: SELNEZ_D +/* 1004 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 1019 +/* 1009 */ MCD_OPC_CheckPredicate, 79, 164, 5, 0, // Skip to: 2458 +/* 1014 */ MCD_OPC_Decode, 196, 16, 229, 2, // Opcode: MADDF_D +/* 1019 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 1034 +/* 1024 */ MCD_OPC_CheckPredicate, 79, 149, 5, 0, // Skip to: 2458 +/* 1029 */ MCD_OPC_Decode, 132, 18, 229, 2, // Opcode: MSUBF_D +/* 1034 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 1056 +/* 1039 */ MCD_OPC_CheckPredicate, 79, 134, 5, 0, // Skip to: 2458 +/* 1044 */ MCD_OPC_CheckField, 16, 5, 0, 127, 5, 0, // Skip to: 2458 +/* 1051 */ MCD_OPC_Decode, 151, 20, 230, 1, // Opcode: RINT_D +/* 1056 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 1078 +/* 1061 */ MCD_OPC_CheckPredicate, 79, 112, 5, 0, // Skip to: 2458 +/* 1066 */ MCD_OPC_CheckField, 16, 5, 0, 105, 5, 0, // Skip to: 2458 +/* 1073 */ MCD_OPC_Decode, 152, 9, 230, 1, // Opcode: CLASS_D +/* 1078 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 1093 +/* 1083 */ MCD_OPC_CheckPredicate, 79, 90, 5, 0, // Skip to: 2458 +/* 1088 */ MCD_OPC_Decode, 180, 17, 230, 2, // Opcode: MIN_D +/* 1093 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 1108 +/* 1098 */ MCD_OPC_CheckPredicate, 79, 75, 5, 0, // Skip to: 2458 +/* 1103 */ MCD_OPC_Decode, 244, 16, 230, 2, // Opcode: MAX_D +/* 1108 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 1123 +/* 1113 */ MCD_OPC_CheckPredicate, 79, 60, 5, 0, // Skip to: 2458 +/* 1118 */ MCD_OPC_Decode, 164, 17, 230, 2, // Opcode: MINA_D +/* 1123 */ MCD_OPC_FilterValue, 31, 50, 5, 0, // Skip to: 2458 +/* 1128 */ MCD_OPC_CheckPredicate, 79, 45, 5, 0, // Skip to: 2458 +/* 1133 */ MCD_OPC_Decode, 228, 16, 230, 2, // Opcode: MAXA_D +/* 1138 */ MCD_OPC_FilterValue, 20, 243, 0, 0, // Skip to: 1386 +/* 1143 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1146 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1161 +/* 1151 */ MCD_OPC_CheckPredicate, 79, 22, 5, 0, // Skip to: 2458 +/* 1156 */ MCD_OPC_Decode, 225, 9, 231, 2, // Opcode: CMP_F_S +/* 1161 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1176 +/* 1166 */ MCD_OPC_CheckPredicate, 79, 7, 5, 0, // Skip to: 2458 +/* 1171 */ MCD_OPC_Decode, 156, 10, 231, 2, // Opcode: CMP_UN_S +/* 1176 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1191 +/* 1181 */ MCD_OPC_CheckPredicate, 79, 248, 4, 0, // Skip to: 2458 +/* 1186 */ MCD_OPC_Decode, 222, 9, 231, 2, // Opcode: CMP_EQ_S +/* 1191 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1206 +/* 1196 */ MCD_OPC_CheckPredicate, 79, 233, 4, 0, // Skip to: 2458 +/* 1201 */ MCD_OPC_Decode, 144, 10, 231, 2, // Opcode: CMP_UEQ_S +/* 1206 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1221 +/* 1211 */ MCD_OPC_CheckPredicate, 79, 218, 4, 0, // Skip to: 2458 +/* 1216 */ MCD_OPC_Decode, 236, 9, 231, 2, // Opcode: CMP_LT_S +/* 1221 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1236 +/* 1226 */ MCD_OPC_CheckPredicate, 79, 203, 4, 0, // Skip to: 2458 +/* 1231 */ MCD_OPC_Decode, 152, 10, 231, 2, // Opcode: CMP_ULT_S +/* 1236 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1251 +/* 1241 */ MCD_OPC_CheckPredicate, 79, 188, 4, 0, // Skip to: 2458 +/* 1246 */ MCD_OPC_Decode, 230, 9, 231, 2, // Opcode: CMP_LE_S +/* 1251 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1266 +/* 1256 */ MCD_OPC_CheckPredicate, 79, 173, 4, 0, // Skip to: 2458 +/* 1261 */ MCD_OPC_Decode, 148, 10, 231, 2, // Opcode: CMP_ULE_S +/* 1266 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1281 +/* 1271 */ MCD_OPC_CheckPredicate, 79, 158, 4, 0, // Skip to: 2458 +/* 1276 */ MCD_OPC_Decode, 240, 9, 231, 2, // Opcode: CMP_SAF_S +/* 1281 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1296 +/* 1286 */ MCD_OPC_CheckPredicate, 79, 143, 4, 0, // Skip to: 2458 +/* 1291 */ MCD_OPC_Decode, 140, 10, 231, 2, // Opcode: CMP_SUN_S +/* 1296 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1311 +/* 1301 */ MCD_OPC_CheckPredicate, 79, 128, 4, 0, // Skip to: 2458 +/* 1306 */ MCD_OPC_Decode, 244, 9, 231, 2, // Opcode: CMP_SEQ_S +/* 1311 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1326 +/* 1316 */ MCD_OPC_CheckPredicate, 79, 113, 4, 0, // Skip to: 2458 +/* 1321 */ MCD_OPC_Decode, 128, 10, 231, 2, // Opcode: CMP_SUEQ_S +/* 1326 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1341 +/* 1331 */ MCD_OPC_CheckPredicate, 79, 98, 4, 0, // Skip to: 2458 +/* 1336 */ MCD_OPC_Decode, 252, 9, 231, 2, // Opcode: CMP_SLT_S +/* 1341 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1356 +/* 1346 */ MCD_OPC_CheckPredicate, 79, 83, 4, 0, // Skip to: 2458 +/* 1351 */ MCD_OPC_Decode, 136, 10, 231, 2, // Opcode: CMP_SULT_S +/* 1356 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1371 +/* 1361 */ MCD_OPC_CheckPredicate, 79, 68, 4, 0, // Skip to: 2458 +/* 1366 */ MCD_OPC_Decode, 248, 9, 231, 2, // Opcode: CMP_SLE_S +/* 1371 */ MCD_OPC_FilterValue, 15, 58, 4, 0, // Skip to: 2458 +/* 1376 */ MCD_OPC_CheckPredicate, 79, 53, 4, 0, // Skip to: 2458 +/* 1381 */ MCD_OPC_Decode, 132, 10, 231, 2, // Opcode: CMP_SULE_S +/* 1386 */ MCD_OPC_FilterValue, 21, 43, 4, 0, // Skip to: 2458 +/* 1391 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1394 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1409 +/* 1399 */ MCD_OPC_CheckPredicate, 79, 30, 4, 0, // Skip to: 2458 +/* 1404 */ MCD_OPC_Decode, 224, 9, 232, 2, // Opcode: CMP_F_D +/* 1409 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1424 +/* 1414 */ MCD_OPC_CheckPredicate, 79, 15, 4, 0, // Skip to: 2458 +/* 1419 */ MCD_OPC_Decode, 154, 10, 232, 2, // Opcode: CMP_UN_D +/* 1424 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1439 +/* 1429 */ MCD_OPC_CheckPredicate, 79, 0, 4, 0, // Skip to: 2458 +/* 1434 */ MCD_OPC_Decode, 218, 9, 232, 2, // Opcode: CMP_EQ_D +/* 1439 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1454 +/* 1444 */ MCD_OPC_CheckPredicate, 79, 241, 3, 0, // Skip to: 2458 +/* 1449 */ MCD_OPC_Decode, 142, 10, 232, 2, // Opcode: CMP_UEQ_D +/* 1454 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1469 +/* 1459 */ MCD_OPC_CheckPredicate, 79, 226, 3, 0, // Skip to: 2458 +/* 1464 */ MCD_OPC_Decode, 232, 9, 232, 2, // Opcode: CMP_LT_D +/* 1469 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1484 +/* 1474 */ MCD_OPC_CheckPredicate, 79, 211, 3, 0, // Skip to: 2458 +/* 1479 */ MCD_OPC_Decode, 150, 10, 232, 2, // Opcode: CMP_ULT_D +/* 1484 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1499 +/* 1489 */ MCD_OPC_CheckPredicate, 79, 196, 3, 0, // Skip to: 2458 +/* 1494 */ MCD_OPC_Decode, 226, 9, 232, 2, // Opcode: CMP_LE_D +/* 1499 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1514 +/* 1504 */ MCD_OPC_CheckPredicate, 79, 181, 3, 0, // Skip to: 2458 +/* 1509 */ MCD_OPC_Decode, 146, 10, 232, 2, // Opcode: CMP_ULE_D +/* 1514 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1529 +/* 1519 */ MCD_OPC_CheckPredicate, 79, 166, 3, 0, // Skip to: 2458 +/* 1524 */ MCD_OPC_Decode, 238, 9, 232, 2, // Opcode: CMP_SAF_D +/* 1529 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1544 +/* 1534 */ MCD_OPC_CheckPredicate, 79, 151, 3, 0, // Skip to: 2458 +/* 1539 */ MCD_OPC_Decode, 138, 10, 232, 2, // Opcode: CMP_SUN_D +/* 1544 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1559 +/* 1549 */ MCD_OPC_CheckPredicate, 79, 136, 3, 0, // Skip to: 2458 +/* 1554 */ MCD_OPC_Decode, 242, 9, 232, 2, // Opcode: CMP_SEQ_D +/* 1559 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1574 +/* 1564 */ MCD_OPC_CheckPredicate, 79, 121, 3, 0, // Skip to: 2458 +/* 1569 */ MCD_OPC_Decode, 254, 9, 232, 2, // Opcode: CMP_SUEQ_D +/* 1574 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1589 +/* 1579 */ MCD_OPC_CheckPredicate, 79, 106, 3, 0, // Skip to: 2458 +/* 1584 */ MCD_OPC_Decode, 250, 9, 232, 2, // Opcode: CMP_SLT_D +/* 1589 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1604 +/* 1594 */ MCD_OPC_CheckPredicate, 79, 91, 3, 0, // Skip to: 2458 +/* 1599 */ MCD_OPC_Decode, 134, 10, 232, 2, // Opcode: CMP_SULT_D +/* 1604 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1619 +/* 1609 */ MCD_OPC_CheckPredicate, 79, 76, 3, 0, // Skip to: 2458 +/* 1614 */ MCD_OPC_Decode, 246, 9, 232, 2, // Opcode: CMP_SLE_D +/* 1619 */ MCD_OPC_FilterValue, 15, 66, 3, 0, // Skip to: 2458 +/* 1624 */ MCD_OPC_CheckPredicate, 79, 61, 3, 0, // Skip to: 2458 +/* 1629 */ MCD_OPC_Decode, 130, 10, 232, 2, // Opcode: CMP_SULE_D +/* 1634 */ MCD_OPC_FilterValue, 18, 93, 0, 0, // Skip to: 1732 +/* 1639 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 1642 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1657 +/* 1647 */ MCD_OPC_CheckPredicate, 76, 38, 3, 0, // Skip to: 2458 +/* 1652 */ MCD_OPC_Decode, 174, 7, 233, 2, // Opcode: BC2EQZ +/* 1657 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1672 +/* 1662 */ MCD_OPC_CheckPredicate, 76, 23, 3, 0, // Skip to: 2458 +/* 1667 */ MCD_OPC_Decode, 140, 16, 234, 2, // Opcode: LWC2_R6 +/* 1672 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1687 +/* 1677 */ MCD_OPC_CheckPredicate, 76, 8, 3, 0, // Skip to: 2458 +/* 1682 */ MCD_OPC_Decode, 138, 23, 234, 2, // Opcode: SWC2_R6 +/* 1687 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1702 +/* 1692 */ MCD_OPC_CheckPredicate, 76, 249, 2, 0, // Skip to: 2458 +/* 1697 */ MCD_OPC_Decode, 176, 7, 233, 2, // Opcode: BC2NEZ +/* 1702 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1717 +/* 1707 */ MCD_OPC_CheckPredicate, 76, 234, 2, 0, // Skip to: 2458 +/* 1712 */ MCD_OPC_Decode, 187, 15, 234, 2, // Opcode: LDC2_R6 +/* 1717 */ MCD_OPC_FilterValue, 15, 224, 2, 0, // Skip to: 2458 +/* 1722 */ MCD_OPC_CheckPredicate, 76, 219, 2, 0, // Skip to: 2458 +/* 1727 */ MCD_OPC_Decode, 234, 20, 234, 2, // Opcode: SDC2_R6 +/* 1732 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 1747 +/* 1737 */ MCD_OPC_CheckPredicate, 76, 204, 2, 0, // Skip to: 2458 +/* 1742 */ MCD_OPC_Decode, 227, 7, 235, 2, // Opcode: BGEZC +/* 1747 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 1762 +/* 1752 */ MCD_OPC_CheckPredicate, 76, 189, 2, 0, // Skip to: 2458 +/* 1757 */ MCD_OPC_Decode, 161, 8, 236, 2, // Opcode: BLTZC +/* 1762 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 1777 +/* 1767 */ MCD_OPC_CheckPredicate, 76, 174, 2, 0, // Skip to: 2458 +/* 1772 */ MCD_OPC_Decode, 172, 8, 237, 2, // Opcode: BNEC +/* 1777 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 1792 +/* 1782 */ MCD_OPC_CheckPredicate, 77, 159, 2, 0, // Skip to: 2458 +/* 1787 */ MCD_OPC_Decode, 198, 11, 238, 2, // Opcode: DAUI +/* 1792 */ MCD_OPC_FilterValue, 31, 135, 1, 0, // Skip to: 2188 +/* 1797 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1800 */ MCD_OPC_FilterValue, 15, 123, 0, 0, // Skip to: 1928 +/* 1805 */ MCD_OPC_ExtractField, 6, 10, // Inst{15-6} ... +/* 1808 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1823 +/* 1813 */ MCD_OPC_CheckPredicate, 80, 128, 2, 0, // Skip to: 2458 +/* 1818 */ MCD_OPC_Decode, 165, 10, 239, 2, // Opcode: CRC32B +/* 1823 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1838 +/* 1828 */ MCD_OPC_CheckPredicate, 80, 113, 2, 0, // Skip to: 2458 +/* 1833 */ MCD_OPC_Decode, 175, 10, 239, 2, // Opcode: CRC32H +/* 1838 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1853 +/* 1843 */ MCD_OPC_CheckPredicate, 80, 98, 2, 0, // Skip to: 2458 +/* 1848 */ MCD_OPC_Decode, 177, 10, 239, 2, // Opcode: CRC32W +/* 1853 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1868 +/* 1858 */ MCD_OPC_CheckPredicate, 81, 83, 2, 0, // Skip to: 2458 +/* 1863 */ MCD_OPC_Decode, 174, 10, 239, 2, // Opcode: CRC32D +/* 1868 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1883 +/* 1873 */ MCD_OPC_CheckPredicate, 80, 68, 2, 0, // Skip to: 2458 +/* 1878 */ MCD_OPC_Decode, 167, 10, 239, 2, // Opcode: CRC32CB +/* 1883 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1898 +/* 1888 */ MCD_OPC_CheckPredicate, 80, 53, 2, 0, // Skip to: 2458 +/* 1893 */ MCD_OPC_Decode, 170, 10, 239, 2, // Opcode: CRC32CH +/* 1898 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1913 +/* 1903 */ MCD_OPC_CheckPredicate, 80, 38, 2, 0, // Skip to: 2458 +/* 1908 */ MCD_OPC_Decode, 172, 10, 239, 2, // Opcode: CRC32CW +/* 1913 */ MCD_OPC_FilterValue, 7, 28, 2, 0, // Skip to: 2458 +/* 1918 */ MCD_OPC_CheckPredicate, 81, 23, 2, 0, // Skip to: 2458 +/* 1923 */ MCD_OPC_Decode, 169, 10, 239, 2, // Opcode: CRC32CD +/* 1928 */ MCD_OPC_FilterValue, 32, 47, 0, 0, // Skip to: 1980 +/* 1933 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 1936 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1965 +/* 1941 */ MCD_OPC_CheckPredicate, 75, 0, 2, 0, // Skip to: 2458 +/* 1946 */ MCD_OPC_CheckField, 21, 5, 0, 249, 1, 0, // Skip to: 2458 +/* 1953 */ MCD_OPC_CheckField, 6, 2, 0, 242, 1, 0, // Skip to: 2458 +/* 1960 */ MCD_OPC_Decode, 132, 8, 204, 2, // Opcode: BITSWAP +/* 1965 */ MCD_OPC_FilterValue, 2, 232, 1, 0, // Skip to: 2458 +/* 1970 */ MCD_OPC_CheckPredicate, 75, 227, 1, 0, // Skip to: 2458 +/* 1975 */ MCD_OPC_Decode, 211, 6, 240, 2, // Opcode: ALIGN +/* 1980 */ MCD_OPC_FilterValue, 36, 47, 0, 0, // Skip to: 2032 +/* 1985 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 1988 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2017 +/* 1993 */ MCD_OPC_CheckPredicate, 77, 204, 1, 0, // Skip to: 2458 +/* 1998 */ MCD_OPC_CheckField, 21, 5, 0, 197, 1, 0, // Skip to: 2458 +/* 2005 */ MCD_OPC_CheckField, 6, 3, 0, 190, 1, 0, // Skip to: 2458 +/* 2012 */ MCD_OPC_Decode, 199, 11, 241, 2, // Opcode: DBITSWAP +/* 2017 */ MCD_OPC_FilterValue, 1, 180, 1, 0, // Skip to: 2458 +/* 2022 */ MCD_OPC_CheckPredicate, 77, 175, 1, 0, // Skip to: 2458 +/* 2027 */ MCD_OPC_Decode, 196, 11, 242, 2, // Opcode: DALIGN +/* 2032 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 2054 +/* 2037 */ MCD_OPC_CheckPredicate, 76, 160, 1, 0, // Skip to: 2458 +/* 2042 */ MCD_OPC_CheckField, 6, 1, 0, 153, 1, 0, // Skip to: 2458 +/* 2049 */ MCD_OPC_Decode, 252, 8, 209, 2, // Opcode: CACHE_R6 +/* 2054 */ MCD_OPC_FilterValue, 38, 10, 0, 0, // Skip to: 2069 +/* 2059 */ MCD_OPC_CheckPredicate, 82, 138, 1, 0, // Skip to: 2458 +/* 2064 */ MCD_OPC_Decode, 217, 20, 243, 2, // Opcode: SC_R6 +/* 2069 */ MCD_OPC_FilterValue, 39, 10, 0, 0, // Skip to: 2084 +/* 2074 */ MCD_OPC_CheckPredicate, 75, 123, 1, 0, // Skip to: 2458 +/* 2079 */ MCD_OPC_Decode, 210, 20, 243, 2, // Opcode: SCD_R6 +/* 2084 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 2106 +/* 2089 */ MCD_OPC_CheckPredicate, 76, 108, 1, 0, // Skip to: 2458 +/* 2094 */ MCD_OPC_CheckField, 6, 1, 0, 101, 1, 0, // Skip to: 2458 +/* 2101 */ MCD_OPC_Decode, 245, 19, 209, 2, // Opcode: PREF_R6 +/* 2106 */ MCD_OPC_FilterValue, 54, 10, 0, 0, // Skip to: 2121 +/* 2111 */ MCD_OPC_CheckPredicate, 82, 86, 1, 0, // Skip to: 2458 +/* 2116 */ MCD_OPC_Decode, 246, 15, 243, 2, // Opcode: LL_R6 +/* 2121 */ MCD_OPC_FilterValue, 55, 10, 0, 0, // Skip to: 2136 +/* 2126 */ MCD_OPC_CheckPredicate, 77, 71, 1, 0, // Skip to: 2458 +/* 2131 */ MCD_OPC_Decode, 239, 15, 243, 2, // Opcode: LLD_R6 +/* 2136 */ MCD_OPC_FilterValue, 61, 61, 1, 0, // Skip to: 2458 +/* 2141 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 2144 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2166 +/* 2149 */ MCD_OPC_CheckPredicate, 83, 48, 1, 0, // Skip to: 2458 +/* 2154 */ MCD_OPC_CheckField, 8, 13, 0, 41, 1, 0, // Skip to: 2458 +/* 2161 */ MCD_OPC_Decode, 184, 14, 186, 1, // Opcode: GINVI +/* 2166 */ MCD_OPC_FilterValue, 2, 31, 1, 0, // Skip to: 2458 +/* 2171 */ MCD_OPC_CheckPredicate, 83, 26, 1, 0, // Skip to: 2458 +/* 2176 */ MCD_OPC_CheckField, 10, 11, 0, 19, 1, 0, // Skip to: 2458 +/* 2183 */ MCD_OPC_Decode, 187, 14, 244, 2, // Opcode: GINVT +/* 2188 */ MCD_OPC_FilterValue, 50, 10, 0, 0, // Skip to: 2203 +/* 2193 */ MCD_OPC_CheckPredicate, 76, 4, 1, 0, // Skip to: 2458 +/* 2198 */ MCD_OPC_Decode, 161, 7, 245, 2, // Opcode: BC +/* 2203 */ MCD_OPC_FilterValue, 53, 27, 0, 0, // Skip to: 2235 +/* 2208 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 2225 +/* 2213 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 2225 +/* 2220 */ MCD_OPC_Decode, 238, 7, 180, 1, // Opcode: BGTZC_MMR6 +/* 2225 */ MCD_OPC_CheckPredicate, 24, 228, 0, 0, // Skip to: 2458 +/* 2230 */ MCD_OPC_Decode, 163, 8, 180, 1, // Opcode: BLTZC_MMR6 +/* 2235 */ MCD_OPC_FilterValue, 54, 26, 0, 0, // Skip to: 2266 +/* 2240 */ MCD_OPC_CheckPredicate, 75, 11, 0, 0, // Skip to: 2256 +/* 2245 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 2256 +/* 2252 */ MCD_OPC_Decode, 129, 15, 103, // Opcode: JIC +/* 2256 */ MCD_OPC_CheckPredicate, 76, 197, 0, 0, // Skip to: 2458 +/* 2261 */ MCD_OPC_Decode, 201, 7, 246, 2, // Opcode: BEQZC +/* 2266 */ MCD_OPC_FilterValue, 58, 10, 0, 0, // Skip to: 2281 +/* 2271 */ MCD_OPC_CheckPredicate, 75, 182, 0, 0, // Skip to: 2458 +/* 2276 */ MCD_OPC_Decode, 148, 7, 245, 2, // Opcode: BALC +/* 2281 */ MCD_OPC_FilterValue, 59, 109, 0, 0, // Skip to: 2395 +/* 2286 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... +/* 2289 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2304 +/* 2294 */ MCD_OPC_CheckPredicate, 75, 159, 0, 0, // Skip to: 2458 +/* 2299 */ MCD_OPC_Decode, 129, 6, 174, 1, // Opcode: ADDIUPC +/* 2304 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2319 +/* 2309 */ MCD_OPC_CheckPredicate, 75, 144, 0, 0, // Skip to: 2458 +/* 2314 */ MCD_OPC_Decode, 158, 16, 174, 1, // Opcode: LWPC +/* 2319 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2334 +/* 2324 */ MCD_OPC_CheckPredicate, 84, 129, 0, 0, // Skip to: 2458 +/* 2329 */ MCD_OPC_Decode, 169, 16, 174, 1, // Opcode: LWUPC +/* 2334 */ MCD_OPC_FilterValue, 3, 119, 0, 0, // Skip to: 2458 +/* 2339 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 2342 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2357 +/* 2347 */ MCD_OPC_CheckPredicate, 84, 106, 0, 0, // Skip to: 2458 +/* 2352 */ MCD_OPC_Decode, 194, 15, 247, 2, // Opcode: LDPC +/* 2357 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 2458 +/* 2362 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 2365 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2380 +/* 2370 */ MCD_OPC_CheckPredicate, 75, 83, 0, 0, // Skip to: 2458 +/* 2375 */ MCD_OPC_Decode, 245, 6, 175, 1, // Opcode: AUIPC +/* 2380 */ MCD_OPC_FilterValue, 3, 73, 0, 0, // Skip to: 2458 +/* 2385 */ MCD_OPC_CheckPredicate, 75, 68, 0, 0, // Skip to: 2458 +/* 2390 */ MCD_OPC_Decode, 213, 6, 175, 1, // Opcode: ALUIPC +/* 2395 */ MCD_OPC_FilterValue, 61, 27, 0, 0, // Skip to: 2427 +/* 2400 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 2417 +/* 2405 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 2417 +/* 2412 */ MCD_OPC_Decode, 140, 8, 182, 1, // Opcode: BLEZC_MMR6 +/* 2417 */ MCD_OPC_CheckPredicate, 24, 36, 0, 0, // Skip to: 2458 +/* 2422 */ MCD_OPC_Decode, 229, 7, 182, 1, // Opcode: BGEZC_MMR6 +/* 2427 */ MCD_OPC_FilterValue, 62, 26, 0, 0, // Skip to: 2458 +/* 2432 */ MCD_OPC_CheckPredicate, 75, 11, 0, 0, // Skip to: 2448 +/* 2437 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 2448 +/* 2444 */ MCD_OPC_Decode, 254, 14, 103, // Opcode: JIALC +/* 2448 */ MCD_OPC_CheckPredicate, 76, 5, 0, 0, // Skip to: 2458 +/* 2453 */ MCD_OPC_Decode, 191, 8, 246, 2, // Opcode: BNEZC +/* 2458 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMips32r6_64r6_Ambiguous32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 6, 27, 0, 0, // Skip to: 35 +/* 8 */ MCD_OPC_CheckPredicate, 76, 12, 0, 0, // Skip to: 25 +/* 13 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 25 +/* 20 */ MCD_OPC_Decode, 136, 8, 223, 2, // Opcode: BLEZALC +/* 25 */ MCD_OPC_CheckPredicate, 76, 165, 0, 0, // Skip to: 195 +/* 30 */ MCD_OPC_Decode, 215, 7, 223, 2, // Opcode: BGEUC +/* 35 */ MCD_OPC_FilterValue, 7, 27, 0, 0, // Skip to: 67 +/* 40 */ MCD_OPC_CheckPredicate, 76, 12, 0, 0, // Skip to: 57 +/* 45 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 57 +/* 52 */ MCD_OPC_Decode, 234, 7, 224, 2, // Opcode: BGTZALC +/* 57 */ MCD_OPC_CheckPredicate, 76, 133, 0, 0, // Skip to: 195 +/* 62 */ MCD_OPC_Decode, 149, 8, 224, 2, // Opcode: BLTUC +/* 67 */ MCD_OPC_FilterValue, 8, 27, 0, 0, // Skip to: 99 +/* 72 */ MCD_OPC_CheckPredicate, 76, 12, 0, 0, // Skip to: 89 +/* 77 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 89 +/* 84 */ MCD_OPC_Decode, 199, 7, 237, 2, // Opcode: BEQZALC +/* 89 */ MCD_OPC_CheckPredicate, 76, 101, 0, 0, // Skip to: 195 +/* 94 */ MCD_OPC_Decode, 206, 8, 225, 2, // Opcode: BOVC +/* 99 */ MCD_OPC_FilterValue, 22, 27, 0, 0, // Skip to: 131 +/* 104 */ MCD_OPC_CheckPredicate, 76, 12, 0, 0, // Skip to: 121 +/* 109 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 121 +/* 116 */ MCD_OPC_Decode, 138, 8, 235, 2, // Opcode: BLEZC +/* 121 */ MCD_OPC_CheckPredicate, 76, 69, 0, 0, // Skip to: 195 +/* 126 */ MCD_OPC_Decode, 209, 7, 235, 2, // Opcode: BGEC +/* 131 */ MCD_OPC_FilterValue, 23, 27, 0, 0, // Skip to: 163 +/* 136 */ MCD_OPC_CheckPredicate, 76, 12, 0, 0, // Skip to: 153 +/* 141 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 153 +/* 148 */ MCD_OPC_Decode, 236, 7, 236, 2, // Opcode: BGTZC +/* 153 */ MCD_OPC_CheckPredicate, 76, 37, 0, 0, // Skip to: 195 +/* 158 */ MCD_OPC_Decode, 143, 8, 236, 2, // Opcode: BLTC +/* 163 */ MCD_OPC_FilterValue, 24, 27, 0, 0, // Skip to: 195 +/* 168 */ MCD_OPC_CheckPredicate, 76, 12, 0, 0, // Skip to: 185 +/* 173 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 185 +/* 180 */ MCD_OPC_Decode, 189, 8, 237, 2, // Opcode: BNEZALC +/* 185 */ MCD_OPC_CheckPredicate, 76, 5, 0, 0, // Skip to: 195 +/* 190 */ MCD_OPC_Decode, 199, 8, 237, 2, // Opcode: BNVC +/* 195 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMips32r6_64r6_BranchZero32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 18 +/* 8 */ MCD_OPC_CheckPredicate, 85, 20, 0, 0, // Skip to: 33 +/* 13 */ MCD_OPC_Decode, 228, 7, 235, 2, // Opcode: BGEZC64 +/* 18 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 33 +/* 23 */ MCD_OPC_CheckPredicate, 85, 5, 0, 0, // Skip to: 33 +/* 28 */ MCD_OPC_Decode, 162, 8, 236, 2, // Opcode: BLTZC64 +/* 33 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMips32r6_64r6_GP6432[] = { -/* 0 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... -/* 3 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 22 -/* 7 */ MCD_OPC_CheckPredicate, 39, 30, 0, // Skip to: 41 -/* 11 */ MCD_OPC_CheckField, 26, 6, 0, 24, 0, // Skip to: 41 -/* 17 */ MCD_OPC_Decode, 175, 11, 224, 1, // Opcode: SELEQZ64 -/* 22 */ MCD_OPC_FilterValue, 55, 15, 0, // Skip to: 41 -/* 26 */ MCD_OPC_CheckPredicate, 39, 11, 0, // Skip to: 41 -/* 30 */ MCD_OPC_CheckField, 26, 6, 0, 5, 0, // Skip to: 41 -/* 36 */ MCD_OPC_Decode, 179, 11, 224, 1, // Opcode: SELNEZ64 -/* 41 */ MCD_OPC_Fail, +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 61 +/* 8 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 11 */ MCD_OPC_FilterValue, 53, 9, 0, 0, // Skip to: 25 +/* 16 */ MCD_OPC_CheckPredicate, 86, 226, 0, 0, // Skip to: 247 +/* 21 */ MCD_OPC_Decode, 251, 20, 23, // Opcode: SELEQZ64 +/* 25 */ MCD_OPC_FilterValue, 55, 9, 0, 0, // Skip to: 39 +/* 30 */ MCD_OPC_CheckPredicate, 86, 212, 0, 0, // Skip to: 247 +/* 35 */ MCD_OPC_Decode, 130, 21, 23, // Opcode: SELNEZ64 +/* 39 */ MCD_OPC_FilterValue, 137, 8, 202, 0, 0, // Skip to: 247 +/* 45 */ MCD_OPC_CheckPredicate, 75, 197, 0, 0, // Skip to: 247 +/* 50 */ MCD_OPC_CheckField, 11, 10, 0, 190, 0, 0, // Skip to: 247 +/* 57 */ MCD_OPC_Decode, 142, 15, 24, // Opcode: JR_HB64_R6 +/* 61 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 76 +/* 66 */ MCD_OPC_CheckPredicate, 85, 176, 0, 0, // Skip to: 247 +/* 71 */ MCD_OPC_Decode, 216, 7, 223, 2, // Opcode: BGEUC64 +/* 76 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 91 +/* 81 */ MCD_OPC_CheckPredicate, 85, 161, 0, 0, // Skip to: 247 +/* 86 */ MCD_OPC_Decode, 150, 8, 224, 2, // Opcode: BLTUC64 +/* 91 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 106 +/* 96 */ MCD_OPC_CheckPredicate, 85, 146, 0, 0, // Skip to: 247 +/* 101 */ MCD_OPC_Decode, 192, 7, 225, 2, // Opcode: BEQC64 +/* 106 */ MCD_OPC_FilterValue, 22, 27, 0, 0, // Skip to: 138 +/* 111 */ MCD_OPC_CheckPredicate, 85, 12, 0, 0, // Skip to: 128 +/* 116 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 128 +/* 123 */ MCD_OPC_Decode, 139, 8, 235, 2, // Opcode: BLEZC64 +/* 128 */ MCD_OPC_CheckPredicate, 85, 114, 0, 0, // Skip to: 247 +/* 133 */ MCD_OPC_Decode, 210, 7, 235, 2, // Opcode: BGEC64 +/* 138 */ MCD_OPC_FilterValue, 23, 27, 0, 0, // Skip to: 170 +/* 143 */ MCD_OPC_CheckPredicate, 85, 12, 0, 0, // Skip to: 160 +/* 148 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 160 +/* 155 */ MCD_OPC_Decode, 237, 7, 236, 2, // Opcode: BGTZC64 +/* 160 */ MCD_OPC_CheckPredicate, 85, 82, 0, 0, // Skip to: 247 +/* 165 */ MCD_OPC_Decode, 144, 8, 236, 2, // Opcode: BLTC64 +/* 170 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 185 +/* 175 */ MCD_OPC_CheckPredicate, 85, 67, 0, 0, // Skip to: 247 +/* 180 */ MCD_OPC_Decode, 174, 8, 237, 2, // Opcode: BNEC64 +/* 185 */ MCD_OPC_FilterValue, 54, 26, 0, 0, // Skip to: 216 +/* 190 */ MCD_OPC_CheckPredicate, 85, 11, 0, 0, // Skip to: 206 +/* 195 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 206 +/* 202 */ MCD_OPC_Decode, 130, 15, 22, // Opcode: JIC64 +/* 206 */ MCD_OPC_CheckPredicate, 85, 36, 0, 0, // Skip to: 247 +/* 211 */ MCD_OPC_Decode, 204, 7, 248, 2, // Opcode: BEQZC64 +/* 216 */ MCD_OPC_FilterValue, 62, 26, 0, 0, // Skip to: 247 +/* 221 */ MCD_OPC_CheckPredicate, 85, 11, 0, 0, // Skip to: 237 +/* 226 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 237 +/* 233 */ MCD_OPC_Decode, 255, 14, 22, // Opcode: JIALC64 +/* 237 */ MCD_OPC_CheckPredicate, 85, 5, 0, 0, // Skip to: 247 +/* 242 */ MCD_OPC_Decode, 194, 8, 248, 2, // Opcode: BNEZC64 +/* 247 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMips32r6_64r6_PTR6432[] = { +/* 0 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 3 */ MCD_OPC_FilterValue, 38, 17, 0, 0, // Skip to: 25 +/* 8 */ MCD_OPC_CheckPredicate, 87, 34, 0, 0, // Skip to: 47 +/* 13 */ MCD_OPC_CheckField, 26, 6, 31, 27, 0, 0, // Skip to: 47 +/* 20 */ MCD_OPC_Decode, 208, 20, 243, 2, // Opcode: SC64_R6 +/* 25 */ MCD_OPC_FilterValue, 54, 17, 0, 0, // Skip to: 47 +/* 30 */ MCD_OPC_CheckPredicate, 87, 12, 0, 0, // Skip to: 47 +/* 35 */ MCD_OPC_CheckField, 26, 6, 31, 5, 0, 0, // Skip to: 47 +/* 42 */ MCD_OPC_Decode, 237, 15, 243, 2, // Opcode: LL64_R6 +/* 47 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMips6432[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 112, 1, // Skip to: 375 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 29 -/* 14 */ MCD_OPC_CheckPredicate, 19, 42, 9, // Skip to: 2364 -/* 18 */ MCD_OPC_CheckField, 6, 5, 0, 36, 9, // Skip to: 2364 -/* 24 */ MCD_OPC_Decode, 255, 4, 252, 1, // Opcode: DSLLV -/* 29 */ MCD_OPC_FilterValue, 22, 29, 0, // Skip to: 62 -/* 33 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 36 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 49 -/* 40 */ MCD_OPC_CheckPredicate, 19, 16, 9, // Skip to: 2364 -/* 44 */ MCD_OPC_Decode, 133, 5, 252, 1, // Opcode: DSRLV -/* 49 */ MCD_OPC_FilterValue, 1, 7, 9, // Skip to: 2364 -/* 53 */ MCD_OPC_CheckPredicate, 40, 3, 9, // Skip to: 2364 -/* 57 */ MCD_OPC_Decode, 248, 4, 252, 1, // Opcode: DROTRV -/* 62 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 81 -/* 66 */ MCD_OPC_CheckPredicate, 19, 246, 8, // Skip to: 2364 -/* 70 */ MCD_OPC_CheckField, 6, 5, 0, 240, 8, // Skip to: 2364 -/* 76 */ MCD_OPC_Decode, 130, 5, 252, 1, // Opcode: DSRAV -/* 81 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 100 -/* 85 */ MCD_OPC_CheckPredicate, 41, 227, 8, // Skip to: 2364 -/* 89 */ MCD_OPC_CheckField, 6, 10, 0, 221, 8, // Skip to: 2364 -/* 95 */ MCD_OPC_Decode, 207, 4, 253, 1, // Opcode: DMULT -/* 100 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 119 -/* 104 */ MCD_OPC_CheckPredicate, 41, 208, 8, // Skip to: 2364 -/* 108 */ MCD_OPC_CheckField, 6, 10, 0, 202, 8, // Skip to: 2364 -/* 114 */ MCD_OPC_Decode, 208, 4, 253, 1, // Opcode: DMULTu -/* 119 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 138 -/* 123 */ MCD_OPC_CheckPredicate, 41, 189, 8, // Skip to: 2364 -/* 127 */ MCD_OPC_CheckField, 6, 10, 0, 183, 8, // Skip to: 2364 -/* 133 */ MCD_OPC_Decode, 250, 4, 253, 1, // Opcode: DSDIV -/* 138 */ MCD_OPC_FilterValue, 31, 15, 0, // Skip to: 157 -/* 142 */ MCD_OPC_CheckPredicate, 41, 170, 8, // Skip to: 2364 -/* 146 */ MCD_OPC_CheckField, 6, 10, 0, 164, 8, // Skip to: 2364 -/* 152 */ MCD_OPC_Decode, 136, 5, 253, 1, // Opcode: DUDIV -/* 157 */ MCD_OPC_FilterValue, 44, 15, 0, // Skip to: 176 -/* 161 */ MCD_OPC_CheckPredicate, 19, 151, 8, // Skip to: 2364 -/* 165 */ MCD_OPC_CheckField, 6, 5, 0, 145, 8, // Skip to: 2364 -/* 171 */ MCD_OPC_Decode, 159, 4, 224, 1, // Opcode: DADD -/* 176 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 195 -/* 180 */ MCD_OPC_CheckPredicate, 19, 132, 8, // Skip to: 2364 -/* 184 */ MCD_OPC_CheckField, 6, 5, 0, 126, 8, // Skip to: 2364 -/* 190 */ MCD_OPC_Decode, 162, 4, 224, 1, // Opcode: DADDu -/* 195 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 214 -/* 199 */ MCD_OPC_CheckPredicate, 19, 113, 8, // Skip to: 2364 -/* 203 */ MCD_OPC_CheckField, 6, 5, 0, 107, 8, // Skip to: 2364 -/* 209 */ MCD_OPC_Decode, 134, 5, 224, 1, // Opcode: DSUB -/* 214 */ MCD_OPC_FilterValue, 47, 15, 0, // Skip to: 233 -/* 218 */ MCD_OPC_CheckPredicate, 19, 94, 8, // Skip to: 2364 -/* 222 */ MCD_OPC_CheckField, 6, 5, 0, 88, 8, // Skip to: 2364 -/* 228 */ MCD_OPC_Decode, 135, 5, 224, 1, // Opcode: DSUBu -/* 233 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 252 -/* 237 */ MCD_OPC_CheckPredicate, 19, 75, 8, // Skip to: 2364 -/* 241 */ MCD_OPC_CheckField, 21, 5, 0, 69, 8, // Skip to: 2364 -/* 247 */ MCD_OPC_Decode, 252, 4, 254, 1, // Opcode: DSLL -/* 252 */ MCD_OPC_FilterValue, 58, 29, 0, // Skip to: 285 -/* 256 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 259 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 272 -/* 263 */ MCD_OPC_CheckPredicate, 19, 49, 8, // Skip to: 2364 -/* 267 */ MCD_OPC_Decode, 131, 5, 254, 1, // Opcode: DSRL -/* 272 */ MCD_OPC_FilterValue, 1, 40, 8, // Skip to: 2364 -/* 276 */ MCD_OPC_CheckPredicate, 40, 36, 8, // Skip to: 2364 -/* 280 */ MCD_OPC_Decode, 246, 4, 254, 1, // Opcode: DROTR -/* 285 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 304 -/* 289 */ MCD_OPC_CheckPredicate, 19, 23, 8, // Skip to: 2364 -/* 293 */ MCD_OPC_CheckField, 21, 5, 0, 17, 8, // Skip to: 2364 -/* 299 */ MCD_OPC_Decode, 128, 5, 254, 1, // Opcode: DSRA -/* 304 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 323 -/* 308 */ MCD_OPC_CheckPredicate, 19, 4, 8, // Skip to: 2364 -/* 312 */ MCD_OPC_CheckField, 21, 5, 0, 254, 7, // Skip to: 2364 -/* 318 */ MCD_OPC_Decode, 253, 4, 254, 1, // Opcode: DSLL32 -/* 323 */ MCD_OPC_FilterValue, 62, 29, 0, // Skip to: 356 -/* 327 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 330 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 343 -/* 334 */ MCD_OPC_CheckPredicate, 19, 234, 7, // Skip to: 2364 -/* 338 */ MCD_OPC_Decode, 132, 5, 254, 1, // Opcode: DSRL32 -/* 343 */ MCD_OPC_FilterValue, 1, 225, 7, // Skip to: 2364 -/* 347 */ MCD_OPC_CheckPredicate, 40, 221, 7, // Skip to: 2364 -/* 351 */ MCD_OPC_Decode, 247, 4, 254, 1, // Opcode: DROTR32 -/* 356 */ MCD_OPC_FilterValue, 63, 212, 7, // Skip to: 2364 -/* 360 */ MCD_OPC_CheckPredicate, 19, 208, 7, // Skip to: 2364 -/* 364 */ MCD_OPC_CheckField, 21, 5, 0, 202, 7, // Skip to: 2364 -/* 370 */ MCD_OPC_Decode, 129, 5, 254, 1, // Opcode: DSRA32 -/* 375 */ MCD_OPC_FilterValue, 16, 41, 0, // Skip to: 420 -/* 379 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 382 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 401 -/* 386 */ MCD_OPC_CheckPredicate, 42, 182, 7, // Skip to: 2364 -/* 390 */ MCD_OPC_CheckField, 3, 8, 0, 176, 7, // Skip to: 2364 -/* 396 */ MCD_OPC_Decode, 196, 4, 255, 1, // Opcode: DMFC0 -/* 401 */ MCD_OPC_FilterValue, 5, 167, 7, // Skip to: 2364 -/* 405 */ MCD_OPC_CheckPredicate, 42, 163, 7, // Skip to: 2364 -/* 409 */ MCD_OPC_CheckField, 3, 8, 0, 157, 7, // Skip to: 2364 -/* 415 */ MCD_OPC_Decode, 201, 4, 255, 1, // Opcode: DMTC0 -/* 420 */ MCD_OPC_FilterValue, 17, 222, 3, // Skip to: 1414 -/* 424 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 427 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 485 -/* 431 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 434 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 453 -/* 438 */ MCD_OPC_CheckPredicate, 43, 130, 7, // Skip to: 2364 -/* 442 */ MCD_OPC_CheckField, 6, 5, 0, 124, 7, // Skip to: 2364 -/* 448 */ MCD_OPC_Decode, 184, 8, 128, 2, // Opcode: MFHC1_D64 -/* 453 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 472 -/* 457 */ MCD_OPC_CheckPredicate, 43, 111, 7, // Skip to: 2364 -/* 461 */ MCD_OPC_CheckField, 6, 5, 0, 105, 7, // Skip to: 2364 -/* 467 */ MCD_OPC_Decode, 174, 9, 129, 2, // Opcode: MTHC1_D64 -/* 472 */ MCD_OPC_FilterValue, 17, 96, 7, // Skip to: 2364 -/* 476 */ MCD_OPC_CheckPredicate, 44, 92, 7, // Skip to: 2364 -/* 480 */ MCD_OPC_Decode, 172, 5, 233, 1, // Opcode: FADD_D64 -/* 485 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 504 -/* 489 */ MCD_OPC_CheckPredicate, 44, 79, 7, // Skip to: 2364 -/* 493 */ MCD_OPC_CheckField, 21, 5, 17, 73, 7, // Skip to: 2364 -/* 499 */ MCD_OPC_Decode, 174, 6, 233, 1, // Opcode: FSUB_D64 -/* 504 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 523 -/* 508 */ MCD_OPC_CheckPredicate, 44, 60, 7, // Skip to: 2364 -/* 512 */ MCD_OPC_CheckField, 21, 5, 17, 54, 7, // Skip to: 2364 -/* 518 */ MCD_OPC_Decode, 137, 6, 233, 1, // Opcode: FMUL_D64 -/* 523 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 542 -/* 527 */ MCD_OPC_CheckPredicate, 44, 41, 7, // Skip to: 2364 -/* 531 */ MCD_OPC_CheckField, 21, 5, 17, 35, 7, // Skip to: 2364 -/* 537 */ MCD_OPC_Decode, 208, 5, 233, 1, // Opcode: FDIV_D64 -/* 542 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 561 -/* 546 */ MCD_OPC_CheckPredicate, 45, 22, 7, // Skip to: 2364 -/* 550 */ MCD_OPC_CheckField, 16, 10, 160, 4, 15, 7, // Skip to: 2364 -/* 557 */ MCD_OPC_Decode, 167, 6, 105, // Opcode: FSQRT_D64 -/* 561 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 580 -/* 565 */ MCD_OPC_CheckPredicate, 44, 3, 7, // Skip to: 2364 -/* 569 */ MCD_OPC_CheckField, 16, 10, 160, 4, 252, 6, // Skip to: 2364 -/* 576 */ MCD_OPC_Decode, 165, 5, 105, // Opcode: FABS_D64 -/* 580 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 599 -/* 584 */ MCD_OPC_CheckPredicate, 44, 240, 6, // Skip to: 2364 -/* 588 */ MCD_OPC_CheckField, 16, 10, 160, 4, 233, 6, // Skip to: 2364 -/* 595 */ MCD_OPC_Decode, 130, 6, 105, // Opcode: FMOV_D64 -/* 599 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 618 -/* 603 */ MCD_OPC_CheckPredicate, 44, 221, 6, // Skip to: 2364 -/* 607 */ MCD_OPC_CheckField, 16, 10, 160, 4, 214, 6, // Skip to: 2364 -/* 614 */ MCD_OPC_Decode, 143, 6, 105, // Opcode: FNEG_D64 -/* 618 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 651 -/* 622 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 625 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 638 -/* 630 */ MCD_OPC_CheckPredicate, 44, 194, 6, // Skip to: 2364 -/* 634 */ MCD_OPC_Decode, 252, 10, 98, // Opcode: ROUND_L_S -/* 638 */ MCD_OPC_FilterValue, 160, 4, 185, 6, // Skip to: 2364 -/* 643 */ MCD_OPC_CheckPredicate, 44, 181, 6, // Skip to: 2364 -/* 647 */ MCD_OPC_Decode, 251, 10, 105, // Opcode: ROUND_L_D64 -/* 651 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 684 -/* 655 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 658 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 671 -/* 663 */ MCD_OPC_CheckPredicate, 44, 161, 6, // Skip to: 2364 -/* 667 */ MCD_OPC_Decode, 215, 13, 98, // Opcode: TRUNC_L_S -/* 671 */ MCD_OPC_FilterValue, 160, 4, 152, 6, // Skip to: 2364 -/* 676 */ MCD_OPC_CheckPredicate, 44, 148, 6, // Skip to: 2364 -/* 680 */ MCD_OPC_Decode, 214, 13, 105, // Opcode: TRUNC_L_D64 -/* 684 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 717 -/* 688 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 691 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 704 -/* 696 */ MCD_OPC_CheckPredicate, 44, 128, 6, // Skip to: 2364 -/* 700 */ MCD_OPC_Decode, 224, 2, 98, // Opcode: CEIL_L_S -/* 704 */ MCD_OPC_FilterValue, 160, 4, 119, 6, // Skip to: 2364 -/* 709 */ MCD_OPC_CheckPredicate, 44, 115, 6, // Skip to: 2364 -/* 713 */ MCD_OPC_Decode, 223, 2, 105, // Opcode: CEIL_L_D64 -/* 717 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 750 -/* 721 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 724 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 737 -/* 729 */ MCD_OPC_CheckPredicate, 44, 95, 6, // Skip to: 2364 -/* 733 */ MCD_OPC_Decode, 240, 5, 98, // Opcode: FLOOR_L_S -/* 737 */ MCD_OPC_FilterValue, 160, 4, 86, 6, // Skip to: 2364 -/* 742 */ MCD_OPC_CheckPredicate, 44, 82, 6, // Skip to: 2364 -/* 746 */ MCD_OPC_Decode, 239, 5, 105, // Opcode: FLOOR_L_D64 -/* 750 */ MCD_OPC_FilterValue, 12, 16, 0, // Skip to: 770 -/* 754 */ MCD_OPC_CheckPredicate, 45, 70, 6, // Skip to: 2364 -/* 758 */ MCD_OPC_CheckField, 16, 10, 160, 4, 63, 6, // Skip to: 2364 -/* 765 */ MCD_OPC_Decode, 254, 10, 130, 2, // Opcode: ROUND_W_D64 -/* 770 */ MCD_OPC_FilterValue, 13, 16, 0, // Skip to: 790 -/* 774 */ MCD_OPC_CheckPredicate, 45, 50, 6, // Skip to: 2364 -/* 778 */ MCD_OPC_CheckField, 16, 10, 160, 4, 43, 6, // Skip to: 2364 -/* 785 */ MCD_OPC_Decode, 217, 13, 130, 2, // Opcode: TRUNC_W_D64 -/* 790 */ MCD_OPC_FilterValue, 14, 16, 0, // Skip to: 810 -/* 794 */ MCD_OPC_CheckPredicate, 45, 30, 6, // Skip to: 2364 -/* 798 */ MCD_OPC_CheckField, 16, 10, 160, 4, 23, 6, // Skip to: 2364 -/* 805 */ MCD_OPC_Decode, 226, 2, 130, 2, // Opcode: CEIL_W_D64 -/* 810 */ MCD_OPC_FilterValue, 15, 16, 0, // Skip to: 830 -/* 814 */ MCD_OPC_CheckPredicate, 45, 10, 6, // Skip to: 2364 -/* 818 */ MCD_OPC_CheckField, 16, 10, 160, 4, 3, 6, // Skip to: 2364 -/* 825 */ MCD_OPC_Decode, 242, 5, 130, 2, // Opcode: FLOOR_W_D64 -/* 830 */ MCD_OPC_FilterValue, 17, 41, 0, // Skip to: 875 -/* 834 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 837 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 856 -/* 841 */ MCD_OPC_CheckPredicate, 46, 239, 5, // Skip to: 2364 -/* 845 */ MCD_OPC_CheckField, 21, 5, 17, 233, 5, // Skip to: 2364 -/* 851 */ MCD_OPC_Decode, 238, 8, 131, 2, // Opcode: MOVF_D64 -/* 856 */ MCD_OPC_FilterValue, 1, 224, 5, // Skip to: 2364 -/* 860 */ MCD_OPC_CheckPredicate, 46, 220, 5, // Skip to: 2364 -/* 864 */ MCD_OPC_CheckField, 21, 5, 17, 214, 5, // Skip to: 2364 -/* 870 */ MCD_OPC_Decode, 130, 9, 131, 2, // Opcode: MOVT_D64 -/* 875 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 894 -/* 879 */ MCD_OPC_CheckPredicate, 46, 201, 5, // Skip to: 2364 -/* 883 */ MCD_OPC_CheckField, 21, 5, 17, 195, 5, // Skip to: 2364 -/* 889 */ MCD_OPC_Decode, 142, 9, 132, 2, // Opcode: MOVZ_I_D64 -/* 894 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 913 -/* 898 */ MCD_OPC_CheckPredicate, 46, 182, 5, // Skip to: 2364 -/* 902 */ MCD_OPC_CheckField, 21, 5, 17, 176, 5, // Skip to: 2364 -/* 908 */ MCD_OPC_Decode, 250, 8, 132, 2, // Opcode: MOVN_I_D64 -/* 913 */ MCD_OPC_FilterValue, 32, 31, 0, // Skip to: 948 -/* 917 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 920 */ MCD_OPC_FilterValue, 160, 4, 9, 0, // Skip to: 934 -/* 925 */ MCD_OPC_CheckPredicate, 44, 155, 5, // Skip to: 2364 -/* 929 */ MCD_OPC_Decode, 226, 3, 130, 2, // Opcode: CVT_S_D64 -/* 934 */ MCD_OPC_FilterValue, 160, 5, 145, 5, // Skip to: 2364 -/* 939 */ MCD_OPC_CheckPredicate, 44, 141, 5, // Skip to: 2364 -/* 943 */ MCD_OPC_Decode, 227, 3, 130, 2, // Opcode: CVT_S_L -/* 948 */ MCD_OPC_FilterValue, 33, 42, 0, // Skip to: 994 -/* 952 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 955 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 968 -/* 960 */ MCD_OPC_CheckPredicate, 44, 120, 5, // Skip to: 2364 -/* 964 */ MCD_OPC_Decode, 217, 3, 98, // Opcode: CVT_D64_S -/* 968 */ MCD_OPC_FilterValue, 128, 5, 8, 0, // Skip to: 981 -/* 973 */ MCD_OPC_CheckPredicate, 44, 107, 5, // Skip to: 2364 -/* 977 */ MCD_OPC_Decode, 218, 3, 98, // Opcode: CVT_D64_W -/* 981 */ MCD_OPC_FilterValue, 160, 5, 98, 5, // Skip to: 2364 -/* 986 */ MCD_OPC_CheckPredicate, 44, 94, 5, // Skip to: 2364 -/* 990 */ MCD_OPC_Decode, 216, 3, 105, // Opcode: CVT_D64_L -/* 994 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1014 -/* 998 */ MCD_OPC_CheckPredicate, 44, 82, 5, // Skip to: 2364 -/* 1002 */ MCD_OPC_CheckField, 16, 10, 160, 4, 75, 5, // Skip to: 2364 -/* 1009 */ MCD_OPC_Decode, 231, 3, 130, 2, // Opcode: CVT_W_D64 -/* 1014 */ MCD_OPC_FilterValue, 48, 21, 0, // Skip to: 1039 -/* 1018 */ MCD_OPC_CheckPredicate, 47, 62, 5, // Skip to: 2364 -/* 1022 */ MCD_OPC_CheckField, 21, 5, 17, 56, 5, // Skip to: 2364 -/* 1028 */ MCD_OPC_CheckField, 6, 5, 0, 50, 5, // Skip to: 2364 -/* 1034 */ MCD_OPC_Decode, 239, 3, 133, 2, // Opcode: C_F_D64 -/* 1039 */ MCD_OPC_FilterValue, 49, 21, 0, // Skip to: 1064 -/* 1043 */ MCD_OPC_CheckPredicate, 47, 37, 5, // Skip to: 2364 -/* 1047 */ MCD_OPC_CheckField, 21, 5, 17, 31, 5, // Skip to: 2364 -/* 1053 */ MCD_OPC_CheckField, 6, 5, 0, 25, 5, // Skip to: 2364 -/* 1059 */ MCD_OPC_Decode, 153, 4, 133, 2, // Opcode: C_UN_D64 -/* 1064 */ MCD_OPC_FilterValue, 50, 21, 0, // Skip to: 1089 -/* 1068 */ MCD_OPC_CheckPredicate, 47, 12, 5, // Skip to: 2364 -/* 1072 */ MCD_OPC_CheckField, 21, 5, 17, 6, 5, // Skip to: 2364 -/* 1078 */ MCD_OPC_CheckField, 6, 5, 0, 0, 5, // Skip to: 2364 -/* 1084 */ MCD_OPC_Decode, 236, 3, 133, 2, // Opcode: C_EQ_D64 -/* 1089 */ MCD_OPC_FilterValue, 51, 21, 0, // Skip to: 1114 -/* 1093 */ MCD_OPC_CheckPredicate, 47, 243, 4, // Skip to: 2364 -/* 1097 */ MCD_OPC_CheckField, 21, 5, 17, 237, 4, // Skip to: 2364 -/* 1103 */ MCD_OPC_CheckField, 6, 5, 0, 231, 4, // Skip to: 2364 -/* 1109 */ MCD_OPC_Decode, 144, 4, 133, 2, // Opcode: C_UEQ_D64 -/* 1114 */ MCD_OPC_FilterValue, 52, 21, 0, // Skip to: 1139 -/* 1118 */ MCD_OPC_CheckPredicate, 47, 218, 4, // Skip to: 2364 -/* 1122 */ MCD_OPC_CheckField, 21, 5, 17, 212, 4, // Skip to: 2364 -/* 1128 */ MCD_OPC_CheckField, 6, 5, 0, 206, 4, // Skip to: 2364 -/* 1134 */ MCD_OPC_Decode, 135, 4, 133, 2, // Opcode: C_OLT_D64 -/* 1139 */ MCD_OPC_FilterValue, 53, 21, 0, // Skip to: 1164 -/* 1143 */ MCD_OPC_CheckPredicate, 47, 193, 4, // Skip to: 2364 -/* 1147 */ MCD_OPC_CheckField, 21, 5, 17, 187, 4, // Skip to: 2364 -/* 1153 */ MCD_OPC_CheckField, 6, 5, 0, 181, 4, // Skip to: 2364 -/* 1159 */ MCD_OPC_Decode, 150, 4, 133, 2, // Opcode: C_ULT_D64 -/* 1164 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 1189 -/* 1168 */ MCD_OPC_CheckPredicate, 47, 168, 4, // Skip to: 2364 -/* 1172 */ MCD_OPC_CheckField, 21, 5, 17, 162, 4, // Skip to: 2364 -/* 1178 */ MCD_OPC_CheckField, 6, 5, 0, 156, 4, // Skip to: 2364 -/* 1184 */ MCD_OPC_Decode, 132, 4, 133, 2, // Opcode: C_OLE_D64 -/* 1189 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 1214 -/* 1193 */ MCD_OPC_CheckPredicate, 47, 143, 4, // Skip to: 2364 -/* 1197 */ MCD_OPC_CheckField, 21, 5, 17, 137, 4, // Skip to: 2364 -/* 1203 */ MCD_OPC_CheckField, 6, 5, 0, 131, 4, // Skip to: 2364 -/* 1209 */ MCD_OPC_Decode, 147, 4, 133, 2, // Opcode: C_ULE_D64 -/* 1214 */ MCD_OPC_FilterValue, 56, 21, 0, // Skip to: 1239 -/* 1218 */ MCD_OPC_CheckPredicate, 47, 118, 4, // Skip to: 2364 -/* 1222 */ MCD_OPC_CheckField, 21, 5, 17, 112, 4, // Skip to: 2364 -/* 1228 */ MCD_OPC_CheckField, 6, 5, 0, 106, 4, // Skip to: 2364 -/* 1234 */ MCD_OPC_Decode, 141, 4, 133, 2, // Opcode: C_SF_D64 -/* 1239 */ MCD_OPC_FilterValue, 57, 21, 0, // Skip to: 1264 -/* 1243 */ MCD_OPC_CheckPredicate, 47, 93, 4, // Skip to: 2364 -/* 1247 */ MCD_OPC_CheckField, 21, 5, 17, 87, 4, // Skip to: 2364 -/* 1253 */ MCD_OPC_CheckField, 6, 5, 0, 81, 4, // Skip to: 2364 -/* 1259 */ MCD_OPC_Decode, 251, 3, 133, 2, // Opcode: C_NGLE_D64 -/* 1264 */ MCD_OPC_FilterValue, 58, 21, 0, // Skip to: 1289 -/* 1268 */ MCD_OPC_CheckPredicate, 47, 68, 4, // Skip to: 2364 -/* 1272 */ MCD_OPC_CheckField, 21, 5, 17, 62, 4, // Skip to: 2364 -/* 1278 */ MCD_OPC_CheckField, 6, 5, 0, 56, 4, // Skip to: 2364 -/* 1284 */ MCD_OPC_Decode, 138, 4, 133, 2, // Opcode: C_SEQ_D64 -/* 1289 */ MCD_OPC_FilterValue, 59, 21, 0, // Skip to: 1314 -/* 1293 */ MCD_OPC_CheckPredicate, 47, 43, 4, // Skip to: 2364 -/* 1297 */ MCD_OPC_CheckField, 21, 5, 17, 37, 4, // Skip to: 2364 -/* 1303 */ MCD_OPC_CheckField, 6, 5, 0, 31, 4, // Skip to: 2364 -/* 1309 */ MCD_OPC_Decode, 254, 3, 133, 2, // Opcode: C_NGL_D64 -/* 1314 */ MCD_OPC_FilterValue, 60, 21, 0, // Skip to: 1339 -/* 1318 */ MCD_OPC_CheckPredicate, 47, 18, 4, // Skip to: 2364 -/* 1322 */ MCD_OPC_CheckField, 21, 5, 17, 12, 4, // Skip to: 2364 -/* 1328 */ MCD_OPC_CheckField, 6, 5, 0, 6, 4, // Skip to: 2364 -/* 1334 */ MCD_OPC_Decode, 245, 3, 133, 2, // Opcode: C_LT_D64 -/* 1339 */ MCD_OPC_FilterValue, 61, 21, 0, // Skip to: 1364 -/* 1343 */ MCD_OPC_CheckPredicate, 47, 249, 3, // Skip to: 2364 -/* 1347 */ MCD_OPC_CheckField, 21, 5, 17, 243, 3, // Skip to: 2364 -/* 1353 */ MCD_OPC_CheckField, 6, 5, 0, 237, 3, // Skip to: 2364 -/* 1359 */ MCD_OPC_Decode, 248, 3, 133, 2, // Opcode: C_NGE_D64 -/* 1364 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 1389 -/* 1368 */ MCD_OPC_CheckPredicate, 47, 224, 3, // Skip to: 2364 -/* 1372 */ MCD_OPC_CheckField, 21, 5, 17, 218, 3, // Skip to: 2364 -/* 1378 */ MCD_OPC_CheckField, 6, 5, 0, 212, 3, // Skip to: 2364 -/* 1384 */ MCD_OPC_Decode, 242, 3, 133, 2, // Opcode: C_LE_D64 -/* 1389 */ MCD_OPC_FilterValue, 63, 203, 3, // Skip to: 2364 -/* 1393 */ MCD_OPC_CheckPredicate, 47, 199, 3, // Skip to: 2364 -/* 1397 */ MCD_OPC_CheckField, 21, 5, 17, 193, 3, // Skip to: 2364 -/* 1403 */ MCD_OPC_CheckField, 6, 5, 0, 187, 3, // Skip to: 2364 -/* 1409 */ MCD_OPC_Decode, 129, 4, 133, 2, // Opcode: C_NGT_D64 -/* 1414 */ MCD_OPC_FilterValue, 18, 41, 0, // Skip to: 1459 -/* 1418 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1421 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1440 -/* 1425 */ MCD_OPC_CheckPredicate, 42, 167, 3, // Skip to: 2364 -/* 1429 */ MCD_OPC_CheckField, 3, 8, 0, 161, 3, // Skip to: 2364 -/* 1435 */ MCD_OPC_Decode, 198, 4, 255, 1, // Opcode: DMFC2 -/* 1440 */ MCD_OPC_FilterValue, 5, 152, 3, // Skip to: 2364 -/* 1444 */ MCD_OPC_CheckPredicate, 42, 148, 3, // Skip to: 2364 -/* 1448 */ MCD_OPC_CheckField, 3, 8, 0, 142, 3, // Skip to: 2364 -/* 1454 */ MCD_OPC_Decode, 203, 4, 255, 1, // Opcode: DMTC2 -/* 1459 */ MCD_OPC_FilterValue, 19, 131, 0, // Skip to: 1594 -/* 1463 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1466 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1485 -/* 1470 */ MCD_OPC_CheckPredicate, 48, 122, 3, // Skip to: 2364 -/* 1474 */ MCD_OPC_CheckField, 11, 5, 0, 116, 3, // Skip to: 2364 -/* 1480 */ MCD_OPC_Decode, 176, 7, 134, 2, // Opcode: LDXC164 -/* 1485 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 1504 -/* 1489 */ MCD_OPC_CheckPredicate, 49, 103, 3, // Skip to: 2364 -/* 1493 */ MCD_OPC_CheckField, 11, 5, 0, 97, 3, // Skip to: 2364 -/* 1499 */ MCD_OPC_Decode, 208, 7, 134, 2, // Opcode: LUXC164 -/* 1504 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1523 -/* 1508 */ MCD_OPC_CheckPredicate, 48, 84, 3, // Skip to: 2364 -/* 1512 */ MCD_OPC_CheckField, 6, 5, 0, 78, 3, // Skip to: 2364 -/* 1518 */ MCD_OPC_Decode, 167, 11, 135, 2, // Opcode: SDXC164 -/* 1523 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1542 -/* 1527 */ MCD_OPC_CheckPredicate, 49, 65, 3, // Skip to: 2364 -/* 1531 */ MCD_OPC_CheckField, 6, 5, 0, 59, 3, // Skip to: 2364 -/* 1537 */ MCD_OPC_Decode, 233, 12, 135, 2, // Opcode: SUXC164 -/* 1542 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 1555 -/* 1546 */ MCD_OPC_CheckPredicate, 48, 46, 3, // Skip to: 2364 -/* 1550 */ MCD_OPC_Decode, 144, 8, 136, 2, // Opcode: MADD_D64 -/* 1555 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 1568 -/* 1559 */ MCD_OPC_CheckPredicate, 48, 33, 3, // Skip to: 2364 -/* 1563 */ MCD_OPC_Decode, 162, 9, 136, 2, // Opcode: MSUB_D64 -/* 1568 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 1581 -/* 1572 */ MCD_OPC_CheckPredicate, 48, 20, 3, // Skip to: 2364 -/* 1576 */ MCD_OPC_Decode, 241, 9, 136, 2, // Opcode: NMADD_D64 -/* 1581 */ MCD_OPC_FilterValue, 57, 11, 3, // Skip to: 2364 -/* 1585 */ MCD_OPC_CheckPredicate, 48, 7, 3, // Skip to: 2364 -/* 1589 */ MCD_OPC_Decode, 246, 9, 136, 2, // Opcode: NMSUB_D64 -/* 1594 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1607 -/* 1598 */ MCD_OPC_CheckPredicate, 41, 250, 2, // Skip to: 2364 -/* 1602 */ MCD_OPC_Decode, 160, 4, 137, 2, // Opcode: DADDi -/* 1607 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 1620 -/* 1611 */ MCD_OPC_CheckPredicate, 19, 237, 2, // Skip to: 2364 -/* 1615 */ MCD_OPC_Decode, 161, 4, 137, 2, // Opcode: DADDiu -/* 1620 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 1633 -/* 1624 */ MCD_OPC_CheckPredicate, 41, 224, 2, // Skip to: 2364 -/* 1628 */ MCD_OPC_Decode, 172, 7, 217, 1, // Opcode: LDL -/* 1633 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 1646 -/* 1637 */ MCD_OPC_CheckPredicate, 41, 211, 2, // Skip to: 2364 -/* 1641 */ MCD_OPC_Decode, 174, 7, 217, 1, // Opcode: LDR -/* 1646 */ MCD_OPC_FilterValue, 28, 159, 1, // Skip to: 2065 -/* 1650 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1653 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1672 -/* 1657 */ MCD_OPC_CheckPredicate, 50, 191, 2, // Skip to: 2364 -/* 1661 */ MCD_OPC_CheckField, 6, 5, 0, 185, 2, // Skip to: 2364 -/* 1667 */ MCD_OPC_Decode, 206, 4, 224, 1, // Opcode: DMUL -/* 1672 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 1691 -/* 1676 */ MCD_OPC_CheckPredicate, 50, 172, 2, // Skip to: 2364 -/* 1680 */ MCD_OPC_CheckField, 6, 15, 0, 166, 2, // Skip to: 2364 -/* 1686 */ MCD_OPC_Decode, 185, 9, 138, 2, // Opcode: MTM0 -/* 1691 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1710 -/* 1695 */ MCD_OPC_CheckPredicate, 50, 153, 2, // Skip to: 2364 -/* 1699 */ MCD_OPC_CheckField, 6, 15, 0, 147, 2, // Skip to: 2364 -/* 1705 */ MCD_OPC_Decode, 188, 9, 138, 2, // Opcode: MTP0 -/* 1710 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1729 -/* 1714 */ MCD_OPC_CheckPredicate, 50, 134, 2, // Skip to: 2364 -/* 1718 */ MCD_OPC_CheckField, 6, 15, 0, 128, 2, // Skip to: 2364 -/* 1724 */ MCD_OPC_Decode, 189, 9, 138, 2, // Opcode: MTP1 -/* 1729 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 1748 -/* 1733 */ MCD_OPC_CheckPredicate, 50, 115, 2, // Skip to: 2364 -/* 1737 */ MCD_OPC_CheckField, 6, 15, 0, 109, 2, // Skip to: 2364 -/* 1743 */ MCD_OPC_Decode, 190, 9, 138, 2, // Opcode: MTP2 -/* 1748 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 1767 -/* 1752 */ MCD_OPC_CheckPredicate, 50, 96, 2, // Skip to: 2364 -/* 1756 */ MCD_OPC_CheckField, 6, 15, 0, 90, 2, // Skip to: 2364 -/* 1762 */ MCD_OPC_Decode, 186, 9, 138, 2, // Opcode: MTM1 -/* 1767 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1786 -/* 1771 */ MCD_OPC_CheckPredicate, 50, 77, 2, // Skip to: 2364 -/* 1775 */ MCD_OPC_CheckField, 6, 15, 0, 71, 2, // Skip to: 2364 -/* 1781 */ MCD_OPC_Decode, 187, 9, 138, 2, // Opcode: MTM2 -/* 1786 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 1805 -/* 1790 */ MCD_OPC_CheckPredicate, 50, 58, 2, // Skip to: 2364 -/* 1794 */ MCD_OPC_CheckField, 6, 5, 0, 52, 2, // Skip to: 2364 -/* 1800 */ MCD_OPC_Decode, 226, 13, 224, 1, // Opcode: VMULU -/* 1805 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 1824 -/* 1809 */ MCD_OPC_CheckPredicate, 50, 39, 2, // Skip to: 2364 -/* 1813 */ MCD_OPC_CheckField, 6, 5, 0, 33, 2, // Skip to: 2364 -/* 1819 */ MCD_OPC_Decode, 225, 13, 224, 1, // Opcode: VMM0 -/* 1824 */ MCD_OPC_FilterValue, 17, 15, 0, // Skip to: 1843 -/* 1828 */ MCD_OPC_CheckPredicate, 50, 20, 2, // Skip to: 2364 -/* 1832 */ MCD_OPC_CheckField, 6, 5, 0, 14, 2, // Skip to: 2364 -/* 1838 */ MCD_OPC_Decode, 224, 13, 224, 1, // Opcode: V3MULU -/* 1843 */ MCD_OPC_FilterValue, 36, 15, 0, // Skip to: 1862 -/* 1847 */ MCD_OPC_CheckPredicate, 51, 1, 2, // Skip to: 2364 -/* 1851 */ MCD_OPC_CheckField, 6, 5, 0, 251, 1, // Skip to: 2364 -/* 1857 */ MCD_OPC_Decode, 170, 4, 139, 2, // Opcode: DCLZ -/* 1862 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1881 -/* 1866 */ MCD_OPC_CheckPredicate, 51, 238, 1, // Skip to: 2364 -/* 1870 */ MCD_OPC_CheckField, 6, 5, 0, 232, 1, // Skip to: 2364 -/* 1876 */ MCD_OPC_Decode, 168, 4, 139, 2, // Opcode: DCLO -/* 1881 */ MCD_OPC_FilterValue, 40, 15, 0, // Skip to: 1900 -/* 1885 */ MCD_OPC_CheckPredicate, 50, 219, 1, // Skip to: 2364 -/* 1889 */ MCD_OPC_CheckField, 6, 5, 0, 213, 1, // Skip to: 2364 -/* 1895 */ MCD_OPC_Decode, 166, 1, 224, 1, // Opcode: BADDu -/* 1900 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 1919 -/* 1904 */ MCD_OPC_CheckPredicate, 50, 200, 1, // Skip to: 2364 -/* 1908 */ MCD_OPC_CheckField, 6, 5, 0, 194, 1, // Skip to: 2364 -/* 1914 */ MCD_OPC_Decode, 184, 11, 224, 1, // Opcode: SEQ -/* 1919 */ MCD_OPC_FilterValue, 43, 15, 0, // Skip to: 1938 -/* 1923 */ MCD_OPC_CheckPredicate, 50, 181, 1, // Skip to: 2364 -/* 1927 */ MCD_OPC_CheckField, 6, 5, 0, 175, 1, // Skip to: 2364 -/* 1933 */ MCD_OPC_Decode, 252, 11, 224, 1, // Opcode: SNE -/* 1938 */ MCD_OPC_FilterValue, 44, 20, 0, // Skip to: 1962 -/* 1942 */ MCD_OPC_CheckPredicate, 50, 162, 1, // Skip to: 2364 -/* 1946 */ MCD_OPC_CheckField, 16, 5, 0, 156, 1, // Skip to: 2364 -/* 1952 */ MCD_OPC_CheckField, 6, 5, 0, 150, 1, // Skip to: 2364 -/* 1958 */ MCD_OPC_Decode, 163, 10, 62, // Opcode: POP -/* 1962 */ MCD_OPC_FilterValue, 45, 21, 0, // Skip to: 1987 -/* 1966 */ MCD_OPC_CheckPredicate, 50, 138, 1, // Skip to: 2364 -/* 1970 */ MCD_OPC_CheckField, 16, 5, 0, 132, 1, // Skip to: 2364 -/* 1976 */ MCD_OPC_CheckField, 6, 5, 0, 126, 1, // Skip to: 2364 -/* 1982 */ MCD_OPC_Decode, 231, 4, 222, 1, // Opcode: DPOP -/* 1987 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 2000 -/* 1991 */ MCD_OPC_CheckPredicate, 50, 113, 1, // Skip to: 2364 -/* 1995 */ MCD_OPC_Decode, 185, 11, 140, 2, // Opcode: SEQi -/* 2000 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 2013 -/* 2004 */ MCD_OPC_CheckPredicate, 50, 100, 1, // Skip to: 2364 -/* 2008 */ MCD_OPC_Decode, 253, 11, 140, 2, // Opcode: SNEi -/* 2013 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2026 -/* 2017 */ MCD_OPC_CheckPredicate, 50, 87, 1, // Skip to: 2364 -/* 2021 */ MCD_OPC_Decode, 241, 2, 141, 2, // Opcode: CINS -/* 2026 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 2039 -/* 2030 */ MCD_OPC_CheckPredicate, 50, 74, 1, // Skip to: 2364 -/* 2034 */ MCD_OPC_Decode, 242, 2, 141, 2, // Opcode: CINS32 -/* 2039 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2052 -/* 2043 */ MCD_OPC_CheckPredicate, 50, 61, 1, // Skip to: 2364 -/* 2047 */ MCD_OPC_Decode, 158, 5, 141, 2, // Opcode: EXTS -/* 2052 */ MCD_OPC_FilterValue, 59, 52, 1, // Skip to: 2364 -/* 2056 */ MCD_OPC_CheckPredicate, 50, 48, 1, // Skip to: 2364 -/* 2060 */ MCD_OPC_Decode, 159, 5, 141, 2, // Opcode: EXTS32 -/* 2065 */ MCD_OPC_FilterValue, 31, 126, 0, // Skip to: 2195 -/* 2069 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 2072 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 2085 -/* 2076 */ MCD_OPC_CheckPredicate, 6, 28, 1, // Skip to: 2364 -/* 2080 */ MCD_OPC_Decode, 177, 4, 142, 2, // Opcode: DEXTM -/* 2085 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 2098 -/* 2089 */ MCD_OPC_CheckPredicate, 6, 15, 1, // Skip to: 2364 -/* 2093 */ MCD_OPC_Decode, 178, 4, 142, 2, // Opcode: DEXTU -/* 2098 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 2111 -/* 2102 */ MCD_OPC_CheckPredicate, 6, 2, 1, // Skip to: 2364 -/* 2106 */ MCD_OPC_Decode, 176, 4, 142, 2, // Opcode: DEXT -/* 2111 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 2124 -/* 2115 */ MCD_OPC_CheckPredicate, 6, 245, 0, // Skip to: 2364 -/* 2119 */ MCD_OPC_Decode, 181, 4, 143, 2, // Opcode: DINSM -/* 2124 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 2137 -/* 2128 */ MCD_OPC_CheckPredicate, 6, 232, 0, // Skip to: 2364 -/* 2132 */ MCD_OPC_Decode, 182, 4, 143, 2, // Opcode: DINSU -/* 2137 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 2150 -/* 2141 */ MCD_OPC_CheckPredicate, 6, 219, 0, // Skip to: 2364 -/* 2145 */ MCD_OPC_Decode, 180, 4, 143, 2, // Opcode: DINS -/* 2150 */ MCD_OPC_FilterValue, 36, 210, 0, // Skip to: 2364 -/* 2154 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 2157 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2176 -/* 2161 */ MCD_OPC_CheckPredicate, 40, 199, 0, // Skip to: 2364 -/* 2165 */ MCD_OPC_CheckField, 21, 5, 0, 193, 0, // Skip to: 2364 -/* 2171 */ MCD_OPC_Decode, 249, 4, 243, 1, // Opcode: DSBH -/* 2176 */ MCD_OPC_FilterValue, 5, 184, 0, // Skip to: 2364 -/* 2180 */ MCD_OPC_CheckPredicate, 40, 180, 0, // Skip to: 2364 -/* 2184 */ MCD_OPC_CheckField, 21, 5, 0, 174, 0, // Skip to: 2364 -/* 2190 */ MCD_OPC_Decode, 251, 4, 243, 1, // Opcode: DSHD -/* 2195 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 2208 -/* 2199 */ MCD_OPC_CheckPredicate, 19, 161, 0, // Skip to: 2364 -/* 2203 */ MCD_OPC_Decode, 241, 7, 217, 1, // Opcode: LWu -/* 2208 */ MCD_OPC_FilterValue, 44, 9, 0, // Skip to: 2221 -/* 2212 */ MCD_OPC_CheckPredicate, 41, 148, 0, // Skip to: 2364 -/* 2216 */ MCD_OPC_Decode, 164, 11, 217, 1, // Opcode: SDL -/* 2221 */ MCD_OPC_FilterValue, 45, 9, 0, // Skip to: 2234 -/* 2225 */ MCD_OPC_CheckPredicate, 41, 135, 0, // Skip to: 2364 -/* 2229 */ MCD_OPC_Decode, 165, 11, 217, 1, // Opcode: SDR -/* 2234 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2247 -/* 2238 */ MCD_OPC_CheckPredicate, 50, 122, 0, // Skip to: 2364 -/* 2242 */ MCD_OPC_Decode, 171, 1, 144, 2, // Opcode: BBIT0 -/* 2247 */ MCD_OPC_FilterValue, 52, 9, 0, // Skip to: 2260 -/* 2251 */ MCD_OPC_CheckPredicate, 41, 109, 0, // Skip to: 2364 -/* 2255 */ MCD_OPC_Decode, 194, 7, 217, 1, // Opcode: LLD -/* 2260 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 2273 -/* 2264 */ MCD_OPC_CheckPredicate, 52, 96, 0, // Skip to: 2364 -/* 2268 */ MCD_OPC_Decode, 163, 7, 219, 1, // Opcode: LDC164 -/* 2273 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 2286 -/* 2277 */ MCD_OPC_CheckPredicate, 50, 83, 0, // Skip to: 2364 -/* 2281 */ MCD_OPC_Decode, 172, 1, 144, 2, // Opcode: BBIT032 -/* 2286 */ MCD_OPC_FilterValue, 55, 9, 0, // Skip to: 2299 -/* 2290 */ MCD_OPC_CheckPredicate, 19, 70, 0, // Skip to: 2364 -/* 2294 */ MCD_OPC_Decode, 161, 7, 217, 1, // Opcode: LD -/* 2299 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2312 -/* 2303 */ MCD_OPC_CheckPredicate, 50, 57, 0, // Skip to: 2364 -/* 2307 */ MCD_OPC_Decode, 173, 1, 144, 2, // Opcode: BBIT1 -/* 2312 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 2325 -/* 2316 */ MCD_OPC_CheckPredicate, 41, 44, 0, // Skip to: 2364 -/* 2320 */ MCD_OPC_Decode, 147, 11, 217, 1, // Opcode: SCD -/* 2325 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 2338 -/* 2329 */ MCD_OPC_CheckPredicate, 52, 31, 0, // Skip to: 2364 -/* 2333 */ MCD_OPC_Decode, 157, 11, 219, 1, // Opcode: SDC164 -/* 2338 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 2351 -/* 2342 */ MCD_OPC_CheckPredicate, 50, 18, 0, // Skip to: 2364 -/* 2346 */ MCD_OPC_Decode, 174, 1, 144, 2, // Opcode: BBIT132 -/* 2351 */ MCD_OPC_FilterValue, 63, 9, 0, // Skip to: 2364 -/* 2355 */ MCD_OPC_CheckPredicate, 19, 5, 0, // Skip to: 2364 -/* 2359 */ MCD_OPC_Decode, 151, 11, 217, 1, // Opcode: SD -/* 2364 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 0, 236, 1, 0, // Skip to: 500 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 32 +/* 16 */ MCD_OPC_CheckPredicate, 88, 244, 4, 0, // Skip to: 1289 +/* 21 */ MCD_OPC_CheckField, 6, 15, 16, 237, 4, 0, // Skip to: 1289 +/* 28 */ MCD_OPC_Decode, 141, 15, 24, // Opcode: JR_HB64 +/* 32 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 82 +/* 37 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 40 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 61 +/* 45 */ MCD_OPC_CheckPredicate, 89, 215, 4, 0, // Skip to: 1289 +/* 50 */ MCD_OPC_CheckField, 16, 5, 0, 208, 4, 0, // Skip to: 1289 +/* 57 */ MCD_OPC_Decode, 238, 14, 26, // Opcode: JALR64 +/* 61 */ MCD_OPC_FilterValue, 16, 199, 4, 0, // Skip to: 1289 +/* 66 */ MCD_OPC_CheckPredicate, 90, 194, 4, 0, // Skip to: 1289 +/* 71 */ MCD_OPC_CheckField, 16, 5, 0, 187, 4, 0, // Skip to: 1289 +/* 78 */ MCD_OPC_Decode, 248, 14, 26, // Opcode: JALR_HB64 +/* 82 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 104 +/* 87 */ MCD_OPC_CheckPredicate, 91, 173, 4, 0, // Skip to: 1289 +/* 92 */ MCD_OPC_CheckField, 6, 5, 0, 166, 4, 0, // Skip to: 1289 +/* 99 */ MCD_OPC_Decode, 190, 12, 249, 2, // Opcode: DSLLV +/* 104 */ MCD_OPC_FilterValue, 22, 33, 0, 0, // Skip to: 142 +/* 109 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 112 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 127 +/* 117 */ MCD_OPC_CheckPredicate, 91, 143, 4, 0, // Skip to: 1289 +/* 122 */ MCD_OPC_Decode, 196, 12, 249, 2, // Opcode: DSRLV +/* 127 */ MCD_OPC_FilterValue, 1, 133, 4, 0, // Skip to: 1289 +/* 132 */ MCD_OPC_CheckPredicate, 90, 128, 4, 0, // Skip to: 1289 +/* 137 */ MCD_OPC_Decode, 183, 12, 249, 2, // Opcode: DROTRV +/* 142 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 164 +/* 147 */ MCD_OPC_CheckPredicate, 91, 113, 4, 0, // Skip to: 1289 +/* 152 */ MCD_OPC_CheckField, 6, 5, 0, 106, 4, 0, // Skip to: 1289 +/* 159 */ MCD_OPC_Decode, 193, 12, 249, 2, // Opcode: DSRAV +/* 164 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 186 +/* 169 */ MCD_OPC_CheckPredicate, 92, 91, 4, 0, // Skip to: 1289 +/* 174 */ MCD_OPC_CheckField, 6, 10, 0, 84, 4, 0, // Skip to: 1289 +/* 181 */ MCD_OPC_Decode, 254, 11, 250, 2, // Opcode: DMULT +/* 186 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 208 +/* 191 */ MCD_OPC_CheckPredicate, 92, 69, 4, 0, // Skip to: 1289 +/* 196 */ MCD_OPC_CheckField, 6, 10, 0, 62, 4, 0, // Skip to: 1289 +/* 203 */ MCD_OPC_Decode, 255, 11, 250, 2, // Opcode: DMULTu +/* 208 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 230 +/* 213 */ MCD_OPC_CheckPredicate, 92, 47, 4, 0, // Skip to: 1289 +/* 218 */ MCD_OPC_CheckField, 6, 10, 0, 40, 4, 0, // Skip to: 1289 +/* 225 */ MCD_OPC_Decode, 185, 12, 250, 2, // Opcode: DSDIV +/* 230 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 252 +/* 235 */ MCD_OPC_CheckPredicate, 92, 25, 4, 0, // Skip to: 1289 +/* 240 */ MCD_OPC_CheckField, 6, 10, 0, 18, 4, 0, // Skip to: 1289 +/* 247 */ MCD_OPC_Decode, 199, 12, 250, 2, // Opcode: DUDIV +/* 252 */ MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 273 +/* 257 */ MCD_OPC_CheckPredicate, 91, 3, 4, 0, // Skip to: 1289 +/* 262 */ MCD_OPC_CheckField, 6, 5, 0, 252, 3, 0, // Skip to: 1289 +/* 269 */ MCD_OPC_Decode, 191, 11, 23, // Opcode: DADD +/* 273 */ MCD_OPC_FilterValue, 45, 16, 0, 0, // Skip to: 294 +/* 278 */ MCD_OPC_CheckPredicate, 91, 238, 3, 0, // Skip to: 1289 +/* 283 */ MCD_OPC_CheckField, 6, 5, 0, 231, 3, 0, // Skip to: 1289 +/* 290 */ MCD_OPC_Decode, 194, 11, 23, // Opcode: DADDu +/* 294 */ MCD_OPC_FilterValue, 46, 16, 0, 0, // Skip to: 315 +/* 299 */ MCD_OPC_CheckPredicate, 91, 217, 3, 0, // Skip to: 1289 +/* 304 */ MCD_OPC_CheckField, 6, 5, 0, 210, 3, 0, // Skip to: 1289 +/* 311 */ MCD_OPC_Decode, 197, 12, 23, // Opcode: DSUB +/* 315 */ MCD_OPC_FilterValue, 47, 16, 0, 0, // Skip to: 336 +/* 320 */ MCD_OPC_CheckPredicate, 91, 196, 3, 0, // Skip to: 1289 +/* 325 */ MCD_OPC_CheckField, 6, 5, 0, 189, 3, 0, // Skip to: 1289 +/* 332 */ MCD_OPC_Decode, 198, 12, 23, // Opcode: DSUBu +/* 336 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 358 +/* 341 */ MCD_OPC_CheckPredicate, 91, 175, 3, 0, // Skip to: 1289 +/* 346 */ MCD_OPC_CheckField, 21, 5, 0, 168, 3, 0, // Skip to: 1289 +/* 353 */ MCD_OPC_Decode, 187, 12, 251, 2, // Opcode: DSLL +/* 358 */ MCD_OPC_FilterValue, 58, 33, 0, 0, // Skip to: 396 +/* 363 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 366 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 381 +/* 371 */ MCD_OPC_CheckPredicate, 91, 145, 3, 0, // Skip to: 1289 +/* 376 */ MCD_OPC_Decode, 194, 12, 251, 2, // Opcode: DSRL +/* 381 */ MCD_OPC_FilterValue, 1, 135, 3, 0, // Skip to: 1289 +/* 386 */ MCD_OPC_CheckPredicate, 90, 130, 3, 0, // Skip to: 1289 +/* 391 */ MCD_OPC_Decode, 181, 12, 251, 2, // Opcode: DROTR +/* 396 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 418 +/* 401 */ MCD_OPC_CheckPredicate, 91, 115, 3, 0, // Skip to: 1289 +/* 406 */ MCD_OPC_CheckField, 21, 5, 0, 108, 3, 0, // Skip to: 1289 +/* 413 */ MCD_OPC_Decode, 191, 12, 251, 2, // Opcode: DSRA +/* 418 */ MCD_OPC_FilterValue, 60, 17, 0, 0, // Skip to: 440 +/* 423 */ MCD_OPC_CheckPredicate, 91, 93, 3, 0, // Skip to: 1289 +/* 428 */ MCD_OPC_CheckField, 21, 5, 0, 86, 3, 0, // Skip to: 1289 +/* 435 */ MCD_OPC_Decode, 188, 12, 251, 2, // Opcode: DSLL32 +/* 440 */ MCD_OPC_FilterValue, 62, 33, 0, 0, // Skip to: 478 +/* 445 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 448 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 463 +/* 453 */ MCD_OPC_CheckPredicate, 91, 63, 3, 0, // Skip to: 1289 +/* 458 */ MCD_OPC_Decode, 195, 12, 251, 2, // Opcode: DSRL32 +/* 463 */ MCD_OPC_FilterValue, 1, 53, 3, 0, // Skip to: 1289 +/* 468 */ MCD_OPC_CheckPredicate, 90, 48, 3, 0, // Skip to: 1289 +/* 473 */ MCD_OPC_Decode, 182, 12, 251, 2, // Opcode: DROTR32 +/* 478 */ MCD_OPC_FilterValue, 63, 38, 3, 0, // Skip to: 1289 +/* 483 */ MCD_OPC_CheckPredicate, 91, 33, 3, 0, // Skip to: 1289 +/* 488 */ MCD_OPC_CheckField, 21, 5, 0, 26, 3, 0, // Skip to: 1289 +/* 495 */ MCD_OPC_Decode, 192, 12, 251, 2, // Opcode: DSRA32 +/* 500 */ MCD_OPC_FilterValue, 16, 85, 0, 0, // Skip to: 590 +/* 505 */ MCD_OPC_ExtractField, 3, 8, // Inst{10-3} ... +/* 508 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 546 +/* 513 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 516 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 531 +/* 521 */ MCD_OPC_CheckPredicate, 93, 251, 2, 0, // Skip to: 1289 +/* 526 */ MCD_OPC_Decode, 237, 11, 252, 2, // Opcode: DMFC0 +/* 531 */ MCD_OPC_FilterValue, 5, 241, 2, 0, // Skip to: 1289 +/* 536 */ MCD_OPC_CheckPredicate, 93, 236, 2, 0, // Skip to: 1289 +/* 541 */ MCD_OPC_Decode, 245, 11, 253, 2, // Opcode: DMTC0 +/* 546 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 568 +/* 551 */ MCD_OPC_CheckPredicate, 94, 221, 2, 0, // Skip to: 1289 +/* 556 */ MCD_OPC_CheckField, 21, 5, 3, 214, 2, 0, // Skip to: 1289 +/* 563 */ MCD_OPC_Decode, 241, 11, 252, 2, // Opcode: DMFGC0 +/* 568 */ MCD_OPC_FilterValue, 96, 204, 2, 0, // Skip to: 1289 +/* 573 */ MCD_OPC_CheckPredicate, 94, 199, 2, 0, // Skip to: 1289 +/* 578 */ MCD_OPC_CheckField, 21, 5, 3, 192, 2, 0, // Skip to: 1289 +/* 585 */ MCD_OPC_Decode, 249, 11, 253, 2, // Opcode: DMTGC0 +/* 590 */ MCD_OPC_FilterValue, 18, 47, 0, 0, // Skip to: 642 +/* 595 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 598 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 620 +/* 603 */ MCD_OPC_CheckPredicate, 93, 169, 2, 0, // Skip to: 1289 +/* 608 */ MCD_OPC_CheckField, 3, 8, 0, 162, 2, 0, // Skip to: 1289 +/* 615 */ MCD_OPC_Decode, 239, 11, 254, 2, // Opcode: DMFC2 +/* 620 */ MCD_OPC_FilterValue, 5, 152, 2, 0, // Skip to: 1289 +/* 625 */ MCD_OPC_CheckPredicate, 93, 147, 2, 0, // Skip to: 1289 +/* 630 */ MCD_OPC_CheckField, 3, 8, 0, 140, 2, 0, // Skip to: 1289 +/* 637 */ MCD_OPC_Decode, 247, 11, 255, 2, // Opcode: DMTC2 +/* 642 */ MCD_OPC_FilterValue, 21, 3, 1, 0, // Skip to: 906 +/* 647 */ MCD_OPC_ExtractField, 0, 13, // Inst{12-0} ... +/* 650 */ MCD_OPC_FilterValue, 188, 8, 10, 0, 0, // Skip to: 666 +/* 656 */ MCD_OPC_CheckPredicate, 15, 116, 2, 0, // Skip to: 1289 +/* 661 */ MCD_OPC_Decode, 229, 10, 128, 3, // Opcode: C_F_D64_MM +/* 666 */ MCD_OPC_FilterValue, 252, 8, 10, 0, 0, // Skip to: 682 +/* 672 */ MCD_OPC_CheckPredicate, 15, 100, 2, 0, // Skip to: 1289 +/* 677 */ MCD_OPC_Decode, 185, 11, 128, 3, // Opcode: C_UN_D64_MM +/* 682 */ MCD_OPC_FilterValue, 188, 9, 10, 0, 0, // Skip to: 698 +/* 688 */ MCD_OPC_CheckPredicate, 15, 84, 2, 0, // Skip to: 1289 +/* 693 */ MCD_OPC_Decode, 223, 10, 128, 3, // Opcode: C_EQ_D64_MM +/* 698 */ MCD_OPC_FilterValue, 252, 9, 10, 0, 0, // Skip to: 714 +/* 704 */ MCD_OPC_CheckPredicate, 15, 68, 2, 0, // Skip to: 1289 +/* 709 */ MCD_OPC_Decode, 167, 11, 128, 3, // Opcode: C_UEQ_D64_MM +/* 714 */ MCD_OPC_FilterValue, 188, 10, 10, 0, 0, // Skip to: 730 +/* 720 */ MCD_OPC_CheckPredicate, 15, 52, 2, 0, // Skip to: 1289 +/* 725 */ MCD_OPC_Decode, 149, 11, 128, 3, // Opcode: C_OLT_D64_MM +/* 730 */ MCD_OPC_FilterValue, 252, 10, 10, 0, 0, // Skip to: 746 +/* 736 */ MCD_OPC_CheckPredicate, 15, 36, 2, 0, // Skip to: 1289 +/* 741 */ MCD_OPC_Decode, 179, 11, 128, 3, // Opcode: C_ULT_D64_MM +/* 746 */ MCD_OPC_FilterValue, 188, 11, 10, 0, 0, // Skip to: 762 +/* 752 */ MCD_OPC_CheckPredicate, 15, 20, 2, 0, // Skip to: 1289 +/* 757 */ MCD_OPC_Decode, 143, 11, 128, 3, // Opcode: C_OLE_D64_MM +/* 762 */ MCD_OPC_FilterValue, 252, 11, 10, 0, 0, // Skip to: 778 +/* 768 */ MCD_OPC_CheckPredicate, 15, 4, 2, 0, // Skip to: 1289 +/* 773 */ MCD_OPC_Decode, 173, 11, 128, 3, // Opcode: C_ULE_D64_MM +/* 778 */ MCD_OPC_FilterValue, 188, 12, 10, 0, 0, // Skip to: 794 +/* 784 */ MCD_OPC_CheckPredicate, 15, 244, 1, 0, // Skip to: 1289 +/* 789 */ MCD_OPC_Decode, 161, 11, 128, 3, // Opcode: C_SF_D64_MM +/* 794 */ MCD_OPC_FilterValue, 252, 12, 10, 0, 0, // Skip to: 810 +/* 800 */ MCD_OPC_CheckPredicate, 15, 228, 1, 0, // Skip to: 1289 +/* 805 */ MCD_OPC_Decode, 253, 10, 128, 3, // Opcode: C_NGLE_D64_MM +/* 810 */ MCD_OPC_FilterValue, 188, 13, 10, 0, 0, // Skip to: 826 +/* 816 */ MCD_OPC_CheckPredicate, 15, 212, 1, 0, // Skip to: 1289 +/* 821 */ MCD_OPC_Decode, 155, 11, 128, 3, // Opcode: C_SEQ_D64_MM +/* 826 */ MCD_OPC_FilterValue, 252, 13, 10, 0, 0, // Skip to: 842 +/* 832 */ MCD_OPC_CheckPredicate, 15, 196, 1, 0, // Skip to: 1289 +/* 837 */ MCD_OPC_Decode, 131, 11, 128, 3, // Opcode: C_NGL_D64_MM +/* 842 */ MCD_OPC_FilterValue, 188, 14, 10, 0, 0, // Skip to: 858 +/* 848 */ MCD_OPC_CheckPredicate, 15, 180, 1, 0, // Skip to: 1289 +/* 853 */ MCD_OPC_Decode, 241, 10, 128, 3, // Opcode: C_LT_D64_MM +/* 858 */ MCD_OPC_FilterValue, 252, 14, 10, 0, 0, // Skip to: 874 +/* 864 */ MCD_OPC_CheckPredicate, 15, 164, 1, 0, // Skip to: 1289 +/* 869 */ MCD_OPC_Decode, 247, 10, 128, 3, // Opcode: C_NGE_D64_MM +/* 874 */ MCD_OPC_FilterValue, 188, 15, 10, 0, 0, // Skip to: 890 +/* 880 */ MCD_OPC_CheckPredicate, 15, 148, 1, 0, // Skip to: 1289 +/* 885 */ MCD_OPC_Decode, 235, 10, 128, 3, // Opcode: C_LE_D64_MM +/* 890 */ MCD_OPC_FilterValue, 252, 15, 137, 1, 0, // Skip to: 1289 +/* 896 */ MCD_OPC_CheckPredicate, 15, 132, 1, 0, // Skip to: 1289 +/* 901 */ MCD_OPC_Decode, 137, 11, 128, 3, // Opcode: C_NGT_D64_MM +/* 906 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 921 +/* 911 */ MCD_OPC_CheckPredicate, 95, 117, 1, 0, // Skip to: 1289 +/* 916 */ MCD_OPC_Decode, 192, 11, 129, 3, // Opcode: DADDi +/* 921 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 936 +/* 926 */ MCD_OPC_CheckPredicate, 91, 102, 1, 0, // Skip to: 1289 +/* 931 */ MCD_OPC_Decode, 193, 11, 129, 3, // Opcode: DADDiu +/* 936 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 951 +/* 941 */ MCD_OPC_CheckPredicate, 95, 87, 1, 0, // Skip to: 1289 +/* 946 */ MCD_OPC_Decode, 193, 15, 141, 1, // Opcode: LDL +/* 951 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 966 +/* 956 */ MCD_OPC_CheckPredicate, 95, 72, 1, 0, // Skip to: 1289 +/* 961 */ MCD_OPC_Decode, 195, 15, 141, 1, // Opcode: LDR +/* 966 */ MCD_OPC_FilterValue, 28, 33, 0, 0, // Skip to: 1004 +/* 971 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 974 */ MCD_OPC_FilterValue, 36, 10, 0, 0, // Skip to: 989 +/* 979 */ MCD_OPC_CheckPredicate, 96, 49, 1, 0, // Skip to: 1289 +/* 984 */ MCD_OPC_Decode, 202, 11, 130, 3, // Opcode: DCLZ +/* 989 */ MCD_OPC_FilterValue, 37, 39, 1, 0, // Skip to: 1289 +/* 994 */ MCD_OPC_CheckPredicate, 96, 34, 1, 0, // Skip to: 1289 +/* 999 */ MCD_OPC_Decode, 200, 11, 130, 3, // Opcode: DCLO +/* 1004 */ MCD_OPC_FilterValue, 31, 145, 0, 0, // Skip to: 1154 +/* 1009 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1012 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1027 +/* 1017 */ MCD_OPC_CheckPredicate, 90, 11, 1, 0, // Skip to: 1289 +/* 1022 */ MCD_OPC_Decode, 212, 11, 131, 3, // Opcode: DEXTM +/* 1027 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1042 +/* 1032 */ MCD_OPC_CheckPredicate, 90, 252, 0, 0, // Skip to: 1289 +/* 1037 */ MCD_OPC_Decode, 213, 11, 131, 3, // Opcode: DEXTU +/* 1042 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1057 +/* 1047 */ MCD_OPC_CheckPredicate, 90, 237, 0, 0, // Skip to: 1289 +/* 1052 */ MCD_OPC_Decode, 210, 11, 131, 3, // Opcode: DEXT +/* 1057 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1072 +/* 1062 */ MCD_OPC_CheckPredicate, 90, 222, 0, 0, // Skip to: 1289 +/* 1067 */ MCD_OPC_Decode, 216, 11, 132, 3, // Opcode: DINSM +/* 1072 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1087 +/* 1077 */ MCD_OPC_CheckPredicate, 90, 207, 0, 0, // Skip to: 1289 +/* 1082 */ MCD_OPC_Decode, 217, 11, 132, 3, // Opcode: DINSU +/* 1087 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1102 +/* 1092 */ MCD_OPC_CheckPredicate, 90, 192, 0, 0, // Skip to: 1289 +/* 1097 */ MCD_OPC_Decode, 215, 11, 132, 3, // Opcode: DINS +/* 1102 */ MCD_OPC_FilterValue, 36, 182, 0, 0, // Skip to: 1289 +/* 1107 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1110 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1132 +/* 1115 */ MCD_OPC_CheckPredicate, 90, 169, 0, 0, // Skip to: 1289 +/* 1120 */ MCD_OPC_CheckField, 21, 5, 0, 162, 0, 0, // Skip to: 1289 +/* 1127 */ MCD_OPC_Decode, 184, 12, 241, 2, // Opcode: DSBH +/* 1132 */ MCD_OPC_FilterValue, 5, 152, 0, 0, // Skip to: 1289 +/* 1137 */ MCD_OPC_CheckPredicate, 90, 147, 0, 0, // Skip to: 1289 +/* 1142 */ MCD_OPC_CheckField, 21, 5, 0, 140, 0, 0, // Skip to: 1289 +/* 1149 */ MCD_OPC_Decode, 186, 12, 241, 2, // Opcode: DSHD +/* 1154 */ MCD_OPC_FilterValue, 39, 10, 0, 0, // Skip to: 1169 +/* 1159 */ MCD_OPC_CheckPredicate, 91, 125, 0, 0, // Skip to: 1289 +/* 1164 */ MCD_OPC_Decode, 183, 16, 141, 1, // Opcode: LWu +/* 1169 */ MCD_OPC_FilterValue, 44, 10, 0, 0, // Skip to: 1184 +/* 1174 */ MCD_OPC_CheckPredicate, 95, 110, 0, 0, // Skip to: 1289 +/* 1179 */ MCD_OPC_Decode, 238, 20, 141, 1, // Opcode: SDL +/* 1184 */ MCD_OPC_FilterValue, 45, 10, 0, 0, // Skip to: 1199 +/* 1189 */ MCD_OPC_CheckPredicate, 95, 95, 0, 0, // Skip to: 1289 +/* 1194 */ MCD_OPC_Decode, 239, 20, 141, 1, // Opcode: SDR +/* 1199 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 1214 +/* 1204 */ MCD_OPC_CheckPredicate, 20, 80, 0, 0, // Skip to: 1289 +/* 1209 */ MCD_OPC_Decode, 231, 20, 139, 1, // Opcode: SDC1_MM_D64 +/* 1214 */ MCD_OPC_FilterValue, 47, 10, 0, 0, // Skip to: 1229 +/* 1219 */ MCD_OPC_CheckPredicate, 20, 65, 0, 0, // Skip to: 1289 +/* 1224 */ MCD_OPC_Decode, 184, 15, 139, 1, // Opcode: LDC1_MM_D64 +/* 1229 */ MCD_OPC_FilterValue, 52, 10, 0, 0, // Skip to: 1244 +/* 1234 */ MCD_OPC_CheckPredicate, 92, 50, 0, 0, // Skip to: 1289 +/* 1239 */ MCD_OPC_Decode, 238, 15, 141, 1, // Opcode: LLD +/* 1244 */ MCD_OPC_FilterValue, 55, 10, 0, 0, // Skip to: 1259 +/* 1249 */ MCD_OPC_CheckPredicate, 91, 35, 0, 0, // Skip to: 1289 +/* 1254 */ MCD_OPC_Decode, 179, 15, 141, 1, // Opcode: LD +/* 1259 */ MCD_OPC_FilterValue, 60, 10, 0, 0, // Skip to: 1274 +/* 1264 */ MCD_OPC_CheckPredicate, 95, 20, 0, 0, // Skip to: 1289 +/* 1269 */ MCD_OPC_Decode, 209, 20, 141, 1, // Opcode: SCD +/* 1274 */ MCD_OPC_FilterValue, 63, 10, 0, 0, // Skip to: 1289 +/* 1279 */ MCD_OPC_CheckPredicate, 91, 5, 0, 0, // Skip to: 1289 +/* 1284 */ MCD_OPC_Decode, 218, 20, 141, 1, // Opcode: SD +/* 1289 */ MCD_OPC_Fail, 0 }; -static bool getbool(uint64_t b) -{ - return b != 0; -} +static const uint8_t DecoderTableMipsDSP32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 18 +/* 8 */ MCD_OPC_CheckPredicate, 97, 20, 0, 0, // Skip to: 33 +/* 13 */ MCD_OPC_Decode, 142, 16, 141, 1, // Opcode: LWDSP +/* 18 */ MCD_OPC_FilterValue, 43, 10, 0, 0, // Skip to: 33 +/* 23 */ MCD_OPC_CheckPredicate, 97, 5, 0, 0, // Skip to: 33 +/* 28 */ MCD_OPC_Decode, 140, 23, 141, 1, // Opcode: SWDSP +/* 33 */ MCD_OPC_Fail, + 0 +}; -static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) -{ +static const uint8_t DecoderTableMipsFP6432[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 17, 249, 5, 0, // Skip to: 1537 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 137 +/* 16 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 19 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41 +/* 24 */ MCD_OPC_CheckPredicate, 98, 158, 6, 0, // Skip to: 1723 +/* 29 */ MCD_OPC_CheckField, 6, 5, 0, 151, 6, 0, // Skip to: 1723 +/* 36 */ MCD_OPC_Decode, 133, 17, 133, 3, // Opcode: MFC1_D64 +/* 41 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 63 +/* 46 */ MCD_OPC_CheckPredicate, 99, 136, 6, 0, // Skip to: 1723 +/* 51 */ MCD_OPC_CheckField, 6, 5, 0, 129, 6, 0, // Skip to: 1723 +/* 58 */ MCD_OPC_Decode, 145, 17, 133, 3, // Opcode: MFHC1_D64 +/* 63 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 85 +/* 68 */ MCD_OPC_CheckPredicate, 98, 114, 6, 0, // Skip to: 1723 +/* 73 */ MCD_OPC_CheckField, 6, 5, 0, 107, 6, 0, // Skip to: 1723 +/* 80 */ MCD_OPC_Decode, 161, 18, 134, 3, // Opcode: MTC1_D64 +/* 85 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 107 +/* 90 */ MCD_OPC_CheckPredicate, 99, 92, 6, 0, // Skip to: 1723 +/* 95 */ MCD_OPC_CheckField, 6, 5, 0, 85, 6, 0, // Skip to: 1723 +/* 102 */ MCD_OPC_Decode, 174, 18, 135, 3, // Opcode: MTHC1_D64 +/* 107 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 122 +/* 112 */ MCD_OPC_CheckPredicate, 98, 70, 6, 0, // Skip to: 1723 +/* 117 */ MCD_OPC_Decode, 139, 13, 230, 2, // Opcode: FADD_D64 +/* 122 */ MCD_OPC_FilterValue, 22, 60, 6, 0, // Skip to: 1723 +/* 127 */ MCD_OPC_CheckPredicate, 100, 55, 6, 0, // Skip to: 1723 +/* 132 */ MCD_OPC_Decode, 141, 13, 230, 2, // Opcode: FADD_PS64 +/* 137 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 175 +/* 142 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 145 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 160 +/* 150 */ MCD_OPC_CheckPredicate, 98, 32, 6, 0, // Skip to: 1723 +/* 155 */ MCD_OPC_Decode, 157, 14, 230, 2, // Opcode: FSUB_D64 +/* 160 */ MCD_OPC_FilterValue, 22, 22, 6, 0, // Skip to: 1723 +/* 165 */ MCD_OPC_CheckPredicate, 100, 17, 6, 0, // Skip to: 1723 +/* 170 */ MCD_OPC_Decode, 159, 14, 230, 2, // Opcode: FSUB_PS64 +/* 175 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 213 +/* 180 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 183 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 198 +/* 188 */ MCD_OPC_CheckPredicate, 98, 250, 5, 0, // Skip to: 1723 +/* 193 */ MCD_OPC_Decode, 240, 13, 230, 2, // Opcode: FMUL_D64 +/* 198 */ MCD_OPC_FilterValue, 22, 240, 5, 0, // Skip to: 1723 +/* 203 */ MCD_OPC_CheckPredicate, 100, 235, 5, 0, // Skip to: 1723 +/* 208 */ MCD_OPC_Decode, 242, 13, 230, 2, // Opcode: FMUL_PS64 +/* 213 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 235 +/* 218 */ MCD_OPC_CheckPredicate, 98, 220, 5, 0, // Skip to: 1723 +/* 223 */ MCD_OPC_CheckField, 21, 5, 17, 213, 5, 0, // Skip to: 1723 +/* 230 */ MCD_OPC_Decode, 178, 13, 230, 2, // Opcode: FDIV_D64 +/* 235 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 258 +/* 240 */ MCD_OPC_CheckPredicate, 101, 198, 5, 0, // Skip to: 1723 +/* 245 */ MCD_OPC_CheckField, 16, 10, 160, 4, 190, 5, 0, // Skip to: 1723 +/* 253 */ MCD_OPC_Decode, 149, 14, 230, 1, // Opcode: FSQRT_D64 +/* 258 */ MCD_OPC_FilterValue, 5, 18, 0, 0, // Skip to: 281 +/* 263 */ MCD_OPC_CheckPredicate, 98, 175, 5, 0, // Skip to: 1723 +/* 268 */ MCD_OPC_CheckField, 16, 10, 160, 4, 167, 5, 0, // Skip to: 1723 +/* 276 */ MCD_OPC_Decode, 132, 13, 230, 1, // Opcode: FABS_D64 +/* 281 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 304 +/* 286 */ MCD_OPC_CheckPredicate, 98, 152, 5, 0, // Skip to: 1723 +/* 291 */ MCD_OPC_CheckField, 16, 10, 160, 4, 144, 5, 0, // Skip to: 1723 +/* 299 */ MCD_OPC_Decode, 229, 13, 230, 1, // Opcode: FMOV_D64 +/* 304 */ MCD_OPC_FilterValue, 7, 18, 0, 0, // Skip to: 327 +/* 309 */ MCD_OPC_CheckPredicate, 98, 129, 5, 0, // Skip to: 1723 +/* 314 */ MCD_OPC_CheckField, 16, 10, 160, 4, 121, 5, 0, // Skip to: 1723 +/* 322 */ MCD_OPC_Decode, 249, 13, 230, 1, // Opcode: FNEG_D64 +/* 327 */ MCD_OPC_FilterValue, 8, 35, 0, 0, // Skip to: 367 +/* 332 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 335 */ MCD_OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 351 +/* 341 */ MCD_OPC_CheckPredicate, 101, 97, 5, 0, // Skip to: 1723 +/* 346 */ MCD_OPC_Decode, 164, 20, 223, 1, // Opcode: ROUND_L_S +/* 351 */ MCD_OPC_FilterValue, 160, 4, 86, 5, 0, // Skip to: 1723 +/* 357 */ MCD_OPC_CheckPredicate, 102, 81, 5, 0, // Skip to: 1723 +/* 362 */ MCD_OPC_Decode, 162, 20, 230, 1, // Opcode: ROUND_L_D64 +/* 367 */ MCD_OPC_FilterValue, 9, 35, 0, 0, // Skip to: 407 +/* 372 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 375 */ MCD_OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 391 +/* 381 */ MCD_OPC_CheckPredicate, 101, 57, 5, 0, // Skip to: 1723 +/* 386 */ MCD_OPC_Decode, 136, 24, 223, 1, // Opcode: TRUNC_L_S +/* 391 */ MCD_OPC_FilterValue, 160, 4, 46, 5, 0, // Skip to: 1723 +/* 397 */ MCD_OPC_CheckPredicate, 102, 41, 5, 0, // Skip to: 1723 +/* 402 */ MCD_OPC_Decode, 134, 24, 230, 1, // Opcode: TRUNC_L_D64 +/* 407 */ MCD_OPC_FilterValue, 10, 35, 0, 0, // Skip to: 447 +/* 412 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 415 */ MCD_OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 431 +/* 421 */ MCD_OPC_CheckPredicate, 101, 17, 5, 0, // Skip to: 1723 +/* 426 */ MCD_OPC_Decode, 255, 8, 223, 1, // Opcode: CEIL_L_S +/* 431 */ MCD_OPC_FilterValue, 160, 4, 6, 5, 0, // Skip to: 1723 +/* 437 */ MCD_OPC_CheckPredicate, 102, 1, 5, 0, // Skip to: 1723 +/* 442 */ MCD_OPC_Decode, 253, 8, 230, 1, // Opcode: CEIL_L_D64 +/* 447 */ MCD_OPC_FilterValue, 11, 35, 0, 0, // Skip to: 487 +/* 452 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 455 */ MCD_OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 471 +/* 461 */ MCD_OPC_CheckPredicate, 101, 233, 4, 0, // Skip to: 1723 +/* 466 */ MCD_OPC_Decode, 208, 13, 223, 1, // Opcode: FLOOR_L_S +/* 471 */ MCD_OPC_FilterValue, 160, 4, 222, 4, 0, // Skip to: 1723 +/* 477 */ MCD_OPC_CheckPredicate, 102, 217, 4, 0, // Skip to: 1723 +/* 482 */ MCD_OPC_Decode, 206, 13, 230, 1, // Opcode: FLOOR_L_D64 +/* 487 */ MCD_OPC_FilterValue, 12, 18, 0, 0, // Skip to: 510 +/* 492 */ MCD_OPC_CheckPredicate, 101, 202, 4, 0, // Skip to: 1723 +/* 497 */ MCD_OPC_CheckField, 16, 10, 160, 4, 194, 4, 0, // Skip to: 1723 +/* 505 */ MCD_OPC_Decode, 167, 20, 136, 3, // Opcode: ROUND_W_D64 +/* 510 */ MCD_OPC_FilterValue, 13, 18, 0, 0, // Skip to: 533 +/* 515 */ MCD_OPC_CheckPredicate, 101, 179, 4, 0, // Skip to: 1723 +/* 520 */ MCD_OPC_CheckField, 16, 10, 160, 4, 171, 4, 0, // Skip to: 1723 +/* 528 */ MCD_OPC_Decode, 139, 24, 136, 3, // Opcode: TRUNC_W_D64 +/* 533 */ MCD_OPC_FilterValue, 14, 18, 0, 0, // Skip to: 556 +/* 538 */ MCD_OPC_CheckPredicate, 101, 156, 4, 0, // Skip to: 1723 +/* 543 */ MCD_OPC_CheckField, 16, 10, 160, 4, 148, 4, 0, // Skip to: 1723 +/* 551 */ MCD_OPC_Decode, 130, 9, 136, 3, // Opcode: CEIL_W_D64 +/* 556 */ MCD_OPC_FilterValue, 15, 18, 0, 0, // Skip to: 579 +/* 561 */ MCD_OPC_CheckPredicate, 101, 133, 4, 0, // Skip to: 1723 +/* 566 */ MCD_OPC_CheckField, 16, 10, 160, 4, 125, 4, 0, // Skip to: 1723 +/* 574 */ MCD_OPC_Decode, 211, 13, 136, 3, // Opcode: FLOOR_W_D64 +/* 579 */ MCD_OPC_FilterValue, 17, 47, 0, 0, // Skip to: 631 +/* 584 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 587 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 609 +/* 592 */ MCD_OPC_CheckPredicate, 103, 102, 4, 0, // Skip to: 1723 +/* 597 */ MCD_OPC_CheckField, 21, 5, 17, 95, 4, 0, // Skip to: 1723 +/* 604 */ MCD_OPC_Decode, 219, 17, 137, 3, // Opcode: MOVF_D64 +/* 609 */ MCD_OPC_FilterValue, 1, 85, 4, 0, // Skip to: 1723 +/* 614 */ MCD_OPC_CheckPredicate, 103, 80, 4, 0, // Skip to: 1723 +/* 619 */ MCD_OPC_CheckField, 21, 5, 17, 73, 4, 0, // Skip to: 1723 +/* 626 */ MCD_OPC_Decode, 240, 17, 137, 3, // Opcode: MOVT_D64 +/* 631 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 653 +/* 636 */ MCD_OPC_CheckPredicate, 103, 58, 4, 0, // Skip to: 1723 +/* 641 */ MCD_OPC_CheckField, 21, 5, 17, 51, 4, 0, // Skip to: 1723 +/* 648 */ MCD_OPC_Decode, 252, 17, 138, 3, // Opcode: MOVZ_I_D64 +/* 653 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 675 +/* 658 */ MCD_OPC_CheckPredicate, 103, 36, 4, 0, // Skip to: 1723 +/* 663 */ MCD_OPC_CheckField, 21, 5, 17, 29, 4, 0, // Skip to: 1723 +/* 670 */ MCD_OPC_Decode, 231, 17, 138, 3, // Opcode: MOVN_I_D64 +/* 675 */ MCD_OPC_FilterValue, 21, 18, 0, 0, // Skip to: 698 +/* 680 */ MCD_OPC_CheckPredicate, 104, 14, 4, 0, // Skip to: 1723 +/* 685 */ MCD_OPC_CheckField, 16, 10, 160, 4, 6, 4, 0, // Skip to: 1723 +/* 693 */ MCD_OPC_Decode, 136, 20, 230, 1, // Opcode: RECIP_D64 +/* 698 */ MCD_OPC_FilterValue, 22, 18, 0, 0, // Skip to: 721 +/* 703 */ MCD_OPC_CheckPredicate, 104, 247, 3, 0, // Skip to: 1723 +/* 708 */ MCD_OPC_CheckField, 16, 10, 160, 4, 239, 3, 0, // Skip to: 1723 +/* 716 */ MCD_OPC_Decode, 175, 20, 230, 1, // Opcode: RSQRT_D64 +/* 721 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 743 +/* 726 */ MCD_OPC_CheckPredicate, 105, 224, 3, 0, // Skip to: 1723 +/* 731 */ MCD_OPC_CheckField, 21, 5, 22, 217, 3, 0, // Skip to: 1723 +/* 738 */ MCD_OPC_Decode, 155, 6, 230, 2, // Opcode: ADDR_PS64 +/* 743 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 765 +/* 748 */ MCD_OPC_CheckPredicate, 105, 202, 3, 0, // Skip to: 1723 +/* 753 */ MCD_OPC_CheckField, 21, 5, 22, 195, 3, 0, // Skip to: 1723 +/* 760 */ MCD_OPC_Decode, 223, 18, 230, 2, // Opcode: MULR_PS64 +/* 765 */ MCD_OPC_FilterValue, 32, 51, 0, 0, // Skip to: 821 +/* 770 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 773 */ MCD_OPC_FilterValue, 160, 4, 10, 0, 0, // Skip to: 789 +/* 779 */ MCD_OPC_CheckPredicate, 98, 171, 3, 0, // Skip to: 1723 +/* 784 */ MCD_OPC_Decode, 204, 10, 136, 3, // Opcode: CVT_S_D64 +/* 789 */ MCD_OPC_FilterValue, 160, 5, 10, 0, 0, // Skip to: 805 +/* 795 */ MCD_OPC_CheckPredicate, 106, 155, 3, 0, // Skip to: 1723 +/* 800 */ MCD_OPC_Decode, 206, 10, 136, 3, // Opcode: CVT_S_L +/* 805 */ MCD_OPC_FilterValue, 192, 5, 144, 3, 0, // Skip to: 1723 +/* 811 */ MCD_OPC_CheckPredicate, 100, 139, 3, 0, // Skip to: 1723 +/* 816 */ MCD_OPC_Decode, 209, 10, 136, 3, // Opcode: CVT_S_PU64 +/* 821 */ MCD_OPC_FilterValue, 33, 51, 0, 0, // Skip to: 877 +/* 826 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 829 */ MCD_OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 845 +/* 835 */ MCD_OPC_CheckPredicate, 98, 115, 3, 0, // Skip to: 1723 +/* 840 */ MCD_OPC_Decode, 188, 10, 223, 1, // Opcode: CVT_D64_S +/* 845 */ MCD_OPC_FilterValue, 128, 5, 10, 0, 0, // Skip to: 861 +/* 851 */ MCD_OPC_CheckPredicate, 98, 99, 3, 0, // Skip to: 1723 +/* 856 */ MCD_OPC_Decode, 190, 10, 223, 1, // Opcode: CVT_D64_W +/* 861 */ MCD_OPC_FilterValue, 160, 5, 88, 3, 0, // Skip to: 1723 +/* 867 */ MCD_OPC_CheckPredicate, 106, 83, 3, 0, // Skip to: 1723 +/* 872 */ MCD_OPC_Decode, 187, 10, 230, 1, // Opcode: CVT_D64_L +/* 877 */ MCD_OPC_FilterValue, 36, 35, 0, 0, // Skip to: 917 +/* 882 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 885 */ MCD_OPC_FilterValue, 160, 4, 10, 0, 0, // Skip to: 901 +/* 891 */ MCD_OPC_CheckPredicate, 98, 59, 3, 0, // Skip to: 1723 +/* 896 */ MCD_OPC_Decode, 215, 10, 136, 3, // Opcode: CVT_W_D64 +/* 901 */ MCD_OPC_FilterValue, 192, 5, 48, 3, 0, // Skip to: 1723 +/* 907 */ MCD_OPC_CheckPredicate, 105, 43, 3, 0, // Skip to: 1723 +/* 912 */ MCD_OPC_Decode, 201, 10, 230, 1, // Opcode: CVT_PW_PS64 +/* 917 */ MCD_OPC_FilterValue, 38, 40, 0, 0, // Skip to: 962 +/* 922 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 925 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 940 +/* 930 */ MCD_OPC_CheckPredicate, 100, 20, 3, 0, // Skip to: 1723 +/* 935 */ MCD_OPC_Decode, 200, 10, 139, 3, // Opcode: CVT_PS_S64 +/* 940 */ MCD_OPC_FilterValue, 20, 10, 3, 0, // Skip to: 1723 +/* 945 */ MCD_OPC_CheckPredicate, 105, 5, 3, 0, // Skip to: 1723 +/* 950 */ MCD_OPC_CheckField, 16, 5, 0, 254, 2, 0, // Skip to: 1723 +/* 957 */ MCD_OPC_Decode, 199, 10, 230, 1, // Opcode: CVT_PS_PW64 +/* 962 */ MCD_OPC_FilterValue, 40, 18, 0, 0, // Skip to: 985 +/* 967 */ MCD_OPC_CheckPredicate, 100, 239, 2, 0, // Skip to: 1723 +/* 972 */ MCD_OPC_CheckField, 16, 10, 192, 5, 231, 2, 0, // Skip to: 1723 +/* 980 */ MCD_OPC_Decode, 208, 10, 136, 3, // Opcode: CVT_S_PL64 +/* 985 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 1007 +/* 990 */ MCD_OPC_CheckPredicate, 100, 216, 2, 0, // Skip to: 1723 +/* 995 */ MCD_OPC_CheckField, 21, 5, 22, 209, 2, 0, // Skip to: 1723 +/* 1002 */ MCD_OPC_Decode, 201, 19, 230, 2, // Opcode: PLL_PS64 +/* 1007 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 1029 +/* 1012 */ MCD_OPC_CheckPredicate, 100, 194, 2, 0, // Skip to: 1723 +/* 1017 */ MCD_OPC_CheckField, 21, 5, 22, 187, 2, 0, // Skip to: 1723 +/* 1024 */ MCD_OPC_Decode, 202, 19, 230, 2, // Opcode: PLU_PS64 +/* 1029 */ MCD_OPC_FilterValue, 46, 17, 0, 0, // Skip to: 1051 +/* 1034 */ MCD_OPC_CheckPredicate, 100, 172, 2, 0, // Skip to: 1723 +/* 1039 */ MCD_OPC_CheckField, 21, 5, 22, 165, 2, 0, // Skip to: 1723 +/* 1046 */ MCD_OPC_Decode, 249, 19, 230, 2, // Opcode: PUL_PS64 +/* 1051 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 1073 +/* 1056 */ MCD_OPC_CheckPredicate, 100, 150, 2, 0, // Skip to: 1723 +/* 1061 */ MCD_OPC_CheckField, 21, 5, 22, 143, 2, 0, // Skip to: 1723 +/* 1068 */ MCD_OPC_Decode, 250, 19, 230, 2, // Opcode: PUU_PS64 +/* 1073 */ MCD_OPC_FilterValue, 48, 24, 0, 0, // Skip to: 1102 +/* 1078 */ MCD_OPC_CheckPredicate, 107, 128, 2, 0, // Skip to: 1723 +/* 1083 */ MCD_OPC_CheckField, 21, 5, 17, 121, 2, 0, // Skip to: 1723 +/* 1090 */ MCD_OPC_CheckField, 6, 2, 0, 114, 2, 0, // Skip to: 1723 +/* 1097 */ MCD_OPC_Decode, 228, 10, 140, 3, // Opcode: C_F_D64 +/* 1102 */ MCD_OPC_FilterValue, 49, 24, 0, 0, // Skip to: 1131 +/* 1107 */ MCD_OPC_CheckPredicate, 107, 99, 2, 0, // Skip to: 1723 +/* 1112 */ MCD_OPC_CheckField, 21, 5, 17, 92, 2, 0, // Skip to: 1723 +/* 1119 */ MCD_OPC_CheckField, 6, 2, 0, 85, 2, 0, // Skip to: 1723 +/* 1126 */ MCD_OPC_Decode, 184, 11, 140, 3, // Opcode: C_UN_D64 +/* 1131 */ MCD_OPC_FilterValue, 50, 24, 0, 0, // Skip to: 1160 +/* 1136 */ MCD_OPC_CheckPredicate, 107, 70, 2, 0, // Skip to: 1723 +/* 1141 */ MCD_OPC_CheckField, 21, 5, 17, 63, 2, 0, // Skip to: 1723 +/* 1148 */ MCD_OPC_CheckField, 6, 2, 0, 56, 2, 0, // Skip to: 1723 +/* 1155 */ MCD_OPC_Decode, 222, 10, 140, 3, // Opcode: C_EQ_D64 +/* 1160 */ MCD_OPC_FilterValue, 51, 24, 0, 0, // Skip to: 1189 +/* 1165 */ MCD_OPC_CheckPredicate, 107, 41, 2, 0, // Skip to: 1723 +/* 1170 */ MCD_OPC_CheckField, 21, 5, 17, 34, 2, 0, // Skip to: 1723 +/* 1177 */ MCD_OPC_CheckField, 6, 2, 0, 27, 2, 0, // Skip to: 1723 +/* 1184 */ MCD_OPC_Decode, 166, 11, 140, 3, // Opcode: C_UEQ_D64 +/* 1189 */ MCD_OPC_FilterValue, 52, 24, 0, 0, // Skip to: 1218 +/* 1194 */ MCD_OPC_CheckPredicate, 107, 12, 2, 0, // Skip to: 1723 +/* 1199 */ MCD_OPC_CheckField, 21, 5, 17, 5, 2, 0, // Skip to: 1723 +/* 1206 */ MCD_OPC_CheckField, 6, 2, 0, 254, 1, 0, // Skip to: 1723 +/* 1213 */ MCD_OPC_Decode, 148, 11, 140, 3, // Opcode: C_OLT_D64 +/* 1218 */ MCD_OPC_FilterValue, 53, 24, 0, 0, // Skip to: 1247 +/* 1223 */ MCD_OPC_CheckPredicate, 107, 239, 1, 0, // Skip to: 1723 +/* 1228 */ MCD_OPC_CheckField, 21, 5, 17, 232, 1, 0, // Skip to: 1723 +/* 1235 */ MCD_OPC_CheckField, 6, 2, 0, 225, 1, 0, // Skip to: 1723 +/* 1242 */ MCD_OPC_Decode, 178, 11, 140, 3, // Opcode: C_ULT_D64 +/* 1247 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1276 +/* 1252 */ MCD_OPC_CheckPredicate, 107, 210, 1, 0, // Skip to: 1723 +/* 1257 */ MCD_OPC_CheckField, 21, 5, 17, 203, 1, 0, // Skip to: 1723 +/* 1264 */ MCD_OPC_CheckField, 6, 2, 0, 196, 1, 0, // Skip to: 1723 +/* 1271 */ MCD_OPC_Decode, 142, 11, 140, 3, // Opcode: C_OLE_D64 +/* 1276 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 1305 +/* 1281 */ MCD_OPC_CheckPredicate, 107, 181, 1, 0, // Skip to: 1723 +/* 1286 */ MCD_OPC_CheckField, 21, 5, 17, 174, 1, 0, // Skip to: 1723 +/* 1293 */ MCD_OPC_CheckField, 6, 2, 0, 167, 1, 0, // Skip to: 1723 +/* 1300 */ MCD_OPC_Decode, 172, 11, 140, 3, // Opcode: C_ULE_D64 +/* 1305 */ MCD_OPC_FilterValue, 56, 24, 0, 0, // Skip to: 1334 +/* 1310 */ MCD_OPC_CheckPredicate, 107, 152, 1, 0, // Skip to: 1723 +/* 1315 */ MCD_OPC_CheckField, 21, 5, 17, 145, 1, 0, // Skip to: 1723 +/* 1322 */ MCD_OPC_CheckField, 6, 2, 0, 138, 1, 0, // Skip to: 1723 +/* 1329 */ MCD_OPC_Decode, 160, 11, 140, 3, // Opcode: C_SF_D64 +/* 1334 */ MCD_OPC_FilterValue, 57, 24, 0, 0, // Skip to: 1363 +/* 1339 */ MCD_OPC_CheckPredicate, 107, 123, 1, 0, // Skip to: 1723 +/* 1344 */ MCD_OPC_CheckField, 21, 5, 17, 116, 1, 0, // Skip to: 1723 +/* 1351 */ MCD_OPC_CheckField, 6, 2, 0, 109, 1, 0, // Skip to: 1723 +/* 1358 */ MCD_OPC_Decode, 252, 10, 140, 3, // Opcode: C_NGLE_D64 +/* 1363 */ MCD_OPC_FilterValue, 58, 24, 0, 0, // Skip to: 1392 +/* 1368 */ MCD_OPC_CheckPredicate, 107, 94, 1, 0, // Skip to: 1723 +/* 1373 */ MCD_OPC_CheckField, 21, 5, 17, 87, 1, 0, // Skip to: 1723 +/* 1380 */ MCD_OPC_CheckField, 6, 2, 0, 80, 1, 0, // Skip to: 1723 +/* 1387 */ MCD_OPC_Decode, 154, 11, 140, 3, // Opcode: C_SEQ_D64 +/* 1392 */ MCD_OPC_FilterValue, 59, 24, 0, 0, // Skip to: 1421 +/* 1397 */ MCD_OPC_CheckPredicate, 107, 65, 1, 0, // Skip to: 1723 +/* 1402 */ MCD_OPC_CheckField, 21, 5, 17, 58, 1, 0, // Skip to: 1723 +/* 1409 */ MCD_OPC_CheckField, 6, 2, 0, 51, 1, 0, // Skip to: 1723 +/* 1416 */ MCD_OPC_Decode, 130, 11, 140, 3, // Opcode: C_NGL_D64 +/* 1421 */ MCD_OPC_FilterValue, 60, 24, 0, 0, // Skip to: 1450 +/* 1426 */ MCD_OPC_CheckPredicate, 107, 36, 1, 0, // Skip to: 1723 +/* 1431 */ MCD_OPC_CheckField, 21, 5, 17, 29, 1, 0, // Skip to: 1723 +/* 1438 */ MCD_OPC_CheckField, 6, 2, 0, 22, 1, 0, // Skip to: 1723 +/* 1445 */ MCD_OPC_Decode, 240, 10, 140, 3, // Opcode: C_LT_D64 +/* 1450 */ MCD_OPC_FilterValue, 61, 24, 0, 0, // Skip to: 1479 +/* 1455 */ MCD_OPC_CheckPredicate, 107, 7, 1, 0, // Skip to: 1723 +/* 1460 */ MCD_OPC_CheckField, 21, 5, 17, 0, 1, 0, // Skip to: 1723 +/* 1467 */ MCD_OPC_CheckField, 6, 2, 0, 249, 0, 0, // Skip to: 1723 +/* 1474 */ MCD_OPC_Decode, 246, 10, 140, 3, // Opcode: C_NGE_D64 +/* 1479 */ MCD_OPC_FilterValue, 62, 24, 0, 0, // Skip to: 1508 +/* 1484 */ MCD_OPC_CheckPredicate, 107, 234, 0, 0, // Skip to: 1723 +/* 1489 */ MCD_OPC_CheckField, 21, 5, 17, 227, 0, 0, // Skip to: 1723 +/* 1496 */ MCD_OPC_CheckField, 6, 2, 0, 220, 0, 0, // Skip to: 1723 +/* 1503 */ MCD_OPC_Decode, 234, 10, 140, 3, // Opcode: C_LE_D64 +/* 1508 */ MCD_OPC_FilterValue, 63, 210, 0, 0, // Skip to: 1723 +/* 1513 */ MCD_OPC_CheckPredicate, 107, 205, 0, 0, // Skip to: 1723 +/* 1518 */ MCD_OPC_CheckField, 21, 5, 17, 198, 0, 0, // Skip to: 1723 +/* 1525 */ MCD_OPC_CheckField, 6, 2, 0, 191, 0, 0, // Skip to: 1723 +/* 1532 */ MCD_OPC_Decode, 136, 11, 140, 3, // Opcode: C_NGT_D64 +/* 1537 */ MCD_OPC_FilterValue, 19, 151, 0, 0, // Skip to: 1693 +/* 1542 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1545 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1567 +/* 1550 */ MCD_OPC_CheckPredicate, 108, 168, 0, 0, // Skip to: 1723 +/* 1555 */ MCD_OPC_CheckField, 11, 5, 0, 161, 0, 0, // Skip to: 1723 +/* 1562 */ MCD_OPC_Decode, 197, 15, 141, 3, // Opcode: LDXC164 +/* 1567 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1589 +/* 1572 */ MCD_OPC_CheckPredicate, 109, 146, 0, 0, // Skip to: 1723 +/* 1577 */ MCD_OPC_CheckField, 11, 5, 0, 139, 0, 0, // Skip to: 1723 +/* 1584 */ MCD_OPC_Decode, 254, 15, 141, 3, // Opcode: LUXC164 +/* 1589 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 1611 +/* 1594 */ MCD_OPC_CheckPredicate, 108, 124, 0, 0, // Skip to: 1723 +/* 1599 */ MCD_OPC_CheckField, 6, 5, 0, 117, 0, 0, // Skip to: 1723 +/* 1606 */ MCD_OPC_Decode, 241, 20, 142, 3, // Opcode: SDXC164 +/* 1611 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 1633 +/* 1616 */ MCD_OPC_CheckPredicate, 109, 102, 0, 0, // Skip to: 1723 +/* 1621 */ MCD_OPC_CheckField, 6, 5, 0, 95, 0, 0, // Skip to: 1723 +/* 1628 */ MCD_OPC_Decode, 254, 22, 142, 3, // Opcode: SUXC164 +/* 1633 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 1648 +/* 1638 */ MCD_OPC_CheckPredicate, 110, 80, 0, 0, // Skip to: 1723 +/* 1643 */ MCD_OPC_Decode, 212, 16, 143, 3, // Opcode: MADD_D64 +/* 1648 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 1663 +/* 1653 */ MCD_OPC_CheckPredicate, 110, 65, 0, 0, // Skip to: 1723 +/* 1658 */ MCD_OPC_Decode, 148, 18, 143, 3, // Opcode: MSUB_D64 +/* 1663 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 1678 +/* 1668 */ MCD_OPC_CheckPredicate, 111, 50, 0, 0, // Skip to: 1723 +/* 1673 */ MCD_OPC_Decode, 141, 19, 143, 3, // Opcode: NMADD_D64 +/* 1678 */ MCD_OPC_FilterValue, 57, 40, 0, 0, // Skip to: 1723 +/* 1683 */ MCD_OPC_CheckPredicate, 111, 35, 0, 0, // Skip to: 1723 +/* 1688 */ MCD_OPC_Decode, 146, 19, 143, 3, // Opcode: NMSUB_D64 +/* 1693 */ MCD_OPC_FilterValue, 53, 10, 0, 0, // Skip to: 1708 +/* 1698 */ MCD_OPC_CheckPredicate, 101, 20, 0, 0, // Skip to: 1723 +/* 1703 */ MCD_OPC_Decode, 181, 15, 219, 2, // Opcode: LDC164 +/* 1708 */ MCD_OPC_FilterValue, 61, 10, 0, 0, // Skip to: 1723 +/* 1713 */ MCD_OPC_CheckPredicate, 101, 5, 0, 0, // Skip to: 1723 +/* 1718 */ MCD_OPC_Decode, 228, 20, 219, 2, // Opcode: SDC164 +/* 1723 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNanoMips16[] = { +/* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 3 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 68 +/* 8 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 25 +/* 13 */ MCD_OPC_CheckField, 2, 8, 2, 5, 0, 0, // Skip to: 25 +/* 20 */ MCD_OPC_Decode, 183, 23, 144, 3, // Opcode: SYSCALL16_NM +/* 25 */ MCD_OPC_ExtractField, 3, 7, // Inst{9-3} ... +/* 28 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 43 +/* 33 */ MCD_OPC_CheckPredicate, 112, 20, 0, 0, // Skip to: 58 +/* 38 */ MCD_OPC_Decode, 214, 8, 145, 3, // Opcode: BREAK16_NM +/* 43 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 58 +/* 48 */ MCD_OPC_CheckPredicate, 112, 5, 0, 0, // Skip to: 58 +/* 53 */ MCD_OPC_Decode, 222, 20, 145, 3, // Opcode: SDBBP16_NM +/* 58 */ MCD_OPC_CheckPredicate, 112, 243, 2, 0, // Skip to: 818 +/* 63 */ MCD_OPC_Decode, 215, 17, 146, 3, // Opcode: MOVE_NM +/* 68 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 83 +/* 73 */ MCD_OPC_CheckPredicate, 112, 228, 2, 0, // Skip to: 818 +/* 78 */ MCD_OPC_Decode, 133, 16, 147, 3, // Opcode: LW16_NM +/* 83 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 98 +/* 88 */ MCD_OPC_CheckPredicate, 112, 213, 2, 0, // Skip to: 818 +/* 93 */ MCD_OPC_Decode, 163, 7, 148, 3, // Opcode: BC16_NM +/* 98 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 136 +/* 103 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 106 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 121 +/* 111 */ MCD_OPC_CheckPredicate, 112, 190, 2, 0, // Skip to: 818 +/* 116 */ MCD_OPC_Decode, 191, 20, 149, 3, // Opcode: SAVE16_NM +/* 121 */ MCD_OPC_FilterValue, 1, 180, 2, 0, // Skip to: 818 +/* 126 */ MCD_OPC_CheckPredicate, 112, 175, 2, 0, // Skip to: 818 +/* 131 */ MCD_OPC_Decode, 148, 20, 149, 3, // Opcode: RESTOREJRC16_NM +/* 136 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 174 +/* 141 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 144 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 159 +/* 149 */ MCD_OPC_CheckPredicate, 112, 152, 2, 0, // Skip to: 818 +/* 154 */ MCD_OPC_Decode, 222, 21, 150, 3, // Opcode: SLL16_NM +/* 159 */ MCD_OPC_FilterValue, 1, 142, 2, 0, // Skip to: 818 +/* 164 */ MCD_OPC_CheckPredicate, 112, 137, 2, 0, // Skip to: 818 +/* 169 */ MCD_OPC_Decode, 163, 22, 150, 3, // Opcode: SRL16_NM +/* 174 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 189 +/* 179 */ MCD_OPC_CheckPredicate, 112, 122, 2, 0, // Skip to: 818 +/* 184 */ MCD_OPC_Decode, 167, 16, 151, 3, // Opcode: LWSP16_NM +/* 189 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 204 +/* 194 */ MCD_OPC_CheckPredicate, 112, 107, 2, 0, // Skip to: 818 +/* 199 */ MCD_OPC_Decode, 149, 7, 148, 3, // Opcode: BALC16_NM +/* 204 */ MCD_OPC_FilterValue, 15, 47, 0, 0, // Skip to: 256 +/* 209 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 212 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 234 +/* 217 */ MCD_OPC_CheckPredicate, 112, 84, 2, 0, // Skip to: 818 +/* 222 */ MCD_OPC_CheckField, 8, 1, 0, 77, 2, 0, // Skip to: 818 +/* 229 */ MCD_OPC_Decode, 208, 6, 152, 3, // Opcode: ADDu4x4_NM +/* 234 */ MCD_OPC_FilterValue, 1, 67, 2, 0, // Skip to: 818 +/* 239 */ MCD_OPC_CheckPredicate, 112, 62, 2, 0, // Skip to: 818 +/* 244 */ MCD_OPC_CheckField, 8, 1, 0, 55, 2, 0, // Skip to: 818 +/* 251 */ MCD_OPC_Decode, 206, 18, 152, 3, // Opcode: MUL4x4_NM +/* 256 */ MCD_OPC_FilterValue, 20, 86, 0, 0, // Skip to: 347 +/* 261 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 264 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 332 +/* 269 */ MCD_OPC_ExtractField, 1, 3, // Inst{3-1} ... +/* 272 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 287 +/* 277 */ MCD_OPC_CheckPredicate, 112, 24, 2, 0, // Skip to: 818 +/* 282 */ MCD_OPC_Decode, 160, 19, 153, 3, // Opcode: NOT16_NM +/* 287 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 302 +/* 292 */ MCD_OPC_CheckPredicate, 112, 9, 2, 0, // Skip to: 818 +/* 297 */ MCD_OPC_Decode, 175, 24, 154, 3, // Opcode: XOR16_NM +/* 302 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 317 +/* 307 */ MCD_OPC_CheckPredicate, 112, 250, 1, 0, // Skip to: 818 +/* 312 */ MCD_OPC_Decode, 219, 6, 154, 3, // Opcode: AND16_NM +/* 317 */ MCD_OPC_FilterValue, 6, 240, 1, 0, // Skip to: 818 +/* 322 */ MCD_OPC_CheckPredicate, 112, 235, 1, 0, // Skip to: 818 +/* 327 */ MCD_OPC_Decode, 166, 19, 154, 3, // Opcode: OR16_NM +/* 332 */ MCD_OPC_FilterValue, 1, 225, 1, 0, // Skip to: 818 +/* 337 */ MCD_OPC_CheckPredicate, 112, 220, 1, 0, // Skip to: 818 +/* 342 */ MCD_OPC_Decode, 174, 16, 155, 3, // Opcode: LWXS16_NM +/* 347 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 362 +/* 352 */ MCD_OPC_CheckPredicate, 112, 205, 1, 0, // Skip to: 818 +/* 357 */ MCD_OPC_Decode, 146, 16, 156, 3, // Opcode: LWGP16_NM +/* 362 */ MCD_OPC_FilterValue, 23, 48, 0, 0, // Skip to: 415 +/* 367 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 370 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 385 +/* 375 */ MCD_OPC_CheckPredicate, 112, 182, 1, 0, // Skip to: 818 +/* 380 */ MCD_OPC_Decode, 155, 15, 157, 3, // Opcode: LB16_NM +/* 385 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 400 +/* 390 */ MCD_OPC_CheckPredicate, 112, 167, 1, 0, // Skip to: 818 +/* 395 */ MCD_OPC_Decode, 196, 20, 158, 3, // Opcode: SB16_NM +/* 400 */ MCD_OPC_FilterValue, 2, 157, 1, 0, // Skip to: 818 +/* 405 */ MCD_OPC_CheckPredicate, 112, 152, 1, 0, // Skip to: 818 +/* 410 */ MCD_OPC_Decode, 161, 15, 157, 3, // Opcode: LBU16_NM +/* 415 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 437 +/* 420 */ MCD_OPC_CheckPredicate, 112, 137, 1, 0, // Skip to: 818 +/* 425 */ MCD_OPC_CheckField, 6, 1, 1, 130, 1, 0, // Skip to: 818 +/* 432 */ MCD_OPC_Decode, 133, 6, 159, 3, // Opcode: ADDIUR1SP_NM +/* 437 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 452 +/* 442 */ MCD_OPC_CheckPredicate, 112, 115, 1, 0, // Skip to: 818 +/* 447 */ MCD_OPC_Decode, 134, 16, 160, 3, // Opcode: LW4x4_NM +/* 452 */ MCD_OPC_FilterValue, 31, 63, 0, 0, // Skip to: 520 +/* 457 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 460 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 498 +/* 465 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 468 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 483 +/* 473 */ MCD_OPC_CheckPredicate, 112, 84, 1, 0, // Skip to: 818 +/* 478 */ MCD_OPC_Decode, 207, 15, 161, 3, // Opcode: LH16_NM +/* 483 */ MCD_OPC_FilterValue, 1, 74, 1, 0, // Skip to: 818 +/* 488 */ MCD_OPC_CheckPredicate, 112, 69, 1, 0, // Skip to: 818 +/* 493 */ MCD_OPC_Decode, 213, 15, 161, 3, // Opcode: LHU16_NM +/* 498 */ MCD_OPC_FilterValue, 1, 59, 1, 0, // Skip to: 818 +/* 503 */ MCD_OPC_CheckPredicate, 112, 54, 1, 0, // Skip to: 818 +/* 508 */ MCD_OPC_CheckField, 3, 1, 0, 47, 1, 0, // Skip to: 818 +/* 515 */ MCD_OPC_Decode, 146, 21, 162, 3, // Opcode: SH16_NM +/* 520 */ MCD_OPC_FilterValue, 36, 56, 0, 0, // Skip to: 581 +/* 525 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 528 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 543 +/* 533 */ MCD_OPC_CheckPredicate, 112, 24, 1, 0, // Skip to: 818 +/* 538 */ MCD_OPC_Decode, 135, 6, 163, 3, // Opcode: ADDIUR2_NM +/* 543 */ MCD_OPC_FilterValue, 1, 14, 1, 0, // Skip to: 818 +/* 548 */ MCD_OPC_CheckPredicate, 112, 18, 0, 0, // Skip to: 571 +/* 553 */ MCD_OPC_CheckField, 4, 6, 0, 11, 0, 0, // Skip to: 571 +/* 560 */ MCD_OPC_CheckField, 0, 3, 0, 4, 0, 0, // Skip to: 571 +/* 567 */ MCD_OPC_Decode, 150, 19, 10, // Opcode: NOP_NM +/* 571 */ MCD_OPC_CheckPredicate, 112, 242, 0, 0, // Skip to: 818 +/* 576 */ MCD_OPC_Decode, 136, 6, 164, 3, // Opcode: ADDIURS5_NM +/* 581 */ MCD_OPC_FilterValue, 37, 10, 0, 0, // Skip to: 596 +/* 586 */ MCD_OPC_CheckPredicate, 112, 227, 0, 0, // Skip to: 818 +/* 591 */ MCD_OPC_Decode, 131, 23, 165, 3, // Opcode: SW16_NM +/* 596 */ MCD_OPC_FilterValue, 38, 10, 0, 0, // Skip to: 611 +/* 601 */ MCD_OPC_CheckPredicate, 112, 212, 0, 0, // Skip to: 818 +/* 606 */ MCD_OPC_Decode, 203, 7, 166, 3, // Opcode: BEQZC16_NM +/* 611 */ MCD_OPC_FilterValue, 44, 33, 0, 0, // Skip to: 649 +/* 616 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 619 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 634 +/* 624 */ MCD_OPC_CheckPredicate, 112, 189, 0, 0, // Skip to: 818 +/* 629 */ MCD_OPC_Decode, 207, 6, 167, 3, // Opcode: ADDu16_NM +/* 634 */ MCD_OPC_FilterValue, 1, 179, 0, 0, // Skip to: 818 +/* 639 */ MCD_OPC_CheckPredicate, 112, 174, 0, 0, // Skip to: 818 +/* 644 */ MCD_OPC_Decode, 250, 22, 167, 3, // Opcode: SUBu16_NM +/* 649 */ MCD_OPC_FilterValue, 45, 10, 0, 0, // Skip to: 664 +/* 654 */ MCD_OPC_CheckPredicate, 112, 159, 0, 0, // Skip to: 818 +/* 659 */ MCD_OPC_Decode, 162, 23, 151, 3, // Opcode: SWSP16_NM +/* 664 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 679 +/* 669 */ MCD_OPC_CheckPredicate, 112, 144, 0, 0, // Skip to: 818 +/* 674 */ MCD_OPC_Decode, 193, 8, 166, 3, // Opcode: BNEZC16_NM +/* 679 */ MCD_OPC_FilterValue, 47, 10, 0, 0, // Skip to: 694 +/* 684 */ MCD_OPC_CheckPredicate, 112, 129, 0, 0, // Skip to: 818 +/* 689 */ MCD_OPC_Decode, 214, 17, 168, 3, // Opcode: MOVEP_NM +/* 694 */ MCD_OPC_FilterValue, 52, 10, 0, 0, // Skip to: 709 +/* 699 */ MCD_OPC_CheckPredicate, 112, 114, 0, 0, // Skip to: 818 +/* 704 */ MCD_OPC_Decode, 233, 15, 169, 3, // Opcode: LI16_NM +/* 709 */ MCD_OPC_FilterValue, 53, 10, 0, 0, // Skip to: 724 +/* 714 */ MCD_OPC_CheckPredicate, 112, 99, 0, 0, // Skip to: 818 +/* 719 */ MCD_OPC_Decode, 144, 23, 170, 3, // Opcode: SWGP16_NM +/* 724 */ MCD_OPC_FilterValue, 54, 44, 0, 0, // Skip to: 773 +/* 729 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 746 +/* 734 */ MCD_OPC_CheckField, 0, 5, 0, 5, 0, 0, // Skip to: 746 +/* 741 */ MCD_OPC_Decode, 139, 15, 171, 3, // Opcode: JRC_NM +/* 746 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 763 +/* 751 */ MCD_OPC_CheckField, 0, 4, 0, 5, 0, 0, // Skip to: 763 +/* 758 */ MCD_OPC_Decode, 240, 14, 172, 3, // Opcode: JALRC16_NM +/* 763 */ MCD_OPC_CheckPredicate, 112, 50, 0, 0, // Skip to: 818 +/* 768 */ MCD_OPC_Decode, 191, 7, 173, 3, // Opcode: BEQC16_NM +/* 773 */ MCD_OPC_FilterValue, 60, 10, 0, 0, // Skip to: 788 +/* 778 */ MCD_OPC_CheckPredicate, 112, 35, 0, 0, // Skip to: 818 +/* 783 */ MCD_OPC_Decode, 223, 6, 174, 3, // Opcode: ANDI16_NM +/* 788 */ MCD_OPC_FilterValue, 61, 10, 0, 0, // Skip to: 803 +/* 793 */ MCD_OPC_CheckPredicate, 112, 20, 0, 0, // Skip to: 818 +/* 798 */ MCD_OPC_Decode, 132, 23, 175, 3, // Opcode: SW4x4_NM +/* 803 */ MCD_OPC_FilterValue, 63, 10, 0, 0, // Skip to: 818 +/* 808 */ MCD_OPC_CheckPredicate, 112, 5, 0, 0, // Skip to: 818 +/* 813 */ MCD_OPC_Decode, 211, 17, 176, 3, // Opcode: MOVEPREV_NM +/* 818 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNanoMips32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 83 +/* 8 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 25 +/* 13 */ MCD_OPC_CheckField, 18, 8, 2, 5, 0, 0, // Skip to: 25 +/* 20 */ MCD_OPC_Decode, 185, 23, 177, 3, // Opcode: SYSCALL_NM +/* 25 */ MCD_OPC_ExtractField, 19, 7, // Inst{25-19} ... +/* 28 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43 +/* 33 */ MCD_OPC_CheckPredicate, 112, 35, 0, 0, // Skip to: 73 +/* 38 */ MCD_OPC_Decode, 210, 21, 178, 3, // Opcode: SIGRIE_NM +/* 43 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 58 +/* 48 */ MCD_OPC_CheckPredicate, 112, 20, 0, 0, // Skip to: 73 +/* 53 */ MCD_OPC_Decode, 217, 8, 178, 3, // Opcode: BREAK_NM +/* 58 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 73 +/* 63 */ MCD_OPC_CheckPredicate, 112, 5, 0, 0, // Skip to: 73 +/* 68 */ MCD_OPC_Decode, 225, 20, 178, 3, // Opcode: SDBBP_NM +/* 73 */ MCD_OPC_CheckPredicate, 112, 165, 12, 0, // Skip to: 3315 +/* 78 */ MCD_OPC_Decode, 140, 6, 179, 3, // Opcode: ADDIU_NM +/* 83 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 98 +/* 88 */ MCD_OPC_CheckPredicate, 112, 150, 12, 0, // Skip to: 3315 +/* 93 */ MCD_OPC_Decode, 152, 15, 180, 3, // Opcode: LAPC32_NM +/* 98 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 113 +/* 103 */ MCD_OPC_CheckPredicate, 112, 135, 12, 0, // Skip to: 3315 +/* 108 */ MCD_OPC_Decode, 210, 17, 181, 3, // Opcode: MOVEBALC_NM +/* 113 */ MCD_OPC_FilterValue, 8, 55, 6, 0, // Skip to: 1709 +/* 118 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 121 */ MCD_OPC_FilterValue, 0, 64, 1, 0, // Skip to: 446 +/* 126 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 129 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 190 +/* 134 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 137 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 175 +/* 142 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 145 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 160 +/* 150 */ MCD_OPC_CheckPredicate, 112, 88, 12, 0, // Skip to: 3315 +/* 155 */ MCD_OPC_Decode, 211, 23, 182, 3, // Opcode: TEQ_NM +/* 160 */ MCD_OPC_FilterValue, 1, 78, 12, 0, // Skip to: 3315 +/* 165 */ MCD_OPC_CheckPredicate, 112, 73, 12, 0, // Skip to: 3315 +/* 170 */ MCD_OPC_Decode, 133, 24, 182, 3, // Opcode: TNE_NM +/* 175 */ MCD_OPC_FilterValue, 7, 63, 12, 0, // Skip to: 3315 +/* 180 */ MCD_OPC_CheckPredicate, 112, 58, 12, 0, // Skip to: 3315 +/* 185 */ MCD_OPC_Decode, 131, 20, 183, 3, // Opcode: RDHWR_NM +/* 190 */ MCD_OPC_FilterValue, 7, 198, 0, 0, // Skip to: 393 +/* 195 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 198 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 213 +/* 203 */ MCD_OPC_CheckPredicate, 112, 35, 12, 0, // Skip to: 3315 +/* 208 */ MCD_OPC_Decode, 169, 15, 184, 3, // Opcode: LBX_NM +/* 213 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 228 +/* 218 */ MCD_OPC_CheckPredicate, 112, 20, 12, 0, // Skip to: 3315 +/* 223 */ MCD_OPC_Decode, 201, 20, 184, 3, // Opcode: SBX_NM +/* 228 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 243 +/* 233 */ MCD_OPC_CheckPredicate, 112, 5, 12, 0, // Skip to: 3315 +/* 238 */ MCD_OPC_Decode, 165, 15, 184, 3, // Opcode: LBUX_NM +/* 243 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 258 +/* 248 */ MCD_OPC_CheckPredicate, 112, 246, 11, 0, // Skip to: 3315 +/* 253 */ MCD_OPC_Decode, 222, 15, 184, 3, // Opcode: LHX_NM +/* 258 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 273 +/* 263 */ MCD_OPC_CheckPredicate, 112, 231, 11, 0, // Skip to: 3315 +/* 268 */ MCD_OPC_Decode, 220, 15, 184, 3, // Opcode: LHXS_NM +/* 273 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 288 +/* 278 */ MCD_OPC_CheckPredicate, 112, 216, 11, 0, // Skip to: 3315 +/* 283 */ MCD_OPC_Decode, 203, 21, 184, 3, // Opcode: SHX_NM +/* 288 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 303 +/* 293 */ MCD_OPC_CheckPredicate, 112, 201, 11, 0, // Skip to: 3315 +/* 298 */ MCD_OPC_Decode, 202, 21, 184, 3, // Opcode: SHXS_NM +/* 303 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 318 +/* 308 */ MCD_OPC_CheckPredicate, 112, 186, 11, 0, // Skip to: 3315 +/* 313 */ MCD_OPC_Decode, 216, 15, 184, 3, // Opcode: LHUX_NM +/* 318 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 333 +/* 323 */ MCD_OPC_CheckPredicate, 112, 171, 11, 0, // Skip to: 3315 +/* 328 */ MCD_OPC_Decode, 215, 15, 184, 3, // Opcode: LHUXS_NM +/* 333 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 348 +/* 338 */ MCD_OPC_CheckPredicate, 112, 156, 11, 0, // Skip to: 3315 +/* 343 */ MCD_OPC_Decode, 178, 16, 184, 3, // Opcode: LWX_NM +/* 348 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 363 +/* 353 */ MCD_OPC_CheckPredicate, 112, 141, 11, 0, // Skip to: 3315 +/* 358 */ MCD_OPC_Decode, 176, 16, 184, 3, // Opcode: LWXS_NM +/* 363 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 378 +/* 368 */ MCD_OPC_CheckPredicate, 112, 126, 11, 0, // Skip to: 3315 +/* 373 */ MCD_OPC_Decode, 168, 23, 184, 3, // Opcode: SWX_NM +/* 378 */ MCD_OPC_FilterValue, 19, 116, 11, 0, // Skip to: 3315 +/* 383 */ MCD_OPC_CheckPredicate, 112, 111, 11, 0, // Skip to: 3315 +/* 388 */ MCD_OPC_Decode, 167, 23, 184, 3, // Opcode: SWXS_NM +/* 393 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 431 +/* 398 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 401 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 416 +/* 406 */ MCD_OPC_CheckPredicate, 112, 88, 11, 0, // Skip to: 3315 +/* 411 */ MCD_OPC_Decode, 245, 20, 185, 3, // Opcode: SEB_NM +/* 416 */ MCD_OPC_FilterValue, 1, 78, 11, 0, // Skip to: 3315 +/* 421 */ MCD_OPC_CheckPredicate, 112, 73, 11, 0, // Skip to: 3315 +/* 426 */ MCD_OPC_Decode, 249, 20, 185, 3, // Opcode: SEH_NM +/* 431 */ MCD_OPC_FilterValue, 15, 63, 11, 0, // Skip to: 3315 +/* 436 */ MCD_OPC_CheckPredicate, 112, 58, 11, 0, // Skip to: 3315 +/* 441 */ MCD_OPC_Decode, 249, 15, 186, 3, // Opcode: LSA_NM +/* 446 */ MCD_OPC_FilterValue, 1, 161, 1, 0, // Skip to: 868 +/* 451 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 454 */ MCD_OPC_FilterValue, 0, 10, 1, 0, // Skip to: 725 +/* 459 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 462 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 477 +/* 467 */ MCD_OPC_CheckPredicate, 112, 27, 11, 0, // Skip to: 3315 +/* 472 */ MCD_OPC_Decode, 231, 21, 187, 3, // Opcode: SLLV_NM +/* 477 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 492 +/* 482 */ MCD_OPC_CheckPredicate, 112, 12, 11, 0, // Skip to: 3315 +/* 487 */ MCD_OPC_Decode, 178, 22, 187, 3, // Opcode: SRLV_NM +/* 492 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 507 +/* 497 */ MCD_OPC_CheckPredicate, 112, 253, 10, 0, // Skip to: 3315 +/* 502 */ MCD_OPC_Decode, 153, 22, 187, 3, // Opcode: SRAV_NM +/* 507 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 522 +/* 512 */ MCD_OPC_CheckPredicate, 112, 238, 10, 0, // Skip to: 3315 +/* 517 */ MCD_OPC_Decode, 158, 20, 187, 3, // Opcode: ROTRV_NM +/* 522 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 537 +/* 527 */ MCD_OPC_CheckPredicate, 112, 223, 10, 0, // Skip to: 3315 +/* 532 */ MCD_OPC_Decode, 201, 6, 187, 3, // Opcode: ADD_NM +/* 537 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 552 +/* 542 */ MCD_OPC_CheckPredicate, 112, 208, 10, 0, // Skip to: 3315 +/* 547 */ MCD_OPC_Decode, 210, 6, 187, 3, // Opcode: ADDu_NM +/* 552 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 567 +/* 557 */ MCD_OPC_CheckPredicate, 112, 193, 10, 0, // Skip to: 3315 +/* 562 */ MCD_OPC_Decode, 248, 22, 187, 3, // Opcode: SUB_NM +/* 567 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 582 +/* 572 */ MCD_OPC_CheckPredicate, 112, 178, 10, 0, // Skip to: 3315 +/* 577 */ MCD_OPC_Decode, 252, 22, 187, 3, // Opcode: SUBu_NM +/* 582 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 620 +/* 587 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 590 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 605 +/* 595 */ MCD_OPC_CheckPredicate, 112, 155, 10, 0, // Skip to: 3315 +/* 600 */ MCD_OPC_Decode, 130, 18, 188, 3, // Opcode: MOVZ_NM +/* 605 */ MCD_OPC_FilterValue, 1, 145, 10, 0, // Skip to: 3315 +/* 610 */ MCD_OPC_CheckPredicate, 112, 140, 10, 0, // Skip to: 3315 +/* 615 */ MCD_OPC_Decode, 237, 17, 188, 3, // Opcode: MOVN_NM +/* 620 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 635 +/* 625 */ MCD_OPC_CheckPredicate, 112, 125, 10, 0, // Skip to: 3315 +/* 630 */ MCD_OPC_Decode, 229, 6, 187, 3, // Opcode: AND_NM +/* 635 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 650 +/* 640 */ MCD_OPC_CheckPredicate, 112, 110, 10, 0, // Skip to: 3315 +/* 645 */ MCD_OPC_Decode, 173, 19, 187, 3, // Opcode: OR_NM +/* 650 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 665 +/* 655 */ MCD_OPC_CheckPredicate, 112, 95, 10, 0, // Skip to: 3315 +/* 660 */ MCD_OPC_Decode, 156, 19, 187, 3, // Opcode: NOR_NM +/* 665 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 680 +/* 670 */ MCD_OPC_CheckPredicate, 112, 80, 10, 0, // Skip to: 3315 +/* 675 */ MCD_OPC_Decode, 182, 24, 187, 3, // Opcode: XOR_NM +/* 680 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 695 +/* 685 */ MCD_OPC_CheckPredicate, 112, 65, 10, 0, // Skip to: 3315 +/* 690 */ MCD_OPC_Decode, 245, 21, 187, 3, // Opcode: SLT_NM +/* 695 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 710 +/* 700 */ MCD_OPC_CheckPredicate, 112, 50, 10, 0, // Skip to: 3315 +/* 705 */ MCD_OPC_Decode, 243, 21, 187, 3, // Opcode: SLTU_NM +/* 710 */ MCD_OPC_FilterValue, 15, 40, 10, 0, // Skip to: 3315 +/* 715 */ MCD_OPC_CheckPredicate, 112, 35, 10, 0, // Skip to: 3315 +/* 720 */ MCD_OPC_Decode, 129, 22, 187, 3, // Opcode: SOV_NM +/* 725 */ MCD_OPC_FilterValue, 8, 123, 0, 0, // Skip to: 853 +/* 730 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 733 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 748 +/* 738 */ MCD_OPC_CheckPredicate, 112, 12, 10, 0, // Skip to: 3315 +/* 743 */ MCD_OPC_Decode, 247, 18, 187, 3, // Opcode: MUL_NM +/* 748 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 763 +/* 753 */ MCD_OPC_CheckPredicate, 112, 253, 9, 0, // Skip to: 3315 +/* 758 */ MCD_OPC_Decode, 204, 18, 187, 3, // Opcode: MUH_NM +/* 763 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 778 +/* 768 */ MCD_OPC_CheckPredicate, 112, 238, 9, 0, // Skip to: 3315 +/* 773 */ MCD_OPC_Decode, 240, 18, 187, 3, // Opcode: MULU_NM +/* 778 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 793 +/* 783 */ MCD_OPC_CheckPredicate, 112, 223, 9, 0, // Skip to: 3315 +/* 788 */ MCD_OPC_Decode, 202, 18, 187, 3, // Opcode: MUHU_NM +/* 793 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 808 +/* 798 */ MCD_OPC_CheckPredicate, 112, 208, 9, 0, // Skip to: 3315 +/* 803 */ MCD_OPC_Decode, 223, 11, 187, 3, // Opcode: DIV_NM +/* 808 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 823 +/* 813 */ MCD_OPC_CheckPredicate, 112, 193, 9, 0, // Skip to: 3315 +/* 818 */ MCD_OPC_Decode, 199, 17, 187, 3, // Opcode: MOD_NM +/* 823 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 838 +/* 828 */ MCD_OPC_CheckPredicate, 112, 178, 9, 0, // Skip to: 3315 +/* 833 */ MCD_OPC_Decode, 221, 11, 187, 3, // Opcode: DIVU_NM +/* 838 */ MCD_OPC_FilterValue, 7, 168, 9, 0, // Skip to: 3315 +/* 843 */ MCD_OPC_CheckPredicate, 112, 163, 9, 0, // Skip to: 3315 +/* 848 */ MCD_OPC_Decode, 197, 17, 187, 3, // Opcode: MODU_NM +/* 853 */ MCD_OPC_FilterValue, 15, 153, 9, 0, // Skip to: 3315 +/* 858 */ MCD_OPC_CheckPredicate, 112, 148, 9, 0, // Skip to: 3315 +/* 863 */ MCD_OPC_Decode, 254, 12, 189, 3, // Opcode: EXTW_NM +/* 868 */ MCD_OPC_FilterValue, 2, 194, 0, 0, // Skip to: 1067 +/* 873 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 876 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 898 +/* 881 */ MCD_OPC_CheckPredicate, 113, 125, 9, 0, // Skip to: 3315 +/* 886 */ MCD_OPC_CheckField, 0, 4, 8, 118, 9, 0, // Skip to: 3315 +/* 893 */ MCD_OPC_Decode, 255, 13, 190, 3, // Opcode: FORK_NM +/* 898 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 927 +/* 903 */ MCD_OPC_CheckPredicate, 113, 103, 9, 0, // Skip to: 3315 +/* 908 */ MCD_OPC_CheckField, 10, 6, 0, 96, 9, 0, // Skip to: 3315 +/* 915 */ MCD_OPC_CheckField, 0, 4, 8, 89, 9, 0, // Skip to: 3315 +/* 922 */ MCD_OPC_Decode, 189, 24, 185, 3, // Opcode: YIELD_NM +/* 927 */ MCD_OPC_FilterValue, 15, 79, 9, 0, // Skip to: 3315 +/* 932 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 935 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 957 +/* 940 */ MCD_OPC_CheckPredicate, 114, 66, 9, 0, // Skip to: 3315 +/* 945 */ MCD_OPC_CheckField, 0, 4, 8, 59, 9, 0, // Skip to: 3315 +/* 952 */ MCD_OPC_Decode, 166, 10, 191, 3, // Opcode: CRC32B_NM +/* 957 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 979 +/* 962 */ MCD_OPC_CheckPredicate, 114, 44, 9, 0, // Skip to: 3315 +/* 967 */ MCD_OPC_CheckField, 0, 4, 8, 37, 9, 0, // Skip to: 3315 +/* 974 */ MCD_OPC_Decode, 176, 10, 191, 3, // Opcode: CRC32H_NM +/* 979 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1001 +/* 984 */ MCD_OPC_CheckPredicate, 114, 22, 9, 0, // Skip to: 3315 +/* 989 */ MCD_OPC_CheckField, 0, 4, 8, 15, 9, 0, // Skip to: 3315 +/* 996 */ MCD_OPC_Decode, 178, 10, 191, 3, // Opcode: CRC32W_NM +/* 1001 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1023 +/* 1006 */ MCD_OPC_CheckPredicate, 114, 0, 9, 0, // Skip to: 3315 +/* 1011 */ MCD_OPC_CheckField, 0, 4, 8, 249, 8, 0, // Skip to: 3315 +/* 1018 */ MCD_OPC_Decode, 168, 10, 191, 3, // Opcode: CRC32CB_NM +/* 1023 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1045 +/* 1028 */ MCD_OPC_CheckPredicate, 114, 234, 8, 0, // Skip to: 3315 +/* 1033 */ MCD_OPC_CheckField, 0, 4, 8, 227, 8, 0, // Skip to: 3315 +/* 1040 */ MCD_OPC_Decode, 171, 10, 191, 3, // Opcode: CRC32CH_NM +/* 1045 */ MCD_OPC_FilterValue, 6, 217, 8, 0, // Skip to: 3315 +/* 1050 */ MCD_OPC_CheckPredicate, 114, 212, 8, 0, // Skip to: 3315 +/* 1055 */ MCD_OPC_CheckField, 0, 4, 8, 205, 8, 0, // Skip to: 3315 +/* 1062 */ MCD_OPC_Decode, 173, 10, 191, 3, // Opcode: CRC32CW_NM +/* 1067 */ MCD_OPC_FilterValue, 3, 195, 8, 0, // Skip to: 3315 +/* 1072 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 1075 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1113 +/* 1080 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1083 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1098 +/* 1088 */ MCD_OPC_CheckPredicate, 112, 174, 8, 0, // Skip to: 3315 +/* 1093 */ MCD_OPC_Decode, 129, 17, 192, 3, // Opcode: MFC0Sel_NM +/* 1098 */ MCD_OPC_FilterValue, 8, 164, 8, 0, // Skip to: 3315 +/* 1103 */ MCD_OPC_CheckPredicate, 112, 159, 8, 0, // Skip to: 3315 +/* 1108 */ MCD_OPC_Decode, 140, 17, 192, 3, // Opcode: MFHC0Sel_NM +/* 1113 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 1151 +/* 1118 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1121 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1136 +/* 1126 */ MCD_OPC_CheckPredicate, 112, 136, 8, 0, // Skip to: 3315 +/* 1131 */ MCD_OPC_Decode, 157, 18, 192, 3, // Opcode: MTC0Sel_NM +/* 1136 */ MCD_OPC_FilterValue, 8, 126, 8, 0, // Skip to: 3315 +/* 1141 */ MCD_OPC_CheckPredicate, 112, 121, 8, 0, // Skip to: 3315 +/* 1146 */ MCD_OPC_Decode, 169, 18, 192, 3, // Opcode: MTHC0Sel_NM +/* 1151 */ MCD_OPC_FilterValue, 5, 47, 0, 0, // Skip to: 1203 +/* 1156 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 1159 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 1181 +/* 1164 */ MCD_OPC_CheckPredicate, 112, 98, 8, 0, // Skip to: 3315 +/* 1169 */ MCD_OPC_CheckField, 0, 4, 15, 91, 8, 0, // Skip to: 3315 +/* 1176 */ MCD_OPC_Decode, 133, 20, 185, 3, // Opcode: RDPGPR_NM +/* 1181 */ MCD_OPC_FilterValue, 60, 81, 8, 0, // Skip to: 3315 +/* 1186 */ MCD_OPC_CheckPredicate, 112, 76, 8, 0, // Skip to: 3315 +/* 1191 */ MCD_OPC_CheckField, 0, 4, 15, 69, 8, 0, // Skip to: 3315 +/* 1198 */ MCD_OPC_Decode, 168, 24, 185, 3, // Opcode: WRPGPR_NM +/* 1203 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 1225 +/* 1208 */ MCD_OPC_CheckPredicate, 113, 54, 8, 0, // Skip to: 3315 +/* 1213 */ MCD_OPC_CheckField, 0, 3, 0, 47, 8, 0, // Skip to: 3315 +/* 1220 */ MCD_OPC_Decode, 163, 17, 193, 3, // Opcode: MFTR_NM +/* 1225 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 1247 +/* 1230 */ MCD_OPC_CheckPredicate, 113, 32, 8, 0, // Skip to: 3315 +/* 1235 */ MCD_OPC_CheckField, 0, 3, 0, 25, 8, 0, // Skip to: 3315 +/* 1242 */ MCD_OPC_Decode, 198, 18, 194, 3, // Opcode: MTTR_NM +/* 1247 */ MCD_OPC_FilterValue, 10, 91, 0, 0, // Skip to: 1343 +/* 1252 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... +/* 1255 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1277 +/* 1260 */ MCD_OPC_CheckPredicate, 113, 2, 8, 0, // Skip to: 3315 +/* 1265 */ MCD_OPC_CheckField, 0, 4, 0, 251, 7, 0, // Skip to: 3315 +/* 1272 */ MCD_OPC_Decode, 202, 12, 195, 3, // Opcode: DVPE_NM +/* 1277 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1299 +/* 1282 */ MCD_OPC_CheckPredicate, 113, 236, 7, 0, // Skip to: 3315 +/* 1287 */ MCD_OPC_CheckField, 0, 4, 0, 229, 7, 0, // Skip to: 3315 +/* 1294 */ MCD_OPC_Decode, 225, 12, 195, 3, // Opcode: EVPE_NM +/* 1299 */ MCD_OPC_FilterValue, 66, 17, 0, 0, // Skip to: 1321 +/* 1304 */ MCD_OPC_CheckPredicate, 113, 214, 7, 0, // Skip to: 3315 +/* 1309 */ MCD_OPC_CheckField, 0, 4, 0, 207, 7, 0, // Skip to: 3315 +/* 1316 */ MCD_OPC_Decode, 250, 11, 195, 3, // Opcode: DMT_NM +/* 1321 */ MCD_OPC_FilterValue, 67, 197, 7, 0, // Skip to: 3315 +/* 1326 */ MCD_OPC_CheckPredicate, 113, 192, 7, 0, // Skip to: 3315 +/* 1331 */ MCD_OPC_CheckField, 0, 4, 0, 185, 7, 0, // Skip to: 3315 +/* 1338 */ MCD_OPC_Decode, 215, 12, 195, 3, // Opcode: EMT_NM +/* 1343 */ MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 1395 +/* 1348 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 1351 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 1373 +/* 1356 */ MCD_OPC_CheckPredicate, 112, 162, 7, 0, // Skip to: 3315 +/* 1361 */ MCD_OPC_CheckField, 0, 4, 15, 155, 7, 0, // Skip to: 3315 +/* 1368 */ MCD_OPC_Decode, 175, 9, 185, 3, // Opcode: CLO_NM +/* 1373 */ MCD_OPC_FilterValue, 22, 145, 7, 0, // Skip to: 3315 +/* 1378 */ MCD_OPC_CheckPredicate, 112, 140, 7, 0, // Skip to: 3315 +/* 1383 */ MCD_OPC_CheckField, 0, 4, 15, 133, 7, 0, // Skip to: 3315 +/* 1390 */ MCD_OPC_Decode, 196, 9, 185, 3, // Opcode: CLZ_NM +/* 1395 */ MCD_OPC_FilterValue, 13, 123, 7, 0, // Skip to: 3315 +/* 1400 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 1403 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1424 +/* 1408 */ MCD_OPC_CheckPredicate, 115, 110, 7, 0, // Skip to: 3315 +/* 1413 */ MCD_OPC_CheckField, 0, 4, 15, 103, 7, 0, // Skip to: 3315 +/* 1420 */ MCD_OPC_Decode, 240, 23, 10, // Opcode: TLBP_NM +/* 1424 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 1445 +/* 1429 */ MCD_OPC_CheckPredicate, 115, 89, 7, 0, // Skip to: 3315 +/* 1434 */ MCD_OPC_CheckField, 0, 4, 15, 82, 7, 0, // Skip to: 3315 +/* 1441 */ MCD_OPC_Decode, 237, 23, 10, // Opcode: TLBINV_NM +/* 1445 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1467 +/* 1450 */ MCD_OPC_CheckPredicate, 116, 68, 7, 0, // Skip to: 3315 +/* 1455 */ MCD_OPC_CheckField, 0, 4, 15, 61, 7, 0, // Skip to: 3315 +/* 1462 */ MCD_OPC_Decode, 189, 14, 196, 3, // Opcode: GINVT_NM +/* 1467 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 1488 +/* 1472 */ MCD_OPC_CheckPredicate, 115, 46, 7, 0, // Skip to: 3315 +/* 1477 */ MCD_OPC_CheckField, 0, 4, 15, 39, 7, 0, // Skip to: 3315 +/* 1484 */ MCD_OPC_Decode, 243, 23, 10, // Opcode: TLBR_NM +/* 1488 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 1509 +/* 1493 */ MCD_OPC_CheckPredicate, 115, 25, 7, 0, // Skip to: 3315 +/* 1498 */ MCD_OPC_CheckField, 0, 4, 15, 18, 7, 0, // Skip to: 3315 +/* 1505 */ MCD_OPC_Decode, 235, 23, 10, // Opcode: TLBINVF_NM +/* 1509 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1531 +/* 1514 */ MCD_OPC_CheckPredicate, 116, 4, 7, 0, // Skip to: 3315 +/* 1519 */ MCD_OPC_CheckField, 0, 4, 15, 253, 6, 0, // Skip to: 3315 +/* 1526 */ MCD_OPC_Decode, 186, 14, 197, 3, // Opcode: GINVI_NM +/* 1531 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 1552 +/* 1536 */ MCD_OPC_CheckPredicate, 115, 238, 6, 0, // Skip to: 3315 +/* 1541 */ MCD_OPC_CheckField, 0, 4, 15, 231, 6, 0, // Skip to: 3315 +/* 1548 */ MCD_OPC_Decode, 246, 23, 10, // Opcode: TLBWI_NM +/* 1552 */ MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 1573 +/* 1557 */ MCD_OPC_CheckPredicate, 115, 217, 6, 0, // Skip to: 3315 +/* 1562 */ MCD_OPC_CheckField, 0, 4, 15, 210, 6, 0, // Skip to: 3315 +/* 1569 */ MCD_OPC_Decode, 249, 23, 10, // Opcode: TLBWR_NM +/* 1573 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 1595 +/* 1578 */ MCD_OPC_CheckPredicate, 112, 196, 6, 0, // Skip to: 3315 +/* 1583 */ MCD_OPC_CheckField, 0, 4, 15, 189, 6, 0, // Skip to: 3315 +/* 1590 */ MCD_OPC_Decode, 234, 11, 195, 3, // Opcode: DI_NM +/* 1595 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 1617 +/* 1600 */ MCD_OPC_CheckPredicate, 112, 174, 6, 0, // Skip to: 3315 +/* 1605 */ MCD_OPC_CheckField, 0, 4, 15, 167, 6, 0, // Skip to: 3315 +/* 1612 */ MCD_OPC_Decode, 213, 12, 195, 3, // Opcode: EI_NM +/* 1617 */ MCD_OPC_FilterValue, 48, 16, 0, 0, // Skip to: 1638 +/* 1622 */ MCD_OPC_CheckPredicate, 112, 152, 6, 0, // Skip to: 3315 +/* 1627 */ MCD_OPC_CheckField, 0, 4, 15, 145, 6, 0, // Skip to: 3315 +/* 1634 */ MCD_OPC_Decode, 164, 24, 88, // Opcode: WAIT_NM +/* 1638 */ MCD_OPC_FilterValue, 56, 16, 0, 0, // Skip to: 1659 +/* 1643 */ MCD_OPC_CheckPredicate, 112, 131, 6, 0, // Skip to: 3315 +/* 1648 */ MCD_OPC_CheckField, 0, 4, 15, 124, 6, 0, // Skip to: 3315 +/* 1655 */ MCD_OPC_Decode, 209, 11, 10, // Opcode: DERET_NM +/* 1659 */ MCD_OPC_FilterValue, 60, 115, 6, 0, // Skip to: 3315 +/* 1664 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1667 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1688 +/* 1672 */ MCD_OPC_CheckPredicate, 112, 102, 6, 0, // Skip to: 3315 +/* 1677 */ MCD_OPC_CheckField, 0, 4, 15, 95, 6, 0, // Skip to: 3315 +/* 1684 */ MCD_OPC_Decode, 222, 12, 10, // Opcode: ERET_NM +/* 1688 */ MCD_OPC_FilterValue, 1, 86, 6, 0, // Skip to: 3315 +/* 1693 */ MCD_OPC_CheckPredicate, 112, 81, 6, 0, // Skip to: 3315 +/* 1698 */ MCD_OPC_CheckField, 0, 4, 15, 74, 6, 0, // Skip to: 3315 +/* 1705 */ MCD_OPC_Decode, 219, 12, 10, // Opcode: ERETNC_NM +/* 1709 */ MCD_OPC_FilterValue, 10, 33, 0, 0, // Skip to: 1747 +/* 1714 */ MCD_OPC_ExtractField, 25, 1, // Inst{25} ... +/* 1717 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1732 +/* 1722 */ MCD_OPC_CheckPredicate, 112, 52, 6, 0, // Skip to: 3315 +/* 1727 */ MCD_OPC_Decode, 187, 7, 198, 3, // Opcode: BC_NM +/* 1732 */ MCD_OPC_FilterValue, 1, 42, 6, 0, // Skip to: 3315 +/* 1737 */ MCD_OPC_CheckPredicate, 112, 37, 6, 0, // Skip to: 3315 +/* 1742 */ MCD_OPC_Decode, 151, 7, 198, 3, // Opcode: BALC_NM +/* 1747 */ MCD_OPC_FilterValue, 16, 48, 0, 0, // Skip to: 1800 +/* 1752 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 1755 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1770 +/* 1760 */ MCD_OPC_CheckPredicate, 112, 14, 6, 0, // Skip to: 3315 +/* 1765 */ MCD_OPC_Decode, 255, 5, 199, 3, // Opcode: ADDIUGPW_NM +/* 1770 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1785 +/* 1775 */ MCD_OPC_CheckPredicate, 112, 255, 5, 0, // Skip to: 3315 +/* 1780 */ MCD_OPC_Decode, 148, 16, 200, 3, // Opcode: LWGP_NM +/* 1785 */ MCD_OPC_FilterValue, 3, 245, 5, 0, // Skip to: 3315 +/* 1790 */ MCD_OPC_CheckPredicate, 112, 240, 5, 0, // Skip to: 3315 +/* 1795 */ MCD_OPC_Decode, 145, 23, 200, 3, // Opcode: SWGP_NM +/* 1800 */ MCD_OPC_FilterValue, 17, 123, 0, 0, // Skip to: 1928 +/* 1805 */ MCD_OPC_ExtractField, 18, 3, // Inst{20-18} ... +/* 1808 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1823 +/* 1813 */ MCD_OPC_CheckPredicate, 112, 217, 5, 0, // Skip to: 3315 +/* 1818 */ MCD_OPC_Decode, 159, 15, 201, 3, // Opcode: LBGP_NM +/* 1823 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1838 +/* 1828 */ MCD_OPC_CheckPredicate, 112, 202, 5, 0, // Skip to: 3315 +/* 1833 */ MCD_OPC_Decode, 200, 20, 201, 3, // Opcode: SBGP_NM +/* 1838 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1853 +/* 1843 */ MCD_OPC_CheckPredicate, 112, 187, 5, 0, // Skip to: 3315 +/* 1848 */ MCD_OPC_Decode, 162, 15, 201, 3, // Opcode: LBUGP_NM +/* 1853 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1868 +/* 1858 */ MCD_OPC_CheckPredicate, 112, 172, 5, 0, // Skip to: 3315 +/* 1863 */ MCD_OPC_Decode, 254, 5, 202, 3, // Opcode: ADDIUGPB_NM +/* 1868 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 1906 +/* 1873 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1876 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1891 +/* 1881 */ MCD_OPC_CheckPredicate, 112, 149, 5, 0, // Skip to: 3315 +/* 1886 */ MCD_OPC_Decode, 211, 15, 203, 3, // Opcode: LHGP_NM +/* 1891 */ MCD_OPC_FilterValue, 1, 139, 5, 0, // Skip to: 3315 +/* 1896 */ MCD_OPC_CheckPredicate, 112, 134, 5, 0, // Skip to: 3315 +/* 1901 */ MCD_OPC_Decode, 214, 15, 203, 3, // Opcode: LHUGP_NM +/* 1906 */ MCD_OPC_FilterValue, 5, 124, 5, 0, // Skip to: 3315 +/* 1911 */ MCD_OPC_CheckPredicate, 112, 119, 5, 0, // Skip to: 3315 +/* 1916 */ MCD_OPC_CheckField, 0, 1, 0, 112, 5, 0, // Skip to: 3315 +/* 1923 */ MCD_OPC_Decode, 153, 21, 203, 3, // Opcode: SHGP_NM +/* 1928 */ MCD_OPC_FilterValue, 18, 65, 0, 0, // Skip to: 1998 +/* 1933 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 1936 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1951 +/* 1941 */ MCD_OPC_CheckPredicate, 112, 89, 5, 0, // Skip to: 3315 +/* 1946 */ MCD_OPC_Decode, 244, 14, 185, 3, // Opcode: JALRC_NM +/* 1951 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1966 +/* 1956 */ MCD_OPC_CheckPredicate, 112, 74, 5, 0, // Skip to: 3315 +/* 1961 */ MCD_OPC_Decode, 241, 14, 185, 3, // Opcode: JALRCHB_NM +/* 1966 */ MCD_OPC_FilterValue, 8, 64, 5, 0, // Skip to: 3315 +/* 1971 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 1988 +/* 1976 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 1988 +/* 1983 */ MCD_OPC_Decode, 218, 8, 197, 3, // Opcode: BRSC_NM +/* 1988 */ MCD_OPC_CheckPredicate, 112, 42, 5, 0, // Skip to: 3315 +/* 1993 */ MCD_OPC_Decode, 154, 7, 204, 3, // Opcode: BALRSC_NM +/* 1998 */ MCD_OPC_FilterValue, 32, 217, 1, 0, // Skip to: 2476 +/* 2003 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 2006 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2021 +/* 2011 */ MCD_OPC_CheckPredicate, 112, 19, 5, 0, // Skip to: 3315 +/* 2016 */ MCD_OPC_Decode, 170, 19, 205, 3, // Opcode: ORI_NM +/* 2021 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2036 +/* 2026 */ MCD_OPC_CheckPredicate, 112, 4, 5, 0, // Skip to: 3315 +/* 2031 */ MCD_OPC_Decode, 179, 24, 205, 3, // Opcode: XORI_NM +/* 2036 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2051 +/* 2041 */ MCD_OPC_CheckPredicate, 112, 245, 4, 0, // Skip to: 3315 +/* 2046 */ MCD_OPC_Decode, 226, 6, 205, 3, // Opcode: ANDI_NM +/* 2051 */ MCD_OPC_FilterValue, 3, 69, 0, 0, // Skip to: 2125 +/* 2056 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 2059 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2081 +/* 2064 */ MCD_OPC_CheckPredicate, 112, 222, 4, 0, // Skip to: 3315 +/* 2069 */ MCD_OPC_CheckField, 20, 1, 0, 215, 4, 0, // Skip to: 3315 +/* 2076 */ MCD_OPC_Decode, 192, 20, 206, 3, // Opcode: SAVE_NM +/* 2081 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 2103 +/* 2086 */ MCD_OPC_CheckPredicate, 112, 200, 4, 0, // Skip to: 3315 +/* 2091 */ MCD_OPC_CheckField, 20, 1, 0, 193, 4, 0, // Skip to: 3315 +/* 2098 */ MCD_OPC_Decode, 150, 20, 206, 3, // Opcode: RESTORE_NM +/* 2103 */ MCD_OPC_FilterValue, 3, 183, 4, 0, // Skip to: 3315 +/* 2108 */ MCD_OPC_CheckPredicate, 112, 178, 4, 0, // Skip to: 3315 +/* 2113 */ MCD_OPC_CheckField, 20, 1, 0, 171, 4, 0, // Skip to: 3315 +/* 2120 */ MCD_OPC_Decode, 149, 20, 206, 3, // Opcode: RESTOREJRC_NM +/* 2125 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 2140 +/* 2130 */ MCD_OPC_CheckPredicate, 112, 156, 4, 0, // Skip to: 3315 +/* 2135 */ MCD_OPC_Decode, 242, 21, 205, 3, // Opcode: SLTI_NM +/* 2140 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 2155 +/* 2145 */ MCD_OPC_CheckPredicate, 112, 141, 4, 0, // Skip to: 3315 +/* 2150 */ MCD_OPC_Decode, 241, 21, 205, 3, // Opcode: SLTIU_NM +/* 2155 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 2170 +/* 2160 */ MCD_OPC_CheckPredicate, 112, 126, 4, 0, // Skip to: 3315 +/* 2165 */ MCD_OPC_Decode, 141, 21, 205, 3, // Opcode: SEQI_NM +/* 2170 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 2185 +/* 2175 */ MCD_OPC_CheckPredicate, 112, 111, 4, 0, // Skip to: 3315 +/* 2180 */ MCD_OPC_Decode, 128, 6, 207, 3, // Opcode: ADDIUNEG_NM +/* 2185 */ MCD_OPC_FilterValue, 12, 150, 0, 0, // Skip to: 2340 +/* 2190 */ MCD_OPC_ExtractField, 5, 4, // Inst{8-5} ... +/* 2193 */ MCD_OPC_FilterValue, 0, 97, 0, 0, // Skip to: 2295 +/* 2198 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 2201 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2222 +/* 2206 */ MCD_OPC_CheckPredicate, 112, 74, 0, 0, // Skip to: 2285 +/* 2211 */ MCD_OPC_CheckField, 16, 10, 0, 67, 0, 0, // Skip to: 2285 +/* 2218 */ MCD_OPC_Decode, 149, 19, 10, // Opcode: NOP32_NM +/* 2222 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 2243 +/* 2227 */ MCD_OPC_CheckPredicate, 112, 53, 0, 0, // Skip to: 2285 +/* 2232 */ MCD_OPC_CheckField, 16, 10, 0, 46, 0, 0, // Skip to: 2285 +/* 2239 */ MCD_OPC_Decode, 209, 12, 10, // Opcode: EHB_NM +/* 2243 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 2264 +/* 2248 */ MCD_OPC_CheckPredicate, 112, 32, 0, 0, // Skip to: 2285 +/* 2253 */ MCD_OPC_CheckField, 16, 10, 0, 25, 0, 0, // Skip to: 2285 +/* 2260 */ MCD_OPC_Decode, 184, 19, 10, // Opcode: PAUSE_NM +/* 2264 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2285 +/* 2269 */ MCD_OPC_CheckPredicate, 112, 11, 0, 0, // Skip to: 2285 +/* 2274 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 2285 +/* 2281 */ MCD_OPC_Decode, 181, 23, 87, // Opcode: SYNC_NM +/* 2285 */ MCD_OPC_CheckPredicate, 112, 1, 4, 0, // Skip to: 3315 +/* 2290 */ MCD_OPC_Decode, 237, 21, 208, 3, // Opcode: SLL_NM +/* 2295 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2310 +/* 2300 */ MCD_OPC_CheckPredicate, 112, 242, 3, 0, // Skip to: 3315 +/* 2305 */ MCD_OPC_Decode, 183, 22, 208, 3, // Opcode: SRL_NM +/* 2310 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 2325 +/* 2315 */ MCD_OPC_CheckPredicate, 112, 227, 3, 0, // Skip to: 3315 +/* 2320 */ MCD_OPC_Decode, 158, 22, 208, 3, // Opcode: SRA_NM +/* 2325 */ MCD_OPC_FilterValue, 6, 217, 3, 0, // Skip to: 3315 +/* 2330 */ MCD_OPC_CheckPredicate, 112, 212, 3, 0, // Skip to: 3315 +/* 2335 */ MCD_OPC_Decode, 160, 20, 208, 3, // Opcode: ROTR_NM +/* 2340 */ MCD_OPC_FilterValue, 13, 73, 0, 0, // Skip to: 2418 +/* 2345 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 2348 */ MCD_OPC_FilterValue, 0, 194, 3, 0, // Skip to: 3315 +/* 2353 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 2356 */ MCD_OPC_FilterValue, 0, 186, 3, 0, // Skip to: 3315 +/* 2361 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 2364 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 2386 +/* 2369 */ MCD_OPC_CheckPredicate, 112, 34, 0, 0, // Skip to: 2408 +/* 2374 */ MCD_OPC_CheckField, 6, 5, 8, 27, 0, 0, // Skip to: 2408 +/* 2381 */ MCD_OPC_Decode, 229, 8, 185, 3, // Opcode: BYTEREVW_NM +/* 2386 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 2408 +/* 2391 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 2408 +/* 2396 */ MCD_OPC_CheckField, 6, 5, 0, 5, 0, 0, // Skip to: 2408 +/* 2403 */ MCD_OPC_Decode, 130, 8, 185, 3, // Opcode: BITREVW_NM +/* 2408 */ MCD_OPC_CheckPredicate, 112, 134, 3, 0, // Skip to: 3315 +/* 2413 */ MCD_OPC_Decode, 161, 20, 209, 3, // Opcode: ROTX_NM +/* 2418 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 2447 +/* 2423 */ MCD_OPC_CheckPredicate, 112, 119, 3, 0, // Skip to: 3315 +/* 2428 */ MCD_OPC_CheckField, 11, 1, 0, 112, 3, 0, // Skip to: 3315 +/* 2435 */ MCD_OPC_CheckField, 5, 1, 0, 105, 3, 0, // Skip to: 3315 +/* 2442 */ MCD_OPC_Decode, 233, 14, 210, 3, // Opcode: INS_NM +/* 2447 */ MCD_OPC_FilterValue, 15, 95, 3, 0, // Skip to: 3315 +/* 2452 */ MCD_OPC_CheckPredicate, 112, 90, 3, 0, // Skip to: 3315 +/* 2457 */ MCD_OPC_CheckField, 11, 1, 0, 83, 3, 0, // Skip to: 3315 +/* 2464 */ MCD_OPC_CheckField, 5, 1, 0, 76, 3, 0, // Skip to: 3315 +/* 2471 */ MCD_OPC_Decode, 129, 13, 211, 3, // Opcode: EXT_NM +/* 2476 */ MCD_OPC_FilterValue, 33, 155, 0, 0, // Skip to: 2636 +/* 2481 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 2484 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2499 +/* 2489 */ MCD_OPC_CheckPredicate, 112, 53, 3, 0, // Skip to: 3315 +/* 2494 */ MCD_OPC_Decode, 172, 15, 212, 3, // Opcode: LB_NM +/* 2499 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2514 +/* 2504 */ MCD_OPC_CheckPredicate, 112, 38, 3, 0, // Skip to: 3315 +/* 2509 */ MCD_OPC_Decode, 204, 20, 212, 3, // Opcode: SB_NM +/* 2514 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2529 +/* 2519 */ MCD_OPC_CheckPredicate, 112, 23, 3, 0, // Skip to: 3315 +/* 2524 */ MCD_OPC_Decode, 167, 15, 212, 3, // Opcode: LBU_NM +/* 2529 */ MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 2561 +/* 2534 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 2551 +/* 2539 */ MCD_OPC_CheckField, 21, 5, 31, 5, 0, 0, // Skip to: 2551 +/* 2546 */ MCD_OPC_Decode, 177, 23, 213, 3, // Opcode: SYNCI_NM +/* 2551 */ MCD_OPC_CheckPredicate, 112, 247, 2, 0, // Skip to: 3315 +/* 2556 */ MCD_OPC_Decode, 244, 19, 214, 3, // Opcode: PREF_NM +/* 2561 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 2576 +/* 2566 */ MCD_OPC_CheckPredicate, 112, 232, 2, 0, // Skip to: 3315 +/* 2571 */ MCD_OPC_Decode, 224, 15, 212, 3, // Opcode: LH_NM +/* 2576 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 2591 +/* 2581 */ MCD_OPC_CheckPredicate, 112, 217, 2, 0, // Skip to: 3315 +/* 2586 */ MCD_OPC_Decode, 206, 21, 212, 3, // Opcode: SH_NM +/* 2591 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 2606 +/* 2596 */ MCD_OPC_CheckPredicate, 112, 202, 2, 0, // Skip to: 3315 +/* 2601 */ MCD_OPC_Decode, 217, 15, 212, 3, // Opcode: LHU_NM +/* 2606 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 2621 +/* 2611 */ MCD_OPC_CheckPredicate, 112, 187, 2, 0, // Skip to: 3315 +/* 2616 */ MCD_OPC_Decode, 181, 16, 212, 3, // Opcode: LW_NM +/* 2621 */ MCD_OPC_FilterValue, 9, 177, 2, 0, // Skip to: 3315 +/* 2626 */ MCD_OPC_CheckPredicate, 112, 172, 2, 0, // Skip to: 3315 +/* 2631 */ MCD_OPC_Decode, 171, 23, 212, 3, // Opcode: SW_NM +/* 2636 */ MCD_OPC_FilterValue, 34, 48, 0, 0, // Skip to: 2689 +/* 2641 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 2644 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2659 +/* 2649 */ MCD_OPC_CheckPredicate, 112, 149, 2, 0, // Skip to: 3315 +/* 2654 */ MCD_OPC_Decode, 194, 7, 215, 3, // Opcode: BEQC_NM +/* 2659 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2674 +/* 2664 */ MCD_OPC_CheckPredicate, 112, 134, 2, 0, // Skip to: 3315 +/* 2669 */ MCD_OPC_Decode, 212, 7, 215, 3, // Opcode: BGEC_NM +/* 2674 */ MCD_OPC_FilterValue, 3, 124, 2, 0, // Skip to: 3315 +/* 2679 */ MCD_OPC_CheckPredicate, 112, 119, 2, 0, // Skip to: 3315 +/* 2684 */ MCD_OPC_Decode, 218, 7, 215, 3, // Opcode: BGEUC_NM +/* 2689 */ MCD_OPC_FilterValue, 41, 146, 1, 0, // Skip to: 3096 +/* 2694 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 2697 */ MCD_OPC_FilterValue, 0, 78, 0, 0, // Skip to: 2780 +/* 2702 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 2705 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2720 +/* 2710 */ MCD_OPC_CheckPredicate, 112, 88, 2, 0, // Skip to: 3315 +/* 2715 */ MCD_OPC_Decode, 173, 15, 216, 3, // Opcode: LBs9_NM +/* 2720 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2735 +/* 2725 */ MCD_OPC_CheckPredicate, 112, 73, 2, 0, // Skip to: 3315 +/* 2730 */ MCD_OPC_Decode, 168, 15, 216, 3, // Opcode: LBUs9_NM +/* 2735 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2750 +/* 2740 */ MCD_OPC_CheckPredicate, 112, 58, 2, 0, // Skip to: 3315 +/* 2745 */ MCD_OPC_Decode, 225, 15, 216, 3, // Opcode: LHs9_NM +/* 2750 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2765 +/* 2755 */ MCD_OPC_CheckPredicate, 112, 43, 2, 0, // Skip to: 3315 +/* 2760 */ MCD_OPC_Decode, 218, 15, 216, 3, // Opcode: LHUs9_NM +/* 2765 */ MCD_OPC_FilterValue, 4, 33, 2, 0, // Skip to: 3315 +/* 2770 */ MCD_OPC_CheckPredicate, 112, 28, 2, 0, // Skip to: 3315 +/* 2775 */ MCD_OPC_Decode, 182, 16, 216, 3, // Opcode: LWs9_NM +/* 2780 */ MCD_OPC_FilterValue, 1, 56, 0, 0, // Skip to: 2841 +/* 2785 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 2788 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2803 +/* 2793 */ MCD_OPC_CheckPredicate, 112, 5, 2, 0, // Skip to: 3315 +/* 2798 */ MCD_OPC_Decode, 146, 24, 141, 1, // Opcode: UALH_NM +/* 2803 */ MCD_OPC_FilterValue, 5, 251, 1, 0, // Skip to: 3315 +/* 2808 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 2811 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2826 +/* 2816 */ MCD_OPC_CheckPredicate, 112, 238, 1, 0, // Skip to: 3315 +/* 2821 */ MCD_OPC_Decode, 245, 15, 217, 3, // Opcode: LL_NM +/* 2826 */ MCD_OPC_FilterValue, 1, 228, 1, 0, // Skip to: 3315 +/* 2831 */ MCD_OPC_CheckPredicate, 112, 223, 1, 0, // Skip to: 3315 +/* 2836 */ MCD_OPC_Decode, 242, 15, 218, 3, // Opcode: LLWP_NM +/* 2841 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 2856 +/* 2846 */ MCD_OPC_CheckPredicate, 112, 208, 1, 0, // Skip to: 3315 +/* 2851 */ MCD_OPC_Decode, 157, 16, 219, 3, // Opcode: LWM_NM +/* 2856 */ MCD_OPC_FilterValue, 5, 27, 0, 0, // Skip to: 2888 +/* 2861 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 2878 +/* 2866 */ MCD_OPC_CheckField, 12, 3, 1, 5, 0, 0, // Skip to: 2878 +/* 2873 */ MCD_OPC_Decode, 148, 24, 141, 1, // Opcode: UALW_NM +/* 2878 */ MCD_OPC_CheckPredicate, 112, 176, 1, 0, // Skip to: 3315 +/* 2883 */ MCD_OPC_Decode, 147, 24, 219, 3, // Opcode: UALWM_NM +/* 2888 */ MCD_OPC_FilterValue, 8, 80, 0, 0, // Skip to: 2973 +/* 2893 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 2896 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2911 +/* 2901 */ MCD_OPC_CheckPredicate, 112, 153, 1, 0, // Skip to: 3315 +/* 2906 */ MCD_OPC_Decode, 205, 20, 216, 3, // Opcode: SBs9_NM +/* 2911 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 2943 +/* 2916 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 2933 +/* 2921 */ MCD_OPC_CheckField, 21, 5, 31, 5, 0, 0, // Skip to: 2933 +/* 2928 */ MCD_OPC_Decode, 178, 23, 220, 3, // Opcode: SYNCIs9_NM +/* 2933 */ MCD_OPC_CheckPredicate, 112, 121, 1, 0, // Skip to: 3315 +/* 2938 */ MCD_OPC_Decode, 246, 19, 221, 3, // Opcode: PREFs9_NM +/* 2943 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2958 +/* 2948 */ MCD_OPC_CheckPredicate, 112, 106, 1, 0, // Skip to: 3315 +/* 2953 */ MCD_OPC_Decode, 207, 21, 216, 3, // Opcode: SHs9_NM +/* 2958 */ MCD_OPC_FilterValue, 4, 96, 1, 0, // Skip to: 3315 +/* 2963 */ MCD_OPC_CheckPredicate, 112, 91, 1, 0, // Skip to: 3315 +/* 2968 */ MCD_OPC_Decode, 172, 23, 216, 3, // Opcode: SWs9_NM +/* 2973 */ MCD_OPC_FilterValue, 9, 71, 0, 0, // Skip to: 3049 +/* 2978 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 2981 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2996 +/* 2986 */ MCD_OPC_CheckPredicate, 112, 68, 1, 0, // Skip to: 3315 +/* 2991 */ MCD_OPC_Decode, 149, 24, 141, 1, // Opcode: UASH_NM +/* 2996 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 3011 +/* 3001 */ MCD_OPC_CheckPredicate, 112, 53, 1, 0, // Skip to: 3315 +/* 3006 */ MCD_OPC_Decode, 251, 8, 221, 3, // Opcode: CACHE_NM +/* 3011 */ MCD_OPC_FilterValue, 5, 43, 1, 0, // Skip to: 3315 +/* 3016 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3019 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3034 +/* 3024 */ MCD_OPC_CheckPredicate, 112, 30, 1, 0, // Skip to: 3315 +/* 3029 */ MCD_OPC_Decode, 216, 20, 222, 3, // Opcode: SC_NM +/* 3034 */ MCD_OPC_FilterValue, 1, 20, 1, 0, // Skip to: 3315 +/* 3039 */ MCD_OPC_CheckPredicate, 112, 15, 1, 0, // Skip to: 3315 +/* 3044 */ MCD_OPC_Decode, 213, 20, 223, 3, // Opcode: SCWP_NM +/* 3049 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 3064 +/* 3054 */ MCD_OPC_CheckPredicate, 112, 0, 1, 0, // Skip to: 3315 +/* 3059 */ MCD_OPC_Decode, 154, 23, 219, 3, // Opcode: SWM_NM +/* 3064 */ MCD_OPC_FilterValue, 13, 246, 0, 0, // Skip to: 3315 +/* 3069 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 3086 +/* 3074 */ MCD_OPC_CheckField, 12, 3, 1, 5, 0, 0, // Skip to: 3086 +/* 3081 */ MCD_OPC_Decode, 151, 24, 141, 1, // Opcode: UASW_NM +/* 3086 */ MCD_OPC_CheckPredicate, 112, 224, 0, 0, // Skip to: 3315 +/* 3091 */ MCD_OPC_Decode, 150, 24, 219, 3, // Opcode: UASWM_NM +/* 3096 */ MCD_OPC_FilterValue, 42, 48, 0, 0, // Skip to: 3149 +/* 3101 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 3104 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3119 +/* 3109 */ MCD_OPC_CheckPredicate, 112, 201, 0, 0, // Skip to: 3315 +/* 3114 */ MCD_OPC_Decode, 176, 8, 215, 3, // Opcode: BNEC_NM +/* 3119 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 3134 +/* 3124 */ MCD_OPC_CheckPredicate, 112, 186, 0, 0, // Skip to: 3315 +/* 3129 */ MCD_OPC_Decode, 146, 8, 215, 3, // Opcode: BLTC_NM +/* 3134 */ MCD_OPC_FilterValue, 3, 176, 0, 0, // Skip to: 3315 +/* 3139 */ MCD_OPC_CheckPredicate, 112, 171, 0, 0, // Skip to: 3315 +/* 3144 */ MCD_OPC_Decode, 152, 8, 215, 3, // Opcode: BLTUC_NM +/* 3149 */ MCD_OPC_FilterValue, 50, 123, 0, 0, // Skip to: 3277 +/* 3154 */ MCD_OPC_ExtractField, 18, 3, // Inst{20-18} ... +/* 3157 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3172 +/* 3162 */ MCD_OPC_CheckPredicate, 112, 148, 0, 0, // Skip to: 3315 +/* 3167 */ MCD_OPC_Decode, 196, 7, 224, 3, // Opcode: BEQIC_NM +/* 3172 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3187 +/* 3177 */ MCD_OPC_CheckPredicate, 112, 133, 0, 0, // Skip to: 3315 +/* 3182 */ MCD_OPC_Decode, 155, 7, 225, 3, // Opcode: BBEQZC_NM +/* 3187 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 3202 +/* 3192 */ MCD_OPC_CheckPredicate, 112, 118, 0, 0, // Skip to: 3315 +/* 3197 */ MCD_OPC_Decode, 213, 7, 224, 3, // Opcode: BGEIC_NM +/* 3202 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 3217 +/* 3207 */ MCD_OPC_CheckPredicate, 112, 103, 0, 0, // Skip to: 3315 +/* 3212 */ MCD_OPC_Decode, 214, 7, 224, 3, // Opcode: BGEIUC_NM +/* 3217 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 3232 +/* 3222 */ MCD_OPC_CheckPredicate, 112, 88, 0, 0, // Skip to: 3315 +/* 3227 */ MCD_OPC_Decode, 186, 8, 224, 3, // Opcode: BNEIC_NM +/* 3232 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 3247 +/* 3237 */ MCD_OPC_CheckPredicate, 112, 73, 0, 0, // Skip to: 3315 +/* 3242 */ MCD_OPC_Decode, 160, 7, 225, 3, // Opcode: BBNEZC_NM +/* 3247 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 3262 +/* 3252 */ MCD_OPC_CheckPredicate, 112, 58, 0, 0, // Skip to: 3315 +/* 3257 */ MCD_OPC_Decode, 147, 8, 224, 3, // Opcode: BLTIC_NM +/* 3262 */ MCD_OPC_FilterValue, 7, 48, 0, 0, // Skip to: 3315 +/* 3267 */ MCD_OPC_CheckPredicate, 112, 43, 0, 0, // Skip to: 3315 +/* 3272 */ MCD_OPC_Decode, 148, 8, 224, 3, // Opcode: BLTIUC_NM +/* 3277 */ MCD_OPC_FilterValue, 56, 33, 0, 0, // Skip to: 3315 +/* 3282 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 3285 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3300 +/* 3290 */ MCD_OPC_CheckPredicate, 112, 20, 0, 0, // Skip to: 3315 +/* 3295 */ MCD_OPC_Decode, 252, 15, 226, 3, // Opcode: LUI_NM +/* 3300 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3315 +/* 3305 */ MCD_OPC_CheckPredicate, 112, 5, 0, 0, // Skip to: 3315 +/* 3310 */ MCD_OPC_Decode, 215, 6, 226, 3, // Opcode: ALUIPC_NM +/* 3315 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNanoMips48[] = { +/* 0 */ MCD_OPC_ExtractField, 32, 5, // Inst{36-32} ... +/* 3 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 25 +/* 8 */ MCD_OPC_CheckPredicate, 112, 122, 0, 0, // Skip to: 135 +/* 13 */ MCD_OPC_CheckField, 42, 6, 24, 115, 0, 0, // Skip to: 135 +/* 20 */ MCD_OPC_Decode, 234, 15, 227, 3, // Opcode: LI48_NM +/* 25 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 47 +/* 30 */ MCD_OPC_CheckPredicate, 112, 100, 0, 0, // Skip to: 135 +/* 35 */ MCD_OPC_CheckField, 42, 6, 24, 93, 0, 0, // Skip to: 135 +/* 42 */ MCD_OPC_Decode, 252, 5, 228, 3, // Opcode: ADDIU48_NM +/* 47 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 69 +/* 52 */ MCD_OPC_CheckPredicate, 112, 78, 0, 0, // Skip to: 135 +/* 57 */ MCD_OPC_CheckField, 42, 6, 24, 71, 0, 0, // Skip to: 135 +/* 64 */ MCD_OPC_Decode, 253, 5, 229, 3, // Opcode: ADDIUGP48_NM +/* 69 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 91 +/* 74 */ MCD_OPC_CheckPredicate, 112, 56, 0, 0, // Skip to: 135 +/* 79 */ MCD_OPC_CheckField, 42, 6, 24, 49, 0, 0, // Skip to: 135 +/* 86 */ MCD_OPC_Decode, 153, 15, 230, 3, // Opcode: LAPC48_NM +/* 91 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 113 +/* 96 */ MCD_OPC_CheckPredicate, 112, 34, 0, 0, // Skip to: 135 +/* 101 */ MCD_OPC_CheckField, 42, 6, 24, 27, 0, 0, // Skip to: 135 +/* 108 */ MCD_OPC_Decode, 160, 16, 230, 3, // Opcode: LWPC_NM +/* 113 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 135 +/* 118 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 135 +/* 123 */ MCD_OPC_CheckField, 42, 6, 24, 5, 0, 0, // Skip to: 135 +/* 130 */ MCD_OPC_Decode, 155, 23, 230, 3, // Opcode: SWPC_NM +/* 135 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNanoMips_Conflict_Space16[] = { +/* 0 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 17 +/* 5 */ MCD_OPC_CheckField, 10, 6, 54, 5, 0, 0, // Skip to: 17 +/* 12 */ MCD_OPC_Decode, 173, 8, 173, 3, // Opcode: BNEC16_NM +/* 17 */ MCD_OPC_Fail, + 0 +}; + +static bool checkDecoderPredicate(MCInst *Inst, unsigned Idx) { switch (Idx) { - default: // llvm_unreachable("Invalid index!"); + default: /* llvm_unreachable("Invalid index!"); */ case 0: - return getbool((Bits & Mips_FeatureMips16)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16)); case 1: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMicroMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCnMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 2: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMicroMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCnMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 3: - return getbool((Bits & Mips_FeatureMicroMips)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCnMips)); case 4: - return getbool((Bits & Mips_FeatureMips32) && (Bits & Mips_FeatureMicroMips)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCnMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 5: - return getbool(!(Bits & Mips_FeatureMips16)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCnMipsP)); case 6: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6)); case 7: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 8: - return getbool((Bits & Mips_FeatureMSA)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSP)); case 9: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSPR2)); case 10: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r5) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureVirt)); case 11: - return getbool(!(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSPR3)); case 12: - return getbool((Bits & Mips_FeatureDSP)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSP)); case 13: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 14: - return getbool((Bits & Mips_FeatureMSA) && (Bits & Mips_FeatureMips64)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4)); case 15: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 16: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4)); case 17: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 18: - return getbool(!(Bits & Mips_FeatureMicroMips)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 19: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 20: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && !(Bits & Mips_FeatureFP64Bit)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 21: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureEVA)); case 22: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32r2)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureEVA)); case 23: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureFP64Bit)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 24: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6)); case 25: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureFP64Bit)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGINV)); case 26: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 27: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 28: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 29: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 30: - return getbool((Bits & Mips_FeatureDSPR2)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMSA)); case 31: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 32: - return getbool((Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6)); case 33: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureUseIndirectJumpsHazard) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 34: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32)); case 35: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 36: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 37: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSP)); case 38: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMSA) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64)); case 39: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 40: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r2)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSP) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 41: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r5) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureVirt) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 42: - return getbool((Bits & Mips_FeatureMips64)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMT) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 43: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && (Bits & Mips_FeatureFP64Bit)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 44: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureEVA) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 45: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && (Bits & Mips_FeatureFP64Bit)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r5) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 46: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 47: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && (Bits & Mips_FeatureFP64Bit)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 48: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 49: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 50: - return getbool((Bits & Mips_FeatureCnMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 51: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 52: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 53: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); + case 54: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 55: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 56: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 57: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 58: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 59: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 60: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 61: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); + case 62: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 63: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips5_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 64: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4)); + case 65: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4)); + case 66: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 67: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 68: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); + case 69: + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSPR2)); + case 70: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureEVA) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 71: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); + case 72: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeaturePTR64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); + case 73: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeaturePTR64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 74: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeaturePTR64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 75: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6)); + case 76: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 77: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 78: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 79: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 80: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCRC) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 81: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCRC) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 82: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeaturePTR64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 83: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGINV) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 84: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6)); + case 85: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6)); + case 86: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6)); + case 87: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeaturePTR64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 88: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 89: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeaturePTR64Bit)); + case 90: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 91: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 92: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 93: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3)); + case 94: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r5) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureVirt)); + case 95: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6)); + case 96: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 97: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSP)); + case 98: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 99: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 100: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 101: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 102: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 103: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 104: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 105: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3D)); + case 106: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 107: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 108: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); + case 109: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips5_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 110: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4)); + case 111: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 112: + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); + case 113: + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMT)); + case 114: + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCRC)); + case 115: + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureTLB)); + case 116: + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGINV)); } } -#define DecodeToMCInst(fname,fieldname, InsnType) \ +#define DecodeToMCInst(fname, fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, void *Decoder) \ + uint64_t Address, const void *Decoder, bool *DecodeComplete) \ { \ + *DecodeComplete = true; \ InsnType tmp; \ switch (Idx) { \ - default: \ + default: /* llvm_unreachable("Invalid index!"); */ \ case 0: \ + tmp = fieldname(insn, 0, 11); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 1: \ tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 2: \ tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 3: \ - tmp = 0; \ - tmp |= fieldname(insn, 3, 2) << 3; \ - tmp |= fieldname(insn, 5, 3) << 0; \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 4: \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 5: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 2) << 3; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 6: \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 7: \ tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 8: \ - tmp = 0; \ + tmp = fieldname(insn, 2, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 9: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 10: \ + return S; \ + case 11: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 12: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 13: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 14: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 0, 5) << 0; \ tmp |= fieldname(insn, 16, 5) << 11; \ tmp |= fieldname(insn, 21, 6) << 5; \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 9: \ - tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 10: \ - if (DecodeFMem3(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 11: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 12: \ - if (DecodeMemMMImm4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 13: \ - tmp = fieldname(insn, 5, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 14: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 15: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeANDI16Imm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + tmp |= fieldname(insn, 21, 6) << 5; \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 16: \ - tmp = fieldname(insn, 3, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + tmp |= fieldname(insn, 21, 6) << 5; \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 17: \ - tmp = fieldname(insn, 3, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 3, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 21, 1) << 5; \ + tmp |= fieldname(insn, 22, 5) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 18: \ - if (DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + tmp |= fieldname(insn, 21, 6) << 5; \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 19: \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFIXMEInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 20: \ - tmp = fieldname(insn, 0, 4); \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + tmp |= fieldname(insn, 21, 6) << 5; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 21: \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeUImm5lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFMem3(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 22: \ - if (DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 23: \ - tmp = fieldname(insn, 5, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 4); \ - if (DecodeSimm4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 24: \ - tmp = fieldname(insn, 1, 9); \ - if (DecodeSimm9SP(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 25: \ - if (DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 26: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - if (DecodeAddiur2Simm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 27: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 6); \ - if (DecodeUImm6Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 10); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_10_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 28: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeMovePRegPair(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 29: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 7); \ - if (DecodeBranchTarget7MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 30: \ - tmp = fieldname(insn, 0, 10); \ - if (DecodeBranchTarget10MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 31: \ tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 7); \ - if (DecodeLiSimm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 32: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeMemMMImm4(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 33: \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 6, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 34: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodePOOL16BEncodedField(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 35: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeANDI16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 36: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 37: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 38: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 39: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 40: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ + tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 41: \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeUImmWithOffsetAndScale_5_0_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 42: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 43: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 1, 4); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_4_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 44: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 9); \ + if (!Check(&S, DecodeSimm9SP(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 45: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 46: \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeAddiur2Simm7(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 47: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 1, 6); \ + if (!Check(&S, DecodeUImmWithOffsetAndScale_6_0_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 48: \ - if (DecodeMemMMImm16(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMovePOperands(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 49: \ - if (DecodeMemMMImm12(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 7); \ + if (!Check(&S, DecodeBranchTarget7MM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 50: \ - if (DecodeCacheOpMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 10); \ + if (!Check(&S, DecodeBranchTarget10MM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 51: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 7); \ + if (!Check(&S, DecodeLi16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 52: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 53: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 54: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 13, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 55: \ - if (DecodeJumpTargetMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 56: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 23); \ - if (DecodeSimm23Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 6, 10); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 57: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeInsSize(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 58: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 59: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 60: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 61: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 62: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 63: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 64: \ - tmp = fieldname(insn, 6, 20); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 65: \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_6_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 66: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeUImmWithOffset_5_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 67: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 68: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 69: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 70: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 71: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 72: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 10); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 73: \ + case 69: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 70: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 71: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 72: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 73: \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 74: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 75: \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 76: \ - if (DecodeSyncI(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 77: \ - if (DecodeJumpTarget(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 78: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 79: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 80: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 81: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 82: \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 83: \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 84: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 85: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 86: \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 87: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 88: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 89: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 90: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 91: \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 92: \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 93: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 94: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 7); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 95: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 96: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 10); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_10_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 97: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 98: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemMMImm16(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 99: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemMMImm12(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 100: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCacheOpMM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 101: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTargetMM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 102: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 103: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 104: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSyncI_MM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 105: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget1SImm16(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 106: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTargetMM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 107: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeBranchTargetMM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 108: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 109: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 110: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 111: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 112: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 113: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 114: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 115: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 116: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 117: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 118: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 119: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 120: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 121: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 122: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 123: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 124: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 125: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 126: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 127: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCCRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 128: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 129: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 130: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCCRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 131: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 132: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 133: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 134: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeMemMMImm9(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 135: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodePrefeOpMM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 136: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeJumpTargetMM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 137: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 23, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 23); \ + if (!Check(&S, DecodeSimm23Lsl2(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 138: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTargetMM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 139: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFMemMMR2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 140: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeJumpTargetXMM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 141: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMem(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 142: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 143: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 144: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 145: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 146: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 147: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 148: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 149: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 150: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 151: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeUImmWithOffsetAndScale_5_0_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 152: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 4); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 153: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 154: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 9, 2); \ + if (!Check(&S, DecodeUImmWithOffset_2_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 155: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 156: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 157: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 16); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 158: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 159: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeLoadByte15(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 160: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFMemCop2MMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 161: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTargetMM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 162: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTargetMM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 163: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSynciR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 164: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 165: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 166: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 167: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 168: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 169: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 170: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 171: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 172: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 173: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePOP35GroupBranchMMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 174: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 19); \ + if (!Check(&S, DecodeSimm19Lsl2(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 175: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 176: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodePOP37GroupBranchMMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 177: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 21); \ + if (!Check(&S, DecodeBranchTarget21MM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 178: \ - if (DecodeINSVE_DF_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 26); \ + if (!Check(&S, DecodeBranchTarget26MM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 179: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeBlezGroupBranchMMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 180: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePOP65GroupBranchMMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 181: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeBgtzGroupBranchMMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 182: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePOP75GroupBranchMMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 183: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 184: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 185: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeUImmWithOffset_2_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 186: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 187: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 188: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 20); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 189: \ tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 190: \ - if (DecodeMSA128Mem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 191: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ - if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 192: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 193: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 194: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeUImmWithOffset_2_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 195: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 196: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 197: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 198: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 199: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 200: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 201: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 202: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 203: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 204: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 205: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 206: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 207: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 208: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 209: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 210: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 211: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 212: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 213: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 214: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 6); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 215: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 216: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 217: \ - if (DecodeMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 218: \ - if (DecodeCacheOp(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 219: \ - if (DecodeFMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 220: \ - if (DecodeFMem2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 221: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 222: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 223: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 224: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 225: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 226: \ - if (DecodeBlezGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 227: \ - if (DecodeBgtzGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 228: \ - if (DecodeAddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 229: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 230: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 231: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 232: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 233: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 234: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 235: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 236: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 237: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 238: \ - if (DecodeFMemCop2R6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 239: \ - if (DecodeBlezlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 240: \ - if (DecodeBgtzlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 241: \ - if (DecodeDaddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 242: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 243: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 244: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 245: \ - if (DecodeCacheOpR6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 246: \ - if (DecodeSpecial3LlSc(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 247: \ - tmp = fieldname(insn, 0, 26); \ - if (DecodeBranchTarget26(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 248: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 21); \ - if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 249: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 19); \ - if (DecodeSimm19Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 250: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 18); \ - if (DecodeSimm18Lsl3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 251: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 252: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 253: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 254: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 255: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 256: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 257: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 258: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 259: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 260: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 261: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 262: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 263: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 264: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 265: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 266: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 267: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 268: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 269: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 197: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 198: \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 199: \ + if (!Check(&S, DecodeSyncI(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 200: \ + if (!Check(&S, DecodeJumpTarget(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 201: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 202: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 203: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 204: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ + case 205: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 206: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 4, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 207: \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 208: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 209: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 210: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCCRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 211: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 212: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 213: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 214: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCCRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 215: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 216: \ + tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 217: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 218: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 219: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 220: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 221: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 222: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 223: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 224: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 225: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 226: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 227: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 228: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 229: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 230: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 231: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 232: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 233: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 234: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 235: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 236: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 237: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 238: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 239: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 240: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 241: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 242: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 243: \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 244: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 245: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 246: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 247: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 248: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 249: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 250: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 251: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 252: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 253: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 254: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 255: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 256: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 257: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 258: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 259: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 260: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 261: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 262: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 263: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 264: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 265: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 266: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 267: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 268: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 269: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ case 270: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ - if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 271: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 272: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 273: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 274: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 275: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 276: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 277: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 278: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 279: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 280: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 281: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 282: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 283: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 284: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 285: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 286: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 287: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 288: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 289: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 290: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 291: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 292: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 293: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 294: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 295: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 296: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 297: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 298: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 299: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 300: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 301: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 302: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 303: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 304: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 305: \ + if (!Check(&S, DecodeINSVE_DF(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 306: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 307: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 308: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 309: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 310: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 311: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 312: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 313: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 314: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 315: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 316: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 317: \ + if (!Check(&S, DecodeMSA128Mem(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 318: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ - if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeUImmWithOffset_5_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 272: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 319: \ tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeInsSize(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 320: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 321: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 322: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 323: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 324: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 325: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 326: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 327: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 328: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 329: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 330: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 331: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 332: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 333: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 334: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 335: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 336: \ + if (!Check(&S, DecodeMemEVA(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 337: \ + if (!Check(&S, DecodeCacheeOp_CacheOpR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 338: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 339: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 340: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 341: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 342: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 343: \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 6); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_6_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 344: \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 345: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 346: \ + if (!Check(&S, DecodeCacheOp(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 347: \ + if (!Check(&S, DecodeFMem(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 348: \ + if (!Check(&S, DecodeFMem2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 349: \ + if (!Check(&S, DecodeDAHIDATI(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 350: \ tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 351: \ + if (!Check(&S, DecodeBlezGroupBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 352: \ + if (!Check(&S, DecodeBgtzGroupBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 353: \ + if (!Check(&S, DecodeAddiGroupBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 354: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 355: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 356: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 357: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 358: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 359: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 360: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 361: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 362: \ + if (!Check(&S, DecodeFMemCop2R6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 363: \ + if (!Check(&S, DecodeBlezlGroupBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 364: \ + if (!Check(&S, DecodeBgtzlGroupBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 365: \ + if (!Check(&S, DecodeDaddiGroupBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 366: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 367: \ + if (!Check(&S, DecodeCRC(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 368: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 369: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 370: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 371: \ + if (!Check(&S, DecodeSpecial3LlSc(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 372: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 373: \ + tmp = fieldname(insn, 0, 26); \ + if (!Check(&S, DecodeBranchTarget26(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 374: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 21); \ + if (!Check(&S, DecodeBranchTarget21(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 375: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 18); \ + if (!Check(&S, DecodeSimm18Lsl3(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 376: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 21); \ + if (!Check(&S, DecodeBranchTarget21(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 377: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 378: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 379: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 380: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 381: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 382: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 383: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 384: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 385: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 386: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 387: \ + if (!Check(&S, DecodeDEXT(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 388: \ + if (!Check(&S, DecodeDINS(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 389: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 390: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 391: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 392: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 393: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 394: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 395: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 396: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 397: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 398: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 399: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 400: \ + tmp = fieldname(insn, 0, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 401: \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 402: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPRNM32NZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 403: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 7) << 2; \ + if (!Check(&S, DecodeMemNM_6_0_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 404: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 10; \ + tmp |= fieldname(insn, 1, 9) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_10(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 405: \ + tmp = fieldname(insn, 4, 4) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + if (!Check(&S, DecodeNMRegList16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 406: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeUImm3Shift(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 407: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5) << 2; \ + if (!Check(&S, DecodeMemNM_7_0_Mips_GPRNMSPRegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 408: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 409: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 410: \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 411: \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 3) << 0; \ + tmp |= fieldname(insn, 7, 3) << 5; \ + if (!Check(&S, DecodeMemNMRX_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 412: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 7) << 2; \ + if (!Check(&S, DecodeMemNM_9_0_Mips_GPRNMGPRegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 413: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 2) << 0; \ + tmp |= fieldname(insn, 4, 3) << 2; \ + if (!Check(&S, DecodeMemNM_2_0_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 414: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 2) << 0; \ + tmp |= fieldname(insn, 4, 3) << 2; \ + if (!Check(&S, DecodeMemNM_2_0_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 415: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 6) << 2; \ + if (!Check(&S, DecodeUImmWithReg_8_0_1_Mips_SP_NM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 416: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 4; \ + tmp |= fieldname(insn, 3, 1) << 3; \ + tmp |= fieldname(insn, 4, 1) << 8; \ + tmp |= fieldname(insn, 8, 1) << 2; \ + if (!Check(&S, DecodeMemNM4x4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 417: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 2) << 1; \ + tmp |= fieldname(insn, 4, 3) << 3; \ + if (!Check(&S, DecodeMemNM_3_0_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 418: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 2) << 1; \ + tmp |= fieldname(insn, 4, 3) << 3; \ + if (!Check(&S, DecodeMemNM_3_0_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 419: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 420: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 4, 1) << 3; \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_4_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 421: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 7) << 2; \ + if (!Check(&S, DecodeMemNM_6_0_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 422: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 7; \ + tmp |= fieldname(insn, 1, 6) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_7(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 423: \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 424: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 1; \ + tmp |= fieldname(insn, 8, 1) << 0; \ + if (!Check(&S, DecodeGPRNM2R1RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 425: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 7); \ + if (!Check(&S, DecodeImmM1To126(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 426: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 7) << 2; \ + if (!Check(&S, DecodeMemNM_9_0_Mips_GPRNMGPRegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 427: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 428: \ + tmp = fieldname(insn, 4, 1); \ + if (!Check(&S, DecodeGPRNMRARegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 429: \ + if (!Check(&S, DecodeBranchConflictNM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 430: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeUImm4Mask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 431: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 4; \ + tmp |= fieldname(insn, 3, 1) << 3; \ + tmp |= fieldname(insn, 4, 1) << 8; \ + tmp |= fieldname(insn, 8, 1) << 2; \ + if (!Check(&S, DecodeMemNM4x4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 432: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 1; \ + tmp |= fieldname(insn, 8, 1) << 0; \ + if (!Check(&S, DecodeGPRNM2R1RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 433: \ + tmp = fieldname(insn, 0, 18); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 434: \ + tmp = fieldname(insn, 0, 19); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 435: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 436: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 21; \ + tmp |= fieldname(insn, 1, 20) << 1; \ + if (!Check(&S, DecodeAddressPCRelNM_22(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 437: \ + tmp = fieldname(insn, 24, 1); \ + if (!Check(&S, DecodeGPRNM1R1RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 21, 3) << 0; \ + tmp |= fieldname(insn, 25, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 21; \ + tmp |= fieldname(insn, 1, 20) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_21(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 438: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 439: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 440: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 10); \ + if (!Check(&S, DecodeMemNMRX_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 441: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 442: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 443: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 444: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 445: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 446: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 447: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 448: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 10); \ + if (!Check(&S, DecodeCOP0SelRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 449: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 3, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 450: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 3, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 451: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 452: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 453: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 454: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 25; \ + tmp |= fieldname(insn, 1, 24) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_25(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 455: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 2, 19) << 2; \ + if (!Check(&S, DecodeUImmWithReg_21_0_1_Mips_GP_NM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 456: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 2, 19) << 2; \ + if (!Check(&S, DecodeMemNM_21_0_Mips_GPRNMGPRegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 457: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 18); \ + if (!Check(&S, DecodeMemNM_18_0_Mips_GPRNMGPRegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 458: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 18); \ + if (!Check(&S, DecodeUImmWithReg_18_0_1_Mips_GP_NM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 459: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 1, 17) << 1; \ + if (!Check(&S, DecodeMemNM_18_0_Mips_GPRNMGPRegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 460: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32NZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 461: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 462: \ + tmp = fieldname(insn, 3, 9) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + tmp |= fieldname(insn, 21, 5) << 5; \ + if (!Check(&S, DecodeNMRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 463: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, DecodeNegImm12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 464: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 465: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 7, 4) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 6, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 466: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeInsSize(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 467: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeUImmWithOffset_5_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 468: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 5) << 12; \ + if (!Check(&S, DecodeMemNM_12_0_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 469: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 5) << 12; \ + if (!Check(&S, DecodeMemNM_12_0_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 470: \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 5) << 12; \ + if (!Check(&S, DecodeMemNM_12_0_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 471: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 14; \ + tmp |= fieldname(insn, 1, 13) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_14(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 472: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 15, 6) << 8; \ + if (!Check(&S, DecodeMemNM_9_1_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 473: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 6) << 2; \ + tmp |= fieldname(insn, 15, 6) << 8; \ + if (!Check(&S, DecodeMemNM_9_1_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 474: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMemZeroNM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 475: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 15, 6) << 8; \ + if (!Check(&S, DecodeMemNM_9_1_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeUImm3Shift(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 476: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 15, 6) << 8; \ + if (!Check(&S, DecodeMemNM_9_1_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 477: \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 15, 6) << 8; \ + if (!Check(&S, DecodeMemNM_9_1_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 478: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 6) << 2; \ + tmp |= fieldname(insn, 15, 6) << 8; \ + if (!Check(&S, DecodeMemNM_9_1_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 479: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMemZeroNM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 480: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 7); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 11; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_11(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 481: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 6); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_32_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 11; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_11(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 482: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 19; \ + tmp |= fieldname(insn, 2, 10) << 9; \ + tmp |= fieldname(insn, 12, 9) << 0; \ + if (!Check(&S, DecodeSImm32s12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 483: \ + tmp = fieldname(insn, 37, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 16) << 16; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 484: \ + tmp = fieldname(insn, 37, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 37, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 16) << 16; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 485: \ + tmp = fieldname(insn, 37, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 16) << 16; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + if (!Check(&S, DecodeSImmWithReg_32_0_1_Mips_GP_NM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 486: \ + tmp = fieldname(insn, 37, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 16) << 16; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + if (!Check(&S, DecodeAddressPCRelNM_32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ - InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \ -{ \ - uint64_t Bits = getFeatureBits(feature); \ + InsnType insn, uint64_t Address, const void *Decoder) { \ const uint8_t *Ptr = DecodeTable; \ - uint32_t CurFieldValue = 0, ExpectedValue; \ + uint64_t CurFieldValue = 0; \ DecodeStatus S = MCDisassembler_Success; \ - unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ - InsnType Val, FieldValue, PositiveMask, NegativeMask; \ - bool Pred, Fail; \ - for (;;) { \ + while (true) { \ switch (*Ptr) { \ default: \ return MCDisassembler_Fail; \ case MCD_OPC_ExtractField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ + unsigned Start = *++Ptr; \ + unsigned Len = *++Ptr; \ ++Ptr; \ - CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ + CurFieldValue = fieldname(insn, Start, Len); \ break; \ } \ case MCD_OPC_FilterValue: { \ - Val = (InsnType)decodeULEB128(++Ptr, &Len); \ + /* Decode the field value. */ \ + unsigned Len; \ + uint64_t Val = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - NumToSkip = *Ptr++; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ if (Val != CurFieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - FieldValue = fieldname(insn, Start, Len); \ - ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ + unsigned Start = *++Ptr; \ + unsigned Len = *++Ptr; \ + uint64_t FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + unsigned PtrLen = 0; \ + uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen); \ + Ptr += PtrLen; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ if (ExpectedValue != FieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckPredicate: { \ - PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ + unsigned Len; \ + /* Decode the Predicate Index value. */ \ + unsigned PIdx = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - NumToSkip = *Ptr++; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ - Pred = checkDecoderPredicate(PIdx, Bits); \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + bool Pred = checkDecoderPredicate(MI, PIdx); \ if (!Pred) \ Ptr += NumToSkip; \ - (void)Pred; \ break; \ } \ case MCD_OPC_Decode: { \ - Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ + unsigned Len; \ + /* Decode the Opcode value. */ \ + unsigned Opc = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ + unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ + MCInst_clear(MI); \ MCInst_setOpcode(MI, Opc); \ - return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ + bool DecodeComplete; \ + S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + unsigned Len; \ + /* Decode the Opcode value. */ \ + unsigned Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + bool DecodeComplete; \ + S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* LLVM uses a MCInst on the stack, but for our use case, */ \ + /* it is enough for now to reset the op counter. */ \ + MCInst_clear(MI); \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ } \ case MCD_OPC_SoftFail: { \ - PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ + /* Decode the mask values. */ \ + unsigned Len; \ + uint64_t PositiveMask = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ + uint64_t NegativeMask = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ - Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; \ if (Fail) \ S = MCDisassembler_SoftFail; \ break; \ @@ -6935,8 +12118,15 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ } \ } \ } \ + /* Bogisity detected in disassembler state machine! */ \ } -FieldFromInstruction(fieldFromInstruction, uint32_t) -DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) -DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) +FieldFromInstruction(fieldFromInstruction_4, uint32_t) +FieldFromInstruction(fieldFromInstruction_2, uint32_t) +FieldFromInstruction(fieldFromInstruction_8, uint64_t) +DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) +DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint32_t) +DecodeToMCInst(decodeToMCInst_8, fieldFromInstruction_8, uint64_t) +DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) +DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint32_t) +DecodeInstruction(decodeInstruction_8, fieldFromInstruction_8, decodeToMCInst_8, uint64_t) diff --git a/arch/Mips/MipsGenInstrInfo.inc b/arch/Mips/MipsGenInstrInfo.inc index b6e8983ed..d4913e6b9 100644 --- a/arch/Mips/MipsGenInstrInfo.inc +++ b/arch/Mips/MipsGenInstrInfo.inc @@ -1,1805 +1,7478 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Target Instruction Enum Values *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM -enum { + enum { Mips_PHI = 0, Mips_INLINEASM = 1, - Mips_CFI_INSTRUCTION = 2, - Mips_EH_LABEL = 3, - Mips_GC_LABEL = 4, - Mips_KILL = 5, - Mips_EXTRACT_SUBREG = 6, - Mips_INSERT_SUBREG = 7, - Mips_IMPLICIT_DEF = 8, - Mips_SUBREG_TO_REG = 9, - Mips_COPY_TO_REGCLASS = 10, - Mips_DBG_VALUE = 11, - Mips_REG_SEQUENCE = 12, - Mips_COPY = 13, - Mips_BUNDLE = 14, - Mips_LIFETIME_START = 15, - Mips_LIFETIME_END = 16, - Mips_STACKMAP = 17, - Mips_PATCHPOINT = 18, - Mips_LOAD_STACK_GUARD = 19, - Mips_STATEPOINT = 20, - Mips_FRAME_ALLOC = 21, - Mips_ABSQ_S_PH = 22, - Mips_ABSQ_S_QB = 23, - Mips_ABSQ_S_W = 24, - Mips_ADD = 25, - Mips_ADDIUPC = 26, - Mips_ADDIUPC_MM = 27, - Mips_ADDIUR1SP_MM = 28, - Mips_ADDIUR2_MM = 29, - Mips_ADDIUS5_MM = 30, - Mips_ADDIUSP_MM = 31, - Mips_ADDQH_PH = 32, - Mips_ADDQH_R_PH = 33, - Mips_ADDQH_R_W = 34, - Mips_ADDQH_W = 35, - Mips_ADDQ_PH = 36, - Mips_ADDQ_S_PH = 37, - Mips_ADDQ_S_W = 38, - Mips_ADDSC = 39, - Mips_ADDS_A_B = 40, - Mips_ADDS_A_D = 41, - Mips_ADDS_A_H = 42, - Mips_ADDS_A_W = 43, - Mips_ADDS_S_B = 44, - Mips_ADDS_S_D = 45, - Mips_ADDS_S_H = 46, - Mips_ADDS_S_W = 47, - Mips_ADDS_U_B = 48, - Mips_ADDS_U_D = 49, - Mips_ADDS_U_H = 50, - Mips_ADDS_U_W = 51, - Mips_ADDU16_MM = 52, - Mips_ADDUH_QB = 53, - Mips_ADDUH_R_QB = 54, - Mips_ADDU_PH = 55, - Mips_ADDU_QB = 56, - Mips_ADDU_S_PH = 57, - Mips_ADDU_S_QB = 58, - Mips_ADDVI_B = 59, - Mips_ADDVI_D = 60, - Mips_ADDVI_H = 61, - Mips_ADDVI_W = 62, - Mips_ADDV_B = 63, - Mips_ADDV_D = 64, - Mips_ADDV_H = 65, - Mips_ADDV_W = 66, - Mips_ADDWC = 67, - Mips_ADD_A_B = 68, - Mips_ADD_A_D = 69, - Mips_ADD_A_H = 70, - Mips_ADD_A_W = 71, - Mips_ADD_MM = 72, - Mips_ADDi = 73, - Mips_ADDi_MM = 74, - Mips_ADDiu = 75, - Mips_ADDiu_MM = 76, - Mips_ADDu = 77, - Mips_ADDu_MM = 78, - Mips_ADJCALLSTACKDOWN = 79, - Mips_ADJCALLSTACKUP = 80, - Mips_ALIGN = 81, - Mips_ALUIPC = 82, - Mips_AND = 83, - Mips_AND16_MM = 84, - Mips_AND64 = 85, - Mips_ANDI16_MM = 86, - Mips_ANDI_B = 87, - Mips_AND_MM = 88, - Mips_AND_V = 89, - Mips_AND_V_D_PSEUDO = 90, - Mips_AND_V_H_PSEUDO = 91, - Mips_AND_V_W_PSEUDO = 92, - Mips_ANDi = 93, - Mips_ANDi64 = 94, - Mips_ANDi_MM = 95, - Mips_APPEND = 96, - Mips_ASUB_S_B = 97, - Mips_ASUB_S_D = 98, - Mips_ASUB_S_H = 99, - Mips_ASUB_S_W = 100, - Mips_ASUB_U_B = 101, - Mips_ASUB_U_D = 102, - Mips_ASUB_U_H = 103, - Mips_ASUB_U_W = 104, - Mips_ATOMIC_CMP_SWAP_I16 = 105, - Mips_ATOMIC_CMP_SWAP_I32 = 106, - Mips_ATOMIC_CMP_SWAP_I64 = 107, - Mips_ATOMIC_CMP_SWAP_I8 = 108, - Mips_ATOMIC_LOAD_ADD_I16 = 109, - Mips_ATOMIC_LOAD_ADD_I32 = 110, - Mips_ATOMIC_LOAD_ADD_I64 = 111, - Mips_ATOMIC_LOAD_ADD_I8 = 112, - Mips_ATOMIC_LOAD_AND_I16 = 113, - Mips_ATOMIC_LOAD_AND_I32 = 114, - Mips_ATOMIC_LOAD_AND_I64 = 115, - Mips_ATOMIC_LOAD_AND_I8 = 116, - Mips_ATOMIC_LOAD_NAND_I16 = 117, - Mips_ATOMIC_LOAD_NAND_I32 = 118, - Mips_ATOMIC_LOAD_NAND_I64 = 119, - Mips_ATOMIC_LOAD_NAND_I8 = 120, - Mips_ATOMIC_LOAD_OR_I16 = 121, - Mips_ATOMIC_LOAD_OR_I32 = 122, - Mips_ATOMIC_LOAD_OR_I64 = 123, - Mips_ATOMIC_LOAD_OR_I8 = 124, - Mips_ATOMIC_LOAD_SUB_I16 = 125, - Mips_ATOMIC_LOAD_SUB_I32 = 126, - Mips_ATOMIC_LOAD_SUB_I64 = 127, - Mips_ATOMIC_LOAD_SUB_I8 = 128, - Mips_ATOMIC_LOAD_XOR_I16 = 129, - Mips_ATOMIC_LOAD_XOR_I32 = 130, - Mips_ATOMIC_LOAD_XOR_I64 = 131, - Mips_ATOMIC_LOAD_XOR_I8 = 132, - Mips_ATOMIC_SWAP_I16 = 133, - Mips_ATOMIC_SWAP_I32 = 134, - Mips_ATOMIC_SWAP_I64 = 135, - Mips_ATOMIC_SWAP_I8 = 136, - Mips_AUI = 137, - Mips_AUIPC = 138, - Mips_AVER_S_B = 139, - Mips_AVER_S_D = 140, - Mips_AVER_S_H = 141, - Mips_AVER_S_W = 142, - Mips_AVER_U_B = 143, - Mips_AVER_U_D = 144, - Mips_AVER_U_H = 145, - Mips_AVER_U_W = 146, - Mips_AVE_S_B = 147, - Mips_AVE_S_D = 148, - Mips_AVE_S_H = 149, - Mips_AVE_S_W = 150, - Mips_AVE_U_B = 151, - Mips_AVE_U_D = 152, - Mips_AVE_U_H = 153, - Mips_AVE_U_W = 154, - Mips_AddiuRxImmX16 = 155, - Mips_AddiuRxPcImmX16 = 156, - Mips_AddiuRxRxImm16 = 157, - Mips_AddiuRxRxImmX16 = 158, - Mips_AddiuRxRyOffMemX16 = 159, - Mips_AddiuSpImm16 = 160, - Mips_AddiuSpImmX16 = 161, - Mips_AdduRxRyRz16 = 162, - Mips_AndRxRxRy16 = 163, - Mips_B = 164, - Mips_B16_MM = 165, - Mips_BADDu = 166, - Mips_BAL = 167, - Mips_BALC = 168, - Mips_BALIGN = 169, - Mips_BAL_BR = 170, - Mips_BBIT0 = 171, - Mips_BBIT032 = 172, - Mips_BBIT1 = 173, - Mips_BBIT132 = 174, - Mips_BC = 175, - Mips_BC0F = 176, - Mips_BC0FL = 177, - Mips_BC0T = 178, - Mips_BC0TL = 179, - Mips_BC1EQZ = 180, - Mips_BC1F = 181, - Mips_BC1FL = 182, - Mips_BC1F_MM = 183, - Mips_BC1NEZ = 184, - Mips_BC1T = 185, - Mips_BC1TL = 186, - Mips_BC1T_MM = 187, - Mips_BC2EQZ = 188, - Mips_BC2F = 189, - Mips_BC2FL = 190, - Mips_BC2NEZ = 191, - Mips_BC2T = 192, - Mips_BC2TL = 193, - Mips_BC3F = 194, - Mips_BC3FL = 195, - Mips_BC3T = 196, - Mips_BC3TL = 197, - Mips_BCLRI_B = 198, - Mips_BCLRI_D = 199, - Mips_BCLRI_H = 200, - Mips_BCLRI_W = 201, - Mips_BCLR_B = 202, - Mips_BCLR_D = 203, - Mips_BCLR_H = 204, - Mips_BCLR_W = 205, - Mips_BEQ = 206, - Mips_BEQ64 = 207, - Mips_BEQC = 208, - Mips_BEQL = 209, - Mips_BEQZ16_MM = 210, - Mips_BEQZALC = 211, - Mips_BEQZC = 212, - Mips_BEQZC_MM = 213, - Mips_BEQ_MM = 214, - Mips_BGEC = 215, - Mips_BGEUC = 216, - Mips_BGEZ = 217, - Mips_BGEZ64 = 218, - Mips_BGEZAL = 219, - Mips_BGEZALC = 220, - Mips_BGEZALL = 221, - Mips_BGEZALS_MM = 222, - Mips_BGEZAL_MM = 223, - Mips_BGEZC = 224, - Mips_BGEZL = 225, - Mips_BGEZ_MM = 226, - Mips_BGTZ = 227, - Mips_BGTZ64 = 228, - Mips_BGTZALC = 229, - Mips_BGTZC = 230, - Mips_BGTZL = 231, - Mips_BGTZ_MM = 232, - Mips_BINSLI_B = 233, - Mips_BINSLI_D = 234, - Mips_BINSLI_H = 235, - Mips_BINSLI_W = 236, - Mips_BINSL_B = 237, - Mips_BINSL_D = 238, - Mips_BINSL_H = 239, - Mips_BINSL_W = 240, - Mips_BINSRI_B = 241, - Mips_BINSRI_D = 242, - Mips_BINSRI_H = 243, - Mips_BINSRI_W = 244, - Mips_BINSR_B = 245, - Mips_BINSR_D = 246, - Mips_BINSR_H = 247, - Mips_BINSR_W = 248, - Mips_BITREV = 249, - Mips_BITSWAP = 250, - Mips_BLEZ = 251, - Mips_BLEZ64 = 252, - Mips_BLEZALC = 253, - Mips_BLEZC = 254, - Mips_BLEZL = 255, - Mips_BLEZ_MM = 256, - Mips_BLTC = 257, - Mips_BLTUC = 258, - Mips_BLTZ = 259, - Mips_BLTZ64 = 260, - Mips_BLTZAL = 261, - Mips_BLTZALC = 262, - Mips_BLTZALL = 263, - Mips_BLTZALS_MM = 264, - Mips_BLTZAL_MM = 265, - Mips_BLTZC = 266, - Mips_BLTZL = 267, - Mips_BLTZ_MM = 268, - Mips_BMNZI_B = 269, - Mips_BMNZ_V = 270, - Mips_BMZI_B = 271, - Mips_BMZ_V = 272, - Mips_BNE = 273, - Mips_BNE64 = 274, - Mips_BNEC = 275, - Mips_BNEGI_B = 276, - Mips_BNEGI_D = 277, - Mips_BNEGI_H = 278, - Mips_BNEGI_W = 279, - Mips_BNEG_B = 280, - Mips_BNEG_D = 281, - Mips_BNEG_H = 282, - Mips_BNEG_W = 283, - Mips_BNEL = 284, - Mips_BNEZ16_MM = 285, - Mips_BNEZALC = 286, - Mips_BNEZC = 287, - Mips_BNEZC_MM = 288, - Mips_BNE_MM = 289, - Mips_BNVC = 290, - Mips_BNZ_B = 291, - Mips_BNZ_D = 292, - Mips_BNZ_H = 293, - Mips_BNZ_V = 294, - Mips_BNZ_W = 295, - Mips_BOVC = 296, - Mips_BPOSGE32 = 297, - Mips_BPOSGE32_PSEUDO = 298, - Mips_BREAK = 299, - Mips_BREAK16_MM = 300, - Mips_BREAK_MM = 301, - Mips_BSELI_B = 302, - Mips_BSEL_D_PSEUDO = 303, - Mips_BSEL_FD_PSEUDO = 304, - Mips_BSEL_FW_PSEUDO = 305, - Mips_BSEL_H_PSEUDO = 306, - Mips_BSEL_V = 307, - Mips_BSEL_W_PSEUDO = 308, - Mips_BSETI_B = 309, - Mips_BSETI_D = 310, - Mips_BSETI_H = 311, - Mips_BSETI_W = 312, - Mips_BSET_B = 313, - Mips_BSET_D = 314, - Mips_BSET_H = 315, - Mips_BSET_W = 316, - Mips_BZ_B = 317, - Mips_BZ_D = 318, - Mips_BZ_H = 319, - Mips_BZ_V = 320, - Mips_BZ_W = 321, - Mips_B_MM_Pseudo = 322, - Mips_BeqzRxImm16 = 323, - Mips_BeqzRxImmX16 = 324, - Mips_Bimm16 = 325, - Mips_BimmX16 = 326, - Mips_BnezRxImm16 = 327, - Mips_BnezRxImmX16 = 328, - Mips_Break16 = 329, - Mips_Bteqz16 = 330, - Mips_BteqzT8CmpX16 = 331, - Mips_BteqzT8CmpiX16 = 332, - Mips_BteqzT8SltX16 = 333, - Mips_BteqzT8SltiX16 = 334, - Mips_BteqzT8SltiuX16 = 335, - Mips_BteqzT8SltuX16 = 336, - Mips_BteqzX16 = 337, - Mips_Btnez16 = 338, - Mips_BtnezT8CmpX16 = 339, - Mips_BtnezT8CmpiX16 = 340, - Mips_BtnezT8SltX16 = 341, - Mips_BtnezT8SltiX16 = 342, - Mips_BtnezT8SltiuX16 = 343, - Mips_BtnezT8SltuX16 = 344, - Mips_BtnezX16 = 345, - Mips_BuildPairF64 = 346, - Mips_BuildPairF64_64 = 347, - Mips_CACHE = 348, - Mips_CACHE_MM = 349, - Mips_CACHE_R6 = 350, - Mips_CEIL_L_D64 = 351, - Mips_CEIL_L_S = 352, - Mips_CEIL_W_D32 = 353, - Mips_CEIL_W_D64 = 354, - Mips_CEIL_W_MM = 355, - Mips_CEIL_W_S = 356, - Mips_CEIL_W_S_MM = 357, - Mips_CEQI_B = 358, - Mips_CEQI_D = 359, - Mips_CEQI_H = 360, - Mips_CEQI_W = 361, - Mips_CEQ_B = 362, - Mips_CEQ_D = 363, - Mips_CEQ_H = 364, - Mips_CEQ_W = 365, - Mips_CFC1 = 366, - Mips_CFC1_MM = 367, - Mips_CFCMSA = 368, - Mips_CINS = 369, - Mips_CINS32 = 370, - Mips_CLASS_D = 371, - Mips_CLASS_S = 372, - Mips_CLEI_S_B = 373, - Mips_CLEI_S_D = 374, - Mips_CLEI_S_H = 375, - Mips_CLEI_S_W = 376, - Mips_CLEI_U_B = 377, - Mips_CLEI_U_D = 378, - Mips_CLEI_U_H = 379, - Mips_CLEI_U_W = 380, - Mips_CLE_S_B = 381, - Mips_CLE_S_D = 382, - Mips_CLE_S_H = 383, - Mips_CLE_S_W = 384, - Mips_CLE_U_B = 385, - Mips_CLE_U_D = 386, - Mips_CLE_U_H = 387, - Mips_CLE_U_W = 388, - Mips_CLO = 389, - Mips_CLO_MM = 390, - Mips_CLO_R6 = 391, - Mips_CLTI_S_B = 392, - Mips_CLTI_S_D = 393, - Mips_CLTI_S_H = 394, - Mips_CLTI_S_W = 395, - Mips_CLTI_U_B = 396, - Mips_CLTI_U_D = 397, - Mips_CLTI_U_H = 398, - Mips_CLTI_U_W = 399, - Mips_CLT_S_B = 400, - Mips_CLT_S_D = 401, - Mips_CLT_S_H = 402, - Mips_CLT_S_W = 403, - Mips_CLT_U_B = 404, - Mips_CLT_U_D = 405, - Mips_CLT_U_H = 406, - Mips_CLT_U_W = 407, - Mips_CLZ = 408, - Mips_CLZ_MM = 409, - Mips_CLZ_R6 = 410, - Mips_CMPGDU_EQ_QB = 411, - Mips_CMPGDU_LE_QB = 412, - Mips_CMPGDU_LT_QB = 413, - Mips_CMPGU_EQ_QB = 414, - Mips_CMPGU_LE_QB = 415, - Mips_CMPGU_LT_QB = 416, - Mips_CMPU_EQ_QB = 417, - Mips_CMPU_LE_QB = 418, - Mips_CMPU_LT_QB = 419, - Mips_CMP_EQ_D = 420, - Mips_CMP_EQ_PH = 421, - Mips_CMP_EQ_S = 422, - Mips_CMP_F_D = 423, - Mips_CMP_F_S = 424, - Mips_CMP_LE_D = 425, - Mips_CMP_LE_PH = 426, - Mips_CMP_LE_S = 427, - Mips_CMP_LT_D = 428, - Mips_CMP_LT_PH = 429, - Mips_CMP_LT_S = 430, - Mips_CMP_SAF_D = 431, - Mips_CMP_SAF_S = 432, - Mips_CMP_SEQ_D = 433, - Mips_CMP_SEQ_S = 434, - Mips_CMP_SLE_D = 435, - Mips_CMP_SLE_S = 436, - Mips_CMP_SLT_D = 437, - Mips_CMP_SLT_S = 438, - Mips_CMP_SUEQ_D = 439, - Mips_CMP_SUEQ_S = 440, - Mips_CMP_SULE_D = 441, - Mips_CMP_SULE_S = 442, - Mips_CMP_SULT_D = 443, - Mips_CMP_SULT_S = 444, - Mips_CMP_SUN_D = 445, - Mips_CMP_SUN_S = 446, - Mips_CMP_UEQ_D = 447, - Mips_CMP_UEQ_S = 448, - Mips_CMP_ULE_D = 449, - Mips_CMP_ULE_S = 450, - Mips_CMP_ULT_D = 451, - Mips_CMP_ULT_S = 452, - Mips_CMP_UN_D = 453, - Mips_CMP_UN_S = 454, - Mips_CONSTPOOL_ENTRY = 455, - Mips_COPY_FD_PSEUDO = 456, - Mips_COPY_FW_PSEUDO = 457, - Mips_COPY_S_B = 458, - Mips_COPY_S_D = 459, - Mips_COPY_S_H = 460, - Mips_COPY_S_W = 461, - Mips_COPY_U_B = 462, - Mips_COPY_U_D = 463, - Mips_COPY_U_H = 464, - Mips_COPY_U_W = 465, - Mips_CTC1 = 466, - Mips_CTC1_MM = 467, - Mips_CTCMSA = 468, - Mips_CVT_D32_S = 469, - Mips_CVT_D32_W = 470, - Mips_CVT_D32_W_MM = 471, - Mips_CVT_D64_L = 472, - Mips_CVT_D64_S = 473, - Mips_CVT_D64_W = 474, - Mips_CVT_D_S_MM = 475, - Mips_CVT_L_D64 = 476, - Mips_CVT_L_D64_MM = 477, - Mips_CVT_L_S = 478, - Mips_CVT_L_S_MM = 479, - Mips_CVT_S_D32 = 480, - Mips_CVT_S_D32_MM = 481, - Mips_CVT_S_D64 = 482, - Mips_CVT_S_L = 483, - Mips_CVT_S_W = 484, - Mips_CVT_S_W_MM = 485, - Mips_CVT_W_D32 = 486, - Mips_CVT_W_D64 = 487, - Mips_CVT_W_MM = 488, - Mips_CVT_W_S = 489, - Mips_CVT_W_S_MM = 490, - Mips_C_EQ_D32 = 491, - Mips_C_EQ_D64 = 492, - Mips_C_EQ_S = 493, - Mips_C_F_D32 = 494, - Mips_C_F_D64 = 495, - Mips_C_F_S = 496, - Mips_C_LE_D32 = 497, - Mips_C_LE_D64 = 498, - Mips_C_LE_S = 499, - Mips_C_LT_D32 = 500, - Mips_C_LT_D64 = 501, - Mips_C_LT_S = 502, - Mips_C_NGE_D32 = 503, - Mips_C_NGE_D64 = 504, - Mips_C_NGE_S = 505, - Mips_C_NGLE_D32 = 506, - Mips_C_NGLE_D64 = 507, - Mips_C_NGLE_S = 508, - Mips_C_NGL_D32 = 509, - Mips_C_NGL_D64 = 510, - Mips_C_NGL_S = 511, - Mips_C_NGT_D32 = 512, - Mips_C_NGT_D64 = 513, - Mips_C_NGT_S = 514, - Mips_C_OLE_D32 = 515, - Mips_C_OLE_D64 = 516, - Mips_C_OLE_S = 517, - Mips_C_OLT_D32 = 518, - Mips_C_OLT_D64 = 519, - Mips_C_OLT_S = 520, - Mips_C_SEQ_D32 = 521, - Mips_C_SEQ_D64 = 522, - Mips_C_SEQ_S = 523, - Mips_C_SF_D32 = 524, - Mips_C_SF_D64 = 525, - Mips_C_SF_S = 526, - Mips_C_UEQ_D32 = 527, - Mips_C_UEQ_D64 = 528, - Mips_C_UEQ_S = 529, - Mips_C_ULE_D32 = 530, - Mips_C_ULE_D64 = 531, - Mips_C_ULE_S = 532, - Mips_C_ULT_D32 = 533, - Mips_C_ULT_D64 = 534, - Mips_C_ULT_S = 535, - Mips_C_UN_D32 = 536, - Mips_C_UN_D64 = 537, - Mips_C_UN_S = 538, - Mips_CmpRxRy16 = 539, - Mips_CmpiRxImm16 = 540, - Mips_CmpiRxImmX16 = 541, - Mips_Constant32 = 542, - Mips_DADD = 543, - Mips_DADDi = 544, - Mips_DADDiu = 545, - Mips_DADDu = 546, - Mips_DAHI = 547, - Mips_DALIGN = 548, - Mips_DATI = 549, - Mips_DAUI = 550, - Mips_DBITSWAP = 551, - Mips_DCLO = 552, - Mips_DCLO_R6 = 553, - Mips_DCLZ = 554, - Mips_DCLZ_R6 = 555, - Mips_DDIV = 556, - Mips_DDIVU = 557, - Mips_DERET = 558, - Mips_DERET_MM = 559, - Mips_DEXT = 560, - Mips_DEXTM = 561, - Mips_DEXTU = 562, - Mips_DI = 563, - Mips_DINS = 564, - Mips_DINSM = 565, - Mips_DINSU = 566, - Mips_DIV = 567, - Mips_DIVU = 568, - Mips_DIV_S_B = 569, - Mips_DIV_S_D = 570, - Mips_DIV_S_H = 571, - Mips_DIV_S_W = 572, - Mips_DIV_U_B = 573, - Mips_DIV_U_D = 574, - Mips_DIV_U_H = 575, - Mips_DIV_U_W = 576, - Mips_DI_MM = 577, - Mips_DLSA = 578, - Mips_DLSA_R6 = 579, - Mips_DMFC0 = 580, - Mips_DMFC1 = 581, - Mips_DMFC2 = 582, - Mips_DMOD = 583, - Mips_DMODU = 584, - Mips_DMTC0 = 585, - Mips_DMTC1 = 586, - Mips_DMTC2 = 587, - Mips_DMUH = 588, - Mips_DMUHU = 589, - Mips_DMUL = 590, - Mips_DMULT = 591, - Mips_DMULTu = 592, - Mips_DMULU = 593, - Mips_DMUL_R6 = 594, - Mips_DOTP_S_D = 595, - Mips_DOTP_S_H = 596, - Mips_DOTP_S_W = 597, - Mips_DOTP_U_D = 598, - Mips_DOTP_U_H = 599, - Mips_DOTP_U_W = 600, - Mips_DPADD_S_D = 601, - Mips_DPADD_S_H = 602, - Mips_DPADD_S_W = 603, - Mips_DPADD_U_D = 604, - Mips_DPADD_U_H = 605, - Mips_DPADD_U_W = 606, - Mips_DPAQX_SA_W_PH = 607, - Mips_DPAQX_S_W_PH = 608, - Mips_DPAQ_SA_L_W = 609, - Mips_DPAQ_S_W_PH = 610, - Mips_DPAU_H_QBL = 611, - Mips_DPAU_H_QBR = 612, - Mips_DPAX_W_PH = 613, - Mips_DPA_W_PH = 614, - Mips_DPOP = 615, - Mips_DPSQX_SA_W_PH = 616, - Mips_DPSQX_S_W_PH = 617, - Mips_DPSQ_SA_L_W = 618, - Mips_DPSQ_S_W_PH = 619, - Mips_DPSUB_S_D = 620, - Mips_DPSUB_S_H = 621, - Mips_DPSUB_S_W = 622, - Mips_DPSUB_U_D = 623, - Mips_DPSUB_U_H = 624, - Mips_DPSUB_U_W = 625, - Mips_DPSU_H_QBL = 626, - Mips_DPSU_H_QBR = 627, - Mips_DPSX_W_PH = 628, - Mips_DPS_W_PH = 629, - Mips_DROTR = 630, - Mips_DROTR32 = 631, - Mips_DROTRV = 632, - Mips_DSBH = 633, - Mips_DSDIV = 634, - Mips_DSHD = 635, - Mips_DSLL = 636, - Mips_DSLL32 = 637, - Mips_DSLL64_32 = 638, - Mips_DSLLV = 639, - Mips_DSRA = 640, - Mips_DSRA32 = 641, - Mips_DSRAV = 642, - Mips_DSRL = 643, - Mips_DSRL32 = 644, - Mips_DSRLV = 645, - Mips_DSUB = 646, - Mips_DSUBu = 647, - Mips_DUDIV = 648, - Mips_DivRxRy16 = 649, - Mips_DivuRxRy16 = 650, - Mips_EHB = 651, - Mips_EHB_MM = 652, - Mips_EI = 653, - Mips_EI_MM = 654, - Mips_ERET = 655, - Mips_ERET_MM = 656, - Mips_EXT = 657, - Mips_EXTP = 658, - Mips_EXTPDP = 659, - Mips_EXTPDPV = 660, - Mips_EXTPV = 661, - Mips_EXTRV_RS_W = 662, - Mips_EXTRV_R_W = 663, - Mips_EXTRV_S_H = 664, - Mips_EXTRV_W = 665, - Mips_EXTR_RS_W = 666, - Mips_EXTR_R_W = 667, - Mips_EXTR_S_H = 668, - Mips_EXTR_W = 669, - Mips_EXTS = 670, - Mips_EXTS32 = 671, - Mips_EXT_MM = 672, - Mips_ExtractElementF64 = 673, - Mips_ExtractElementF64_64 = 674, - Mips_FABS_D = 675, - Mips_FABS_D32 = 676, - Mips_FABS_D64 = 677, - Mips_FABS_MM = 678, - Mips_FABS_S = 679, - Mips_FABS_S_MM = 680, - Mips_FABS_W = 681, - Mips_FADD_D = 682, - Mips_FADD_D32 = 683, - Mips_FADD_D64 = 684, - Mips_FADD_MM = 685, - Mips_FADD_S = 686, - Mips_FADD_S_MM = 687, - Mips_FADD_W = 688, - Mips_FCAF_D = 689, - Mips_FCAF_W = 690, - Mips_FCEQ_D = 691, - Mips_FCEQ_W = 692, - Mips_FCLASS_D = 693, - Mips_FCLASS_W = 694, - Mips_FCLE_D = 695, - Mips_FCLE_W = 696, - Mips_FCLT_D = 697, - Mips_FCLT_W = 698, - Mips_FCMP_D32 = 699, - Mips_FCMP_D32_MM = 700, - Mips_FCMP_D64 = 701, - Mips_FCMP_S32 = 702, - Mips_FCMP_S32_MM = 703, - Mips_FCNE_D = 704, - Mips_FCNE_W = 705, - Mips_FCOR_D = 706, - Mips_FCOR_W = 707, - Mips_FCUEQ_D = 708, - Mips_FCUEQ_W = 709, - Mips_FCULE_D = 710, - Mips_FCULE_W = 711, - Mips_FCULT_D = 712, - Mips_FCULT_W = 713, - Mips_FCUNE_D = 714, - Mips_FCUNE_W = 715, - Mips_FCUN_D = 716, - Mips_FCUN_W = 717, - Mips_FDIV_D = 718, - Mips_FDIV_D32 = 719, - Mips_FDIV_D64 = 720, - Mips_FDIV_MM = 721, - Mips_FDIV_S = 722, - Mips_FDIV_S_MM = 723, - Mips_FDIV_W = 724, - Mips_FEXDO_H = 725, - Mips_FEXDO_W = 726, - Mips_FEXP2_D = 727, - Mips_FEXP2_D_1_PSEUDO = 728, - Mips_FEXP2_W = 729, - Mips_FEXP2_W_1_PSEUDO = 730, - Mips_FEXUPL_D = 731, - Mips_FEXUPL_W = 732, - Mips_FEXUPR_D = 733, - Mips_FEXUPR_W = 734, - Mips_FFINT_S_D = 735, - Mips_FFINT_S_W = 736, - Mips_FFINT_U_D = 737, - Mips_FFINT_U_W = 738, - Mips_FFQL_D = 739, - Mips_FFQL_W = 740, - Mips_FFQR_D = 741, - Mips_FFQR_W = 742, - Mips_FILL_B = 743, - Mips_FILL_D = 744, - Mips_FILL_FD_PSEUDO = 745, - Mips_FILL_FW_PSEUDO = 746, - Mips_FILL_H = 747, - Mips_FILL_W = 748, - Mips_FLOG2_D = 749, - Mips_FLOG2_W = 750, - Mips_FLOOR_L_D64 = 751, - Mips_FLOOR_L_S = 752, - Mips_FLOOR_W_D32 = 753, - Mips_FLOOR_W_D64 = 754, - Mips_FLOOR_W_MM = 755, - Mips_FLOOR_W_S = 756, - Mips_FLOOR_W_S_MM = 757, - Mips_FMADD_D = 758, - Mips_FMADD_W = 759, - Mips_FMAX_A_D = 760, - Mips_FMAX_A_W = 761, - Mips_FMAX_D = 762, - Mips_FMAX_W = 763, - Mips_FMIN_A_D = 764, - Mips_FMIN_A_W = 765, - Mips_FMIN_D = 766, - Mips_FMIN_W = 767, - Mips_FMOV_D32 = 768, - Mips_FMOV_D32_MM = 769, - Mips_FMOV_D64 = 770, - Mips_FMOV_S = 771, - Mips_FMOV_S_MM = 772, - Mips_FMSUB_D = 773, - Mips_FMSUB_W = 774, - Mips_FMUL_D = 775, - Mips_FMUL_D32 = 776, - Mips_FMUL_D64 = 777, - Mips_FMUL_MM = 778, - Mips_FMUL_S = 779, - Mips_FMUL_S_MM = 780, - Mips_FMUL_W = 781, - Mips_FNEG_D32 = 782, - Mips_FNEG_D64 = 783, - Mips_FNEG_MM = 784, - Mips_FNEG_S = 785, - Mips_FNEG_S_MM = 786, - Mips_FRCP_D = 787, - Mips_FRCP_W = 788, - Mips_FRINT_D = 789, - Mips_FRINT_W = 790, - Mips_FRSQRT_D = 791, - Mips_FRSQRT_W = 792, - Mips_FSAF_D = 793, - Mips_FSAF_W = 794, - Mips_FSEQ_D = 795, - Mips_FSEQ_W = 796, - Mips_FSLE_D = 797, - Mips_FSLE_W = 798, - Mips_FSLT_D = 799, - Mips_FSLT_W = 800, - Mips_FSNE_D = 801, - Mips_FSNE_W = 802, - Mips_FSOR_D = 803, - Mips_FSOR_W = 804, - Mips_FSQRT_D = 805, - Mips_FSQRT_D32 = 806, - Mips_FSQRT_D64 = 807, - Mips_FSQRT_MM = 808, - Mips_FSQRT_S = 809, - Mips_FSQRT_S_MM = 810, - Mips_FSQRT_W = 811, - Mips_FSUB_D = 812, - Mips_FSUB_D32 = 813, - Mips_FSUB_D64 = 814, - Mips_FSUB_MM = 815, - Mips_FSUB_S = 816, - Mips_FSUB_S_MM = 817, - Mips_FSUB_W = 818, - Mips_FSUEQ_D = 819, - Mips_FSUEQ_W = 820, - Mips_FSULE_D = 821, - Mips_FSULE_W = 822, - Mips_FSULT_D = 823, - Mips_FSULT_W = 824, - Mips_FSUNE_D = 825, - Mips_FSUNE_W = 826, - Mips_FSUN_D = 827, - Mips_FSUN_W = 828, - Mips_FTINT_S_D = 829, - Mips_FTINT_S_W = 830, - Mips_FTINT_U_D = 831, - Mips_FTINT_U_W = 832, - Mips_FTQ_H = 833, - Mips_FTQ_W = 834, - Mips_FTRUNC_S_D = 835, - Mips_FTRUNC_S_W = 836, - Mips_FTRUNC_U_D = 837, - Mips_FTRUNC_U_W = 838, - Mips_GotPrologue16 = 839, - Mips_HADD_S_D = 840, - Mips_HADD_S_H = 841, - Mips_HADD_S_W = 842, - Mips_HADD_U_D = 843, - Mips_HADD_U_H = 844, - Mips_HADD_U_W = 845, - Mips_HSUB_S_D = 846, - Mips_HSUB_S_H = 847, - Mips_HSUB_S_W = 848, - Mips_HSUB_U_D = 849, - Mips_HSUB_U_H = 850, - Mips_HSUB_U_W = 851, - Mips_ILVEV_B = 852, - Mips_ILVEV_D = 853, - Mips_ILVEV_H = 854, - Mips_ILVEV_W = 855, - Mips_ILVL_B = 856, - Mips_ILVL_D = 857, - Mips_ILVL_H = 858, - Mips_ILVL_W = 859, - Mips_ILVOD_B = 860, - Mips_ILVOD_D = 861, - Mips_ILVOD_H = 862, - Mips_ILVOD_W = 863, - Mips_ILVR_B = 864, - Mips_ILVR_D = 865, - Mips_ILVR_H = 866, - Mips_ILVR_W = 867, - Mips_INS = 868, - Mips_INSERT_B = 869, - Mips_INSERT_B_VIDX_PSEUDO = 870, - Mips_INSERT_D = 871, - Mips_INSERT_D_VIDX_PSEUDO = 872, - Mips_INSERT_FD_PSEUDO = 873, - Mips_INSERT_FD_VIDX_PSEUDO = 874, - Mips_INSERT_FW_PSEUDO = 875, - Mips_INSERT_FW_VIDX_PSEUDO = 876, - Mips_INSERT_H = 877, - Mips_INSERT_H_VIDX_PSEUDO = 878, - Mips_INSERT_W = 879, - Mips_INSERT_W_VIDX_PSEUDO = 880, - Mips_INSV = 881, - Mips_INSVE_B = 882, - Mips_INSVE_D = 883, - Mips_INSVE_H = 884, - Mips_INSVE_W = 885, - Mips_INS_MM = 886, - Mips_J = 887, - Mips_JAL = 888, - Mips_JALR = 889, - Mips_JALR16_MM = 890, - Mips_JALR64 = 891, - Mips_JALR64Pseudo = 892, - Mips_JALRPseudo = 893, - Mips_JALRS16_MM = 894, - Mips_JALRS_MM = 895, - Mips_JALR_HB = 896, - Mips_JALR_MM = 897, - Mips_JALS_MM = 898, - Mips_JALX = 899, - Mips_JALX_MM = 900, - Mips_JAL_MM = 901, - Mips_JIALC = 902, - Mips_JIC = 903, - Mips_JR = 904, - Mips_JR16_MM = 905, - Mips_JR64 = 906, - Mips_JRADDIUSP = 907, - Mips_JRC16_MM = 908, - Mips_JR_HB = 909, - Mips_JR_HB_R6 = 910, - Mips_JR_MM = 911, - Mips_J_MM = 912, - Mips_Jal16 = 913, - Mips_JalB16 = 914, - Mips_JalOneReg = 915, - Mips_JalTwoReg = 916, - Mips_JrRa16 = 917, - Mips_JrcRa16 = 918, - Mips_JrcRx16 = 919, - Mips_JumpLinkReg16 = 920, - Mips_LB = 921, - Mips_LB64 = 922, - Mips_LBU16_MM = 923, - Mips_LBUX = 924, - Mips_LB_MM = 925, - Mips_LBu = 926, - Mips_LBu64 = 927, - Mips_LBu_MM = 928, - Mips_LD = 929, - Mips_LDC1 = 930, - Mips_LDC164 = 931, - Mips_LDC1_MM = 932, - Mips_LDC2 = 933, - Mips_LDC2_R6 = 934, - Mips_LDC3 = 935, - Mips_LDI_B = 936, - Mips_LDI_D = 937, - Mips_LDI_H = 938, - Mips_LDI_W = 939, - Mips_LDL = 940, - Mips_LDPC = 941, - Mips_LDR = 942, - Mips_LDXC1 = 943, - Mips_LDXC164 = 944, - Mips_LD_B = 945, - Mips_LD_D = 946, - Mips_LD_H = 947, - Mips_LD_W = 948, - Mips_LEA_ADDiu = 949, - Mips_LEA_ADDiu64 = 950, - Mips_LEA_ADDiu_MM = 951, - Mips_LH = 952, - Mips_LH64 = 953, - Mips_LHU16_MM = 954, - Mips_LHX = 955, - Mips_LH_MM = 956, - Mips_LHu = 957, - Mips_LHu64 = 958, - Mips_LHu_MM = 959, - Mips_LI16_MM = 960, - Mips_LL = 961, - Mips_LLD = 962, - Mips_LLD_R6 = 963, - Mips_LL_MM = 964, - Mips_LL_R6 = 965, - Mips_LOAD_ACC128 = 966, - Mips_LOAD_ACC64 = 967, - Mips_LOAD_ACC64DSP = 968, - Mips_LOAD_CCOND_DSP = 969, - Mips_LONG_BRANCH_ADDiu = 970, - Mips_LONG_BRANCH_DADDiu = 971, - Mips_LONG_BRANCH_LUi = 972, - Mips_LSA = 973, - Mips_LSA_R6 = 974, - Mips_LUXC1 = 975, - Mips_LUXC164 = 976, - Mips_LUXC1_MM = 977, - Mips_LUi = 978, - Mips_LUi64 = 979, - Mips_LUi_MM = 980, - Mips_LW = 981, - Mips_LW16_MM = 982, - Mips_LW64 = 983, - Mips_LWC1 = 984, - Mips_LWC1_MM = 985, - Mips_LWC2 = 986, - Mips_LWC2_R6 = 987, - Mips_LWC3 = 988, - Mips_LWGP_MM = 989, - Mips_LWL = 990, - Mips_LWL64 = 991, - Mips_LWL_MM = 992, - Mips_LWM16_MM = 993, - Mips_LWM32_MM = 994, - Mips_LWM_MM = 995, - Mips_LWPC = 996, - Mips_LWP_MM = 997, - Mips_LWR = 998, - Mips_LWR64 = 999, - Mips_LWR_MM = 1000, - Mips_LWSP_MM = 1001, - Mips_LWUPC = 1002, - Mips_LWU_MM = 1003, - Mips_LWX = 1004, - Mips_LWXC1 = 1005, - Mips_LWXC1_MM = 1006, - Mips_LWXS_MM = 1007, - Mips_LW_MM = 1008, - Mips_LWu = 1009, - Mips_LbRxRyOffMemX16 = 1010, - Mips_LbuRxRyOffMemX16 = 1011, - Mips_LhRxRyOffMemX16 = 1012, - Mips_LhuRxRyOffMemX16 = 1013, - Mips_LiRxImm16 = 1014, - Mips_LiRxImmAlignX16 = 1015, - Mips_LiRxImmX16 = 1016, - Mips_LoadAddr32Imm = 1017, - Mips_LoadAddr32Reg = 1018, - Mips_LoadImm32Reg = 1019, - Mips_LoadImm64Reg = 1020, - Mips_LwConstant32 = 1021, - Mips_LwRxPcTcp16 = 1022, - Mips_LwRxPcTcpX16 = 1023, - Mips_LwRxRyOffMemX16 = 1024, - Mips_LwRxSpImmX16 = 1025, - Mips_MADD = 1026, - Mips_MADDF_D = 1027, - Mips_MADDF_S = 1028, - Mips_MADDR_Q_H = 1029, - Mips_MADDR_Q_W = 1030, - Mips_MADDU = 1031, - Mips_MADDU_DSP = 1032, - Mips_MADDU_MM = 1033, - Mips_MADDV_B = 1034, - Mips_MADDV_D = 1035, - Mips_MADDV_H = 1036, - Mips_MADDV_W = 1037, - Mips_MADD_D32 = 1038, - Mips_MADD_D32_MM = 1039, - Mips_MADD_D64 = 1040, - Mips_MADD_DSP = 1041, - Mips_MADD_MM = 1042, - Mips_MADD_Q_H = 1043, - Mips_MADD_Q_W = 1044, - Mips_MADD_S = 1045, - Mips_MADD_S_MM = 1046, - Mips_MAQ_SA_W_PHL = 1047, - Mips_MAQ_SA_W_PHR = 1048, - Mips_MAQ_S_W_PHL = 1049, - Mips_MAQ_S_W_PHR = 1050, - Mips_MAXA_D = 1051, - Mips_MAXA_S = 1052, - Mips_MAXI_S_B = 1053, - Mips_MAXI_S_D = 1054, - Mips_MAXI_S_H = 1055, - Mips_MAXI_S_W = 1056, - Mips_MAXI_U_B = 1057, - Mips_MAXI_U_D = 1058, - Mips_MAXI_U_H = 1059, - Mips_MAXI_U_W = 1060, - Mips_MAX_A_B = 1061, - Mips_MAX_A_D = 1062, - Mips_MAX_A_H = 1063, - Mips_MAX_A_W = 1064, - Mips_MAX_D = 1065, - Mips_MAX_S = 1066, - Mips_MAX_S_B = 1067, - Mips_MAX_S_D = 1068, - Mips_MAX_S_H = 1069, - Mips_MAX_S_W = 1070, - Mips_MAX_U_B = 1071, - Mips_MAX_U_D = 1072, - Mips_MAX_U_H = 1073, - Mips_MAX_U_W = 1074, - Mips_MFC0 = 1075, - Mips_MFC1 = 1076, - Mips_MFC1_MM = 1077, - Mips_MFC2 = 1078, - Mips_MFHC1_D32 = 1079, - Mips_MFHC1_D64 = 1080, - Mips_MFHC1_MM = 1081, - Mips_MFHI = 1082, - Mips_MFHI16_MM = 1083, - Mips_MFHI64 = 1084, - Mips_MFHI_DSP = 1085, - Mips_MFHI_MM = 1086, - Mips_MFLO = 1087, - Mips_MFLO16_MM = 1088, - Mips_MFLO64 = 1089, - Mips_MFLO_DSP = 1090, - Mips_MFLO_MM = 1091, - Mips_MINA_D = 1092, - Mips_MINA_S = 1093, - Mips_MINI_S_B = 1094, - Mips_MINI_S_D = 1095, - Mips_MINI_S_H = 1096, - Mips_MINI_S_W = 1097, - Mips_MINI_U_B = 1098, - Mips_MINI_U_D = 1099, - Mips_MINI_U_H = 1100, - Mips_MINI_U_W = 1101, - Mips_MIN_A_B = 1102, - Mips_MIN_A_D = 1103, - Mips_MIN_A_H = 1104, - Mips_MIN_A_W = 1105, - Mips_MIN_D = 1106, - Mips_MIN_S = 1107, - Mips_MIN_S_B = 1108, - Mips_MIN_S_D = 1109, - Mips_MIN_S_H = 1110, - Mips_MIN_S_W = 1111, - Mips_MIN_U_B = 1112, - Mips_MIN_U_D = 1113, - Mips_MIN_U_H = 1114, - Mips_MIN_U_W = 1115, - Mips_MIPSeh_return32 = 1116, - Mips_MIPSeh_return64 = 1117, - Mips_MOD = 1118, - Mips_MODSUB = 1119, - Mips_MODU = 1120, - Mips_MOD_S_B = 1121, - Mips_MOD_S_D = 1122, - Mips_MOD_S_H = 1123, - Mips_MOD_S_W = 1124, - Mips_MOD_U_B = 1125, - Mips_MOD_U_D = 1126, - Mips_MOD_U_H = 1127, - Mips_MOD_U_W = 1128, - Mips_MOVE16_MM = 1129, - Mips_MOVEP_MM = 1130, - Mips_MOVE_V = 1131, - Mips_MOVF_D32 = 1132, - Mips_MOVF_D32_MM = 1133, - Mips_MOVF_D64 = 1134, - Mips_MOVF_I = 1135, - Mips_MOVF_I64 = 1136, - Mips_MOVF_I_MM = 1137, - Mips_MOVF_S = 1138, - Mips_MOVF_S_MM = 1139, - Mips_MOVN_I64_D64 = 1140, - Mips_MOVN_I64_I = 1141, - Mips_MOVN_I64_I64 = 1142, - Mips_MOVN_I64_S = 1143, - Mips_MOVN_I_D32 = 1144, - Mips_MOVN_I_D32_MM = 1145, - Mips_MOVN_I_D64 = 1146, - Mips_MOVN_I_I = 1147, - Mips_MOVN_I_I64 = 1148, - Mips_MOVN_I_MM = 1149, - Mips_MOVN_I_S = 1150, - Mips_MOVN_I_S_MM = 1151, - Mips_MOVT_D32 = 1152, - Mips_MOVT_D32_MM = 1153, - Mips_MOVT_D64 = 1154, - Mips_MOVT_I = 1155, - Mips_MOVT_I64 = 1156, - Mips_MOVT_I_MM = 1157, - Mips_MOVT_S = 1158, - Mips_MOVT_S_MM = 1159, - Mips_MOVZ_I64_D64 = 1160, - Mips_MOVZ_I64_I = 1161, - Mips_MOVZ_I64_I64 = 1162, - Mips_MOVZ_I64_S = 1163, - Mips_MOVZ_I_D32 = 1164, - Mips_MOVZ_I_D32_MM = 1165, - Mips_MOVZ_I_D64 = 1166, - Mips_MOVZ_I_I = 1167, - Mips_MOVZ_I_I64 = 1168, - Mips_MOVZ_I_MM = 1169, - Mips_MOVZ_I_S = 1170, - Mips_MOVZ_I_S_MM = 1171, - Mips_MSUB = 1172, - Mips_MSUBF_D = 1173, - Mips_MSUBF_S = 1174, - Mips_MSUBR_Q_H = 1175, - Mips_MSUBR_Q_W = 1176, - Mips_MSUBU = 1177, - Mips_MSUBU_DSP = 1178, - Mips_MSUBU_MM = 1179, - Mips_MSUBV_B = 1180, - Mips_MSUBV_D = 1181, - Mips_MSUBV_H = 1182, - Mips_MSUBV_W = 1183, - Mips_MSUB_D32 = 1184, - Mips_MSUB_D32_MM = 1185, - Mips_MSUB_D64 = 1186, - Mips_MSUB_DSP = 1187, - Mips_MSUB_MM = 1188, - Mips_MSUB_Q_H = 1189, - Mips_MSUB_Q_W = 1190, - Mips_MSUB_S = 1191, - Mips_MSUB_S_MM = 1192, - Mips_MTC0 = 1193, - Mips_MTC1 = 1194, - Mips_MTC1_MM = 1195, - Mips_MTC2 = 1196, - Mips_MTHC1_D32 = 1197, - Mips_MTHC1_D64 = 1198, - Mips_MTHC1_MM = 1199, - Mips_MTHI = 1200, - Mips_MTHI64 = 1201, - Mips_MTHI_DSP = 1202, - Mips_MTHI_MM = 1203, - Mips_MTHLIP = 1204, - Mips_MTLO = 1205, - Mips_MTLO64 = 1206, - Mips_MTLO_DSP = 1207, - Mips_MTLO_MM = 1208, - Mips_MTM0 = 1209, - Mips_MTM1 = 1210, - Mips_MTM2 = 1211, - Mips_MTP0 = 1212, - Mips_MTP1 = 1213, - Mips_MTP2 = 1214, - Mips_MUH = 1215, - Mips_MUHU = 1216, - Mips_MUL = 1217, - Mips_MULEQ_S_W_PHL = 1218, - Mips_MULEQ_S_W_PHR = 1219, - Mips_MULEU_S_PH_QBL = 1220, - Mips_MULEU_S_PH_QBR = 1221, - Mips_MULQ_RS_PH = 1222, - Mips_MULQ_RS_W = 1223, - Mips_MULQ_S_PH = 1224, - Mips_MULQ_S_W = 1225, - Mips_MULR_Q_H = 1226, - Mips_MULR_Q_W = 1227, - Mips_MULSAQ_S_W_PH = 1228, - Mips_MULSA_W_PH = 1229, - Mips_MULT = 1230, - Mips_MULTU_DSP = 1231, - Mips_MULT_DSP = 1232, - Mips_MULT_MM = 1233, - Mips_MULTu = 1234, - Mips_MULTu_MM = 1235, - Mips_MULU = 1236, - Mips_MULV_B = 1237, - Mips_MULV_D = 1238, - Mips_MULV_H = 1239, - Mips_MULV_W = 1240, - Mips_MUL_MM = 1241, - Mips_MUL_PH = 1242, - Mips_MUL_Q_H = 1243, - Mips_MUL_Q_W = 1244, - Mips_MUL_R6 = 1245, - Mips_MUL_S_PH = 1246, - Mips_Mfhi16 = 1247, - Mips_Mflo16 = 1248, - Mips_Move32R16 = 1249, - Mips_MoveR3216 = 1250, - Mips_MultRxRy16 = 1251, - Mips_MultRxRyRz16 = 1252, - Mips_MultuRxRy16 = 1253, - Mips_MultuRxRyRz16 = 1254, - Mips_NLOC_B = 1255, - Mips_NLOC_D = 1256, - Mips_NLOC_H = 1257, - Mips_NLOC_W = 1258, - Mips_NLZC_B = 1259, - Mips_NLZC_D = 1260, - Mips_NLZC_H = 1261, - Mips_NLZC_W = 1262, - Mips_NMADD_D32 = 1263, - Mips_NMADD_D32_MM = 1264, - Mips_NMADD_D64 = 1265, - Mips_NMADD_S = 1266, - Mips_NMADD_S_MM = 1267, - Mips_NMSUB_D32 = 1268, - Mips_NMSUB_D32_MM = 1269, - Mips_NMSUB_D64 = 1270, - Mips_NMSUB_S = 1271, - Mips_NMSUB_S_MM = 1272, - Mips_NOP = 1273, - Mips_NOR = 1274, - Mips_NOR64 = 1275, - Mips_NORI_B = 1276, - Mips_NOR_MM = 1277, - Mips_NOR_V = 1278, - Mips_NOR_V_D_PSEUDO = 1279, - Mips_NOR_V_H_PSEUDO = 1280, - Mips_NOR_V_W_PSEUDO = 1281, - Mips_NOT16_MM = 1282, - Mips_NegRxRy16 = 1283, - Mips_NotRxRy16 = 1284, - Mips_OR = 1285, - Mips_OR16_MM = 1286, - Mips_OR64 = 1287, - Mips_ORI_B = 1288, - Mips_OR_MM = 1289, - Mips_OR_V = 1290, - Mips_OR_V_D_PSEUDO = 1291, - Mips_OR_V_H_PSEUDO = 1292, - Mips_OR_V_W_PSEUDO = 1293, - Mips_ORi = 1294, - Mips_ORi64 = 1295, - Mips_ORi_MM = 1296, - Mips_OrRxRxRy16 = 1297, - Mips_PACKRL_PH = 1298, - Mips_PAUSE = 1299, - Mips_PAUSE_MM = 1300, - Mips_PCKEV_B = 1301, - Mips_PCKEV_D = 1302, - Mips_PCKEV_H = 1303, - Mips_PCKEV_W = 1304, - Mips_PCKOD_B = 1305, - Mips_PCKOD_D = 1306, - Mips_PCKOD_H = 1307, - Mips_PCKOD_W = 1308, - Mips_PCNT_B = 1309, - Mips_PCNT_D = 1310, - Mips_PCNT_H = 1311, - Mips_PCNT_W = 1312, - Mips_PICK_PH = 1313, - Mips_PICK_QB = 1314, - Mips_POP = 1315, - Mips_PRECEQU_PH_QBL = 1316, - Mips_PRECEQU_PH_QBLA = 1317, - Mips_PRECEQU_PH_QBR = 1318, - Mips_PRECEQU_PH_QBRA = 1319, - Mips_PRECEQ_W_PHL = 1320, - Mips_PRECEQ_W_PHR = 1321, - Mips_PRECEU_PH_QBL = 1322, - Mips_PRECEU_PH_QBLA = 1323, - Mips_PRECEU_PH_QBR = 1324, - Mips_PRECEU_PH_QBRA = 1325, - Mips_PRECRQU_S_QB_PH = 1326, - Mips_PRECRQ_PH_W = 1327, - Mips_PRECRQ_QB_PH = 1328, - Mips_PRECRQ_RS_PH_W = 1329, - Mips_PRECR_QB_PH = 1330, - Mips_PRECR_SRA_PH_W = 1331, - Mips_PRECR_SRA_R_PH_W = 1332, - Mips_PREF = 1333, - Mips_PREF_MM = 1334, - Mips_PREF_R6 = 1335, - Mips_PREPEND = 1336, - Mips_PseudoCMPU_EQ_QB = 1337, - Mips_PseudoCMPU_LE_QB = 1338, - Mips_PseudoCMPU_LT_QB = 1339, - Mips_PseudoCMP_EQ_PH = 1340, - Mips_PseudoCMP_LE_PH = 1341, - Mips_PseudoCMP_LT_PH = 1342, - Mips_PseudoCVT_D32_W = 1343, - Mips_PseudoCVT_D64_L = 1344, - Mips_PseudoCVT_D64_W = 1345, - Mips_PseudoCVT_S_L = 1346, - Mips_PseudoCVT_S_W = 1347, - Mips_PseudoDMULT = 1348, - Mips_PseudoDMULTu = 1349, - Mips_PseudoDSDIV = 1350, - Mips_PseudoDUDIV = 1351, - Mips_PseudoIndirectBranch = 1352, - Mips_PseudoIndirectBranch64 = 1353, - Mips_PseudoMADD = 1354, - Mips_PseudoMADDU = 1355, - Mips_PseudoMFHI = 1356, - Mips_PseudoMFHI64 = 1357, - Mips_PseudoMFLO = 1358, - Mips_PseudoMFLO64 = 1359, - Mips_PseudoMSUB = 1360, - Mips_PseudoMSUBU = 1361, - Mips_PseudoMTLOHI = 1362, - Mips_PseudoMTLOHI64 = 1363, - Mips_PseudoMTLOHI_DSP = 1364, - Mips_PseudoMULT = 1365, - Mips_PseudoMULTu = 1366, - Mips_PseudoPICK_PH = 1367, - Mips_PseudoPICK_QB = 1368, - Mips_PseudoReturn = 1369, - Mips_PseudoReturn64 = 1370, - Mips_PseudoSDIV = 1371, - Mips_PseudoSELECTFP_F_D32 = 1372, - Mips_PseudoSELECTFP_F_D64 = 1373, - Mips_PseudoSELECTFP_F_I = 1374, - Mips_PseudoSELECTFP_F_I64 = 1375, - Mips_PseudoSELECTFP_F_S = 1376, - Mips_PseudoSELECTFP_T_D32 = 1377, - Mips_PseudoSELECTFP_T_D64 = 1378, - Mips_PseudoSELECTFP_T_I = 1379, - Mips_PseudoSELECTFP_T_I64 = 1380, - Mips_PseudoSELECTFP_T_S = 1381, - Mips_PseudoSELECT_D32 = 1382, - Mips_PseudoSELECT_D64 = 1383, - Mips_PseudoSELECT_I = 1384, - Mips_PseudoSELECT_I64 = 1385, - Mips_PseudoSELECT_S = 1386, - Mips_PseudoUDIV = 1387, - Mips_RADDU_W_QB = 1388, - Mips_RDDSP = 1389, - Mips_RDHWR = 1390, - Mips_RDHWR64 = 1391, - Mips_RDHWR_MM = 1392, - Mips_REPLV_PH = 1393, - Mips_REPLV_QB = 1394, - Mips_REPL_PH = 1395, - Mips_REPL_QB = 1396, - Mips_RINT_D = 1397, - Mips_RINT_S = 1398, - Mips_ROTR = 1399, - Mips_ROTRV = 1400, - Mips_ROTRV_MM = 1401, - Mips_ROTR_MM = 1402, - Mips_ROUND_L_D64 = 1403, - Mips_ROUND_L_S = 1404, - Mips_ROUND_W_D32 = 1405, - Mips_ROUND_W_D64 = 1406, - Mips_ROUND_W_MM = 1407, - Mips_ROUND_W_S = 1408, - Mips_ROUND_W_S_MM = 1409, - Mips_Restore16 = 1410, - Mips_RestoreX16 = 1411, - Mips_RetRA = 1412, - Mips_RetRA16 = 1413, - Mips_SAT_S_B = 1414, - Mips_SAT_S_D = 1415, - Mips_SAT_S_H = 1416, - Mips_SAT_S_W = 1417, - Mips_SAT_U_B = 1418, - Mips_SAT_U_D = 1419, - Mips_SAT_U_H = 1420, - Mips_SAT_U_W = 1421, - Mips_SB = 1422, - Mips_SB16_MM = 1423, - Mips_SB64 = 1424, - Mips_SB_MM = 1425, - Mips_SC = 1426, - Mips_SCD = 1427, - Mips_SCD_R6 = 1428, - Mips_SC_MM = 1429, - Mips_SC_R6 = 1430, - Mips_SD = 1431, - Mips_SDBBP = 1432, - Mips_SDBBP16_MM = 1433, - Mips_SDBBP_MM = 1434, - Mips_SDBBP_R6 = 1435, - Mips_SDC1 = 1436, - Mips_SDC164 = 1437, - Mips_SDC1_MM = 1438, - Mips_SDC2 = 1439, - Mips_SDC2_R6 = 1440, - Mips_SDC3 = 1441, - Mips_SDIV = 1442, - Mips_SDIV_MM = 1443, - Mips_SDL = 1444, - Mips_SDR = 1445, - Mips_SDXC1 = 1446, - Mips_SDXC164 = 1447, - Mips_SEB = 1448, - Mips_SEB64 = 1449, - Mips_SEB_MM = 1450, - Mips_SEH = 1451, - Mips_SEH64 = 1452, - Mips_SEH_MM = 1453, - Mips_SELEQZ = 1454, - Mips_SELEQZ64 = 1455, - Mips_SELEQZ_D = 1456, - Mips_SELEQZ_S = 1457, - Mips_SELNEZ = 1458, - Mips_SELNEZ64 = 1459, - Mips_SELNEZ_D = 1460, - Mips_SELNEZ_S = 1461, - Mips_SEL_D = 1462, - Mips_SEL_S = 1463, - Mips_SEQ = 1464, - Mips_SEQi = 1465, - Mips_SH = 1466, - Mips_SH16_MM = 1467, - Mips_SH64 = 1468, - Mips_SHF_B = 1469, - Mips_SHF_H = 1470, - Mips_SHF_W = 1471, - Mips_SHILO = 1472, - Mips_SHILOV = 1473, - Mips_SHLLV_PH = 1474, - Mips_SHLLV_QB = 1475, - Mips_SHLLV_S_PH = 1476, - Mips_SHLLV_S_W = 1477, - Mips_SHLL_PH = 1478, - Mips_SHLL_QB = 1479, - Mips_SHLL_S_PH = 1480, - Mips_SHLL_S_W = 1481, - Mips_SHRAV_PH = 1482, - Mips_SHRAV_QB = 1483, - Mips_SHRAV_R_PH = 1484, - Mips_SHRAV_R_QB = 1485, - Mips_SHRAV_R_W = 1486, - Mips_SHRA_PH = 1487, - Mips_SHRA_QB = 1488, - Mips_SHRA_R_PH = 1489, - Mips_SHRA_R_QB = 1490, - Mips_SHRA_R_W = 1491, - Mips_SHRLV_PH = 1492, - Mips_SHRLV_QB = 1493, - Mips_SHRL_PH = 1494, - Mips_SHRL_QB = 1495, - Mips_SH_MM = 1496, - Mips_SLDI_B = 1497, - Mips_SLDI_D = 1498, - Mips_SLDI_H = 1499, - Mips_SLDI_W = 1500, - Mips_SLD_B = 1501, - Mips_SLD_D = 1502, - Mips_SLD_H = 1503, - Mips_SLD_W = 1504, - Mips_SLL = 1505, - Mips_SLL16_MM = 1506, - Mips_SLL64_32 = 1507, - Mips_SLL64_64 = 1508, - Mips_SLLI_B = 1509, - Mips_SLLI_D = 1510, - Mips_SLLI_H = 1511, - Mips_SLLI_W = 1512, - Mips_SLLV = 1513, - Mips_SLLV_MM = 1514, - Mips_SLL_B = 1515, - Mips_SLL_D = 1516, - Mips_SLL_H = 1517, - Mips_SLL_MM = 1518, - Mips_SLL_W = 1519, - Mips_SLT = 1520, - Mips_SLT64 = 1521, - Mips_SLT_MM = 1522, - Mips_SLTi = 1523, - Mips_SLTi64 = 1524, - Mips_SLTi_MM = 1525, - Mips_SLTiu = 1526, - Mips_SLTiu64 = 1527, - Mips_SLTiu_MM = 1528, - Mips_SLTu = 1529, - Mips_SLTu64 = 1530, - Mips_SLTu_MM = 1531, - Mips_SNE = 1532, - Mips_SNEi = 1533, - Mips_SNZ_B_PSEUDO = 1534, - Mips_SNZ_D_PSEUDO = 1535, - Mips_SNZ_H_PSEUDO = 1536, - Mips_SNZ_V_PSEUDO = 1537, - Mips_SNZ_W_PSEUDO = 1538, - Mips_SPLATI_B = 1539, - Mips_SPLATI_D = 1540, - Mips_SPLATI_H = 1541, - Mips_SPLATI_W = 1542, - Mips_SPLAT_B = 1543, - Mips_SPLAT_D = 1544, - Mips_SPLAT_H = 1545, - Mips_SPLAT_W = 1546, - Mips_SRA = 1547, - Mips_SRAI_B = 1548, - Mips_SRAI_D = 1549, - Mips_SRAI_H = 1550, - Mips_SRAI_W = 1551, - Mips_SRARI_B = 1552, - Mips_SRARI_D = 1553, - Mips_SRARI_H = 1554, - Mips_SRARI_W = 1555, - Mips_SRAR_B = 1556, - Mips_SRAR_D = 1557, - Mips_SRAR_H = 1558, - Mips_SRAR_W = 1559, - Mips_SRAV = 1560, - Mips_SRAV_MM = 1561, - Mips_SRA_B = 1562, - Mips_SRA_D = 1563, - Mips_SRA_H = 1564, - Mips_SRA_MM = 1565, - Mips_SRA_W = 1566, - Mips_SRL = 1567, - Mips_SRL16_MM = 1568, - Mips_SRLI_B = 1569, - Mips_SRLI_D = 1570, - Mips_SRLI_H = 1571, - Mips_SRLI_W = 1572, - Mips_SRLRI_B = 1573, - Mips_SRLRI_D = 1574, - Mips_SRLRI_H = 1575, - Mips_SRLRI_W = 1576, - Mips_SRLR_B = 1577, - Mips_SRLR_D = 1578, - Mips_SRLR_H = 1579, - Mips_SRLR_W = 1580, - Mips_SRLV = 1581, - Mips_SRLV_MM = 1582, - Mips_SRL_B = 1583, - Mips_SRL_D = 1584, - Mips_SRL_H = 1585, - Mips_SRL_MM = 1586, - Mips_SRL_W = 1587, - Mips_SSNOP = 1588, - Mips_SSNOP_MM = 1589, - Mips_STORE_ACC128 = 1590, - Mips_STORE_ACC64 = 1591, - Mips_STORE_ACC64DSP = 1592, - Mips_STORE_CCOND_DSP = 1593, - Mips_ST_B = 1594, - Mips_ST_D = 1595, - Mips_ST_H = 1596, - Mips_ST_W = 1597, - Mips_SUB = 1598, - Mips_SUBQH_PH = 1599, - Mips_SUBQH_R_PH = 1600, - Mips_SUBQH_R_W = 1601, - Mips_SUBQH_W = 1602, - Mips_SUBQ_PH = 1603, - Mips_SUBQ_S_PH = 1604, - Mips_SUBQ_S_W = 1605, - Mips_SUBSUS_U_B = 1606, - Mips_SUBSUS_U_D = 1607, - Mips_SUBSUS_U_H = 1608, - Mips_SUBSUS_U_W = 1609, - Mips_SUBSUU_S_B = 1610, - Mips_SUBSUU_S_D = 1611, - Mips_SUBSUU_S_H = 1612, - Mips_SUBSUU_S_W = 1613, - Mips_SUBS_S_B = 1614, - Mips_SUBS_S_D = 1615, - Mips_SUBS_S_H = 1616, - Mips_SUBS_S_W = 1617, - Mips_SUBS_U_B = 1618, - Mips_SUBS_U_D = 1619, - Mips_SUBS_U_H = 1620, - Mips_SUBS_U_W = 1621, - Mips_SUBU16_MM = 1622, - Mips_SUBUH_QB = 1623, - Mips_SUBUH_R_QB = 1624, - Mips_SUBU_PH = 1625, - Mips_SUBU_QB = 1626, - Mips_SUBU_S_PH = 1627, - Mips_SUBU_S_QB = 1628, - Mips_SUBVI_B = 1629, - Mips_SUBVI_D = 1630, - Mips_SUBVI_H = 1631, - Mips_SUBVI_W = 1632, - Mips_SUBV_B = 1633, - Mips_SUBV_D = 1634, - Mips_SUBV_H = 1635, - Mips_SUBV_W = 1636, - Mips_SUB_MM = 1637, - Mips_SUBu = 1638, - Mips_SUBu_MM = 1639, - Mips_SUXC1 = 1640, - Mips_SUXC164 = 1641, - Mips_SUXC1_MM = 1642, - Mips_SW = 1643, - Mips_SW16_MM = 1644, - Mips_SW64 = 1645, - Mips_SWC1 = 1646, - Mips_SWC1_MM = 1647, - Mips_SWC2 = 1648, - Mips_SWC2_R6 = 1649, - Mips_SWC3 = 1650, - Mips_SWL = 1651, - Mips_SWL64 = 1652, - Mips_SWL_MM = 1653, - Mips_SWM16_MM = 1654, - Mips_SWM32_MM = 1655, - Mips_SWM_MM = 1656, - Mips_SWP_MM = 1657, - Mips_SWR = 1658, - Mips_SWR64 = 1659, - Mips_SWR_MM = 1660, - Mips_SWSP_MM = 1661, - Mips_SWXC1 = 1662, - Mips_SWXC1_MM = 1663, - Mips_SW_MM = 1664, - Mips_SYNC = 1665, - Mips_SYNCI = 1666, - Mips_SYNC_MM = 1667, - Mips_SYSCALL = 1668, - Mips_SYSCALL_MM = 1669, - Mips_SZ_B_PSEUDO = 1670, - Mips_SZ_D_PSEUDO = 1671, - Mips_SZ_H_PSEUDO = 1672, - Mips_SZ_V_PSEUDO = 1673, - Mips_SZ_W_PSEUDO = 1674, - Mips_Save16 = 1675, - Mips_SaveX16 = 1676, - Mips_SbRxRyOffMemX16 = 1677, - Mips_SebRx16 = 1678, - Mips_SehRx16 = 1679, - Mips_SelBeqZ = 1680, - Mips_SelBneZ = 1681, - Mips_SelTBteqZCmp = 1682, - Mips_SelTBteqZCmpi = 1683, - Mips_SelTBteqZSlt = 1684, - Mips_SelTBteqZSlti = 1685, - Mips_SelTBteqZSltiu = 1686, - Mips_SelTBteqZSltu = 1687, - Mips_SelTBtneZCmp = 1688, - Mips_SelTBtneZCmpi = 1689, - Mips_SelTBtneZSlt = 1690, - Mips_SelTBtneZSlti = 1691, - Mips_SelTBtneZSltiu = 1692, - Mips_SelTBtneZSltu = 1693, - Mips_ShRxRyOffMemX16 = 1694, - Mips_SllX16 = 1695, - Mips_SllvRxRy16 = 1696, - Mips_SltCCRxRy16 = 1697, - Mips_SltRxRy16 = 1698, - Mips_SltiCCRxImmX16 = 1699, - Mips_SltiRxImm16 = 1700, - Mips_SltiRxImmX16 = 1701, - Mips_SltiuCCRxImmX16 = 1702, - Mips_SltiuRxImm16 = 1703, - Mips_SltiuRxImmX16 = 1704, - Mips_SltuCCRxRy16 = 1705, - Mips_SltuRxRy16 = 1706, - Mips_SltuRxRyRz16 = 1707, - Mips_SraX16 = 1708, - Mips_SravRxRy16 = 1709, - Mips_SrlX16 = 1710, - Mips_SrlvRxRy16 = 1711, - Mips_SubuRxRyRz16 = 1712, - Mips_SwRxRyOffMemX16 = 1713, - Mips_SwRxSpImmX16 = 1714, - Mips_TAILCALL = 1715, - Mips_TAILCALL64_R = 1716, - Mips_TAILCALL_R = 1717, - Mips_TEQ = 1718, - Mips_TEQI = 1719, - Mips_TEQI_MM = 1720, - Mips_TEQ_MM = 1721, - Mips_TGE = 1722, - Mips_TGEI = 1723, - Mips_TGEIU = 1724, - Mips_TGEIU_MM = 1725, - Mips_TGEI_MM = 1726, - Mips_TGEU = 1727, - Mips_TGEU_MM = 1728, - Mips_TGE_MM = 1729, - Mips_TLBP = 1730, - Mips_TLBP_MM = 1731, - Mips_TLBR = 1732, - Mips_TLBR_MM = 1733, - Mips_TLBWI = 1734, - Mips_TLBWI_MM = 1735, - Mips_TLBWR = 1736, - Mips_TLBWR_MM = 1737, - Mips_TLT = 1738, - Mips_TLTI = 1739, - Mips_TLTIU_MM = 1740, - Mips_TLTI_MM = 1741, - Mips_TLTU = 1742, - Mips_TLTU_MM = 1743, - Mips_TLT_MM = 1744, - Mips_TNE = 1745, - Mips_TNEI = 1746, - Mips_TNEI_MM = 1747, - Mips_TNE_MM = 1748, - Mips_TRAP = 1749, - Mips_TRUNC_L_D64 = 1750, - Mips_TRUNC_L_S = 1751, - Mips_TRUNC_W_D32 = 1752, - Mips_TRUNC_W_D64 = 1753, - Mips_TRUNC_W_MM = 1754, - Mips_TRUNC_W_S = 1755, - Mips_TRUNC_W_S_MM = 1756, - Mips_TTLTIU = 1757, - Mips_UDIV = 1758, - Mips_UDIV_MM = 1759, - Mips_V3MULU = 1760, - Mips_VMM0 = 1761, - Mips_VMULU = 1762, - Mips_VSHF_B = 1763, - Mips_VSHF_D = 1764, - Mips_VSHF_H = 1765, - Mips_VSHF_W = 1766, - Mips_WAIT = 1767, - Mips_WAIT_MM = 1768, - Mips_WRDSP = 1769, - Mips_WSBH = 1770, - Mips_WSBH_MM = 1771, - Mips_XOR = 1772, - Mips_XOR16_MM = 1773, - Mips_XOR64 = 1774, - Mips_XORI_B = 1775, - Mips_XOR_MM = 1776, - Mips_XOR_V = 1777, - Mips_XOR_V_D_PSEUDO = 1778, - Mips_XOR_V_H_PSEUDO = 1779, - Mips_XOR_V_W_PSEUDO = 1780, - Mips_XORi = 1781, - Mips_XORi64 = 1782, - Mips_XORi_MM = 1783, - Mips_XorRxRxRy16 = 1784, - Mips_INSTRUCTION_LIST_END = 1785 -}; + Mips_INLINEASM_BR = 2, + Mips_CFI_INSTRUCTION = 3, + Mips_EH_LABEL = 4, + Mips_GC_LABEL = 5, + Mips_ANNOTATION_LABEL = 6, + Mips_KILL = 7, + Mips_EXTRACT_SUBREG = 8, + Mips_INSERT_SUBREG = 9, + Mips_IMPLICIT_DEF = 10, + Mips_SUBREG_TO_REG = 11, + Mips_COPY_TO_REGCLASS = 12, + Mips_DBG_VALUE = 13, + Mips_DBG_VALUE_LIST = 14, + Mips_DBG_INSTR_REF = 15, + Mips_DBG_PHI = 16, + Mips_DBG_LABEL = 17, + Mips_REG_SEQUENCE = 18, + Mips_COPY = 19, + Mips_BUNDLE = 20, + Mips_LIFETIME_START = 21, + Mips_LIFETIME_END = 22, + Mips_PSEUDO_PROBE = 23, + Mips_ARITH_FENCE = 24, + Mips_STACKMAP = 25, + Mips_FENTRY_CALL = 26, + Mips_PATCHPOINT = 27, + Mips_LOAD_STACK_GUARD = 28, + Mips_PREALLOCATED_SETUP = 29, + Mips_PREALLOCATED_ARG = 30, + Mips_STATEPOINT = 31, + Mips_LOCAL_ESCAPE = 32, + Mips_FAULTING_OP = 33, + Mips_PATCHABLE_OP = 34, + Mips_PATCHABLE_FUNCTION_ENTER = 35, + Mips_PATCHABLE_RET = 36, + Mips_PATCHABLE_FUNCTION_EXIT = 37, + Mips_PATCHABLE_TAIL_CALL = 38, + Mips_PATCHABLE_EVENT_CALL = 39, + Mips_PATCHABLE_TYPED_EVENT_CALL = 40, + Mips_ICALL_BRANCH_FUNNEL = 41, + Mips_MEMBARRIER = 42, + Mips_JUMP_TABLE_DEBUG_INFO = 43, + Mips_G_ASSERT_SEXT = 44, + Mips_G_ASSERT_ZEXT = 45, + Mips_G_ASSERT_ALIGN = 46, + Mips_G_ADD = 47, + Mips_G_SUB = 48, + Mips_G_MUL = 49, + Mips_G_SDIV = 50, + Mips_G_UDIV = 51, + Mips_G_SREM = 52, + Mips_G_UREM = 53, + Mips_G_SDIVREM = 54, + Mips_G_UDIVREM = 55, + Mips_G_AND = 56, + Mips_G_OR = 57, + Mips_G_XOR = 58, + Mips_G_IMPLICIT_DEF = 59, + Mips_G_PHI = 60, + Mips_G_FRAME_INDEX = 61, + Mips_G_GLOBAL_VALUE = 62, + Mips_G_CONSTANT_POOL = 63, + Mips_G_EXTRACT = 64, + Mips_G_UNMERGE_VALUES = 65, + Mips_G_INSERT = 66, + Mips_G_MERGE_VALUES = 67, + Mips_G_BUILD_VECTOR = 68, + Mips_G_BUILD_VECTOR_TRUNC = 69, + Mips_G_CONCAT_VECTORS = 70, + Mips_G_PTRTOINT = 71, + Mips_G_INTTOPTR = 72, + Mips_G_BITCAST = 73, + Mips_G_FREEZE = 74, + Mips_G_CONSTANT_FOLD_BARRIER = 75, + Mips_G_INTRINSIC_FPTRUNC_ROUND = 76, + Mips_G_INTRINSIC_TRUNC = 77, + Mips_G_INTRINSIC_ROUND = 78, + Mips_G_INTRINSIC_LRINT = 79, + Mips_G_INTRINSIC_ROUNDEVEN = 80, + Mips_G_READCYCLECOUNTER = 81, + Mips_G_LOAD = 82, + Mips_G_SEXTLOAD = 83, + Mips_G_ZEXTLOAD = 84, + Mips_G_INDEXED_LOAD = 85, + Mips_G_INDEXED_SEXTLOAD = 86, + Mips_G_INDEXED_ZEXTLOAD = 87, + Mips_G_STORE = 88, + Mips_G_INDEXED_STORE = 89, + Mips_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90, + Mips_G_ATOMIC_CMPXCHG = 91, + Mips_G_ATOMICRMW_XCHG = 92, + Mips_G_ATOMICRMW_ADD = 93, + Mips_G_ATOMICRMW_SUB = 94, + Mips_G_ATOMICRMW_AND = 95, + Mips_G_ATOMICRMW_NAND = 96, + Mips_G_ATOMICRMW_OR = 97, + Mips_G_ATOMICRMW_XOR = 98, + Mips_G_ATOMICRMW_MAX = 99, + Mips_G_ATOMICRMW_MIN = 100, + Mips_G_ATOMICRMW_UMAX = 101, + Mips_G_ATOMICRMW_UMIN = 102, + Mips_G_ATOMICRMW_FADD = 103, + Mips_G_ATOMICRMW_FSUB = 104, + Mips_G_ATOMICRMW_FMAX = 105, + Mips_G_ATOMICRMW_FMIN = 106, + Mips_G_ATOMICRMW_UINC_WRAP = 107, + Mips_G_ATOMICRMW_UDEC_WRAP = 108, + Mips_G_FENCE = 109, + Mips_G_PREFETCH = 110, + Mips_G_BRCOND = 111, + Mips_G_BRINDIRECT = 112, + Mips_G_INVOKE_REGION_START = 113, + Mips_G_INTRINSIC = 114, + Mips_G_INTRINSIC_W_SIDE_EFFECTS = 115, + Mips_G_INTRINSIC_CONVERGENT = 116, + Mips_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117, + Mips_G_ANYEXT = 118, + Mips_G_TRUNC = 119, + Mips_G_CONSTANT = 120, + Mips_G_FCONSTANT = 121, + Mips_G_VASTART = 122, + Mips_G_VAARG = 123, + Mips_G_SEXT = 124, + Mips_G_SEXT_INREG = 125, + Mips_G_ZEXT = 126, + Mips_G_SHL = 127, + Mips_G_LSHR = 128, + Mips_G_ASHR = 129, + Mips_G_FSHL = 130, + Mips_G_FSHR = 131, + Mips_G_ROTR = 132, + Mips_G_ROTL = 133, + Mips_G_ICMP = 134, + Mips_G_FCMP = 135, + Mips_G_SELECT = 136, + Mips_G_UADDO = 137, + Mips_G_UADDE = 138, + Mips_G_USUBO = 139, + Mips_G_USUBE = 140, + Mips_G_SADDO = 141, + Mips_G_SADDE = 142, + Mips_G_SSUBO = 143, + Mips_G_SSUBE = 144, + Mips_G_UMULO = 145, + Mips_G_SMULO = 146, + Mips_G_UMULH = 147, + Mips_G_SMULH = 148, + Mips_G_UADDSAT = 149, + Mips_G_SADDSAT = 150, + Mips_G_USUBSAT = 151, + Mips_G_SSUBSAT = 152, + Mips_G_USHLSAT = 153, + Mips_G_SSHLSAT = 154, + Mips_G_SMULFIX = 155, + Mips_G_UMULFIX = 156, + Mips_G_SMULFIXSAT = 157, + Mips_G_UMULFIXSAT = 158, + Mips_G_SDIVFIX = 159, + Mips_G_UDIVFIX = 160, + Mips_G_SDIVFIXSAT = 161, + Mips_G_UDIVFIXSAT = 162, + Mips_G_FADD = 163, + Mips_G_FSUB = 164, + Mips_G_FMUL = 165, + Mips_G_FMA = 166, + Mips_G_FMAD = 167, + Mips_G_FDIV = 168, + Mips_G_FREM = 169, + Mips_G_FPOW = 170, + Mips_G_FPOWI = 171, + Mips_G_FEXP = 172, + Mips_G_FEXP2 = 173, + Mips_G_FEXP10 = 174, + Mips_G_FLOG = 175, + Mips_G_FLOG2 = 176, + Mips_G_FLOG10 = 177, + Mips_G_FLDEXP = 178, + Mips_G_FFREXP = 179, + Mips_G_FNEG = 180, + Mips_G_FPEXT = 181, + Mips_G_FPTRUNC = 182, + Mips_G_FPTOSI = 183, + Mips_G_FPTOUI = 184, + Mips_G_SITOFP = 185, + Mips_G_UITOFP = 186, + Mips_G_FABS = 187, + Mips_G_FCOPYSIGN = 188, + Mips_G_IS_FPCLASS = 189, + Mips_G_FCANONICALIZE = 190, + Mips_G_FMINNUM = 191, + Mips_G_FMAXNUM = 192, + Mips_G_FMINNUM_IEEE = 193, + Mips_G_FMAXNUM_IEEE = 194, + Mips_G_FMINIMUM = 195, + Mips_G_FMAXIMUM = 196, + Mips_G_GET_FPENV = 197, + Mips_G_SET_FPENV = 198, + Mips_G_RESET_FPENV = 199, + Mips_G_GET_FPMODE = 200, + Mips_G_SET_FPMODE = 201, + Mips_G_RESET_FPMODE = 202, + Mips_G_PTR_ADD = 203, + Mips_G_PTRMASK = 204, + Mips_G_SMIN = 205, + Mips_G_SMAX = 206, + Mips_G_UMIN = 207, + Mips_G_UMAX = 208, + Mips_G_ABS = 209, + Mips_G_LROUND = 210, + Mips_G_LLROUND = 211, + Mips_G_BR = 212, + Mips_G_BRJT = 213, + Mips_G_INSERT_VECTOR_ELT = 214, + Mips_G_EXTRACT_VECTOR_ELT = 215, + Mips_G_SHUFFLE_VECTOR = 216, + Mips_G_CTTZ = 217, + Mips_G_CTTZ_ZERO_UNDEF = 218, + Mips_G_CTLZ = 219, + Mips_G_CTLZ_ZERO_UNDEF = 220, + Mips_G_CTPOP = 221, + Mips_G_BSWAP = 222, + Mips_G_BITREVERSE = 223, + Mips_G_FCEIL = 224, + Mips_G_FCOS = 225, + Mips_G_FSIN = 226, + Mips_G_FSQRT = 227, + Mips_G_FFLOOR = 228, + Mips_G_FRINT = 229, + Mips_G_FNEARBYINT = 230, + Mips_G_ADDRSPACE_CAST = 231, + Mips_G_BLOCK_ADDR = 232, + Mips_G_JUMP_TABLE = 233, + Mips_G_DYN_STACKALLOC = 234, + Mips_G_STACKSAVE = 235, + Mips_G_STACKRESTORE = 236, + Mips_G_STRICT_FADD = 237, + Mips_G_STRICT_FSUB = 238, + Mips_G_STRICT_FMUL = 239, + Mips_G_STRICT_FDIV = 240, + Mips_G_STRICT_FREM = 241, + Mips_G_STRICT_FMA = 242, + Mips_G_STRICT_FSQRT = 243, + Mips_G_STRICT_FLDEXP = 244, + Mips_G_READ_REGISTER = 245, + Mips_G_WRITE_REGISTER = 246, + Mips_G_MEMCPY = 247, + Mips_G_MEMCPY_INLINE = 248, + Mips_G_MEMMOVE = 249, + Mips_G_MEMSET = 250, + Mips_G_BZERO = 251, + Mips_G_VECREDUCE_SEQ_FADD = 252, + Mips_G_VECREDUCE_SEQ_FMUL = 253, + Mips_G_VECREDUCE_FADD = 254, + Mips_G_VECREDUCE_FMUL = 255, + Mips_G_VECREDUCE_FMAX = 256, + Mips_G_VECREDUCE_FMIN = 257, + Mips_G_VECREDUCE_FMAXIMUM = 258, + Mips_G_VECREDUCE_FMINIMUM = 259, + Mips_G_VECREDUCE_ADD = 260, + Mips_G_VECREDUCE_MUL = 261, + Mips_G_VECREDUCE_AND = 262, + Mips_G_VECREDUCE_OR = 263, + Mips_G_VECREDUCE_XOR = 264, + Mips_G_VECREDUCE_SMAX = 265, + Mips_G_VECREDUCE_SMIN = 266, + Mips_G_VECREDUCE_UMAX = 267, + Mips_G_VECREDUCE_UMIN = 268, + Mips_G_SBFX = 269, + Mips_G_UBFX = 270, + Mips_ABSMacro = 271, + Mips_ADJCALLSTACKDOWN = 272, + Mips_ADJCALLSTACKDOWN_NM = 273, + Mips_ADJCALLSTACKUP = 274, + Mips_ADJCALLSTACKUP_NM = 275, + Mips_ALIGN_NM = 276, + Mips_AND_V_D_PSEUDO = 277, + Mips_AND_V_H_PSEUDO = 278, + Mips_AND_V_W_PSEUDO = 279, + Mips_ATOMIC_CMP_SWAP_I16 = 280, + Mips_ATOMIC_CMP_SWAP_I16_POSTRA = 281, + Mips_ATOMIC_CMP_SWAP_I32 = 282, + Mips_ATOMIC_CMP_SWAP_I32_POSTRA = 283, + Mips_ATOMIC_CMP_SWAP_I64 = 284, + Mips_ATOMIC_CMP_SWAP_I64_POSTRA = 285, + Mips_ATOMIC_CMP_SWAP_I8 = 286, + Mips_ATOMIC_CMP_SWAP_I8_POSTRA = 287, + Mips_ATOMIC_LOAD_ADD_I16 = 288, + Mips_ATOMIC_LOAD_ADD_I16_POSTRA = 289, + Mips_ATOMIC_LOAD_ADD_I32 = 290, + Mips_ATOMIC_LOAD_ADD_I32_POSTRA = 291, + Mips_ATOMIC_LOAD_ADD_I64 = 292, + Mips_ATOMIC_LOAD_ADD_I64_POSTRA = 293, + Mips_ATOMIC_LOAD_ADD_I8 = 294, + Mips_ATOMIC_LOAD_ADD_I8_POSTRA = 295, + Mips_ATOMIC_LOAD_AND_I16 = 296, + Mips_ATOMIC_LOAD_AND_I16_POSTRA = 297, + Mips_ATOMIC_LOAD_AND_I32 = 298, + Mips_ATOMIC_LOAD_AND_I32_POSTRA = 299, + Mips_ATOMIC_LOAD_AND_I64 = 300, + Mips_ATOMIC_LOAD_AND_I64_POSTRA = 301, + Mips_ATOMIC_LOAD_AND_I8 = 302, + Mips_ATOMIC_LOAD_AND_I8_POSTRA = 303, + Mips_ATOMIC_LOAD_MAX_I16 = 304, + Mips_ATOMIC_LOAD_MAX_I16_POSTRA = 305, + Mips_ATOMIC_LOAD_MAX_I32 = 306, + Mips_ATOMIC_LOAD_MAX_I32_POSTRA = 307, + Mips_ATOMIC_LOAD_MAX_I64 = 308, + Mips_ATOMIC_LOAD_MAX_I64_POSTRA = 309, + Mips_ATOMIC_LOAD_MAX_I8 = 310, + Mips_ATOMIC_LOAD_MAX_I8_POSTRA = 311, + Mips_ATOMIC_LOAD_MIN_I16 = 312, + Mips_ATOMIC_LOAD_MIN_I16_POSTRA = 313, + Mips_ATOMIC_LOAD_MIN_I32 = 314, + Mips_ATOMIC_LOAD_MIN_I32_POSTRA = 315, + Mips_ATOMIC_LOAD_MIN_I64 = 316, + Mips_ATOMIC_LOAD_MIN_I64_POSTRA = 317, + Mips_ATOMIC_LOAD_MIN_I8 = 318, + Mips_ATOMIC_LOAD_MIN_I8_POSTRA = 319, + Mips_ATOMIC_LOAD_NAND_I16 = 320, + Mips_ATOMIC_LOAD_NAND_I16_POSTRA = 321, + Mips_ATOMIC_LOAD_NAND_I32 = 322, + Mips_ATOMIC_LOAD_NAND_I32_POSTRA = 323, + Mips_ATOMIC_LOAD_NAND_I64 = 324, + Mips_ATOMIC_LOAD_NAND_I64_POSTRA = 325, + Mips_ATOMIC_LOAD_NAND_I8 = 326, + Mips_ATOMIC_LOAD_NAND_I8_POSTRA = 327, + Mips_ATOMIC_LOAD_OR_I16 = 328, + Mips_ATOMIC_LOAD_OR_I16_POSTRA = 329, + Mips_ATOMIC_LOAD_OR_I32 = 330, + Mips_ATOMIC_LOAD_OR_I32_POSTRA = 331, + Mips_ATOMIC_LOAD_OR_I64 = 332, + Mips_ATOMIC_LOAD_OR_I64_POSTRA = 333, + Mips_ATOMIC_LOAD_OR_I8 = 334, + Mips_ATOMIC_LOAD_OR_I8_POSTRA = 335, + Mips_ATOMIC_LOAD_SUB_I16 = 336, + Mips_ATOMIC_LOAD_SUB_I16_POSTRA = 337, + Mips_ATOMIC_LOAD_SUB_I32 = 338, + Mips_ATOMIC_LOAD_SUB_I32_POSTRA = 339, + Mips_ATOMIC_LOAD_SUB_I64 = 340, + Mips_ATOMIC_LOAD_SUB_I64_POSTRA = 341, + Mips_ATOMIC_LOAD_SUB_I8 = 342, + Mips_ATOMIC_LOAD_SUB_I8_POSTRA = 343, + Mips_ATOMIC_LOAD_UMAX_I16 = 344, + Mips_ATOMIC_LOAD_UMAX_I16_POSTRA = 345, + Mips_ATOMIC_LOAD_UMAX_I32 = 346, + Mips_ATOMIC_LOAD_UMAX_I32_POSTRA = 347, + Mips_ATOMIC_LOAD_UMAX_I64 = 348, + Mips_ATOMIC_LOAD_UMAX_I64_POSTRA = 349, + Mips_ATOMIC_LOAD_UMAX_I8 = 350, + Mips_ATOMIC_LOAD_UMAX_I8_POSTRA = 351, + Mips_ATOMIC_LOAD_UMIN_I16 = 352, + Mips_ATOMIC_LOAD_UMIN_I16_POSTRA = 353, + Mips_ATOMIC_LOAD_UMIN_I32 = 354, + Mips_ATOMIC_LOAD_UMIN_I32_POSTRA = 355, + Mips_ATOMIC_LOAD_UMIN_I64 = 356, + Mips_ATOMIC_LOAD_UMIN_I64_POSTRA = 357, + Mips_ATOMIC_LOAD_UMIN_I8 = 358, + Mips_ATOMIC_LOAD_UMIN_I8_POSTRA = 359, + Mips_ATOMIC_LOAD_XOR_I16 = 360, + Mips_ATOMIC_LOAD_XOR_I16_POSTRA = 361, + Mips_ATOMIC_LOAD_XOR_I32 = 362, + Mips_ATOMIC_LOAD_XOR_I32_POSTRA = 363, + Mips_ATOMIC_LOAD_XOR_I64 = 364, + Mips_ATOMIC_LOAD_XOR_I64_POSTRA = 365, + Mips_ATOMIC_LOAD_XOR_I8 = 366, + Mips_ATOMIC_LOAD_XOR_I8_POSTRA = 367, + Mips_ATOMIC_SWAP_I16 = 368, + Mips_ATOMIC_SWAP_I16_POSTRA = 369, + Mips_ATOMIC_SWAP_I32 = 370, + Mips_ATOMIC_SWAP_I32_POSTRA = 371, + Mips_ATOMIC_SWAP_I64 = 372, + Mips_ATOMIC_SWAP_I64_POSTRA = 373, + Mips_ATOMIC_SWAP_I8 = 374, + Mips_ATOMIC_SWAP_I8_POSTRA = 375, + Mips_B = 376, + Mips_BAL_BR = 377, + Mips_BAL_BR_MM = 378, + Mips_BEQLImmMacro = 379, + Mips_BGE = 380, + Mips_BGEImmMacro = 381, + Mips_BGEL = 382, + Mips_BGELImmMacro = 383, + Mips_BGEU = 384, + Mips_BGEUImmMacro = 385, + Mips_BGEUL = 386, + Mips_BGEULImmMacro = 387, + Mips_BGT = 388, + Mips_BGTImmMacro = 389, + Mips_BGTL = 390, + Mips_BGTLImmMacro = 391, + Mips_BGTU = 392, + Mips_BGTUImmMacro = 393, + Mips_BGTUL = 394, + Mips_BGTULImmMacro = 395, + Mips_BLE = 396, + Mips_BLEImmMacro = 397, + Mips_BLEL = 398, + Mips_BLELImmMacro = 399, + Mips_BLEU = 400, + Mips_BLEUImmMacro = 401, + Mips_BLEUL = 402, + Mips_BLEULImmMacro = 403, + Mips_BLT = 404, + Mips_BLTImmMacro = 405, + Mips_BLTL = 406, + Mips_BLTLImmMacro = 407, + Mips_BLTU = 408, + Mips_BLTUImmMacro = 409, + Mips_BLTUL = 410, + Mips_BLTULImmMacro = 411, + Mips_BNELImmMacro = 412, + Mips_BPOSGE32_PSEUDO = 413, + Mips_BSEL_D_PSEUDO = 414, + Mips_BSEL_FD_PSEUDO = 415, + Mips_BSEL_FW_PSEUDO = 416, + Mips_BSEL_H_PSEUDO = 417, + Mips_BSEL_W_PSEUDO = 418, + Mips_B_MM = 419, + Mips_B_MMR6_Pseudo = 420, + Mips_B_MM_Pseudo = 421, + Mips_BeqImm = 422, + Mips_BneImm = 423, + Mips_BteqzT8CmpX16 = 424, + Mips_BteqzT8CmpiX16 = 425, + Mips_BteqzT8SltX16 = 426, + Mips_BteqzT8SltiX16 = 427, + Mips_BteqzT8SltiuX16 = 428, + Mips_BteqzT8SltuX16 = 429, + Mips_BtnezT8CmpX16 = 430, + Mips_BtnezT8CmpiX16 = 431, + Mips_BtnezT8SltX16 = 432, + Mips_BtnezT8SltiX16 = 433, + Mips_BtnezT8SltiuX16 = 434, + Mips_BtnezT8SltuX16 = 435, + Mips_BuildPairF64 = 436, + Mips_BuildPairF64_64 = 437, + Mips_CFTC1 = 438, + Mips_CONSTPOOL_ENTRY = 439, + Mips_COPY_FD_PSEUDO = 440, + Mips_COPY_FW_PSEUDO = 441, + Mips_CTTC1 = 442, + Mips_Constant32 = 443, + Mips_DMULImmMacro = 444, + Mips_DMULMacro = 445, + Mips_DMULOMacro = 446, + Mips_DMULOUMacro = 447, + Mips_DROL = 448, + Mips_DROLImm = 449, + Mips_DROR = 450, + Mips_DRORImm = 451, + Mips_DSDivIMacro = 452, + Mips_DSDivMacro = 453, + Mips_DSRemIMacro = 454, + Mips_DSRemMacro = 455, + Mips_DUDivIMacro = 456, + Mips_DUDivMacro = 457, + Mips_DURemIMacro = 458, + Mips_DURemMacro = 459, + Mips_ERet = 460, + Mips_ExtractElementF64 = 461, + Mips_ExtractElementF64_64 = 462, + Mips_FABS_D = 463, + Mips_FABS_W = 464, + Mips_FEXP2_D_1_PSEUDO = 465, + Mips_FEXP2_W_1_PSEUDO = 466, + Mips_FILL_FD_PSEUDO = 467, + Mips_FILL_FW_PSEUDO = 468, + Mips_GotPrologue16 = 469, + Mips_INSERT_B_VIDX64_PSEUDO = 470, + Mips_INSERT_B_VIDX_PSEUDO = 471, + Mips_INSERT_D_VIDX64_PSEUDO = 472, + Mips_INSERT_D_VIDX_PSEUDO = 473, + Mips_INSERT_FD_PSEUDO = 474, + Mips_INSERT_FD_VIDX64_PSEUDO = 475, + Mips_INSERT_FD_VIDX_PSEUDO = 476, + Mips_INSERT_FW_PSEUDO = 477, + Mips_INSERT_FW_VIDX64_PSEUDO = 478, + Mips_INSERT_FW_VIDX_PSEUDO = 479, + Mips_INSERT_H_VIDX64_PSEUDO = 480, + Mips_INSERT_H_VIDX_PSEUDO = 481, + Mips_INSERT_W_VIDX64_PSEUDO = 482, + Mips_INSERT_W_VIDX_PSEUDO = 483, + Mips_JALR64Pseudo = 484, + Mips_JALRCPseudo = 485, + Mips_JALRHB64Pseudo = 486, + Mips_JALRHBPseudo = 487, + Mips_JALRPseudo = 488, + Mips_JAL_MMR6 = 489, + Mips_JalOneReg = 490, + Mips_JalTwoReg = 491, + Mips_LDMacro = 492, + Mips_LDR_D = 493, + Mips_LDR_W = 494, + Mips_LD_F16 = 495, + Mips_LOAD_ACC128 = 496, + Mips_LOAD_ACC64 = 497, + Mips_LOAD_ACC64DSP = 498, + Mips_LOAD_CCOND_DSP = 499, + Mips_LONG_BRANCH_ADDiu = 500, + Mips_LONG_BRANCH_ADDiu2Op = 501, + Mips_LONG_BRANCH_DADDiu = 502, + Mips_LONG_BRANCH_DADDiu2Op = 503, + Mips_LONG_BRANCH_LUi = 504, + Mips_LONG_BRANCH_LUi2Op = 505, + Mips_LONG_BRANCH_LUi2Op_64 = 506, + Mips_LWM_MM = 507, + Mips_LoadAddrImm32 = 508, + Mips_LoadAddrImm64 = 509, + Mips_LoadAddrReg32 = 510, + Mips_LoadAddrReg64 = 511, + Mips_LoadImm32 = 512, + Mips_LoadImm64 = 513, + Mips_LoadImmDoubleFGR = 514, + Mips_LoadImmDoubleFGR_32 = 515, + Mips_LoadImmDoubleGPR = 516, + Mips_LoadImmSingleFGR = 517, + Mips_LoadImmSingleGPR = 518, + Mips_LoadJumpTableOffset = 519, + Mips_LwConstant32 = 520, + Mips_MFTACX = 521, + Mips_MFTACX_NM = 522, + Mips_MFTC0 = 523, + Mips_MFTC0_NM = 524, + Mips_MFTC1 = 525, + Mips_MFTDSP = 526, + Mips_MFTDSP_NM = 527, + Mips_MFTGPR = 528, + Mips_MFTGPR_NM = 529, + Mips_MFTHC1 = 530, + Mips_MFTHI = 531, + Mips_MFTHI_NM = 532, + Mips_MFTLO = 533, + Mips_MFTLO_NM = 534, + Mips_MIPSeh_return32 = 535, + Mips_MIPSeh_return64 = 536, + Mips_MSA_FP_EXTEND_D_PSEUDO = 537, + Mips_MSA_FP_EXTEND_W_PSEUDO = 538, + Mips_MSA_FP_ROUND_D_PSEUDO = 539, + Mips_MSA_FP_ROUND_W_PSEUDO = 540, + Mips_MTTACX = 541, + Mips_MTTACX_NM = 542, + Mips_MTTC0 = 543, + Mips_MTTC0_NM = 544, + Mips_MTTC1 = 545, + Mips_MTTDSP = 546, + Mips_MTTDSP_NM = 547, + Mips_MTTGPR = 548, + Mips_MTTGPR_NM = 549, + Mips_MTTHC1 = 550, + Mips_MTTHI = 551, + Mips_MTTHI_NM = 552, + Mips_MTTLO = 553, + Mips_MTTLO_NM = 554, + Mips_MULImmMacro = 555, + Mips_MULOMacro = 556, + Mips_MULOUMacro = 557, + Mips_MUSTTAILCALLREG_NM = 558, + Mips_MUSTTAILCALL_NM = 559, + Mips_MultRxRy16 = 560, + Mips_MultRxRyRz16 = 561, + Mips_MultuRxRy16 = 562, + Mips_MultuRxRyRz16 = 563, + Mips_NOP = 564, + Mips_NORImm = 565, + Mips_NORImm64 = 566, + Mips_NOR_V_D_PSEUDO = 567, + Mips_NOR_V_H_PSEUDO = 568, + Mips_NOR_V_W_PSEUDO = 569, + Mips_OR_V_D_PSEUDO = 570, + Mips_OR_V_H_PSEUDO = 571, + Mips_OR_V_W_PSEUDO = 572, + Mips_PseudoADDIU_NM = 573, + Mips_PseudoANDI_NM = 574, + Mips_PseudoCMPU_EQ_QB = 575, + Mips_PseudoCMPU_LE_QB = 576, + Mips_PseudoCMPU_LT_QB = 577, + Mips_PseudoCMP_EQ_PH = 578, + Mips_PseudoCMP_LE_PH = 579, + Mips_PseudoCMP_LT_PH = 580, + Mips_PseudoCVT_D32_W = 581, + Mips_PseudoCVT_D64_L = 582, + Mips_PseudoCVT_D64_W = 583, + Mips_PseudoCVT_S_L = 584, + Mips_PseudoCVT_S_W = 585, + Mips_PseudoDMULT = 586, + Mips_PseudoDMULTu = 587, + Mips_PseudoDSDIV = 588, + Mips_PseudoDUDIV = 589, + Mips_PseudoD_SELECT_I = 590, + Mips_PseudoD_SELECT_I64 = 591, + Mips_PseudoIndirectBranch = 592, + Mips_PseudoIndirectBranch64 = 593, + Mips_PseudoIndirectBranch64R6 = 594, + Mips_PseudoIndirectBranchNM = 595, + Mips_PseudoIndirectBranchR6 = 596, + Mips_PseudoIndirectBranch_MM = 597, + Mips_PseudoIndirectBranch_MMR6 = 598, + Mips_PseudoIndirectHazardBranch = 599, + Mips_PseudoIndirectHazardBranch64 = 600, + Mips_PseudoIndrectHazardBranch64R6 = 601, + Mips_PseudoIndrectHazardBranchR6 = 602, + Mips_PseudoLA_NM = 603, + Mips_PseudoLI_NM = 604, + Mips_PseudoMADD = 605, + Mips_PseudoMADDU = 606, + Mips_PseudoMADDU_MM = 607, + Mips_PseudoMADD_MM = 608, + Mips_PseudoMFHI = 609, + Mips_PseudoMFHI64 = 610, + Mips_PseudoMFHI_MM = 611, + Mips_PseudoMFLO = 612, + Mips_PseudoMFLO64 = 613, + Mips_PseudoMFLO_MM = 614, + Mips_PseudoMSUB = 615, + Mips_PseudoMSUBU = 616, + Mips_PseudoMSUBU_MM = 617, + Mips_PseudoMSUB_MM = 618, + Mips_PseudoMTLOHI = 619, + Mips_PseudoMTLOHI64 = 620, + Mips_PseudoMTLOHI_DSP = 621, + Mips_PseudoMTLOHI_MM = 622, + Mips_PseudoMULT = 623, + Mips_PseudoMULT_MM = 624, + Mips_PseudoMULTu = 625, + Mips_PseudoMULTu_MM = 626, + Mips_PseudoPICK_PH = 627, + Mips_PseudoPICK_QB = 628, + Mips_PseudoReturn = 629, + Mips_PseudoReturn64 = 630, + Mips_PseudoReturnNM = 631, + Mips_PseudoSDIV = 632, + Mips_PseudoSELECTFP_F_D32 = 633, + Mips_PseudoSELECTFP_F_D64 = 634, + Mips_PseudoSELECTFP_F_I = 635, + Mips_PseudoSELECTFP_F_I64 = 636, + Mips_PseudoSELECTFP_F_S = 637, + Mips_PseudoSELECTFP_T_D32 = 638, + Mips_PseudoSELECTFP_T_D64 = 639, + Mips_PseudoSELECTFP_T_I = 640, + Mips_PseudoSELECTFP_T_I64 = 641, + Mips_PseudoSELECTFP_T_S = 642, + Mips_PseudoSELECT_D32 = 643, + Mips_PseudoSELECT_D64 = 644, + Mips_PseudoSELECT_I = 645, + Mips_PseudoSELECT_I64 = 646, + Mips_PseudoSELECT_S = 647, + Mips_PseudoSUBU_NM = 648, + Mips_PseudoTRUNC_W_D = 649, + Mips_PseudoTRUNC_W_D32 = 650, + Mips_PseudoTRUNC_W_S = 651, + Mips_PseudoUDIV = 652, + Mips_ROL = 653, + Mips_ROLImm = 654, + Mips_ROR = 655, + Mips_RORImm = 656, + Mips_RetRA = 657, + Mips_RetRA16 = 658, + Mips_SDC1_M1 = 659, + Mips_SDIV_MM_Pseudo = 660, + Mips_SDMacro = 661, + Mips_SDivIMacro = 662, + Mips_SDivMacro = 663, + Mips_SEQIMacro = 664, + Mips_SEQMacro = 665, + Mips_SGE = 666, + Mips_SGEImm = 667, + Mips_SGEImm64 = 668, + Mips_SGEU = 669, + Mips_SGEUImm = 670, + Mips_SGEUImm64 = 671, + Mips_SGTImm = 672, + Mips_SGTImm64 = 673, + Mips_SGTUImm = 674, + Mips_SGTUImm64 = 675, + Mips_SLE = 676, + Mips_SLEImm = 677, + Mips_SLEImm64 = 678, + Mips_SLEU = 679, + Mips_SLEUImm = 680, + Mips_SLEUImm64 = 681, + Mips_SLTImm64 = 682, + Mips_SLTUImm64 = 683, + Mips_SNEIMacro = 684, + Mips_SNEMacro = 685, + Mips_SNZ_B_PSEUDO = 686, + Mips_SNZ_D_PSEUDO = 687, + Mips_SNZ_H_PSEUDO = 688, + Mips_SNZ_V_PSEUDO = 689, + Mips_SNZ_W_PSEUDO = 690, + Mips_SRemIMacro = 691, + Mips_SRemMacro = 692, + Mips_STORE_ACC128 = 693, + Mips_STORE_ACC64 = 694, + Mips_STORE_ACC64DSP = 695, + Mips_STORE_CCOND_DSP = 696, + Mips_STR_D = 697, + Mips_STR_W = 698, + Mips_ST_F16 = 699, + Mips_SWM_MM = 700, + Mips_SZ_B_PSEUDO = 701, + Mips_SZ_D_PSEUDO = 702, + Mips_SZ_H_PSEUDO = 703, + Mips_SZ_V_PSEUDO = 704, + Mips_SZ_W_PSEUDO = 705, + Mips_SaaAddr = 706, + Mips_SaadAddr = 707, + Mips_SelBeqZ = 708, + Mips_SelBneZ = 709, + Mips_SelTBteqZCmp = 710, + Mips_SelTBteqZCmpi = 711, + Mips_SelTBteqZSlt = 712, + Mips_SelTBteqZSlti = 713, + Mips_SelTBteqZSltiu = 714, + Mips_SelTBteqZSltu = 715, + Mips_SelTBtneZCmp = 716, + Mips_SelTBtneZCmpi = 717, + Mips_SelTBtneZSlt = 718, + Mips_SelTBtneZSlti = 719, + Mips_SelTBtneZSltiu = 720, + Mips_SelTBtneZSltu = 721, + Mips_SltCCRxRy16 = 722, + Mips_SltiCCRxImmX16 = 723, + Mips_SltiuCCRxImmX16 = 724, + Mips_SltuCCRxRy16 = 725, + Mips_SltuRxRyRz16 = 726, + Mips_TAILCALL = 727, + Mips_TAILCALL64R6REG = 728, + Mips_TAILCALLHB64R6REG = 729, + Mips_TAILCALLHBR6REG = 730, + Mips_TAILCALLR6REG = 731, + Mips_TAILCALLREG = 732, + Mips_TAILCALLREG64 = 733, + Mips_TAILCALLREGHB = 734, + Mips_TAILCALLREGHB64 = 735, + Mips_TAILCALLREG_MM = 736, + Mips_TAILCALLREG_MMR6 = 737, + Mips_TAILCALLREG_NM = 738, + Mips_TAILCALL_MM = 739, + Mips_TAILCALL_MMR6 = 740, + Mips_TAILCALL_NM = 741, + Mips_TRAP = 742, + Mips_TRAP_MM = 743, + Mips_UDIV_MM_Pseudo = 744, + Mips_UDivIMacro = 745, + Mips_UDivMacro = 746, + Mips_URemIMacro = 747, + Mips_URemMacro = 748, + Mips_Ulh = 749, + Mips_Ulhu = 750, + Mips_Ulw = 751, + Mips_Ush = 752, + Mips_Usw = 753, + Mips_XOR_V_D_PSEUDO = 754, + Mips_XOR_V_H_PSEUDO = 755, + Mips_XOR_V_W_PSEUDO = 756, + Mips_ABSQ_S_PH = 757, + Mips_ABSQ_S_PH_MM = 758, + Mips_ABSQ_S_QB = 759, + Mips_ABSQ_S_QB_MMR2 = 760, + Mips_ABSQ_S_W = 761, + Mips_ABSQ_S_W_MM = 762, + Mips_ADD = 763, + Mips_ADDIU48_NM = 764, + Mips_ADDIUGP48_NM = 765, + Mips_ADDIUGPB_NM = 766, + Mips_ADDIUGPW_NM = 767, + Mips_ADDIUNEG_NM = 768, + Mips_ADDIUPC = 769, + Mips_ADDIUPC_MM = 770, + Mips_ADDIUPC_MMR6 = 771, + Mips_ADDIUR1SP_MM = 772, + Mips_ADDIUR1SP_NM = 773, + Mips_ADDIUR2_MM = 774, + Mips_ADDIUR2_NM = 775, + Mips_ADDIURS5_NM = 776, + Mips_ADDIUS5_MM = 777, + Mips_ADDIUSP_MM = 778, + Mips_ADDIU_MMR6 = 779, + Mips_ADDIU_NM = 780, + Mips_ADDQH_PH = 781, + Mips_ADDQH_PH_MMR2 = 782, + Mips_ADDQH_R_PH = 783, + Mips_ADDQH_R_PH_MMR2 = 784, + Mips_ADDQH_R_W = 785, + Mips_ADDQH_R_W_MMR2 = 786, + Mips_ADDQH_W = 787, + Mips_ADDQH_W_MMR2 = 788, + Mips_ADDQ_PH = 789, + Mips_ADDQ_PH_MM = 790, + Mips_ADDQ_S_PH = 791, + Mips_ADDQ_S_PH_MM = 792, + Mips_ADDQ_S_W = 793, + Mips_ADDQ_S_W_MM = 794, + Mips_ADDR_PS64 = 795, + Mips_ADDSC = 796, + Mips_ADDSC_MM = 797, + Mips_ADDS_A_B = 798, + Mips_ADDS_A_D = 799, + Mips_ADDS_A_H = 800, + Mips_ADDS_A_W = 801, + Mips_ADDS_S_B = 802, + Mips_ADDS_S_D = 803, + Mips_ADDS_S_H = 804, + Mips_ADDS_S_W = 805, + Mips_ADDS_U_B = 806, + Mips_ADDS_U_D = 807, + Mips_ADDS_U_H = 808, + Mips_ADDS_U_W = 809, + Mips_ADDU16_MM = 810, + Mips_ADDU16_MMR6 = 811, + Mips_ADDUH_QB = 812, + Mips_ADDUH_QB_MMR2 = 813, + Mips_ADDUH_R_QB = 814, + Mips_ADDUH_R_QB_MMR2 = 815, + Mips_ADDU_MMR6 = 816, + Mips_ADDU_PH = 817, + Mips_ADDU_PH_MMR2 = 818, + Mips_ADDU_QB = 819, + Mips_ADDU_QB_MM = 820, + Mips_ADDU_S_PH = 821, + Mips_ADDU_S_PH_MMR2 = 822, + Mips_ADDU_S_QB = 823, + Mips_ADDU_S_QB_MM = 824, + Mips_ADDVI_B = 825, + Mips_ADDVI_D = 826, + Mips_ADDVI_H = 827, + Mips_ADDVI_W = 828, + Mips_ADDV_B = 829, + Mips_ADDV_D = 830, + Mips_ADDV_H = 831, + Mips_ADDV_W = 832, + Mips_ADDWC = 833, + Mips_ADDWC_MM = 834, + Mips_ADD_A_B = 835, + Mips_ADD_A_D = 836, + Mips_ADD_A_H = 837, + Mips_ADD_A_W = 838, + Mips_ADD_MM = 839, + Mips_ADD_MMR6 = 840, + Mips_ADD_NM = 841, + Mips_ADDi = 842, + Mips_ADDi_MM = 843, + Mips_ADDiu = 844, + Mips_ADDiu_MM = 845, + Mips_ADDu = 846, + Mips_ADDu16_NM = 847, + Mips_ADDu4x4_NM = 848, + Mips_ADDu_MM = 849, + Mips_ADDu_NM = 850, + Mips_ALIGN = 851, + Mips_ALIGN_MMR6 = 852, + Mips_ALUIPC = 853, + Mips_ALUIPC_MMR6 = 854, + Mips_ALUIPC_NM = 855, + Mips_AND = 856, + Mips_AND16_MM = 857, + Mips_AND16_MMR6 = 858, + Mips_AND16_NM = 859, + Mips_AND64 = 860, + Mips_ANDI16_MM = 861, + Mips_ANDI16_MMR6 = 862, + Mips_ANDI16_NM = 863, + Mips_ANDI_B = 864, + Mips_ANDI_MMR6 = 865, + Mips_ANDI_NM = 866, + Mips_AND_MM = 867, + Mips_AND_MMR6 = 868, + Mips_AND_NM = 869, + Mips_AND_V = 870, + Mips_ANDi = 871, + Mips_ANDi64 = 872, + Mips_ANDi_MM = 873, + Mips_APPEND = 874, + Mips_APPEND_MMR2 = 875, + Mips_ASUB_S_B = 876, + Mips_ASUB_S_D = 877, + Mips_ASUB_S_H = 878, + Mips_ASUB_S_W = 879, + Mips_ASUB_U_B = 880, + Mips_ASUB_U_D = 881, + Mips_ASUB_U_H = 882, + Mips_ASUB_U_W = 883, + Mips_AUI = 884, + Mips_AUIPC = 885, + Mips_AUIPC_MMR6 = 886, + Mips_AUI_MMR6 = 887, + Mips_AVER_S_B = 888, + Mips_AVER_S_D = 889, + Mips_AVER_S_H = 890, + Mips_AVER_S_W = 891, + Mips_AVER_U_B = 892, + Mips_AVER_U_D = 893, + Mips_AVER_U_H = 894, + Mips_AVER_U_W = 895, + Mips_AVE_S_B = 896, + Mips_AVE_S_D = 897, + Mips_AVE_S_H = 898, + Mips_AVE_S_W = 899, + Mips_AVE_U_B = 900, + Mips_AVE_U_D = 901, + Mips_AVE_U_H = 902, + Mips_AVE_U_W = 903, + Mips_AddiuRxImmX16 = 904, + Mips_AddiuRxPcImmX16 = 905, + Mips_AddiuRxRxImm16 = 906, + Mips_AddiuRxRxImmX16 = 907, + Mips_AddiuRxRyOffMemX16 = 908, + Mips_AddiuSpImm16 = 909, + Mips_AddiuSpImmX16 = 910, + Mips_AdduRxRyRz16 = 911, + Mips_AndRxRxRy16 = 912, + Mips_B16_MM = 913, + Mips_BADDu = 914, + Mips_BAL = 915, + Mips_BALC = 916, + Mips_BALC16_NM = 917, + Mips_BALC_MMR6 = 918, + Mips_BALC_NM = 919, + Mips_BALIGN = 920, + Mips_BALIGN_MMR2 = 921, + Mips_BALRSC_NM = 922, + Mips_BBEQZC_NM = 923, + Mips_BBIT0 = 924, + Mips_BBIT032 = 925, + Mips_BBIT1 = 926, + Mips_BBIT132 = 927, + Mips_BBNEZC_NM = 928, + Mips_BC = 929, + Mips_BC16_MMR6 = 930, + Mips_BC16_NM = 931, + Mips_BC1EQZ = 932, + Mips_BC1EQZC_MMR6 = 933, + Mips_BC1F = 934, + Mips_BC1FL = 935, + Mips_BC1F_MM = 936, + Mips_BC1NEZ = 937, + Mips_BC1NEZC_MMR6 = 938, + Mips_BC1T = 939, + Mips_BC1TL = 940, + Mips_BC1T_MM = 941, + Mips_BC2EQZ = 942, + Mips_BC2EQZC_MMR6 = 943, + Mips_BC2NEZ = 944, + Mips_BC2NEZC_MMR6 = 945, + Mips_BCLRI_B = 946, + Mips_BCLRI_D = 947, + Mips_BCLRI_H = 948, + Mips_BCLRI_W = 949, + Mips_BCLR_B = 950, + Mips_BCLR_D = 951, + Mips_BCLR_H = 952, + Mips_BCLR_W = 953, + Mips_BC_MMR6 = 954, + Mips_BC_NM = 955, + Mips_BEQ = 956, + Mips_BEQ64 = 957, + Mips_BEQC = 958, + Mips_BEQC16_NM = 959, + Mips_BEQC64 = 960, + Mips_BEQC_MMR6 = 961, + Mips_BEQC_NM = 962, + Mips_BEQCzero_NM = 963, + Mips_BEQIC_NM = 964, + Mips_BEQL = 965, + Mips_BEQZ16_MM = 966, + Mips_BEQZALC = 967, + Mips_BEQZALC_MMR6 = 968, + Mips_BEQZC = 969, + Mips_BEQZC16_MMR6 = 970, + Mips_BEQZC16_NM = 971, + Mips_BEQZC64 = 972, + Mips_BEQZC_MM = 973, + Mips_BEQZC_MMR6 = 974, + Mips_BEQZC_NM = 975, + Mips_BEQ_MM = 976, + Mips_BGEC = 977, + Mips_BGEC64 = 978, + Mips_BGEC_MMR6 = 979, + Mips_BGEC_NM = 980, + Mips_BGEIC_NM = 981, + Mips_BGEIUC_NM = 982, + Mips_BGEUC = 983, + Mips_BGEUC64 = 984, + Mips_BGEUC_MMR6 = 985, + Mips_BGEUC_NM = 986, + Mips_BGEZ = 987, + Mips_BGEZ64 = 988, + Mips_BGEZAL = 989, + Mips_BGEZALC = 990, + Mips_BGEZALC_MMR6 = 991, + Mips_BGEZALL = 992, + Mips_BGEZALS_MM = 993, + Mips_BGEZAL_MM = 994, + Mips_BGEZC = 995, + Mips_BGEZC64 = 996, + Mips_BGEZC_MMR6 = 997, + Mips_BGEZL = 998, + Mips_BGEZ_MM = 999, + Mips_BGTZ = 1000, + Mips_BGTZ64 = 1001, + Mips_BGTZALC = 1002, + Mips_BGTZALC_MMR6 = 1003, + Mips_BGTZC = 1004, + Mips_BGTZC64 = 1005, + Mips_BGTZC_MMR6 = 1006, + Mips_BGTZL = 1007, + Mips_BGTZ_MM = 1008, + Mips_BINSLI_B = 1009, + Mips_BINSLI_D = 1010, + Mips_BINSLI_H = 1011, + Mips_BINSLI_W = 1012, + Mips_BINSL_B = 1013, + Mips_BINSL_D = 1014, + Mips_BINSL_H = 1015, + Mips_BINSL_W = 1016, + Mips_BINSRI_B = 1017, + Mips_BINSRI_D = 1018, + Mips_BINSRI_H = 1019, + Mips_BINSRI_W = 1020, + Mips_BINSR_B = 1021, + Mips_BINSR_D = 1022, + Mips_BINSR_H = 1023, + Mips_BINSR_W = 1024, + Mips_BITREV = 1025, + Mips_BITREVW_NM = 1026, + Mips_BITREV_MM = 1027, + Mips_BITSWAP = 1028, + Mips_BITSWAP_MMR6 = 1029, + Mips_BLEZ = 1030, + Mips_BLEZ64 = 1031, + Mips_BLEZALC = 1032, + Mips_BLEZALC_MMR6 = 1033, + Mips_BLEZC = 1034, + Mips_BLEZC64 = 1035, + Mips_BLEZC_MMR6 = 1036, + Mips_BLEZL = 1037, + Mips_BLEZ_MM = 1038, + Mips_BLTC = 1039, + Mips_BLTC64 = 1040, + Mips_BLTC_MMR6 = 1041, + Mips_BLTC_NM = 1042, + Mips_BLTIC_NM = 1043, + Mips_BLTIUC_NM = 1044, + Mips_BLTUC = 1045, + Mips_BLTUC64 = 1046, + Mips_BLTUC_MMR6 = 1047, + Mips_BLTUC_NM = 1048, + Mips_BLTZ = 1049, + Mips_BLTZ64 = 1050, + Mips_BLTZAL = 1051, + Mips_BLTZALC = 1052, + Mips_BLTZALC_MMR6 = 1053, + Mips_BLTZALL = 1054, + Mips_BLTZALS_MM = 1055, + Mips_BLTZAL_MM = 1056, + Mips_BLTZC = 1057, + Mips_BLTZC64 = 1058, + Mips_BLTZC_MMR6 = 1059, + Mips_BLTZL = 1060, + Mips_BLTZ_MM = 1061, + Mips_BMNZI_B = 1062, + Mips_BMNZ_V = 1063, + Mips_BMZI_B = 1064, + Mips_BMZ_V = 1065, + Mips_BNE = 1066, + Mips_BNE64 = 1067, + Mips_BNEC = 1068, + Mips_BNEC16_NM = 1069, + Mips_BNEC64 = 1070, + Mips_BNEC_MMR6 = 1071, + Mips_BNEC_NM = 1072, + Mips_BNECzero_NM = 1073, + Mips_BNEGI_B = 1074, + Mips_BNEGI_D = 1075, + Mips_BNEGI_H = 1076, + Mips_BNEGI_W = 1077, + Mips_BNEG_B = 1078, + Mips_BNEG_D = 1079, + Mips_BNEG_H = 1080, + Mips_BNEG_W = 1081, + Mips_BNEIC_NM = 1082, + Mips_BNEL = 1083, + Mips_BNEZ16_MM = 1084, + Mips_BNEZALC = 1085, + Mips_BNEZALC_MMR6 = 1086, + Mips_BNEZC = 1087, + Mips_BNEZC16_MMR6 = 1088, + Mips_BNEZC16_NM = 1089, + Mips_BNEZC64 = 1090, + Mips_BNEZC_MM = 1091, + Mips_BNEZC_MMR6 = 1092, + Mips_BNEZC_NM = 1093, + Mips_BNE_MM = 1094, + Mips_BNVC = 1095, + Mips_BNVC_MMR6 = 1096, + Mips_BNZ_B = 1097, + Mips_BNZ_D = 1098, + Mips_BNZ_H = 1099, + Mips_BNZ_V = 1100, + Mips_BNZ_W = 1101, + Mips_BOVC = 1102, + Mips_BOVC_MMR6 = 1103, + Mips_BPOSGE32 = 1104, + Mips_BPOSGE32C_MMR3 = 1105, + Mips_BPOSGE32_MM = 1106, + Mips_BREAK = 1107, + Mips_BREAK16_MM = 1108, + Mips_BREAK16_MMR6 = 1109, + Mips_BREAK16_NM = 1110, + Mips_BREAK_MM = 1111, + Mips_BREAK_MMR6 = 1112, + Mips_BREAK_NM = 1113, + Mips_BRSC_NM = 1114, + Mips_BSELI_B = 1115, + Mips_BSEL_V = 1116, + Mips_BSETI_B = 1117, + Mips_BSETI_D = 1118, + Mips_BSETI_H = 1119, + Mips_BSETI_W = 1120, + Mips_BSET_B = 1121, + Mips_BSET_D = 1122, + Mips_BSET_H = 1123, + Mips_BSET_W = 1124, + Mips_BYTEREVW_NM = 1125, + Mips_BZ_B = 1126, + Mips_BZ_D = 1127, + Mips_BZ_H = 1128, + Mips_BZ_V = 1129, + Mips_BZ_W = 1130, + Mips_BeqzRxImm16 = 1131, + Mips_BeqzRxImmX16 = 1132, + Mips_Bimm16 = 1133, + Mips_BimmX16 = 1134, + Mips_BnezRxImm16 = 1135, + Mips_BnezRxImmX16 = 1136, + Mips_Break16 = 1137, + Mips_Bteqz16 = 1138, + Mips_BteqzX16 = 1139, + Mips_Btnez16 = 1140, + Mips_BtnezX16 = 1141, + Mips_CACHE = 1142, + Mips_CACHEE = 1143, + Mips_CACHEE_MM = 1144, + Mips_CACHE_MM = 1145, + Mips_CACHE_MMR6 = 1146, + Mips_CACHE_NM = 1147, + Mips_CACHE_R6 = 1148, + Mips_CEIL_L_D64 = 1149, + Mips_CEIL_L_D_MMR6 = 1150, + Mips_CEIL_L_S = 1151, + Mips_CEIL_L_S_MMR6 = 1152, + Mips_CEIL_W_D32 = 1153, + Mips_CEIL_W_D64 = 1154, + Mips_CEIL_W_D_MMR6 = 1155, + Mips_CEIL_W_MM = 1156, + Mips_CEIL_W_S = 1157, + Mips_CEIL_W_S_MM = 1158, + Mips_CEIL_W_S_MMR6 = 1159, + Mips_CEQI_B = 1160, + Mips_CEQI_D = 1161, + Mips_CEQI_H = 1162, + Mips_CEQI_W = 1163, + Mips_CEQ_B = 1164, + Mips_CEQ_D = 1165, + Mips_CEQ_H = 1166, + Mips_CEQ_W = 1167, + Mips_CFC1 = 1168, + Mips_CFC1_MM = 1169, + Mips_CFC2_MM = 1170, + Mips_CFCMSA = 1171, + Mips_CINS = 1172, + Mips_CINS32 = 1173, + Mips_CINS64_32 = 1174, + Mips_CINS_i32 = 1175, + Mips_CLASS_D = 1176, + Mips_CLASS_D_MMR6 = 1177, + Mips_CLASS_S = 1178, + Mips_CLASS_S_MMR6 = 1179, + Mips_CLEI_S_B = 1180, + Mips_CLEI_S_D = 1181, + Mips_CLEI_S_H = 1182, + Mips_CLEI_S_W = 1183, + Mips_CLEI_U_B = 1184, + Mips_CLEI_U_D = 1185, + Mips_CLEI_U_H = 1186, + Mips_CLEI_U_W = 1187, + Mips_CLE_S_B = 1188, + Mips_CLE_S_D = 1189, + Mips_CLE_S_H = 1190, + Mips_CLE_S_W = 1191, + Mips_CLE_U_B = 1192, + Mips_CLE_U_D = 1193, + Mips_CLE_U_H = 1194, + Mips_CLE_U_W = 1195, + Mips_CLO = 1196, + Mips_CLO_MM = 1197, + Mips_CLO_MMR6 = 1198, + Mips_CLO_NM = 1199, + Mips_CLO_R6 = 1200, + Mips_CLTI_S_B = 1201, + Mips_CLTI_S_D = 1202, + Mips_CLTI_S_H = 1203, + Mips_CLTI_S_W = 1204, + Mips_CLTI_U_B = 1205, + Mips_CLTI_U_D = 1206, + Mips_CLTI_U_H = 1207, + Mips_CLTI_U_W = 1208, + Mips_CLT_S_B = 1209, + Mips_CLT_S_D = 1210, + Mips_CLT_S_H = 1211, + Mips_CLT_S_W = 1212, + Mips_CLT_U_B = 1213, + Mips_CLT_U_D = 1214, + Mips_CLT_U_H = 1215, + Mips_CLT_U_W = 1216, + Mips_CLZ = 1217, + Mips_CLZ_MM = 1218, + Mips_CLZ_MMR6 = 1219, + Mips_CLZ_NM = 1220, + Mips_CLZ_R6 = 1221, + Mips_CMPGDU_EQ_QB = 1222, + Mips_CMPGDU_EQ_QB_MMR2 = 1223, + Mips_CMPGDU_LE_QB = 1224, + Mips_CMPGDU_LE_QB_MMR2 = 1225, + Mips_CMPGDU_LT_QB = 1226, + Mips_CMPGDU_LT_QB_MMR2 = 1227, + Mips_CMPGU_EQ_QB = 1228, + Mips_CMPGU_EQ_QB_MM = 1229, + Mips_CMPGU_LE_QB = 1230, + Mips_CMPGU_LE_QB_MM = 1231, + Mips_CMPGU_LT_QB = 1232, + Mips_CMPGU_LT_QB_MM = 1233, + Mips_CMPU_EQ_QB = 1234, + Mips_CMPU_EQ_QB_MM = 1235, + Mips_CMPU_LE_QB = 1236, + Mips_CMPU_LE_QB_MM = 1237, + Mips_CMPU_LT_QB = 1238, + Mips_CMPU_LT_QB_MM = 1239, + Mips_CMP_AF_D_MMR6 = 1240, + Mips_CMP_AF_S_MMR6 = 1241, + Mips_CMP_EQ_D = 1242, + Mips_CMP_EQ_D_MMR6 = 1243, + Mips_CMP_EQ_PH = 1244, + Mips_CMP_EQ_PH_MM = 1245, + Mips_CMP_EQ_S = 1246, + Mips_CMP_EQ_S_MMR6 = 1247, + Mips_CMP_F_D = 1248, + Mips_CMP_F_S = 1249, + Mips_CMP_LE_D = 1250, + Mips_CMP_LE_D_MMR6 = 1251, + Mips_CMP_LE_PH = 1252, + Mips_CMP_LE_PH_MM = 1253, + Mips_CMP_LE_S = 1254, + Mips_CMP_LE_S_MMR6 = 1255, + Mips_CMP_LT_D = 1256, + Mips_CMP_LT_D_MMR6 = 1257, + Mips_CMP_LT_PH = 1258, + Mips_CMP_LT_PH_MM = 1259, + Mips_CMP_LT_S = 1260, + Mips_CMP_LT_S_MMR6 = 1261, + Mips_CMP_SAF_D = 1262, + Mips_CMP_SAF_D_MMR6 = 1263, + Mips_CMP_SAF_S = 1264, + Mips_CMP_SAF_S_MMR6 = 1265, + Mips_CMP_SEQ_D = 1266, + Mips_CMP_SEQ_D_MMR6 = 1267, + Mips_CMP_SEQ_S = 1268, + Mips_CMP_SEQ_S_MMR6 = 1269, + Mips_CMP_SLE_D = 1270, + Mips_CMP_SLE_D_MMR6 = 1271, + Mips_CMP_SLE_S = 1272, + Mips_CMP_SLE_S_MMR6 = 1273, + Mips_CMP_SLT_D = 1274, + Mips_CMP_SLT_D_MMR6 = 1275, + Mips_CMP_SLT_S = 1276, + Mips_CMP_SLT_S_MMR6 = 1277, + Mips_CMP_SUEQ_D = 1278, + Mips_CMP_SUEQ_D_MMR6 = 1279, + Mips_CMP_SUEQ_S = 1280, + Mips_CMP_SUEQ_S_MMR6 = 1281, + Mips_CMP_SULE_D = 1282, + Mips_CMP_SULE_D_MMR6 = 1283, + Mips_CMP_SULE_S = 1284, + Mips_CMP_SULE_S_MMR6 = 1285, + Mips_CMP_SULT_D = 1286, + Mips_CMP_SULT_D_MMR6 = 1287, + Mips_CMP_SULT_S = 1288, + Mips_CMP_SULT_S_MMR6 = 1289, + Mips_CMP_SUN_D = 1290, + Mips_CMP_SUN_D_MMR6 = 1291, + Mips_CMP_SUN_S = 1292, + Mips_CMP_SUN_S_MMR6 = 1293, + Mips_CMP_UEQ_D = 1294, + Mips_CMP_UEQ_D_MMR6 = 1295, + Mips_CMP_UEQ_S = 1296, + Mips_CMP_UEQ_S_MMR6 = 1297, + Mips_CMP_ULE_D = 1298, + Mips_CMP_ULE_D_MMR6 = 1299, + Mips_CMP_ULE_S = 1300, + Mips_CMP_ULE_S_MMR6 = 1301, + Mips_CMP_ULT_D = 1302, + Mips_CMP_ULT_D_MMR6 = 1303, + Mips_CMP_ULT_S = 1304, + Mips_CMP_ULT_S_MMR6 = 1305, + Mips_CMP_UN_D = 1306, + Mips_CMP_UN_D_MMR6 = 1307, + Mips_CMP_UN_S = 1308, + Mips_CMP_UN_S_MMR6 = 1309, + Mips_COPY_S_B = 1310, + Mips_COPY_S_D = 1311, + Mips_COPY_S_H = 1312, + Mips_COPY_S_W = 1313, + Mips_COPY_U_B = 1314, + Mips_COPY_U_H = 1315, + Mips_COPY_U_W = 1316, + Mips_CRC32B = 1317, + Mips_CRC32B_NM = 1318, + Mips_CRC32CB = 1319, + Mips_CRC32CB_NM = 1320, + Mips_CRC32CD = 1321, + Mips_CRC32CH = 1322, + Mips_CRC32CH_NM = 1323, + Mips_CRC32CW = 1324, + Mips_CRC32CW_NM = 1325, + Mips_CRC32D = 1326, + Mips_CRC32H = 1327, + Mips_CRC32H_NM = 1328, + Mips_CRC32W = 1329, + Mips_CRC32W_NM = 1330, + Mips_CTC1 = 1331, + Mips_CTC1_MM = 1332, + Mips_CTC2_MM = 1333, + Mips_CTCMSA = 1334, + Mips_CVT_D32_S = 1335, + Mips_CVT_D32_S_MM = 1336, + Mips_CVT_D32_W = 1337, + Mips_CVT_D32_W_MM = 1338, + Mips_CVT_D64_L = 1339, + Mips_CVT_D64_S = 1340, + Mips_CVT_D64_S_MM = 1341, + Mips_CVT_D64_W = 1342, + Mips_CVT_D64_W_MM = 1343, + Mips_CVT_D_L_MMR6 = 1344, + Mips_CVT_L_D64 = 1345, + Mips_CVT_L_D64_MM = 1346, + Mips_CVT_L_D_MMR6 = 1347, + Mips_CVT_L_S = 1348, + Mips_CVT_L_S_MM = 1349, + Mips_CVT_L_S_MMR6 = 1350, + Mips_CVT_PS_PW64 = 1351, + Mips_CVT_PS_S64 = 1352, + Mips_CVT_PW_PS64 = 1353, + Mips_CVT_S_D32 = 1354, + Mips_CVT_S_D32_MM = 1355, + Mips_CVT_S_D64 = 1356, + Mips_CVT_S_D64_MM = 1357, + Mips_CVT_S_L = 1358, + Mips_CVT_S_L_MMR6 = 1359, + Mips_CVT_S_PL64 = 1360, + Mips_CVT_S_PU64 = 1361, + Mips_CVT_S_W = 1362, + Mips_CVT_S_W_MM = 1363, + Mips_CVT_S_W_MMR6 = 1364, + Mips_CVT_W_D32 = 1365, + Mips_CVT_W_D32_MM = 1366, + Mips_CVT_W_D64 = 1367, + Mips_CVT_W_D64_MM = 1368, + Mips_CVT_W_S = 1369, + Mips_CVT_W_S_MM = 1370, + Mips_CVT_W_S_MMR6 = 1371, + Mips_C_EQ_D32 = 1372, + Mips_C_EQ_D32_MM = 1373, + Mips_C_EQ_D64 = 1374, + Mips_C_EQ_D64_MM = 1375, + Mips_C_EQ_S = 1376, + Mips_C_EQ_S_MM = 1377, + Mips_C_F_D32 = 1378, + Mips_C_F_D32_MM = 1379, + Mips_C_F_D64 = 1380, + Mips_C_F_D64_MM = 1381, + Mips_C_F_S = 1382, + Mips_C_F_S_MM = 1383, + Mips_C_LE_D32 = 1384, + Mips_C_LE_D32_MM = 1385, + Mips_C_LE_D64 = 1386, + Mips_C_LE_D64_MM = 1387, + Mips_C_LE_S = 1388, + Mips_C_LE_S_MM = 1389, + Mips_C_LT_D32 = 1390, + Mips_C_LT_D32_MM = 1391, + Mips_C_LT_D64 = 1392, + Mips_C_LT_D64_MM = 1393, + Mips_C_LT_S = 1394, + Mips_C_LT_S_MM = 1395, + Mips_C_NGE_D32 = 1396, + Mips_C_NGE_D32_MM = 1397, + Mips_C_NGE_D64 = 1398, + Mips_C_NGE_D64_MM = 1399, + Mips_C_NGE_S = 1400, + Mips_C_NGE_S_MM = 1401, + Mips_C_NGLE_D32 = 1402, + Mips_C_NGLE_D32_MM = 1403, + Mips_C_NGLE_D64 = 1404, + Mips_C_NGLE_D64_MM = 1405, + Mips_C_NGLE_S = 1406, + Mips_C_NGLE_S_MM = 1407, + Mips_C_NGL_D32 = 1408, + Mips_C_NGL_D32_MM = 1409, + Mips_C_NGL_D64 = 1410, + Mips_C_NGL_D64_MM = 1411, + Mips_C_NGL_S = 1412, + Mips_C_NGL_S_MM = 1413, + Mips_C_NGT_D32 = 1414, + Mips_C_NGT_D32_MM = 1415, + Mips_C_NGT_D64 = 1416, + Mips_C_NGT_D64_MM = 1417, + Mips_C_NGT_S = 1418, + Mips_C_NGT_S_MM = 1419, + Mips_C_OLE_D32 = 1420, + Mips_C_OLE_D32_MM = 1421, + Mips_C_OLE_D64 = 1422, + Mips_C_OLE_D64_MM = 1423, + Mips_C_OLE_S = 1424, + Mips_C_OLE_S_MM = 1425, + Mips_C_OLT_D32 = 1426, + Mips_C_OLT_D32_MM = 1427, + Mips_C_OLT_D64 = 1428, + Mips_C_OLT_D64_MM = 1429, + Mips_C_OLT_S = 1430, + Mips_C_OLT_S_MM = 1431, + Mips_C_SEQ_D32 = 1432, + Mips_C_SEQ_D32_MM = 1433, + Mips_C_SEQ_D64 = 1434, + Mips_C_SEQ_D64_MM = 1435, + Mips_C_SEQ_S = 1436, + Mips_C_SEQ_S_MM = 1437, + Mips_C_SF_D32 = 1438, + Mips_C_SF_D32_MM = 1439, + Mips_C_SF_D64 = 1440, + Mips_C_SF_D64_MM = 1441, + Mips_C_SF_S = 1442, + Mips_C_SF_S_MM = 1443, + Mips_C_UEQ_D32 = 1444, + Mips_C_UEQ_D32_MM = 1445, + Mips_C_UEQ_D64 = 1446, + Mips_C_UEQ_D64_MM = 1447, + Mips_C_UEQ_S = 1448, + Mips_C_UEQ_S_MM = 1449, + Mips_C_ULE_D32 = 1450, + Mips_C_ULE_D32_MM = 1451, + Mips_C_ULE_D64 = 1452, + Mips_C_ULE_D64_MM = 1453, + Mips_C_ULE_S = 1454, + Mips_C_ULE_S_MM = 1455, + Mips_C_ULT_D32 = 1456, + Mips_C_ULT_D32_MM = 1457, + Mips_C_ULT_D64 = 1458, + Mips_C_ULT_D64_MM = 1459, + Mips_C_ULT_S = 1460, + Mips_C_ULT_S_MM = 1461, + Mips_C_UN_D32 = 1462, + Mips_C_UN_D32_MM = 1463, + Mips_C_UN_D64 = 1464, + Mips_C_UN_D64_MM = 1465, + Mips_C_UN_S = 1466, + Mips_C_UN_S_MM = 1467, + Mips_CmpRxRy16 = 1468, + Mips_CmpiRxImm16 = 1469, + Mips_CmpiRxImmX16 = 1470, + Mips_DADD = 1471, + Mips_DADDi = 1472, + Mips_DADDiu = 1473, + Mips_DADDu = 1474, + Mips_DAHI = 1475, + Mips_DALIGN = 1476, + Mips_DATI = 1477, + Mips_DAUI = 1478, + Mips_DBITSWAP = 1479, + Mips_DCLO = 1480, + Mips_DCLO_R6 = 1481, + Mips_DCLZ = 1482, + Mips_DCLZ_R6 = 1483, + Mips_DDIV = 1484, + Mips_DDIVU = 1485, + Mips_DERET = 1486, + Mips_DERET_MM = 1487, + Mips_DERET_MMR6 = 1488, + Mips_DERET_NM = 1489, + Mips_DEXT = 1490, + Mips_DEXT64_32 = 1491, + Mips_DEXTM = 1492, + Mips_DEXTU = 1493, + Mips_DI = 1494, + Mips_DINS = 1495, + Mips_DINSM = 1496, + Mips_DINSU = 1497, + Mips_DIV = 1498, + Mips_DIVU = 1499, + Mips_DIVU_MMR6 = 1500, + Mips_DIVU_NM = 1501, + Mips_DIV_MMR6 = 1502, + Mips_DIV_NM = 1503, + Mips_DIV_S_B = 1504, + Mips_DIV_S_D = 1505, + Mips_DIV_S_H = 1506, + Mips_DIV_S_W = 1507, + Mips_DIV_U_B = 1508, + Mips_DIV_U_D = 1509, + Mips_DIV_U_H = 1510, + Mips_DIV_U_W = 1511, + Mips_DI_MM = 1512, + Mips_DI_MMR6 = 1513, + Mips_DI_NM = 1514, + Mips_DLSA = 1515, + Mips_DLSA_R6 = 1516, + Mips_DMFC0 = 1517, + Mips_DMFC1 = 1518, + Mips_DMFC2 = 1519, + Mips_DMFC2_OCTEON = 1520, + Mips_DMFGC0 = 1521, + Mips_DMOD = 1522, + Mips_DMODU = 1523, + Mips_DMT = 1524, + Mips_DMTC0 = 1525, + Mips_DMTC1 = 1526, + Mips_DMTC2 = 1527, + Mips_DMTC2_OCTEON = 1528, + Mips_DMTGC0 = 1529, + Mips_DMT_NM = 1530, + Mips_DMUH = 1531, + Mips_DMUHU = 1532, + Mips_DMUL = 1533, + Mips_DMULT = 1534, + Mips_DMULTu = 1535, + Mips_DMULU = 1536, + Mips_DMUL_R6 = 1537, + Mips_DOTP_S_D = 1538, + Mips_DOTP_S_H = 1539, + Mips_DOTP_S_W = 1540, + Mips_DOTP_U_D = 1541, + Mips_DOTP_U_H = 1542, + Mips_DOTP_U_W = 1543, + Mips_DPADD_S_D = 1544, + Mips_DPADD_S_H = 1545, + Mips_DPADD_S_W = 1546, + Mips_DPADD_U_D = 1547, + Mips_DPADD_U_H = 1548, + Mips_DPADD_U_W = 1549, + Mips_DPAQX_SA_W_PH = 1550, + Mips_DPAQX_SA_W_PH_MMR2 = 1551, + Mips_DPAQX_S_W_PH = 1552, + Mips_DPAQX_S_W_PH_MMR2 = 1553, + Mips_DPAQ_SA_L_W = 1554, + Mips_DPAQ_SA_L_W_MM = 1555, + Mips_DPAQ_S_W_PH = 1556, + Mips_DPAQ_S_W_PH_MM = 1557, + Mips_DPAU_H_QBL = 1558, + Mips_DPAU_H_QBL_MM = 1559, + Mips_DPAU_H_QBR = 1560, + Mips_DPAU_H_QBR_MM = 1561, + Mips_DPAX_W_PH = 1562, + Mips_DPAX_W_PH_MMR2 = 1563, + Mips_DPA_W_PH = 1564, + Mips_DPA_W_PH_MMR2 = 1565, + Mips_DPOP = 1566, + Mips_DPSQX_SA_W_PH = 1567, + Mips_DPSQX_SA_W_PH_MMR2 = 1568, + Mips_DPSQX_S_W_PH = 1569, + Mips_DPSQX_S_W_PH_MMR2 = 1570, + Mips_DPSQ_SA_L_W = 1571, + Mips_DPSQ_SA_L_W_MM = 1572, + Mips_DPSQ_S_W_PH = 1573, + Mips_DPSQ_S_W_PH_MM = 1574, + Mips_DPSUB_S_D = 1575, + Mips_DPSUB_S_H = 1576, + Mips_DPSUB_S_W = 1577, + Mips_DPSUB_U_D = 1578, + Mips_DPSUB_U_H = 1579, + Mips_DPSUB_U_W = 1580, + Mips_DPSU_H_QBL = 1581, + Mips_DPSU_H_QBL_MM = 1582, + Mips_DPSU_H_QBR = 1583, + Mips_DPSU_H_QBR_MM = 1584, + Mips_DPSX_W_PH = 1585, + Mips_DPSX_W_PH_MMR2 = 1586, + Mips_DPS_W_PH = 1587, + Mips_DPS_W_PH_MMR2 = 1588, + Mips_DROTR = 1589, + Mips_DROTR32 = 1590, + Mips_DROTRV = 1591, + Mips_DSBH = 1592, + Mips_DSDIV = 1593, + Mips_DSHD = 1594, + Mips_DSLL = 1595, + Mips_DSLL32 = 1596, + Mips_DSLL64_32 = 1597, + Mips_DSLLV = 1598, + Mips_DSRA = 1599, + Mips_DSRA32 = 1600, + Mips_DSRAV = 1601, + Mips_DSRL = 1602, + Mips_DSRL32 = 1603, + Mips_DSRLV = 1604, + Mips_DSUB = 1605, + Mips_DSUBu = 1606, + Mips_DUDIV = 1607, + Mips_DVP = 1608, + Mips_DVPE = 1609, + Mips_DVPE_NM = 1610, + Mips_DVP_MMR6 = 1611, + Mips_DivRxRy16 = 1612, + Mips_DivuRxRy16 = 1613, + Mips_EHB = 1614, + Mips_EHB_MM = 1615, + Mips_EHB_MMR6 = 1616, + Mips_EHB_NM = 1617, + Mips_EI = 1618, + Mips_EI_MM = 1619, + Mips_EI_MMR6 = 1620, + Mips_EI_NM = 1621, + Mips_EMT = 1622, + Mips_EMT_NM = 1623, + Mips_ERET = 1624, + Mips_ERETNC = 1625, + Mips_ERETNC_MMR6 = 1626, + Mips_ERETNC_NM = 1627, + Mips_ERET_MM = 1628, + Mips_ERET_MMR6 = 1629, + Mips_ERET_NM = 1630, + Mips_EVP = 1631, + Mips_EVPE = 1632, + Mips_EVPE_NM = 1633, + Mips_EVP_MMR6 = 1634, + Mips_EXT = 1635, + Mips_EXTP = 1636, + Mips_EXTPDP = 1637, + Mips_EXTPDPV = 1638, + Mips_EXTPDPV_MM = 1639, + Mips_EXTPDP_MM = 1640, + Mips_EXTPV = 1641, + Mips_EXTPV_MM = 1642, + Mips_EXTP_MM = 1643, + Mips_EXTRV_RS_W = 1644, + Mips_EXTRV_RS_W_MM = 1645, + Mips_EXTRV_R_W = 1646, + Mips_EXTRV_R_W_MM = 1647, + Mips_EXTRV_S_H = 1648, + Mips_EXTRV_S_H_MM = 1649, + Mips_EXTRV_W = 1650, + Mips_EXTRV_W_MM = 1651, + Mips_EXTR_RS_W = 1652, + Mips_EXTR_RS_W_MM = 1653, + Mips_EXTR_R_W = 1654, + Mips_EXTR_R_W_MM = 1655, + Mips_EXTR_S_H = 1656, + Mips_EXTR_S_H_MM = 1657, + Mips_EXTR_W = 1658, + Mips_EXTR_W_MM = 1659, + Mips_EXTS = 1660, + Mips_EXTS32 = 1661, + Mips_EXTW_NM = 1662, + Mips_EXT_MM = 1663, + Mips_EXT_MMR6 = 1664, + Mips_EXT_NM = 1665, + Mips_FABS_D32 = 1666, + Mips_FABS_D32_MM = 1667, + Mips_FABS_D64 = 1668, + Mips_FABS_D64_MM = 1669, + Mips_FABS_S = 1670, + Mips_FABS_S_MM = 1671, + Mips_FADD_D = 1672, + Mips_FADD_D32 = 1673, + Mips_FADD_D32_MM = 1674, + Mips_FADD_D64 = 1675, + Mips_FADD_D64_MM = 1676, + Mips_FADD_PS64 = 1677, + Mips_FADD_S = 1678, + Mips_FADD_S_MM = 1679, + Mips_FADD_S_MMR6 = 1680, + Mips_FADD_W = 1681, + Mips_FCAF_D = 1682, + Mips_FCAF_W = 1683, + Mips_FCEQ_D = 1684, + Mips_FCEQ_W = 1685, + Mips_FCLASS_D = 1686, + Mips_FCLASS_W = 1687, + Mips_FCLE_D = 1688, + Mips_FCLE_W = 1689, + Mips_FCLT_D = 1690, + Mips_FCLT_W = 1691, + Mips_FCMP_D32 = 1692, + Mips_FCMP_D32_MM = 1693, + Mips_FCMP_D64 = 1694, + Mips_FCMP_S32 = 1695, + Mips_FCMP_S32_MM = 1696, + Mips_FCNE_D = 1697, + Mips_FCNE_W = 1698, + Mips_FCOR_D = 1699, + Mips_FCOR_W = 1700, + Mips_FCUEQ_D = 1701, + Mips_FCUEQ_W = 1702, + Mips_FCULE_D = 1703, + Mips_FCULE_W = 1704, + Mips_FCULT_D = 1705, + Mips_FCULT_W = 1706, + Mips_FCUNE_D = 1707, + Mips_FCUNE_W = 1708, + Mips_FCUN_D = 1709, + Mips_FCUN_W = 1710, + Mips_FDIV_D = 1711, + Mips_FDIV_D32 = 1712, + Mips_FDIV_D32_MM = 1713, + Mips_FDIV_D64 = 1714, + Mips_FDIV_D64_MM = 1715, + Mips_FDIV_S = 1716, + Mips_FDIV_S_MM = 1717, + Mips_FDIV_S_MMR6 = 1718, + Mips_FDIV_W = 1719, + Mips_FEXDO_H = 1720, + Mips_FEXDO_W = 1721, + Mips_FEXP2_D = 1722, + Mips_FEXP2_W = 1723, + Mips_FEXUPL_D = 1724, + Mips_FEXUPL_W = 1725, + Mips_FEXUPR_D = 1726, + Mips_FEXUPR_W = 1727, + Mips_FFINT_S_D = 1728, + Mips_FFINT_S_W = 1729, + Mips_FFINT_U_D = 1730, + Mips_FFINT_U_W = 1731, + Mips_FFQL_D = 1732, + Mips_FFQL_W = 1733, + Mips_FFQR_D = 1734, + Mips_FFQR_W = 1735, + Mips_FILL_B = 1736, + Mips_FILL_D = 1737, + Mips_FILL_H = 1738, + Mips_FILL_W = 1739, + Mips_FLOG2_D = 1740, + Mips_FLOG2_W = 1741, + Mips_FLOOR_L_D64 = 1742, + Mips_FLOOR_L_D_MMR6 = 1743, + Mips_FLOOR_L_S = 1744, + Mips_FLOOR_L_S_MMR6 = 1745, + Mips_FLOOR_W_D32 = 1746, + Mips_FLOOR_W_D64 = 1747, + Mips_FLOOR_W_D_MMR6 = 1748, + Mips_FLOOR_W_MM = 1749, + Mips_FLOOR_W_S = 1750, + Mips_FLOOR_W_S_MM = 1751, + Mips_FLOOR_W_S_MMR6 = 1752, + Mips_FMADD_D = 1753, + Mips_FMADD_W = 1754, + Mips_FMAX_A_D = 1755, + Mips_FMAX_A_W = 1756, + Mips_FMAX_D = 1757, + Mips_FMAX_W = 1758, + Mips_FMIN_A_D = 1759, + Mips_FMIN_A_W = 1760, + Mips_FMIN_D = 1761, + Mips_FMIN_W = 1762, + Mips_FMOV_D32 = 1763, + Mips_FMOV_D32_MM = 1764, + Mips_FMOV_D64 = 1765, + Mips_FMOV_D64_MM = 1766, + Mips_FMOV_D_MMR6 = 1767, + Mips_FMOV_S = 1768, + Mips_FMOV_S_MM = 1769, + Mips_FMOV_S_MMR6 = 1770, + Mips_FMSUB_D = 1771, + Mips_FMSUB_W = 1772, + Mips_FMUL_D = 1773, + Mips_FMUL_D32 = 1774, + Mips_FMUL_D32_MM = 1775, + Mips_FMUL_D64 = 1776, + Mips_FMUL_D64_MM = 1777, + Mips_FMUL_PS64 = 1778, + Mips_FMUL_S = 1779, + Mips_FMUL_S_MM = 1780, + Mips_FMUL_S_MMR6 = 1781, + Mips_FMUL_W = 1782, + Mips_FNEG_D32 = 1783, + Mips_FNEG_D32_MM = 1784, + Mips_FNEG_D64 = 1785, + Mips_FNEG_D64_MM = 1786, + Mips_FNEG_S = 1787, + Mips_FNEG_S_MM = 1788, + Mips_FNEG_S_MMR6 = 1789, + Mips_FORK = 1790, + Mips_FORK_NM = 1791, + Mips_FRCP_D = 1792, + Mips_FRCP_W = 1793, + Mips_FRINT_D = 1794, + Mips_FRINT_W = 1795, + Mips_FRSQRT_D = 1796, + Mips_FRSQRT_W = 1797, + Mips_FSAF_D = 1798, + Mips_FSAF_W = 1799, + Mips_FSEQ_D = 1800, + Mips_FSEQ_W = 1801, + Mips_FSLE_D = 1802, + Mips_FSLE_W = 1803, + Mips_FSLT_D = 1804, + Mips_FSLT_W = 1805, + Mips_FSNE_D = 1806, + Mips_FSNE_W = 1807, + Mips_FSOR_D = 1808, + Mips_FSOR_W = 1809, + Mips_FSQRT_D = 1810, + Mips_FSQRT_D32 = 1811, + Mips_FSQRT_D32_MM = 1812, + Mips_FSQRT_D64 = 1813, + Mips_FSQRT_D64_MM = 1814, + Mips_FSQRT_S = 1815, + Mips_FSQRT_S_MM = 1816, + Mips_FSQRT_W = 1817, + Mips_FSUB_D = 1818, + Mips_FSUB_D32 = 1819, + Mips_FSUB_D32_MM = 1820, + Mips_FSUB_D64 = 1821, + Mips_FSUB_D64_MM = 1822, + Mips_FSUB_PS64 = 1823, + Mips_FSUB_S = 1824, + Mips_FSUB_S_MM = 1825, + Mips_FSUB_S_MMR6 = 1826, + Mips_FSUB_W = 1827, + Mips_FSUEQ_D = 1828, + Mips_FSUEQ_W = 1829, + Mips_FSULE_D = 1830, + Mips_FSULE_W = 1831, + Mips_FSULT_D = 1832, + Mips_FSULT_W = 1833, + Mips_FSUNE_D = 1834, + Mips_FSUNE_W = 1835, + Mips_FSUN_D = 1836, + Mips_FSUN_W = 1837, + Mips_FTINT_S_D = 1838, + Mips_FTINT_S_W = 1839, + Mips_FTINT_U_D = 1840, + Mips_FTINT_U_W = 1841, + Mips_FTQ_H = 1842, + Mips_FTQ_W = 1843, + Mips_FTRUNC_S_D = 1844, + Mips_FTRUNC_S_W = 1845, + Mips_FTRUNC_U_D = 1846, + Mips_FTRUNC_U_W = 1847, + Mips_GINVI = 1848, + Mips_GINVI_MMR6 = 1849, + Mips_GINVI_NM = 1850, + Mips_GINVT = 1851, + Mips_GINVT_MMR6 = 1852, + Mips_GINVT_NM = 1853, + Mips_HADD_S_D = 1854, + Mips_HADD_S_H = 1855, + Mips_HADD_S_W = 1856, + Mips_HADD_U_D = 1857, + Mips_HADD_U_H = 1858, + Mips_HADD_U_W = 1859, + Mips_HSUB_S_D = 1860, + Mips_HSUB_S_H = 1861, + Mips_HSUB_S_W = 1862, + Mips_HSUB_U_D = 1863, + Mips_HSUB_U_H = 1864, + Mips_HSUB_U_W = 1865, + Mips_HYPCALL = 1866, + Mips_HYPCALL_MM = 1867, + Mips_ILVEV_B = 1868, + Mips_ILVEV_D = 1869, + Mips_ILVEV_H = 1870, + Mips_ILVEV_W = 1871, + Mips_ILVL_B = 1872, + Mips_ILVL_D = 1873, + Mips_ILVL_H = 1874, + Mips_ILVL_W = 1875, + Mips_ILVOD_B = 1876, + Mips_ILVOD_D = 1877, + Mips_ILVOD_H = 1878, + Mips_ILVOD_W = 1879, + Mips_ILVR_B = 1880, + Mips_ILVR_D = 1881, + Mips_ILVR_H = 1882, + Mips_ILVR_W = 1883, + Mips_INS = 1884, + Mips_INSERT_B = 1885, + Mips_INSERT_D = 1886, + Mips_INSERT_H = 1887, + Mips_INSERT_W = 1888, + Mips_INSV = 1889, + Mips_INSVE_B = 1890, + Mips_INSVE_D = 1891, + Mips_INSVE_H = 1892, + Mips_INSVE_W = 1893, + Mips_INSV_MM = 1894, + Mips_INS_MM = 1895, + Mips_INS_MMR6 = 1896, + Mips_INS_NM = 1897, + Mips_J = 1898, + Mips_JAL = 1899, + Mips_JALR = 1900, + Mips_JALR16_MM = 1901, + Mips_JALR64 = 1902, + Mips_JALRC16_MMR6 = 1903, + Mips_JALRC16_NM = 1904, + Mips_JALRCHB_NM = 1905, + Mips_JALRC_HB_MMR6 = 1906, + Mips_JALRC_MMR6 = 1907, + Mips_JALRC_NM = 1908, + Mips_JALRS16_MM = 1909, + Mips_JALRS_MM = 1910, + Mips_JALR_HB = 1911, + Mips_JALR_HB64 = 1912, + Mips_JALR_MM = 1913, + Mips_JALS_MM = 1914, + Mips_JALX = 1915, + Mips_JALX_MM = 1916, + Mips_JAL_MM = 1917, + Mips_JIALC = 1918, + Mips_JIALC64 = 1919, + Mips_JIALC_MMR6 = 1920, + Mips_JIC = 1921, + Mips_JIC64 = 1922, + Mips_JIC_MMR6 = 1923, + Mips_JR = 1924, + Mips_JR16_MM = 1925, + Mips_JR64 = 1926, + Mips_JRADDIUSP = 1927, + Mips_JRC16_MM = 1928, + Mips_JRC16_MMR6 = 1929, + Mips_JRCADDIUSP_MMR6 = 1930, + Mips_JRC_NM = 1931, + Mips_JR_HB = 1932, + Mips_JR_HB64 = 1933, + Mips_JR_HB64_R6 = 1934, + Mips_JR_HB_R6 = 1935, + Mips_JR_MM = 1936, + Mips_J_MM = 1937, + Mips_Jal16 = 1938, + Mips_JalB16 = 1939, + Mips_JrRa16 = 1940, + Mips_JrcRa16 = 1941, + Mips_JrcRx16 = 1942, + Mips_JumpLinkReg16 = 1943, + Mips_LAPC32_NM = 1944, + Mips_LAPC48_NM = 1945, + Mips_LB = 1946, + Mips_LB16_NM = 1947, + Mips_LB64 = 1948, + Mips_LBE = 1949, + Mips_LBE_MM = 1950, + Mips_LBGP_NM = 1951, + Mips_LBU16_MM = 1952, + Mips_LBU16_NM = 1953, + Mips_LBUGP_NM = 1954, + Mips_LBUX = 1955, + Mips_LBUX_MM = 1956, + Mips_LBUX_NM = 1957, + Mips_LBU_MMR6 = 1958, + Mips_LBU_NM = 1959, + Mips_LBUs9_NM = 1960, + Mips_LBX_NM = 1961, + Mips_LB_MM = 1962, + Mips_LB_MMR6 = 1963, + Mips_LB_NM = 1964, + Mips_LBs9_NM = 1965, + Mips_LBu = 1966, + Mips_LBu64 = 1967, + Mips_LBuE = 1968, + Mips_LBuE_MM = 1969, + Mips_LBu_MM = 1970, + Mips_LD = 1971, + Mips_LDC1 = 1972, + Mips_LDC164 = 1973, + Mips_LDC1_D64_MMR6 = 1974, + Mips_LDC1_MM_D32 = 1975, + Mips_LDC1_MM_D64 = 1976, + Mips_LDC2 = 1977, + Mips_LDC2_MMR6 = 1978, + Mips_LDC2_R6 = 1979, + Mips_LDC3 = 1980, + Mips_LDI_B = 1981, + Mips_LDI_D = 1982, + Mips_LDI_H = 1983, + Mips_LDI_W = 1984, + Mips_LDL = 1985, + Mips_LDPC = 1986, + Mips_LDR = 1987, + Mips_LDXC1 = 1988, + Mips_LDXC164 = 1989, + Mips_LD_B = 1990, + Mips_LD_D = 1991, + Mips_LD_H = 1992, + Mips_LD_W = 1993, + Mips_LEA_ADDIU_NM = 1994, + Mips_LEA_ADDiu = 1995, + Mips_LEA_ADDiu64 = 1996, + Mips_LEA_ADDiu_MM = 1997, + Mips_LH = 1998, + Mips_LH16_NM = 1999, + Mips_LH64 = 2000, + Mips_LHE = 2001, + Mips_LHE_MM = 2002, + Mips_LHGP_NM = 2003, + Mips_LHU16_MM = 2004, + Mips_LHU16_NM = 2005, + Mips_LHUGP_NM = 2006, + Mips_LHUXS_NM = 2007, + Mips_LHUX_NM = 2008, + Mips_LHU_NM = 2009, + Mips_LHUs9_NM = 2010, + Mips_LHX = 2011, + Mips_LHXS_NM = 2012, + Mips_LHX_MM = 2013, + Mips_LHX_NM = 2014, + Mips_LH_MM = 2015, + Mips_LH_NM = 2016, + Mips_LHs9_NM = 2017, + Mips_LHu = 2018, + Mips_LHu64 = 2019, + Mips_LHuE = 2020, + Mips_LHuE_MM = 2021, + Mips_LHu_MM = 2022, + Mips_LI16_MM = 2023, + Mips_LI16_MMR6 = 2024, + Mips_LI16_NM = 2025, + Mips_LI48_NM = 2026, + Mips_LL = 2027, + Mips_LL64 = 2028, + Mips_LL64_R6 = 2029, + Mips_LLD = 2030, + Mips_LLD_R6 = 2031, + Mips_LLE = 2032, + Mips_LLE_MM = 2033, + Mips_LLWP_NM = 2034, + Mips_LL_MM = 2035, + Mips_LL_MMR6 = 2036, + Mips_LL_NM = 2037, + Mips_LL_R6 = 2038, + Mips_LSA = 2039, + Mips_LSA_MMR6 = 2040, + Mips_LSA_NM = 2041, + Mips_LSA_R6 = 2042, + Mips_LUI_MMR6 = 2043, + Mips_LUI_NM = 2044, + Mips_LUXC1 = 2045, + Mips_LUXC164 = 2046, + Mips_LUXC1_MM = 2047, + Mips_LUi = 2048, + Mips_LUi64 = 2049, + Mips_LUi_MM = 2050, + Mips_LW = 2051, + Mips_LW16_MM = 2052, + Mips_LW16_NM = 2053, + Mips_LW4x4_NM = 2054, + Mips_LW64 = 2055, + Mips_LWC1 = 2056, + Mips_LWC1_MM = 2057, + Mips_LWC2 = 2058, + Mips_LWC2_MMR6 = 2059, + Mips_LWC2_R6 = 2060, + Mips_LWC3 = 2061, + Mips_LWDSP = 2062, + Mips_LWDSP_MM = 2063, + Mips_LWE = 2064, + Mips_LWE_MM = 2065, + Mips_LWGP16_NM = 2066, + Mips_LWGP_MM = 2067, + Mips_LWGP_NM = 2068, + Mips_LWL = 2069, + Mips_LWL64 = 2070, + Mips_LWLE = 2071, + Mips_LWLE_MM = 2072, + Mips_LWL_MM = 2073, + Mips_LWM16_MM = 2074, + Mips_LWM16_MMR6 = 2075, + Mips_LWM32_MM = 2076, + Mips_LWM_NM = 2077, + Mips_LWPC = 2078, + Mips_LWPC_MMR6 = 2079, + Mips_LWPC_NM = 2080, + Mips_LWP_MM = 2081, + Mips_LWR = 2082, + Mips_LWR64 = 2083, + Mips_LWRE = 2084, + Mips_LWRE_MM = 2085, + Mips_LWR_MM = 2086, + Mips_LWSP16_NM = 2087, + Mips_LWSP_MM = 2088, + Mips_LWUPC = 2089, + Mips_LWU_MM = 2090, + Mips_LWX = 2091, + Mips_LWXC1 = 2092, + Mips_LWXC1_MM = 2093, + Mips_LWXS16_NM = 2094, + Mips_LWXS_MM = 2095, + Mips_LWXS_NM = 2096, + Mips_LWX_MM = 2097, + Mips_LWX_NM = 2098, + Mips_LW_MM = 2099, + Mips_LW_MMR6 = 2100, + Mips_LW_NM = 2101, + Mips_LWs9_NM = 2102, + Mips_LWu = 2103, + Mips_LbRxRyOffMemX16 = 2104, + Mips_LbuRxRyOffMemX16 = 2105, + Mips_LhRxRyOffMemX16 = 2106, + Mips_LhuRxRyOffMemX16 = 2107, + Mips_LiRxImm16 = 2108, + Mips_LiRxImmAlignX16 = 2109, + Mips_LiRxImmX16 = 2110, + Mips_LwRxPcTcp16 = 2111, + Mips_LwRxPcTcpX16 = 2112, + Mips_LwRxRyOffMemX16 = 2113, + Mips_LwRxSpImmX16 = 2114, + Mips_MADD = 2115, + Mips_MADDF_D = 2116, + Mips_MADDF_D_MMR6 = 2117, + Mips_MADDF_S = 2118, + Mips_MADDF_S_MMR6 = 2119, + Mips_MADDR_Q_H = 2120, + Mips_MADDR_Q_W = 2121, + Mips_MADDU = 2122, + Mips_MADDU_DSP = 2123, + Mips_MADDU_DSP_MM = 2124, + Mips_MADDU_MM = 2125, + Mips_MADDV_B = 2126, + Mips_MADDV_D = 2127, + Mips_MADDV_H = 2128, + Mips_MADDV_W = 2129, + Mips_MADD_D32 = 2130, + Mips_MADD_D32_MM = 2131, + Mips_MADD_D64 = 2132, + Mips_MADD_DSP = 2133, + Mips_MADD_DSP_MM = 2134, + Mips_MADD_MM = 2135, + Mips_MADD_Q_H = 2136, + Mips_MADD_Q_W = 2137, + Mips_MADD_S = 2138, + Mips_MADD_S_MM = 2139, + Mips_MAQ_SA_W_PHL = 2140, + Mips_MAQ_SA_W_PHL_MM = 2141, + Mips_MAQ_SA_W_PHR = 2142, + Mips_MAQ_SA_W_PHR_MM = 2143, + Mips_MAQ_S_W_PHL = 2144, + Mips_MAQ_S_W_PHL_MM = 2145, + Mips_MAQ_S_W_PHR = 2146, + Mips_MAQ_S_W_PHR_MM = 2147, + Mips_MAXA_D = 2148, + Mips_MAXA_D_MMR6 = 2149, + Mips_MAXA_S = 2150, + Mips_MAXA_S_MMR6 = 2151, + Mips_MAXI_S_B = 2152, + Mips_MAXI_S_D = 2153, + Mips_MAXI_S_H = 2154, + Mips_MAXI_S_W = 2155, + Mips_MAXI_U_B = 2156, + Mips_MAXI_U_D = 2157, + Mips_MAXI_U_H = 2158, + Mips_MAXI_U_W = 2159, + Mips_MAX_A_B = 2160, + Mips_MAX_A_D = 2161, + Mips_MAX_A_H = 2162, + Mips_MAX_A_W = 2163, + Mips_MAX_D = 2164, + Mips_MAX_D_MMR6 = 2165, + Mips_MAX_S = 2166, + Mips_MAX_S_B = 2167, + Mips_MAX_S_D = 2168, + Mips_MAX_S_H = 2169, + Mips_MAX_S_MMR6 = 2170, + Mips_MAX_S_W = 2171, + Mips_MAX_U_B = 2172, + Mips_MAX_U_D = 2173, + Mips_MAX_U_H = 2174, + Mips_MAX_U_W = 2175, + Mips_MFC0 = 2176, + Mips_MFC0Sel_NM = 2177, + Mips_MFC0_MMR6 = 2178, + Mips_MFC0_NM = 2179, + Mips_MFC1 = 2180, + Mips_MFC1_D64 = 2181, + Mips_MFC1_MM = 2182, + Mips_MFC1_MMR6 = 2183, + Mips_MFC2 = 2184, + Mips_MFC2_MMR6 = 2185, + Mips_MFGC0 = 2186, + Mips_MFGC0_MM = 2187, + Mips_MFHC0Sel_NM = 2188, + Mips_MFHC0_MMR6 = 2189, + Mips_MFHC0_NM = 2190, + Mips_MFHC1_D32 = 2191, + Mips_MFHC1_D32_MM = 2192, + Mips_MFHC1_D64 = 2193, + Mips_MFHC1_D64_MM = 2194, + Mips_MFHC2_MMR6 = 2195, + Mips_MFHGC0 = 2196, + Mips_MFHGC0_MM = 2197, + Mips_MFHI = 2198, + Mips_MFHI16_MM = 2199, + Mips_MFHI64 = 2200, + Mips_MFHI_DSP = 2201, + Mips_MFHI_DSP_MM = 2202, + Mips_MFHI_MM = 2203, + Mips_MFLO = 2204, + Mips_MFLO16_MM = 2205, + Mips_MFLO64 = 2206, + Mips_MFLO_DSP = 2207, + Mips_MFLO_DSP_MM = 2208, + Mips_MFLO_MM = 2209, + Mips_MFTR = 2210, + Mips_MFTR_NM = 2211, + Mips_MINA_D = 2212, + Mips_MINA_D_MMR6 = 2213, + Mips_MINA_S = 2214, + Mips_MINA_S_MMR6 = 2215, + Mips_MINI_S_B = 2216, + Mips_MINI_S_D = 2217, + Mips_MINI_S_H = 2218, + Mips_MINI_S_W = 2219, + Mips_MINI_U_B = 2220, + Mips_MINI_U_D = 2221, + Mips_MINI_U_H = 2222, + Mips_MINI_U_W = 2223, + Mips_MIN_A_B = 2224, + Mips_MIN_A_D = 2225, + Mips_MIN_A_H = 2226, + Mips_MIN_A_W = 2227, + Mips_MIN_D = 2228, + Mips_MIN_D_MMR6 = 2229, + Mips_MIN_S = 2230, + Mips_MIN_S_B = 2231, + Mips_MIN_S_D = 2232, + Mips_MIN_S_H = 2233, + Mips_MIN_S_MMR6 = 2234, + Mips_MIN_S_W = 2235, + Mips_MIN_U_B = 2236, + Mips_MIN_U_D = 2237, + Mips_MIN_U_H = 2238, + Mips_MIN_U_W = 2239, + Mips_MOD = 2240, + Mips_MODSUB = 2241, + Mips_MODSUB_MM = 2242, + Mips_MODU = 2243, + Mips_MODU_MMR6 = 2244, + Mips_MODU_NM = 2245, + Mips_MOD_MMR6 = 2246, + Mips_MOD_NM = 2247, + Mips_MOD_S_B = 2248, + Mips_MOD_S_D = 2249, + Mips_MOD_S_H = 2250, + Mips_MOD_S_W = 2251, + Mips_MOD_U_B = 2252, + Mips_MOD_U_D = 2253, + Mips_MOD_U_H = 2254, + Mips_MOD_U_W = 2255, + Mips_MOVE16_MM = 2256, + Mips_MOVE16_MMR6 = 2257, + Mips_MOVEBALC_NM = 2258, + Mips_MOVEPREV_NM = 2259, + Mips_MOVEP_MM = 2260, + Mips_MOVEP_MMR6 = 2261, + Mips_MOVEP_NM = 2262, + Mips_MOVE_NM = 2263, + Mips_MOVE_V = 2264, + Mips_MOVF_D32 = 2265, + Mips_MOVF_D32_MM = 2266, + Mips_MOVF_D64 = 2267, + Mips_MOVF_I = 2268, + Mips_MOVF_I64 = 2269, + Mips_MOVF_I_MM = 2270, + Mips_MOVF_S = 2271, + Mips_MOVF_S_MM = 2272, + Mips_MOVN_I64_D64 = 2273, + Mips_MOVN_I64_I = 2274, + Mips_MOVN_I64_I64 = 2275, + Mips_MOVN_I64_S = 2276, + Mips_MOVN_I_D32 = 2277, + Mips_MOVN_I_D32_MM = 2278, + Mips_MOVN_I_D64 = 2279, + Mips_MOVN_I_I = 2280, + Mips_MOVN_I_I64 = 2281, + Mips_MOVN_I_MM = 2282, + Mips_MOVN_I_S = 2283, + Mips_MOVN_I_S_MM = 2284, + Mips_MOVN_NM = 2285, + Mips_MOVT_D32 = 2286, + Mips_MOVT_D32_MM = 2287, + Mips_MOVT_D64 = 2288, + Mips_MOVT_I = 2289, + Mips_MOVT_I64 = 2290, + Mips_MOVT_I_MM = 2291, + Mips_MOVT_S = 2292, + Mips_MOVT_S_MM = 2293, + Mips_MOVZ_I64_D64 = 2294, + Mips_MOVZ_I64_I = 2295, + Mips_MOVZ_I64_I64 = 2296, + Mips_MOVZ_I64_S = 2297, + Mips_MOVZ_I_D32 = 2298, + Mips_MOVZ_I_D32_MM = 2299, + Mips_MOVZ_I_D64 = 2300, + Mips_MOVZ_I_I = 2301, + Mips_MOVZ_I_I64 = 2302, + Mips_MOVZ_I_MM = 2303, + Mips_MOVZ_I_S = 2304, + Mips_MOVZ_I_S_MM = 2305, + Mips_MOVZ_NM = 2306, + Mips_MSUB = 2307, + Mips_MSUBF_D = 2308, + Mips_MSUBF_D_MMR6 = 2309, + Mips_MSUBF_S = 2310, + Mips_MSUBF_S_MMR6 = 2311, + Mips_MSUBR_Q_H = 2312, + Mips_MSUBR_Q_W = 2313, + Mips_MSUBU = 2314, + Mips_MSUBU_DSP = 2315, + Mips_MSUBU_DSP_MM = 2316, + Mips_MSUBU_MM = 2317, + Mips_MSUBV_B = 2318, + Mips_MSUBV_D = 2319, + Mips_MSUBV_H = 2320, + Mips_MSUBV_W = 2321, + Mips_MSUB_D32 = 2322, + Mips_MSUB_D32_MM = 2323, + Mips_MSUB_D64 = 2324, + Mips_MSUB_DSP = 2325, + Mips_MSUB_DSP_MM = 2326, + Mips_MSUB_MM = 2327, + Mips_MSUB_Q_H = 2328, + Mips_MSUB_Q_W = 2329, + Mips_MSUB_S = 2330, + Mips_MSUB_S_MM = 2331, + Mips_MTC0 = 2332, + Mips_MTC0Sel_NM = 2333, + Mips_MTC0_MMR6 = 2334, + Mips_MTC0_NM = 2335, + Mips_MTC1 = 2336, + Mips_MTC1_D64 = 2337, + Mips_MTC1_D64_MM = 2338, + Mips_MTC1_MM = 2339, + Mips_MTC1_MMR6 = 2340, + Mips_MTC2 = 2341, + Mips_MTC2_MMR6 = 2342, + Mips_MTGC0 = 2343, + Mips_MTGC0_MM = 2344, + Mips_MTHC0Sel_NM = 2345, + Mips_MTHC0_MMR6 = 2346, + Mips_MTHC0_NM = 2347, + Mips_MTHC1_D32 = 2348, + Mips_MTHC1_D32_MM = 2349, + Mips_MTHC1_D64 = 2350, + Mips_MTHC1_D64_MM = 2351, + Mips_MTHC2_MMR6 = 2352, + Mips_MTHGC0 = 2353, + Mips_MTHGC0_MM = 2354, + Mips_MTHI = 2355, + Mips_MTHI64 = 2356, + Mips_MTHI_DSP = 2357, + Mips_MTHI_DSP_MM = 2358, + Mips_MTHI_MM = 2359, + Mips_MTHLIP = 2360, + Mips_MTHLIP_MM = 2361, + Mips_MTLO = 2362, + Mips_MTLO64 = 2363, + Mips_MTLO_DSP = 2364, + Mips_MTLO_DSP_MM = 2365, + Mips_MTLO_MM = 2366, + Mips_MTM0 = 2367, + Mips_MTM1 = 2368, + Mips_MTM2 = 2369, + Mips_MTP0 = 2370, + Mips_MTP1 = 2371, + Mips_MTP2 = 2372, + Mips_MTTR = 2373, + Mips_MTTR_NM = 2374, + Mips_MUH = 2375, + Mips_MUHU = 2376, + Mips_MUHU_MMR6 = 2377, + Mips_MUHU_NM = 2378, + Mips_MUH_MMR6 = 2379, + Mips_MUH_NM = 2380, + Mips_MUL = 2381, + Mips_MUL4x4_NM = 2382, + Mips_MULEQ_S_W_PHL = 2383, + Mips_MULEQ_S_W_PHL_MM = 2384, + Mips_MULEQ_S_W_PHR = 2385, + Mips_MULEQ_S_W_PHR_MM = 2386, + Mips_MULEU_S_PH_QBL = 2387, + Mips_MULEU_S_PH_QBL_MM = 2388, + Mips_MULEU_S_PH_QBR = 2389, + Mips_MULEU_S_PH_QBR_MM = 2390, + Mips_MULQ_RS_PH = 2391, + Mips_MULQ_RS_PH_MM = 2392, + Mips_MULQ_RS_W = 2393, + Mips_MULQ_RS_W_MMR2 = 2394, + Mips_MULQ_S_PH = 2395, + Mips_MULQ_S_PH_MMR2 = 2396, + Mips_MULQ_S_W = 2397, + Mips_MULQ_S_W_MMR2 = 2398, + Mips_MULR_PS64 = 2399, + Mips_MULR_Q_H = 2400, + Mips_MULR_Q_W = 2401, + Mips_MULSAQ_S_W_PH = 2402, + Mips_MULSAQ_S_W_PH_MM = 2403, + Mips_MULSA_W_PH = 2404, + Mips_MULSA_W_PH_MMR2 = 2405, + Mips_MULT = 2406, + Mips_MULTU_DSP = 2407, + Mips_MULTU_DSP_MM = 2408, + Mips_MULT_DSP = 2409, + Mips_MULT_DSP_MM = 2410, + Mips_MULT_MM = 2411, + Mips_MULTu = 2412, + Mips_MULTu_MM = 2413, + Mips_MULU = 2414, + Mips_MULU_MMR6 = 2415, + Mips_MULU_NM = 2416, + Mips_MULV_B = 2417, + Mips_MULV_D = 2418, + Mips_MULV_H = 2419, + Mips_MULV_W = 2420, + Mips_MUL_MM = 2421, + Mips_MUL_MMR6 = 2422, + Mips_MUL_NM = 2423, + Mips_MUL_PH = 2424, + Mips_MUL_PH_MMR2 = 2425, + Mips_MUL_Q_H = 2426, + Mips_MUL_Q_W = 2427, + Mips_MUL_R6 = 2428, + Mips_MUL_S_PH = 2429, + Mips_MUL_S_PH_MMR2 = 2430, + Mips_Mfhi16 = 2431, + Mips_Mflo16 = 2432, + Mips_Move32R16 = 2433, + Mips_MoveR3216 = 2434, + Mips_NLOC_B = 2435, + Mips_NLOC_D = 2436, + Mips_NLOC_H = 2437, + Mips_NLOC_W = 2438, + Mips_NLZC_B = 2439, + Mips_NLZC_D = 2440, + Mips_NLZC_H = 2441, + Mips_NLZC_W = 2442, + Mips_NMADD_D32 = 2443, + Mips_NMADD_D32_MM = 2444, + Mips_NMADD_D64 = 2445, + Mips_NMADD_S = 2446, + Mips_NMADD_S_MM = 2447, + Mips_NMSUB_D32 = 2448, + Mips_NMSUB_D32_MM = 2449, + Mips_NMSUB_D64 = 2450, + Mips_NMSUB_S = 2451, + Mips_NMSUB_S_MM = 2452, + Mips_NOP32_NM = 2453, + Mips_NOP_NM = 2454, + Mips_NOR = 2455, + Mips_NOR64 = 2456, + Mips_NORI_B = 2457, + Mips_NOR_MM = 2458, + Mips_NOR_MMR6 = 2459, + Mips_NOR_NM = 2460, + Mips_NOR_V = 2461, + Mips_NOT16_MM = 2462, + Mips_NOT16_MMR6 = 2463, + Mips_NOT16_NM = 2464, + Mips_NegRxRy16 = 2465, + Mips_NotRxRy16 = 2466, + Mips_OR = 2467, + Mips_OR16_MM = 2468, + Mips_OR16_MMR6 = 2469, + Mips_OR16_NM = 2470, + Mips_OR64 = 2471, + Mips_ORI_B = 2472, + Mips_ORI_MMR6 = 2473, + Mips_ORI_NM = 2474, + Mips_OR_MM = 2475, + Mips_OR_MMR6 = 2476, + Mips_OR_NM = 2477, + Mips_OR_V = 2478, + Mips_ORi = 2479, + Mips_ORi64 = 2480, + Mips_ORi_MM = 2481, + Mips_OrRxRxRy16 = 2482, + Mips_PACKRL_PH = 2483, + Mips_PACKRL_PH_MM = 2484, + Mips_PAUSE = 2485, + Mips_PAUSE_MM = 2486, + Mips_PAUSE_MMR6 = 2487, + Mips_PAUSE_NM = 2488, + Mips_PCKEV_B = 2489, + Mips_PCKEV_D = 2490, + Mips_PCKEV_H = 2491, + Mips_PCKEV_W = 2492, + Mips_PCKOD_B = 2493, + Mips_PCKOD_D = 2494, + Mips_PCKOD_H = 2495, + Mips_PCKOD_W = 2496, + Mips_PCNT_B = 2497, + Mips_PCNT_D = 2498, + Mips_PCNT_H = 2499, + Mips_PCNT_W = 2500, + Mips_PICK_PH = 2501, + Mips_PICK_PH_MM = 2502, + Mips_PICK_QB = 2503, + Mips_PICK_QB_MM = 2504, + Mips_PLL_PS64 = 2505, + Mips_PLU_PS64 = 2506, + Mips_POP = 2507, + Mips_PRECEQU_PH_QBL = 2508, + Mips_PRECEQU_PH_QBLA = 2509, + Mips_PRECEQU_PH_QBLA_MM = 2510, + Mips_PRECEQU_PH_QBL_MM = 2511, + Mips_PRECEQU_PH_QBR = 2512, + Mips_PRECEQU_PH_QBRA = 2513, + Mips_PRECEQU_PH_QBRA_MM = 2514, + Mips_PRECEQU_PH_QBR_MM = 2515, + Mips_PRECEQ_W_PHL = 2516, + Mips_PRECEQ_W_PHL_MM = 2517, + Mips_PRECEQ_W_PHR = 2518, + Mips_PRECEQ_W_PHR_MM = 2519, + Mips_PRECEU_PH_QBL = 2520, + Mips_PRECEU_PH_QBLA = 2521, + Mips_PRECEU_PH_QBLA_MM = 2522, + Mips_PRECEU_PH_QBL_MM = 2523, + Mips_PRECEU_PH_QBR = 2524, + Mips_PRECEU_PH_QBRA = 2525, + Mips_PRECEU_PH_QBRA_MM = 2526, + Mips_PRECEU_PH_QBR_MM = 2527, + Mips_PRECRQU_S_QB_PH = 2528, + Mips_PRECRQU_S_QB_PH_MM = 2529, + Mips_PRECRQ_PH_W = 2530, + Mips_PRECRQ_PH_W_MM = 2531, + Mips_PRECRQ_QB_PH = 2532, + Mips_PRECRQ_QB_PH_MM = 2533, + Mips_PRECRQ_RS_PH_W = 2534, + Mips_PRECRQ_RS_PH_W_MM = 2535, + Mips_PRECR_QB_PH = 2536, + Mips_PRECR_QB_PH_MMR2 = 2537, + Mips_PRECR_SRA_PH_W = 2538, + Mips_PRECR_SRA_PH_W_MMR2 = 2539, + Mips_PRECR_SRA_R_PH_W = 2540, + Mips_PRECR_SRA_R_PH_W_MMR2 = 2541, + Mips_PREF = 2542, + Mips_PREFE = 2543, + Mips_PREFE_MM = 2544, + Mips_PREFX_MM = 2545, + Mips_PREF_MM = 2546, + Mips_PREF_MMR6 = 2547, + Mips_PREF_NM = 2548, + Mips_PREF_R6 = 2549, + Mips_PREFs9_NM = 2550, + Mips_PREPEND = 2551, + Mips_PREPEND_MMR2 = 2552, + Mips_PUL_PS64 = 2553, + Mips_PUU_PS64 = 2554, + Mips_RADDU_W_QB = 2555, + Mips_RADDU_W_QB_MM = 2556, + Mips_RDDSP = 2557, + Mips_RDDSP_MM = 2558, + Mips_RDHWR = 2559, + Mips_RDHWR64 = 2560, + Mips_RDHWR_MM = 2561, + Mips_RDHWR_MMR6 = 2562, + Mips_RDHWR_NM = 2563, + Mips_RDPGPR_MMR6 = 2564, + Mips_RDPGPR_NM = 2565, + Mips_RECIP_D32 = 2566, + Mips_RECIP_D32_MM = 2567, + Mips_RECIP_D64 = 2568, + Mips_RECIP_D64_MM = 2569, + Mips_RECIP_S = 2570, + Mips_RECIP_S_MM = 2571, + Mips_REPLV_PH = 2572, + Mips_REPLV_PH_MM = 2573, + Mips_REPLV_QB = 2574, + Mips_REPLV_QB_MM = 2575, + Mips_REPL_PH = 2576, + Mips_REPL_PH_MM = 2577, + Mips_REPL_QB = 2578, + Mips_REPL_QB_MM = 2579, + Mips_RESTOREJRC16_NM = 2580, + Mips_RESTOREJRC_NM = 2581, + Mips_RESTORE_NM = 2582, + Mips_RINT_D = 2583, + Mips_RINT_D_MMR6 = 2584, + Mips_RINT_S = 2585, + Mips_RINT_S_MMR6 = 2586, + Mips_ROTR = 2587, + Mips_ROTRV = 2588, + Mips_ROTRV_MM = 2589, + Mips_ROTRV_NM = 2590, + Mips_ROTR_MM = 2591, + Mips_ROTR_NM = 2592, + Mips_ROTX_NM = 2593, + Mips_ROUND_L_D64 = 2594, + Mips_ROUND_L_D_MMR6 = 2595, + Mips_ROUND_L_S = 2596, + Mips_ROUND_L_S_MMR6 = 2597, + Mips_ROUND_W_D32 = 2598, + Mips_ROUND_W_D64 = 2599, + Mips_ROUND_W_D_MMR6 = 2600, + Mips_ROUND_W_MM = 2601, + Mips_ROUND_W_S = 2602, + Mips_ROUND_W_S_MM = 2603, + Mips_ROUND_W_S_MMR6 = 2604, + Mips_RSQRT_D32 = 2605, + Mips_RSQRT_D32_MM = 2606, + Mips_RSQRT_D64 = 2607, + Mips_RSQRT_D64_MM = 2608, + Mips_RSQRT_S = 2609, + Mips_RSQRT_S_MM = 2610, + Mips_Restore16 = 2611, + Mips_RestoreX16 = 2612, + Mips_SAA = 2613, + Mips_SAAD = 2614, + Mips_SAT_S_B = 2615, + Mips_SAT_S_D = 2616, + Mips_SAT_S_H = 2617, + Mips_SAT_S_W = 2618, + Mips_SAT_U_B = 2619, + Mips_SAT_U_D = 2620, + Mips_SAT_U_H = 2621, + Mips_SAT_U_W = 2622, + Mips_SAVE16_NM = 2623, + Mips_SAVE_NM = 2624, + Mips_SB = 2625, + Mips_SB16_MM = 2626, + Mips_SB16_MMR6 = 2627, + Mips_SB16_NM = 2628, + Mips_SB64 = 2629, + Mips_SBE = 2630, + Mips_SBE_MM = 2631, + Mips_SBGP_NM = 2632, + Mips_SBX_NM = 2633, + Mips_SB_MM = 2634, + Mips_SB_MMR6 = 2635, + Mips_SB_NM = 2636, + Mips_SBs9_NM = 2637, + Mips_SC = 2638, + Mips_SC64 = 2639, + Mips_SC64_R6 = 2640, + Mips_SCD = 2641, + Mips_SCD_R6 = 2642, + Mips_SCE = 2643, + Mips_SCE_MM = 2644, + Mips_SCWP_NM = 2645, + Mips_SC_MM = 2646, + Mips_SC_MMR6 = 2647, + Mips_SC_NM = 2648, + Mips_SC_R6 = 2649, + Mips_SD = 2650, + Mips_SDBBP = 2651, + Mips_SDBBP16_MM = 2652, + Mips_SDBBP16_MMR6 = 2653, + Mips_SDBBP16_NM = 2654, + Mips_SDBBP_MM = 2655, + Mips_SDBBP_MMR6 = 2656, + Mips_SDBBP_NM = 2657, + Mips_SDBBP_R6 = 2658, + Mips_SDC1 = 2659, + Mips_SDC164 = 2660, + Mips_SDC1_D64_MMR6 = 2661, + Mips_SDC1_MM_D32 = 2662, + Mips_SDC1_MM_D64 = 2663, + Mips_SDC2 = 2664, + Mips_SDC2_MMR6 = 2665, + Mips_SDC2_R6 = 2666, + Mips_SDC3 = 2667, + Mips_SDIV = 2668, + Mips_SDIV_MM = 2669, + Mips_SDL = 2670, + Mips_SDR = 2671, + Mips_SDXC1 = 2672, + Mips_SDXC164 = 2673, + Mips_SEB = 2674, + Mips_SEB64 = 2675, + Mips_SEB_MM = 2676, + Mips_SEB_NM = 2677, + Mips_SEH = 2678, + Mips_SEH64 = 2679, + Mips_SEH_MM = 2680, + Mips_SEH_NM = 2681, + Mips_SELEQZ = 2682, + Mips_SELEQZ64 = 2683, + Mips_SELEQZ_D = 2684, + Mips_SELEQZ_D_MMR6 = 2685, + Mips_SELEQZ_MMR6 = 2686, + Mips_SELEQZ_S = 2687, + Mips_SELEQZ_S_MMR6 = 2688, + Mips_SELNEZ = 2689, + Mips_SELNEZ64 = 2690, + Mips_SELNEZ_D = 2691, + Mips_SELNEZ_D_MMR6 = 2692, + Mips_SELNEZ_MMR6 = 2693, + Mips_SELNEZ_S = 2694, + Mips_SELNEZ_S_MMR6 = 2695, + Mips_SEL_D = 2696, + Mips_SEL_D_MMR6 = 2697, + Mips_SEL_S = 2698, + Mips_SEL_S_MMR6 = 2699, + Mips_SEQ = 2700, + Mips_SEQI_NM = 2701, + Mips_SEQi = 2702, + Mips_SH = 2703, + Mips_SH16_MM = 2704, + Mips_SH16_MMR6 = 2705, + Mips_SH16_NM = 2706, + Mips_SH64 = 2707, + Mips_SHE = 2708, + Mips_SHE_MM = 2709, + Mips_SHF_B = 2710, + Mips_SHF_H = 2711, + Mips_SHF_W = 2712, + Mips_SHGP_NM = 2713, + Mips_SHILO = 2714, + Mips_SHILOV = 2715, + Mips_SHILOV_MM = 2716, + Mips_SHILO_MM = 2717, + Mips_SHLLV_PH = 2718, + Mips_SHLLV_PH_MM = 2719, + Mips_SHLLV_QB = 2720, + Mips_SHLLV_QB_MM = 2721, + Mips_SHLLV_S_PH = 2722, + Mips_SHLLV_S_PH_MM = 2723, + Mips_SHLLV_S_W = 2724, + Mips_SHLLV_S_W_MM = 2725, + Mips_SHLL_PH = 2726, + Mips_SHLL_PH_MM = 2727, + Mips_SHLL_QB = 2728, + Mips_SHLL_QB_MM = 2729, + Mips_SHLL_S_PH = 2730, + Mips_SHLL_S_PH_MM = 2731, + Mips_SHLL_S_W = 2732, + Mips_SHLL_S_W_MM = 2733, + Mips_SHRAV_PH = 2734, + Mips_SHRAV_PH_MM = 2735, + Mips_SHRAV_QB = 2736, + Mips_SHRAV_QB_MMR2 = 2737, + Mips_SHRAV_R_PH = 2738, + Mips_SHRAV_R_PH_MM = 2739, + Mips_SHRAV_R_QB = 2740, + Mips_SHRAV_R_QB_MMR2 = 2741, + Mips_SHRAV_R_W = 2742, + Mips_SHRAV_R_W_MM = 2743, + Mips_SHRA_PH = 2744, + Mips_SHRA_PH_MM = 2745, + Mips_SHRA_QB = 2746, + Mips_SHRA_QB_MMR2 = 2747, + Mips_SHRA_R_PH = 2748, + Mips_SHRA_R_PH_MM = 2749, + Mips_SHRA_R_QB = 2750, + Mips_SHRA_R_QB_MMR2 = 2751, + Mips_SHRA_R_W = 2752, + Mips_SHRA_R_W_MM = 2753, + Mips_SHRLV_PH = 2754, + Mips_SHRLV_PH_MMR2 = 2755, + Mips_SHRLV_QB = 2756, + Mips_SHRLV_QB_MM = 2757, + Mips_SHRL_PH = 2758, + Mips_SHRL_PH_MMR2 = 2759, + Mips_SHRL_QB = 2760, + Mips_SHRL_QB_MM = 2761, + Mips_SHXS_NM = 2762, + Mips_SHX_NM = 2763, + Mips_SH_MM = 2764, + Mips_SH_MMR6 = 2765, + Mips_SH_NM = 2766, + Mips_SHs9_NM = 2767, + Mips_SIGRIE = 2768, + Mips_SIGRIE_MMR6 = 2769, + Mips_SIGRIE_NM = 2770, + Mips_SLDI_B = 2771, + Mips_SLDI_D = 2772, + Mips_SLDI_H = 2773, + Mips_SLDI_W = 2774, + Mips_SLD_B = 2775, + Mips_SLD_D = 2776, + Mips_SLD_H = 2777, + Mips_SLD_W = 2778, + Mips_SLL = 2779, + Mips_SLL16_MM = 2780, + Mips_SLL16_MMR6 = 2781, + Mips_SLL16_NM = 2782, + Mips_SLL64_32 = 2783, + Mips_SLL64_64 = 2784, + Mips_SLLI_B = 2785, + Mips_SLLI_D = 2786, + Mips_SLLI_H = 2787, + Mips_SLLI_W = 2788, + Mips_SLLV = 2789, + Mips_SLLV_MM = 2790, + Mips_SLLV_NM = 2791, + Mips_SLL_B = 2792, + Mips_SLL_D = 2793, + Mips_SLL_H = 2794, + Mips_SLL_MM = 2795, + Mips_SLL_MMR6 = 2796, + Mips_SLL_NM = 2797, + Mips_SLL_W = 2798, + Mips_SLT = 2799, + Mips_SLT64 = 2800, + Mips_SLTIU_NM = 2801, + Mips_SLTI_NM = 2802, + Mips_SLTU_NM = 2803, + Mips_SLT_MM = 2804, + Mips_SLT_NM = 2805, + Mips_SLTi = 2806, + Mips_SLTi64 = 2807, + Mips_SLTi_MM = 2808, + Mips_SLTiu = 2809, + Mips_SLTiu64 = 2810, + Mips_SLTiu_MM = 2811, + Mips_SLTu = 2812, + Mips_SLTu64 = 2813, + Mips_SLTu_MM = 2814, + Mips_SNE = 2815, + Mips_SNEi = 2816, + Mips_SOV_NM = 2817, + Mips_SPLATI_B = 2818, + Mips_SPLATI_D = 2819, + Mips_SPLATI_H = 2820, + Mips_SPLATI_W = 2821, + Mips_SPLAT_B = 2822, + Mips_SPLAT_D = 2823, + Mips_SPLAT_H = 2824, + Mips_SPLAT_W = 2825, + Mips_SRA = 2826, + Mips_SRAI_B = 2827, + Mips_SRAI_D = 2828, + Mips_SRAI_H = 2829, + Mips_SRAI_W = 2830, + Mips_SRARI_B = 2831, + Mips_SRARI_D = 2832, + Mips_SRARI_H = 2833, + Mips_SRARI_W = 2834, + Mips_SRAR_B = 2835, + Mips_SRAR_D = 2836, + Mips_SRAR_H = 2837, + Mips_SRAR_W = 2838, + Mips_SRAV = 2839, + Mips_SRAV_MM = 2840, + Mips_SRAV_NM = 2841, + Mips_SRA_B = 2842, + Mips_SRA_D = 2843, + Mips_SRA_H = 2844, + Mips_SRA_MM = 2845, + Mips_SRA_NM = 2846, + Mips_SRA_W = 2847, + Mips_SRL = 2848, + Mips_SRL16_MM = 2849, + Mips_SRL16_MMR6 = 2850, + Mips_SRL16_NM = 2851, + Mips_SRLI_B = 2852, + Mips_SRLI_D = 2853, + Mips_SRLI_H = 2854, + Mips_SRLI_W = 2855, + Mips_SRLRI_B = 2856, + Mips_SRLRI_D = 2857, + Mips_SRLRI_H = 2858, + Mips_SRLRI_W = 2859, + Mips_SRLR_B = 2860, + Mips_SRLR_D = 2861, + Mips_SRLR_H = 2862, + Mips_SRLR_W = 2863, + Mips_SRLV = 2864, + Mips_SRLV_MM = 2865, + Mips_SRLV_NM = 2866, + Mips_SRL_B = 2867, + Mips_SRL_D = 2868, + Mips_SRL_H = 2869, + Mips_SRL_MM = 2870, + Mips_SRL_NM = 2871, + Mips_SRL_W = 2872, + Mips_SSNOP = 2873, + Mips_SSNOP_MM = 2874, + Mips_SSNOP_MMR6 = 2875, + Mips_ST_B = 2876, + Mips_ST_D = 2877, + Mips_ST_H = 2878, + Mips_ST_W = 2879, + Mips_SUB = 2880, + Mips_SUBQH_PH = 2881, + Mips_SUBQH_PH_MMR2 = 2882, + Mips_SUBQH_R_PH = 2883, + Mips_SUBQH_R_PH_MMR2 = 2884, + Mips_SUBQH_R_W = 2885, + Mips_SUBQH_R_W_MMR2 = 2886, + Mips_SUBQH_W = 2887, + Mips_SUBQH_W_MMR2 = 2888, + Mips_SUBQ_PH = 2889, + Mips_SUBQ_PH_MM = 2890, + Mips_SUBQ_S_PH = 2891, + Mips_SUBQ_S_PH_MM = 2892, + Mips_SUBQ_S_W = 2893, + Mips_SUBQ_S_W_MM = 2894, + Mips_SUBSUS_U_B = 2895, + Mips_SUBSUS_U_D = 2896, + Mips_SUBSUS_U_H = 2897, + Mips_SUBSUS_U_W = 2898, + Mips_SUBSUU_S_B = 2899, + Mips_SUBSUU_S_D = 2900, + Mips_SUBSUU_S_H = 2901, + Mips_SUBSUU_S_W = 2902, + Mips_SUBS_S_B = 2903, + Mips_SUBS_S_D = 2904, + Mips_SUBS_S_H = 2905, + Mips_SUBS_S_W = 2906, + Mips_SUBS_U_B = 2907, + Mips_SUBS_U_D = 2908, + Mips_SUBS_U_H = 2909, + Mips_SUBS_U_W = 2910, + Mips_SUBU16_MM = 2911, + Mips_SUBU16_MMR6 = 2912, + Mips_SUBUH_QB = 2913, + Mips_SUBUH_QB_MMR2 = 2914, + Mips_SUBUH_R_QB = 2915, + Mips_SUBUH_R_QB_MMR2 = 2916, + Mips_SUBU_MMR6 = 2917, + Mips_SUBU_PH = 2918, + Mips_SUBU_PH_MMR2 = 2919, + Mips_SUBU_QB = 2920, + Mips_SUBU_QB_MM = 2921, + Mips_SUBU_S_PH = 2922, + Mips_SUBU_S_PH_MMR2 = 2923, + Mips_SUBU_S_QB = 2924, + Mips_SUBU_S_QB_MM = 2925, + Mips_SUBVI_B = 2926, + Mips_SUBVI_D = 2927, + Mips_SUBVI_H = 2928, + Mips_SUBVI_W = 2929, + Mips_SUBV_B = 2930, + Mips_SUBV_D = 2931, + Mips_SUBV_H = 2932, + Mips_SUBV_W = 2933, + Mips_SUB_MM = 2934, + Mips_SUB_MMR6 = 2935, + Mips_SUB_NM = 2936, + Mips_SUBu = 2937, + Mips_SUBu16_NM = 2938, + Mips_SUBu_MM = 2939, + Mips_SUBu_NM = 2940, + Mips_SUXC1 = 2941, + Mips_SUXC164 = 2942, + Mips_SUXC1_MM = 2943, + Mips_SW = 2944, + Mips_SW16_MM = 2945, + Mips_SW16_MMR6 = 2946, + Mips_SW16_NM = 2947, + Mips_SW4x4_NM = 2948, + Mips_SW64 = 2949, + Mips_SWC1 = 2950, + Mips_SWC1_MM = 2951, + Mips_SWC2 = 2952, + Mips_SWC2_MMR6 = 2953, + Mips_SWC2_R6 = 2954, + Mips_SWC3 = 2955, + Mips_SWDSP = 2956, + Mips_SWDSP_MM = 2957, + Mips_SWE = 2958, + Mips_SWE_MM = 2959, + Mips_SWGP16_NM = 2960, + Mips_SWGP_NM = 2961, + Mips_SWL = 2962, + Mips_SWL64 = 2963, + Mips_SWLE = 2964, + Mips_SWLE_MM = 2965, + Mips_SWL_MM = 2966, + Mips_SWM16_MM = 2967, + Mips_SWM16_MMR6 = 2968, + Mips_SWM32_MM = 2969, + Mips_SWM_NM = 2970, + Mips_SWPC_NM = 2971, + Mips_SWP_MM = 2972, + Mips_SWR = 2973, + Mips_SWR64 = 2974, + Mips_SWRE = 2975, + Mips_SWRE_MM = 2976, + Mips_SWR_MM = 2977, + Mips_SWSP16_NM = 2978, + Mips_SWSP_MM = 2979, + Mips_SWSP_MMR6 = 2980, + Mips_SWXC1 = 2981, + Mips_SWXC1_MM = 2982, + Mips_SWXS_NM = 2983, + Mips_SWX_NM = 2984, + Mips_SW_MM = 2985, + Mips_SW_MMR6 = 2986, + Mips_SW_NM = 2987, + Mips_SWs9_NM = 2988, + Mips_SYNC = 2989, + Mips_SYNCI = 2990, + Mips_SYNCI_MM = 2991, + Mips_SYNCI_MMR6 = 2992, + Mips_SYNCI_NM = 2993, + Mips_SYNCIs9_NM = 2994, + Mips_SYNC_MM = 2995, + Mips_SYNC_MMR6 = 2996, + Mips_SYNC_NM = 2997, + Mips_SYSCALL = 2998, + Mips_SYSCALL16_NM = 2999, + Mips_SYSCALL_MM = 3000, + Mips_SYSCALL_NM = 3001, + Mips_Save16 = 3002, + Mips_SaveX16 = 3003, + Mips_SbRxRyOffMemX16 = 3004, + Mips_SebRx16 = 3005, + Mips_SehRx16 = 3006, + Mips_ShRxRyOffMemX16 = 3007, + Mips_SllX16 = 3008, + Mips_SllvRxRy16 = 3009, + Mips_SltRxRy16 = 3010, + Mips_SltiRxImm16 = 3011, + Mips_SltiRxImmX16 = 3012, + Mips_SltiuRxImm16 = 3013, + Mips_SltiuRxImmX16 = 3014, + Mips_SltuRxRy16 = 3015, + Mips_SraX16 = 3016, + Mips_SravRxRy16 = 3017, + Mips_SrlX16 = 3018, + Mips_SrlvRxRy16 = 3019, + Mips_SubuRxRyRz16 = 3020, + Mips_SwRxRyOffMemX16 = 3021, + Mips_SwRxSpImmX16 = 3022, + Mips_TEQ = 3023, + Mips_TEQI = 3024, + Mips_TEQI_MM = 3025, + Mips_TEQ_MM = 3026, + Mips_TEQ_NM = 3027, + Mips_TGE = 3028, + Mips_TGEI = 3029, + Mips_TGEIU = 3030, + Mips_TGEIU_MM = 3031, + Mips_TGEI_MM = 3032, + Mips_TGEU = 3033, + Mips_TGEU_MM = 3034, + Mips_TGE_MM = 3035, + Mips_TLBGINV = 3036, + Mips_TLBGINVF = 3037, + Mips_TLBGINVF_MM = 3038, + Mips_TLBGINV_MM = 3039, + Mips_TLBGP = 3040, + Mips_TLBGP_MM = 3041, + Mips_TLBGR = 3042, + Mips_TLBGR_MM = 3043, + Mips_TLBGWI = 3044, + Mips_TLBGWI_MM = 3045, + Mips_TLBGWR = 3046, + Mips_TLBGWR_MM = 3047, + Mips_TLBINV = 3048, + Mips_TLBINVF = 3049, + Mips_TLBINVF_MMR6 = 3050, + Mips_TLBINVF_NM = 3051, + Mips_TLBINV_MMR6 = 3052, + Mips_TLBINV_NM = 3053, + Mips_TLBP = 3054, + Mips_TLBP_MM = 3055, + Mips_TLBP_NM = 3056, + Mips_TLBR = 3057, + Mips_TLBR_MM = 3058, + Mips_TLBR_NM = 3059, + Mips_TLBWI = 3060, + Mips_TLBWI_MM = 3061, + Mips_TLBWI_NM = 3062, + Mips_TLBWR = 3063, + Mips_TLBWR_MM = 3064, + Mips_TLBWR_NM = 3065, + Mips_TLT = 3066, + Mips_TLTI = 3067, + Mips_TLTIU_MM = 3068, + Mips_TLTI_MM = 3069, + Mips_TLTU = 3070, + Mips_TLTU_MM = 3071, + Mips_TLT_MM = 3072, + Mips_TNE = 3073, + Mips_TNEI = 3074, + Mips_TNEI_MM = 3075, + Mips_TNE_MM = 3076, + Mips_TNE_NM = 3077, + Mips_TRUNC_L_D64 = 3078, + Mips_TRUNC_L_D_MMR6 = 3079, + Mips_TRUNC_L_S = 3080, + Mips_TRUNC_L_S_MMR6 = 3081, + Mips_TRUNC_W_D32 = 3082, + Mips_TRUNC_W_D64 = 3083, + Mips_TRUNC_W_D_MMR6 = 3084, + Mips_TRUNC_W_MM = 3085, + Mips_TRUNC_W_S = 3086, + Mips_TRUNC_W_S_MM = 3087, + Mips_TRUNC_W_S_MMR6 = 3088, + Mips_TTLTIU = 3089, + Mips_UALH_NM = 3090, + Mips_UALWM_NM = 3091, + Mips_UALW_NM = 3092, + Mips_UASH_NM = 3093, + Mips_UASWM_NM = 3094, + Mips_UASW_NM = 3095, + Mips_UDIV = 3096, + Mips_UDIV_MM = 3097, + Mips_V3MULU = 3098, + Mips_VMM0 = 3099, + Mips_VMULU = 3100, + Mips_VSHF_B = 3101, + Mips_VSHF_D = 3102, + Mips_VSHF_H = 3103, + Mips_VSHF_W = 3104, + Mips_WAIT = 3105, + Mips_WAIT_MM = 3106, + Mips_WAIT_MMR6 = 3107, + Mips_WAIT_NM = 3108, + Mips_WRDSP = 3109, + Mips_WRDSP_MM = 3110, + Mips_WRPGPR_MMR6 = 3111, + Mips_WRPGPR_NM = 3112, + Mips_WSBH = 3113, + Mips_WSBH_MM = 3114, + Mips_WSBH_MMR6 = 3115, + Mips_XOR = 3116, + Mips_XOR16_MM = 3117, + Mips_XOR16_MMR6 = 3118, + Mips_XOR16_NM = 3119, + Mips_XOR64 = 3120, + Mips_XORI_B = 3121, + Mips_XORI_MMR6 = 3122, + Mips_XORI_NM = 3123, + Mips_XOR_MM = 3124, + Mips_XOR_MMR6 = 3125, + Mips_XOR_NM = 3126, + Mips_XOR_V = 3127, + Mips_XORi = 3128, + Mips_XORi64 = 3129, + Mips_XORi_MM = 3130, + Mips_XorRxRxRy16 = 3131, + Mips_YIELD = 3132, + Mips_YIELD_NM = 3133, + INSTRUCTION_LIST_END = 3134 + }; #endif // GET_INSTRINFO_ENUM + +#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) +typedef struct MipsInstrTable { + MCInstrDesc Insts[3134]; + MCOperandInfo OperandInfo[1301]; + MCPhysReg ImplicitOps[70]; +} MipsInstrTable; + +#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) + +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const unsigned MipsImpOpBase = sizeof(MCOperandInfo) / (sizeof(MCPhysReg)); + +static const MipsInstrTable MipsDescs = { + { + { 2, &MipsDescs.OperandInfo[416] }, // Inst #3133 = YIELD_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3132 = YIELD + { 3, &MipsDescs.OperandInfo[626] }, // Inst #3131 = XorRxRxRy16 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3130 = XORi_MM + { 3, &MipsDescs.OperandInfo[224] }, // Inst #3129 = XORi64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3128 = XORi + { 3, &MipsDescs.OperandInfo[578] }, // Inst #3127 = XOR_V + { 3, &MipsDescs.OperandInfo[596] }, // Inst #3126 = XOR_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #3125 = XOR_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #3124 = XOR_MM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #3123 = XORI_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3122 = XORI_MMR6 + { 3, &MipsDescs.OperandInfo[584] }, // Inst #3121 = XORI_B + { 3, &MipsDescs.OperandInfo[227] }, // Inst #3120 = XOR64 + { 3, &MipsDescs.OperandInfo[599] }, // Inst #3119 = XOR16_NM + { 3, &MipsDescs.OperandInfo[611] }, // Inst #3118 = XOR16_MMR6 + { 3, &MipsDescs.OperandInfo[611] }, // Inst #3117 = XOR16_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #3116 = XOR + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3115 = WSBH_MMR6 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3114 = WSBH_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3113 = WSBH + { 2, &MipsDescs.OperandInfo[416] }, // Inst #3112 = WRPGPR_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3111 = WRPGPR_MMR6 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3110 = WRDSP_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3109 = WRDSP + { 1, &MipsDescs.OperandInfo[0] }, // Inst #3108 = WAIT_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #3107 = WAIT_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #3106 = WAIT_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3105 = WAIT + { 4, &MipsDescs.OperandInfo[194] }, // Inst #3104 = VSHF_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #3103 = VSHF_H + { 4, &MipsDescs.OperandInfo[190] }, // Inst #3102 = VSHF_D + { 4, &MipsDescs.OperandInfo[672] }, // Inst #3101 = VSHF_B + { 3, &MipsDescs.OperandInfo[227] }, // Inst #3100 = VMULU + { 3, &MipsDescs.OperandInfo[227] }, // Inst #3099 = VMM0 + { 3, &MipsDescs.OperandInfo[227] }, // Inst #3098 = V3MULU + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3097 = UDIV_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3096 = UDIV + { 3, &MipsDescs.OperandInfo[928] }, // Inst #3095 = UASW_NM + { 4, &MipsDescs.OperandInfo[1010] }, // Inst #3094 = UASWM_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #3093 = UASH_NM + { 4, &MipsDescs.OperandInfo[1297] }, // Inst #3092 = UALW_NM + { 4, &MipsDescs.OperandInfo[1010] }, // Inst #3091 = UALWM_NM + { 4, &MipsDescs.OperandInfo[1297] }, // Inst #3090 = UALH_NM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3089 = TTLTIU + { 2, &MipsDescs.OperandInfo[699] }, // Inst #3088 = TRUNC_W_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #3087 = TRUNC_W_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #3086 = TRUNC_W_S + { 2, &MipsDescs.OperandInfo[695] }, // Inst #3085 = TRUNC_W_MM + { 2, &MipsDescs.OperandInfo[697] }, // Inst #3084 = TRUNC_W_D_MMR6 + { 2, &MipsDescs.OperandInfo[697] }, // Inst #3083 = TRUNC_W_D64 + { 2, &MipsDescs.OperandInfo[695] }, // Inst #3082 = TRUNC_W_D32 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #3081 = TRUNC_L_S_MMR6 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #3080 = TRUNC_L_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #3079 = TRUNC_L_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #3078 = TRUNC_L_D64 + { 3, &MipsDescs.OperandInfo[391] }, // Inst #3077 = TNE_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3076 = TNE_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3075 = TNEI_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3074 = TNEI + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3073 = TNE + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3072 = TLT_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3071 = TLTU_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3070 = TLTU + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3069 = TLTI_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3068 = TLTIU_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3067 = TLTI + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3066 = TLT + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3065 = TLBWR_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3064 = TLBWR_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3063 = TLBWR + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3062 = TLBWI_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3061 = TLBWI_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3060 = TLBWI + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3059 = TLBR_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3058 = TLBR_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3057 = TLBR + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3056 = TLBP_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3055 = TLBP_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3054 = TLBP + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3053 = TLBINV_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3052 = TLBINV_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3051 = TLBINVF_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3050 = TLBINVF_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3049 = TLBINVF + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3048 = TLBINV + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3047 = TLBGWR_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3046 = TLBGWR + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3045 = TLBGWI_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3044 = TLBGWI + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3043 = TLBGR_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3042 = TLBGR + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3041 = TLBGP_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3040 = TLBGP + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3039 = TLBGINV_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3038 = TLBGINVF_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3037 = TLBGINVF + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3036 = TLBGINV + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3035 = TGE_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3034 = TGEU_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3033 = TGEU + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3032 = TGEI_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3031 = TGEIU_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3030 = TGEIU + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3029 = TGEI + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3028 = TGE + { 3, &MipsDescs.OperandInfo[391] }, // Inst #3027 = TEQ_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3026 = TEQ_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3025 = TEQI_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3024 = TEQI + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3023 = TEQ + { 3, &MipsDescs.OperandInfo[623] }, // Inst #3022 = SwRxSpImmX16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #3021 = SwRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[421] }, // Inst #3020 = SubuRxRyRz16 + { 3, &MipsDescs.OperandInfo[626] }, // Inst #3019 = SrlvRxRy16 + { 3, &MipsDescs.OperandInfo[547] }, // Inst #3018 = SrlX16 + { 3, &MipsDescs.OperandInfo[626] }, // Inst #3017 = SravRxRy16 + { 3, &MipsDescs.OperandInfo[547] }, // Inst #3016 = SraX16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #3015 = SltuRxRy16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #3014 = SltiuRxImmX16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #3013 = SltiuRxImm16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #3012 = SltiRxImmX16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #3011 = SltiRxImm16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #3010 = SltRxRy16 + { 3, &MipsDescs.OperandInfo[626] }, // Inst #3009 = SllvRxRy16 + { 3, &MipsDescs.OperandInfo[547] }, // Inst #3008 = SllX16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #3007 = ShRxRyOffMemX16 + { 2, &MipsDescs.OperandInfo[1295] }, // Inst #3006 = SehRx16 + { 2, &MipsDescs.OperandInfo[1295] }, // Inst #3005 = SebRx16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #3004 = SbRxRyOffMemX16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3003 = SaveX16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3002 = Save16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #3001 = SYSCALL_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #3000 = SYSCALL_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2999 = SYSCALL16_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2998 = SYSCALL + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2997 = SYNC_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2996 = SYNC_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2995 = SYNC_MM + { 2, &MipsDescs.OperandInfo[1293] }, // Inst #2994 = SYNCIs9_NM + { 2, &MipsDescs.OperandInfo[1293] }, // Inst #2993 = SYNCI_NM + { 2, &MipsDescs.OperandInfo[1293] }, // Inst #2992 = SYNCI_MMR6 + { 2, &MipsDescs.OperandInfo[1293] }, // Inst #2991 = SYNCI_MM + { 2, &MipsDescs.OperandInfo[1293] }, // Inst #2990 = SYNCI + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2989 = SYNC + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2988 = SWs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2987 = SW_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2986 = SW_MMR6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2985 = SW_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2984 = SWX_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2983 = SWXS_NM + { 3, &MipsDescs.OperandInfo[1024] }, // Inst #2982 = SWXC1_MM + { 3, &MipsDescs.OperandInfo[1024] }, // Inst #2981 = SWXC1 + { 3, &MipsDescs.OperandInfo[1021] }, // Inst #2980 = SWSP_MMR6 + { 3, &MipsDescs.OperandInfo[1021] }, // Inst #2979 = SWSP_MM + { 3, &MipsDescs.OperandInfo[1018] }, // Inst #2978 = SWSP16_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2977 = SWR_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2976 = SWRE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2975 = SWRE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2974 = SWR64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2973 = SWR + { 4, &MipsDescs.OperandInfo[1014] }, // Inst #2972 = SWP_MM + { 2, &MipsDescs.OperandInfo[609] }, // Inst #2971 = SWPC_NM + { 4, &MipsDescs.OperandInfo[1010] }, // Inst #2970 = SWM_NM + { 3, &MipsDescs.OperandInfo[354] }, // Inst #2969 = SWM32_MM + { 3, &MipsDescs.OperandInfo[1007] }, // Inst #2968 = SWM16_MMR6 + { 3, &MipsDescs.OperandInfo[1007] }, // Inst #2967 = SWM16_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2966 = SWL_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2965 = SWLE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2964 = SWLE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2963 = SWL64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2962 = SWL + { 3, &MipsDescs.OperandInfo[1000] }, // Inst #2961 = SWGP_NM + { 3, &MipsDescs.OperandInfo[1290] }, // Inst #2960 = SWGP16_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2959 = SWE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2958 = SWE + { 3, &MipsDescs.OperandInfo[991] }, // Inst #2957 = SWDSP_MM + { 3, &MipsDescs.OperandInfo[991] }, // Inst #2956 = SWDSP + { 3, &MipsDescs.OperandInfo[940] }, // Inst #2955 = SWC3 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #2954 = SWC2_R6 + { 3, &MipsDescs.OperandInfo[937] }, // Inst #2953 = SWC2_MMR6 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #2952 = SWC2 + { 3, &MipsDescs.OperandInfo[988] }, // Inst #2951 = SWC1_MM + { 3, &MipsDescs.OperandInfo[988] }, // Inst #2950 = SWC1 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2949 = SW64 + { 3, &MipsDescs.OperandInfo[1287] }, // Inst #2948 = SW4x4_NM + { 3, &MipsDescs.OperandInfo[1212] }, // Inst #2947 = SW16_NM + { 3, &MipsDescs.OperandInfo[1209] }, // Inst #2946 = SW16_MMR6 + { 3, &MipsDescs.OperandInfo[1209] }, // Inst #2945 = SW16_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2944 = SW + { 3, &MipsDescs.OperandInfo[958] }, // Inst #2943 = SUXC1_MM + { 3, &MipsDescs.OperandInfo[958] }, // Inst #2942 = SUXC164 + { 3, &MipsDescs.OperandInfo[955] }, // Inst #2941 = SUXC1 + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2940 = SUBu_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2939 = SUBu_MM + { 3, &MipsDescs.OperandInfo[599] }, // Inst #2938 = SUBu16_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2937 = SUBu + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2936 = SUB_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2935 = SUB_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2934 = SUB_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2933 = SUBV_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2932 = SUBV_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2931 = SUBV_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2930 = SUBV_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2929 = SUBVI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2928 = SUBVI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2927 = SUBVI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2926 = SUBVI_B + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2925 = SUBU_S_QB_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2924 = SUBU_S_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2923 = SUBU_S_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2922 = SUBU_S_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2921 = SUBU_QB_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2920 = SUBU_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2919 = SUBU_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2918 = SUBU_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2917 = SUBU_MMR6 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2916 = SUBUH_R_QB_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2915 = SUBUH_R_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2914 = SUBUH_QB_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2913 = SUBUH_QB + { 3, &MipsDescs.OperandInfo[581] }, // Inst #2912 = SUBU16_MMR6 + { 3, &MipsDescs.OperandInfo[581] }, // Inst #2911 = SUBU16_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2910 = SUBS_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2909 = SUBS_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2908 = SUBS_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2907 = SUBS_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2906 = SUBS_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2905 = SUBS_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2904 = SUBS_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2903 = SUBS_S_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2902 = SUBSUU_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2901 = SUBSUU_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2900 = SUBSUU_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2899 = SUBSUU_S_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2898 = SUBSUS_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2897 = SUBSUS_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2896 = SUBSUS_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2895 = SUBSUS_U_B + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2894 = SUBQ_S_W_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2893 = SUBQ_S_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2892 = SUBQ_S_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2891 = SUBQ_S_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2890 = SUBQ_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2889 = SUBQ_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2888 = SUBQH_W_MMR2 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2887 = SUBQH_W + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2886 = SUBQH_R_W_MMR2 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2885 = SUBQH_R_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2884 = SUBQH_R_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2883 = SUBQH_R_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2882 = SUBQH_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2881 = SUBQH_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2880 = SUB + { 3, &MipsDescs.OperandInfo[970] }, // Inst #2879 = ST_W + { 3, &MipsDescs.OperandInfo[967] }, // Inst #2878 = ST_H + { 3, &MipsDescs.OperandInfo[964] }, // Inst #2877 = ST_D + { 3, &MipsDescs.OperandInfo[961] }, // Inst #2876 = ST_B + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2875 = SSNOP_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2874 = SSNOP_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2873 = SSNOP + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2872 = SRL_W + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2871 = SRL_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2870 = SRL_MM + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2869 = SRL_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2868 = SRL_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2867 = SRL_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2866 = SRLV_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2865 = SRLV_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2864 = SRLV + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2863 = SRLR_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2862 = SRLR_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2861 = SRLR_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2860 = SRLR_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2859 = SRLRI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2858 = SRLRI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2857 = SRLRI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2856 = SRLRI_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2855 = SRLI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2854 = SRLI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2853 = SRLI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2852 = SRLI_B + { 3, &MipsDescs.OperandInfo[566] }, // Inst #2851 = SRL16_NM + { 3, &MipsDescs.OperandInfo[563] }, // Inst #2850 = SRL16_MMR6 + { 3, &MipsDescs.OperandInfo[563] }, // Inst #2849 = SRL16_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2848 = SRL + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2847 = SRA_W + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2846 = SRA_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2845 = SRA_MM + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2844 = SRA_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2843 = SRA_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2842 = SRA_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2841 = SRAV_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2840 = SRAV_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2839 = SRAV + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2838 = SRAR_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2837 = SRAR_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2836 = SRAR_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2835 = SRAR_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2834 = SRARI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2833 = SRARI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2832 = SRARI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2831 = SRARI_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2830 = SRAI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2829 = SRAI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2828 = SRAI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2827 = SRAI_B + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2826 = SRA + { 3, &MipsDescs.OperandInfo[1284] }, // Inst #2825 = SPLAT_W + { 3, &MipsDescs.OperandInfo[1281] }, // Inst #2824 = SPLAT_H + { 3, &MipsDescs.OperandInfo[1278] }, // Inst #2823 = SPLAT_D + { 3, &MipsDescs.OperandInfo[1275] }, // Inst #2822 = SPLAT_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2821 = SPLATI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2820 = SPLATI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2819 = SPLATI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2818 = SPLATI_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2817 = SOV_NM + { 3, &MipsDescs.OperandInfo[224] }, // Inst #2816 = SNEi + { 3, &MipsDescs.OperandInfo[227] }, // Inst #2815 = SNE + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2814 = SLTu_MM + { 3, &MipsDescs.OperandInfo[1269] }, // Inst #2813 = SLTu64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2812 = SLTu + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2811 = SLTiu_MM + { 3, &MipsDescs.OperandInfo[1272] }, // Inst #2810 = SLTiu64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2809 = SLTiu + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2808 = SLTi_MM + { 3, &MipsDescs.OperandInfo[1272] }, // Inst #2807 = SLTi64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2806 = SLTi + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2805 = SLT_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2804 = SLT_MM + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2803 = SLTU_NM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2802 = SLTI_NM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2801 = SLTIU_NM + { 3, &MipsDescs.OperandInfo[1269] }, // Inst #2800 = SLT64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2799 = SLT + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2798 = SLL_W + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2797 = SLL_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2796 = SLL_MMR6 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2795 = SLL_MM + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2794 = SLL_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2793 = SLL_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2792 = SLL_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2791 = SLLV_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2790 = SLLV_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2789 = SLLV + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2788 = SLLI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2787 = SLLI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2786 = SLLI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2785 = SLLI_B + { 2, &MipsDescs.OperandInfo[394] }, // Inst #2784 = SLL64_64 + { 2, &MipsDescs.OperandInfo[817] }, // Inst #2783 = SLL64_32 + { 3, &MipsDescs.OperandInfo[566] }, // Inst #2782 = SLL16_NM + { 3, &MipsDescs.OperandInfo[563] }, // Inst #2781 = SLL16_MMR6 + { 3, &MipsDescs.OperandInfo[563] }, // Inst #2780 = SLL16_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2779 = SLL + { 4, &MipsDescs.OperandInfo[1265] }, // Inst #2778 = SLD_W + { 4, &MipsDescs.OperandInfo[1261] }, // Inst #2777 = SLD_H + { 4, &MipsDescs.OperandInfo[1257] }, // Inst #2776 = SLD_D + { 4, &MipsDescs.OperandInfo[1253] }, // Inst #2775 = SLD_B + { 4, &MipsDescs.OperandInfo[668] }, // Inst #2774 = SLDI_W + { 4, &MipsDescs.OperandInfo[664] }, // Inst #2773 = SLDI_H + { 4, &MipsDescs.OperandInfo[660] }, // Inst #2772 = SLDI_D + { 4, &MipsDescs.OperandInfo[656] }, // Inst #2771 = SLDI_B + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2770 = SIGRIE_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2769 = SIGRIE_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2768 = SIGRIE + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2767 = SHs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2766 = SH_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2765 = SH_MMR6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2764 = SH_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2763 = SHX_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2762 = SHXS_NM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2761 = SHRL_QB_MM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2760 = SHRL_QB + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2759 = SHRL_PH_MMR2 + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2758 = SHRL_PH + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2757 = SHRLV_QB_MM + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2756 = SHRLV_QB + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2755 = SHRLV_PH_MMR2 + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2754 = SHRLV_PH + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2753 = SHRA_R_W_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2752 = SHRA_R_W + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2751 = SHRA_R_QB_MMR2 + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2750 = SHRA_R_QB + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2749 = SHRA_R_PH_MM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2748 = SHRA_R_PH + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2747 = SHRA_QB_MMR2 + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2746 = SHRA_QB + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2745 = SHRA_PH_MM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2744 = SHRA_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2743 = SHRAV_R_W_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2742 = SHRAV_R_W + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2741 = SHRAV_R_QB_MMR2 + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2740 = SHRAV_R_QB + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2739 = SHRAV_R_PH_MM + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2738 = SHRAV_R_PH + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2737 = SHRAV_QB_MMR2 + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2736 = SHRAV_QB + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2735 = SHRAV_PH_MM + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2734 = SHRAV_PH + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2733 = SHLL_S_W_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2732 = SHLL_S_W + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2731 = SHLL_S_PH_MM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2730 = SHLL_S_PH + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2729 = SHLL_QB_MM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2728 = SHLL_QB + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2727 = SHLL_PH_MM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2726 = SHLL_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2725 = SHLLV_S_W_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2724 = SHLLV_S_W + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2723 = SHLLV_S_PH_MM + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2722 = SHLLV_S_PH + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2721 = SHLLV_QB_MM + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2720 = SHLLV_QB + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2719 = SHLLV_PH_MM + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2718 = SHLLV_PH + { 3, &MipsDescs.OperandInfo[1244] }, // Inst #2717 = SHILO_MM + { 3, &MipsDescs.OperandInfo[1160] }, // Inst #2716 = SHILOV_MM + { 3, &MipsDescs.OperandInfo[1160] }, // Inst #2715 = SHILOV + { 3, &MipsDescs.OperandInfo[1244] }, // Inst #2714 = SHILO + { 3, &MipsDescs.OperandInfo[919] }, // Inst #2713 = SHGP_NM + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2712 = SHF_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2711 = SHF_H + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2710 = SHF_B + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2709 = SHE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2708 = SHE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2707 = SH64 + { 3, &MipsDescs.OperandInfo[1212] }, // Inst #2706 = SH16_NM + { 3, &MipsDescs.OperandInfo[1209] }, // Inst #2705 = SH16_MMR6 + { 3, &MipsDescs.OperandInfo[1209] }, // Inst #2704 = SH16_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2703 = SH + { 3, &MipsDescs.OperandInfo[224] }, // Inst #2702 = SEQi + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2701 = SEQI_NM + { 3, &MipsDescs.OperandInfo[227] }, // Inst #2700 = SEQ + { 4, &MipsDescs.OperandInfo[1240] }, // Inst #2699 = SEL_S_MMR6 + { 4, &MipsDescs.OperandInfo[1240] }, // Inst #2698 = SEL_S + { 4, &MipsDescs.OperandInfo[1033] }, // Inst #2697 = SEL_D_MMR6 + { 4, &MipsDescs.OperandInfo[1033] }, // Inst #2696 = SEL_D + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2695 = SELNEZ_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2694 = SELNEZ_S + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2693 = SELNEZ_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2692 = SELNEZ_D_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2691 = SELNEZ_D + { 3, &MipsDescs.OperandInfo[227] }, // Inst #2690 = SELNEZ64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2689 = SELNEZ + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2688 = SELEQZ_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2687 = SELEQZ_S + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2686 = SELEQZ_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2685 = SELEQZ_D_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2684 = SELEQZ_D + { 3, &MipsDescs.OperandInfo[227] }, // Inst #2683 = SELEQZ64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2682 = SELEQZ + { 2, &MipsDescs.OperandInfo[416] }, // Inst #2681 = SEH_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2680 = SEH_MM + { 2, &MipsDescs.OperandInfo[394] }, // Inst #2679 = SEH64 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2678 = SEH + { 2, &MipsDescs.OperandInfo[416] }, // Inst #2677 = SEB_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2676 = SEB_MM + { 2, &MipsDescs.OperandInfo[394] }, // Inst #2675 = SEB64 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2674 = SEB + { 3, &MipsDescs.OperandInfo[958] }, // Inst #2673 = SDXC164 + { 3, &MipsDescs.OperandInfo[955] }, // Inst #2672 = SDXC1 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2671 = SDR + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2670 = SDL + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2669 = SDIV_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2668 = SDIV + { 3, &MipsDescs.OperandInfo[940] }, // Inst #2667 = SDC3 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #2666 = SDC2_R6 + { 3, &MipsDescs.OperandInfo[937] }, // Inst #2665 = SDC2_MMR6 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #2664 = SDC2 + { 3, &MipsDescs.OperandInfo[931] }, // Inst #2663 = SDC1_MM_D64 + { 3, &MipsDescs.OperandInfo[519] }, // Inst #2662 = SDC1_MM_D32 + { 3, &MipsDescs.OperandInfo[931] }, // Inst #2661 = SDC1_D64_MMR6 + { 3, &MipsDescs.OperandInfo[931] }, // Inst #2660 = SDC164 + { 3, &MipsDescs.OperandInfo[519] }, // Inst #2659 = SDC1 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2658 = SDBBP_R6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2657 = SDBBP_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2656 = SDBBP_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2655 = SDBBP_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2654 = SDBBP16_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2653 = SDBBP16_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2652 = SDBBP16_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2651 = SDBBP + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2650 = SD + { 4, &MipsDescs.OperandInfo[1219] }, // Inst #2649 = SC_R6 + { 4, &MipsDescs.OperandInfo[1236] }, // Inst #2648 = SC_NM + { 4, &MipsDescs.OperandInfo[1215] }, // Inst #2647 = SC_MMR6 + { 4, &MipsDescs.OperandInfo[1215] }, // Inst #2646 = SC_MM + { 5, &MipsDescs.OperandInfo[1231] }, // Inst #2645 = SCWP_NM + { 4, &MipsDescs.OperandInfo[1215] }, // Inst #2644 = SCE_MM + { 4, &MipsDescs.OperandInfo[1215] }, // Inst #2643 = SCE + { 4, &MipsDescs.OperandInfo[1227] }, // Inst #2642 = SCD_R6 + { 4, &MipsDescs.OperandInfo[1223] }, // Inst #2641 = SCD + { 4, &MipsDescs.OperandInfo[1219] }, // Inst #2640 = SC64_R6 + { 4, &MipsDescs.OperandInfo[1215] }, // Inst #2639 = SC64 + { 4, &MipsDescs.OperandInfo[1215] }, // Inst #2638 = SC + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2637 = SBs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2636 = SB_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2635 = SB_MMR6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2634 = SB_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2633 = SBX_NM + { 3, &MipsDescs.OperandInfo[919] }, // Inst #2632 = SBGP_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2631 = SBE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2630 = SBE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2629 = SB64 + { 3, &MipsDescs.OperandInfo[1212] }, // Inst #2628 = SB16_NM + { 3, &MipsDescs.OperandInfo[1209] }, // Inst #2627 = SB16_MMR6 + { 3, &MipsDescs.OperandInfo[1209] }, // Inst #2626 = SB16_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2625 = SB + { 2, &MipsDescs.OperandInfo[1202] }, // Inst #2624 = SAVE_NM + { 2, &MipsDescs.OperandInfo[1202] }, // Inst #2623 = SAVE16_NM + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2622 = SAT_U_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2621 = SAT_U_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2620 = SAT_U_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2619 = SAT_U_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2618 = SAT_S_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2617 = SAT_S_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2616 = SAT_S_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2615 = SAT_S_B + { 2, &MipsDescs.OperandInfo[394] }, // Inst #2614 = SAAD + { 2, &MipsDescs.OperandInfo[394] }, // Inst #2613 = SAA + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2612 = RestoreX16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2611 = Restore16 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2610 = RSQRT_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2609 = RSQRT_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2608 = RSQRT_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2607 = RSQRT_D64 + { 2, &MipsDescs.OperandInfo[829] }, // Inst #2606 = RSQRT_D32_MM + { 2, &MipsDescs.OperandInfo[829] }, // Inst #2605 = RSQRT_D32 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2604 = ROUND_W_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2603 = ROUND_W_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2602 = ROUND_W_S + { 2, &MipsDescs.OperandInfo[695] }, // Inst #2601 = ROUND_W_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2600 = ROUND_W_D_MMR6 + { 2, &MipsDescs.OperandInfo[697] }, // Inst #2599 = ROUND_W_D64 + { 2, &MipsDescs.OperandInfo[695] }, // Inst #2598 = ROUND_W_D32 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #2597 = ROUND_L_S_MMR6 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #2596 = ROUND_L_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2595 = ROUND_L_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2594 = ROUND_L_D64 + { 5, &MipsDescs.OperandInfo[1204] }, // Inst #2593 = ROTX_NM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2592 = ROTR_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2591 = ROTR_MM + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2590 = ROTRV_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2589 = ROTRV_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2588 = ROTRV + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2587 = ROTR + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2586 = RINT_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2585 = RINT_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2584 = RINT_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2583 = RINT_D + { 2, &MipsDescs.OperandInfo[1202] }, // Inst #2582 = RESTORE_NM + { 2, &MipsDescs.OperandInfo[1202] }, // Inst #2581 = RESTOREJRC_NM + { 2, &MipsDescs.OperandInfo[1202] }, // Inst #2580 = RESTOREJRC16_NM + { 2, &MipsDescs.OperandInfo[1200] }, // Inst #2579 = REPL_QB_MM + { 2, &MipsDescs.OperandInfo[1200] }, // Inst #2578 = REPL_QB + { 2, &MipsDescs.OperandInfo[1200] }, // Inst #2577 = REPL_PH_MM + { 2, &MipsDescs.OperandInfo[1200] }, // Inst #2576 = REPL_PH + { 2, &MipsDescs.OperandInfo[1198] }, // Inst #2575 = REPLV_QB_MM + { 2, &MipsDescs.OperandInfo[1198] }, // Inst #2574 = REPLV_QB + { 2, &MipsDescs.OperandInfo[1198] }, // Inst #2573 = REPLV_PH_MM + { 2, &MipsDescs.OperandInfo[1198] }, // Inst #2572 = REPLV_PH + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2571 = RECIP_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2570 = RECIP_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2569 = RECIP_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2568 = RECIP_D64 + { 2, &MipsDescs.OperandInfo[829] }, // Inst #2567 = RECIP_D32_MM + { 2, &MipsDescs.OperandInfo[829] }, // Inst #2566 = RECIP_D32 + { 2, &MipsDescs.OperandInfo[416] }, // Inst #2565 = RDPGPR_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2564 = RDPGPR_MMR6 + { 3, &MipsDescs.OperandInfo[386] }, // Inst #2563 = RDHWR_NM + { 3, &MipsDescs.OperandInfo[1192] }, // Inst #2562 = RDHWR_MMR6 + { 3, &MipsDescs.OperandInfo[1192] }, // Inst #2561 = RDHWR_MM + { 3, &MipsDescs.OperandInfo[1195] }, // Inst #2560 = RDHWR64 + { 3, &MipsDescs.OperandInfo[1192] }, // Inst #2559 = RDHWR + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2558 = RDDSP_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2557 = RDDSP + { 2, &MipsDescs.OperandInfo[1180] }, // Inst #2556 = RADDU_W_QB_MM + { 2, &MipsDescs.OperandInfo[1180] }, // Inst #2555 = RADDU_W_QB + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2554 = PUU_PS64 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2553 = PUL_PS64 + { 4, &MipsDescs.OperandInfo[614] }, // Inst #2552 = PREPEND_MMR2 + { 4, &MipsDescs.OperandInfo[614] }, // Inst #2551 = PREPEND + { 3, &MipsDescs.OperandInfo[354] }, // Inst #2550 = PREFs9_NM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #2549 = PREF_R6 + { 3, &MipsDescs.OperandInfo[354] }, // Inst #2548 = PREF_NM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #2547 = PREF_MMR6 + { 3, &MipsDescs.OperandInfo[688] }, // Inst #2546 = PREF_MM + { 3, &MipsDescs.OperandInfo[1189] }, // Inst #2545 = PREFX_MM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #2544 = PREFE_MM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #2543 = PREFE + { 3, &MipsDescs.OperandInfo[688] }, // Inst #2542 = PREF + { 4, &MipsDescs.OperandInfo[1185] }, // Inst #2541 = PRECR_SRA_R_PH_W_MMR2 + { 4, &MipsDescs.OperandInfo[1185] }, // Inst #2540 = PRECR_SRA_R_PH_W + { 4, &MipsDescs.OperandInfo[1185] }, // Inst #2539 = PRECR_SRA_PH_W_MMR2 + { 4, &MipsDescs.OperandInfo[1185] }, // Inst #2538 = PRECR_SRA_PH_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2537 = PRECR_QB_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2536 = PRECR_QB_PH + { 3, &MipsDescs.OperandInfo[1182] }, // Inst #2535 = PRECRQ_RS_PH_W_MM + { 3, &MipsDescs.OperandInfo[1182] }, // Inst #2534 = PRECRQ_RS_PH_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2533 = PRECRQ_QB_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2532 = PRECRQ_QB_PH + { 3, &MipsDescs.OperandInfo[1182] }, // Inst #2531 = PRECRQ_PH_W_MM + { 3, &MipsDescs.OperandInfo[1182] }, // Inst #2530 = PRECRQ_PH_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2529 = PRECRQU_S_QB_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2528 = PRECRQU_S_QB_PH + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2527 = PRECEU_PH_QBR_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2526 = PRECEU_PH_QBRA_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2525 = PRECEU_PH_QBRA + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2524 = PRECEU_PH_QBR + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2523 = PRECEU_PH_QBL_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2522 = PRECEU_PH_QBLA_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2521 = PRECEU_PH_QBLA + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2520 = PRECEU_PH_QBL + { 2, &MipsDescs.OperandInfo[1180] }, // Inst #2519 = PRECEQ_W_PHR_MM + { 2, &MipsDescs.OperandInfo[1180] }, // Inst #2518 = PRECEQ_W_PHR + { 2, &MipsDescs.OperandInfo[1180] }, // Inst #2517 = PRECEQ_W_PHL_MM + { 2, &MipsDescs.OperandInfo[1180] }, // Inst #2516 = PRECEQ_W_PHL + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2515 = PRECEQU_PH_QBR_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2514 = PRECEQU_PH_QBRA_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2513 = PRECEQU_PH_QBRA + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2512 = PRECEQU_PH_QBR + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2511 = PRECEQU_PH_QBL_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2510 = PRECEQU_PH_QBLA_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2509 = PRECEQU_PH_QBLA + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2508 = PRECEQU_PH_QBL + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2507 = POP + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2506 = PLU_PS64 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2505 = PLL_PS64 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2504 = PICK_QB_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2503 = PICK_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2502 = PICK_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2501 = PICK_PH + { 2, &MipsDescs.OperandInfo[244] }, // Inst #2500 = PCNT_W + { 2, &MipsDescs.OperandInfo[1174] }, // Inst #2499 = PCNT_H + { 2, &MipsDescs.OperandInfo[242] }, // Inst #2498 = PCNT_D + { 2, &MipsDescs.OperandInfo[1087] }, // Inst #2497 = PCNT_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2496 = PCKOD_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2495 = PCKOD_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2494 = PCKOD_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2493 = PCKOD_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2492 = PCKEV_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2491 = PCKEV_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2490 = PCKEV_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2489 = PCKEV_B + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2488 = PAUSE_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2487 = PAUSE_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2486 = PAUSE_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2485 = PAUSE + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2484 = PACKRL_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2483 = PACKRL_PH + { 3, &MipsDescs.OperandInfo[626] }, // Inst #2482 = OrRxRxRy16 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2481 = ORi_MM + { 3, &MipsDescs.OperandInfo[224] }, // Inst #2480 = ORi64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2479 = ORi + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2478 = OR_V + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2477 = OR_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2476 = OR_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2475 = OR_MM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2474 = ORI_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2473 = ORI_MMR6 + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2472 = ORI_B + { 3, &MipsDescs.OperandInfo[227] }, // Inst #2471 = OR64 + { 3, &MipsDescs.OperandInfo[599] }, // Inst #2470 = OR16_NM + { 3, &MipsDescs.OperandInfo[611] }, // Inst #2469 = OR16_MMR6 + { 3, &MipsDescs.OperandInfo[611] }, // Inst #2468 = OR16_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2467 = OR + { 2, &MipsDescs.OperandInfo[419] }, // Inst #2466 = NotRxRy16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #2465 = NegRxRy16 + { 2, &MipsDescs.OperandInfo[1178] }, // Inst #2464 = NOT16_NM + { 2, &MipsDescs.OperandInfo[1176] }, // Inst #2463 = NOT16_MMR6 + { 2, &MipsDescs.OperandInfo[1176] }, // Inst #2462 = NOT16_MM + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2461 = NOR_V + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2460 = NOR_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2459 = NOR_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2458 = NOR_MM + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2457 = NORI_B + { 3, &MipsDescs.OperandInfo[227] }, // Inst #2456 = NOR64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2455 = NOR + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2454 = NOP_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2453 = NOP32_NM + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2452 = NMSUB_S_MM + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2451 = NMSUB_S + { 4, &MipsDescs.OperandInfo[1045] }, // Inst #2450 = NMSUB_D64 + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2449 = NMSUB_D32_MM + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2448 = NMSUB_D32 + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2447 = NMADD_S_MM + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2446 = NMADD_S + { 4, &MipsDescs.OperandInfo[1045] }, // Inst #2445 = NMADD_D64 + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2444 = NMADD_D32_MM + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2443 = NMADD_D32 + { 2, &MipsDescs.OperandInfo[244] }, // Inst #2442 = NLZC_W + { 2, &MipsDescs.OperandInfo[1174] }, // Inst #2441 = NLZC_H + { 2, &MipsDescs.OperandInfo[242] }, // Inst #2440 = NLZC_D + { 2, &MipsDescs.OperandInfo[1087] }, // Inst #2439 = NLZC_B + { 2, &MipsDescs.OperandInfo[244] }, // Inst #2438 = NLOC_W + { 2, &MipsDescs.OperandInfo[1174] }, // Inst #2437 = NLOC_H + { 2, &MipsDescs.OperandInfo[242] }, // Inst #2436 = NLOC_D + { 2, &MipsDescs.OperandInfo[1087] }, // Inst #2435 = NLOC_B + { 2, &MipsDescs.OperandInfo[1172] }, // Inst #2434 = MoveR3216 + { 2, &MipsDescs.OperandInfo[1170] }, // Inst #2433 = Move32R16 + { 1, &MipsDescs.OperandInfo[915] }, // Inst #2432 = Mflo16 + { 1, &MipsDescs.OperandInfo[915] }, // Inst #2431 = Mfhi16 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2430 = MUL_S_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2429 = MUL_S_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2428 = MUL_R6 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2427 = MUL_Q_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2426 = MUL_Q_H + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2425 = MUL_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2424 = MUL_PH + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2423 = MUL_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2422 = MUL_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2421 = MUL_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2420 = MULV_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2419 = MULV_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2418 = MULV_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2417 = MULV_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2416 = MULU_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2415 = MULU_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2414 = MULU + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2413 = MULTu_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2412 = MULTu + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2411 = MULT_MM + { 3, &MipsDescs.OperandInfo[463] }, // Inst #2410 = MULT_DSP_MM + { 3, &MipsDescs.OperandInfo[463] }, // Inst #2409 = MULT_DSP + { 3, &MipsDescs.OperandInfo[463] }, // Inst #2408 = MULTU_DSP_MM + { 3, &MipsDescs.OperandInfo[463] }, // Inst #2407 = MULTU_DSP + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2406 = MULT + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2405 = MULSA_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2404 = MULSA_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2403 = MULSAQ_S_W_PH_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2402 = MULSAQ_S_W_PH + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2401 = MULR_Q_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2400 = MULR_Q_H + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2399 = MULR_PS64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2398 = MULQ_S_W_MMR2 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2397 = MULQ_S_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2396 = MULQ_S_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2395 = MULQ_S_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2394 = MULQ_RS_W_MMR2 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2393 = MULQ_RS_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2392 = MULQ_RS_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2391 = MULQ_RS_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2390 = MULEU_S_PH_QBR_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2389 = MULEU_S_PH_QBR + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2388 = MULEU_S_PH_QBL_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2387 = MULEU_S_PH_QBL + { 3, &MipsDescs.OperandInfo[719] }, // Inst #2386 = MULEQ_S_W_PHR_MM + { 3, &MipsDescs.OperandInfo[719] }, // Inst #2385 = MULEQ_S_W_PHR + { 3, &MipsDescs.OperandInfo[719] }, // Inst #2384 = MULEQ_S_W_PHL_MM + { 3, &MipsDescs.OperandInfo[719] }, // Inst #2383 = MULEQ_S_W_PHL + { 3, &MipsDescs.OperandInfo[602] }, // Inst #2382 = MUL4x4_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2381 = MUL + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2380 = MUH_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2379 = MUH_MMR6 + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2378 = MUHU_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2377 = MUHU_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2376 = MUHU + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2375 = MUH + { 5, &MipsDescs.OperandInfo[1165] }, // Inst #2374 = MTTR_NM + { 5, &MipsDescs.OperandInfo[1062] }, // Inst #2373 = MTTR + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2372 = MTP2 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2371 = MTP1 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2370 = MTP0 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2369 = MTM2 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2368 = MTM1 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2367 = MTM0 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2366 = MTLO_MM + { 2, &MipsDescs.OperandInfo[1163] }, // Inst #2365 = MTLO_DSP_MM + { 2, &MipsDescs.OperandInfo[1163] }, // Inst #2364 = MTLO_DSP + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2363 = MTLO64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2362 = MTLO + { 3, &MipsDescs.OperandInfo[1160] }, // Inst #2361 = MTHLIP_MM + { 3, &MipsDescs.OperandInfo[1160] }, // Inst #2360 = MTHLIP + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2359 = MTHI_MM + { 2, &MipsDescs.OperandInfo[1158] }, // Inst #2358 = MTHI_DSP_MM + { 2, &MipsDescs.OperandInfo[1158] }, // Inst #2357 = MTHI_DSP + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2356 = MTHI64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2355 = MTHI + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2354 = MTHGC0_MM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2353 = MTHGC0 + { 2, &MipsDescs.OperandInfo[745] }, // Inst #2352 = MTHC2_MMR6 + { 3, &MipsDescs.OperandInfo[1155] }, // Inst #2351 = MTHC1_D64_MM + { 3, &MipsDescs.OperandInfo[1155] }, // Inst #2350 = MTHC1_D64 + { 3, &MipsDescs.OperandInfo[1152] }, // Inst #2349 = MTHC1_D32_MM + { 3, &MipsDescs.OperandInfo[1152] }, // Inst #2348 = MTHC1_D32 + { 3, &MipsDescs.OperandInfo[386] }, // Inst #2347 = MTHC0_NM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2346 = MTHC0_MMR6 + { 2, &MipsDescs.OperandInfo[1053] }, // Inst #2345 = MTHC0Sel_NM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2344 = MTGC0_MM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2343 = MTGC0 + { 2, &MipsDescs.OperandInfo[745] }, // Inst #2342 = MTC2_MMR6 + { 3, &MipsDescs.OperandInfo[1149] }, // Inst #2341 = MTC2 + { 2, &MipsDescs.OperandInfo[414] }, // Inst #2340 = MTC1_MMR6 + { 2, &MipsDescs.OperandInfo[414] }, // Inst #2339 = MTC1_MM + { 2, &MipsDescs.OperandInfo[431] }, // Inst #2338 = MTC1_D64_MM + { 2, &MipsDescs.OperandInfo[431] }, // Inst #2337 = MTC1_D64 + { 2, &MipsDescs.OperandInfo[414] }, // Inst #2336 = MTC1 + { 3, &MipsDescs.OperandInfo[386] }, // Inst #2335 = MTC0_NM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2334 = MTC0_MMR6 + { 2, &MipsDescs.OperandInfo[1053] }, // Inst #2333 = MTC0Sel_NM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2332 = MTC0 + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2331 = MSUB_S_MM + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2330 = MSUB_S + { 4, &MipsDescs.OperandInfo[194] }, // Inst #2329 = MSUB_Q_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #2328 = MSUB_Q_H + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2327 = MSUB_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2326 = MSUB_DSP_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2325 = MSUB_DSP + { 4, &MipsDescs.OperandInfo[1045] }, // Inst #2324 = MSUB_D64 + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2323 = MSUB_D32_MM + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2322 = MSUB_D32 + { 4, &MipsDescs.OperandInfo[194] }, // Inst #2321 = MSUBV_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #2320 = MSUBV_H + { 4, &MipsDescs.OperandInfo[190] }, // Inst #2319 = MSUBV_D + { 4, &MipsDescs.OperandInfo[672] }, // Inst #2318 = MSUBV_B + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2317 = MSUBU_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2316 = MSUBU_DSP_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2315 = MSUBU_DSP + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2314 = MSUBU + { 4, &MipsDescs.OperandInfo[194] }, // Inst #2313 = MSUBR_Q_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #2312 = MSUBR_Q_H + { 4, &MipsDescs.OperandInfo[1037] }, // Inst #2311 = MSUBF_S_MMR6 + { 4, &MipsDescs.OperandInfo[1037] }, // Inst #2310 = MSUBF_S + { 4, &MipsDescs.OperandInfo[1033] }, // Inst #2309 = MSUBF_D_MMR6 + { 4, &MipsDescs.OperandInfo[1033] }, // Inst #2308 = MSUBF_D + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2307 = MSUB + { 4, &MipsDescs.OperandInfo[1145] }, // Inst #2306 = MOVZ_NM + { 4, &MipsDescs.OperandInfo[1141] }, // Inst #2305 = MOVZ_I_S_MM + { 4, &MipsDescs.OperandInfo[1141] }, // Inst #2304 = MOVZ_I_S + { 4, &MipsDescs.OperandInfo[1133] }, // Inst #2303 = MOVZ_I_MM + { 4, &MipsDescs.OperandInfo[1137] }, // Inst #2302 = MOVZ_I_I64 + { 4, &MipsDescs.OperandInfo[1133] }, // Inst #2301 = MOVZ_I_I + { 4, &MipsDescs.OperandInfo[1129] }, // Inst #2300 = MOVZ_I_D64 + { 4, &MipsDescs.OperandInfo[1125] }, // Inst #2299 = MOVZ_I_D32_MM + { 4, &MipsDescs.OperandInfo[1125] }, // Inst #2298 = MOVZ_I_D32 + { 4, &MipsDescs.OperandInfo[1121] }, // Inst #2297 = MOVZ_I64_S + { 4, &MipsDescs.OperandInfo[1117] }, // Inst #2296 = MOVZ_I64_I64 + { 4, &MipsDescs.OperandInfo[1113] }, // Inst #2295 = MOVZ_I64_I + { 4, &MipsDescs.OperandInfo[1109] }, // Inst #2294 = MOVZ_I64_D64 + { 4, &MipsDescs.OperandInfo[1105] }, // Inst #2293 = MOVT_S_MM + { 4, &MipsDescs.OperandInfo[1105] }, // Inst #2292 = MOVT_S + { 4, &MipsDescs.OperandInfo[1097] }, // Inst #2291 = MOVT_I_MM + { 4, &MipsDescs.OperandInfo[1101] }, // Inst #2290 = MOVT_I64 + { 4, &MipsDescs.OperandInfo[1097] }, // Inst #2289 = MOVT_I + { 4, &MipsDescs.OperandInfo[1093] }, // Inst #2288 = MOVT_D64 + { 4, &MipsDescs.OperandInfo[1089] }, // Inst #2287 = MOVT_D32_MM + { 4, &MipsDescs.OperandInfo[1089] }, // Inst #2286 = MOVT_D32 + { 4, &MipsDescs.OperandInfo[1145] }, // Inst #2285 = MOVN_NM + { 4, &MipsDescs.OperandInfo[1141] }, // Inst #2284 = MOVN_I_S_MM + { 4, &MipsDescs.OperandInfo[1141] }, // Inst #2283 = MOVN_I_S + { 4, &MipsDescs.OperandInfo[1133] }, // Inst #2282 = MOVN_I_MM + { 4, &MipsDescs.OperandInfo[1137] }, // Inst #2281 = MOVN_I_I64 + { 4, &MipsDescs.OperandInfo[1133] }, // Inst #2280 = MOVN_I_I + { 4, &MipsDescs.OperandInfo[1129] }, // Inst #2279 = MOVN_I_D64 + { 4, &MipsDescs.OperandInfo[1125] }, // Inst #2278 = MOVN_I_D32_MM + { 4, &MipsDescs.OperandInfo[1125] }, // Inst #2277 = MOVN_I_D32 + { 4, &MipsDescs.OperandInfo[1121] }, // Inst #2276 = MOVN_I64_S + { 4, &MipsDescs.OperandInfo[1117] }, // Inst #2275 = MOVN_I64_I64 + { 4, &MipsDescs.OperandInfo[1113] }, // Inst #2274 = MOVN_I64_I + { 4, &MipsDescs.OperandInfo[1109] }, // Inst #2273 = MOVN_I64_D64 + { 4, &MipsDescs.OperandInfo[1105] }, // Inst #2272 = MOVF_S_MM + { 4, &MipsDescs.OperandInfo[1105] }, // Inst #2271 = MOVF_S + { 4, &MipsDescs.OperandInfo[1097] }, // Inst #2270 = MOVF_I_MM + { 4, &MipsDescs.OperandInfo[1101] }, // Inst #2269 = MOVF_I64 + { 4, &MipsDescs.OperandInfo[1097] }, // Inst #2268 = MOVF_I + { 4, &MipsDescs.OperandInfo[1093] }, // Inst #2267 = MOVF_D64 + { 4, &MipsDescs.OperandInfo[1089] }, // Inst #2266 = MOVF_D32_MM + { 4, &MipsDescs.OperandInfo[1089] }, // Inst #2265 = MOVF_D32 + { 2, &MipsDescs.OperandInfo[1087] }, // Inst #2264 = MOVE_V + { 2, &MipsDescs.OperandInfo[629] }, // Inst #2263 = MOVE_NM + { 4, &MipsDescs.OperandInfo[1083] }, // Inst #2262 = MOVEP_NM + { 4, &MipsDescs.OperandInfo[1079] }, // Inst #2261 = MOVEP_MMR6 + { 4, &MipsDescs.OperandInfo[1079] }, // Inst #2260 = MOVEP_MM + { 4, &MipsDescs.OperandInfo[1075] }, // Inst #2259 = MOVEPREV_NM + { 3, &MipsDescs.OperandInfo[1072] }, // Inst #2258 = MOVEBALC_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2257 = MOVE16_MMR6 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2256 = MOVE16_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2255 = MOD_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2254 = MOD_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2253 = MOD_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2252 = MOD_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2251 = MOD_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2250 = MOD_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2249 = MOD_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2248 = MOD_S_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2247 = MOD_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2246 = MOD_MMR6 + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2245 = MODU_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2244 = MODU_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2243 = MODU + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2242 = MODSUB_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2241 = MODSUB + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2240 = MOD + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2239 = MIN_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2238 = MIN_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2237 = MIN_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2236 = MIN_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2235 = MIN_S_W + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2234 = MIN_S_MMR6 + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2233 = MIN_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2232 = MIN_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2231 = MIN_S_B + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2230 = MIN_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2229 = MIN_D_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2228 = MIN_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2227 = MIN_A_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2226 = MIN_A_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2225 = MIN_A_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2224 = MIN_A_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2223 = MINI_U_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2222 = MINI_U_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2221 = MINI_U_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2220 = MINI_U_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2219 = MINI_S_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2218 = MINI_S_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2217 = MINI_S_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2216 = MINI_S_B + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2215 = MINA_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2214 = MINA_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2213 = MINA_D_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2212 = MINA_D + { 5, &MipsDescs.OperandInfo[1067] }, // Inst #2211 = MFTR_NM + { 5, &MipsDescs.OperandInfo[1062] }, // Inst #2210 = MFTR + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2209 = MFLO_MM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #2208 = MFLO_DSP_MM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #2207 = MFLO_DSP + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2206 = MFLO64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2205 = MFLO16_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2204 = MFLO + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2203 = MFHI_MM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #2202 = MFHI_DSP_MM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #2201 = MFHI_DSP + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2200 = MFHI64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2199 = MFHI16_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2198 = MFHI + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2197 = MFHGC0_MM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2196 = MFHGC0 + { 2, &MipsDescs.OperandInfo[703] }, // Inst #2195 = MFHC2_MMR6 + { 2, &MipsDescs.OperandInfo[1055] }, // Inst #2194 = MFHC1_D64_MM + { 2, &MipsDescs.OperandInfo[1055] }, // Inst #2193 = MFHC1_D64 + { 2, &MipsDescs.OperandInfo[1060] }, // Inst #2192 = MFHC1_D32_MM + { 2, &MipsDescs.OperandInfo[1060] }, // Inst #2191 = MFHC1_D32 + { 3, &MipsDescs.OperandInfo[386] }, // Inst #2190 = MFHC0_NM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2189 = MFHC0_MMR6 + { 2, &MipsDescs.OperandInfo[1053] }, // Inst #2188 = MFHC0Sel_NM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2187 = MFGC0_MM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2186 = MFGC0 + { 2, &MipsDescs.OperandInfo[703] }, // Inst #2185 = MFC2_MMR6 + { 3, &MipsDescs.OperandInfo[1057] }, // Inst #2184 = MFC2 + { 2, &MipsDescs.OperandInfo[389] }, // Inst #2183 = MFC1_MMR6 + { 2, &MipsDescs.OperandInfo[389] }, // Inst #2182 = MFC1_MM + { 2, &MipsDescs.OperandInfo[1055] }, // Inst #2181 = MFC1_D64 + { 2, &MipsDescs.OperandInfo[389] }, // Inst #2180 = MFC1 + { 3, &MipsDescs.OperandInfo[386] }, // Inst #2179 = MFC0_NM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2178 = MFC0_MMR6 + { 2, &MipsDescs.OperandInfo[1053] }, // Inst #2177 = MFC0Sel_NM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2176 = MFC0 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2175 = MAX_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2174 = MAX_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2173 = MAX_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2172 = MAX_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2171 = MAX_S_W + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2170 = MAX_S_MMR6 + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2169 = MAX_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2168 = MAX_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2167 = MAX_S_B + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2166 = MAX_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2165 = MAX_D_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2164 = MAX_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2163 = MAX_A_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2162 = MAX_A_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2161 = MAX_A_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2160 = MAX_A_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2159 = MAXI_U_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2158 = MAXI_U_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2157 = MAXI_U_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2156 = MAXI_U_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2155 = MAXI_S_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2154 = MAXI_S_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2153 = MAXI_S_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2152 = MAXI_S_B + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2151 = MAXA_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2150 = MAXA_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2149 = MAXA_D_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2148 = MAXA_D + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2147 = MAQ_S_W_PHR_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2146 = MAQ_S_W_PHR + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2145 = MAQ_S_W_PHL_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2144 = MAQ_S_W_PHL + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2143 = MAQ_SA_W_PHR_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2142 = MAQ_SA_W_PHR + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2141 = MAQ_SA_W_PHL_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2140 = MAQ_SA_W_PHL + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2139 = MADD_S_MM + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2138 = MADD_S + { 4, &MipsDescs.OperandInfo[194] }, // Inst #2137 = MADD_Q_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #2136 = MADD_Q_H + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2135 = MADD_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2134 = MADD_DSP_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2133 = MADD_DSP + { 4, &MipsDescs.OperandInfo[1045] }, // Inst #2132 = MADD_D64 + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2131 = MADD_D32_MM + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2130 = MADD_D32 + { 4, &MipsDescs.OperandInfo[194] }, // Inst #2129 = MADDV_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #2128 = MADDV_H + { 4, &MipsDescs.OperandInfo[190] }, // Inst #2127 = MADDV_D + { 4, &MipsDescs.OperandInfo[672] }, // Inst #2126 = MADDV_B + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2125 = MADDU_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2124 = MADDU_DSP_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2123 = MADDU_DSP + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2122 = MADDU + { 4, &MipsDescs.OperandInfo[194] }, // Inst #2121 = MADDR_Q_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #2120 = MADDR_Q_H + { 4, &MipsDescs.OperandInfo[1037] }, // Inst #2119 = MADDF_S_MMR6 + { 4, &MipsDescs.OperandInfo[1037] }, // Inst #2118 = MADDF_S + { 4, &MipsDescs.OperandInfo[1033] }, // Inst #2117 = MADDF_D_MMR6 + { 4, &MipsDescs.OperandInfo[1033] }, // Inst #2116 = MADDF_D + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2115 = MADD + { 3, &MipsDescs.OperandInfo[623] }, // Inst #2114 = LwRxSpImmX16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #2113 = LwRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[1030] }, // Inst #2112 = LwRxPcTcpX16 + { 3, &MipsDescs.OperandInfo[1030] }, // Inst #2111 = LwRxPcTcp16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #2110 = LiRxImmX16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #2109 = LiRxImmAlignX16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #2108 = LiRxImm16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #2107 = LhuRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #2106 = LhRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #2105 = LbuRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #2104 = LbRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2103 = LWu + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2102 = LWs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2101 = LW_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2100 = LW_MMR6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2099 = LW_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2098 = LWX_NM + { 3, &MipsDescs.OperandInfo[925] }, // Inst #2097 = LWX_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2096 = LWXS_NM + { 3, &MipsDescs.OperandInfo[925] }, // Inst #2095 = LWXS_MM + { 3, &MipsDescs.OperandInfo[916] }, // Inst #2094 = LWXS16_NM + { 3, &MipsDescs.OperandInfo[1024] }, // Inst #2093 = LWXC1_MM + { 3, &MipsDescs.OperandInfo[1024] }, // Inst #2092 = LWXC1 + { 3, &MipsDescs.OperandInfo[925] }, // Inst #2091 = LWX + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2090 = LWU_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2089 = LWUPC + { 3, &MipsDescs.OperandInfo[1021] }, // Inst #2088 = LWSP_MM + { 3, &MipsDescs.OperandInfo[1018] }, // Inst #2087 = LWSP16_NM + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2086 = LWR_MM + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2085 = LWRE_MM + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2084 = LWRE + { 4, &MipsDescs.OperandInfo[951] }, // Inst #2083 = LWR64 + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2082 = LWR + { 4, &MipsDescs.OperandInfo[1014] }, // Inst #2081 = LWP_MM + { 2, &MipsDescs.OperandInfo[609] }, // Inst #2080 = LWPC_NM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2079 = LWPC_MMR6 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2078 = LWPC + { 4, &MipsDescs.OperandInfo[1010] }, // Inst #2077 = LWM_NM + { 3, &MipsDescs.OperandInfo[354] }, // Inst #2076 = LWM32_MM + { 3, &MipsDescs.OperandInfo[1007] }, // Inst #2075 = LWM16_MMR6 + { 3, &MipsDescs.OperandInfo[1007] }, // Inst #2074 = LWM16_MM + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2073 = LWL_MM + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2072 = LWLE_MM + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2071 = LWLE + { 4, &MipsDescs.OperandInfo[951] }, // Inst #2070 = LWL64 + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2069 = LWL + { 3, &MipsDescs.OperandInfo[1000] }, // Inst #2068 = LWGP_NM + { 3, &MipsDescs.OperandInfo[997] }, // Inst #2067 = LWGP_MM + { 3, &MipsDescs.OperandInfo[994] }, // Inst #2066 = LWGP16_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2065 = LWE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2064 = LWE + { 3, &MipsDescs.OperandInfo[991] }, // Inst #2063 = LWDSP_MM + { 3, &MipsDescs.OperandInfo[991] }, // Inst #2062 = LWDSP + { 3, &MipsDescs.OperandInfo[940] }, // Inst #2061 = LWC3 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #2060 = LWC2_R6 + { 3, &MipsDescs.OperandInfo[937] }, // Inst #2059 = LWC2_MMR6 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #2058 = LWC2 + { 3, &MipsDescs.OperandInfo[988] }, // Inst #2057 = LWC1_MM + { 3, &MipsDescs.OperandInfo[988] }, // Inst #2056 = LWC1 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2055 = LW64 + { 3, &MipsDescs.OperandInfo[985] }, // Inst #2054 = LW4x4_NM + { 3, &MipsDescs.OperandInfo[916] }, // Inst #2053 = LW16_NM + { 3, &MipsDescs.OperandInfo[922] }, // Inst #2052 = LW16_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2051 = LW + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2050 = LUi_MM + { 2, &MipsDescs.OperandInfo[359] }, // Inst #2049 = LUi64 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2048 = LUi + { 3, &MipsDescs.OperandInfo[958] }, // Inst #2047 = LUXC1_MM + { 3, &MipsDescs.OperandInfo[958] }, // Inst #2046 = LUXC164 + { 3, &MipsDescs.OperandInfo[955] }, // Inst #2045 = LUXC1 + { 2, &MipsDescs.OperandInfo[450] }, // Inst #2044 = LUI_NM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2043 = LUI_MMR6 + { 4, &MipsDescs.OperandInfo[605] }, // Inst #2042 = LSA_R6 + { 4, &MipsDescs.OperandInfo[142] }, // Inst #2041 = LSA_NM + { 4, &MipsDescs.OperandInfo[605] }, // Inst #2040 = LSA_MMR6 + { 4, &MipsDescs.OperandInfo[605] }, // Inst #2039 = LSA + { 3, &MipsDescs.OperandInfo[975] }, // Inst #2038 = LL_R6 + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2037 = LL_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2036 = LL_MMR6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2035 = LL_MM + { 4, &MipsDescs.OperandInfo[981] }, // Inst #2034 = LLWP_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2033 = LLE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2032 = LLE + { 3, &MipsDescs.OperandInfo[978] }, // Inst #2031 = LLD_R6 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2030 = LLD + { 3, &MipsDescs.OperandInfo[975] }, // Inst #2029 = LL64_R6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2028 = LL64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2027 = LL + { 2, &MipsDescs.OperandInfo[450] }, // Inst #2026 = LI48_NM + { 2, &MipsDescs.OperandInfo[973] }, // Inst #2025 = LI16_NM + { 2, &MipsDescs.OperandInfo[558] }, // Inst #2024 = LI16_MMR6 + { 2, &MipsDescs.OperandInfo[558] }, // Inst #2023 = LI16_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2022 = LHu_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2021 = LHuE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2020 = LHuE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2019 = LHu64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2018 = LHu + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2017 = LHs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2016 = LH_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2015 = LH_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2014 = LHX_NM + { 3, &MipsDescs.OperandInfo[925] }, // Inst #2013 = LHX_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2012 = LHXS_NM + { 3, &MipsDescs.OperandInfo[925] }, // Inst #2011 = LHX + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2010 = LHUs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2009 = LHU_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2008 = LHUX_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2007 = LHUXS_NM + { 3, &MipsDescs.OperandInfo[919] }, // Inst #2006 = LHUGP_NM + { 3, &MipsDescs.OperandInfo[916] }, // Inst #2005 = LHU16_NM + { 3, &MipsDescs.OperandInfo[922] }, // Inst #2004 = LHU16_MM + { 3, &MipsDescs.OperandInfo[919] }, // Inst #2003 = LHGP_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2002 = LHE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2001 = LHE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2000 = LH64 + { 3, &MipsDescs.OperandInfo[916] }, // Inst #1999 = LH16_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1998 = LH + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1997 = LEA_ADDiu_MM + { 3, &MipsDescs.OperandInfo[361] }, // Inst #1996 = LEA_ADDiu64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1995 = LEA_ADDiu + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1994 = LEA_ADDIU_NM + { 3, &MipsDescs.OperandInfo[970] }, // Inst #1993 = LD_W + { 3, &MipsDescs.OperandInfo[967] }, // Inst #1992 = LD_H + { 3, &MipsDescs.OperandInfo[964] }, // Inst #1991 = LD_D + { 3, &MipsDescs.OperandInfo[961] }, // Inst #1990 = LD_B + { 3, &MipsDescs.OperandInfo[958] }, // Inst #1989 = LDXC164 + { 3, &MipsDescs.OperandInfo[955] }, // Inst #1988 = LDXC1 + { 4, &MipsDescs.OperandInfo[951] }, // Inst #1987 = LDR + { 2, &MipsDescs.OperandInfo[359] }, // Inst #1986 = LDPC + { 4, &MipsDescs.OperandInfo[951] }, // Inst #1985 = LDL + { 2, &MipsDescs.OperandInfo[949] }, // Inst #1984 = LDI_W + { 2, &MipsDescs.OperandInfo[947] }, // Inst #1983 = LDI_H + { 2, &MipsDescs.OperandInfo[945] }, // Inst #1982 = LDI_D + { 2, &MipsDescs.OperandInfo[943] }, // Inst #1981 = LDI_B + { 3, &MipsDescs.OperandInfo[940] }, // Inst #1980 = LDC3 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #1979 = LDC2_R6 + { 3, &MipsDescs.OperandInfo[937] }, // Inst #1978 = LDC2_MMR6 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #1977 = LDC2 + { 3, &MipsDescs.OperandInfo[931] }, // Inst #1976 = LDC1_MM_D64 + { 3, &MipsDescs.OperandInfo[519] }, // Inst #1975 = LDC1_MM_D32 + { 3, &MipsDescs.OperandInfo[931] }, // Inst #1974 = LDC1_D64_MMR6 + { 3, &MipsDescs.OperandInfo[931] }, // Inst #1973 = LDC164 + { 3, &MipsDescs.OperandInfo[519] }, // Inst #1972 = LDC1 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #1971 = LD + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1970 = LBu_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1969 = LBuE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1968 = LBuE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #1967 = LBu64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1966 = LBu + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1965 = LBs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1964 = LB_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1963 = LB_MMR6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1962 = LB_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1961 = LBX_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1960 = LBUs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1959 = LBU_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1958 = LBU_MMR6 + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1957 = LBUX_NM + { 3, &MipsDescs.OperandInfo[925] }, // Inst #1956 = LBUX_MM + { 3, &MipsDescs.OperandInfo[925] }, // Inst #1955 = LBUX + { 3, &MipsDescs.OperandInfo[919] }, // Inst #1954 = LBUGP_NM + { 3, &MipsDescs.OperandInfo[916] }, // Inst #1953 = LBU16_NM + { 3, &MipsDescs.OperandInfo[922] }, // Inst #1952 = LBU16_MM + { 3, &MipsDescs.OperandInfo[919] }, // Inst #1951 = LBGP_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1950 = LBE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1949 = LBE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #1948 = LB64 + { 3, &MipsDescs.OperandInfo[916] }, // Inst #1947 = LB16_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1946 = LB + { 2, &MipsDescs.OperandInfo[609] }, // Inst #1945 = LAPC48_NM + { 2, &MipsDescs.OperandInfo[609] }, // Inst #1944 = LAPC32_NM + { 1, &MipsDescs.OperandInfo[915] }, // Inst #1943 = JumpLinkReg16 + { 1, &MipsDescs.OperandInfo[915] }, // Inst #1942 = JrcRx16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1941 = JrcRa16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1940 = JrRa16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1939 = JalB16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1938 = Jal16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1937 = J_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1936 = JR_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1935 = JR_HB_R6 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #1934 = JR_HB64_R6 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #1933 = JR_HB64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1932 = JR_HB + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1931 = JRC_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1930 = JRCADDIUSP_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1929 = JRC16_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1928 = JRC16_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1927 = JRADDIUSP + { 1, &MipsDescs.OperandInfo[310] }, // Inst #1926 = JR64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1925 = JR16_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1924 = JR + { 2, &MipsDescs.OperandInfo[364] }, // Inst #1923 = JIC_MMR6 + { 2, &MipsDescs.OperandInfo[359] }, // Inst #1922 = JIC64 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #1921 = JIC + { 2, &MipsDescs.OperandInfo[364] }, // Inst #1920 = JIALC_MMR6 + { 2, &MipsDescs.OperandInfo[359] }, // Inst #1919 = JIALC64 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #1918 = JIALC + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1917 = JAL_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1916 = JALX_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1915 = JALX + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1914 = JALS_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1913 = JALR_MM + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1912 = JALR_HB64 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1911 = JALR_HB + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1910 = JALRS_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1909 = JALRS16_MM + { 2, &MipsDescs.OperandInfo[416] }, // Inst #1908 = JALRC_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1907 = JALRC_MMR6 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1906 = JALRC_HB_MMR6 + { 2, &MipsDescs.OperandInfo[416] }, // Inst #1905 = JALRCHB_NM + { 2, &MipsDescs.OperandInfo[913] }, // Inst #1904 = JALRC16_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1903 = JALRC16_MMR6 + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1902 = JALR64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1901 = JALR16_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1900 = JALR + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1899 = JAL + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1898 = J + { 5, &MipsDescs.OperandInfo[908] }, // Inst #1897 = INS_NM + { 5, &MipsDescs.OperandInfo[864] }, // Inst #1896 = INS_MMR6 + { 5, &MipsDescs.OperandInfo[864] }, // Inst #1895 = INS_MM + { 3, &MipsDescs.OperandInfo[885] }, // Inst #1894 = INSV_MM + { 5, &MipsDescs.OperandInfo[903] }, // Inst #1893 = INSVE_W + { 5, &MipsDescs.OperandInfo[898] }, // Inst #1892 = INSVE_H + { 5, &MipsDescs.OperandInfo[893] }, // Inst #1891 = INSVE_D + { 5, &MipsDescs.OperandInfo[888] }, // Inst #1890 = INSVE_B + { 3, &MipsDescs.OperandInfo[885] }, // Inst #1889 = INSV + { 4, &MipsDescs.OperandInfo[881] }, // Inst #1888 = INSERT_W + { 4, &MipsDescs.OperandInfo[877] }, // Inst #1887 = INSERT_H + { 4, &MipsDescs.OperandInfo[873] }, // Inst #1886 = INSERT_D + { 4, &MipsDescs.OperandInfo[869] }, // Inst #1885 = INSERT_B + { 5, &MipsDescs.OperandInfo[864] }, // Inst #1884 = INS + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1883 = ILVR_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1882 = ILVR_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1881 = ILVR_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1880 = ILVR_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1879 = ILVOD_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1878 = ILVOD_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1877 = ILVOD_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1876 = ILVOD_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1875 = ILVL_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1874 = ILVL_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1873 = ILVL_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1872 = ILVL_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1871 = ILVEV_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1870 = ILVEV_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1869 = ILVEV_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1868 = ILVEV_B + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1867 = HYPCALL_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1866 = HYPCALL + { 3, &MipsDescs.OperandInfo[795] }, // Inst #1865 = HSUB_U_W + { 3, &MipsDescs.OperandInfo[792] }, // Inst #1864 = HSUB_U_H + { 3, &MipsDescs.OperandInfo[789] }, // Inst #1863 = HSUB_U_D + { 3, &MipsDescs.OperandInfo[795] }, // Inst #1862 = HSUB_S_W + { 3, &MipsDescs.OperandInfo[792] }, // Inst #1861 = HSUB_S_H + { 3, &MipsDescs.OperandInfo[789] }, // Inst #1860 = HSUB_S_D + { 3, &MipsDescs.OperandInfo[795] }, // Inst #1859 = HADD_U_W + { 3, &MipsDescs.OperandInfo[792] }, // Inst #1858 = HADD_U_H + { 3, &MipsDescs.OperandInfo[789] }, // Inst #1857 = HADD_U_D + { 3, &MipsDescs.OperandInfo[795] }, // Inst #1856 = HADD_S_W + { 3, &MipsDescs.OperandInfo[792] }, // Inst #1855 = HADD_S_H + { 3, &MipsDescs.OperandInfo[789] }, // Inst #1854 = HADD_S_D + { 2, &MipsDescs.OperandInfo[450] }, // Inst #1853 = GINVT_NM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #1852 = GINVT_MMR6 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #1851 = GINVT + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1850 = GINVI_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1849 = GINVI_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1848 = GINVI + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1847 = FTRUNC_U_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1846 = FTRUNC_U_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1845 = FTRUNC_S_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1844 = FTRUNC_S_D + { 3, &MipsDescs.OperandInfo[849] }, // Inst #1843 = FTQ_W + { 3, &MipsDescs.OperandInfo[846] }, // Inst #1842 = FTQ_H + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1841 = FTINT_U_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1840 = FTINT_U_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1839 = FTINT_S_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1838 = FTINT_S_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1837 = FSUN_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1836 = FSUN_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1835 = FSUNE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1834 = FSUNE_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1833 = FSULT_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1832 = FSULT_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1831 = FSULE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1830 = FSULE_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1829 = FSUEQ_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1828 = FSUEQ_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1827 = FSUB_W + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1826 = FSUB_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1825 = FSUB_S_MM + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1824 = FSUB_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1823 = FSUB_PS64 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1822 = FSUB_D64_MM + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1821 = FSUB_D64 + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1820 = FSUB_D32_MM + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1819 = FSUB_D32 + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1818 = FSUB_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1817 = FSQRT_W + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1816 = FSQRT_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1815 = FSQRT_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1814 = FSQRT_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1813 = FSQRT_D64 + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1812 = FSQRT_D32_MM + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1811 = FSQRT_D32 + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1810 = FSQRT_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1809 = FSOR_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1808 = FSOR_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1807 = FSNE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1806 = FSNE_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1805 = FSLT_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1804 = FSLT_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1803 = FSLE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1802 = FSLE_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1801 = FSEQ_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1800 = FSEQ_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1799 = FSAF_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1798 = FSAF_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1797 = FRSQRT_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1796 = FRSQRT_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1795 = FRINT_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1794 = FRINT_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1793 = FRCP_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1792 = FRCP_D + { 3, &MipsDescs.OperandInfo[596] }, // Inst #1791 = FORK_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1790 = FORK + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1789 = FNEG_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1788 = FNEG_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1787 = FNEG_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1786 = FNEG_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1785 = FNEG_D64 + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1784 = FNEG_D32_MM + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1783 = FNEG_D32 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1782 = FMUL_W + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1781 = FMUL_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1780 = FMUL_S_MM + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1779 = FMUL_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1778 = FMUL_PS64 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1777 = FMUL_D64_MM + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1776 = FMUL_D64 + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1775 = FMUL_D32_MM + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1774 = FMUL_D32 + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1773 = FMUL_D + { 4, &MipsDescs.OperandInfo[194] }, // Inst #1772 = FMSUB_W + { 4, &MipsDescs.OperandInfo[190] }, // Inst #1771 = FMSUB_D + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1770 = FMOV_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1769 = FMOV_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1768 = FMOV_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1767 = FMOV_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1766 = FMOV_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1765 = FMOV_D64 + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1764 = FMOV_D32_MM + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1763 = FMOV_D32 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1762 = FMIN_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1761 = FMIN_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1760 = FMIN_A_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1759 = FMIN_A_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1758 = FMAX_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1757 = FMAX_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1756 = FMAX_A_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1755 = FMAX_A_D + { 4, &MipsDescs.OperandInfo[194] }, // Inst #1754 = FMADD_W + { 4, &MipsDescs.OperandInfo[190] }, // Inst #1753 = FMADD_D + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1752 = FLOOR_W_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1751 = FLOOR_W_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1750 = FLOOR_W_S + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1749 = FLOOR_W_MM + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1748 = FLOOR_W_D_MMR6 + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1747 = FLOOR_W_D64 + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1746 = FLOOR_W_D32 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1745 = FLOOR_L_S_MMR6 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1744 = FLOOR_L_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1743 = FLOOR_L_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1742 = FLOOR_L_D64 + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1741 = FLOG2_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1740 = FLOG2_D + { 2, &MipsDescs.OperandInfo[862] }, // Inst #1739 = FILL_W + { 2, &MipsDescs.OperandInfo[860] }, // Inst #1738 = FILL_H + { 2, &MipsDescs.OperandInfo[858] }, // Inst #1737 = FILL_D + { 2, &MipsDescs.OperandInfo[856] }, // Inst #1736 = FILL_B + { 2, &MipsDescs.OperandInfo[854] }, // Inst #1735 = FFQR_W + { 2, &MipsDescs.OperandInfo[852] }, // Inst #1734 = FFQR_D + { 2, &MipsDescs.OperandInfo[854] }, // Inst #1733 = FFQL_W + { 2, &MipsDescs.OperandInfo[852] }, // Inst #1732 = FFQL_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1731 = FFINT_U_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1730 = FFINT_U_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1729 = FFINT_S_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1728 = FFINT_S_D + { 2, &MipsDescs.OperandInfo[854] }, // Inst #1727 = FEXUPR_W + { 2, &MipsDescs.OperandInfo[852] }, // Inst #1726 = FEXUPR_D + { 2, &MipsDescs.OperandInfo[854] }, // Inst #1725 = FEXUPL_W + { 2, &MipsDescs.OperandInfo[852] }, // Inst #1724 = FEXUPL_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1723 = FEXP2_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1722 = FEXP2_D + { 3, &MipsDescs.OperandInfo[849] }, // Inst #1721 = FEXDO_W + { 3, &MipsDescs.OperandInfo[846] }, // Inst #1720 = FEXDO_H + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1719 = FDIV_W + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1718 = FDIV_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1717 = FDIV_S_MM + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1716 = FDIV_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1715 = FDIV_D64_MM + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1714 = FDIV_D64 + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1713 = FDIV_D32_MM + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1712 = FDIV_D32 + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1711 = FDIV_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1710 = FCUN_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1709 = FCUN_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1708 = FCUNE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1707 = FCUNE_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1706 = FCULT_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1705 = FCULT_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1704 = FCULE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1703 = FCULE_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1702 = FCUEQ_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1701 = FCUEQ_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1700 = FCOR_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1699 = FCOR_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1698 = FCNE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1697 = FCNE_D + { 3, &MipsDescs.OperandInfo[843] }, // Inst #1696 = FCMP_S32_MM + { 3, &MipsDescs.OperandInfo[843] }, // Inst #1695 = FCMP_S32 + { 3, &MipsDescs.OperandInfo[840] }, // Inst #1694 = FCMP_D64 + { 3, &MipsDescs.OperandInfo[837] }, // Inst #1693 = FCMP_D32_MM + { 3, &MipsDescs.OperandInfo[837] }, // Inst #1692 = FCMP_D32 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1691 = FCLT_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1690 = FCLT_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1689 = FCLE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1688 = FCLE_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1687 = FCLASS_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1686 = FCLASS_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1685 = FCEQ_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1684 = FCEQ_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1683 = FCAF_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1682 = FCAF_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1681 = FADD_W + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1680 = FADD_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1679 = FADD_S_MM + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1678 = FADD_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1677 = FADD_PS64 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1676 = FADD_D64_MM + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1675 = FADD_D64 + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1674 = FADD_D32_MM + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1673 = FADD_D32 + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1672 = FADD_D + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1671 = FABS_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1670 = FABS_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1669 = FABS_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1668 = FABS_D64 + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1667 = FABS_D32_MM + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1666 = FABS_D32 + { 4, &MipsDescs.OperandInfo[825] }, // Inst #1665 = EXT_NM + { 4, &MipsDescs.OperandInfo[715] }, // Inst #1664 = EXT_MMR6 + { 4, &MipsDescs.OperandInfo[715] }, // Inst #1663 = EXT_MM + { 4, &MipsDescs.OperandInfo[142] }, // Inst #1662 = EXTW_NM + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1661 = EXTS32 + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1660 = EXTS + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1659 = EXTR_W_MM + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1658 = EXTR_W + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1657 = EXTR_S_H_MM + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1656 = EXTR_S_H + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1655 = EXTR_R_W_MM + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1654 = EXTR_R_W + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1653 = EXTR_RS_W_MM + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1652 = EXTR_RS_W + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1651 = EXTRV_W_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1650 = EXTRV_W + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1649 = EXTRV_S_H_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1648 = EXTRV_S_H + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1647 = EXTRV_R_W_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1646 = EXTRV_R_W + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1645 = EXTRV_RS_W_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1644 = EXTRV_RS_W + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1643 = EXTP_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1642 = EXTPV_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1641 = EXTPV + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1640 = EXTPDP_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1639 = EXTPDPV_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1638 = EXTPDPV + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1637 = EXTPDP + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1636 = EXTP + { 4, &MipsDescs.OperandInfo[715] }, // Inst #1635 = EXT + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1634 = EVP_MMR6 + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1633 = EVPE_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1632 = EVPE + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1631 = EVP + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1630 = ERET_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1629 = ERET_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1628 = ERET_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1627 = ERETNC_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1626 = ERETNC_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1625 = ERETNC + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1624 = ERET + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1623 = EMT_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1622 = EMT + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1621 = EI_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1620 = EI_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1619 = EI_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1618 = EI + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1617 = EHB_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1616 = EHB_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1615 = EHB_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1614 = EHB + { 2, &MipsDescs.OperandInfo[419] }, // Inst #1613 = DivuRxRy16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #1612 = DivRxRy16 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1611 = DVP_MMR6 + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1610 = DVPE_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1609 = DVPE + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1608 = DVP + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1607 = DUDIV + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1606 = DSUBu + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1605 = DSUB + { 3, &MipsDescs.OperandInfo[814] }, // Inst #1604 = DSRLV + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1603 = DSRL32 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1602 = DSRL + { 3, &MipsDescs.OperandInfo[814] }, // Inst #1601 = DSRAV + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1600 = DSRA32 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1599 = DSRA + { 3, &MipsDescs.OperandInfo[814] }, // Inst #1598 = DSLLV + { 2, &MipsDescs.OperandInfo[817] }, // Inst #1597 = DSLL64_32 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1596 = DSLL32 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1595 = DSLL + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1594 = DSHD + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1593 = DSDIV + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1592 = DSBH + { 3, &MipsDescs.OperandInfo[814] }, // Inst #1591 = DROTRV + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1590 = DROTR32 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1589 = DROTR + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1588 = DPS_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1587 = DPS_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1586 = DPSX_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1585 = DPSX_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1584 = DPSU_H_QBR_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1583 = DPSU_H_QBR + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1582 = DPSU_H_QBL_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1581 = DPSU_H_QBL + { 4, &MipsDescs.OperandInfo[806] }, // Inst #1580 = DPSUB_U_W + { 4, &MipsDescs.OperandInfo[802] }, // Inst #1579 = DPSUB_U_H + { 4, &MipsDescs.OperandInfo[798] }, // Inst #1578 = DPSUB_U_D + { 4, &MipsDescs.OperandInfo[806] }, // Inst #1577 = DPSUB_S_W + { 4, &MipsDescs.OperandInfo[802] }, // Inst #1576 = DPSUB_S_H + { 4, &MipsDescs.OperandInfo[798] }, // Inst #1575 = DPSUB_S_D + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1574 = DPSQ_S_W_PH_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1573 = DPSQ_S_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1572 = DPSQ_SA_L_W_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1571 = DPSQ_SA_L_W + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1570 = DPSQX_S_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1569 = DPSQX_S_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1568 = DPSQX_SA_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1567 = DPSQX_SA_W_PH + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1566 = DPOP + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1565 = DPA_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1564 = DPA_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1563 = DPAX_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1562 = DPAX_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1561 = DPAU_H_QBR_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1560 = DPAU_H_QBR + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1559 = DPAU_H_QBL_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1558 = DPAU_H_QBL + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1557 = DPAQ_S_W_PH_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1556 = DPAQ_S_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1555 = DPAQ_SA_L_W_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1554 = DPAQ_SA_L_W + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1553 = DPAQX_S_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1552 = DPAQX_S_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1551 = DPAQX_SA_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1550 = DPAQX_SA_W_PH + { 4, &MipsDescs.OperandInfo[806] }, // Inst #1549 = DPADD_U_W + { 4, &MipsDescs.OperandInfo[802] }, // Inst #1548 = DPADD_U_H + { 4, &MipsDescs.OperandInfo[798] }, // Inst #1547 = DPADD_U_D + { 4, &MipsDescs.OperandInfo[806] }, // Inst #1546 = DPADD_S_W + { 4, &MipsDescs.OperandInfo[802] }, // Inst #1545 = DPADD_S_H + { 4, &MipsDescs.OperandInfo[798] }, // Inst #1544 = DPADD_S_D + { 3, &MipsDescs.OperandInfo[795] }, // Inst #1543 = DOTP_U_W + { 3, &MipsDescs.OperandInfo[792] }, // Inst #1542 = DOTP_U_H + { 3, &MipsDescs.OperandInfo[789] }, // Inst #1541 = DOTP_U_D + { 3, &MipsDescs.OperandInfo[795] }, // Inst #1540 = DOTP_S_W + { 3, &MipsDescs.OperandInfo[792] }, // Inst #1539 = DOTP_S_H + { 3, &MipsDescs.OperandInfo[789] }, // Inst #1538 = DOTP_S_D + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1537 = DMUL_R6 + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1536 = DMULU + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1535 = DMULTu + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1534 = DMULT + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1533 = DMUL + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1532 = DMUHU + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1531 = DMUH + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1530 = DMT_NM + { 3, &MipsDescs.OperandInfo[783] }, // Inst #1529 = DMTGC0 + { 2, &MipsDescs.OperandInfo[359] }, // Inst #1528 = DMTC2_OCTEON + { 3, &MipsDescs.OperandInfo[786] }, // Inst #1527 = DMTC2 + { 2, &MipsDescs.OperandInfo[429] }, // Inst #1526 = DMTC1 + { 3, &MipsDescs.OperandInfo[783] }, // Inst #1525 = DMTC0 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1524 = DMT + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1523 = DMODU + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1522 = DMOD + { 3, &MipsDescs.OperandInfo[775] }, // Inst #1521 = DMFGC0 + { 2, &MipsDescs.OperandInfo[359] }, // Inst #1520 = DMFC2_OCTEON + { 3, &MipsDescs.OperandInfo[780] }, // Inst #1519 = DMFC2 + { 2, &MipsDescs.OperandInfo[778] }, // Inst #1518 = DMFC1 + { 3, &MipsDescs.OperandInfo[775] }, // Inst #1517 = DMFC0 + { 4, &MipsDescs.OperandInfo[766] }, // Inst #1516 = DLSA_R6 + { 4, &MipsDescs.OperandInfo[766] }, // Inst #1515 = DLSA + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1514 = DI_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1513 = DI_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1512 = DI_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1511 = DIV_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1510 = DIV_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1509 = DIV_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1508 = DIV_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1507 = DIV_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1506 = DIV_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1505 = DIV_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1504 = DIV_S_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #1503 = DIV_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1502 = DIV_MMR6 + { 3, &MipsDescs.OperandInfo[596] }, // Inst #1501 = DIVU_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1500 = DIVU_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1499 = DIVU + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1498 = DIV + { 5, &MipsDescs.OperandInfo[770] }, // Inst #1497 = DINSU + { 5, &MipsDescs.OperandInfo[770] }, // Inst #1496 = DINSM + { 5, &MipsDescs.OperandInfo[770] }, // Inst #1495 = DINS + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1494 = DI + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1493 = DEXTU + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1492 = DEXTM + { 4, &MipsDescs.OperandInfo[711] }, // Inst #1491 = DEXT64_32 + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1490 = DEXT + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1489 = DERET_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1488 = DERET_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1487 = DERET_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1486 = DERET + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1485 = DDIVU + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1484 = DDIV + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1483 = DCLZ_R6 + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1482 = DCLZ + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1481 = DCLO_R6 + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1480 = DCLO + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1479 = DBITSWAP + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1478 = DAUI + { 3, &MipsDescs.OperandInfo[763] }, // Inst #1477 = DATI + { 4, &MipsDescs.OperandInfo[766] }, // Inst #1476 = DALIGN + { 3, &MipsDescs.OperandInfo[763] }, // Inst #1475 = DAHI + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1474 = DADDu + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1473 = DADDiu + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1472 = DADDi + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1471 = DADD + { 2, &MipsDescs.OperandInfo[618] }, // Inst #1470 = CmpiRxImmX16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #1469 = CmpiRxImm16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #1468 = CmpRxRy16 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1467 = C_UN_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1466 = C_UN_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1465 = C_UN_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1464 = C_UN_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1463 = C_UN_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1462 = C_UN_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1461 = C_ULT_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1460 = C_ULT_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1459 = C_ULT_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1458 = C_ULT_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1457 = C_ULT_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1456 = C_ULT_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1455 = C_ULE_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1454 = C_ULE_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1453 = C_ULE_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1452 = C_ULE_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1451 = C_ULE_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1450 = C_ULE_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1449 = C_UEQ_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1448 = C_UEQ_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1447 = C_UEQ_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1446 = C_UEQ_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1445 = C_UEQ_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1444 = C_UEQ_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1443 = C_SF_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1442 = C_SF_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1441 = C_SF_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1440 = C_SF_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1439 = C_SF_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1438 = C_SF_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1437 = C_SEQ_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1436 = C_SEQ_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1435 = C_SEQ_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1434 = C_SEQ_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1433 = C_SEQ_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1432 = C_SEQ_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1431 = C_OLT_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1430 = C_OLT_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1429 = C_OLT_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1428 = C_OLT_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1427 = C_OLT_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1426 = C_OLT_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1425 = C_OLE_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1424 = C_OLE_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1423 = C_OLE_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1422 = C_OLE_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1421 = C_OLE_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1420 = C_OLE_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1419 = C_NGT_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1418 = C_NGT_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1417 = C_NGT_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1416 = C_NGT_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1415 = C_NGT_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1414 = C_NGT_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1413 = C_NGL_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1412 = C_NGL_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1411 = C_NGL_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1410 = C_NGL_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1409 = C_NGL_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1408 = C_NGL_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1407 = C_NGLE_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1406 = C_NGLE_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1405 = C_NGLE_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1404 = C_NGLE_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1403 = C_NGLE_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1402 = C_NGLE_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1401 = C_NGE_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1400 = C_NGE_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1399 = C_NGE_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1398 = C_NGE_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1397 = C_NGE_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1396 = C_NGE_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1395 = C_LT_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1394 = C_LT_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1393 = C_LT_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1392 = C_LT_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1391 = C_LT_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1390 = C_LT_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1389 = C_LE_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1388 = C_LE_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1387 = C_LE_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1386 = C_LE_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1385 = C_LE_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1384 = C_LE_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1383 = C_F_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1382 = C_F_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1381 = C_F_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1380 = C_F_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1379 = C_F_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1378 = C_F_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1377 = C_EQ_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1376 = C_EQ_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1375 = C_EQ_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1374 = C_EQ_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1373 = C_EQ_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1372 = C_EQ_D32 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1371 = CVT_W_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1370 = CVT_W_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1369 = CVT_W_S + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1368 = CVT_W_D64_MM + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1367 = CVT_W_D64 + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1366 = CVT_W_D32_MM + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1365 = CVT_W_D32 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1364 = CVT_S_W_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1363 = CVT_S_W_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1362 = CVT_S_W + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1361 = CVT_S_PU64 + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1360 = CVT_S_PL64 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1359 = CVT_S_L_MMR6 + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1358 = CVT_S_L + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1357 = CVT_S_D64_MM + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1356 = CVT_S_D64 + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1355 = CVT_S_D32_MM + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1354 = CVT_S_D32 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1353 = CVT_PW_PS64 + { 3, &MipsDescs.OperandInfo[751] }, // Inst #1352 = CVT_PS_S64 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1351 = CVT_PS_PW64 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1350 = CVT_L_S_MMR6 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1349 = CVT_L_S_MM + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1348 = CVT_L_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1347 = CVT_L_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1346 = CVT_L_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1345 = CVT_L_D64 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1344 = CVT_D_L_MMR6 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1343 = CVT_D64_W_MM + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1342 = CVT_D64_W + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1341 = CVT_D64_S_MM + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1340 = CVT_D64_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1339 = CVT_D64_L + { 2, &MipsDescs.OperandInfo[749] }, // Inst #1338 = CVT_D32_W_MM + { 2, &MipsDescs.OperandInfo[749] }, // Inst #1337 = CVT_D32_W + { 2, &MipsDescs.OperandInfo[749] }, // Inst #1336 = CVT_D32_S_MM + { 2, &MipsDescs.OperandInfo[749] }, // Inst #1335 = CVT_D32_S + { 2, &MipsDescs.OperandInfo[747] }, // Inst #1334 = CTCMSA + { 2, &MipsDescs.OperandInfo[745] }, // Inst #1333 = CTC2_MM + { 2, &MipsDescs.OperandInfo[743] }, // Inst #1332 = CTC1_MM + { 2, &MipsDescs.OperandInfo[743] }, // Inst #1331 = CTC1 + { 3, &MipsDescs.OperandInfo[740] }, // Inst #1330 = CRC32W_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1329 = CRC32W + { 3, &MipsDescs.OperandInfo[740] }, // Inst #1328 = CRC32H_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1327 = CRC32H + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1326 = CRC32D + { 3, &MipsDescs.OperandInfo[740] }, // Inst #1325 = CRC32CW_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1324 = CRC32CW + { 3, &MipsDescs.OperandInfo[740] }, // Inst #1323 = CRC32CH_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1322 = CRC32CH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1321 = CRC32CD + { 3, &MipsDescs.OperandInfo[740] }, // Inst #1320 = CRC32CB_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1319 = CRC32CB + { 3, &MipsDescs.OperandInfo[740] }, // Inst #1318 = CRC32B_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1317 = CRC32B + { 3, &MipsDescs.OperandInfo[737] }, // Inst #1316 = COPY_U_W + { 3, &MipsDescs.OperandInfo[734] }, // Inst #1315 = COPY_U_H + { 3, &MipsDescs.OperandInfo[728] }, // Inst #1314 = COPY_U_B + { 3, &MipsDescs.OperandInfo[737] }, // Inst #1313 = COPY_S_W + { 3, &MipsDescs.OperandInfo[734] }, // Inst #1312 = COPY_S_H + { 3, &MipsDescs.OperandInfo[731] }, // Inst #1311 = COPY_S_D + { 3, &MipsDescs.OperandInfo[728] }, // Inst #1310 = COPY_S_B + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1309 = CMP_UN_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1308 = CMP_UN_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1307 = CMP_UN_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1306 = CMP_UN_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1305 = CMP_ULT_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1304 = CMP_ULT_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1303 = CMP_ULT_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1302 = CMP_ULT_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1301 = CMP_ULE_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1300 = CMP_ULE_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1299 = CMP_ULE_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1298 = CMP_ULE_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1297 = CMP_UEQ_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1296 = CMP_UEQ_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1295 = CMP_UEQ_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1294 = CMP_UEQ_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1293 = CMP_SUN_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1292 = CMP_SUN_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1291 = CMP_SUN_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1290 = CMP_SUN_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1289 = CMP_SULT_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1288 = CMP_SULT_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1287 = CMP_SULT_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1286 = CMP_SULT_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1285 = CMP_SULE_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1284 = CMP_SULE_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1283 = CMP_SULE_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1282 = CMP_SULE_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1281 = CMP_SUEQ_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1280 = CMP_SUEQ_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1279 = CMP_SUEQ_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1278 = CMP_SUEQ_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1277 = CMP_SLT_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1276 = CMP_SLT_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1275 = CMP_SLT_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1274 = CMP_SLT_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1273 = CMP_SLE_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1272 = CMP_SLE_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1271 = CMP_SLE_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1270 = CMP_SLE_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1269 = CMP_SEQ_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1268 = CMP_SEQ_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1267 = CMP_SEQ_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1266 = CMP_SEQ_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1265 = CMP_SAF_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1264 = CMP_SAF_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1263 = CMP_SAF_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1262 = CMP_SAF_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1261 = CMP_LT_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1260 = CMP_LT_S + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1259 = CMP_LT_PH_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1258 = CMP_LT_PH + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1257 = CMP_LT_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1256 = CMP_LT_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1255 = CMP_LE_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1254 = CMP_LE_S + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1253 = CMP_LE_PH_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1252 = CMP_LE_PH + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1251 = CMP_LE_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1250 = CMP_LE_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1249 = CMP_F_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1248 = CMP_F_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1247 = CMP_EQ_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1246 = CMP_EQ_S + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1245 = CMP_EQ_PH_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1244 = CMP_EQ_PH + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1243 = CMP_EQ_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1242 = CMP_EQ_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1241 = CMP_AF_S_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1240 = CMP_AF_D_MMR6 + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1239 = CMPU_LT_QB_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1238 = CMPU_LT_QB + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1237 = CMPU_LE_QB_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1236 = CMPU_LE_QB + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1235 = CMPU_EQ_QB_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1234 = CMPU_EQ_QB + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1233 = CMPGU_LT_QB_MM + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1232 = CMPGU_LT_QB + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1231 = CMPGU_LE_QB_MM + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1230 = CMPGU_LE_QB + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1229 = CMPGU_EQ_QB_MM + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1228 = CMPGU_EQ_QB + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1227 = CMPGDU_LT_QB_MMR2 + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1226 = CMPGDU_LT_QB + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1225 = CMPGDU_LE_QB_MMR2 + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1224 = CMPGDU_LE_QB + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1223 = CMPGDU_EQ_QB_MMR2 + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1222 = CMPGDU_EQ_QB + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1221 = CLZ_R6 + { 2, &MipsDescs.OperandInfo[416] }, // Inst #1220 = CLZ_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1219 = CLZ_MMR6 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1218 = CLZ_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1217 = CLZ + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1216 = CLT_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1215 = CLT_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1214 = CLT_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1213 = CLT_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1212 = CLT_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1211 = CLT_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1210 = CLT_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1209 = CLT_S_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1208 = CLTI_U_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1207 = CLTI_U_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1206 = CLTI_U_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1205 = CLTI_U_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1204 = CLTI_S_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1203 = CLTI_S_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1202 = CLTI_S_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1201 = CLTI_S_B + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1200 = CLO_R6 + { 2, &MipsDescs.OperandInfo[416] }, // Inst #1199 = CLO_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1198 = CLO_MMR6 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1197 = CLO_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1196 = CLO + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1195 = CLE_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1194 = CLE_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1193 = CLE_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1192 = CLE_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1191 = CLE_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1190 = CLE_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1189 = CLE_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1188 = CLE_S_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1187 = CLEI_U_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1186 = CLEI_U_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1185 = CLEI_U_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1184 = CLEI_U_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1183 = CLEI_S_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1182 = CLEI_S_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1181 = CLEI_S_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1180 = CLEI_S_B + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1179 = CLASS_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1178 = CLASS_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1177 = CLASS_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1176 = CLASS_D + { 4, &MipsDescs.OperandInfo[715] }, // Inst #1175 = CINS_i32 + { 4, &MipsDescs.OperandInfo[711] }, // Inst #1174 = CINS64_32 + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1173 = CINS32 + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1172 = CINS + { 2, &MipsDescs.OperandInfo[705] }, // Inst #1171 = CFCMSA + { 2, &MipsDescs.OperandInfo[703] }, // Inst #1170 = CFC2_MM + { 2, &MipsDescs.OperandInfo[701] }, // Inst #1169 = CFC1_MM + { 2, &MipsDescs.OperandInfo[701] }, // Inst #1168 = CFC1 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1167 = CEQ_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1166 = CEQ_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1165 = CEQ_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1164 = CEQ_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1163 = CEQI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1162 = CEQI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1161 = CEQI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1160 = CEQI_B + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1159 = CEIL_W_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1158 = CEIL_W_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1157 = CEIL_W_S + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1156 = CEIL_W_MM + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1155 = CEIL_W_D_MMR6 + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1154 = CEIL_W_D64 + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1153 = CEIL_W_D32 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1152 = CEIL_L_S_MMR6 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1151 = CEIL_L_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1150 = CEIL_L_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1149 = CEIL_L_D64 + { 3, &MipsDescs.OperandInfo[688] }, // Inst #1148 = CACHE_R6 + { 3, &MipsDescs.OperandInfo[354] }, // Inst #1147 = CACHE_NM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #1146 = CACHE_MMR6 + { 3, &MipsDescs.OperandInfo[688] }, // Inst #1145 = CACHE_MM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #1144 = CACHEE_MM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #1143 = CACHEE + { 3, &MipsDescs.OperandInfo[688] }, // Inst #1142 = CACHE + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1141 = BtnezX16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1140 = Btnez16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1139 = BteqzX16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1138 = Bteqz16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1137 = Break16 + { 2, &MipsDescs.OperandInfo[686] }, // Inst #1136 = BnezRxImmX16 + { 2, &MipsDescs.OperandInfo[686] }, // Inst #1135 = BnezRxImm16 + { 1, &MipsDescs.OperandInfo[182] }, // Inst #1134 = BimmX16 + { 1, &MipsDescs.OperandInfo[182] }, // Inst #1133 = Bimm16 + { 2, &MipsDescs.OperandInfo[686] }, // Inst #1132 = BeqzRxImmX16 + { 2, &MipsDescs.OperandInfo[686] }, // Inst #1131 = BeqzRxImm16 + { 2, &MipsDescs.OperandInfo[682] }, // Inst #1130 = BZ_W + { 2, &MipsDescs.OperandInfo[676] }, // Inst #1129 = BZ_V + { 2, &MipsDescs.OperandInfo[680] }, // Inst #1128 = BZ_H + { 2, &MipsDescs.OperandInfo[678] }, // Inst #1127 = BZ_D + { 2, &MipsDescs.OperandInfo[676] }, // Inst #1126 = BZ_B + { 2, &MipsDescs.OperandInfo[416] }, // Inst #1125 = BYTEREVW_NM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1124 = BSET_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1123 = BSET_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1122 = BSET_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1121 = BSET_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1120 = BSETI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1119 = BSETI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1118 = BSETI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1117 = BSETI_B + { 4, &MipsDescs.OperandInfo[672] }, // Inst #1116 = BSEL_V + { 4, &MipsDescs.OperandInfo[656] }, // Inst #1115 = BSELI_B + { 2, &MipsDescs.OperandInfo[684] }, // Inst #1114 = BRSC_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1113 = BREAK_NM + { 2, &MipsDescs.OperandInfo[13] }, // Inst #1112 = BREAK_MMR6 + { 2, &MipsDescs.OperandInfo[13] }, // Inst #1111 = BREAK_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1110 = BREAK16_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1109 = BREAK16_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1108 = BREAK16_MM + { 2, &MipsDescs.OperandInfo[13] }, // Inst #1107 = BREAK + { 1, &MipsDescs.OperandInfo[182] }, // Inst #1106 = BPOSGE32_MM + { 1, &MipsDescs.OperandInfo[182] }, // Inst #1105 = BPOSGE32C_MMR3 + { 1, &MipsDescs.OperandInfo[182] }, // Inst #1104 = BPOSGE32 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1103 = BOVC_MMR6 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1102 = BOVC + { 2, &MipsDescs.OperandInfo[682] }, // Inst #1101 = BNZ_W + { 2, &MipsDescs.OperandInfo[676] }, // Inst #1100 = BNZ_V + { 2, &MipsDescs.OperandInfo[680] }, // Inst #1099 = BNZ_H + { 2, &MipsDescs.OperandInfo[678] }, // Inst #1098 = BNZ_D + { 2, &MipsDescs.OperandInfo[676] }, // Inst #1097 = BNZ_B + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1096 = BNVC_MMR6 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1095 = BNVC + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1094 = BNE_MM + { 2, &MipsDescs.OperandInfo[609] }, // Inst #1093 = BNEZC_NM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1092 = BNEZC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1091 = BNEZC_MM + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1090 = BNEZC64 + { 2, &MipsDescs.OperandInfo[654] }, // Inst #1089 = BNEZC16_NM + { 2, &MipsDescs.OperandInfo[652] }, // Inst #1088 = BNEZC16_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1087 = BNEZC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1086 = BNEZALC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1085 = BNEZALC + { 2, &MipsDescs.OperandInfo[652] }, // Inst #1084 = BNEZ16_MM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1083 = BNEL + { 3, &MipsDescs.OperandInfo[631] }, // Inst #1082 = BNEIC_NM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1081 = BNEG_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1080 = BNEG_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1079 = BNEG_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1078 = BNEG_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1077 = BNEGI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1076 = BNEGI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1075 = BNEGI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1074 = BNEGI_B + { 3, &MipsDescs.OperandInfo[649] }, // Inst #1073 = BNECzero_NM + { 3, &MipsDescs.OperandInfo[646] }, // Inst #1072 = BNEC_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1071 = BNEC_MMR6 + { 3, &MipsDescs.OperandInfo[344] }, // Inst #1070 = BNEC64 + { 3, &MipsDescs.OperandInfo[643] }, // Inst #1069 = BNEC16_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1068 = BNEC + { 3, &MipsDescs.OperandInfo[344] }, // Inst #1067 = BNE64 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1066 = BNE + { 4, &MipsDescs.OperandInfo[672] }, // Inst #1065 = BMZ_V + { 4, &MipsDescs.OperandInfo[656] }, // Inst #1064 = BMZI_B + { 4, &MipsDescs.OperandInfo[672] }, // Inst #1063 = BMNZ_V + { 4, &MipsDescs.OperandInfo[656] }, // Inst #1062 = BMNZI_B + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1061 = BLTZ_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1060 = BLTZL + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1059 = BLTZC_MMR6 + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1058 = BLTZC64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1057 = BLTZC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1056 = BLTZAL_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1055 = BLTZALS_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1054 = BLTZALL + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1053 = BLTZALC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1052 = BLTZALC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1051 = BLTZAL + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1050 = BLTZ64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1049 = BLTZ + { 3, &MipsDescs.OperandInfo[646] }, // Inst #1048 = BLTUC_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1047 = BLTUC_MMR6 + { 3, &MipsDescs.OperandInfo[344] }, // Inst #1046 = BLTUC64 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1045 = BLTUC + { 3, &MipsDescs.OperandInfo[631] }, // Inst #1044 = BLTIUC_NM + { 3, &MipsDescs.OperandInfo[631] }, // Inst #1043 = BLTIC_NM + { 3, &MipsDescs.OperandInfo[646] }, // Inst #1042 = BLTC_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1041 = BLTC_MMR6 + { 3, &MipsDescs.OperandInfo[344] }, // Inst #1040 = BLTC64 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1039 = BLTC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1038 = BLEZ_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1037 = BLEZL + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1036 = BLEZC_MMR6 + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1035 = BLEZC64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1034 = BLEZC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1033 = BLEZALC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1032 = BLEZALC + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1031 = BLEZ64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1030 = BLEZ + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1029 = BITSWAP_MMR6 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1028 = BITSWAP + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1027 = BITREV_MM + { 2, &MipsDescs.OperandInfo[416] }, // Inst #1026 = BITREVW_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1025 = BITREV + { 4, &MipsDescs.OperandInfo[194] }, // Inst #1024 = BINSR_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #1023 = BINSR_H + { 4, &MipsDescs.OperandInfo[190] }, // Inst #1022 = BINSR_D + { 4, &MipsDescs.OperandInfo[672] }, // Inst #1021 = BINSR_B + { 4, &MipsDescs.OperandInfo[668] }, // Inst #1020 = BINSRI_W + { 4, &MipsDescs.OperandInfo[664] }, // Inst #1019 = BINSRI_H + { 4, &MipsDescs.OperandInfo[660] }, // Inst #1018 = BINSRI_D + { 4, &MipsDescs.OperandInfo[656] }, // Inst #1017 = BINSRI_B + { 4, &MipsDescs.OperandInfo[194] }, // Inst #1016 = BINSL_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #1015 = BINSL_H + { 4, &MipsDescs.OperandInfo[190] }, // Inst #1014 = BINSL_D + { 4, &MipsDescs.OperandInfo[672] }, // Inst #1013 = BINSL_B + { 4, &MipsDescs.OperandInfo[668] }, // Inst #1012 = BINSLI_W + { 4, &MipsDescs.OperandInfo[664] }, // Inst #1011 = BINSLI_H + { 4, &MipsDescs.OperandInfo[660] }, // Inst #1010 = BINSLI_D + { 4, &MipsDescs.OperandInfo[656] }, // Inst #1009 = BINSLI_B + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1008 = BGTZ_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1007 = BGTZL + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1006 = BGTZC_MMR6 + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1005 = BGTZC64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1004 = BGTZC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1003 = BGTZALC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1002 = BGTZALC + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1001 = BGTZ64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1000 = BGTZ + { 2, &MipsDescs.OperandInfo[350] }, // Inst #999 = BGEZ_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #998 = BGEZL + { 2, &MipsDescs.OperandInfo[350] }, // Inst #997 = BGEZC_MMR6 + { 2, &MipsDescs.OperandInfo[352] }, // Inst #996 = BGEZC64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #995 = BGEZC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #994 = BGEZAL_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #993 = BGEZALS_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #992 = BGEZALL + { 2, &MipsDescs.OperandInfo[350] }, // Inst #991 = BGEZALC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #990 = BGEZALC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #989 = BGEZAL + { 2, &MipsDescs.OperandInfo[352] }, // Inst #988 = BGEZ64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #987 = BGEZ + { 3, &MipsDescs.OperandInfo[646] }, // Inst #986 = BGEUC_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #985 = BGEUC_MMR6 + { 3, &MipsDescs.OperandInfo[344] }, // Inst #984 = BGEUC64 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #983 = BGEUC + { 3, &MipsDescs.OperandInfo[631] }, // Inst #982 = BGEIUC_NM + { 3, &MipsDescs.OperandInfo[631] }, // Inst #981 = BGEIC_NM + { 3, &MipsDescs.OperandInfo[646] }, // Inst #980 = BGEC_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #979 = BGEC_MMR6 + { 3, &MipsDescs.OperandInfo[344] }, // Inst #978 = BGEC64 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #977 = BGEC + { 3, &MipsDescs.OperandInfo[186] }, // Inst #976 = BEQ_MM + { 2, &MipsDescs.OperandInfo[609] }, // Inst #975 = BEQZC_NM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #974 = BEQZC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #973 = BEQZC_MM + { 2, &MipsDescs.OperandInfo[352] }, // Inst #972 = BEQZC64 + { 2, &MipsDescs.OperandInfo[654] }, // Inst #971 = BEQZC16_NM + { 2, &MipsDescs.OperandInfo[652] }, // Inst #970 = BEQZC16_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #969 = BEQZC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #968 = BEQZALC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #967 = BEQZALC + { 2, &MipsDescs.OperandInfo[652] }, // Inst #966 = BEQZ16_MM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #965 = BEQL + { 3, &MipsDescs.OperandInfo[631] }, // Inst #964 = BEQIC_NM + { 3, &MipsDescs.OperandInfo[649] }, // Inst #963 = BEQCzero_NM + { 3, &MipsDescs.OperandInfo[646] }, // Inst #962 = BEQC_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #961 = BEQC_MMR6 + { 3, &MipsDescs.OperandInfo[344] }, // Inst #960 = BEQC64 + { 3, &MipsDescs.OperandInfo[643] }, // Inst #959 = BEQC16_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #958 = BEQC + { 3, &MipsDescs.OperandInfo[344] }, // Inst #957 = BEQ64 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #956 = BEQ + { 1, &MipsDescs.OperandInfo[182] }, // Inst #955 = BC_NM + { 1, &MipsDescs.OperandInfo[182] }, // Inst #954 = BC_MMR6 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #953 = BCLR_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #952 = BCLR_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #951 = BCLR_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #950 = BCLR_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #949 = BCLRI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #948 = BCLRI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #947 = BCLRI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #946 = BCLRI_B + { 2, &MipsDescs.OperandInfo[641] }, // Inst #945 = BC2NEZC_MMR6 + { 2, &MipsDescs.OperandInfo[641] }, // Inst #944 = BC2NEZ + { 2, &MipsDescs.OperandInfo[641] }, // Inst #943 = BC2EQZC_MMR6 + { 2, &MipsDescs.OperandInfo[641] }, // Inst #942 = BC2EQZ + { 2, &MipsDescs.OperandInfo[639] }, // Inst #941 = BC1T_MM + { 2, &MipsDescs.OperandInfo[639] }, // Inst #940 = BC1TL + { 2, &MipsDescs.OperandInfo[639] }, // Inst #939 = BC1T + { 2, &MipsDescs.OperandInfo[637] }, // Inst #938 = BC1NEZC_MMR6 + { 2, &MipsDescs.OperandInfo[637] }, // Inst #937 = BC1NEZ + { 2, &MipsDescs.OperandInfo[639] }, // Inst #936 = BC1F_MM + { 2, &MipsDescs.OperandInfo[639] }, // Inst #935 = BC1FL + { 2, &MipsDescs.OperandInfo[639] }, // Inst #934 = BC1F + { 2, &MipsDescs.OperandInfo[637] }, // Inst #933 = BC1EQZC_MMR6 + { 2, &MipsDescs.OperandInfo[637] }, // Inst #932 = BC1EQZ + { 1, &MipsDescs.OperandInfo[182] }, // Inst #931 = BC16_NM + { 1, &MipsDescs.OperandInfo[182] }, // Inst #930 = BC16_MMR6 + { 1, &MipsDescs.OperandInfo[182] }, // Inst #929 = BC + { 3, &MipsDescs.OperandInfo[631] }, // Inst #928 = BBNEZC_NM + { 3, &MipsDescs.OperandInfo[634] }, // Inst #927 = BBIT132 + { 3, &MipsDescs.OperandInfo[634] }, // Inst #926 = BBIT1 + { 3, &MipsDescs.OperandInfo[634] }, // Inst #925 = BBIT032 + { 3, &MipsDescs.OperandInfo[634] }, // Inst #924 = BBIT0 + { 3, &MipsDescs.OperandInfo[631] }, // Inst #923 = BBEQZC_NM + { 2, &MipsDescs.OperandInfo[629] }, // Inst #922 = BALRSC_NM + { 4, &MipsDescs.OperandInfo[614] }, // Inst #921 = BALIGN_MMR2 + { 4, &MipsDescs.OperandInfo[614] }, // Inst #920 = BALIGN + { 1, &MipsDescs.OperandInfo[182] }, // Inst #919 = BALC_NM + { 1, &MipsDescs.OperandInfo[182] }, // Inst #918 = BALC_MMR6 + { 1, &MipsDescs.OperandInfo[182] }, // Inst #917 = BALC16_NM + { 1, &MipsDescs.OperandInfo[182] }, // Inst #916 = BALC + { 1, &MipsDescs.OperandInfo[182] }, // Inst #915 = BAL + { 3, &MipsDescs.OperandInfo[227] }, // Inst #914 = BADDu + { 1, &MipsDescs.OperandInfo[182] }, // Inst #913 = B16_MM + { 3, &MipsDescs.OperandInfo[626] }, // Inst #912 = AndRxRxRy16 + { 3, &MipsDescs.OperandInfo[421] }, // Inst #911 = AdduRxRyRz16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #910 = AddiuSpImmX16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #909 = AddiuSpImm16 + { 3, &MipsDescs.OperandInfo[623] }, // Inst #908 = AddiuRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[620] }, // Inst #907 = AddiuRxRxImmX16 + { 3, &MipsDescs.OperandInfo[620] }, // Inst #906 = AddiuRxRxImm16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #905 = AddiuRxPcImmX16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #904 = AddiuRxImmX16 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #903 = AVE_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #902 = AVE_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #901 = AVE_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #900 = AVE_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #899 = AVE_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #898 = AVE_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #897 = AVE_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #896 = AVE_S_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #895 = AVER_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #894 = AVER_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #893 = AVER_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #892 = AVER_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #891 = AVER_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #890 = AVER_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #889 = AVER_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #888 = AVER_S_B + { 3, &MipsDescs.OperandInfo[233] }, // Inst #887 = AUI_MMR6 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #886 = AUIPC_MMR6 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #885 = AUIPC + { 3, &MipsDescs.OperandInfo[233] }, // Inst #884 = AUI + { 3, &MipsDescs.OperandInfo[152] }, // Inst #883 = ASUB_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #882 = ASUB_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #881 = ASUB_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #880 = ASUB_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #879 = ASUB_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #878 = ASUB_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #877 = ASUB_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #876 = ASUB_S_B + { 4, &MipsDescs.OperandInfo[614] }, // Inst #875 = APPEND_MMR2 + { 4, &MipsDescs.OperandInfo[614] }, // Inst #874 = APPEND + { 3, &MipsDescs.OperandInfo[233] }, // Inst #873 = ANDi_MM + { 3, &MipsDescs.OperandInfo[224] }, // Inst #872 = ANDi64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #871 = ANDi + { 3, &MipsDescs.OperandInfo[578] }, // Inst #870 = AND_V + { 3, &MipsDescs.OperandInfo[596] }, // Inst #869 = AND_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #868 = AND_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #867 = AND_MM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #866 = ANDI_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #865 = ANDI_MMR6 + { 3, &MipsDescs.OperandInfo[584] }, // Inst #864 = ANDI_B + { 3, &MipsDescs.OperandInfo[566] }, // Inst #863 = ANDI16_NM + { 3, &MipsDescs.OperandInfo[563] }, // Inst #862 = ANDI16_MMR6 + { 3, &MipsDescs.OperandInfo[563] }, // Inst #861 = ANDI16_MM + { 3, &MipsDescs.OperandInfo[227] }, // Inst #860 = AND64 + { 3, &MipsDescs.OperandInfo[599] }, // Inst #859 = AND16_NM + { 3, &MipsDescs.OperandInfo[611] }, // Inst #858 = AND16_MMR6 + { 3, &MipsDescs.OperandInfo[611] }, // Inst #857 = AND16_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #856 = AND + { 2, &MipsDescs.OperandInfo[609] }, // Inst #855 = ALUIPC_NM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #854 = ALUIPC_MMR6 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #853 = ALUIPC + { 4, &MipsDescs.OperandInfo[605] }, // Inst #852 = ALIGN_MMR6 + { 4, &MipsDescs.OperandInfo[605] }, // Inst #851 = ALIGN + { 3, &MipsDescs.OperandInfo[596] }, // Inst #850 = ADDu_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #849 = ADDu_MM + { 3, &MipsDescs.OperandInfo[602] }, // Inst #848 = ADDu4x4_NM + { 3, &MipsDescs.OperandInfo[599] }, // Inst #847 = ADDu16_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #846 = ADDu + { 3, &MipsDescs.OperandInfo[233] }, // Inst #845 = ADDiu_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #844 = ADDiu + { 3, &MipsDescs.OperandInfo[233] }, // Inst #843 = ADDi_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #842 = ADDi + { 3, &MipsDescs.OperandInfo[596] }, // Inst #841 = ADD_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #840 = ADD_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #839 = ADD_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #838 = ADD_A_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #837 = ADD_A_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #836 = ADD_A_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #835 = ADD_A_B + { 3, &MipsDescs.OperandInfo[230] }, // Inst #834 = ADDWC_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #833 = ADDWC + { 3, &MipsDescs.OperandInfo[152] }, // Inst #832 = ADDV_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #831 = ADDV_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #830 = ADDV_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #829 = ADDV_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #828 = ADDVI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #827 = ADDVI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #826 = ADDVI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #825 = ADDVI_B + { 3, &MipsDescs.OperandInfo[572] }, // Inst #824 = ADDU_S_QB_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #823 = ADDU_S_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #822 = ADDU_S_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #821 = ADDU_S_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #820 = ADDU_QB_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #819 = ADDU_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #818 = ADDU_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #817 = ADDU_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #816 = ADDU_MMR6 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #815 = ADDUH_R_QB_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #814 = ADDUH_R_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #813 = ADDUH_QB_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #812 = ADDUH_QB + { 3, &MipsDescs.OperandInfo[581] }, // Inst #811 = ADDU16_MMR6 + { 3, &MipsDescs.OperandInfo[581] }, // Inst #810 = ADDU16_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #809 = ADDS_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #808 = ADDS_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #807 = ADDS_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #806 = ADDS_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #805 = ADDS_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #804 = ADDS_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #803 = ADDS_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #802 = ADDS_S_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #801 = ADDS_A_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #800 = ADDS_A_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #799 = ADDS_A_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #798 = ADDS_A_B + { 3, &MipsDescs.OperandInfo[230] }, // Inst #797 = ADDSC_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #796 = ADDSC + { 3, &MipsDescs.OperandInfo[575] }, // Inst #795 = ADDR_PS64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #794 = ADDQ_S_W_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #793 = ADDQ_S_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #792 = ADDQ_S_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #791 = ADDQ_S_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #790 = ADDQ_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #789 = ADDQ_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #788 = ADDQH_W_MMR2 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #787 = ADDQH_W + { 3, &MipsDescs.OperandInfo[230] }, // Inst #786 = ADDQH_R_W_MMR2 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #785 = ADDQH_R_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #784 = ADDQH_R_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #783 = ADDQH_R_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #782 = ADDQH_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #781 = ADDQH_PH + { 3, &MipsDescs.OperandInfo[391] }, // Inst #780 = ADDIU_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #779 = ADDIU_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #778 = ADDIUSP_MM + { 3, &MipsDescs.OperandInfo[569] }, // Inst #777 = ADDIUS5_MM + { 3, &MipsDescs.OperandInfo[552] }, // Inst #776 = ADDIURS5_NM + { 3, &MipsDescs.OperandInfo[566] }, // Inst #775 = ADDIUR2_NM + { 3, &MipsDescs.OperandInfo[563] }, // Inst #774 = ADDIUR2_MM + { 3, &MipsDescs.OperandInfo[560] }, // Inst #773 = ADDIUR1SP_NM + { 2, &MipsDescs.OperandInfo[558] }, // Inst #772 = ADDIUR1SP_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #771 = ADDIUPC_MMR6 + { 2, &MipsDescs.OperandInfo[558] }, // Inst #770 = ADDIUPC_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #769 = ADDIUPC + { 3, &MipsDescs.OperandInfo[391] }, // Inst #768 = ADDIUNEG_NM + { 3, &MipsDescs.OperandInfo[555] }, // Inst #767 = ADDIUGPW_NM + { 3, &MipsDescs.OperandInfo[555] }, // Inst #766 = ADDIUGPB_NM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #765 = ADDIUGP48_NM + { 3, &MipsDescs.OperandInfo[552] }, // Inst #764 = ADDIU48_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #763 = ADD + { 2, &MipsDescs.OperandInfo[140] }, // Inst #762 = ABSQ_S_W_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #761 = ABSQ_S_W + { 2, &MipsDescs.OperandInfo[550] }, // Inst #760 = ABSQ_S_QB_MMR2 + { 2, &MipsDescs.OperandInfo[550] }, // Inst #759 = ABSQ_S_QB + { 2, &MipsDescs.OperandInfo[550] }, // Inst #758 = ABSQ_S_PH_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #757 = ABSQ_S_PH + { 3, &MipsDescs.OperandInfo[152] }, // Inst #756 = XOR_V_W_PSEUDO + { 3, &MipsDescs.OperandInfo[149] }, // Inst #755 = XOR_V_H_PSEUDO + { 3, &MipsDescs.OperandInfo[146] }, // Inst #754 = XOR_V_D_PSEUDO + { 3, &MipsDescs.OperandInfo[312] }, // Inst #753 = Usw + { 3, &MipsDescs.OperandInfo[312] }, // Inst #752 = Ush + { 3, &MipsDescs.OperandInfo[312] }, // Inst #751 = Ulw + { 3, &MipsDescs.OperandInfo[312] }, // Inst #750 = Ulhu + { 3, &MipsDescs.OperandInfo[312] }, // Inst #749 = Ulh + { 3, &MipsDescs.OperandInfo[230] }, // Inst #748 = URemMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #747 = URemIMacro + { 3, &MipsDescs.OperandInfo[230] }, // Inst #746 = UDivMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #745 = UDivIMacro + { 3, &MipsDescs.OperandInfo[460] }, // Inst #744 = UDIV_MM_Pseudo + { 0, &MipsDescs.OperandInfo[1] }, // Inst #743 = TRAP_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #742 = TRAP + { 1, &MipsDescs.OperandInfo[182] }, // Inst #741 = TAILCALL_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #740 = TAILCALL_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #739 = TAILCALL_MM + { 1, &MipsDescs.OperandInfo[418] }, // Inst #738 = TAILCALLREG_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #737 = TAILCALLREG_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #736 = TAILCALLREG_MM + { 1, &MipsDescs.OperandInfo[310] }, // Inst #735 = TAILCALLREGHB64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #734 = TAILCALLREGHB + { 1, &MipsDescs.OperandInfo[310] }, // Inst #733 = TAILCALLREG64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #732 = TAILCALLREG + { 1, &MipsDescs.OperandInfo[189] }, // Inst #731 = TAILCALLR6REG + { 1, &MipsDescs.OperandInfo[189] }, // Inst #730 = TAILCALLHBR6REG + { 1, &MipsDescs.OperandInfo[310] }, // Inst #729 = TAILCALLHB64R6REG + { 1, &MipsDescs.OperandInfo[310] }, // Inst #728 = TAILCALL64R6REG + { 1, &MipsDescs.OperandInfo[0] }, // Inst #727 = TAILCALL + { 3, &MipsDescs.OperandInfo[421] }, // Inst #726 = SltuRxRyRz16 + { 3, &MipsDescs.OperandInfo[421] }, // Inst #725 = SltuCCRxRy16 + { 3, &MipsDescs.OperandInfo[547] }, // Inst #724 = SltiuCCRxImmX16 + { 3, &MipsDescs.OperandInfo[547] }, // Inst #723 = SltiCCRxImmX16 + { 3, &MipsDescs.OperandInfo[421] }, // Inst #722 = SltCCRxRy16 + { 5, &MipsDescs.OperandInfo[537] }, // Inst #721 = SelTBtneZSltu + { 5, &MipsDescs.OperandInfo[542] }, // Inst #720 = SelTBtneZSltiu + { 5, &MipsDescs.OperandInfo[542] }, // Inst #719 = SelTBtneZSlti + { 5, &MipsDescs.OperandInfo[537] }, // Inst #718 = SelTBtneZSlt + { 5, &MipsDescs.OperandInfo[542] }, // Inst #717 = SelTBtneZCmpi + { 5, &MipsDescs.OperandInfo[537] }, // Inst #716 = SelTBtneZCmp + { 5, &MipsDescs.OperandInfo[537] }, // Inst #715 = SelTBteqZSltu + { 5, &MipsDescs.OperandInfo[542] }, // Inst #714 = SelTBteqZSltiu + { 5, &MipsDescs.OperandInfo[542] }, // Inst #713 = SelTBteqZSlti + { 5, &MipsDescs.OperandInfo[537] }, // Inst #712 = SelTBteqZSlt + { 5, &MipsDescs.OperandInfo[542] }, // Inst #711 = SelTBteqZCmpi + { 5, &MipsDescs.OperandInfo[537] }, // Inst #710 = SelTBteqZCmp + { 4, &MipsDescs.OperandInfo[533] }, // Inst #709 = SelBneZ + { 4, &MipsDescs.OperandInfo[533] }, // Inst #708 = SelBeqZ + { 3, &MipsDescs.OperandInfo[361] }, // Inst #707 = SaadAddr + { 3, &MipsDescs.OperandInfo[361] }, // Inst #706 = SaaAddr + { 2, &MipsDescs.OperandInfo[531] }, // Inst #705 = SZ_W_PSEUDO + { 2, &MipsDescs.OperandInfo[525] }, // Inst #704 = SZ_V_PSEUDO + { 2, &MipsDescs.OperandInfo[529] }, // Inst #703 = SZ_H_PSEUDO + { 2, &MipsDescs.OperandInfo[527] }, // Inst #702 = SZ_D_PSEUDO + { 2, &MipsDescs.OperandInfo[525] }, // Inst #701 = SZ_B_PSEUDO + { 3, &MipsDescs.OperandInfo[354] }, // Inst #700 = SWM_MM + { 3, &MipsDescs.OperandInfo[321] }, // Inst #699 = ST_F16 + { 3, &MipsDescs.OperandInfo[318] }, // Inst #698 = STR_W + { 3, &MipsDescs.OperandInfo[315] }, // Inst #697 = STR_D + { 3, &MipsDescs.OperandInfo[333] }, // Inst #696 = STORE_CCOND_DSP + { 3, &MipsDescs.OperandInfo[330] }, // Inst #695 = STORE_ACC64DSP + { 3, &MipsDescs.OperandInfo[327] }, // Inst #694 = STORE_ACC64 + { 3, &MipsDescs.OperandInfo[324] }, // Inst #693 = STORE_ACC128 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #692 = SRemMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #691 = SRemIMacro + { 2, &MipsDescs.OperandInfo[531] }, // Inst #690 = SNZ_W_PSEUDO + { 2, &MipsDescs.OperandInfo[525] }, // Inst #689 = SNZ_V_PSEUDO + { 2, &MipsDescs.OperandInfo[529] }, // Inst #688 = SNZ_H_PSEUDO + { 2, &MipsDescs.OperandInfo[527] }, // Inst #687 = SNZ_D_PSEUDO + { 2, &MipsDescs.OperandInfo[525] }, // Inst #686 = SNZ_B_PSEUDO + { 3, &MipsDescs.OperandInfo[230] }, // Inst #685 = SNEMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #684 = SNEIMacro + { 3, &MipsDescs.OperandInfo[224] }, // Inst #683 = SLTUImm64 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #682 = SLTImm64 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #681 = SLEUImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #680 = SLEUImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #679 = SLEU + { 3, &MipsDescs.OperandInfo[224] }, // Inst #678 = SLEImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #677 = SLEImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #676 = SLE + { 3, &MipsDescs.OperandInfo[224] }, // Inst #675 = SGTUImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #674 = SGTUImm + { 3, &MipsDescs.OperandInfo[224] }, // Inst #673 = SGTImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #672 = SGTImm + { 3, &MipsDescs.OperandInfo[224] }, // Inst #671 = SGEUImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #670 = SGEUImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #669 = SGEU + { 3, &MipsDescs.OperandInfo[224] }, // Inst #668 = SGEImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #667 = SGEImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #666 = SGE + { 3, &MipsDescs.OperandInfo[230] }, // Inst #665 = SEQMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #664 = SEQIMacro + { 3, &MipsDescs.OperandInfo[522] }, // Inst #663 = SDivMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #662 = SDivIMacro + { 3, &MipsDescs.OperandInfo[312] }, // Inst #661 = SDMacro + { 3, &MipsDescs.OperandInfo[460] }, // Inst #660 = SDIV_MM_Pseudo + { 3, &MipsDescs.OperandInfo[519] }, // Inst #659 = SDC1_M1 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #658 = RetRA16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #657 = RetRA + { 3, &MipsDescs.OperandInfo[233] }, // Inst #656 = RORImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #655 = ROR + { 3, &MipsDescs.OperandInfo[233] }, // Inst #654 = ROLImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #653 = ROL + { 3, &MipsDescs.OperandInfo[460] }, // Inst #652 = PseudoUDIV + { 3, &MipsDescs.OperandInfo[516] }, // Inst #651 = PseudoTRUNC_W_S + { 3, &MipsDescs.OperandInfo[513] }, // Inst #650 = PseudoTRUNC_W_D32 + { 3, &MipsDescs.OperandInfo[510] }, // Inst #649 = PseudoTRUNC_W_D + { 3, &MipsDescs.OperandInfo[391] }, // Inst #648 = PseudoSUBU_NM + { 4, &MipsDescs.OperandInfo[506] }, // Inst #647 = PseudoSELECT_S + { 4, &MipsDescs.OperandInfo[502] }, // Inst #646 = PseudoSELECT_I64 + { 4, &MipsDescs.OperandInfo[498] }, // Inst #645 = PseudoSELECT_I + { 4, &MipsDescs.OperandInfo[494] }, // Inst #644 = PseudoSELECT_D64 + { 4, &MipsDescs.OperandInfo[490] }, // Inst #643 = PseudoSELECT_D32 + { 4, &MipsDescs.OperandInfo[486] }, // Inst #642 = PseudoSELECTFP_T_S + { 4, &MipsDescs.OperandInfo[482] }, // Inst #641 = PseudoSELECTFP_T_I64 + { 4, &MipsDescs.OperandInfo[478] }, // Inst #640 = PseudoSELECTFP_T_I + { 4, &MipsDescs.OperandInfo[474] }, // Inst #639 = PseudoSELECTFP_T_D64 + { 4, &MipsDescs.OperandInfo[470] }, // Inst #638 = PseudoSELECTFP_T_D32 + { 4, &MipsDescs.OperandInfo[486] }, // Inst #637 = PseudoSELECTFP_F_S + { 4, &MipsDescs.OperandInfo[482] }, // Inst #636 = PseudoSELECTFP_F_I64 + { 4, &MipsDescs.OperandInfo[478] }, // Inst #635 = PseudoSELECTFP_F_I + { 4, &MipsDescs.OperandInfo[474] }, // Inst #634 = PseudoSELECTFP_F_D64 + { 4, &MipsDescs.OperandInfo[470] }, // Inst #633 = PseudoSELECTFP_F_D32 + { 3, &MipsDescs.OperandInfo[460] }, // Inst #632 = PseudoSDIV + { 1, &MipsDescs.OperandInfo[311] }, // Inst #631 = PseudoReturnNM + { 1, &MipsDescs.OperandInfo[310] }, // Inst #630 = PseudoReturn64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #629 = PseudoReturn + { 4, &MipsDescs.OperandInfo[466] }, // Inst #628 = PseudoPICK_QB + { 4, &MipsDescs.OperandInfo[466] }, // Inst #627 = PseudoPICK_PH + { 3, &MipsDescs.OperandInfo[460] }, // Inst #626 = PseudoMULTu_MM + { 3, &MipsDescs.OperandInfo[460] }, // Inst #625 = PseudoMULTu + { 3, &MipsDescs.OperandInfo[460] }, // Inst #624 = PseudoMULT_MM + { 3, &MipsDescs.OperandInfo[460] }, // Inst #623 = PseudoMULT + { 3, &MipsDescs.OperandInfo[460] }, // Inst #622 = PseudoMTLOHI_MM + { 3, &MipsDescs.OperandInfo[463] }, // Inst #621 = PseudoMTLOHI_DSP + { 3, &MipsDescs.OperandInfo[433] }, // Inst #620 = PseudoMTLOHI64 + { 3, &MipsDescs.OperandInfo[460] }, // Inst #619 = PseudoMTLOHI + { 4, &MipsDescs.OperandInfo[452] }, // Inst #618 = PseudoMSUB_MM + { 4, &MipsDescs.OperandInfo[452] }, // Inst #617 = PseudoMSUBU_MM + { 4, &MipsDescs.OperandInfo[452] }, // Inst #616 = PseudoMSUBU + { 4, &MipsDescs.OperandInfo[452] }, // Inst #615 = PseudoMSUB + { 2, &MipsDescs.OperandInfo[456] }, // Inst #614 = PseudoMFLO_MM + { 2, &MipsDescs.OperandInfo[458] }, // Inst #613 = PseudoMFLO64 + { 2, &MipsDescs.OperandInfo[456] }, // Inst #612 = PseudoMFLO + { 2, &MipsDescs.OperandInfo[456] }, // Inst #611 = PseudoMFHI_MM + { 2, &MipsDescs.OperandInfo[458] }, // Inst #610 = PseudoMFHI64 + { 2, &MipsDescs.OperandInfo[456] }, // Inst #609 = PseudoMFHI + { 4, &MipsDescs.OperandInfo[452] }, // Inst #608 = PseudoMADD_MM + { 4, &MipsDescs.OperandInfo[452] }, // Inst #607 = PseudoMADDU_MM + { 4, &MipsDescs.OperandInfo[452] }, // Inst #606 = PseudoMADDU + { 4, &MipsDescs.OperandInfo[452] }, // Inst #605 = PseudoMADD + { 2, &MipsDescs.OperandInfo[450] }, // Inst #604 = PseudoLI_NM + { 2, &MipsDescs.OperandInfo[450] }, // Inst #603 = PseudoLA_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #602 = PseudoIndrectHazardBranchR6 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #601 = PseudoIndrectHazardBranch64R6 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #600 = PseudoIndirectHazardBranch64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #599 = PseudoIndirectHazardBranch + { 1, &MipsDescs.OperandInfo[189] }, // Inst #598 = PseudoIndirectBranch_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #597 = PseudoIndirectBranch_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #596 = PseudoIndirectBranchR6 + { 1, &MipsDescs.OperandInfo[311] }, // Inst #595 = PseudoIndirectBranchNM + { 1, &MipsDescs.OperandInfo[310] }, // Inst #594 = PseudoIndirectBranch64R6 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #593 = PseudoIndirectBranch64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #592 = PseudoIndirectBranch + { 7, &MipsDescs.OperandInfo[443] }, // Inst #591 = PseudoD_SELECT_I64 + { 7, &MipsDescs.OperandInfo[436] }, // Inst #590 = PseudoD_SELECT_I + { 3, &MipsDescs.OperandInfo[433] }, // Inst #589 = PseudoDUDIV + { 3, &MipsDescs.OperandInfo[433] }, // Inst #588 = PseudoDSDIV + { 3, &MipsDescs.OperandInfo[433] }, // Inst #587 = PseudoDMULTu + { 3, &MipsDescs.OperandInfo[433] }, // Inst #586 = PseudoDMULT + { 2, &MipsDescs.OperandInfo[414] }, // Inst #585 = PseudoCVT_S_W + { 2, &MipsDescs.OperandInfo[429] }, // Inst #584 = PseudoCVT_S_L + { 2, &MipsDescs.OperandInfo[431] }, // Inst #583 = PseudoCVT_D64_W + { 2, &MipsDescs.OperandInfo[429] }, // Inst #582 = PseudoCVT_D64_L + { 2, &MipsDescs.OperandInfo[427] }, // Inst #581 = PseudoCVT_D32_W + { 3, &MipsDescs.OperandInfo[424] }, // Inst #580 = PseudoCMP_LT_PH + { 3, &MipsDescs.OperandInfo[424] }, // Inst #579 = PseudoCMP_LE_PH + { 3, &MipsDescs.OperandInfo[424] }, // Inst #578 = PseudoCMP_EQ_PH + { 3, &MipsDescs.OperandInfo[424] }, // Inst #577 = PseudoCMPU_LT_QB + { 3, &MipsDescs.OperandInfo[424] }, // Inst #576 = PseudoCMPU_LE_QB + { 3, &MipsDescs.OperandInfo[424] }, // Inst #575 = PseudoCMPU_EQ_QB + { 3, &MipsDescs.OperandInfo[391] }, // Inst #574 = PseudoANDI_NM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #573 = PseudoADDIU_NM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #572 = OR_V_W_PSEUDO + { 3, &MipsDescs.OperandInfo[149] }, // Inst #571 = OR_V_H_PSEUDO + { 3, &MipsDescs.OperandInfo[146] }, // Inst #570 = OR_V_D_PSEUDO + { 3, &MipsDescs.OperandInfo[152] }, // Inst #569 = NOR_V_W_PSEUDO + { 3, &MipsDescs.OperandInfo[149] }, // Inst #568 = NOR_V_H_PSEUDO + { 3, &MipsDescs.OperandInfo[146] }, // Inst #567 = NOR_V_D_PSEUDO + { 3, &MipsDescs.OperandInfo[224] }, // Inst #566 = NORImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #565 = NORImm + { 0, &MipsDescs.OperandInfo[1] }, // Inst #564 = NOP + { 3, &MipsDescs.OperandInfo[421] }, // Inst #563 = MultuRxRyRz16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #562 = MultuRxRy16 + { 3, &MipsDescs.OperandInfo[421] }, // Inst #561 = MultRxRyRz16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #560 = MultRxRy16 + { 1, &MipsDescs.OperandInfo[182] }, // Inst #559 = MUSTTAILCALL_NM + { 1, &MipsDescs.OperandInfo[418] }, // Inst #558 = MUSTTAILCALLREG_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #557 = MULOUMacro + { 3, &MipsDescs.OperandInfo[230] }, // Inst #556 = MULOMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #555 = MULImmMacro + { 2, &MipsDescs.OperandInfo[406] }, // Inst #554 = MTTLO_NM + { 2, &MipsDescs.OperandInfo[404] }, // Inst #553 = MTTLO + { 2, &MipsDescs.OperandInfo[406] }, // Inst #552 = MTTHI_NM + { 2, &MipsDescs.OperandInfo[404] }, // Inst #551 = MTTHI + { 2, &MipsDescs.OperandInfo[414] }, // Inst #550 = MTTHC1 + { 2, &MipsDescs.OperandInfo[416] }, // Inst #549 = MTTGPR_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #548 = MTTGPR + { 1, &MipsDescs.OperandInfo[311] }, // Inst #547 = MTTDSP_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #546 = MTTDSP + { 2, &MipsDescs.OperandInfo[414] }, // Inst #545 = MTTC1 + { 3, &MipsDescs.OperandInfo[411] }, // Inst #544 = MTTC0_NM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #543 = MTTC0 + { 2, &MipsDescs.OperandInfo[406] }, // Inst #542 = MTTACX_NM + { 2, &MipsDescs.OperandInfo[404] }, // Inst #541 = MTTACX + { 2, &MipsDescs.OperandInfo[402] }, // Inst #540 = MSA_FP_ROUND_W_PSEUDO + { 2, &MipsDescs.OperandInfo[400] }, // Inst #539 = MSA_FP_ROUND_D_PSEUDO + { 2, &MipsDescs.OperandInfo[398] }, // Inst #538 = MSA_FP_EXTEND_W_PSEUDO + { 2, &MipsDescs.OperandInfo[396] }, // Inst #537 = MSA_FP_EXTEND_D_PSEUDO + { 2, &MipsDescs.OperandInfo[394] }, // Inst #536 = MIPSeh_return64 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #535 = MIPSeh_return32 + { 2, &MipsDescs.OperandInfo[381] }, // Inst #534 = MFTLO_NM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #533 = MFTLO + { 2, &MipsDescs.OperandInfo[381] }, // Inst #532 = MFTHI_NM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #531 = MFTHI + { 2, &MipsDescs.OperandInfo[389] }, // Inst #530 = MFTHC1 + { 3, &MipsDescs.OperandInfo[391] }, // Inst #529 = MFTGPR_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #528 = MFTGPR + { 1, &MipsDescs.OperandInfo[311] }, // Inst #527 = MFTDSP_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #526 = MFTDSP + { 2, &MipsDescs.OperandInfo[389] }, // Inst #525 = MFTC1 + { 3, &MipsDescs.OperandInfo[386] }, // Inst #524 = MFTC0_NM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #523 = MFTC0 + { 2, &MipsDescs.OperandInfo[381] }, // Inst #522 = MFTACX_NM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #521 = MFTACX + { 3, &MipsDescs.OperandInfo[376] }, // Inst #520 = LwConstant32 + { 4, &MipsDescs.OperandInfo[372] }, // Inst #519 = LoadJumpTableOffset + { 2, &MipsDescs.OperandInfo[364] }, // Inst #518 = LoadImmSingleGPR + { 2, &MipsDescs.OperandInfo[370] }, // Inst #517 = LoadImmSingleFGR + { 2, &MipsDescs.OperandInfo[364] }, // Inst #516 = LoadImmDoubleGPR + { 2, &MipsDescs.OperandInfo[368] }, // Inst #515 = LoadImmDoubleFGR_32 + { 2, &MipsDescs.OperandInfo[366] }, // Inst #514 = LoadImmDoubleFGR + { 2, &MipsDescs.OperandInfo[359] }, // Inst #513 = LoadImm64 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #512 = LoadImm32 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #511 = LoadAddrReg64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #510 = LoadAddrReg32 + { 2, &MipsDescs.OperandInfo[359] }, // Inst #509 = LoadAddrImm64 + { 2, &MipsDescs.OperandInfo[357] }, // Inst #508 = LoadAddrImm32 + { 3, &MipsDescs.OperandInfo[354] }, // Inst #507 = LWM_MM + { 2, &MipsDescs.OperandInfo[352] }, // Inst #506 = LONG_BRANCH_LUi2Op_64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #505 = LONG_BRANCH_LUi2Op + { 3, &MipsDescs.OperandInfo[347] }, // Inst #504 = LONG_BRANCH_LUi + { 3, &MipsDescs.OperandInfo[344] }, // Inst #503 = LONG_BRANCH_DADDiu2Op + { 4, &MipsDescs.OperandInfo[340] }, // Inst #502 = LONG_BRANCH_DADDiu + { 3, &MipsDescs.OperandInfo[186] }, // Inst #501 = LONG_BRANCH_ADDiu2Op + { 4, &MipsDescs.OperandInfo[336] }, // Inst #500 = LONG_BRANCH_ADDiu + { 3, &MipsDescs.OperandInfo[333] }, // Inst #499 = LOAD_CCOND_DSP + { 3, &MipsDescs.OperandInfo[330] }, // Inst #498 = LOAD_ACC64DSP + { 3, &MipsDescs.OperandInfo[327] }, // Inst #497 = LOAD_ACC64 + { 3, &MipsDescs.OperandInfo[324] }, // Inst #496 = LOAD_ACC128 + { 3, &MipsDescs.OperandInfo[321] }, // Inst #495 = LD_F16 + { 3, &MipsDescs.OperandInfo[318] }, // Inst #494 = LDR_W + { 3, &MipsDescs.OperandInfo[315] }, // Inst #493 = LDR_D + { 3, &MipsDescs.OperandInfo[312] }, // Inst #492 = LDMacro + { 2, &MipsDescs.OperandInfo[140] }, // Inst #491 = JalTwoReg + { 1, &MipsDescs.OperandInfo[189] }, // Inst #490 = JalOneReg + { 1, &MipsDescs.OperandInfo[0] }, // Inst #489 = JAL_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #488 = JALRPseudo + { 1, &MipsDescs.OperandInfo[189] }, // Inst #487 = JALRHBPseudo + { 1, &MipsDescs.OperandInfo[310] }, // Inst #486 = JALRHB64Pseudo + { 1, &MipsDescs.OperandInfo[311] }, // Inst #485 = JALRCPseudo + { 1, &MipsDescs.OperandInfo[310] }, // Inst #484 = JALR64Pseudo + { 4, &MipsDescs.OperandInfo[306] }, // Inst #483 = INSERT_W_VIDX_PSEUDO + { 4, &MipsDescs.OperandInfo[302] }, // Inst #482 = INSERT_W_VIDX64_PSEUDO + { 4, &MipsDescs.OperandInfo[298] }, // Inst #481 = INSERT_H_VIDX_PSEUDO + { 4, &MipsDescs.OperandInfo[294] }, // Inst #480 = INSERT_H_VIDX64_PSEUDO + { 4, &MipsDescs.OperandInfo[290] }, // Inst #479 = INSERT_FW_VIDX_PSEUDO + { 4, &MipsDescs.OperandInfo[286] }, // Inst #478 = INSERT_FW_VIDX64_PSEUDO + { 4, &MipsDescs.OperandInfo[282] }, // Inst #477 = INSERT_FW_PSEUDO + { 4, &MipsDescs.OperandInfo[278] }, // Inst #476 = INSERT_FD_VIDX_PSEUDO + { 4, &MipsDescs.OperandInfo[274] }, // Inst #475 = INSERT_FD_VIDX64_PSEUDO + { 4, &MipsDescs.OperandInfo[270] }, // Inst #474 = INSERT_FD_PSEUDO + { 4, &MipsDescs.OperandInfo[266] }, // Inst #473 = INSERT_D_VIDX_PSEUDO + { 4, &MipsDescs.OperandInfo[262] }, // Inst #472 = INSERT_D_VIDX64_PSEUDO + { 4, &MipsDescs.OperandInfo[258] }, // Inst #471 = INSERT_B_VIDX_PSEUDO + { 4, &MipsDescs.OperandInfo[254] }, // Inst #470 = INSERT_B_VIDX64_PSEUDO + { 4, &MipsDescs.OperandInfo[250] }, // Inst #469 = GotPrologue16 + { 2, &MipsDescs.OperandInfo[248] }, // Inst #468 = FILL_FW_PSEUDO + { 2, &MipsDescs.OperandInfo[246] }, // Inst #467 = FILL_FD_PSEUDO + { 2, &MipsDescs.OperandInfo[244] }, // Inst #466 = FEXP2_W_1_PSEUDO + { 2, &MipsDescs.OperandInfo[242] }, // Inst #465 = FEXP2_D_1_PSEUDO + { 2, &MipsDescs.OperandInfo[244] }, // Inst #464 = FABS_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #463 = FABS_D + { 3, &MipsDescs.OperandInfo[239] }, // Inst #462 = ExtractElementF64_64 + { 3, &MipsDescs.OperandInfo[236] }, // Inst #461 = ExtractElementF64 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #460 = ERet + { 3, &MipsDescs.OperandInfo[227] }, // Inst #459 = DURemMacro + { 3, &MipsDescs.OperandInfo[224] }, // Inst #458 = DURemIMacro + { 3, &MipsDescs.OperandInfo[227] }, // Inst #457 = DUDivMacro + { 3, &MipsDescs.OperandInfo[224] }, // Inst #456 = DUDivIMacro + { 3, &MipsDescs.OperandInfo[227] }, // Inst #455 = DSRemMacro + { 3, &MipsDescs.OperandInfo[224] }, // Inst #454 = DSRemIMacro + { 3, &MipsDescs.OperandInfo[227] }, // Inst #453 = DSDivMacro + { 3, &MipsDescs.OperandInfo[224] }, // Inst #452 = DSDivIMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #451 = DRORImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #450 = DROR + { 3, &MipsDescs.OperandInfo[233] }, // Inst #449 = DROLImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #448 = DROL + { 3, &MipsDescs.OperandInfo[227] }, // Inst #447 = DMULOUMacro + { 3, &MipsDescs.OperandInfo[227] }, // Inst #446 = DMULOMacro + { 3, &MipsDescs.OperandInfo[227] }, // Inst #445 = DMULMacro + { 3, &MipsDescs.OperandInfo[224] }, // Inst #444 = DMULImmMacro + { 1, &MipsDescs.OperandInfo[0] }, // Inst #443 = Constant32 + { 2, &MipsDescs.OperandInfo[222] }, // Inst #442 = CTTC1 + { 3, &MipsDescs.OperandInfo[219] }, // Inst #441 = COPY_FW_PSEUDO + { 3, &MipsDescs.OperandInfo[216] }, // Inst #440 = COPY_FD_PSEUDO + { 3, &MipsDescs.OperandInfo[2] }, // Inst #439 = CONSTPOOL_ENTRY + { 2, &MipsDescs.OperandInfo[214] }, // Inst #438 = CFTC1 + { 3, &MipsDescs.OperandInfo[211] }, // Inst #437 = BuildPairF64_64 + { 3, &MipsDescs.OperandInfo[208] }, // Inst #436 = BuildPairF64 + { 3, &MipsDescs.OperandInfo[202] }, // Inst #435 = BtnezT8SltuX16 + { 3, &MipsDescs.OperandInfo[205] }, // Inst #434 = BtnezT8SltiuX16 + { 3, &MipsDescs.OperandInfo[205] }, // Inst #433 = BtnezT8SltiX16 + { 3, &MipsDescs.OperandInfo[202] }, // Inst #432 = BtnezT8SltX16 + { 3, &MipsDescs.OperandInfo[205] }, // Inst #431 = BtnezT8CmpiX16 + { 3, &MipsDescs.OperandInfo[202] }, // Inst #430 = BtnezT8CmpX16 + { 3, &MipsDescs.OperandInfo[202] }, // Inst #429 = BteqzT8SltuX16 + { 3, &MipsDescs.OperandInfo[205] }, // Inst #428 = BteqzT8SltiuX16 + { 3, &MipsDescs.OperandInfo[205] }, // Inst #427 = BteqzT8SltiX16 + { 3, &MipsDescs.OperandInfo[202] }, // Inst #426 = BteqzT8SltX16 + { 3, &MipsDescs.OperandInfo[205] }, // Inst #425 = BteqzT8CmpiX16 + { 3, &MipsDescs.OperandInfo[202] }, // Inst #424 = BteqzT8CmpX16 + { 3, &MipsDescs.OperandInfo[183] }, // Inst #423 = BneImm + { 3, &MipsDescs.OperandInfo[183] }, // Inst #422 = BeqImm + { 1, &MipsDescs.OperandInfo[182] }, // Inst #421 = B_MM_Pseudo + { 1, &MipsDescs.OperandInfo[182] }, // Inst #420 = B_MMR6_Pseudo + { 1, &MipsDescs.OperandInfo[182] }, // Inst #419 = B_MM + { 4, &MipsDescs.OperandInfo[194] }, // Inst #418 = BSEL_W_PSEUDO + { 4, &MipsDescs.OperandInfo[198] }, // Inst #417 = BSEL_H_PSEUDO + { 4, &MipsDescs.OperandInfo[194] }, // Inst #416 = BSEL_FW_PSEUDO + { 4, &MipsDescs.OperandInfo[190] }, // Inst #415 = BSEL_FD_PSEUDO + { 4, &MipsDescs.OperandInfo[190] }, // Inst #414 = BSEL_D_PSEUDO + { 1, &MipsDescs.OperandInfo[189] }, // Inst #413 = BPOSGE32_PSEUDO + { 3, &MipsDescs.OperandInfo[183] }, // Inst #412 = BNELImmMacro + { 3, &MipsDescs.OperandInfo[183] }, // Inst #411 = BLTULImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #410 = BLTUL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #409 = BLTUImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #408 = BLTU + { 3, &MipsDescs.OperandInfo[183] }, // Inst #407 = BLTLImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #406 = BLTL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #405 = BLTImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #404 = BLT + { 3, &MipsDescs.OperandInfo[183] }, // Inst #403 = BLEULImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #402 = BLEUL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #401 = BLEUImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #400 = BLEU + { 3, &MipsDescs.OperandInfo[183] }, // Inst #399 = BLELImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #398 = BLEL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #397 = BLEImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #396 = BLE + { 3, &MipsDescs.OperandInfo[183] }, // Inst #395 = BGTULImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #394 = BGTUL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #393 = BGTUImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #392 = BGTU + { 3, &MipsDescs.OperandInfo[183] }, // Inst #391 = BGTLImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #390 = BGTL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #389 = BGTImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #388 = BGT + { 3, &MipsDescs.OperandInfo[183] }, // Inst #387 = BGEULImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #386 = BGEUL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #385 = BGEUImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #384 = BGEU + { 3, &MipsDescs.OperandInfo[183] }, // Inst #383 = BGELImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #382 = BGEL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #381 = BGEImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #380 = BGE + { 3, &MipsDescs.OperandInfo[183] }, // Inst #379 = BEQLImmMacro + { 1, &MipsDescs.OperandInfo[182] }, // Inst #378 = BAL_BR_MM + { 1, &MipsDescs.OperandInfo[182] }, // Inst #377 = BAL_BR + { 1, &MipsDescs.OperandInfo[182] }, // Inst #376 = B + { 6, &MipsDescs.OperandInfo[173] }, // Inst #375 = ATOMIC_SWAP_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #374 = ATOMIC_SWAP_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #373 = ATOMIC_SWAP_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #372 = ATOMIC_SWAP_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #371 = ATOMIC_SWAP_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #370 = ATOMIC_SWAP_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #369 = ATOMIC_SWAP_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #368 = ATOMIC_SWAP_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #367 = ATOMIC_LOAD_XOR_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #366 = ATOMIC_LOAD_XOR_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #365 = ATOMIC_LOAD_XOR_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #364 = ATOMIC_LOAD_XOR_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #363 = ATOMIC_LOAD_XOR_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #362 = ATOMIC_LOAD_XOR_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #361 = ATOMIC_LOAD_XOR_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #360 = ATOMIC_LOAD_XOR_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #359 = ATOMIC_LOAD_UMIN_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #358 = ATOMIC_LOAD_UMIN_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #357 = ATOMIC_LOAD_UMIN_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #356 = ATOMIC_LOAD_UMIN_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #355 = ATOMIC_LOAD_UMIN_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #354 = ATOMIC_LOAD_UMIN_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #353 = ATOMIC_LOAD_UMIN_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #352 = ATOMIC_LOAD_UMIN_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #351 = ATOMIC_LOAD_UMAX_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #350 = ATOMIC_LOAD_UMAX_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #349 = ATOMIC_LOAD_UMAX_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #348 = ATOMIC_LOAD_UMAX_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #347 = ATOMIC_LOAD_UMAX_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #346 = ATOMIC_LOAD_UMAX_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #345 = ATOMIC_LOAD_UMAX_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #344 = ATOMIC_LOAD_UMAX_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #343 = ATOMIC_LOAD_SUB_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #342 = ATOMIC_LOAD_SUB_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #341 = ATOMIC_LOAD_SUB_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #340 = ATOMIC_LOAD_SUB_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #339 = ATOMIC_LOAD_SUB_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #338 = ATOMIC_LOAD_SUB_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #337 = ATOMIC_LOAD_SUB_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #336 = ATOMIC_LOAD_SUB_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #335 = ATOMIC_LOAD_OR_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #334 = ATOMIC_LOAD_OR_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #333 = ATOMIC_LOAD_OR_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #332 = ATOMIC_LOAD_OR_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #331 = ATOMIC_LOAD_OR_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #330 = ATOMIC_LOAD_OR_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #329 = ATOMIC_LOAD_OR_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #328 = ATOMIC_LOAD_OR_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #327 = ATOMIC_LOAD_NAND_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #326 = ATOMIC_LOAD_NAND_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #325 = ATOMIC_LOAD_NAND_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #324 = ATOMIC_LOAD_NAND_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #323 = ATOMIC_LOAD_NAND_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #322 = ATOMIC_LOAD_NAND_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #321 = ATOMIC_LOAD_NAND_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #320 = ATOMIC_LOAD_NAND_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #319 = ATOMIC_LOAD_MIN_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #318 = ATOMIC_LOAD_MIN_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #317 = ATOMIC_LOAD_MIN_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #316 = ATOMIC_LOAD_MIN_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #315 = ATOMIC_LOAD_MIN_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #314 = ATOMIC_LOAD_MIN_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #313 = ATOMIC_LOAD_MIN_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #312 = ATOMIC_LOAD_MIN_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #311 = ATOMIC_LOAD_MAX_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #310 = ATOMIC_LOAD_MAX_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #309 = ATOMIC_LOAD_MAX_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #308 = ATOMIC_LOAD_MAX_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #307 = ATOMIC_LOAD_MAX_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #306 = ATOMIC_LOAD_MAX_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #305 = ATOMIC_LOAD_MAX_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #304 = ATOMIC_LOAD_MAX_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #303 = ATOMIC_LOAD_AND_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #302 = ATOMIC_LOAD_AND_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #301 = ATOMIC_LOAD_AND_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #300 = ATOMIC_LOAD_AND_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #299 = ATOMIC_LOAD_AND_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #298 = ATOMIC_LOAD_AND_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #297 = ATOMIC_LOAD_AND_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #296 = ATOMIC_LOAD_AND_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #295 = ATOMIC_LOAD_ADD_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #294 = ATOMIC_LOAD_ADD_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #293 = ATOMIC_LOAD_ADD_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #292 = ATOMIC_LOAD_ADD_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #291 = ATOMIC_LOAD_ADD_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #290 = ATOMIC_LOAD_ADD_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #289 = ATOMIC_LOAD_ADD_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #288 = ATOMIC_LOAD_ADD_I16 + { 7, &MipsDescs.OperandInfo[159] }, // Inst #287 = ATOMIC_CMP_SWAP_I8_POSTRA + { 4, &MipsDescs.OperandInfo[155] }, // Inst #286 = ATOMIC_CMP_SWAP_I8 + { 4, &MipsDescs.OperandInfo[166] }, // Inst #285 = ATOMIC_CMP_SWAP_I64_POSTRA + { 4, &MipsDescs.OperandInfo[166] }, // Inst #284 = ATOMIC_CMP_SWAP_I64 + { 4, &MipsDescs.OperandInfo[155] }, // Inst #283 = ATOMIC_CMP_SWAP_I32_POSTRA + { 4, &MipsDescs.OperandInfo[155] }, // Inst #282 = ATOMIC_CMP_SWAP_I32 + { 7, &MipsDescs.OperandInfo[159] }, // Inst #281 = ATOMIC_CMP_SWAP_I16_POSTRA + { 4, &MipsDescs.OperandInfo[155] }, // Inst #280 = ATOMIC_CMP_SWAP_I16 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #279 = AND_V_W_PSEUDO + { 3, &MipsDescs.OperandInfo[149] }, // Inst #278 = AND_V_H_PSEUDO + { 3, &MipsDescs.OperandInfo[146] }, // Inst #277 = AND_V_D_PSEUDO + { 4, &MipsDescs.OperandInfo[142] }, // Inst #276 = ALIGN_NM + { 2, &MipsDescs.OperandInfo[21] }, // Inst #275 = ADJCALLSTACKUP_NM + { 2, &MipsDescs.OperandInfo[21] }, // Inst #274 = ADJCALLSTACKUP + { 2, &MipsDescs.OperandInfo[21] }, // Inst #273 = ADJCALLSTACKDOWN_NM + { 2, &MipsDescs.OperandInfo[21] }, // Inst #272 = ADJCALLSTACKDOWN + { 2, &MipsDescs.OperandInfo[140] }, // Inst #271 = ABSMacro + { 4, &MipsDescs.OperandInfo[136] }, // Inst #270 = G_UBFX + { 4, &MipsDescs.OperandInfo[136] }, // Inst #269 = G_SBFX + { 2, &MipsDescs.OperandInfo[56] }, // Inst #268 = G_VECREDUCE_UMIN + { 2, &MipsDescs.OperandInfo[56] }, // Inst #267 = G_VECREDUCE_UMAX + { 2, &MipsDescs.OperandInfo[56] }, // Inst #266 = G_VECREDUCE_SMIN + { 2, &MipsDescs.OperandInfo[56] }, // Inst #265 = G_VECREDUCE_SMAX + { 2, &MipsDescs.OperandInfo[56] }, // Inst #264 = G_VECREDUCE_XOR + { 2, &MipsDescs.OperandInfo[56] }, // Inst #263 = G_VECREDUCE_OR + { 2, &MipsDescs.OperandInfo[56] }, // Inst #262 = G_VECREDUCE_AND + { 2, &MipsDescs.OperandInfo[56] }, // Inst #261 = G_VECREDUCE_MUL + { 2, &MipsDescs.OperandInfo[56] }, // Inst #260 = G_VECREDUCE_ADD + { 2, &MipsDescs.OperandInfo[56] }, // Inst #259 = G_VECREDUCE_FMINIMUM + { 2, &MipsDescs.OperandInfo[56] }, // Inst #258 = G_VECREDUCE_FMAXIMUM + { 2, &MipsDescs.OperandInfo[56] }, // Inst #257 = G_VECREDUCE_FMIN + { 2, &MipsDescs.OperandInfo[56] }, // Inst #256 = G_VECREDUCE_FMAX + { 2, &MipsDescs.OperandInfo[56] }, // Inst #255 = G_VECREDUCE_FMUL + { 2, &MipsDescs.OperandInfo[56] }, // Inst #254 = G_VECREDUCE_FADD + { 3, &MipsDescs.OperandInfo[123] }, // Inst #253 = G_VECREDUCE_SEQ_FMUL + { 3, &MipsDescs.OperandInfo[123] }, // Inst #252 = G_VECREDUCE_SEQ_FADD + { 3, &MipsDescs.OperandInfo[53] }, // Inst #251 = G_BZERO + { 4, &MipsDescs.OperandInfo[132] }, // Inst #250 = G_MEMSET + { 4, &MipsDescs.OperandInfo[132] }, // Inst #249 = G_MEMMOVE + { 3, &MipsDescs.OperandInfo[123] }, // Inst #248 = G_MEMCPY_INLINE + { 4, &MipsDescs.OperandInfo[132] }, // Inst #247 = G_MEMCPY + { 2, &MipsDescs.OperandInfo[130] }, // Inst #246 = G_WRITE_REGISTER + { 2, &MipsDescs.OperandInfo[51] }, // Inst #245 = G_READ_REGISTER + { 3, &MipsDescs.OperandInfo[96] }, // Inst #244 = G_STRICT_FLDEXP + { 2, &MipsDescs.OperandInfo[62] }, // Inst #243 = G_STRICT_FSQRT + { 4, &MipsDescs.OperandInfo[46] }, // Inst #242 = G_STRICT_FMA + { 3, &MipsDescs.OperandInfo[43] }, // Inst #241 = G_STRICT_FREM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #240 = G_STRICT_FDIV + { 3, &MipsDescs.OperandInfo[43] }, // Inst #239 = G_STRICT_FMUL + { 3, &MipsDescs.OperandInfo[43] }, // Inst #238 = G_STRICT_FSUB + { 3, &MipsDescs.OperandInfo[43] }, // Inst #237 = G_STRICT_FADD + { 1, &MipsDescs.OperandInfo[50] }, // Inst #236 = G_STACKRESTORE + { 1, &MipsDescs.OperandInfo[50] }, // Inst #235 = G_STACKSAVE + { 3, &MipsDescs.OperandInfo[64] }, // Inst #234 = G_DYN_STACKALLOC + { 2, &MipsDescs.OperandInfo[51] }, // Inst #233 = G_JUMP_TABLE + { 2, &MipsDescs.OperandInfo[51] }, // Inst #232 = G_BLOCK_ADDR + { 2, &MipsDescs.OperandInfo[56] }, // Inst #231 = G_ADDRSPACE_CAST + { 2, &MipsDescs.OperandInfo[62] }, // Inst #230 = G_FNEARBYINT + { 2, &MipsDescs.OperandInfo[62] }, // Inst #229 = G_FRINT + { 2, &MipsDescs.OperandInfo[62] }, // Inst #228 = G_FFLOOR + { 2, &MipsDescs.OperandInfo[62] }, // Inst #227 = G_FSQRT + { 2, &MipsDescs.OperandInfo[62] }, // Inst #226 = G_FSIN + { 2, &MipsDescs.OperandInfo[62] }, // Inst #225 = G_FCOS + { 2, &MipsDescs.OperandInfo[62] }, // Inst #224 = G_FCEIL + { 2, &MipsDescs.OperandInfo[62] }, // Inst #223 = G_BITREVERSE + { 2, &MipsDescs.OperandInfo[62] }, // Inst #222 = G_BSWAP + { 2, &MipsDescs.OperandInfo[56] }, // Inst #221 = G_CTPOP + { 2, &MipsDescs.OperandInfo[56] }, // Inst #220 = G_CTLZ_ZERO_UNDEF + { 2, &MipsDescs.OperandInfo[56] }, // Inst #219 = G_CTLZ + { 2, &MipsDescs.OperandInfo[56] }, // Inst #218 = G_CTTZ_ZERO_UNDEF + { 2, &MipsDescs.OperandInfo[56] }, // Inst #217 = G_CTTZ + { 4, &MipsDescs.OperandInfo[126] }, // Inst #216 = G_SHUFFLE_VECTOR + { 3, &MipsDescs.OperandInfo[123] }, // Inst #215 = G_EXTRACT_VECTOR_ELT + { 4, &MipsDescs.OperandInfo[119] }, // Inst #214 = G_INSERT_VECTOR_ELT + { 3, &MipsDescs.OperandInfo[116] }, // Inst #213 = G_BRJT + { 1, &MipsDescs.OperandInfo[0] }, // Inst #212 = G_BR + { 2, &MipsDescs.OperandInfo[56] }, // Inst #211 = G_LLROUND + { 2, &MipsDescs.OperandInfo[56] }, // Inst #210 = G_LROUND + { 2, &MipsDescs.OperandInfo[62] }, // Inst #209 = G_ABS + { 3, &MipsDescs.OperandInfo[43] }, // Inst #208 = G_UMAX + { 3, &MipsDescs.OperandInfo[43] }, // Inst #207 = G_UMIN + { 3, &MipsDescs.OperandInfo[43] }, // Inst #206 = G_SMAX + { 3, &MipsDescs.OperandInfo[43] }, // Inst #205 = G_SMIN + { 3, &MipsDescs.OperandInfo[96] }, // Inst #204 = G_PTRMASK + { 3, &MipsDescs.OperandInfo[96] }, // Inst #203 = G_PTR_ADD + { 0, &MipsDescs.OperandInfo[1] }, // Inst #202 = G_RESET_FPMODE + { 1, &MipsDescs.OperandInfo[50] }, // Inst #201 = G_SET_FPMODE + { 1, &MipsDescs.OperandInfo[50] }, // Inst #200 = G_GET_FPMODE + { 0, &MipsDescs.OperandInfo[1] }, // Inst #199 = G_RESET_FPENV + { 1, &MipsDescs.OperandInfo[50] }, // Inst #198 = G_SET_FPENV + { 1, &MipsDescs.OperandInfo[50] }, // Inst #197 = G_GET_FPENV + { 3, &MipsDescs.OperandInfo[43] }, // Inst #196 = G_FMAXIMUM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #195 = G_FMINIMUM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #194 = G_FMAXNUM_IEEE + { 3, &MipsDescs.OperandInfo[43] }, // Inst #193 = G_FMINNUM_IEEE + { 3, &MipsDescs.OperandInfo[43] }, // Inst #192 = G_FMAXNUM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #191 = G_FMINNUM + { 2, &MipsDescs.OperandInfo[62] }, // Inst #190 = G_FCANONICALIZE + { 3, &MipsDescs.OperandInfo[93] }, // Inst #189 = G_IS_FPCLASS + { 3, &MipsDescs.OperandInfo[96] }, // Inst #188 = G_FCOPYSIGN + { 2, &MipsDescs.OperandInfo[62] }, // Inst #187 = G_FABS + { 2, &MipsDescs.OperandInfo[56] }, // Inst #186 = G_UITOFP + { 2, &MipsDescs.OperandInfo[56] }, // Inst #185 = G_SITOFP + { 2, &MipsDescs.OperandInfo[56] }, // Inst #184 = G_FPTOUI + { 2, &MipsDescs.OperandInfo[56] }, // Inst #183 = G_FPTOSI + { 2, &MipsDescs.OperandInfo[56] }, // Inst #182 = G_FPTRUNC + { 2, &MipsDescs.OperandInfo[56] }, // Inst #181 = G_FPEXT + { 2, &MipsDescs.OperandInfo[62] }, // Inst #180 = G_FNEG + { 3, &MipsDescs.OperandInfo[86] }, // Inst #179 = G_FFREXP + { 3, &MipsDescs.OperandInfo[96] }, // Inst #178 = G_FLDEXP + { 2, &MipsDescs.OperandInfo[62] }, // Inst #177 = G_FLOG10 + { 2, &MipsDescs.OperandInfo[62] }, // Inst #176 = G_FLOG2 + { 2, &MipsDescs.OperandInfo[62] }, // Inst #175 = G_FLOG + { 2, &MipsDescs.OperandInfo[62] }, // Inst #174 = G_FEXP10 + { 2, &MipsDescs.OperandInfo[62] }, // Inst #173 = G_FEXP2 + { 2, &MipsDescs.OperandInfo[62] }, // Inst #172 = G_FEXP + { 3, &MipsDescs.OperandInfo[96] }, // Inst #171 = G_FPOWI + { 3, &MipsDescs.OperandInfo[43] }, // Inst #170 = G_FPOW + { 3, &MipsDescs.OperandInfo[43] }, // Inst #169 = G_FREM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #168 = G_FDIV + { 4, &MipsDescs.OperandInfo[46] }, // Inst #167 = G_FMAD + { 4, &MipsDescs.OperandInfo[46] }, // Inst #166 = G_FMA + { 3, &MipsDescs.OperandInfo[43] }, // Inst #165 = G_FMUL + { 3, &MipsDescs.OperandInfo[43] }, // Inst #164 = G_FSUB + { 3, &MipsDescs.OperandInfo[43] }, // Inst #163 = G_FADD + { 4, &MipsDescs.OperandInfo[112] }, // Inst #162 = G_UDIVFIXSAT + { 4, &MipsDescs.OperandInfo[112] }, // Inst #161 = G_SDIVFIXSAT + { 4, &MipsDescs.OperandInfo[112] }, // Inst #160 = G_UDIVFIX + { 4, &MipsDescs.OperandInfo[112] }, // Inst #159 = G_SDIVFIX + { 4, &MipsDescs.OperandInfo[112] }, // Inst #158 = G_UMULFIXSAT + { 4, &MipsDescs.OperandInfo[112] }, // Inst #157 = G_SMULFIXSAT + { 4, &MipsDescs.OperandInfo[112] }, // Inst #156 = G_UMULFIX + { 4, &MipsDescs.OperandInfo[112] }, // Inst #155 = G_SMULFIX + { 3, &MipsDescs.OperandInfo[96] }, // Inst #154 = G_SSHLSAT + { 3, &MipsDescs.OperandInfo[96] }, // Inst #153 = G_USHLSAT + { 3, &MipsDescs.OperandInfo[43] }, // Inst #152 = G_SSUBSAT + { 3, &MipsDescs.OperandInfo[43] }, // Inst #151 = G_USUBSAT + { 3, &MipsDescs.OperandInfo[43] }, // Inst #150 = G_SADDSAT + { 3, &MipsDescs.OperandInfo[43] }, // Inst #149 = G_UADDSAT + { 3, &MipsDescs.OperandInfo[43] }, // Inst #148 = G_SMULH + { 3, &MipsDescs.OperandInfo[43] }, // Inst #147 = G_UMULH + { 4, &MipsDescs.OperandInfo[82] }, // Inst #146 = G_SMULO + { 4, &MipsDescs.OperandInfo[82] }, // Inst #145 = G_UMULO + { 5, &MipsDescs.OperandInfo[107] }, // Inst #144 = G_SSUBE + { 4, &MipsDescs.OperandInfo[82] }, // Inst #143 = G_SSUBO + { 5, &MipsDescs.OperandInfo[107] }, // Inst #142 = G_SADDE + { 4, &MipsDescs.OperandInfo[82] }, // Inst #141 = G_SADDO + { 5, &MipsDescs.OperandInfo[107] }, // Inst #140 = G_USUBE + { 4, &MipsDescs.OperandInfo[82] }, // Inst #139 = G_USUBO + { 5, &MipsDescs.OperandInfo[107] }, // Inst #138 = G_UADDE + { 4, &MipsDescs.OperandInfo[82] }, // Inst #137 = G_UADDO + { 4, &MipsDescs.OperandInfo[82] }, // Inst #136 = G_SELECT + { 4, &MipsDescs.OperandInfo[103] }, // Inst #135 = G_FCMP + { 4, &MipsDescs.OperandInfo[103] }, // Inst #134 = G_ICMP + { 3, &MipsDescs.OperandInfo[96] }, // Inst #133 = G_ROTL + { 3, &MipsDescs.OperandInfo[96] }, // Inst #132 = G_ROTR + { 4, &MipsDescs.OperandInfo[99] }, // Inst #131 = G_FSHR + { 4, &MipsDescs.OperandInfo[99] }, // Inst #130 = G_FSHL + { 3, &MipsDescs.OperandInfo[96] }, // Inst #129 = G_ASHR + { 3, &MipsDescs.OperandInfo[96] }, // Inst #128 = G_LSHR + { 3, &MipsDescs.OperandInfo[96] }, // Inst #127 = G_SHL + { 2, &MipsDescs.OperandInfo[56] }, // Inst #126 = G_ZEXT + { 3, &MipsDescs.OperandInfo[40] }, // Inst #125 = G_SEXT_INREG + { 2, &MipsDescs.OperandInfo[56] }, // Inst #124 = G_SEXT + { 3, &MipsDescs.OperandInfo[93] }, // Inst #123 = G_VAARG + { 1, &MipsDescs.OperandInfo[50] }, // Inst #122 = G_VASTART + { 2, &MipsDescs.OperandInfo[51] }, // Inst #121 = G_FCONSTANT + { 2, &MipsDescs.OperandInfo[51] }, // Inst #120 = G_CONSTANT + { 2, &MipsDescs.OperandInfo[56] }, // Inst #119 = G_TRUNC + { 2, &MipsDescs.OperandInfo[56] }, // Inst #118 = G_ANYEXT + { 1, &MipsDescs.OperandInfo[0] }, // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS + { 1, &MipsDescs.OperandInfo[0] }, // Inst #116 = G_INTRINSIC_CONVERGENT + { 1, &MipsDescs.OperandInfo[0] }, // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS + { 1, &MipsDescs.OperandInfo[0] }, // Inst #114 = G_INTRINSIC + { 0, &MipsDescs.OperandInfo[1] }, // Inst #113 = G_INVOKE_REGION_START + { 1, &MipsDescs.OperandInfo[50] }, // Inst #112 = G_BRINDIRECT + { 2, &MipsDescs.OperandInfo[51] }, // Inst #111 = G_BRCOND + { 4, &MipsDescs.OperandInfo[89] }, // Inst #110 = G_PREFETCH + { 2, &MipsDescs.OperandInfo[21] }, // Inst #109 = G_FENCE + { 3, &MipsDescs.OperandInfo[86] }, // Inst #108 = G_ATOMICRMW_UDEC_WRAP + { 3, &MipsDescs.OperandInfo[86] }, // Inst #107 = G_ATOMICRMW_UINC_WRAP + { 3, &MipsDescs.OperandInfo[86] }, // Inst #106 = G_ATOMICRMW_FMIN + { 3, &MipsDescs.OperandInfo[86] }, // Inst #105 = G_ATOMICRMW_FMAX + { 3, &MipsDescs.OperandInfo[86] }, // Inst #104 = G_ATOMICRMW_FSUB + { 3, &MipsDescs.OperandInfo[86] }, // Inst #103 = G_ATOMICRMW_FADD + { 3, &MipsDescs.OperandInfo[86] }, // Inst #102 = G_ATOMICRMW_UMIN + { 3, &MipsDescs.OperandInfo[86] }, // Inst #101 = G_ATOMICRMW_UMAX + { 3, &MipsDescs.OperandInfo[86] }, // Inst #100 = G_ATOMICRMW_MIN + { 3, &MipsDescs.OperandInfo[86] }, // Inst #99 = G_ATOMICRMW_MAX + { 3, &MipsDescs.OperandInfo[86] }, // Inst #98 = G_ATOMICRMW_XOR + { 3, &MipsDescs.OperandInfo[86] }, // Inst #97 = G_ATOMICRMW_OR + { 3, &MipsDescs.OperandInfo[86] }, // Inst #96 = G_ATOMICRMW_NAND + { 3, &MipsDescs.OperandInfo[86] }, // Inst #95 = G_ATOMICRMW_AND + { 3, &MipsDescs.OperandInfo[86] }, // Inst #94 = G_ATOMICRMW_SUB + { 3, &MipsDescs.OperandInfo[86] }, // Inst #93 = G_ATOMICRMW_ADD + { 3, &MipsDescs.OperandInfo[86] }, // Inst #92 = G_ATOMICRMW_XCHG + { 4, &MipsDescs.OperandInfo[82] }, // Inst #91 = G_ATOMIC_CMPXCHG + { 5, &MipsDescs.OperandInfo[77] }, // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS + { 5, &MipsDescs.OperandInfo[72] }, // Inst #89 = G_INDEXED_STORE + { 2, &MipsDescs.OperandInfo[56] }, // Inst #88 = G_STORE + { 5, &MipsDescs.OperandInfo[67] }, // Inst #87 = G_INDEXED_ZEXTLOAD + { 5, &MipsDescs.OperandInfo[67] }, // Inst #86 = G_INDEXED_SEXTLOAD + { 5, &MipsDescs.OperandInfo[67] }, // Inst #85 = G_INDEXED_LOAD + { 2, &MipsDescs.OperandInfo[56] }, // Inst #84 = G_ZEXTLOAD + { 2, &MipsDescs.OperandInfo[56] }, // Inst #83 = G_SEXTLOAD + { 2, &MipsDescs.OperandInfo[56] }, // Inst #82 = G_LOAD + { 1, &MipsDescs.OperandInfo[50] }, // Inst #81 = G_READCYCLECOUNTER + { 2, &MipsDescs.OperandInfo[62] }, // Inst #80 = G_INTRINSIC_ROUNDEVEN + { 2, &MipsDescs.OperandInfo[56] }, // Inst #79 = G_INTRINSIC_LRINT + { 2, &MipsDescs.OperandInfo[62] }, // Inst #78 = G_INTRINSIC_ROUND + { 2, &MipsDescs.OperandInfo[62] }, // Inst #77 = G_INTRINSIC_TRUNC + { 3, &MipsDescs.OperandInfo[64] }, // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND + { 2, &MipsDescs.OperandInfo[62] }, // Inst #75 = G_CONSTANT_FOLD_BARRIER + { 2, &MipsDescs.OperandInfo[62] }, // Inst #74 = G_FREEZE + { 2, &MipsDescs.OperandInfo[56] }, // Inst #73 = G_BITCAST + { 2, &MipsDescs.OperandInfo[56] }, // Inst #72 = G_INTTOPTR + { 2, &MipsDescs.OperandInfo[56] }, // Inst #71 = G_PTRTOINT + { 2, &MipsDescs.OperandInfo[56] }, // Inst #70 = G_CONCAT_VECTORS + { 2, &MipsDescs.OperandInfo[56] }, // Inst #69 = G_BUILD_VECTOR_TRUNC + { 2, &MipsDescs.OperandInfo[56] }, // Inst #68 = G_BUILD_VECTOR + { 2, &MipsDescs.OperandInfo[56] }, // Inst #67 = G_MERGE_VALUES + { 4, &MipsDescs.OperandInfo[58] }, // Inst #66 = G_INSERT + { 2, &MipsDescs.OperandInfo[56] }, // Inst #65 = G_UNMERGE_VALUES + { 3, &MipsDescs.OperandInfo[53] }, // Inst #64 = G_EXTRACT + { 2, &MipsDescs.OperandInfo[51] }, // Inst #63 = G_CONSTANT_POOL + { 2, &MipsDescs.OperandInfo[51] }, // Inst #62 = G_GLOBAL_VALUE + { 2, &MipsDescs.OperandInfo[51] }, // Inst #61 = G_FRAME_INDEX + { 1, &MipsDescs.OperandInfo[50] }, // Inst #60 = G_PHI + { 1, &MipsDescs.OperandInfo[50] }, // Inst #59 = G_IMPLICIT_DEF + { 3, &MipsDescs.OperandInfo[43] }, // Inst #58 = G_XOR + { 3, &MipsDescs.OperandInfo[43] }, // Inst #57 = G_OR + { 3, &MipsDescs.OperandInfo[43] }, // Inst #56 = G_AND + { 4, &MipsDescs.OperandInfo[46] }, // Inst #55 = G_UDIVREM + { 4, &MipsDescs.OperandInfo[46] }, // Inst #54 = G_SDIVREM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #53 = G_UREM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #52 = G_SREM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #51 = G_UDIV + { 3, &MipsDescs.OperandInfo[43] }, // Inst #50 = G_SDIV + { 3, &MipsDescs.OperandInfo[43] }, // Inst #49 = G_MUL + { 3, &MipsDescs.OperandInfo[43] }, // Inst #48 = G_SUB + { 3, &MipsDescs.OperandInfo[43] }, // Inst #47 = G_ADD + { 3, &MipsDescs.OperandInfo[40] }, // Inst #46 = G_ASSERT_ALIGN + { 3, &MipsDescs.OperandInfo[40] }, // Inst #45 = G_ASSERT_ZEXT + { 3, &MipsDescs.OperandInfo[40] }, // Inst #44 = G_ASSERT_SEXT + { 1, &MipsDescs.OperandInfo[1] }, // Inst #43 = JUMP_TABLE_DEBUG_INFO + { 0, &MipsDescs.OperandInfo[1] }, // Inst #42 = MEMBARRIER + { 0, &MipsDescs.OperandInfo[1] }, // Inst #41 = ICALL_BRANCH_FUNNEL + { 3, &MipsDescs.OperandInfo[37] }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL + { 2, &MipsDescs.OperandInfo[35] }, // Inst #39 = PATCHABLE_EVENT_CALL + { 0, &MipsDescs.OperandInfo[1] }, // Inst #38 = PATCHABLE_TAIL_CALL + { 0, &MipsDescs.OperandInfo[1] }, // Inst #37 = PATCHABLE_FUNCTION_EXIT + { 0, &MipsDescs.OperandInfo[1] }, // Inst #36 = PATCHABLE_RET + { 0, &MipsDescs.OperandInfo[1] }, // Inst #35 = PATCHABLE_FUNCTION_ENTER + { 0, &MipsDescs.OperandInfo[1] }, // Inst #34 = PATCHABLE_OP + { 1, &MipsDescs.OperandInfo[0] }, // Inst #33 = FAULTING_OP + { 2, &MipsDescs.OperandInfo[33] }, // Inst #32 = LOCAL_ESCAPE + { 0, &MipsDescs.OperandInfo[1] }, // Inst #31 = STATEPOINT + { 3, &MipsDescs.OperandInfo[30] }, // Inst #30 = PREALLOCATED_ARG + { 1, &MipsDescs.OperandInfo[1] }, // Inst #29 = PREALLOCATED_SETUP + { 1, &MipsDescs.OperandInfo[29] }, // Inst #28 = LOAD_STACK_GUARD + { 6, &MipsDescs.OperandInfo[23] }, // Inst #27 = PATCHPOINT + { 0, &MipsDescs.OperandInfo[1] }, // Inst #26 = FENTRY_CALL + { 2, &MipsDescs.OperandInfo[21] }, // Inst #25 = STACKMAP + { 2, &MipsDescs.OperandInfo[19] }, // Inst #24 = ARITH_FENCE + { 4, &MipsDescs.OperandInfo[15] }, // Inst #23 = PSEUDO_PROBE + { 1, &MipsDescs.OperandInfo[1] }, // Inst #22 = LIFETIME_END + { 1, &MipsDescs.OperandInfo[1] }, // Inst #21 = LIFETIME_START + { 0, &MipsDescs.OperandInfo[1] }, // Inst #20 = BUNDLE + { 2, &MipsDescs.OperandInfo[13] }, // Inst #19 = COPY + { 2, &MipsDescs.OperandInfo[13] }, // Inst #18 = REG_SEQUENCE + { 1, &MipsDescs.OperandInfo[0] }, // Inst #17 = DBG_LABEL + { 0, &MipsDescs.OperandInfo[1] }, // Inst #16 = DBG_PHI + { 0, &MipsDescs.OperandInfo[1] }, // Inst #15 = DBG_INSTR_REF + { 0, &MipsDescs.OperandInfo[1] }, // Inst #14 = DBG_VALUE_LIST + { 0, &MipsDescs.OperandInfo[1] }, // Inst #13 = DBG_VALUE + { 3, &MipsDescs.OperandInfo[2] }, // Inst #12 = COPY_TO_REGCLASS + { 4, &MipsDescs.OperandInfo[9] }, // Inst #11 = SUBREG_TO_REG + { 1, &MipsDescs.OperandInfo[0] }, // Inst #10 = IMPLICIT_DEF + { 4, &MipsDescs.OperandInfo[5] }, // Inst #9 = INSERT_SUBREG + { 3, &MipsDescs.OperandInfo[2] }, // Inst #8 = EXTRACT_SUBREG + { 0, &MipsDescs.OperandInfo[1] }, // Inst #7 = KILL + { 1, &MipsDescs.OperandInfo[1] }, // Inst #6 = ANNOTATION_LABEL + { 1, &MipsDescs.OperandInfo[1] }, // Inst #5 = GC_LABEL + { 1, &MipsDescs.OperandInfo[1] }, // Inst #4 = EH_LABEL + { 1, &MipsDescs.OperandInfo[1] }, // Inst #3 = CFI_INSTRUCTION + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2 = INLINEASM_BR + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1 = INLINEASM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #0 = PHI + }, { + /* 0 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 1 */ + /* 1 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 2 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 5 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 9 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 13 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 15 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 19 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, + /* 21 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 23 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 29 */ { 0, 0|(1<, 2013-2019 */ - - #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { Mips_NoRegister, Mips_AT = 1, - Mips_DSPCCond = 2, - Mips_DSPCarry = 3, - Mips_DSPEFI = 4, - Mips_DSPOutFlag = 5, - Mips_DSPPos = 6, - Mips_DSPSCount = 7, - Mips_FP = 8, - Mips_GP = 9, - Mips_MSAAccess = 10, - Mips_MSACSR = 11, - Mips_MSAIR = 12, - Mips_MSAMap = 13, - Mips_MSAModify = 14, - Mips_MSARequest = 15, - Mips_MSASave = 16, - Mips_MSAUnmap = 17, - Mips_PC = 18, - Mips_RA = 19, - Mips_SP = 20, - Mips_ZERO = 21, - Mips_A0 = 22, - Mips_A1 = 23, - Mips_A2 = 24, - Mips_A3 = 25, - Mips_AC0 = 26, - Mips_AC1 = 27, - Mips_AC2 = 28, - Mips_AC3 = 29, - Mips_AT_64 = 30, - Mips_CC0 = 31, - Mips_CC1 = 32, - Mips_CC2 = 33, - Mips_CC3 = 34, - Mips_CC4 = 35, - Mips_CC5 = 36, - Mips_CC6 = 37, - Mips_CC7 = 38, - Mips_COP20 = 39, - Mips_COP21 = 40, - Mips_COP22 = 41, - Mips_COP23 = 42, - Mips_COP24 = 43, - Mips_COP25 = 44, - Mips_COP26 = 45, - Mips_COP27 = 46, - Mips_COP28 = 47, - Mips_COP29 = 48, - Mips_COP30 = 49, - Mips_COP31 = 50, - Mips_COP32 = 51, - Mips_COP33 = 52, - Mips_COP34 = 53, - Mips_COP35 = 54, - Mips_COP36 = 55, - Mips_COP37 = 56, - Mips_COP38 = 57, - Mips_COP39 = 58, - Mips_COP210 = 59, - Mips_COP211 = 60, - Mips_COP212 = 61, - Mips_COP213 = 62, - Mips_COP214 = 63, - Mips_COP215 = 64, - Mips_COP216 = 65, - Mips_COP217 = 66, - Mips_COP218 = 67, - Mips_COP219 = 68, - Mips_COP220 = 69, - Mips_COP221 = 70, - Mips_COP222 = 71, - Mips_COP223 = 72, - Mips_COP224 = 73, - Mips_COP225 = 74, - Mips_COP226 = 75, - Mips_COP227 = 76, - Mips_COP228 = 77, - Mips_COP229 = 78, - Mips_COP230 = 79, - Mips_COP231 = 80, - Mips_COP310 = 81, - Mips_COP311 = 82, - Mips_COP312 = 83, - Mips_COP313 = 84, - Mips_COP314 = 85, - Mips_COP315 = 86, - Mips_COP316 = 87, - Mips_COP317 = 88, - Mips_COP318 = 89, - Mips_COP319 = 90, - Mips_COP320 = 91, - Mips_COP321 = 92, - Mips_COP322 = 93, - Mips_COP323 = 94, - Mips_COP324 = 95, - Mips_COP325 = 96, - Mips_COP326 = 97, - Mips_COP327 = 98, - Mips_COP328 = 99, - Mips_COP329 = 100, - Mips_COP330 = 101, - Mips_COP331 = 102, - Mips_D0 = 103, - Mips_D1 = 104, - Mips_D2 = 105, - Mips_D3 = 106, - Mips_D4 = 107, - Mips_D5 = 108, - Mips_D6 = 109, - Mips_D7 = 110, - Mips_D8 = 111, - Mips_D9 = 112, - Mips_D10 = 113, - Mips_D11 = 114, - Mips_D12 = 115, - Mips_D13 = 116, - Mips_D14 = 117, - Mips_D15 = 118, - Mips_DSPOutFlag20 = 119, - Mips_DSPOutFlag21 = 120, - Mips_DSPOutFlag22 = 121, - Mips_DSPOutFlag23 = 122, - Mips_F0 = 123, - Mips_F1 = 124, - Mips_F2 = 125, - Mips_F3 = 126, - Mips_F4 = 127, - Mips_F5 = 128, - Mips_F6 = 129, - Mips_F7 = 130, - Mips_F8 = 131, - Mips_F9 = 132, - Mips_F10 = 133, - Mips_F11 = 134, - Mips_F12 = 135, - Mips_F13 = 136, - Mips_F14 = 137, - Mips_F15 = 138, - Mips_F16 = 139, - Mips_F17 = 140, - Mips_F18 = 141, - Mips_F19 = 142, - Mips_F20 = 143, - Mips_F21 = 144, - Mips_F22 = 145, - Mips_F23 = 146, - Mips_F24 = 147, - Mips_F25 = 148, - Mips_F26 = 149, - Mips_F27 = 150, - Mips_F28 = 151, - Mips_F29 = 152, - Mips_F30 = 153, - Mips_F31 = 154, - Mips_FCC0 = 155, - Mips_FCC1 = 156, - Mips_FCC2 = 157, - Mips_FCC3 = 158, - Mips_FCC4 = 159, - Mips_FCC5 = 160, - Mips_FCC6 = 161, - Mips_FCC7 = 162, - Mips_FCR0 = 163, - Mips_FCR1 = 164, - Mips_FCR2 = 165, - Mips_FCR3 = 166, - Mips_FCR4 = 167, - Mips_FCR5 = 168, - Mips_FCR6 = 169, - Mips_FCR7 = 170, - Mips_FCR8 = 171, - Mips_FCR9 = 172, - Mips_FCR10 = 173, - Mips_FCR11 = 174, - Mips_FCR12 = 175, - Mips_FCR13 = 176, - Mips_FCR14 = 177, - Mips_FCR15 = 178, - Mips_FCR16 = 179, - Mips_FCR17 = 180, - Mips_FCR18 = 181, - Mips_FCR19 = 182, - Mips_FCR20 = 183, - Mips_FCR21 = 184, - Mips_FCR22 = 185, - Mips_FCR23 = 186, - Mips_FCR24 = 187, - Mips_FCR25 = 188, - Mips_FCR26 = 189, - Mips_FCR27 = 190, - Mips_FCR28 = 191, - Mips_FCR29 = 192, - Mips_FCR30 = 193, - Mips_FCR31 = 194, - Mips_FP_64 = 195, - Mips_F_HI0 = 196, - Mips_F_HI1 = 197, - Mips_F_HI2 = 198, - Mips_F_HI3 = 199, - Mips_F_HI4 = 200, - Mips_F_HI5 = 201, - Mips_F_HI6 = 202, - Mips_F_HI7 = 203, - Mips_F_HI8 = 204, - Mips_F_HI9 = 205, - Mips_F_HI10 = 206, - Mips_F_HI11 = 207, - Mips_F_HI12 = 208, - Mips_F_HI13 = 209, - Mips_F_HI14 = 210, - Mips_F_HI15 = 211, - Mips_F_HI16 = 212, - Mips_F_HI17 = 213, - Mips_F_HI18 = 214, - Mips_F_HI19 = 215, - Mips_F_HI20 = 216, - Mips_F_HI21 = 217, - Mips_F_HI22 = 218, - Mips_F_HI23 = 219, - Mips_F_HI24 = 220, - Mips_F_HI25 = 221, - Mips_F_HI26 = 222, - Mips_F_HI27 = 223, - Mips_F_HI28 = 224, - Mips_F_HI29 = 225, - Mips_F_HI30 = 226, - Mips_F_HI31 = 227, - Mips_GP_64 = 228, - Mips_HI0 = 229, - Mips_HI1 = 230, - Mips_HI2 = 231, - Mips_HI3 = 232, - Mips_HWR0 = 233, - Mips_HWR1 = 234, - Mips_HWR2 = 235, - Mips_HWR3 = 236, - Mips_HWR4 = 237, - Mips_HWR5 = 238, - Mips_HWR6 = 239, - Mips_HWR7 = 240, - Mips_HWR8 = 241, - Mips_HWR9 = 242, - Mips_HWR10 = 243, - Mips_HWR11 = 244, - Mips_HWR12 = 245, - Mips_HWR13 = 246, - Mips_HWR14 = 247, - Mips_HWR15 = 248, - Mips_HWR16 = 249, - Mips_HWR17 = 250, - Mips_HWR18 = 251, - Mips_HWR19 = 252, - Mips_HWR20 = 253, - Mips_HWR21 = 254, - Mips_HWR22 = 255, - Mips_HWR23 = 256, - Mips_HWR24 = 257, - Mips_HWR25 = 258, - Mips_HWR26 = 259, - Mips_HWR27 = 260, - Mips_HWR28 = 261, - Mips_HWR29 = 262, - Mips_HWR30 = 263, - Mips_HWR31 = 264, - Mips_K0 = 265, - Mips_K1 = 266, - Mips_LO0 = 267, - Mips_LO1 = 268, - Mips_LO2 = 269, - Mips_LO3 = 270, - Mips_MPL0 = 271, - Mips_MPL1 = 272, - Mips_MPL2 = 273, - Mips_P0 = 274, - Mips_P1 = 275, - Mips_P2 = 276, - Mips_RA_64 = 277, - Mips_S0 = 278, - Mips_S1 = 279, - Mips_S2 = 280, - Mips_S3 = 281, - Mips_S4 = 282, - Mips_S5 = 283, - Mips_S6 = 284, - Mips_S7 = 285, - Mips_SP_64 = 286, - Mips_T0 = 287, - Mips_T1 = 288, - Mips_T2 = 289, - Mips_T3 = 290, - Mips_T4 = 291, - Mips_T5 = 292, - Mips_T6 = 293, - Mips_T7 = 294, - Mips_T8 = 295, - Mips_T9 = 296, - Mips_V0 = 297, - Mips_V1 = 298, - Mips_W0 = 299, - Mips_W1 = 300, - Mips_W2 = 301, - Mips_W3 = 302, - Mips_W4 = 303, - Mips_W5 = 304, - Mips_W6 = 305, - Mips_W7 = 306, - Mips_W8 = 307, - Mips_W9 = 308, - Mips_W10 = 309, - Mips_W11 = 310, - Mips_W12 = 311, - Mips_W13 = 312, - Mips_W14 = 313, - Mips_W15 = 314, - Mips_W16 = 315, - Mips_W17 = 316, - Mips_W18 = 317, - Mips_W19 = 318, - Mips_W20 = 319, - Mips_W21 = 320, - Mips_W22 = 321, - Mips_W23 = 322, - Mips_W24 = 323, - Mips_W25 = 324, - Mips_W26 = 325, - Mips_W27 = 326, - Mips_W28 = 327, - Mips_W29 = 328, - Mips_W30 = 329, - Mips_W31 = 330, - Mips_ZERO_64 = 331, - Mips_A0_64 = 332, - Mips_A1_64 = 333, - Mips_A2_64 = 334, - Mips_A3_64 = 335, - Mips_AC0_64 = 336, - Mips_D0_64 = 337, - Mips_D1_64 = 338, - Mips_D2_64 = 339, - Mips_D3_64 = 340, - Mips_D4_64 = 341, - Mips_D5_64 = 342, - Mips_D6_64 = 343, - Mips_D7_64 = 344, - Mips_D8_64 = 345, - Mips_D9_64 = 346, - Mips_D10_64 = 347, - Mips_D11_64 = 348, - Mips_D12_64 = 349, - Mips_D13_64 = 350, - Mips_D14_64 = 351, - Mips_D15_64 = 352, - Mips_D16_64 = 353, - Mips_D17_64 = 354, - Mips_D18_64 = 355, - Mips_D19_64 = 356, - Mips_D20_64 = 357, - Mips_D21_64 = 358, - Mips_D22_64 = 359, - Mips_D23_64 = 360, - Mips_D24_64 = 361, - Mips_D25_64 = 362, - Mips_D26_64 = 363, - Mips_D27_64 = 364, - Mips_D28_64 = 365, - Mips_D29_64 = 366, - Mips_D30_64 = 367, - Mips_D31_64 = 368, - Mips_DSPOutFlag16_19 = 369, - Mips_HI0_64 = 370, - Mips_K0_64 = 371, - Mips_K1_64 = 372, - Mips_LO0_64 = 373, - Mips_S0_64 = 374, - Mips_S1_64 = 375, - Mips_S2_64 = 376, - Mips_S3_64 = 377, - Mips_S4_64 = 378, - Mips_S5_64 = 379, - Mips_S6_64 = 380, - Mips_S7_64 = 381, - Mips_T0_64 = 382, - Mips_T1_64 = 383, - Mips_T2_64 = 384, - Mips_T3_64 = 385, - Mips_T4_64 = 386, - Mips_T5_64 = 387, - Mips_T6_64 = 388, - Mips_T7_64 = 389, - Mips_T8_64 = 390, - Mips_T9_64 = 391, - Mips_V0_64 = 392, - Mips_V1_64 = 393, - Mips_NUM_TARGET_REGS // 394 + Mips_AT_NM = 2, + Mips_DSPCCond = 3, + Mips_DSPCarry = 4, + Mips_DSPEFI = 5, + Mips_DSPOutFlag = 6, + Mips_DSPPos = 7, + Mips_DSPSCount = 8, + Mips_FP = 9, + Mips_FP_NM = 10, + Mips_GP = 11, + Mips_GP_NM = 12, + Mips_MSAAccess = 13, + Mips_MSACSR = 14, + Mips_MSAIR = 15, + Mips_MSAMap = 16, + Mips_MSAModify = 17, + Mips_MSARequest = 18, + Mips_MSASave = 19, + Mips_MSAUnmap = 20, + Mips_PC = 21, + Mips_RA = 22, + Mips_RA_NM = 23, + Mips_SP = 24, + Mips_SP_NM = 25, + Mips_ZERO = 26, + Mips_ZERO_NM = 27, + Mips_A0 = 28, + Mips_A1 = 29, + Mips_A2 = 30, + Mips_A3 = 31, + Mips_AC0 = 32, + Mips_AC1 = 33, + Mips_AC2 = 34, + Mips_AC3 = 35, + Mips_AT_64 = 36, + Mips_COP00 = 37, + Mips_COP01 = 38, + Mips_COP02 = 39, + Mips_COP03 = 40, + Mips_COP04 = 41, + Mips_COP05 = 42, + Mips_COP06 = 43, + Mips_COP07 = 44, + Mips_COP08 = 45, + Mips_COP09 = 46, + Mips_COP20 = 47, + Mips_COP21 = 48, + Mips_COP22 = 49, + Mips_COP23 = 50, + Mips_COP24 = 51, + Mips_COP25 = 52, + Mips_COP26 = 53, + Mips_COP27 = 54, + Mips_COP28 = 55, + Mips_COP29 = 56, + Mips_COP30 = 57, + Mips_COP31 = 58, + Mips_COP32 = 59, + Mips_COP33 = 60, + Mips_COP34 = 61, + Mips_COP35 = 62, + Mips_COP36 = 63, + Mips_COP37 = 64, + Mips_COP38 = 65, + Mips_COP39 = 66, + Mips_COP010 = 67, + Mips_COP011 = 68, + Mips_COP012 = 69, + Mips_COP013 = 70, + Mips_COP014 = 71, + Mips_COP015 = 72, + Mips_COP016 = 73, + Mips_COP017 = 74, + Mips_COP018 = 75, + Mips_COP019 = 76, + Mips_COP020 = 77, + Mips_COP021 = 78, + Mips_COP022 = 79, + Mips_COP023 = 80, + Mips_COP024 = 81, + Mips_COP025 = 82, + Mips_COP026 = 83, + Mips_COP027 = 84, + Mips_COP028 = 85, + Mips_COP029 = 86, + Mips_COP030 = 87, + Mips_COP031 = 88, + Mips_COP210 = 89, + Mips_COP211 = 90, + Mips_COP212 = 91, + Mips_COP213 = 92, + Mips_COP214 = 93, + Mips_COP215 = 94, + Mips_COP216 = 95, + Mips_COP217 = 96, + Mips_COP218 = 97, + Mips_COP219 = 98, + Mips_COP220 = 99, + Mips_COP221 = 100, + Mips_COP222 = 101, + Mips_COP223 = 102, + Mips_COP224 = 103, + Mips_COP225 = 104, + Mips_COP226 = 105, + Mips_COP227 = 106, + Mips_COP228 = 107, + Mips_COP229 = 108, + Mips_COP230 = 109, + Mips_COP231 = 110, + Mips_COP310 = 111, + Mips_COP311 = 112, + Mips_COP312 = 113, + Mips_COP313 = 114, + Mips_COP314 = 115, + Mips_COP315 = 116, + Mips_COP316 = 117, + Mips_COP317 = 118, + Mips_COP318 = 119, + Mips_COP319 = 120, + Mips_COP320 = 121, + Mips_COP321 = 122, + Mips_COP322 = 123, + Mips_COP323 = 124, + Mips_COP324 = 125, + Mips_COP325 = 126, + Mips_COP326 = 127, + Mips_COP327 = 128, + Mips_COP328 = 129, + Mips_COP329 = 130, + Mips_COP330 = 131, + Mips_COP331 = 132, + Mips_D0 = 133, + Mips_D1 = 134, + Mips_D2 = 135, + Mips_D3 = 136, + Mips_D4 = 137, + Mips_D5 = 138, + Mips_D6 = 139, + Mips_D7 = 140, + Mips_D8 = 141, + Mips_D9 = 142, + Mips_D10 = 143, + Mips_D11 = 144, + Mips_D12 = 145, + Mips_D13 = 146, + Mips_D14 = 147, + Mips_D15 = 148, + Mips_DSPOutFlag20 = 149, + Mips_DSPOutFlag21 = 150, + Mips_DSPOutFlag22 = 151, + Mips_DSPOutFlag23 = 152, + Mips_F0 = 153, + Mips_F1 = 154, + Mips_F2 = 155, + Mips_F3 = 156, + Mips_F4 = 157, + Mips_F5 = 158, + Mips_F6 = 159, + Mips_F7 = 160, + Mips_F8 = 161, + Mips_F9 = 162, + Mips_F10 = 163, + Mips_F11 = 164, + Mips_F12 = 165, + Mips_F13 = 166, + Mips_F14 = 167, + Mips_F15 = 168, + Mips_F16 = 169, + Mips_F17 = 170, + Mips_F18 = 171, + Mips_F19 = 172, + Mips_F20 = 173, + Mips_F21 = 174, + Mips_F22 = 175, + Mips_F23 = 176, + Mips_F24 = 177, + Mips_F25 = 178, + Mips_F26 = 179, + Mips_F27 = 180, + Mips_F28 = 181, + Mips_F29 = 182, + Mips_F30 = 183, + Mips_F31 = 184, + Mips_FCC0 = 185, + Mips_FCC1 = 186, + Mips_FCC2 = 187, + Mips_FCC3 = 188, + Mips_FCC4 = 189, + Mips_FCC5 = 190, + Mips_FCC6 = 191, + Mips_FCC7 = 192, + Mips_FCR0 = 193, + Mips_FCR1 = 194, + Mips_FCR2 = 195, + Mips_FCR3 = 196, + Mips_FCR4 = 197, + Mips_FCR5 = 198, + Mips_FCR6 = 199, + Mips_FCR7 = 200, + Mips_FCR8 = 201, + Mips_FCR9 = 202, + Mips_FCR10 = 203, + Mips_FCR11 = 204, + Mips_FCR12 = 205, + Mips_FCR13 = 206, + Mips_FCR14 = 207, + Mips_FCR15 = 208, + Mips_FCR16 = 209, + Mips_FCR17 = 210, + Mips_FCR18 = 211, + Mips_FCR19 = 212, + Mips_FCR20 = 213, + Mips_FCR21 = 214, + Mips_FCR22 = 215, + Mips_FCR23 = 216, + Mips_FCR24 = 217, + Mips_FCR25 = 218, + Mips_FCR26 = 219, + Mips_FCR27 = 220, + Mips_FCR28 = 221, + Mips_FCR29 = 222, + Mips_FCR30 = 223, + Mips_FCR31 = 224, + Mips_FP_64 = 225, + Mips_F_HI0 = 226, + Mips_F_HI1 = 227, + Mips_F_HI2 = 228, + Mips_F_HI3 = 229, + Mips_F_HI4 = 230, + Mips_F_HI5 = 231, + Mips_F_HI6 = 232, + Mips_F_HI7 = 233, + Mips_F_HI8 = 234, + Mips_F_HI9 = 235, + Mips_F_HI10 = 236, + Mips_F_HI11 = 237, + Mips_F_HI12 = 238, + Mips_F_HI13 = 239, + Mips_F_HI14 = 240, + Mips_F_HI15 = 241, + Mips_F_HI16 = 242, + Mips_F_HI17 = 243, + Mips_F_HI18 = 244, + Mips_F_HI19 = 245, + Mips_F_HI20 = 246, + Mips_F_HI21 = 247, + Mips_F_HI22 = 248, + Mips_F_HI23 = 249, + Mips_F_HI24 = 250, + Mips_F_HI25 = 251, + Mips_F_HI26 = 252, + Mips_F_HI27 = 253, + Mips_F_HI28 = 254, + Mips_F_HI29 = 255, + Mips_F_HI30 = 256, + Mips_F_HI31 = 257, + Mips_GP_64 = 258, + Mips_HI0 = 259, + Mips_HI1 = 260, + Mips_HI2 = 261, + Mips_HI3 = 262, + Mips_HWR0 = 263, + Mips_HWR1 = 264, + Mips_HWR2 = 265, + Mips_HWR3 = 266, + Mips_HWR4 = 267, + Mips_HWR5 = 268, + Mips_HWR6 = 269, + Mips_HWR7 = 270, + Mips_HWR8 = 271, + Mips_HWR9 = 272, + Mips_HWR10 = 273, + Mips_HWR11 = 274, + Mips_HWR12 = 275, + Mips_HWR13 = 276, + Mips_HWR14 = 277, + Mips_HWR15 = 278, + Mips_HWR16 = 279, + Mips_HWR17 = 280, + Mips_HWR18 = 281, + Mips_HWR19 = 282, + Mips_HWR20 = 283, + Mips_HWR21 = 284, + Mips_HWR22 = 285, + Mips_HWR23 = 286, + Mips_HWR24 = 287, + Mips_HWR25 = 288, + Mips_HWR26 = 289, + Mips_HWR27 = 290, + Mips_HWR28 = 291, + Mips_HWR29 = 292, + Mips_HWR30 = 293, + Mips_HWR31 = 294, + Mips_K0 = 295, + Mips_K1 = 296, + Mips_LO0 = 297, + Mips_LO1 = 298, + Mips_LO2 = 299, + Mips_LO3 = 300, + Mips_MPL0 = 301, + Mips_MPL1 = 302, + Mips_MPL2 = 303, + Mips_MSA8 = 304, + Mips_MSA9 = 305, + Mips_MSA10 = 306, + Mips_MSA11 = 307, + Mips_MSA12 = 308, + Mips_MSA13 = 309, + Mips_MSA14 = 310, + Mips_MSA15 = 311, + Mips_MSA16 = 312, + Mips_MSA17 = 313, + Mips_MSA18 = 314, + Mips_MSA19 = 315, + Mips_MSA20 = 316, + Mips_MSA21 = 317, + Mips_MSA22 = 318, + Mips_MSA23 = 319, + Mips_MSA24 = 320, + Mips_MSA25 = 321, + Mips_MSA26 = 322, + Mips_MSA27 = 323, + Mips_MSA28 = 324, + Mips_MSA29 = 325, + Mips_MSA30 = 326, + Mips_MSA31 = 327, + Mips_P0 = 328, + Mips_P1 = 329, + Mips_P2 = 330, + Mips_RA_64 = 331, + Mips_S0 = 332, + Mips_S1 = 333, + Mips_S2 = 334, + Mips_S3 = 335, + Mips_S4 = 336, + Mips_S5 = 337, + Mips_S6 = 338, + Mips_S7 = 339, + Mips_SP_64 = 340, + Mips_T0 = 341, + Mips_T1 = 342, + Mips_T2 = 343, + Mips_T3 = 344, + Mips_T4 = 345, + Mips_T5 = 346, + Mips_T6 = 347, + Mips_T7 = 348, + Mips_T8 = 349, + Mips_T9 = 350, + Mips_V0 = 351, + Mips_V1 = 352, + Mips_W0 = 353, + Mips_W1 = 354, + Mips_W2 = 355, + Mips_W3 = 356, + Mips_W4 = 357, + Mips_W5 = 358, + Mips_W6 = 359, + Mips_W7 = 360, + Mips_W8 = 361, + Mips_W9 = 362, + Mips_W10 = 363, + Mips_W11 = 364, + Mips_W12 = 365, + Mips_W13 = 366, + Mips_W14 = 367, + Mips_W15 = 368, + Mips_W16 = 369, + Mips_W17 = 370, + Mips_W18 = 371, + Mips_W19 = 372, + Mips_W20 = 373, + Mips_W21 = 374, + Mips_W22 = 375, + Mips_W23 = 376, + Mips_W24 = 377, + Mips_W25 = 378, + Mips_W26 = 379, + Mips_W27 = 380, + Mips_W28 = 381, + Mips_W29 = 382, + Mips_W30 = 383, + Mips_W31 = 384, + Mips_ZERO_64 = 385, + Mips_A0_NM = 386, + Mips_A1_NM = 387, + Mips_A2_NM = 388, + Mips_A3_NM = 389, + Mips_A4_NM = 390, + Mips_A5_NM = 391, + Mips_A6_NM = 392, + Mips_A7_NM = 393, + Mips_COP0Sel_BADINST = 394, + Mips_COP0Sel_BADINSTRP = 395, + Mips_COP0Sel_BADINSTRX = 396, + Mips_COP0Sel_BADVADDR = 397, + Mips_COP0Sel_BEVVA = 398, + Mips_COP0Sel_CACHEERR = 399, + Mips_COP0Sel_CAUSE = 400, + Mips_COP0Sel_CDMMBASE = 401, + Mips_COP0Sel_CMGCRBASE = 402, + Mips_COP0Sel_COMPARE = 403, + Mips_COP0Sel_CONFIG = 404, + Mips_COP0Sel_CONTEXT = 405, + Mips_COP0Sel_CONTEXTCONFIG = 406, + Mips_COP0Sel_COUNT = 407, + Mips_COP0Sel_DDATAHI = 408, + Mips_COP0Sel_DDATALO = 409, + Mips_COP0Sel_DEBUG = 410, + Mips_COP0Sel_DEBUGCONTEXTID = 411, + Mips_COP0Sel_DEPC = 412, + Mips_COP0Sel_DESAVE = 413, + Mips_COP0Sel_DTAGHI = 414, + Mips_COP0Sel_DTAGLO = 415, + Mips_COP0Sel_EBASE = 416, + Mips_COP0Sel_ENTRYHI = 417, + Mips_COP0Sel_EPC = 418, + Mips_COP0Sel_ERRCTL = 419, + Mips_COP0Sel_ERROREPC = 420, + Mips_COP0Sel_GLOBALNUMBER = 421, + Mips_COP0Sel_GTOFFSET = 422, + Mips_COP0Sel_HWRENA = 423, + Mips_COP0Sel_IDATAHI = 424, + Mips_COP0Sel_IDATALO = 425, + Mips_COP0Sel_INDEX = 426, + Mips_COP0Sel_INTCTL = 427, + Mips_COP0Sel_ITAGHI = 428, + Mips_COP0Sel_ITAGLO = 429, + Mips_COP0Sel_LLADDR = 430, + Mips_COP0Sel_MAAR = 431, + Mips_COP0Sel_MAARI = 432, + Mips_COP0Sel_MEMORYMAPID = 433, + Mips_COP0Sel_MVPCONTROL = 434, + Mips_COP0Sel_NESTEDEPC = 435, + Mips_COP0Sel_NESTEDEXC = 436, + Mips_COP0Sel_PAGEGRAIN = 437, + Mips_COP0Sel_PAGEMASK = 438, + Mips_COP0Sel_PRID = 439, + Mips_COP0Sel_PWBASE = 440, + Mips_COP0Sel_PWCTL = 441, + Mips_COP0Sel_PWFIELD = 442, + Mips_COP0Sel_PWSIZE = 443, + Mips_COP0Sel_RANDOM = 444, + Mips_COP0Sel_SRSCTL = 445, + Mips_COP0Sel_SRSMAP = 446, + Mips_COP0Sel_STATUS = 447, + Mips_COP0Sel_TCBIND = 448, + Mips_COP0Sel_TCCONTEXT = 449, + Mips_COP0Sel_TCHALT = 450, + Mips_COP0Sel_TCOPT = 451, + Mips_COP0Sel_TCRESTART = 452, + Mips_COP0Sel_TCSCHEDULE = 453, + Mips_COP0Sel_TCSCHEFBACK = 454, + Mips_COP0Sel_TCSTATUS = 455, + Mips_COP0Sel_TRACECONTROL = 456, + Mips_COP0Sel_TRACEDBPC = 457, + Mips_COP0Sel_TRACEIBPC = 458, + Mips_COP0Sel_USERLOCAL = 459, + Mips_COP0Sel_VIEW_IPL = 460, + Mips_COP0Sel_VIEW_RIPL = 461, + Mips_COP0Sel_VPCONTROL = 462, + Mips_COP0Sel_VPECONTROL = 463, + Mips_COP0Sel_VPEOPT = 464, + Mips_COP0Sel_VPESCHEDULE = 465, + Mips_COP0Sel_VPESCHEFBACK = 466, + Mips_COP0Sel_WIRED = 467, + Mips_COP0Sel_XCONTEXT = 468, + Mips_COP0Sel_XCONTEXTCONFIG = 469, + Mips_COP0Sel_YQMASK = 470, + Mips_K0_NM = 471, + Mips_K1_NM = 472, + Mips_S0_NM = 473, + Mips_S1_NM = 474, + Mips_S2_NM = 475, + Mips_S3_NM = 476, + Mips_S4_NM = 477, + Mips_S5_NM = 478, + Mips_S6_NM = 479, + Mips_S7_NM = 480, + Mips_T0_NM = 481, + Mips_T1_NM = 482, + Mips_T2_NM = 483, + Mips_T3_NM = 484, + Mips_T4_NM = 485, + Mips_T5_NM = 486, + Mips_T8_NM = 487, + Mips_T9_NM = 488, + Mips_A0_64 = 489, + Mips_A1_64 = 490, + Mips_A2_64 = 491, + Mips_A3_64 = 492, + Mips_AC0_64 = 493, + Mips_COP0Sel_CONFIG1 = 494, + Mips_COP0Sel_CONFIG2 = 495, + Mips_COP0Sel_CONFIG3 = 496, + Mips_COP0Sel_CONFIG4 = 497, + Mips_COP0Sel_CONFIG5 = 498, + Mips_COP0Sel_DEBUG2 = 499, + Mips_COP0Sel_ENTRYLO0 = 500, + Mips_COP0Sel_ENTRYLO1 = 501, + Mips_COP0Sel_GUESTCTL0 = 502, + Mips_COP0Sel_GUESTCTL1 = 503, + Mips_COP0Sel_GUESTCTL2 = 504, + Mips_COP0Sel_GUESTCTL3 = 505, + Mips_COP0Sel_KSCRATCH1 = 506, + Mips_COP0Sel_KSCRATCH2 = 507, + Mips_COP0Sel_KSCRATCH3 = 508, + Mips_COP0Sel_KSCRATCH4 = 509, + Mips_COP0Sel_KSCRATCH5 = 510, + Mips_COP0Sel_KSCRATCH6 = 511, + Mips_COP0Sel_MVPCONF0 = 512, + Mips_COP0Sel_MVPCONF1 = 513, + Mips_COP0Sel_PERFCNT0 = 514, + Mips_COP0Sel_PERFCNT1 = 515, + Mips_COP0Sel_PERFCNT2 = 516, + Mips_COP0Sel_PERFCNT3 = 517, + Mips_COP0Sel_PERFCNT4 = 518, + Mips_COP0Sel_PERFCNT5 = 519, + Mips_COP0Sel_PERFCNT6 = 520, + Mips_COP0Sel_PERFCNT7 = 521, + Mips_COP0Sel_PERFCTL0 = 522, + Mips_COP0Sel_PERFCTL1 = 523, + Mips_COP0Sel_PERFCTL2 = 524, + Mips_COP0Sel_PERFCTL3 = 525, + Mips_COP0Sel_PERFCTL4 = 526, + Mips_COP0Sel_PERFCTL5 = 527, + Mips_COP0Sel_PERFCTL6 = 528, + Mips_COP0Sel_PERFCTL7 = 529, + Mips_COP0Sel_SEGCTL0 = 530, + Mips_COP0Sel_SEGCTL1 = 531, + Mips_COP0Sel_SEGCTL2 = 532, + Mips_COP0Sel_SRSCONF0 = 533, + Mips_COP0Sel_SRSCONF1 = 534, + Mips_COP0Sel_SRSCONF2 = 535, + Mips_COP0Sel_SRSCONF3 = 536, + Mips_COP0Sel_SRSCONF4 = 537, + Mips_COP0Sel_SRSMAP2 = 538, + Mips_COP0Sel_TRACECONTROL2 = 539, + Mips_COP0Sel_TRACECONTROL3 = 540, + Mips_COP0Sel_USERTRACEDATA1 = 541, + Mips_COP0Sel_USERTRACEDATA2 = 542, + Mips_COP0Sel_VPECONF0 = 543, + Mips_COP0Sel_VPECONF1 = 544, + Mips_COP0Sel_WATCHHI0 = 545, + Mips_COP0Sel_WATCHHI1 = 546, + Mips_COP0Sel_WATCHHI2 = 547, + Mips_COP0Sel_WATCHHI3 = 548, + Mips_COP0Sel_WATCHHI4 = 549, + Mips_COP0Sel_WATCHHI5 = 550, + Mips_COP0Sel_WATCHHI6 = 551, + Mips_COP0Sel_WATCHHI7 = 552, + Mips_COP0Sel_WATCHHI8 = 553, + Mips_COP0Sel_WATCHHI9 = 554, + Mips_COP0Sel_WATCHHI10 = 555, + Mips_COP0Sel_WATCHHI11 = 556, + Mips_COP0Sel_WATCHHI12 = 557, + Mips_COP0Sel_WATCHHI13 = 558, + Mips_COP0Sel_WATCHHI14 = 559, + Mips_COP0Sel_WATCHHI15 = 560, + Mips_COP0Sel_WATCHLO0 = 561, + Mips_COP0Sel_WATCHLO1 = 562, + Mips_COP0Sel_WATCHLO2 = 563, + Mips_COP0Sel_WATCHLO3 = 564, + Mips_COP0Sel_WATCHLO4 = 565, + Mips_COP0Sel_WATCHLO5 = 566, + Mips_COP0Sel_WATCHLO6 = 567, + Mips_COP0Sel_WATCHLO7 = 568, + Mips_COP0Sel_WATCHLO8 = 569, + Mips_COP0Sel_WATCHLO9 = 570, + Mips_COP0Sel_WATCHLO10 = 571, + Mips_COP0Sel_WATCHLO11 = 572, + Mips_COP0Sel_WATCHLO12 = 573, + Mips_COP0Sel_WATCHLO13 = 574, + Mips_COP0Sel_WATCHLO14 = 575, + Mips_COP0Sel_WATCHLO15 = 576, + Mips_D0_64 = 577, + Mips_D1_64 = 578, + Mips_D2_64 = 579, + Mips_D3_64 = 580, + Mips_D4_64 = 581, + Mips_D5_64 = 582, + Mips_D6_64 = 583, + Mips_D7_64 = 584, + Mips_D8_64 = 585, + Mips_D9_64 = 586, + Mips_D10_64 = 587, + Mips_D11_64 = 588, + Mips_D12_64 = 589, + Mips_D13_64 = 590, + Mips_D14_64 = 591, + Mips_D15_64 = 592, + Mips_D16_64 = 593, + Mips_D17_64 = 594, + Mips_D18_64 = 595, + Mips_D19_64 = 596, + Mips_D20_64 = 597, + Mips_D21_64 = 598, + Mips_D22_64 = 599, + Mips_D23_64 = 600, + Mips_D24_64 = 601, + Mips_D25_64 = 602, + Mips_D26_64 = 603, + Mips_D27_64 = 604, + Mips_D28_64 = 605, + Mips_D29_64 = 606, + Mips_D30_64 = 607, + Mips_D31_64 = 608, + Mips_DSPOutFlag16_19 = 609, + Mips_HI0_64 = 610, + Mips_K0_64 = 611, + Mips_K1_64 = 612, + Mips_LO0_64 = 613, + Mips_S0_64 = 614, + Mips_S1_64 = 615, + Mips_S2_64 = 616, + Mips_S3_64 = 617, + Mips_S4_64 = 618, + Mips_S5_64 = 619, + Mips_S6_64 = 620, + Mips_S7_64 = 621, + Mips_T0_64 = 622, + Mips_T1_64 = 623, + Mips_T2_64 = 624, + Mips_T3_64 = 625, + Mips_T4_64 = 626, + Mips_T5_64 = 627, + Mips_T6_64 = 628, + Mips_T7_64 = 629, + Mips_T8_64 = 630, + Mips_T9_64 = 631, + Mips_V0_64 = 632, + Mips_V1_64 = 633, + Mips_COP0Sel_GUESTCTL0EXT = 634, + NUM_TARGET_REGS // 635 }; // Register classes + enum { - Mips_OddSPRegClassID = 0, - Mips_CCRRegClassID = 1, - Mips_COP2RegClassID = 2, - Mips_COP3RegClassID = 3, - Mips_DSPRRegClassID = 4, - Mips_FGR32RegClassID = 5, - Mips_FGRCCRegClassID = 6, - Mips_FGRH32RegClassID = 7, - Mips_GPR32RegClassID = 8, - Mips_HWRegsRegClassID = 9, - Mips_OddSP_with_sub_hiRegClassID = 10, - Mips_FGR32_and_OddSPRegClassID = 11, - Mips_FGRH32_and_OddSPRegClassID = 12, - Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 13, - Mips_CPU16RegsPlusSPRegClassID = 14, - Mips_CCRegClassID = 15, - Mips_CPU16RegsRegClassID = 16, - Mips_FCCRegClassID = 17, - Mips_GPRMM16RegClassID = 18, - Mips_GPRMM16MovePRegClassID = 19, - Mips_GPRMM16ZeroRegClassID = 20, - Mips_MSACtrlRegClassID = 21, - Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 22, - Mips_CPU16Regs_and_GPRMM16ZeroRegClassID = 23, - Mips_CPU16Regs_and_GPRMM16MovePRegClassID = 24, - Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 25, - Mips_HI32DSPRegClassID = 26, - Mips_LO32DSPRegClassID = 27, - Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 28, - Mips_CPURARegRegClassID = 29, - Mips_CPUSPRegRegClassID = 30, - Mips_DSPCCRegClassID = 31, - Mips_HI32RegClassID = 32, - Mips_LO32RegClassID = 33, - Mips_FGR64RegClassID = 34, - Mips_GPR64RegClassID = 35, - Mips_AFGR64RegClassID = 36, - Mips_FGR64_and_OddSPRegClassID = 37, - Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 38, - Mips_AFGR64_and_OddSPRegClassID = 39, - Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 40, - Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 41, - Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 42, - Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 43, - Mips_ACC64DSPRegClassID = 44, - Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 45, - Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 46, - Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 47, - Mips_OCTEON_MPLRegClassID = 48, - Mips_OCTEON_PRegClassID = 49, - Mips_ACC64RegClassID = 50, - Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 51, - Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID = 52, - Mips_HI64RegClassID = 53, - Mips_LO64RegClassID = 54, - Mips_MSA128BRegClassID = 55, - Mips_MSA128DRegClassID = 56, - Mips_MSA128HRegClassID = 57, - Mips_MSA128WRegClassID = 58, - Mips_MSA128B_with_sub_64_in_OddSPRegClassID = 59, - Mips_MSA128WEvensRegClassID = 60, - Mips_ACC128RegClassID = 61, + Mips_MSA128F16RegClassID = 0, + Mips_COP0SelRegClassID = 1, + Mips_CCRRegClassID = 2, + Mips_COP0RegClassID = 3, + Mips_COP2RegClassID = 4, + Mips_COP3RegClassID = 5, + Mips_DSPRRegClassID = 6, + Mips_FGR32RegClassID = 7, + Mips_FGRCCRegClassID = 8, + Mips_GPR32RegClassID = 9, + Mips_GPRNM32RegClassID = 10, + Mips_HWRegsRegClassID = 11, + Mips_MSACtrlRegClassID = 12, + Mips_GPR32NONZERORegClassID = 13, + Mips_GPRNM32NZRegClassID = 14, + Mips_GPRNM32_TAILRegClassID = 15, + Mips_GPRNM4RegClassID = 16, + Mips_GPRNM4ZRegClassID = 17, + Mips_GPRNM4_and_GPRNM4ZRegClassID = 18, + Mips_CPU16RegsPlusSPRegClassID = 19, + Mips_CPU16RegsRegClassID = 20, + Mips_FCCRegClassID = 21, + Mips_GPRMM16RegClassID = 22, + Mips_GPRMM16MovePRegClassID = 23, + Mips_GPRMM16ZeroRegClassID = 24, + Mips_GPRNM3RegClassID = 25, + Mips_GPRNM3ZRegClassID = 26, + Mips_GPRNM4_and_GPRNM32_TAILRegClassID = 27, + Mips_CPU16Regs_and_GPRMM16ZeroRegClassID = 28, + Mips_GPR32NONZERO_and_GPRMM16MovePRegClassID = 29, + Mips_GPRNM3_and_GPRNM3ZRegClassID = 30, + Mips_GPRNM4Z_and_GPRNM32_TAILRegClassID = 31, + Mips_GPRMM16MovePPairSecondRegClassID = 32, + Mips_CPU16Regs_and_GPRMM16MovePRegClassID = 33, + Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 34, + Mips_GPRNM2R1RegClassID = 35, + Mips_GPRNM2R2RegClassID = 36, + Mips_HI32DSPRegClassID = 37, + Mips_LO32DSPRegClassID = 38, + Mips_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 39, + Mips_GPRMM16MovePPairFirstRegClassID = 40, + Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 41, + Mips_GPRNM2R1_and_GPRNM2R2RegClassID = 42, + Mips_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 43, + Mips_GPRNM1R1RegClassID = 44, + Mips_CPURARegRegClassID = 45, + Mips_CPUSPRegRegClassID = 46, + Mips_DSPCCRegClassID = 47, + Mips_GP32RegClassID = 48, + Mips_GPR32ZERORegClassID = 49, + Mips_GPRNM1R1_and_GPRNM2R2RegClassID = 50, + Mips_GPRNMGPRegClassID = 51, + Mips_GPRNMRARegClassID = 52, + Mips_GPRNMSPRegClassID = 53, + Mips_HI32RegClassID = 54, + Mips_LO32RegClassID = 55, + Mips_SP32RegClassID = 56, + Mips_FGR64RegClassID = 57, + Mips_GPR64RegClassID = 58, + Mips_GPR64_with_sub_32_in_GPR32NONZERORegClassID = 59, + Mips_AFGR64RegClassID = 60, + Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 61, + Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 62, + Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 63, + Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 64, + Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 65, + Mips_GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 66, + Mips_GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 67, + Mips_ACC64DSPRegClassID = 68, + Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 69, + Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 70, + Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 71, + Mips_GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 72, + Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 73, + Mips_OCTEON_MPLRegClassID = 74, + Mips_OCTEON_PRegClassID = 75, + Mips_GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 76, + Mips_ACC64RegClassID = 77, + Mips_GP64RegClassID = 78, + Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 79, + Mips_GPR64_with_sub_32_in_GPR32ZERORegClassID = 80, + Mips_HI64RegClassID = 81, + Mips_LO64RegClassID = 82, + Mips_SP64RegClassID = 83, + Mips_MSA128BRegClassID = 84, + Mips_MSA128DRegClassID = 85, + Mips_MSA128HRegClassID = 86, + Mips_MSA128WRegClassID = 87, + Mips_MSA128WEvensRegClassID = 88, + Mips_ACC128RegClassID = 89, + }; +// Subregister indices + +enum { + Mips_NoSubRegister, + Mips_sub_32, // 1 + Mips_sub_64, // 2 + Mips_sub_dsp16_19, // 3 + Mips_sub_dsp20, // 4 + Mips_sub_dsp21, // 5 + Mips_sub_dsp22, // 6 + Mips_sub_dsp23, // 7 + Mips_sub_hi, // 8 + Mips_sub_lo, // 9 + Mips_sub_hi_then_sub_32, // 10 + Mips_sub_32_sub_hi_then_sub_32, // 11 + Mips_NUM_TARGET_SUBREGS +}; #endif // GET_REGINFO_ENUM -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*MC Register Information *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2019 */ +/* LLVM-commit: */ +/* LLVM-tag: */ +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg MipsRegDiffLists[] = { - /* 0 */ 0, 0, - /* 2 */ 4, 1, 1, 1, 1, 0, - /* 8 */ 364, -250, 1, 1, 1, 0, - /* 14 */ 20, 1, 0, - /* 17 */ 21, 1, 0, - /* 20 */ 22, 1, 0, - /* 23 */ 23, 1, 0, - /* 26 */ 24, 1, 0, - /* 29 */ 25, 1, 0, - /* 32 */ 26, 1, 0, - /* 35 */ 27, 1, 0, - /* 38 */ 28, 1, 0, - /* 41 */ 29, 1, 0, - /* 44 */ 30, 1, 0, - /* 47 */ 31, 1, 0, - /* 50 */ 32, 1, 0, - /* 53 */ 33, 1, 0, - /* 56 */ 34, 1, 0, - /* 59 */ 35, 1, 0, - /* 62 */ -97, 1, 0, - /* 65 */ -23, 1, 0, - /* 68 */ 3, 0, - /* 70 */ 4, 0, - /* 72 */ 6, 0, - /* 74 */ 11, 0, - /* 76 */ 12, 0, - /* 78 */ 22, 0, - /* 80 */ 23, 0, - /* 82 */ 29, 0, - /* 84 */ 30, 0, - /* 86 */ -228, 72, 0, - /* 89 */ -190, 72, 0, - /* 92 */ 38, -214, 73, 0, - /* 96 */ 95, 0, - /* 98 */ 96, 0, - /* 100 */ 106, 0, - /* 102 */ 187, 0, - /* 104 */ 219, 0, - /* 106 */ 258, 0, - /* 108 */ 266, 0, - /* 110 */ 310, 0, - /* 112 */ -505, 0, - /* 114 */ -428, 0, - /* 116 */ -364, 0, - /* 118 */ -310, 0, - /* 120 */ -307, 0, - /* 122 */ -266, 0, - /* 124 */ -258, 0, - /* 126 */ -241, 0, - /* 128 */ -219, 0, - /* 130 */ 37, -106, 103, -141, -203, 0, - /* 136 */ -187, 0, - /* 138 */ -141, 0, - /* 140 */ -126, 0, - /* 142 */ -121, 0, - /* 144 */ -117, 0, - /* 146 */ -116, 0, - /* 148 */ -115, 0, - /* 150 */ -114, 0, - /* 152 */ -106, 0, - /* 154 */ -96, 0, - /* 156 */ -95, 0, - /* 158 */ 141, -38, 0, - /* 161 */ -20, 234, -38, 0, - /* 165 */ -21, 235, -38, 0, - /* 169 */ -22, 236, -38, 0, - /* 173 */ -23, 237, -38, 0, - /* 177 */ -24, 238, -38, 0, - /* 181 */ -25, 239, -38, 0, - /* 185 */ -26, 240, -38, 0, - /* 189 */ -27, 241, -38, 0, - /* 193 */ -28, 242, -38, 0, - /* 197 */ -29, 243, -38, 0, - /* 201 */ -30, 244, -38, 0, - /* 205 */ -31, 245, -38, 0, - /* 209 */ -32, 246, -38, 0, - /* 213 */ -33, 247, -38, 0, - /* 217 */ -34, 248, -38, 0, - /* 221 */ -35, 249, -38, 0, - /* 225 */ -36, 250, -38, 0, - /* 229 */ -241, 347, -37, 0, - /* 233 */ -203, 344, -34, 0, - /* 237 */ -29, 0, - /* 239 */ -26, 0, - /* 241 */ -25, 0, - /* 243 */ -24, 0, - /* 245 */ -20, 0, - /* 247 */ -15, 0, - /* 249 */ -14, 0, - /* 251 */ -1, 0, + /* 0 */ -603, 0, + /* 2 */ -461, 0, + /* 4 */ -359, 0, + /* 6 */ -351, 0, + /* 8 */ -316, 0, + /* 10 */ -309, 0, + /* 12 */ -282, 0, + /* 14 */ -281, 0, + /* 16 */ -265, 0, + /* 18 */ -247, 0, + /* 20 */ 120, -316, 313, -351, -227, 0, + /* 26 */ 351, -224, 0, + /* 29 */ -20, 444, -224, 0, + /* 33 */ -21, 445, -224, 0, + /* 37 */ -22, 446, -224, 0, + /* 41 */ -23, 447, -224, 0, + /* 45 */ -24, 448, -224, 0, + /* 49 */ -25, 449, -224, 0, + /* 53 */ -26, 450, -224, 0, + /* 57 */ -27, 451, -224, 0, + /* 61 */ -28, 452, -224, 0, + /* 65 */ -29, 453, -224, 0, + /* 69 */ -30, 454, -224, 0, + /* 73 */ -31, 455, -224, 0, + /* 77 */ -32, 456, -224, 0, + /* 81 */ -33, 457, -224, 0, + /* 85 */ -34, 458, -224, 0, + /* 89 */ -35, 459, -224, 0, + /* 93 */ -36, 460, -224, 0, + /* 97 */ -216, 0, + /* 99 */ -146, 0, + /* 101 */ -145, 0, + /* 103 */ -144, 0, + /* 105 */ -143, 0, + /* 107 */ -265, 581, -120, 0, + /* 111 */ -227, 578, -117, 0, + /* 115 */ 265, -38, 0, + /* 118 */ -35, 0, + /* 120 */ 603, -460, 1, 1, 1, 0, + /* 126 */ 1, 1, 1, 1, 0, + /* 131 */ 20, 1, 0, + /* 134 */ 21, 1, 0, + /* 137 */ 22, 1, 0, + /* 140 */ 23, 1, 0, + /* 143 */ 24, 1, 0, + /* 146 */ 25, 1, 0, + /* 149 */ 26, 1, 0, + /* 152 */ 27, 1, 0, + /* 155 */ 28, 1, 0, + /* 158 */ 29, 1, 0, + /* 161 */ 30, 1, 0, + /* 164 */ 31, 1, 0, + /* 167 */ 32, 1, 0, + /* 170 */ 33, 1, 0, + /* 173 */ 34, 1, 0, + /* 176 */ 35, 1, 0, + /* 179 */ 35, 0, + /* 181 */ 72, 0, + /* 183 */ 224, -424, 73, 0, + /* 187 */ 216, 0, + /* 189 */ 247, 0, + /* 191 */ 281, 0, + /* 193 */ 282, 0, + /* 195 */ 309, 0, + /* 197 */ 316, 0, + /* 199 */ 359, 0, + /* 201 */ 461, 0, }; static const uint16_t MipsSubRegIdxLists[] = { @@ -595,1085 +849,2274 @@ static const uint16_t MipsSubRegIdxLists[] = { }; static const MCRegisterDesc MipsRegDesc[] = { // Descriptors - { 6, 0, 0, 0, 0, 0 }, - { 2007, 1, 82, 1, 4017, 0 }, - { 2010, 1, 1, 1, 4017, 0 }, - { 2102, 1, 1, 1, 4017, 0 }, - { 1973, 1, 1, 1, 4017, 0 }, - { 2027, 8, 1, 2, 32, 4 }, - { 2054, 1, 1, 1, 1089, 0 }, - { 2071, 1, 1, 1, 1089, 0 }, - { 1985, 1, 102, 1, 1089, 0 }, - { 1988, 1, 104, 1, 1089, 0 }, - { 2061, 1, 1, 1, 1089, 0 }, - { 2000, 1, 1, 1, 1089, 0 }, - { 1994, 1, 1, 1, 1089, 0 }, - { 2038, 1, 1, 1, 1089, 0 }, - { 2092, 1, 1, 1, 1089, 0 }, - { 2081, 1, 1, 1, 1089, 0 }, - { 2019, 1, 1, 1, 1089, 0 }, - { 2045, 1, 1, 1, 1089, 0 }, - { 1970, 1, 1, 1, 1089, 0 }, - { 1967, 1, 106, 1, 1089, 0 }, - { 1991, 1, 108, 1, 1089, 0 }, - { 1980, 1, 110, 1, 1089, 0 }, - { 152, 1, 110, 1, 1089, 0 }, - { 365, 1, 110, 1, 1089, 0 }, - { 537, 1, 110, 1, 1089, 0 }, - { 703, 1, 110, 1, 1089, 0 }, - { 155, 190, 110, 9, 1042, 10 }, - { 368, 190, 1, 9, 1042, 10 }, - { 540, 190, 1, 9, 1042, 10 }, - { 706, 190, 1, 9, 1042, 10 }, - { 1271, 237, 1, 0, 0, 2 }, - { 160, 1, 1, 1, 1153, 0 }, - { 373, 1, 1, 1, 1153, 0 }, - { 545, 1, 1, 1, 1153, 0 }, - { 711, 1, 1, 1, 1153, 0 }, - { 1278, 1, 1, 1, 1153, 0 }, - { 1412, 1, 1, 1, 1153, 0 }, - { 1542, 1, 1, 1, 1153, 0 }, - { 1672, 1, 1, 1, 1153, 0 }, - { 70, 1, 1, 1, 1153, 0 }, - { 283, 1, 1, 1, 1153, 0 }, - { 496, 1, 1, 1, 1153, 0 }, - { 662, 1, 1, 1, 1153, 0 }, - { 820, 1, 1, 1, 1153, 0 }, - { 1383, 1, 1, 1, 1153, 0 }, - { 1513, 1, 1, 1, 1153, 0 }, - { 1643, 1, 1, 1, 1153, 0 }, - { 1773, 1, 1, 1, 1153, 0 }, - { 1911, 1, 1, 1, 1153, 0 }, - { 130, 1, 1, 1, 1153, 0 }, - { 343, 1, 1, 1, 1153, 0 }, - { 531, 1, 1, 1, 1153, 0 }, - { 697, 1, 1, 1, 1153, 0 }, - { 842, 1, 1, 1, 1153, 0 }, - { 1405, 1, 1, 1, 1153, 0 }, - { 1535, 1, 1, 1, 1153, 0 }, - { 1665, 1, 1, 1, 1153, 0 }, - { 1795, 1, 1, 1, 1153, 0 }, - { 1933, 1, 1, 1, 1153, 0 }, - { 0, 1, 1, 1, 1153, 0 }, - { 213, 1, 1, 1, 1153, 0 }, - { 426, 1, 1, 1, 1153, 0 }, - { 592, 1, 1, 1, 1153, 0 }, - { 750, 1, 1, 1, 1153, 0 }, - { 1313, 1, 1, 1, 1153, 0 }, - { 1447, 1, 1, 1, 1153, 0 }, - { 1577, 1, 1, 1, 1153, 0 }, - { 1707, 1, 1, 1, 1153, 0 }, - { 1829, 1, 1, 1, 1153, 0 }, - { 45, 1, 1, 1, 1153, 0 }, - { 258, 1, 1, 1, 1153, 0 }, - { 471, 1, 1, 1, 1153, 0 }, - { 637, 1, 1, 1, 1153, 0 }, - { 795, 1, 1, 1, 1153, 0 }, - { 1358, 1, 1, 1, 1153, 0 }, - { 1488, 1, 1, 1, 1153, 0 }, - { 1618, 1, 1, 1, 1153, 0 }, - { 1748, 1, 1, 1, 1153, 0 }, - { 1886, 1, 1, 1, 1153, 0 }, - { 105, 1, 1, 1, 1153, 0 }, - { 318, 1, 1, 1, 1153, 0 }, - { 7, 1, 1, 1, 1153, 0 }, - { 220, 1, 1, 1, 1153, 0 }, - { 433, 1, 1, 1, 1153, 0 }, - { 599, 1, 1, 1, 1153, 0 }, - { 757, 1, 1, 1, 1153, 0 }, - { 1320, 1, 1, 1, 1153, 0 }, - { 1454, 1, 1, 1, 1153, 0 }, - { 1584, 1, 1, 1, 1153, 0 }, - { 1714, 1, 1, 1, 1153, 0 }, - { 1836, 1, 1, 1, 1153, 0 }, - { 52, 1, 1, 1, 1153, 0 }, - { 265, 1, 1, 1, 1153, 0 }, - { 478, 1, 1, 1, 1153, 0 }, - { 644, 1, 1, 1, 1153, 0 }, - { 802, 1, 1, 1, 1153, 0 }, - { 1365, 1, 1, 1, 1153, 0 }, - { 1495, 1, 1, 1, 1153, 0 }, - { 1625, 1, 1, 1, 1153, 0 }, - { 1755, 1, 1, 1, 1153, 0 }, - { 1893, 1, 1, 1, 1153, 0 }, - { 112, 1, 1, 1, 1153, 0 }, - { 325, 1, 1, 1, 1153, 0 }, - { 164, 14, 1, 9, 994, 10 }, - { 377, 17, 1, 9, 994, 10 }, - { 549, 20, 1, 9, 994, 10 }, - { 715, 23, 1, 9, 994, 10 }, - { 1282, 26, 1, 9, 994, 10 }, - { 1416, 29, 1, 9, 994, 10 }, - { 1546, 32, 1, 9, 994, 10 }, - { 1676, 35, 1, 9, 994, 10 }, - { 1801, 38, 1, 9, 994, 10 }, - { 1939, 41, 1, 9, 994, 10 }, - { 14, 44, 1, 9, 994, 10 }, - { 227, 47, 1, 9, 994, 10 }, - { 440, 50, 1, 9, 994, 10 }, - { 606, 53, 1, 9, 994, 10 }, - { 764, 56, 1, 9, 994, 10 }, - { 1327, 59, 1, 9, 994, 10 }, - { 92, 1, 150, 1, 2401, 0 }, - { 305, 1, 148, 1, 2401, 0 }, - { 518, 1, 146, 1, 2401, 0 }, - { 684, 1, 144, 1, 2401, 0 }, - { 167, 1, 161, 1, 3985, 0 }, - { 380, 1, 165, 1, 3985, 0 }, - { 552, 1, 165, 1, 3985, 0 }, - { 718, 1, 169, 1, 3985, 0 }, - { 1285, 1, 169, 1, 3985, 0 }, - { 1419, 1, 173, 1, 3985, 0 }, - { 1549, 1, 173, 1, 3985, 0 }, - { 1679, 1, 177, 1, 3985, 0 }, - { 1804, 1, 177, 1, 3985, 0 }, - { 1942, 1, 181, 1, 3985, 0 }, - { 18, 1, 181, 1, 3985, 0 }, - { 231, 1, 185, 1, 3985, 0 }, - { 444, 1, 185, 1, 3985, 0 }, - { 610, 1, 189, 1, 3985, 0 }, - { 768, 1, 189, 1, 3985, 0 }, - { 1331, 1, 193, 1, 3985, 0 }, - { 1461, 1, 193, 1, 3985, 0 }, - { 1591, 1, 197, 1, 3985, 0 }, - { 1721, 1, 197, 1, 3985, 0 }, - { 1843, 1, 201, 1, 3985, 0 }, - { 59, 1, 201, 1, 3985, 0 }, - { 272, 1, 205, 1, 3985, 0 }, - { 485, 1, 205, 1, 3985, 0 }, - { 651, 1, 209, 1, 3985, 0 }, - { 809, 1, 209, 1, 3985, 0 }, - { 1372, 1, 213, 1, 3985, 0 }, - { 1502, 1, 213, 1, 3985, 0 }, - { 1632, 1, 217, 1, 3985, 0 }, - { 1762, 1, 217, 1, 3985, 0 }, - { 1900, 1, 221, 1, 3985, 0 }, - { 119, 1, 221, 1, 3985, 0 }, - { 332, 1, 225, 1, 3985, 0 }, - { 159, 1, 1, 1, 3985, 0 }, - { 372, 1, 1, 1, 3985, 0 }, - { 544, 1, 1, 1, 3985, 0 }, - { 710, 1, 1, 1, 3985, 0 }, - { 1277, 1, 1, 1, 3985, 0 }, - { 1411, 1, 1, 1, 3985, 0 }, - { 1541, 1, 1, 1, 3985, 0 }, - { 1671, 1, 1, 1, 3985, 0 }, - { 191, 1, 1, 1, 3985, 0 }, - { 404, 1, 1, 1, 3985, 0 }, - { 573, 1, 1, 1, 3985, 0 }, - { 731, 1, 1, 1, 3985, 0 }, - { 1294, 1, 1, 1, 3985, 0 }, - { 1428, 1, 1, 1, 3985, 0 }, - { 1558, 1, 1, 1, 3985, 0 }, - { 1688, 1, 1, 1, 3985, 0 }, - { 1813, 1, 1, 1, 3985, 0 }, - { 1951, 1, 1, 1, 3985, 0 }, - { 29, 1, 1, 1, 3985, 0 }, - { 242, 1, 1, 1, 3985, 0 }, - { 455, 1, 1, 1, 3985, 0 }, - { 621, 1, 1, 1, 3985, 0 }, - { 779, 1, 1, 1, 3985, 0 }, - { 1342, 1, 1, 1, 3985, 0 }, - { 1472, 1, 1, 1, 3985, 0 }, - { 1602, 1, 1, 1, 3985, 0 }, - { 1732, 1, 1, 1, 3985, 0 }, - { 1854, 1, 1, 1, 3985, 0 }, - { 76, 1, 1, 1, 3985, 0 }, - { 289, 1, 1, 1, 3985, 0 }, - { 502, 1, 1, 1, 3985, 0 }, - { 668, 1, 1, 1, 3985, 0 }, - { 826, 1, 1, 1, 3985, 0 }, - { 1389, 1, 1, 1, 3985, 0 }, - { 1519, 1, 1, 1, 3985, 0 }, - { 1649, 1, 1, 1, 3985, 0 }, - { 1779, 1, 1, 1, 3985, 0 }, - { 1917, 1, 1, 1, 3985, 0 }, - { 136, 1, 1, 1, 3985, 0 }, - { 349, 1, 1, 1, 3985, 0 }, - { 1253, 136, 1, 0, 1184, 2 }, - { 170, 1, 158, 1, 3953, 0 }, - { 383, 1, 158, 1, 3953, 0 }, - { 555, 1, 158, 1, 3953, 0 }, - { 721, 1, 158, 1, 3953, 0 }, - { 1288, 1, 158, 1, 3953, 0 }, - { 1422, 1, 158, 1, 3953, 0 }, - { 1552, 1, 158, 1, 3953, 0 }, - { 1682, 1, 158, 1, 3953, 0 }, - { 1807, 1, 158, 1, 3953, 0 }, - { 1945, 1, 158, 1, 3953, 0 }, - { 22, 1, 158, 1, 3953, 0 }, - { 235, 1, 158, 1, 3953, 0 }, - { 448, 1, 158, 1, 3953, 0 }, - { 614, 1, 158, 1, 3953, 0 }, - { 772, 1, 158, 1, 3953, 0 }, - { 1335, 1, 158, 1, 3953, 0 }, - { 1465, 1, 158, 1, 3953, 0 }, - { 1595, 1, 158, 1, 3953, 0 }, - { 1725, 1, 158, 1, 3953, 0 }, - { 1847, 1, 158, 1, 3953, 0 }, - { 63, 1, 158, 1, 3953, 0 }, - { 276, 1, 158, 1, 3953, 0 }, - { 489, 1, 158, 1, 3953, 0 }, - { 655, 1, 158, 1, 3953, 0 }, - { 813, 1, 158, 1, 3953, 0 }, - { 1376, 1, 158, 1, 3953, 0 }, - { 1506, 1, 158, 1, 3953, 0 }, - { 1636, 1, 158, 1, 3953, 0 }, - { 1766, 1, 158, 1, 3953, 0 }, - { 1904, 1, 158, 1, 3953, 0 }, - { 123, 1, 158, 1, 3953, 0 }, - { 336, 1, 158, 1, 3953, 0 }, - { 1259, 128, 1, 0, 1216, 2 }, - { 172, 1, 233, 1, 1826, 0 }, - { 385, 1, 134, 1, 1826, 0 }, - { 557, 1, 134, 1, 1826, 0 }, - { 723, 1, 134, 1, 1826, 0 }, - { 196, 1, 1, 1, 3921, 0 }, - { 409, 1, 1, 1, 3921, 0 }, - { 578, 1, 1, 1, 3921, 0 }, - { 736, 1, 1, 1, 3921, 0 }, - { 1299, 1, 1, 1, 3921, 0 }, - { 1433, 1, 1, 1, 3921, 0 }, - { 1563, 1, 1, 1, 3921, 0 }, - { 1693, 1, 1, 1, 3921, 0 }, - { 1818, 1, 1, 1, 3921, 0 }, - { 1956, 1, 1, 1, 3921, 0 }, - { 35, 1, 1, 1, 3921, 0 }, - { 248, 1, 1, 1, 3921, 0 }, - { 461, 1, 1, 1, 3921, 0 }, - { 627, 1, 1, 1, 3921, 0 }, - { 785, 1, 1, 1, 3921, 0 }, - { 1348, 1, 1, 1, 3921, 0 }, - { 1478, 1, 1, 1, 3921, 0 }, - { 1608, 1, 1, 1, 3921, 0 }, - { 1738, 1, 1, 1, 3921, 0 }, - { 1860, 1, 1, 1, 3921, 0 }, - { 82, 1, 1, 1, 3921, 0 }, - { 295, 1, 1, 1, 3921, 0 }, - { 508, 1, 1, 1, 3921, 0 }, - { 674, 1, 1, 1, 3921, 0 }, - { 832, 1, 1, 1, 3921, 0 }, - { 1395, 1, 1, 1, 3921, 0 }, - { 1525, 1, 1, 1, 3921, 0 }, - { 1655, 1, 1, 1, 3921, 0 }, - { 1785, 1, 1, 1, 3921, 0 }, - { 1923, 1, 1, 1, 3921, 0 }, - { 142, 1, 1, 1, 3921, 0 }, - { 355, 1, 1, 1, 3921, 0 }, - { 176, 1, 100, 1, 3921, 0 }, - { 389, 1, 100, 1, 3921, 0 }, - { 184, 1, 229, 1, 1794, 0 }, - { 397, 1, 126, 1, 1794, 0 }, - { 566, 1, 126, 1, 1794, 0 }, - { 727, 1, 126, 1, 1794, 0 }, - { 179, 1, 1, 1, 3889, 0 }, - { 392, 1, 1, 1, 3889, 0 }, - { 561, 1, 1, 1, 3889, 0 }, - { 188, 1, 1, 1, 3889, 0 }, - { 401, 1, 1, 1, 3889, 0 }, - { 570, 1, 1, 1, 3889, 0 }, - { 1239, 124, 1, 0, 1248, 2 }, - { 201, 1, 98, 1, 3857, 0 }, - { 414, 1, 98, 1, 3857, 0 }, - { 583, 1, 98, 1, 3857, 0 }, - { 741, 1, 98, 1, 3857, 0 }, - { 1304, 1, 98, 1, 3857, 0 }, - { 1438, 1, 98, 1, 3857, 0 }, - { 1568, 1, 98, 1, 3857, 0 }, - { 1698, 1, 98, 1, 3857, 0 }, - { 1265, 122, 1, 0, 1280, 2 }, - { 204, 1, 96, 1, 3825, 0 }, - { 417, 1, 96, 1, 3825, 0 }, - { 586, 1, 96, 1, 3825, 0 }, - { 744, 1, 96, 1, 3825, 0 }, - { 1307, 1, 96, 1, 3825, 0 }, - { 1441, 1, 96, 1, 3825, 0 }, - { 1571, 1, 96, 1, 3825, 0 }, - { 1701, 1, 96, 1, 3825, 0 }, - { 1823, 1, 96, 1, 3825, 0 }, - { 1961, 1, 96, 1, 3825, 0 }, - { 207, 1, 96, 1, 3825, 0 }, - { 420, 1, 96, 1, 3825, 0 }, - { 210, 92, 1, 8, 1425, 10 }, - { 423, 92, 1, 8, 1425, 10 }, - { 589, 92, 1, 8, 1425, 10 }, - { 747, 92, 1, 8, 1425, 10 }, - { 1310, 92, 1, 8, 1425, 10 }, - { 1444, 92, 1, 8, 1425, 10 }, - { 1574, 92, 1, 8, 1425, 10 }, - { 1704, 92, 1, 8, 1425, 10 }, - { 1826, 92, 1, 8, 1425, 10 }, - { 1964, 92, 1, 8, 1425, 10 }, - { 41, 92, 1, 8, 1425, 10 }, - { 254, 92, 1, 8, 1425, 10 }, - { 467, 92, 1, 8, 1425, 10 }, - { 633, 92, 1, 8, 1425, 10 }, - { 791, 92, 1, 8, 1425, 10 }, - { 1354, 92, 1, 8, 1425, 10 }, - { 1484, 92, 1, 8, 1425, 10 }, - { 1614, 92, 1, 8, 1425, 10 }, - { 1744, 92, 1, 8, 1425, 10 }, - { 1866, 92, 1, 8, 1425, 10 }, - { 88, 92, 1, 8, 1425, 10 }, - { 301, 92, 1, 8, 1425, 10 }, - { 514, 92, 1, 8, 1425, 10 }, - { 680, 92, 1, 8, 1425, 10 }, - { 838, 92, 1, 8, 1425, 10 }, - { 1401, 92, 1, 8, 1425, 10 }, - { 1531, 92, 1, 8, 1425, 10 }, - { 1661, 92, 1, 8, 1425, 10 }, - { 1791, 92, 1, 8, 1425, 10 }, - { 1929, 92, 1, 8, 1425, 10 }, - { 148, 92, 1, 8, 1425, 10 }, - { 361, 92, 1, 8, 1425, 10 }, - { 1245, 118, 1, 0, 1921, 2 }, - { 869, 118, 1, 0, 1921, 2 }, - { 947, 118, 1, 0, 1921, 2 }, - { 997, 118, 1, 0, 1921, 2 }, - { 1035, 118, 1, 0, 1921, 2 }, - { 875, 130, 1, 12, 656, 10 }, - { 882, 93, 159, 9, 1377, 10 }, - { 953, 93, 159, 9, 1377, 10 }, - { 1003, 93, 159, 9, 1377, 10 }, - { 1041, 93, 159, 9, 1377, 10 }, - { 1073, 93, 159, 9, 1377, 10 }, - { 1105, 93, 159, 9, 1377, 10 }, - { 1137, 93, 159, 9, 1377, 10 }, - { 1169, 93, 159, 9, 1377, 10 }, - { 1201, 93, 159, 9, 1377, 10 }, - { 1227, 93, 159, 9, 1377, 10 }, - { 848, 93, 159, 9, 1377, 10 }, - { 926, 93, 159, 9, 1377, 10 }, - { 983, 93, 159, 9, 1377, 10 }, - { 1021, 93, 159, 9, 1377, 10 }, - { 1059, 93, 159, 9, 1377, 10 }, - { 1091, 93, 159, 9, 1377, 10 }, - { 1123, 93, 159, 9, 1377, 10 }, - { 1155, 93, 159, 9, 1377, 10 }, - { 1187, 93, 159, 9, 1377, 10 }, - { 1213, 93, 159, 9, 1377, 10 }, - { 855, 93, 159, 9, 1377, 10 }, - { 933, 93, 159, 9, 1377, 10 }, - { 990, 93, 159, 9, 1377, 10 }, - { 1028, 93, 159, 9, 1377, 10 }, - { 1066, 93, 159, 9, 1377, 10 }, - { 1098, 93, 159, 9, 1377, 10 }, - { 1130, 93, 159, 9, 1377, 10 }, - { 1162, 93, 159, 9, 1377, 10 }, - { 1194, 93, 159, 9, 1377, 10 }, - { 1220, 93, 159, 9, 1377, 10 }, - { 862, 93, 159, 9, 1377, 10 }, - { 940, 93, 159, 9, 1377, 10 }, - { 1870, 1, 116, 1, 1120, 0 }, - { 888, 138, 235, 0, 1344, 2 }, - { 895, 152, 1, 0, 2241, 2 }, - { 959, 152, 1, 0, 2241, 2 }, - { 901, 152, 231, 0, 1312, 2 }, - { 908, 154, 1, 0, 2273, 2 }, - { 965, 154, 1, 0, 2273, 2 }, - { 1009, 154, 1, 0, 2273, 2 }, - { 1047, 154, 1, 0, 2273, 2 }, - { 1079, 154, 1, 0, 2273, 2 }, - { 1111, 154, 1, 0, 2273, 2 }, - { 1143, 154, 1, 0, 2273, 2 }, - { 1175, 154, 1, 0, 2273, 2 }, - { 914, 156, 1, 0, 2273, 2 }, - { 971, 156, 1, 0, 2273, 2 }, - { 1015, 156, 1, 0, 2273, 2 }, - { 1053, 156, 1, 0, 2273, 2 }, - { 1085, 156, 1, 0, 2273, 2 }, - { 1117, 156, 1, 0, 2273, 2 }, - { 1149, 156, 1, 0, 2273, 2 }, - { 1181, 156, 1, 0, 2273, 2 }, - { 1207, 156, 1, 0, 2273, 2 }, - { 1233, 156, 1, 0, 2273, 2 }, - { 920, 156, 1, 0, 2273, 2 }, - { 977, 156, 1, 0, 2273, 2 }, + { 5, 0, 0, 0, 0, 0 }, + { 5012, 1, 179, 1, 4096, 11 }, + { 4736, 1, 1, 1, 4097, 11 }, + { 5228, 1, 1, 1, 4098, 11 }, + { 5320, 1, 1, 1, 4099, 11 }, + { 4187, 1, 1, 1, 4100, 11 }, + { 5245, 120, 1, 2, 516101, 2 }, + { 5272, 1, 1, 1, 4106, 11 }, + { 5289, 1, 1, 1, 4107, 11 }, + { 4857, 1, 187, 1, 4108, 11 }, + { 4718, 1, 1, 1, 4109, 11 }, + { 4860, 1, 189, 1, 4110, 11 }, + { 4724, 1, 1, 1, 4111, 11 }, + { 5279, 1, 1, 1, 4112, 11 }, + { 4973, 1, 1, 1, 4113, 11 }, + { 4950, 1, 1, 1, 4114, 11 }, + { 5256, 1, 1, 1, 4115, 11 }, + { 5310, 1, 1, 1, 4116, 11 }, + { 5299, 1, 1, 1, 4117, 11 }, + { 5237, 1, 1, 1, 4118, 11 }, + { 5263, 1, 1, 1, 4119, 11 }, + { 3750, 1, 1, 1, 4120, 11 }, + { 3718, 1, 195, 1, 4121, 11 }, + { 4704, 1, 1, 1, 4122, 11 }, + { 4881, 1, 197, 1, 4123, 11 }, + { 4730, 1, 1, 1, 4124, 11 }, + { 4837, 1, 199, 1, 4125, 11 }, + { 4710, 1, 1, 1, 4126, 11 }, + { 233, 1, 201, 1, 4127, 11 }, + { 707, 1, 201, 1, 4128, 11 }, + { 1161, 1, 201, 1, 4129, 11 }, + { 1588, 1, 201, 1, 4130, 11 }, + { 236, 115, 201, 9, 507939, 8 }, + { 710, 115, 1, 9, 507941, 8 }, + { 1164, 115, 1, 9, 507943, 8 }, + { 1591, 115, 1, 9, 507945, 8 }, + { 2373, 118, 1, 0, 4096, 0 }, + { 0, 1, 1, 1, 4139, 11 }, + { 454, 1, 1, 1, 4140, 11 }, + { 962, 1, 1, 1, 4141, 11 }, + { 1409, 1, 1, 1, 4142, 11 }, + { 1784, 1, 1, 1, 4143, 11 }, + { 2528, 1, 1, 1, 4144, 11 }, + { 2829, 1, 1, 1, 4145, 11 }, + { 3074, 1, 1, 1, 4146, 11 }, + { 3301, 1, 1, 1, 4147, 11 }, + { 3494, 1, 1, 1, 4148, 11 }, + { 138, 1, 1, 1, 4149, 11 }, + { 592, 1, 1, 1, 4150, 11 }, + { 1100, 1, 1, 1, 4151, 11 }, + { 1547, 1, 1, 1, 4152, 11 }, + { 1922, 1, 1, 1, 4153, 11 }, + { 2666, 1, 1, 1, 4154, 11 }, + { 2927, 1, 1, 1, 4155, 11 }, + { 3172, 1, 1, 1, 4156, 11 }, + { 3399, 1, 1, 1, 4157, 11 }, + { 3608, 1, 1, 1, 4158, 11 }, + { 211, 1, 1, 1, 4159, 11 }, + { 665, 1, 1, 1, 4160, 11 }, + { 1135, 1, 1, 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}, + { 4534, 1, 1, 1, 4478, 11 }, + { 3919, 1, 1, 1, 4479, 11 }, + { 4098, 1, 1, 1, 4480, 11 }, + { 4742, 1, 1, 1, 4481, 11 }, + { 4504, 1, 1, 1, 4482, 11 }, + { 4842, 1, 1, 1, 4483, 11 }, + { 4997, 1, 1, 1, 4484, 11 }, + { 3935, 1, 1, 1, 4485, 11 }, + { 5145, 1, 1, 1, 4486, 11 }, + { 5032, 1, 1, 1, 4487, 11 }, + { 5061, 1, 1, 1, 4488, 11 }, + { 5090, 1, 1, 1, 4489, 11 }, + { 3950, 1, 1, 1, 4490, 11 }, + { 4286, 1, 1, 1, 4491, 11 }, + { 4980, 1, 1, 1, 4492, 11 }, + { 4377, 1, 1, 1, 4493, 11 }, + { 3735, 1, 1, 1, 4494, 11 }, + { 3753, 1, 1, 1, 4495, 11 }, + { 4359, 1, 1, 1, 4496, 11 }, + { 4472, 1, 1, 1, 4497, 11 }, + { 4454, 1, 1, 1, 4498, 11 }, + { 4436, 1, 1, 1, 4499, 11 }, + { 4398, 1, 1, 1, 4500, 11 }, + { 5075, 1, 1, 1, 4501, 11 }, + { 3969, 1, 1, 1, 4502, 11 }, + { 4306, 1, 1, 1, 4503, 11 }, + { 3849, 1, 1, 1, 4504, 11 }, + { 5163, 1, 1, 1, 4505, 11 }, + { 4113, 1, 1, 1, 4506, 11 }, + { 4344, 1, 1, 1, 4507, 11 }, + { 4554, 1, 1, 1, 4508, 11 }, + { 4578, 1, 1, 1, 4509, 11 }, + { 4560, 1, 1, 1, 4510, 11 }, + { 4584, 1, 1, 1, 4511, 11 }, + { 4602, 1, 1, 1, 4512, 11 }, + { 4620, 1, 1, 1, 4513, 11 }, + { 4638, 1, 1, 1, 4514, 11 }, + { 4656, 1, 1, 1, 4515, 11 }, + { 4674, 1, 1, 1, 4516, 11 }, + { 4686, 1, 1, 1, 4517, 11 }, + { 4566, 1, 1, 1, 4518, 11 }, + { 4590, 1, 1, 1, 4519, 11 }, + { 4608, 1, 1, 1, 4520, 11 }, + { 4626, 1, 1, 1, 4521, 11 }, + { 4644, 1, 1, 1, 4522, 11 }, + { 4662, 1, 1, 1, 4523, 11 }, + { 4692, 1, 1, 1, 4524, 11 }, + { 4698, 1, 1, 1, 4525, 11 }, + { 1971, 2, 1, 0, 4127, 0 }, + { 2049, 2, 1, 0, 4128, 0 }, + { 2099, 2, 1, 0, 4129, 0 }, + { 2137, 2, 1, 0, 4130, 0 }, + { 1977, 20, 1, 12, 507939, 8 }, + { 773, 1, 1, 1, 4526, 11 }, + { 1193, 1, 1, 1, 4527, 11 }, + { 1620, 1, 1, 1, 4528, 11 }, + { 2404, 1, 1, 1, 4529, 11 }, + { 2705, 1, 1, 1, 4530, 11 }, + { 1209, 1, 1, 1, 4531, 11 }, + { 398, 1, 1, 1, 4532, 11 }, + { 906, 1, 1, 1, 4533, 11 }, + { 363, 1, 1, 1, 4534, 11 }, + { 871, 1, 1, 1, 4535, 11 }, + { 1325, 1, 1, 1, 4536, 11 }, + { 1716, 1, 1, 1, 4537, 11 }, + { 789, 1, 1, 1, 4538, 11 }, + { 1224, 1, 1, 1, 4539, 11 }, + { 1636, 1, 1, 1, 4540, 11 }, + { 2420, 1, 1, 1, 4541, 11 }, + { 2721, 1, 1, 1, 4542, 11 }, + { 2966, 1, 1, 1, 4543, 11 }, + { 265, 1, 1, 1, 4544, 11 }, + { 739, 1, 1, 1, 4545, 11 }, + { 431, 1, 1, 1, 4546, 11 }, + { 939, 1, 1, 1, 4547, 11 }, + { 1389, 1, 1, 1, 4548, 11 }, + { 1764, 1, 1, 1, 4549, 11 }, + { 2508, 1, 1, 1, 4550, 11 }, + { 2809, 1, 1, 1, 4551, 11 }, + { 3054, 1, 1, 1, 4552, 11 }, + { 3281, 1, 1, 1, 4553, 11 }, + { 330, 1, 1, 1, 4554, 11 }, + { 838, 1, 1, 1, 4555, 11 }, + { 1292, 1, 1, 1, 4556, 11 }, + { 1699, 1, 1, 1, 4557, 11 }, + { 2461, 1, 1, 1, 4558, 11 }, + { 2762, 1, 1, 1, 4559, 11 }, + { 3007, 1, 1, 1, 4560, 11 }, + { 3234, 1, 1, 1, 4561, 11 }, + { 347, 1, 1, 1, 4562, 11 }, + { 855, 1, 1, 1, 4563, 11 }, + { 1309, 1, 1, 1, 4564, 11 }, + { 282, 1, 1, 1, 4565, 11 }, + { 756, 1, 1, 1, 4566, 11 }, + { 1176, 1, 1, 1, 4567, 11 }, + { 1603, 1, 1, 1, 4568, 11 }, + { 2387, 1, 1, 1, 4569, 11 }, + { 1360, 1, 1, 1, 4570, 11 }, + { 1265, 1, 1, 1, 4571, 11 }, + { 1677, 1, 1, 1, 4572, 11 }, + { 687, 1, 1, 1, 4573, 11 }, + { 1141, 1, 1, 1, 4574, 11 }, + { 248, 1, 1, 1, 4575, 11 }, + { 722, 1, 1, 1, 4576, 11 }, + { 299, 1, 1, 1, 4577, 11 }, + { 807, 1, 1, 1, 4578, 11 }, + { 1242, 1, 1, 1, 4579, 11 }, + { 1654, 1, 1, 1, 4580, 11 }, + { 2438, 1, 1, 1, 4581, 11 }, + { 2739, 1, 1, 1, 4582, 11 }, + { 2984, 1, 1, 1, 4583, 11 }, + { 3211, 1, 1, 1, 4584, 11 }, + { 3438, 1, 1, 1, 4585, 11 }, + { 3647, 1, 1, 1, 4586, 11 }, + { 41, 1, 1, 1, 4587, 11 }, + { 495, 1, 1, 1, 4588, 11 }, + { 1003, 1, 1, 1, 4589, 11 }, + { 1450, 1, 1, 1, 4590, 11 }, + { 1825, 1, 1, 1, 4591, 11 }, + { 2569, 1, 1, 1, 4592, 11 }, + { 381, 1, 1, 1, 4593, 11 }, + { 889, 1, 1, 1, 4594, 11 }, + { 1343, 1, 1, 1, 4595, 11 }, + { 1734, 1, 1, 1, 4596, 11 }, + { 2478, 1, 1, 1, 4597, 11 }, + { 2779, 1, 1, 1, 4598, 11 }, + { 3024, 1, 1, 1, 4599, 11 }, + { 3251, 1, 1, 1, 4600, 11 }, + { 3461, 1, 1, 1, 4601, 11 }, + { 3670, 1, 1, 1, 4602, 11 }, + { 66, 1, 1, 1, 4603, 11 }, + { 520, 1, 1, 1, 4604, 11 }, + { 1028, 1, 1, 1, 4605, 11 }, + { 1475, 1, 1, 1, 4606, 11 }, + { 1850, 1, 1, 1, 4607, 11 }, + { 2594, 1, 1, 1, 4608, 11 }, + { 1984, 184, 27, 9, 741515, 8 }, + { 2055, 184, 27, 9, 741516, 8 }, + { 2105, 184, 27, 9, 741517, 8 }, + { 2143, 184, 27, 9, 741518, 8 }, + { 2175, 184, 27, 9, 741519, 8 }, + { 2207, 184, 27, 9, 741520, 8 }, + { 2239, 184, 27, 9, 741521, 8 }, + { 2271, 184, 27, 9, 741522, 8 }, + { 2303, 184, 27, 9, 741523, 8 }, + { 2329, 184, 27, 9, 741524, 8 }, + { 1950, 184, 27, 9, 741525, 8 }, + { 2028, 184, 27, 9, 741526, 8 }, + { 2085, 184, 27, 9, 741527, 8 }, + { 2123, 184, 27, 9, 741528, 8 }, + { 2161, 184, 27, 9, 741529, 8 }, + { 2193, 184, 27, 9, 741530, 8 }, + { 2225, 184, 27, 9, 741531, 8 }, + { 2257, 184, 27, 9, 741532, 8 }, + { 2289, 184, 27, 9, 741533, 8 }, + { 2315, 184, 27, 9, 741534, 8 }, + { 1957, 184, 27, 9, 741535, 8 }, + { 2035, 184, 27, 9, 741536, 8 }, + { 2092, 184, 27, 9, 741537, 8 }, + { 2130, 184, 27, 9, 741538, 8 }, + { 2168, 184, 27, 9, 741539, 8 }, + { 2200, 184, 27, 9, 741540, 8 }, + { 2232, 184, 27, 9, 741541, 8 }, + { 2264, 184, 27, 9, 741542, 8 }, + { 2296, 184, 27, 9, 741543, 8 }, + { 2322, 184, 27, 9, 741544, 8 }, + { 1964, 184, 27, 9, 741545, 8 }, + { 2042, 184, 27, 9, 741546, 8 }, + { 3554, 1, 0, 1, 4101, 11 }, + { 1990, 6, 113, 0, 4132, 0 }, + { 1997, 8, 1, 0, 4371, 0 }, + { 2061, 8, 1, 0, 4372, 0 }, + { 2003, 8, 109, 0, 4131, 0 }, + { 2010, 12, 1, 0, 4403, 0 }, + { 2067, 12, 1, 0, 4404, 0 }, + { 2111, 12, 1, 0, 4405, 0 }, + { 2149, 12, 1, 0, 4406, 0 }, + { 2181, 12, 1, 0, 4407, 0 }, + { 2213, 12, 1, 0, 4408, 0 }, + { 2245, 12, 1, 0, 4409, 0 }, + { 2277, 12, 1, 0, 4410, 0 }, + { 2016, 14, 1, 0, 4411, 0 }, + { 2073, 14, 1, 0, 4412, 0 }, + { 2117, 14, 1, 0, 4413, 0 }, + { 2155, 14, 1, 0, 4414, 0 }, + { 2187, 14, 1, 0, 4415, 0 }, + { 2219, 14, 1, 0, 4416, 0 }, + { 2251, 14, 1, 0, 4417, 0 }, + { 2283, 14, 1, 0, 4418, 0 }, + { 2309, 14, 1, 0, 4419, 0 }, + { 2335, 14, 1, 0, 4420, 0 }, + { 2022, 14, 1, 0, 4421, 0 }, + { 2079, 14, 1, 0, 4422, 0 }, + { 5124, 1, 1, 1, 4609, 11 }, }; - // OddSP Register Class... - static const MCPhysReg OddSP[] = { - Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, + // MSA128F16 Register Class... + static const MCPhysReg MSA128F16[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; - // OddSP Bit set. - static const uint8_t OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, + // MSA128F16 Bit set. + static const uint8_t MSA128F16Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, + }; + + // COP0Sel Register Class... + static const MCPhysReg COP0Sel[] = { + Mips_COP0Sel_INDEX, Mips_COP0Sel_MVPCONTROL, Mips_COP0Sel_MVPCONF0, Mips_COP0Sel_MVPCONF1, Mips_COP0Sel_VPCONTROL, Mips_COP0Sel_RANDOM, Mips_COP0Sel_VPECONTROL, Mips_COP0Sel_VPECONF0, Mips_COP0Sel_VPECONF1, Mips_COP0Sel_YQMASK, Mips_COP0Sel_VPESCHEDULE, Mips_COP0Sel_VPESCHEFBACK, Mips_COP0Sel_VPEOPT, Mips_COP0Sel_ENTRYLO0, Mips_COP0Sel_TCSTATUS, Mips_COP0Sel_TCBIND, Mips_COP0Sel_TCRESTART, Mips_COP0Sel_TCHALT, Mips_COP0Sel_TCCONTEXT, Mips_COP0Sel_TCSCHEDULE, Mips_COP0Sel_TCSCHEFBACK, Mips_COP0Sel_ENTRYLO1, Mips_COP0Sel_GLOBALNUMBER, Mips_COP0Sel_TCOPT, Mips_COP0Sel_CONTEXT, Mips_COP0Sel_CONTEXTCONFIG, Mips_COP0Sel_USERLOCAL, Mips_COP0Sel_XCONTEXTCONFIG, Mips_COP0Sel_DEBUGCONTEXTID, Mips_COP0Sel_MEMORYMAPID, Mips_COP0Sel_PAGEMASK, Mips_COP0Sel_PAGEGRAIN, Mips_COP0Sel_SEGCTL0, Mips_COP0Sel_SEGCTL1, Mips_COP0Sel_SEGCTL2, Mips_COP0Sel_PWBASE, Mips_COP0Sel_PWFIELD, Mips_COP0Sel_PWSIZE, Mips_COP0Sel_WIRED, Mips_COP0Sel_SRSCONF0, Mips_COP0Sel_SRSCONF1, Mips_COP0Sel_SRSCONF2, Mips_COP0Sel_SRSCONF3, Mips_COP0Sel_SRSCONF4, Mips_COP0Sel_PWCTL, Mips_COP0Sel_HWRENA, Mips_COP0Sel_BADVADDR, Mips_COP0Sel_BADINST, Mips_COP0Sel_BADINSTRP, Mips_COP0Sel_BADINSTRX, Mips_COP0Sel_COUNT, Mips_COP0Sel_ENTRYHI, Mips_COP0Sel_GUESTCTL1, Mips_COP0Sel_GUESTCTL2, Mips_COP0Sel_GUESTCTL3, Mips_COP0Sel_COMPARE, Mips_COP0Sel_GUESTCTL0EXT, Mips_COP0Sel_STATUS, Mips_COP0Sel_INTCTL, Mips_COP0Sel_SRSCTL, Mips_COP0Sel_SRSMAP, Mips_COP0Sel_VIEW_IPL, Mips_COP0Sel_SRSMAP2, Mips_COP0Sel_GUESTCTL0, Mips_COP0Sel_GTOFFSET, Mips_COP0Sel_CAUSE, Mips_COP0Sel_VIEW_RIPL, Mips_COP0Sel_NESTEDEXC, Mips_COP0Sel_EPC, Mips_COP0Sel_NESTEDEPC, Mips_COP0Sel_PRID, Mips_COP0Sel_EBASE, Mips_COP0Sel_CDMMBASE, Mips_COP0Sel_CMGCRBASE, Mips_COP0Sel_BEVVA, Mips_COP0Sel_CONFIG, Mips_COP0Sel_CONFIG1, Mips_COP0Sel_CONFIG2, Mips_COP0Sel_CONFIG3, Mips_COP0Sel_CONFIG4, Mips_COP0Sel_CONFIG5, Mips_COP0Sel_LLADDR, Mips_COP0Sel_MAAR, Mips_COP0Sel_MAARI, Mips_COP0Sel_WATCHLO0, Mips_COP0Sel_WATCHLO1, Mips_COP0Sel_WATCHLO2, Mips_COP0Sel_WATCHLO3, Mips_COP0Sel_WATCHLO4, Mips_COP0Sel_WATCHLO5, Mips_COP0Sel_WATCHLO6, Mips_COP0Sel_WATCHLO7, Mips_COP0Sel_WATCHLO8, Mips_COP0Sel_WATCHLO9, Mips_COP0Sel_WATCHLO10, Mips_COP0Sel_WATCHLO11, Mips_COP0Sel_WATCHLO12, Mips_COP0Sel_WATCHLO13, Mips_COP0Sel_WATCHLO14, Mips_COP0Sel_WATCHLO15, Mips_COP0Sel_WATCHHI0, Mips_COP0Sel_WATCHHI1, Mips_COP0Sel_WATCHHI2, Mips_COP0Sel_WATCHHI3, Mips_COP0Sel_WATCHHI4, Mips_COP0Sel_WATCHHI5, Mips_COP0Sel_WATCHHI6, Mips_COP0Sel_WATCHHI7, Mips_COP0Sel_WATCHHI8, Mips_COP0Sel_WATCHHI9, Mips_COP0Sel_WATCHHI10, Mips_COP0Sel_WATCHHI11, Mips_COP0Sel_WATCHHI12, Mips_COP0Sel_WATCHHI13, Mips_COP0Sel_WATCHHI14, Mips_COP0Sel_WATCHHI15, Mips_COP0Sel_XCONTEXT, Mips_COP0Sel_DEBUG, Mips_COP0Sel_TRACECONTROL, Mips_COP0Sel_TRACECONTROL2, Mips_COP0Sel_USERTRACEDATA1, Mips_COP0Sel_TRACEIBPC, Mips_COP0Sel_TRACEDBPC, Mips_COP0Sel_DEBUG2, Mips_COP0Sel_DEPC, Mips_COP0Sel_TRACECONTROL3, Mips_COP0Sel_USERTRACEDATA2, Mips_COP0Sel_PERFCTL0, Mips_COP0Sel_PERFCNT0, Mips_COP0Sel_PERFCTL1, Mips_COP0Sel_PERFCNT1, Mips_COP0Sel_PERFCTL2, Mips_COP0Sel_PERFCNT2, Mips_COP0Sel_PERFCTL3, Mips_COP0Sel_PERFCNT3, Mips_COP0Sel_PERFCTL4, Mips_COP0Sel_PERFCNT4, Mips_COP0Sel_PERFCTL5, Mips_COP0Sel_PERFCNT5, Mips_COP0Sel_PERFCTL6, Mips_COP0Sel_PERFCNT6, Mips_COP0Sel_PERFCTL7, Mips_COP0Sel_PERFCNT7, Mips_COP0Sel_ERRCTL, Mips_COP0Sel_CACHEERR, Mips_COP0Sel_ITAGLO, Mips_COP0Sel_IDATALO, Mips_COP0Sel_DTAGLO, Mips_COP0Sel_DDATALO, Mips_COP0Sel_ITAGHI, Mips_COP0Sel_IDATAHI, Mips_COP0Sel_DTAGHI, Mips_COP0Sel_DDATAHI, Mips_COP0Sel_ERROREPC, Mips_COP0Sel_DESAVE, Mips_COP0Sel_KSCRATCH1, Mips_COP0Sel_KSCRATCH2, Mips_COP0Sel_KSCRATCH3, Mips_COP0Sel_KSCRATCH4, Mips_COP0Sel_KSCRATCH5, Mips_COP0Sel_KSCRATCH6, + }; + + // COP0Sel Bit set. + static const uint8_t COP0SelBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, }; // CCR Register Class... static const MCPhysReg CCR[] = { - Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31, + Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31, }; // CCR Bit set. static const uint8_t CCRBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, + }; + + // COP0 Register Class... + static const MCPhysReg COP0[] = { + Mips_COP00, Mips_COP01, Mips_COP02, Mips_COP03, Mips_COP04, Mips_COP05, Mips_COP06, Mips_COP07, Mips_COP08, Mips_COP09, Mips_COP010, Mips_COP011, Mips_COP012, Mips_COP013, Mips_COP014, Mips_COP015, Mips_COP016, Mips_COP017, Mips_COP018, Mips_COP019, Mips_COP020, Mips_COP021, Mips_COP022, Mips_COP023, Mips_COP024, Mips_COP025, Mips_COP026, Mips_COP027, Mips_COP028, Mips_COP029, Mips_COP030, Mips_COP031, + }; + + // COP0 Bit set. + static const uint8_t COP0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0xe0, 0x7f, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, }; // COP2 Register Class... static const MCPhysReg COP2[] = { - Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231, + Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231, }; // COP2 Bit set. static const uint8_t COP2Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f, }; // COP3 Register Class... static const MCPhysReg COP3[] = { - Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331, + Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331, }; // COP3 Bit set. static const uint8_t COP3Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x1f, }; // DSPR Register Class... static const MCPhysReg DSPR[] = { - Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, + Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, }; // DSPR Bit set. static const uint8_t DSPRBits[] = { - 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, + 0x02, 0x0a, 0x40, 0xf5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0xf0, 0xef, 0xff, 0x01, }; // FGR32 Register Class... static const MCPhysReg FGR32[] = { - Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, + Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, }; // FGR32 Bit set. static const uint8_t FGR32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // FGRCC Register Class... static const MCPhysReg FGRCC[] = { - Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, + Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, }; // FGRCC Bit set. static const uint8_t FGRCCBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // FGRH32 Register Class... - static const MCPhysReg FGRH32[] = { - Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31, - }; - - // FGRH32 Bit set. - static const uint8_t FGRH32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // GPR32 Register Class... static const MCPhysReg GPR32[] = { - Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, + Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, }; // GPR32 Bit set. static const uint8_t GPR32Bits[] = { - 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, + 0x02, 0x0a, 0x40, 0xf5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0xf0, 0xef, 0xff, 0x01, + }; + + // GPRNM32 Register Class... + static const MCPhysReg GPRNM32[] = { + Mips_ZERO_NM, Mips_AT_NM, Mips_T4_NM, Mips_T5_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A7_NM, Mips_T0_NM, Mips_T1_NM, Mips_T2_NM, Mips_T3_NM, Mips_S0_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_S4_NM, Mips_S5_NM, Mips_S6_NM, Mips_S7_NM, Mips_T8_NM, Mips_T9_NM, Mips_K0_NM, Mips_K1_NM, Mips_GP_NM, Mips_SP_NM, Mips_FP_NM, Mips_RA_NM, + }; + + // GPRNM32 Bit set. + static const uint8_t GPRNM32Bits[] = { + 0x04, 0x14, 0x80, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x01, }; // HWRegs Register Class... static const MCPhysReg HWRegs[] = { - Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31, + Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31, }; // HWRegs Bit set. static const uint8_t HWRegsBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, - }; - - // OddSP_with_sub_hi Register Class... - static const MCPhysReg OddSP_with_sub_hi[] = { - Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, - }; - - // OddSP_with_sub_hi Bit set. - static const uint8_t OddSP_with_sub_hiBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, - }; - - // FGR32_and_OddSP Register Class... - static const MCPhysReg FGR32_and_OddSP[] = { - Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, - }; - - // FGR32_and_OddSP Bit set. - static const uint8_t FGR32_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, - }; - - // FGRH32_and_OddSP Register Class... - static const MCPhysReg FGRH32_and_OddSP[] = { - Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, - }; - - // FGRH32_and_OddSP Bit set. - static const uint8_t FGRH32_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, - }; - - // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class... - static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = { - Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, - }; - - // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set. - static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, - }; - - // CPU16RegsPlusSP Register Class... - static const MCPhysReg CPU16RegsPlusSP[] = { - Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP, - }; - - // CPU16RegsPlusSP Bit set. - static const uint8_t CPU16RegsPlusSPBits[] = { - 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, - }; - - // CC Register Class... - static const MCPhysReg CC[] = { - Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7, - }; - - // CC Bit set. - static const uint8_t CCBits[] = { - 0x00, 0x00, 0x00, 0x80, 0x7f, - }; - - // CPU16Regs Register Class... - static const MCPhysReg CPU16Regs[] = { - Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, - }; - - // CPU16Regs Bit set. - static const uint8_t CPU16RegsBits[] = { - 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, - }; - - // FCC Register Class... - static const MCPhysReg FCC[] = { - Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, - }; - - // FCC Bit set. - static const uint8_t FCCBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, - }; - - // GPRMM16 Register Class... - static const MCPhysReg GPRMM16[] = { - Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, - }; - - // GPRMM16 Bit set. - static const uint8_t GPRMM16Bits[] = { - 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, - }; - - // GPRMM16MoveP Register Class... - static const MCPhysReg GPRMM16MoveP[] = { - Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, - }; - - // GPRMM16MoveP Bit set. - static const uint8_t GPRMM16MovePBits[] = { - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, - }; - - // GPRMM16Zero Register Class... - static const MCPhysReg GPRMM16Zero[] = { - Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, - }; - - // GPRMM16Zero Bit set. - static const uint8_t GPRMM16ZeroBits[] = { - 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // MSACtrl Register Class... static const MCPhysReg MSACtrl[] = { - Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, + Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, Mips_MSA8, Mips_MSA9, Mips_MSA10, Mips_MSA11, Mips_MSA12, Mips_MSA13, Mips_MSA14, Mips_MSA15, Mips_MSA16, Mips_MSA17, Mips_MSA18, Mips_MSA19, Mips_MSA20, Mips_MSA21, Mips_MSA22, Mips_MSA23, Mips_MSA24, Mips_MSA25, Mips_MSA26, Mips_MSA27, Mips_MSA28, Mips_MSA29, Mips_MSA30, Mips_MSA31, }; // MSACtrl Bit set. static const uint8_t MSACtrlBits[] = { - 0x00, 0xfc, 0x03, + 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, }; - // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class... - static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = { - Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, + // GPR32NONZERO Register Class... + static const MCPhysReg GPR32NONZERO[] = { + Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, }; - // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set. - static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, + // GPR32NONZERO Bit set. + static const uint8_t GPR32NONZEROBits[] = { + 0x02, 0x0a, 0x40, 0xf1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0xf0, 0xef, 0xff, 0x01, + }; + + // GPRNM32NZ Register Class... + static const MCPhysReg GPRNM32NZ[] = { + Mips_AT_NM, Mips_T4_NM, Mips_T5_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A7_NM, Mips_T0_NM, Mips_T1_NM, Mips_T2_NM, Mips_T3_NM, Mips_S0_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_S4_NM, Mips_S5_NM, Mips_S6_NM, Mips_S7_NM, Mips_T8_NM, Mips_T9_NM, Mips_K0_NM, Mips_K1_NM, Mips_GP_NM, Mips_SP_NM, Mips_FP_NM, Mips_RA_NM, + }; + + // GPRNM32NZ Bit set. + static const uint8_t GPRNM32NZBits[] = { + 0x04, 0x14, 0x80, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x01, + }; + + // GPRNM32_TAIL Register Class... + static const MCPhysReg GPRNM32_TAIL[] = { + Mips_T4_NM, Mips_T5_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A7_NM, Mips_T0_NM, Mips_T1_NM, Mips_T2_NM, Mips_T3_NM, Mips_T8_NM, Mips_T9_NM, + }; + + // GPRNM32_TAIL Bit set. + static const uint8_t GPRNM32_TAILBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, + }; + + // GPRNM4 Register Class... + static const MCPhysReg GPRNM4[] = { + Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A7_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_S0_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_S4_NM, Mips_S5_NM, Mips_S6_NM, Mips_S7_NM, + }; + + // GPRNM4 Bit set. + static const uint8_t GPRNM4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, + }; + + // GPRNM4Z Register Class... + static const MCPhysReg GPRNM4Z[] = { + Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_ZERO_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_S0_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_S4_NM, Mips_S5_NM, Mips_S6_NM, Mips_S7_NM, + }; + + // GPRNM4Z Bit set. + static const uint8_t GPRNM4ZBits[] = { + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, + }; + + // GPRNM4_and_GPRNM4Z Register Class... + static const MCPhysReg GPRNM4_and_GPRNM4Z[] = { + Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_S0_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_S4_NM, Mips_S5_NM, Mips_S6_NM, Mips_S7_NM, + }; + + // GPRNM4_and_GPRNM4Z Bit set. + static const uint8_t GPRNM4_and_GPRNM4ZBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, + }; + + // CPU16RegsPlusSP Register Class... + static const MCPhysReg CPU16RegsPlusSP[] = { + Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP, + }; + + // CPU16RegsPlusSP Bit set. + static const uint8_t CPU16RegsPlusSPBits[] = { + 0x00, 0x00, 0x00, 0xf1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x80, 0x01, + }; + + // CPU16Regs Register Class... + static const MCPhysReg CPU16Regs[] = { + Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, + }; + + // CPU16Regs Bit set. + static const uint8_t CPU16RegsBits[] = { + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x80, 0x01, + }; + + // FCC Register Class... + static const MCPhysReg FCC[] = { + Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, + }; + + // FCC Bit set. + static const uint8_t FCCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, + }; + + // GPRMM16 Register Class... + static const MCPhysReg GPRMM16[] = { + Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + }; + + // GPRMM16 Bit set. + static const uint8_t GPRMM16Bits[] = { + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x80, 0x01, + }; + + // GPRMM16MoveP Register Class... + static const MCPhysReg GPRMM16MoveP[] = { + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, + }; + + // GPRMM16MoveP Bit set. + static const uint8_t GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 0x80, 0x01, + }; + + // GPRMM16Zero Register Class... + static const MCPhysReg GPRMM16Zero[] = { + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + }; + + // GPRMM16Zero Bit set. + static const uint8_t GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0xf4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x80, 0x01, + }; + + // GPRNM3 Register Class... + static const MCPhysReg GPRNM3[] = { + Mips_S0_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, + }; + + // GPRNM3 Bit set. + static const uint8_t GPRNM3Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, + }; + + // GPRNM3Z Register Class... + static const MCPhysReg GPRNM3Z[] = { + Mips_ZERO_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, + }; + + // GPRNM3Z Bit set. + static const uint8_t GPRNM3ZBits[] = { + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, + }; + + // GPRNM4_and_GPRNM32_TAIL Register Class... + static const MCPhysReg GPRNM4_and_GPRNM32_TAIL[] = { + Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A7_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, + }; + + // GPRNM4_and_GPRNM32_TAIL Bit set. + static const uint8_t GPRNM4_and_GPRNM32_TAILBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, }; // CPU16Regs_and_GPRMM16Zero Register Class... static const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { - Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, }; // CPU16Regs_and_GPRMM16Zero Bit set. static const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x80, 0x01, + }; + + // GPR32NONZERO_and_GPRMM16MoveP Register Class... + static const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = { + Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, + }; + + // GPR32NONZERO_and_GPRMM16MoveP Bit set. + static const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 0x80, 0x01, + }; + + // GPRNM3_and_GPRNM3Z Register Class... + static const MCPhysReg GPRNM3_and_GPRNM3Z[] = { + Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, + }; + + // GPRNM3_and_GPRNM3Z Bit set. + static const uint8_t GPRNM3_and_GPRNM3ZBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, + }; + + // GPRNM4Z_and_GPRNM32_TAIL Register Class... + static const MCPhysReg GPRNM4Z_and_GPRNM32_TAIL[] = { + Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, + }; + + // GPRNM4Z_and_GPRNM32_TAIL Bit set. + static const uint8_t GPRNM4Z_and_GPRNM32_TAILBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, + }; + + // GPRMM16MovePPairSecond Register Class... + static const MCPhysReg GPRMM16MovePPairSecond[] = { + Mips_A1, Mips_A2, Mips_A3, Mips_S5, Mips_S6, + }; + + // GPRMM16MovePPairSecond Bit set. + static const uint8_t GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, }; // CPU16Regs_and_GPRMM16MoveP Register Class... static const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { - Mips_S1, Mips_V0, Mips_V1, Mips_S0, + Mips_S1, Mips_V0, Mips_V1, Mips_S0, }; // CPU16Regs_and_GPRMM16MoveP Bit set. static const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x80, 0x01, }; // GPRMM16MoveP_and_GPRMM16Zero Register Class... static const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { - Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, }; // GPRMM16MoveP_and_GPRMM16Zero Bit set. static const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x80, 0x01, + }; + + // GPRNM2R1 Register Class... + static const MCPhysReg GPRNM2R1[] = { + Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, + }; + + // GPRNM2R1 Bit set. + static const uint8_t GPRNM2R1Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, + }; + + // GPRNM2R2 Register Class... + static const MCPhysReg GPRNM2R2[] = { + Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_A4_NM, + }; + + // GPRNM2R2 Bit set. + static const uint8_t GPRNM2R2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, }; // HI32DSP Register Class... static const MCPhysReg HI32DSP[] = { - Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3, + Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3, }; // HI32DSP Bit set. static const uint8_t HI32DSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, }; // LO32DSP Register Class... static const MCPhysReg LO32DSP[] = { - Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3, + Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3, }; // LO32DSP Bit set. static const uint8_t LO32DSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, + }; + + // CPU16Regs_and_GPRMM16MovePPairSecond Register Class... + static const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = { + Mips_A1, Mips_A2, Mips_A3, + }; + + // CPU16Regs_and_GPRMM16MovePPairSecond Bit set. + static const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0xe0, + }; + + // GPRMM16MovePPairFirst Register Class... + static const MCPhysReg GPRMM16MovePPairFirst[] = { + Mips_A0, Mips_A1, Mips_A2, + }; + + // GPRMM16MovePPairFirst Bit set. + static const uint8_t GPRMM16MovePPairFirstBits[] = { + 0x00, 0x00, 0x00, 0x70, }; // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... static const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { - Mips_S1, Mips_V0, Mips_V1, + Mips_S1, Mips_V0, Mips_V1, }; // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. static const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x80, 0x01, + }; + + // GPRNM2R1_and_GPRNM2R2 Register Class... + static const MCPhysReg GPRNM2R1_and_GPRNM2R2[] = { + Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, + }; + + // GPRNM2R1_and_GPRNM2R2 Bit set. + static const uint8_t GPRNM2R1_and_GPRNM2R2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, + }; + + // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class... + static const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = { + Mips_A1, Mips_A2, + }; + + // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set. + static const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0x60, + }; + + // GPRNM1R1 Register Class... + static const MCPhysReg GPRNM1R1[] = { + Mips_A0_NM, Mips_A1_NM, + }; + + // GPRNM1R1 Bit set. + static const uint8_t GPRNM1R1Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, }; // CPURAReg Register Class... static const MCPhysReg CPURAReg[] = { - Mips_RA, + Mips_RA, }; // CPURAReg Bit set. static const uint8_t CPURARegBits[] = { - 0x00, 0x00, 0x08, + 0x00, 0x00, 0x40, }; // CPUSPReg Register Class... static const MCPhysReg CPUSPReg[] = { - Mips_SP, + Mips_SP, }; // CPUSPReg Bit set. static const uint8_t CPUSPRegBits[] = { - 0x00, 0x00, 0x10, + 0x00, 0x00, 0x00, 0x01, }; // DSPCC Register Class... static const MCPhysReg DSPCC[] = { - Mips_DSPCCond, + Mips_DSPCCond, }; // DSPCC Bit set. static const uint8_t DSPCCBits[] = { - 0x04, + 0x08, + }; + + // GP32 Register Class... + static const MCPhysReg GP32[] = { + Mips_GP, + }; + + // GP32 Bit set. + static const uint8_t GP32Bits[] = { + 0x00, 0x08, + }; + + // GPR32ZERO Register Class... + static const MCPhysReg GPR32ZERO[] = { + Mips_ZERO, + }; + + // GPR32ZERO Bit set. + static const uint8_t GPR32ZEROBits[] = { + 0x00, 0x00, 0x00, 0x04, + }; + + // GPRNM1R1_and_GPRNM2R2 Register Class... + static const MCPhysReg GPRNM1R1_and_GPRNM2R2[] = { + Mips_A1_NM, + }; + + // GPRNM1R1_and_GPRNM2R2 Bit set. + static const uint8_t GPRNM1R1_and_GPRNM2R2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + }; + + // GPRNMGP Register Class... + static const MCPhysReg GPRNMGP[] = { + Mips_GP_NM, + }; + + // GPRNMGP Bit set. + static const uint8_t GPRNMGPBits[] = { + 0x00, 0x10, + }; + + // GPRNMRA Register Class... + static const MCPhysReg GPRNMRA[] = { + Mips_RA_NM, + }; + + // GPRNMRA Bit set. + static const uint8_t GPRNMRABits[] = { + 0x00, 0x00, 0x80, + }; + + // GPRNMSP Register Class... + static const MCPhysReg GPRNMSP[] = { + Mips_SP_NM, + }; + + // GPRNMSP Bit set. + static const uint8_t GPRNMSPBits[] = { + 0x00, 0x00, 0x00, 0x02, }; // HI32 Register Class... static const MCPhysReg HI32[] = { - Mips_HI0, + Mips_HI0, }; // HI32 Bit set. static const uint8_t HI32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, }; // LO32 Register Class... static const MCPhysReg LO32[] = { - Mips_LO0, + Mips_LO0, }; // LO32 Bit set. static const uint8_t LO32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + }; + + // SP32 Register Class... + static const MCPhysReg SP32[] = { + Mips_SP, + }; + + // SP32 Bit set. + static const uint8_t SP32Bits[] = { + 0x00, 0x00, 0x00, 0x01, }; // FGR64 Register Class... static const MCPhysReg FGR64[] = { - Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64, + Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64, }; // FGR64 Bit set. static const uint8_t FGR64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // GPR64 Register Class... static const MCPhysReg GPR64[] = { - Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, + Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, }; // GPR64 Bit set. static const uint8_t GPR64Bits[] = { - 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, + }; + + // GPR64_with_sub_32_in_GPR32NONZERO Register Class... + static const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = { + Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, + }; + + // GPR64_with_sub_32_in_GPR32NONZERO Bit set. + static const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, }; // AFGR64 Register Class... static const MCPhysReg AFGR64[] = { - Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15, + Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15, }; // AFGR64 Bit set. static const uint8_t AFGR64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, - }; - - // FGR64_and_OddSP Register Class... - static const MCPhysReg FGR64_and_OddSP[] = { - Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, - }; - - // FGR64_and_OddSP Bit set. - static const uint8_t FGR64_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { - Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, }; // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. static const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, - }; - - // AFGR64_and_OddSP Register Class... - static const MCPhysReg AFGR64_and_OddSP[] = { - Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, - }; - - // AFGR64_and_OddSP Bit set. - static const uint8_t AFGR64_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_CPU16Regs Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { - Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, }; // GPR64_with_sub_32_in_CPU16Regs Bit set. static const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MoveP Register Class... static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { - Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP Bit set. static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16Zero Register Class... static const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { - Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, }; // GPR64_with_sub_32_in_GPRMM16Zero Bit set. static const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { - Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + }; + + // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class... + static const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = { + Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, + }; + + // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set. + static const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, + }; + + // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class... + static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = { + Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S5_64, Mips_S6_64, + }; + + // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set. + static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, }; // ACC64DSP Register Class... static const MCPhysReg ACC64DSP[] = { - Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3, + Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3, }; // ACC64DSP Bit set. static const uint8_t ACC64DSPBits[] = { - 0x00, 0x00, 0x00, 0x3c, + 0x00, 0x00, 0x00, 0x00, 0x0f, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { - Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, + Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { - Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64, + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + }; + + // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class... + static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = { + Mips_A1_64, Mips_A2_64, Mips_A3_64, + }; + + // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set. + static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, + }; + + // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class... + static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = { + Mips_A0_64, Mips_A1_64, Mips_A2_64, + }; + + // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set. + static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { - Mips_V0_64, Mips_V1_64, Mips_S1_64, + Mips_V0_64, Mips_V1_64, Mips_S1_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // OCTEON_MPL Register Class... static const MCPhysReg OCTEON_MPL[] = { - Mips_MPL0, Mips_MPL1, Mips_MPL2, + Mips_MPL0, Mips_MPL1, Mips_MPL2, }; // OCTEON_MPL Bit set. static const uint8_t OCTEON_MPLBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, }; // OCTEON_P Register Class... static const MCPhysReg OCTEON_P[] = { - Mips_P0, Mips_P1, Mips_P2, + Mips_P0, Mips_P1, Mips_P2, }; // OCTEON_P Bit set. static const uint8_t OCTEON_PBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, + }; + + // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class... + static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = { + Mips_A1_64, Mips_A2_64, + }; + + // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set. + static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, }; // ACC64 Register Class... static const MCPhysReg ACC64[] = { - Mips_AC0, + Mips_AC0, }; // ACC64 Bit set. static const uint8_t ACC64Bits[] = { - 0x00, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x01, + }; + + // GP64 Register Class... + static const MCPhysReg GP64[] = { + Mips_GP_64, + }; + + // GP64 Bit set. + static const uint8_t GP64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, }; // GPR64_with_sub_32_in_CPURAReg Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { - Mips_RA_64, + Mips_RA_64, }; // GPR64_with_sub_32_in_CPURAReg Bit set. static const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, }; - // GPR64_with_sub_32_in_CPUSPReg Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = { - Mips_SP_64, + // GPR64_with_sub_32_in_GPR32ZERO Register Class... + static const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = { + Mips_ZERO_64, }; - // GPR64_with_sub_32_in_CPUSPReg Bit set. - static const uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, + // GPR64_with_sub_32_in_GPR32ZERO Bit set. + static const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, }; // HI64 Register Class... static const MCPhysReg HI64[] = { - Mips_HI0_64, + Mips_HI0_64, }; // HI64 Bit set. static const uint8_t HI64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, }; // LO64 Register Class... static const MCPhysReg LO64[] = { - Mips_LO0_64, + Mips_LO0_64, }; // LO64 Bit set. static const uint8_t LO64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + }; + + // SP64 Register Class... + static const MCPhysReg SP64[] = { + Mips_SP_64, + }; + + // SP64 Bit set. + static const uint8_t SP64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, }; // MSA128B Register Class... static const MCPhysReg MSA128B[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128B Bit set. static const uint8_t MSA128BBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // MSA128D Register Class... static const MCPhysReg MSA128D[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128D Bit set. static const uint8_t MSA128DBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // MSA128H Register Class... static const MCPhysReg MSA128H[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128H Bit set. static const uint8_t MSA128HBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // MSA128W Register Class... static const MCPhysReg MSA128W[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128W Bit set. static const uint8_t MSA128WBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // MSA128B_with_sub_64_in_OddSP Register Class... - static const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = { - Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31, - }; - - // MSA128B_with_sub_64_in_OddSP Bit set. - static const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // MSA128WEvens Register Class... static const MCPhysReg MSA128WEvens[] = { - Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30, + Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30, }; // MSA128WEvens Bit set. static const uint8_t MSA128WEvensBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, }; // ACC128 Register Class... static const MCPhysReg ACC128[] = { - Mips_AC0_64, + Mips_AC0_64, }; // ACC128 Bit set. static const uint8_t ACC128Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; static const MCRegisterClass MipsMCRegisterClasses[] = { - { OddSP, OddSPBits, sizeof(OddSPBits) }, + { MSA128F16, MSA128F16Bits, sizeof(MSA128F16Bits) }, + { COP0Sel, COP0SelBits, sizeof(COP0SelBits) }, { CCR, CCRBits, sizeof(CCRBits) }, + { COP0, COP0Bits, sizeof(COP0Bits) }, { COP2, COP2Bits, sizeof(COP2Bits) }, { COP3, COP3Bits, sizeof(COP3Bits) }, { DSPR, DSPRBits, sizeof(DSPRBits) }, { FGR32, FGR32Bits, sizeof(FGR32Bits) }, { FGRCC, FGRCCBits, sizeof(FGRCCBits) }, - { FGRH32, FGRH32Bits, sizeof(FGRH32Bits) }, { GPR32, GPR32Bits, sizeof(GPR32Bits) }, + { GPRNM32, GPRNM32Bits, sizeof(GPRNM32Bits) }, { HWRegs, HWRegsBits, sizeof(HWRegsBits) }, - { OddSP_with_sub_hi, OddSP_with_sub_hiBits, sizeof(OddSP_with_sub_hiBits) }, - { FGR32_and_OddSP, FGR32_and_OddSPBits, sizeof(FGR32_and_OddSPBits) }, - { FGRH32_and_OddSP, FGRH32_and_OddSPBits, sizeof(FGRH32_and_OddSPBits) }, - { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits) }, + { MSACtrl, MSACtrlBits, sizeof(MSACtrlBits) }, + { GPR32NONZERO, GPR32NONZEROBits, sizeof(GPR32NONZEROBits) }, + { GPRNM32NZ, GPRNM32NZBits, sizeof(GPRNM32NZBits) }, + { GPRNM32_TAIL, GPRNM32_TAILBits, sizeof(GPRNM32_TAILBits) }, + { GPRNM4, GPRNM4Bits, sizeof(GPRNM4Bits) }, + { GPRNM4Z, GPRNM4ZBits, sizeof(GPRNM4ZBits) }, + { GPRNM4_and_GPRNM4Z, GPRNM4_and_GPRNM4ZBits, sizeof(GPRNM4_and_GPRNM4ZBits) }, { CPU16RegsPlusSP, CPU16RegsPlusSPBits, sizeof(CPU16RegsPlusSPBits) }, - { CC, CCBits, sizeof(CCBits) }, { CPU16Regs, CPU16RegsBits, sizeof(CPU16RegsBits) }, { FCC, FCCBits, sizeof(FCCBits) }, { GPRMM16, GPRMM16Bits, sizeof(GPRMM16Bits) }, { GPRMM16MoveP, GPRMM16MovePBits, sizeof(GPRMM16MovePBits) }, { GPRMM16Zero, GPRMM16ZeroBits, sizeof(GPRMM16ZeroBits) }, - { MSACtrl, MSACtrlBits, sizeof(MSACtrlBits) }, - { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits) }, + { GPRNM3, GPRNM3Bits, sizeof(GPRNM3Bits) }, + { GPRNM3Z, GPRNM3ZBits, sizeof(GPRNM3ZBits) }, + { GPRNM4_and_GPRNM32_TAIL, GPRNM4_and_GPRNM32_TAILBits, sizeof(GPRNM4_and_GPRNM32_TAILBits) }, { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, sizeof(CPU16Regs_and_GPRMM16ZeroBits) }, + { GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, sizeof(GPR32NONZERO_and_GPRMM16MovePBits) }, + { GPRNM3_and_GPRNM3Z, GPRNM3_and_GPRNM3ZBits, sizeof(GPRNM3_and_GPRNM3ZBits) }, + { GPRNM4Z_and_GPRNM32_TAIL, GPRNM4Z_and_GPRNM32_TAILBits, sizeof(GPRNM4Z_and_GPRNM32_TAILBits) }, + { GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, sizeof(GPRMM16MovePPairSecondBits) }, { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, sizeof(CPU16Regs_and_GPRMM16MovePBits) }, { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits) }, + { GPRNM2R1, GPRNM2R1Bits, sizeof(GPRNM2R1Bits) }, + { GPRNM2R2, GPRNM2R2Bits, sizeof(GPRNM2R2Bits) }, { HI32DSP, HI32DSPBits, sizeof(HI32DSPBits) }, { LO32DSP, LO32DSPBits, sizeof(LO32DSPBits) }, + { CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits) }, + { GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, sizeof(GPRMM16MovePPairFirstBits) }, { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits) }, + { GPRNM2R1_and_GPRNM2R2, GPRNM2R1_and_GPRNM2R2Bits, sizeof(GPRNM2R1_and_GPRNM2R2Bits) }, + { GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits) }, + { GPRNM1R1, GPRNM1R1Bits, sizeof(GPRNM1R1Bits) }, { CPURAReg, CPURARegBits, sizeof(CPURARegBits) }, { CPUSPReg, CPUSPRegBits, sizeof(CPUSPRegBits) }, { DSPCC, DSPCCBits, sizeof(DSPCCBits) }, + { GP32, GP32Bits, sizeof(GP32Bits) }, + { GPR32ZERO, GPR32ZEROBits, sizeof(GPR32ZEROBits) }, + { GPRNM1R1_and_GPRNM2R2, GPRNM1R1_and_GPRNM2R2Bits, sizeof(GPRNM1R1_and_GPRNM2R2Bits) }, + { GPRNMGP, GPRNMGPBits, sizeof(GPRNMGPBits) }, + { GPRNMRA, GPRNMRABits, sizeof(GPRNMRABits) }, + { GPRNMSP, GPRNMSPBits, sizeof(GPRNMSPBits) }, { HI32, HI32Bits, sizeof(HI32Bits) }, { LO32, LO32Bits, sizeof(LO32Bits) }, + { SP32, SP32Bits, sizeof(SP32Bits) }, { FGR64, FGR64Bits, sizeof(FGR64Bits) }, { GPR64, GPR64Bits, sizeof(GPR64Bits) }, + { GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits) }, { AFGR64, AFGR64Bits, sizeof(AFGR64Bits) }, - { FGR64_and_OddSP, FGR64_and_OddSPBits, sizeof(FGR64_and_OddSPBits) }, { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits) }, - { AFGR64_and_OddSP, AFGR64_and_OddSPBits, sizeof(AFGR64_and_OddSPBits) }, { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, sizeof(GPR64_with_sub_32_in_CPU16RegsBits) }, { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits) }, { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits) }, { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits) }, + { GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits) }, + { GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits) }, { ACC64DSP, ACC64DSPBits, sizeof(ACC64DSPBits) }, { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits) }, { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits) }, + { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits) }, + { GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits) }, { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits) }, { OCTEON_MPL, OCTEON_MPLBits, sizeof(OCTEON_MPLBits) }, { OCTEON_P, OCTEON_PBits, sizeof(OCTEON_PBits) }, + { GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits) }, { ACC64, ACC64Bits, sizeof(ACC64Bits) }, + { GP64, GP64Bits, sizeof(GP64Bits) }, { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, sizeof(GPR64_with_sub_32_in_CPURARegBits) }, - { GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, sizeof(GPR64_with_sub_32_in_CPUSPRegBits) }, + { GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits) }, { HI64, HI64Bits, sizeof(HI64Bits) }, { LO64, LO64Bits, sizeof(LO64Bits) }, + { SP64, SP64Bits, sizeof(SP64Bits) }, { MSA128B, MSA128BBits, sizeof(MSA128BBits) }, { MSA128D, MSA128DBits, sizeof(MSA128DBits) }, { MSA128H, MSA128HBits, sizeof(MSA128HBits) }, { MSA128W, MSA128WBits, sizeof(MSA128WBits) }, - { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, sizeof(MSA128B_with_sub_64_in_OddSPBits) }, { MSA128WEvens, MSA128WEvensBits, sizeof(MSA128WEvensBits) }, { ACC128, ACC128Bits, sizeof(ACC128Bits) }, }; -#endif // GET_REGINFO_MC_DESC \ No newline at end of file +static const uint16_t MipsRegEncodingTable[] = { + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 30, + 30, + 28, + 28, + 2, + 1, + 0, + 6, + 4, + 5, + 3, + 7, + 0, + 31, + 31, + 29, + 29, + 0, + 0, + 4, + 5, + 6, + 7, + 0, + 1, + 2, + 3, + 1, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 2, + 4, + 6, + 8, + 10, + 12, + 14, + 16, + 18, + 20, + 22, + 24, + 26, + 28, + 30, + 0, + 0, + 0, + 0, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 30, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 28, + 0, + 1, + 2, + 3, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 26, + 27, + 0, + 1, + 2, + 3, + 0, + 1, + 2, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 1, + 2, + 31, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 29, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 24, + 25, + 2, + 3, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 257, + 258, + 259, + 256, + 484, + 864, + 416, + 482, + 483, + 352, + 512, + 128, + 129, + 288, + 931, + 899, + 736, + 132, + 768, + 992, + 930, + 898, + 481, + 320, + 448, + 832, + 960, + 97, + 391, + 224, + 929, + 897, + 0, + 385, + 928, + 896, + 544, + 545, + 546, + 133, + 1, + 450, + 421, + 161, + 160, + 480, + 165, + 198, + 166, + 167, + 32, + 386, + 387, + 384, + 66, + 69, + 68, + 103, + 67, + 70, + 71, + 65, + 737, + 741, + 740, + 130, + 388, + 420, + 4, + 33, + 39, + 37, + 38, + 192, + 640, + 131, + 36, + 26, + 27, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 12, + 13, + 14, + 15, + 2, + 3, + 24, + 25, + 4, + 5, + 6, + 7, + 0, + 513, + 514, + 515, + 516, + 517, + 742, + 64, + 96, + 390, + 324, + 325, + 326, + 994, + 995, + 996, + 997, + 998, + 999, + 2, + 3, + 801, + 803, + 805, + 807, + 809, + 811, + 813, + 815, + 800, + 802, + 804, + 806, + 808, + 810, + 812, + 814, + 162, + 163, + 164, + 193, + 194, + 195, + 196, + 197, + 389, + 738, + 770, + 739, + 771, + 34, + 35, + 608, + 609, + 610, + 611, + 612, + 613, + 614, + 615, + 616, + 617, + 618, + 619, + 620, + 621, + 622, + 623, + 576, + 577, + 578, + 579, + 580, + 581, + 582, + 583, + 584, + 585, + 586, + 587, + 588, + 589, + 590, + 591, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 0, + 26, + 27, + 0, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 24, + 25, + 2, + 3, + 356, +}; +#endif // GET_REGINFO_MC_DESC + + + diff --git a/arch/Mips/MipsGenSubtargetInfo.inc b/arch/Mips/MipsGenSubtargetInfo.inc index 36e7a7f86..8501cd9e2 100644 --- a/arch/Mips/MipsGenSubtargetInfo.inc +++ b/arch/Mips/MipsGenSubtargetInfo.inc @@ -1,52 +1,83 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Subtarget Enumeration Source Fragment *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ #ifdef GET_SUBTARGETINFO_ENUM #undef GET_SUBTARGETINFO_ENUM -#define Mips_FeatureCnMips (1ULL << 0) -#define Mips_FeatureDSP (1ULL << 1) -#define Mips_FeatureDSPR2 (1ULL << 2) -#define Mips_FeatureFP64Bit (1ULL << 3) -#define Mips_FeatureFPXX (1ULL << 4) -#define Mips_FeatureGP64Bit (1ULL << 5) -#define Mips_FeatureMSA (1ULL << 6) -#define Mips_FeatureMicroMips (1ULL << 7) -#define Mips_FeatureMips1 (1ULL << 8) -#define Mips_FeatureMips2 (1ULL << 9) -#define Mips_FeatureMips3 (1ULL << 10) -#define Mips_FeatureMips3_32 (1ULL << 11) -#define Mips_FeatureMips3_32r2 (1ULL << 12) -#define Mips_FeatureMips4 (1ULL << 13) -#define Mips_FeatureMips4_32 (1ULL << 14) -#define Mips_FeatureMips4_32r2 (1ULL << 15) -#define Mips_FeatureMips5 (1ULL << 16) -#define Mips_FeatureMips5_32r2 (1ULL << 17) -#define Mips_FeatureMips16 (1ULL << 18) -#define Mips_FeatureMips32 (1ULL << 19) -#define Mips_FeatureMips32r2 (1ULL << 20) -#define Mips_FeatureMips32r3 (1ULL << 21) -#define Mips_FeatureMips32r5 (1ULL << 22) -#define Mips_FeatureMips32r6 (1ULL << 23) -#define Mips_FeatureMips64 (1ULL << 24) -#define Mips_FeatureMips64r2 (1ULL << 25) -#define Mips_FeatureMips64r3 (1ULL << 26) -#define Mips_FeatureMips64r5 (1ULL << 27) -#define Mips_FeatureMips64r6 (1ULL << 28) -#define Mips_FeatureNaN2008 (1ULL << 29) -#define Mips_FeatureNoABICalls (1ULL << 30) -#define Mips_FeatureNoOddSPReg (1ULL << 31) -#define Mips_FeatureSingleFloat (1ULL << 32) -#define Mips_FeatureVFPU (1ULL << 33) - +enum { + Mips_FeatureAbs2008 = 0, + Mips_FeatureCRC = 1, + Mips_FeatureCnMips = 2, + Mips_FeatureCnMipsP = 3, + Mips_FeatureDSP = 4, + Mips_FeatureDSPR2 = 5, + Mips_FeatureDSPR3 = 6, + Mips_FeatureEVA = 7, + Mips_FeatureFP64Bit = 8, + Mips_FeatureFPXX = 9, + Mips_FeatureGINV = 10, + Mips_FeatureGP64Bit = 11, + Mips_FeatureI7200 = 12, + Mips_FeatureLongCalls = 13, + Mips_FeatureMSA = 14, + Mips_FeatureMT = 15, + Mips_FeatureMicroMips = 16, + Mips_FeatureMips1 = 17, + Mips_FeatureMips2 = 18, + Mips_FeatureMips3 = 19, + Mips_FeatureMips3D = 20, + Mips_FeatureMips3_32 = 21, + Mips_FeatureMips3_32r2 = 22, + Mips_FeatureMips4 = 23, + Mips_FeatureMips4_32 = 24, + Mips_FeatureMips4_32r2 = 25, + Mips_FeatureMips5 = 26, + Mips_FeatureMips5_32r2 = 27, + Mips_FeatureMips16 = 28, + Mips_FeatureMips32 = 29, + Mips_FeatureMips32r2 = 30, + Mips_FeatureMips32r3 = 31, + Mips_FeatureMips32r5 = 32, + Mips_FeatureMips32r6 = 33, + Mips_FeatureMips64 = 34, + Mips_FeatureMips64r2 = 35, + Mips_FeatureMips64r3 = 36, + Mips_FeatureMips64r5 = 37, + Mips_FeatureMips64r6 = 38, + Mips_FeatureNMS1 = 39, + Mips_FeatureNaN2008 = 40, + Mips_FeatureNanoMips = 41, + Mips_FeatureNoABICalls = 42, + Mips_FeatureNoMadd4 = 43, + Mips_FeatureNoOddSPReg = 44, + Mips_FeaturePCRel = 45, + Mips_FeaturePTR64Bit = 46, + Mips_FeatureRelax = 47, + Mips_FeatureSingleFloat = 48, + Mips_FeatureSoftFloat = 49, + Mips_FeatureSym32 = 50, + Mips_FeatureTLB = 51, + Mips_FeatureUseAbsoluteJumpTables = 52, + Mips_FeatureUseIndirectJumpsHazard = 53, + Mips_FeatureUseTCCInDIV = 54, + Mips_FeatureVFPU = 55, + Mips_FeatureVirt = 56, + Mips_FeatureXGOT = 57, + Mips_FeatureXformHw110880 = 58, + Mips_ImplP5600 = 59, + Mips_NumSubtargetFeatures = 60 +}; #endif // GET_SUBTARGETINFO_ENUM + + diff --git a/arch/Mips/MipsInstPrinter.c b/arch/Mips/MipsInstPrinter.c index 9b00ad924..eda806294 100644 --- a/arch/Mips/MipsInstPrinter.c +++ b/arch/Mips/MipsInstPrinter.c @@ -1,9 +1,22 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -11,251 +24,257 @@ // //===----------------------------------------------------------------------===// -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#ifdef CAPSTONE_HAS_MIPS - -#include -#include -#include // debug +#include #include +#include +#include -#include "MipsInstPrinter.h" -#include "../../MCInst.h" -#include "../../utils.h" -#include "../../SStream.h" -#include "../../MCRegisterInfo.h" #include "MipsMapping.h" - #include "MipsInstPrinter.h" -static void printUnsignedImm(MCInst *MI, int opNum, SStream *O); -static char *printAliasInstr(MCInst *MI, SStream *O, void *info); -static char *printAlias(MCInst *MI, SStream *OS); - -// These enumeration declarations were originally in MipsInstrInfo.h but -// had to be moved here to avoid circular dependencies between -// LLVMMipsCodeGen and LLVMMipsAsmPrinter. - -// Mips Condition Codes -typedef enum Mips_CondCode { - // To be used with float branch True - Mips_FCOND_F, - Mips_FCOND_UN, - Mips_FCOND_OEQ, - Mips_FCOND_UEQ, - Mips_FCOND_OLT, - Mips_FCOND_ULT, - Mips_FCOND_OLE, - Mips_FCOND_ULE, - Mips_FCOND_SF, - Mips_FCOND_NGLE, - Mips_FCOND_SEQ, - Mips_FCOND_NGL, - Mips_FCOND_LT, - Mips_FCOND_NGE, - Mips_FCOND_LE, - Mips_FCOND_NGT, - - // To be used with float branch False - // This conditions have the same mnemonic as the - // above ones, but are used with a branch False; - Mips_FCOND_T, - Mips_FCOND_OR, - Mips_FCOND_UNE, - Mips_FCOND_ONE, - Mips_FCOND_UGE, - Mips_FCOND_OGE, - Mips_FCOND_UGT, - Mips_FCOND_OGT, - Mips_FCOND_ST, - Mips_FCOND_GLE, - Mips_FCOND_SNE, - Mips_FCOND_GL, - Mips_FCOND_NLT, - Mips_FCOND_GE, - Mips_FCOND_NLE, - Mips_FCOND_GT -} Mips_CondCode; +#define GET_SUBTARGETINFO_ENUM +#include "MipsGenSubtargetInfo.inc" #define GET_INSTRINFO_ENUM #include "MipsGenInstrInfo.inc" -static const char *getRegisterName(unsigned RegNo); -static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI); +#define GET_REGINFO_ENUM +#include "MipsGenRegisterInfo.inc" -static void set_mem_access(MCInst *MI, bool status) +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b + +#define DEBUG_TYPE "asm-printer" + +#define PRINT_ALIAS_INSTR +#include "MipsGenAsmWriter.inc" + +static bool isReg(const MCInst *MI, unsigned OpNo, unsigned R) { - MI->csh->doing_mem = status; - - if (MI->csh->detail_opt != CS_OPT_ON) - return; - - if (status) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0; - } else { - // done, create the next operand slot - MI->flat_insn->detail->mips.op_count++; - } + return MCOperand_getReg(MCInst_getOperand((MCInst *)MI, (OpNo))) == R; } -static bool isReg(MCInst *MI, unsigned OpNo, unsigned R) -{ - return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) && - MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R); -} - -static const char* MipsFCCToString(Mips_CondCode CC) +static const char *MipsFCCToString(Mips_CondCode CC) { switch (CC) { - default: return 0; // never reach - case Mips_FCOND_F: - case Mips_FCOND_T: return "f"; - case Mips_FCOND_UN: - case Mips_FCOND_OR: return "un"; - case Mips_FCOND_OEQ: - case Mips_FCOND_UNE: return "eq"; - case Mips_FCOND_UEQ: - case Mips_FCOND_ONE: return "ueq"; - case Mips_FCOND_OLT: - case Mips_FCOND_UGE: return "olt"; - case Mips_FCOND_ULT: - case Mips_FCOND_OGE: return "ult"; - case Mips_FCOND_OLE: - case Mips_FCOND_UGT: return "ole"; - case Mips_FCOND_ULE: - case Mips_FCOND_OGT: return "ule"; - case Mips_FCOND_SF: - case Mips_FCOND_ST: return "sf"; - case Mips_FCOND_NGLE: - case Mips_FCOND_GLE: return "ngle"; - case Mips_FCOND_SEQ: - case Mips_FCOND_SNE: return "seq"; - case Mips_FCOND_NGL: - case Mips_FCOND_GL: return "ngl"; - case Mips_FCOND_LT: - case Mips_FCOND_NLT: return "lt"; - case Mips_FCOND_NGE: - case Mips_FCOND_GE: return "nge"; - case Mips_FCOND_LE: - case Mips_FCOND_NLE: return "le"; - case Mips_FCOND_NGT: - case Mips_FCOND_GT: return "ngt"; + case Mips_FCOND_F: + case Mips_FCOND_T: + return "f"; + case Mips_FCOND_UN: + case Mips_FCOND_OR: + return "un"; + case Mips_FCOND_OEQ: + case Mips_FCOND_UNE: + return "eq"; + case Mips_FCOND_UEQ: + case Mips_FCOND_ONE: + return "ueq"; + case Mips_FCOND_OLT: + case Mips_FCOND_UGE: + return "olt"; + case Mips_FCOND_ULT: + case Mips_FCOND_OGE: + return "ult"; + case Mips_FCOND_OLE: + case Mips_FCOND_UGT: + return "ole"; + case Mips_FCOND_ULE: + case Mips_FCOND_OGT: + return "ule"; + case Mips_FCOND_SF: + case Mips_FCOND_ST: + return "sf"; + case Mips_FCOND_NGLE: + case Mips_FCOND_GLE: + return "ngle"; + case Mips_FCOND_SEQ: + case Mips_FCOND_SNE: + return "seq"; + case Mips_FCOND_NGL: + case Mips_FCOND_GL: + return "ngl"; + case Mips_FCOND_LT: + case Mips_FCOND_NLT: + return "lt"; + case Mips_FCOND_NGE: + case Mips_FCOND_GE: + return "nge"; + case Mips_FCOND_LE: + case Mips_FCOND_NLE: + return "le"; + case Mips_FCOND_NGT: + case Mips_FCOND_GT: + return "ngt"; + } + assert(0 && "Impossible condition code!"); + return ""; +} + +const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName); + +static void printRegName(MCInst *MI, SStream *OS, MCRegister Reg) +{ + int syntax_opt = MI->csh->syntax; + if (!(syntax_opt & CS_OPT_SYNTAX_NO_DOLLAR)) { + SStream_concat1(OS, '$'); + } + SStream_concat0(OS, Mips_LLVM_getRegisterName(Reg, syntax_opt & CS_OPT_SYNTAX_NOREGNAME)); +} + +void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O) { + bool useAliasDetails = map_use_alias_details(MI); + if (!useAliasDetails) { + SStream_Close(O); + printInstruction(MI, Address, O); + SStream_Open(O); + map_set_fill_detail_ops(MI, false); + } + + if (printAliasInstr(MI, Address, O) || + printAlias4(MI, Address, O)) { + MCInst_setIsAlias(MI, true); + } else { + printInstruction(MI, Address, O); + } + + if (!useAliasDetails) { + map_set_fill_detail_ops(MI, true); } } -static void printRegName(SStream *OS, unsigned RegNo) +void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { - SStream_concat(OS, "$%s", getRegisterName(RegNo)); -} - -void Mips_printInst(MCInst *MI, SStream *O, void *info) -{ - char *mnem; - switch (MCInst_getOpcode(MI)) { - default: break; - case Mips_Save16: - case Mips_SaveX16: - case Mips_Restore16: - case Mips_RestoreX16: - return; + default: + break; + case Mips_AND16_NM: + case Mips_XOR16_NM: + case Mips_OR16_NM: + if (MCInst_getNumOperands(MI) == 2 && OpNo == 2) + OpNo = 0; // rt, rs -> rt, rs, rt + break; + case Mips_ADDu4x4_NM: + case Mips_MUL4x4_NM: + if (MCInst_getNumOperands(MI) == 2 && OpNo > 0) + OpNo = OpNo - 1; // rt, rs -> rt, rt, rs + break; } - // Try to print any aliases first. - mnem = printAliasInstr(MI, O, info); - if (!mnem) { - mnem = printAlias(MI, O); - if (!mnem) { - printInstruction(MI, O, NULL); - } - } - - if (mnem) { - // fixup instruction id due to the change in alias instruction - MCInst_setOpcodePub(MI, Mips_map_insn(mnem)); - cs_mem_free(mnem); - } -} - -static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - MCOperand *Op; - - if (OpNo >= MI->size) - return; - - Op = MCInst_getOperand(MI, OpNo); + MCOperand *Op = MCInst_getOperand(MI, (OpNo)); if (MCOperand_isReg(Op)) { - unsigned int reg = MCOperand_getReg(Op); - printRegName(O, reg); - reg = Mips_map_register(reg); - if (MI->csh->detail_opt) { - if (MI->csh->doing_mem) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg; - } else { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; - MI->flat_insn->detail->mips.op_count++; - } - } - } else if (MCOperand_isImm(Op)) { - int64_t imm = MCOperand_getImm(Op); - if (MI->csh->doing_mem) { - if (imm) { // only print Imm offset if it is not 0 - printInt64(O, imm); - } - if (MI->csh->detail_opt) - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm; - } else { - printInt64(O, imm); + add_cs_detail(MI, Mips_OP_GROUP_Operand, OpNo); + printRegName(MI, O, MCOperand_getReg(Op)); + return; + } - if (MI->csh->detail_opt) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; - MI->flat_insn->detail->mips.op_count++; - } + + if (MCOperand_isImm(Op)) { + switch (MCInst_getOpcode(MI)) { + case Mips_LI48_NM: + case Mips_ANDI16_NM: + case Mips_ANDI_NM: + case Mips_ORI_NM: + case Mips_XORI_NM: + case Mips_TEQ_NM: + case Mips_TNE_NM: + case Mips_SIGRIE_NM: + case Mips_SDBBP_NM: + case Mips_SDBBP16_NM: + case Mips_BREAK_NM: + case Mips_BREAK16_NM: + case Mips_SYSCALL_NM: + case Mips_SYSCALL16_NM: + case Mips_WAIT_NM: + CONCAT(printUImm, CONCAT(32, 0)) + (MI, OpNo, O); + break; + default: + add_cs_detail(MI, Mips_OP_GROUP_Operand, OpNo); + printInt64(O, MCOperand_getImm(Op)); + break; } + return; } } -static void printUnsignedImm(MCInst *MI, int opNum, SStream *O) +static void printJumpOperand(MCInst *MI, unsigned OpNo, SStream *O) { - MCOperand *MO = MCInst_getOperand(MI, opNum); - if (MCOperand_isImm(MO)) { - int64_t imm = MCOperand_getImm(MO); - printInt64(O, imm); + add_cs_detail(MI, Mips_OP_GROUP_JumpOperand, OpNo); + MCOperand *Op = MCInst_getOperand(MI, (OpNo)); + if (MCOperand_isReg(Op)) + return printRegName(MI, O, MCOperand_getReg(Op)); - if (MI->csh->detail_opt) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm; - MI->flat_insn->detail->mips.op_count++; - } - } else - printOperand(MI, opNum, O); + printInt64(O, MCOperand_getImm(Op)); } -static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O) +static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, SStream *O) { - MCOperand *MO = MCInst_getOperand(MI, opNum); - if (MCOperand_isImm(MO)) { - uint8_t imm = (uint8_t)MCOperand_getImm(MO); - if (imm > HEX_THRESHOLD) - SStream_concat(O, "0x%x", imm); - else - SStream_concat(O, "%u", imm); - if (MI->csh->detail_opt) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; - MI->flat_insn->detail->mips.op_count++; - } - } else - printOperand(MI, opNum, O); + add_cs_detail(MI, Mips_OP_GROUP_BranchOperand, OpNo); + MCOperand *Op = MCInst_getOperand(MI, (OpNo)); + if (MCOperand_isReg(Op)) + return printRegName(MI, O, MCOperand_getReg(Op)); + + uint64_t Target = Address + MCOperand_getImm(Op); + printInt64(O, Target); } +#define DEFINE_printUImm(Bits) \ + static void CONCAT(printUImm, CONCAT(Bits, 0))(MCInst * MI, int opNum, \ + SStream *O) \ + { \ + add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), opNum); \ + MCOperand *MO = MCInst_getOperand(MI, (opNum)); \ + if (MCOperand_isImm(MO)) { \ + uint64_t Imm = MCOperand_getImm(MO); \ + Imm &= (((uint64_t)1) << Bits) - 1; \ + printUInt64(O, Imm); \ + return; \ + } \ + MCOperand *Op = MCInst_getOperand(MI, (opNum)); \ + printRegName(MI, O, MCOperand_getReg(Op)); \ + } + +#define DEFINE_printUImm_2(Bits, Offset) \ + static void CONCAT(printUImm, CONCAT(Bits, Offset))(MCInst * MI, int opNum, \ + SStream *O) \ + { \ + add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, Offset)), \ + opNum); \ + MCOperand *MO = MCInst_getOperand(MI, (opNum)); \ + if (MCOperand_isImm(MO)) { \ + uint64_t Imm = MCOperand_getImm(MO); \ + Imm -= Offset; \ + Imm &= (1 << Bits) - 1; \ + Imm += Offset; \ + printUInt64(O, Imm); \ + return; \ + } \ + MCOperand *Op = MCInst_getOperand(MI, (opNum)); \ + printRegName(MI, O, MCOperand_getReg(Op)); \ + } + +DEFINE_printUImm(0); +DEFINE_printUImm(1); +DEFINE_printUImm(10); +DEFINE_printUImm(12); +DEFINE_printUImm(16); +DEFINE_printUImm(2); +DEFINE_printUImm(20); +DEFINE_printUImm(26); +DEFINE_printUImm(3); +DEFINE_printUImm(32); +DEFINE_printUImm(4); +DEFINE_printUImm(5); +DEFINE_printUImm(6); +DEFINE_printUImm(7); +DEFINE_printUImm(8); +DEFINE_printUImm_2(2, 1); +DEFINE_printUImm_2(5, 1); +DEFINE_printUImm_2(5, 32); +DEFINE_printUImm_2(5, 33); +DEFINE_printUImm_2(6, 1); +DEFINE_printUImm_2(6, 2); + static void printMemOperand(MCInst *MI, int opNum, SStream *O) { // Load/Store memory operands -- imm($reg) @@ -265,160 +284,348 @@ static void printMemOperand(MCInst *MI, int opNum, SStream *O) // opNum can be invalid if instruction had reglist as operand. // MemOperand is always last operand of instruction (base + offset). switch (MCInst_getOpcode(MI)) { - default: - break; - case Mips_SWM32_MM: - case Mips_LWM32_MM: - case Mips_SWM16_MM: - case Mips_LWM16_MM: - opNum = MCInst_getNumOperands(MI) - 2; - break; + default: + break; + case Mips_SWM32_MM: + case Mips_LWM32_MM: + case Mips_SWM16_MM: + case Mips_SWM16_MMR6: + case Mips_LWM16_MM: + case Mips_LWM16_MMR6: + opNum = MCInst_getNumOperands(MI) - 2; + break; } set_mem_access(MI, true); - printOperand(MI, opNum + 1, O); + // Index register is encoded as immediate value + // in case of nanoMIPS indexed instructions + switch (MCInst_getOpcode(MI)) { + // No offset needed for paired LL/SC + case Mips_LLWP_NM: + case Mips_SCWP_NM: + break; + case Mips_LWX_NM: + case Mips_LWXS_NM: + case Mips_LWXS16_NM: + case Mips_LBX_NM: + case Mips_LBUX_NM: + case Mips_LHX_NM: + case Mips_LHUX_NM: + case Mips_LHXS_NM: + case Mips_LHUXS_NM: + case Mips_SWX_NM: + case Mips_SWXS_NM: + case Mips_SBX_NM: + case Mips_SHX_NM: + case Mips_SHXS_NM: + if (!MCOperand_isReg(MCInst_getOperand(MI, (opNum + 1)))) { + add_cs_detail(MI, Mips_OP_GROUP_MemOperand, (opNum + 1)); + printRegName(MI, O, MCOperand_getImm(MCInst_getOperand( + MI, (opNum + 1)))); + break; + } + // Fall through + default: + printOperand((MCInst *)MI, opNum + 1, O); + break; + } SStream_concat0(O, "("); - printOperand(MI, opNum, O); + printOperand((MCInst *)MI, opNum, O); SStream_concat0(O, ")"); set_mem_access(MI, false); } -// TODO??? static void printMemOperandEA(MCInst *MI, int opNum, SStream *O) { // when using stack locations for not load/store instructions // print the same way as all normal 3 operand instructions. - printOperand(MI, opNum, O); + printOperand((MCInst *)MI, opNum, O); SStream_concat0(O, ", "); - printOperand(MI, opNum + 1, O); - return; + printOperand((MCInst *)MI, opNum + 1, O); } static void printFCCOperand(MCInst *MI, int opNum, SStream *O) { - MCOperand *MO = MCInst_getOperand(MI, opNum); - SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO))); + MCOperand *MO = MCInst_getOperand(MI, (opNum)); + SStream_concat0(O, + MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO))); } -static void printRegisterPair(MCInst *MI, int opNum, SStream *O) +static bool printAlias(const char *Str, const MCInst *MI, uint64_t Address, + unsigned OpNo, SStream *OS, bool IsBranch) { - printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum))); + SStream_concat(OS, "%s%s", "\t", Str); + SStream_concat0(OS, "\t"); + if (IsBranch) + printBranchOperand((MCInst *)MI, Address, OpNo, OS); + else + printOperand((MCInst *)MI, OpNo, OS); + return true; } -static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS) +static bool printAlias2(const char *Str, const MCInst *MI, uint64_t Address, + unsigned OpNo0, unsigned OpNo1, SStream *OS, bool IsBranch) { - SStream_concat(OS, "%s\t", Str); - printOperand(MI, OpNo, OS); - return cs_strdup(Str); -} - -static char *printAlias2(const char *Str, MCInst *MI, - unsigned OpNo0, unsigned OpNo1, SStream *OS) -{ - char *tmp; - - tmp = printAlias1(Str, MI, OpNo0, OS); + printAlias(Str, MI, Address, OpNo0, OS, IsBranch); SStream_concat0(OS, ", "); - printOperand(MI, OpNo1, OS); - - return tmp; + if (IsBranch) + printBranchOperand((MCInst *)MI, Address, OpNo1, OS); + else + printOperand((MCInst *)MI, OpNo1, OS); + return true; } -#define GET_REGINFO_ENUM -#include "MipsGenRegisterInfo.inc" +static bool printAlias3(const char *Str, const MCInst *MI, uint64_t Address, + unsigned OpNo0, unsigned OpNo1, unsigned OpNo2, SStream *OS) +{ + printAlias(Str, MI, Address, OpNo0, OS, false); + SStream_concat0(OS, ", "); + printOperand((MCInst *)MI, OpNo1, OS); + SStream_concat0(OS, ", "); + printOperand((MCInst *)MI, OpNo2, OS); + return true; +} -static char *printAlias(MCInst *MI, SStream *OS) +static bool printAlias4(const MCInst *MI, uint64_t Address, SStream *OS) { switch (MCInst_getOpcode(MI)) { - case Mips_BEQ: - case Mips_BEQ_MM: - // beq $zero, $zero, $L2 => b $L2 - // beq $r0, $zero, $L2 => beqz $r0, $L2 - if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO)) - return printAlias1("b", MI, 2, OS); - if (isReg(MI, 1, Mips_ZERO)) - return printAlias2("beqz", MI, 0, 2, OS); - return NULL; - case Mips_BEQ64: - // beq $r0, $zero, $L2 => beqz $r0, $L2 - if (isReg(MI, 1, Mips_ZERO_64)) - return printAlias2("beqz", MI, 0, 2, OS); - return NULL; - case Mips_BNE: - // bne $r0, $zero, $L2 => bnez $r0, $L2 - if (isReg(MI, 1, Mips_ZERO)) - return printAlias2("bnez", MI, 0, 2, OS); - return NULL; - case Mips_BNE64: - // bne $r0, $zero, $L2 => bnez $r0, $L2 - if (isReg(MI, 1, Mips_ZERO_64)) - return printAlias2("bnez", MI, 0, 2, OS); - return NULL; - case Mips_BGEZAL: - // bgezal $zero, $L1 => bal $L1 - if (isReg(MI, 0, Mips_ZERO)) - return printAlias1("bal", MI, 1, OS); - return NULL; - case Mips_BC1T: - // bc1t $fcc0, $L1 => bc1t $L1 - if (isReg(MI, 0, Mips_FCC0)) - return printAlias1("bc1t", MI, 1, OS); - return NULL; - case Mips_BC1F: - // bc1f $fcc0, $L1 => bc1f $L1 - if (isReg(MI, 0, Mips_FCC0)) - return printAlias1("bc1f", MI, 1, OS); - return NULL; - case Mips_JALR: - // jalr $ra, $r1 => jalr $r1 - if (isReg(MI, 0, Mips_RA)) - return printAlias1("jalr", MI, 1, OS); - return NULL; - case Mips_JALR64: - // jalr $ra, $r1 => jalr $r1 - if (isReg(MI, 0, Mips_RA_64)) - return printAlias1("jalr", MI, 1, OS); - return NULL; - case Mips_NOR: - case Mips_NOR_MM: - // nor $r0, $r1, $zero => not $r0, $r1 - if (isReg(MI, 2, Mips_ZERO)) - return printAlias2("not", MI, 0, 1, OS); - return NULL; - case Mips_NOR64: - // nor $r0, $r1, $zero => not $r0, $r1 - if (isReg(MI, 2, Mips_ZERO_64)) - return printAlias2("not", MI, 0, 1, OS); - return NULL; - case Mips_OR: - // or $r0, $r1, $zero => move $r0, $r1 - if (isReg(MI, 2, Mips_ZERO)) - return printAlias2("move", MI, 0, 1, OS); - return NULL; - default: return NULL; + case Mips_BEQ: + case Mips_BEQ_MM: + // beq $zero, $zero, $L2 => b $L2 + // beq $r0, $zero, $L2 => beqz $r0, $L2 + return (isReg(MI, 0, Mips_ZERO) && + isReg(MI, 1, Mips_ZERO) && + printAlias("b", MI, Address, 2, OS, true)) || + (isReg(MI, 1, Mips_ZERO) && + printAlias2("beqz", MI, Address, 0, 2, OS, true)); + case Mips_BEQ64: + // beq $r0, $zero, $L2 => beqz $r0, $L2 + return isReg(MI, 1, Mips_ZERO_64) && + printAlias2("beqz", MI, Address, 0, 2, OS, true); + case Mips_BNE: + case Mips_BNE_MM: + // bne $r0, $zero, $L2 => bnez $r0, $L2 + return isReg(MI, 1, Mips_ZERO) && + printAlias2("bnez", MI, Address, 0, 2, OS, true); + case Mips_BNE64: + // bne $r0, $zero, $L2 => bnez $r0, $L2 + return isReg(MI, 1, Mips_ZERO_64) && + printAlias2("bnez", MI, Address, 0, 2, OS, true); + case Mips_BGEZAL: + // bgezal $zero, $L1 => bal $L1 + return isReg(MI, 0, Mips_ZERO) && + printAlias("bal", MI, Address, 1, OS, true); + case Mips_BC1T: + // bc1t $fcc0, $L1 => bc1t $L1 + return isReg(MI, 0, Mips_FCC0) && + printAlias("bc1t", MI, Address, 1, OS, true); + case Mips_BC1F: + // bc1f $fcc0, $L1 => bc1f $L1 + return isReg(MI, 0, Mips_FCC0) && + printAlias("bc1f", MI, Address, 1, OS, true); + case Mips_JALR: + // jalr $zero, $r1 => jr $r1 + // jalr $ra, $r1 => jalr $r1 + return (isReg(MI, 0, Mips_ZERO) && + printAlias("jr", MI, Address, 1, OS, false)) || + (isReg(MI, 0, Mips_RA) && + printAlias("jalr", MI, Address, 1, OS, false)); + case Mips_JALR64: + // jalr $zero, $r1 => jr $r1 + // jalr $ra, $r1 => jalr $r1 + return (isReg(MI, 0, Mips_ZERO_64) && + printAlias("jr", MI, Address, 1, OS, false)) || + (isReg(MI, 0, Mips_RA_64) && + printAlias("jalr", MI, Address, 1, OS, false)); + case Mips_NOR: + case Mips_NOR_MM: + case Mips_NOR_MMR6: + // nor $r0, $r1, $zero => not $r0, $r1 + return isReg(MI, 2, Mips_ZERO) && + printAlias2("not", MI, Address, 0, 1, OS, false); + case Mips_NOR64: + // nor $r0, $r1, $zero => not $r0, $r1 + return isReg(MI, 2, Mips_ZERO_64) && + printAlias2("not", MI, Address, 0, 1, OS, false); + case Mips_OR: + case Mips_ADDu: + // or $r0, $r1, $zero => move $r0, $r1 + // addu $r0, $r1, $zero => move $r0, $r1 + return isReg(MI, 2, Mips_ZERO) && + printAlias2("move", MI, Address, 0, 1, OS, false); + case Mips_LI48_NM: + case Mips_LI16_NM: + // li[16/48] $r0, imm => li $r0, imm + return printAlias2("li", MI, Address, 0, 1, OS, false); + case Mips_ADDIU_NM: + case Mips_ADDIUNEG_NM: + if (isReg(MI, 1, Mips_ZERO_NM)) + return printAlias2("li", MI, Address, 0, 2, OS, false); + else + return printAlias3("addiu", MI, Address, 0, 1, 2, OS); + case Mips_ADDIU48_NM: + case Mips_ADDIURS5_NM: + case Mips_ADDIUR1SP_NM: + case Mips_ADDIUR2_NM: + case Mips_ADDIUGPB_NM: + case Mips_ADDIUGPW_NM: + return printAlias3("addiu", MI, Address, 0, 1, 2, OS); + case Mips_ANDI16_NM: + case Mips_ANDI_NM: + // andi[16/32] $r0, $r1, imm => andi $r0, $r1, imm + return printAlias3("andi", MI, Address, 0, 1, 2, OS); + default: + return false; } } static void printRegisterList(MCInst *MI, int opNum, SStream *O) { - int i, e, reg; - // - 2 because register List is always first operand of instruction and it is // always followed by memory operand (base + offset). - for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) { + add_cs_detail(MI, Mips_OP_GROUP_RegisterList, opNum); + for (int i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) { if (i != opNum) SStream_concat0(O, ", "); - reg = MCOperand_getReg(MCInst_getOperand(MI, i)); - printRegName(O, reg); - if (MI->csh->detail_opt) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; - MI->flat_insn->detail->mips.op_count++; - } + printRegName(MI, O, MCOperand_getReg(MCInst_getOperand(MI, (i)))); } } -#define PRINT_ALIAS_INSTR -#include "MipsGenAsmWriter.inc" +static void printNanoMipsRegisterList(MCInst *MI, int OpNum, SStream *O) +{ + add_cs_detail(MI, Mips_OP_GROUP_NanoMipsRegisterList, OpNum); + for (unsigned I = OpNum; I < MCInst_getNumOperands(MI); I++) { + SStream_concat0(O, ", "); + printRegName(MI, O, MCOperand_getReg(MCInst_getOperand(MI, (I)))); + } +} -#endif +static void printHi20(MCInst *MI, int OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); + if (MCOperand_isImm(MO)) { + add_cs_detail(MI, Mips_OP_GROUP_Hi20, OpNum); + SStream_concat0(O, "%hi("); + printUInt64(O, MCOperand_getImm(MO)); + SStream_concat0(O, ")"); + } else + printOperand(MI, OpNum, O); +} + +static void printHi20PCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); + if (MCOperand_isImm(MO)) { + add_cs_detail(MI, Mips_OP_GROUP_Hi20PCRel, OpNum); + SStream_concat0(O, "%pcrel_hi("); + printUInt64(O, MCOperand_getImm(MO) + Address); + SStream_concat0(O, ")"); + } else + printOperand(MI, OpNum, O); +} + +static void printPCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); + if (MCOperand_isImm(MO)) { + add_cs_detail(MI, Mips_OP_GROUP_PCRel, OpNum); + printUInt64(O, MCOperand_getImm(MO) + Address); + } + else + printOperand(MI, OpNum, O); +} + +const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName) +{ + if (!RegNo || RegNo >= MIPS_REG_ENDING) { + return NULL; + } + if (noRegName) { + return getRegisterName(RegNo); + } + switch(RegNo) { + case MIPS_REG_AT: + case MIPS_REG_AT_64: + return "at"; + case MIPS_REG_A0: + case MIPS_REG_A0_64: + return "a0"; + case MIPS_REG_A1: + case MIPS_REG_A1_64: + return "a1"; + case MIPS_REG_A2: + case MIPS_REG_A2_64: + return "a2"; + case MIPS_REG_A3: + case MIPS_REG_A3_64: + return "a3"; + case MIPS_REG_K0: + case MIPS_REG_K0_64: + return "k0"; + case MIPS_REG_K1: + case MIPS_REG_K1_64: + return "k1"; + case MIPS_REG_S0: + case MIPS_REG_S0_64: + return "s0"; + case MIPS_REG_S1: + case MIPS_REG_S1_64: + return "s1"; + case MIPS_REG_S2: + case MIPS_REG_S2_64: + return "s2"; + case MIPS_REG_S3: + case MIPS_REG_S3_64: + return "s3"; + case MIPS_REG_S4: + case MIPS_REG_S4_64: + return "s4"; + case MIPS_REG_S5: + case MIPS_REG_S5_64: + return "s5"; + case MIPS_REG_S6: + case MIPS_REG_S6_64: + return "s6"; + case MIPS_REG_S7: + case MIPS_REG_S7_64: + return "s7"; + case MIPS_REG_T0: + case MIPS_REG_T0_64: + return "t0"; + case MIPS_REG_T1: + case MIPS_REG_T1_64: + return "t1"; + case MIPS_REG_T2: + case MIPS_REG_T2_64: + return "t2"; + case MIPS_REG_T3: + case MIPS_REG_T3_64: + return "t3"; + case MIPS_REG_T4: + case MIPS_REG_T4_64: + return "t4"; + case MIPS_REG_T5: + case MIPS_REG_T5_64: + return "t5"; + case MIPS_REG_T6: + case MIPS_REG_T6_64: + return "t6"; + case MIPS_REG_T7: + case MIPS_REG_T7_64: + return "t7"; + case MIPS_REG_T8: + case MIPS_REG_T8_64: + return "t8"; + case MIPS_REG_T9: + case MIPS_REG_T9_64: + return "t9"; + case MIPS_REG_V0: + case MIPS_REG_V0_64: + return "v0"; + case MIPS_REG_V1: + case MIPS_REG_V1_64: + return "v1"; + default: + return getRegisterName(RegNo); + } +} \ No newline at end of file diff --git a/arch/Mips/MipsInstPrinter.h b/arch/Mips/MipsInstPrinter.h index 659ef7790..0d92d8d79 100644 --- a/arch/Mips/MipsInstPrinter.h +++ b/arch/Mips/MipsInstPrinter.h @@ -1,9 +1,24 @@ +#include "../../SStream.h" +#include "../../MCInst.h" +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + //=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -11,15 +26,133 @@ // //===----------------------------------------------------------------------===// -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSINSTPRINTER_H +#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSINSTPRINTER_H +#include +#include +#include +#include -#ifndef CS_MIPSINSTPRINTER_H -#define CS_MIPSINSTPRINTER_H +#include "../../MCInstPrinter.h" +#include "../../cs_priv.h" +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b -#include "../../MCInst.h" -#include "../../SStream.h" +// These enumeration declarations were originally in MipsInstrInfo.h but +// had to be moved here to avoid circular dependencies between +// LLVMMipsCodeGen and LLVMMipsAsmPrinter. +// CS namespace begin: Mips -void Mips_printInst(MCInst *MI, SStream *O, void *info); +// Mips Branch Codes +typedef enum MipsFPBranchCode { + Mips_BRANCH_F, + Mips_BRANCH_T, + Mips_BRANCH_FL, + Mips_BRANCH_TL, + Mips_BRANCH_INVALID +} Mips_FPBranchCode; + +// Mips Condition Codes +typedef enum MipsCondCode { + // To be used with float branch True + Mips_FCOND_F, + Mips_FCOND_UN, + Mips_FCOND_OEQ, + Mips_FCOND_UEQ, + Mips_FCOND_OLT, + Mips_FCOND_ULT, + Mips_FCOND_OLE, + Mips_FCOND_ULE, + Mips_FCOND_SF, + Mips_FCOND_NGLE, + Mips_FCOND_SEQ, + Mips_FCOND_NGL, + Mips_FCOND_LT, + Mips_FCOND_NGE, + Mips_FCOND_LE, + Mips_FCOND_NGT, + + // To be used with float branch False + // This conditions have the same mnemonic as the + // above ones, but are used with a branch False; + Mips_FCOND_T, + Mips_FCOND_OR, + Mips_FCOND_UNE, + Mips_FCOND_ONE, + Mips_FCOND_UGE, + Mips_FCOND_OGE, + Mips_FCOND_UGT, + Mips_FCOND_OGT, + Mips_FCOND_ST, + Mips_FCOND_GLE, + Mips_FCOND_SNE, + Mips_FCOND_GL, + Mips_FCOND_NLT, + Mips_FCOND_GE, + Mips_FCOND_NLE, + Mips_FCOND_GT +} Mips_CondCode; + +static const char *MipsFCCToString(Mips_CondCode CC); + +// CS namespace end: Mips + +// end namespace Mips + +// Autogenerated by tblgen. +static const char *getRegisterName(unsigned RegNo); +static void printInstruction(MCInst *MI, uint64_t Address, SStream *O); +static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS); +static void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *O); +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printJumpOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, + SStream *O); + +#define DECLARE_printUImm_2(Bits, Offset) \ + static void CONCAT(printUImm, CONCAT(Bits, Offset))( \ + MCInst *MI, int opNum, SStream *O) +#define DECLARE_printUImm(Bits) \ + static void CONCAT(printUImm, CONCAT(Bits, 0))( \ + MCInst *MI, int opNum, SStream *O) +DECLARE_printUImm(0); +DECLARE_printUImm(1); +DECLARE_printUImm(10); +DECLARE_printUImm(12); +DECLARE_printUImm(16); +DECLARE_printUImm(2); +DECLARE_printUImm(20); +DECLARE_printUImm(26); +DECLARE_printUImm(3); +DECLARE_printUImm(32); +DECLARE_printUImm(4); +DECLARE_printUImm(5); +DECLARE_printUImm(6); +DECLARE_printUImm(7); +DECLARE_printUImm(8); +DECLARE_printUImm_2(2, 1); +DECLARE_printUImm_2(5, 1); +DECLARE_printUImm_2(5, 32); +DECLARE_printUImm_2(5, 33); +DECLARE_printUImm_2(6, 1); +DECLARE_printUImm_2(6, 2); + +static void printMemOperand(MCInst *MI, int opNum, SStream *O); +static void printMemOperandEA(MCInst *MI, int opNum, SStream *O); +static void printFCCOperand(MCInst *MI, int opNum, SStream *O); +static bool printAlias(const char *Str, const MCInst *MI, uint64_t Address, + unsigned OpNo, SStream *OS, bool IsBranch); +static bool printAlias2(const char *Str, const MCInst *MI, uint64_t Address, + unsigned OpNo0, unsigned OpNo1, SStream *OS, + bool IsBranch); +static bool printAlias3(const char *Str, const MCInst *MI, uint64_t Address, + unsigned OpNo0, unsigned OpNo1, unsigned OpNo2, SStream *OS); +static bool printAlias4(const MCInst *MI, uint64_t Address, SStream *OS); +static void printRegisterList(MCInst *MI, int opNum, SStream *O); +static void printNanoMipsRegisterList(MCInst *MI, int opNum, SStream *O); +static void printHi20(MCInst *MI, int OpNum, SStream *O); +static void printHi20PCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O); +static void printPCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O); #endif diff --git a/arch/Mips/MipsLinkage.h b/arch/Mips/MipsLinkage.h new file mode 100644 index 000000000..93d3d9980 --- /dev/null +++ b/arch/Mips/MipsLinkage.h @@ -0,0 +1,21 @@ +/* Capstone Disassembly Engine */ +/* By Giovanni Dante Grazioli, deroad , 2024 */ + +#ifndef CS_MIPS_LINKAGE_H +#define CS_MIPS_LINKAGE_H + +// Function definitions to call static LLVM functions. + +#include "../../MCDisassembler.h" +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" +#include "capstone/capstone.h" + +const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName); +void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O); +DecodeStatus Mips_LLVM_getInstruction(MCInst *Instr, uint64_t *Size, + const uint8_t *Bytes, size_t BytesLen, + uint64_t Address, SStream *CStream); + +#endif // CS_MIPS_LINKAGE_H diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c index 41dda33d3..3f1ec49ce 100644 --- a/arch/Mips/MipsMapping.c +++ b/arch/Mips/MipsMapping.c @@ -1,898 +1,63 @@ /* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* By Giovanni Dante Grazioli, deroad , 2024 */ #ifdef CAPSTONE_HAS_MIPS -#include // debug +#include #include +#include +#include + #include "../../Mapping.h" -#include "../../utils.h" +#include "../../MCDisassembler.h" +#include "../../cs_priv.h" +#include "../../cs_simple_types.h" #include "MipsMapping.h" +#include "MipsLinkage.h" +#include "MipsDisassembler.h" + +#define GET_REGINFO_ENUM +#define GET_REGINFO_MC_DESC +#include "MipsGenRegisterInfo.inc" #define GET_INSTRINFO_ENUM #include "MipsGenInstrInfo.inc" -#ifndef CAPSTONE_DIET -static const name_map reg_name_maps[] = { - { MIPS_REG_INVALID, NULL }, - - { MIPS_REG_PC, "pc"}, - - //{ MIPS_REG_0, "0"}, - { MIPS_REG_0, "zero"}, - { MIPS_REG_1, "at"}, - //{ MIPS_REG_1, "1"}, - { MIPS_REG_2, "v0"}, - //{ MIPS_REG_2, "2"}, - { MIPS_REG_3, "v1"}, - //{ MIPS_REG_3, "3"}, - { MIPS_REG_4, "a0"}, - //{ MIPS_REG_4, "4"}, - { MIPS_REG_5, "a1"}, - //{ MIPS_REG_5, "5"}, - { MIPS_REG_6, "a2"}, - //{ MIPS_REG_6, "6"}, - { MIPS_REG_7, "a3"}, - //{ MIPS_REG_7, "7"}, - { MIPS_REG_8, "t0"}, - //{ MIPS_REG_8, "8"}, - { MIPS_REG_9, "t1"}, - //{ MIPS_REG_9, "9"}, - { MIPS_REG_10, "t2"}, - //{ MIPS_REG_10, "10"}, - { MIPS_REG_11, "t3"}, - //{ MIPS_REG_11, "11"}, - { MIPS_REG_12, "t4"}, - //{ MIPS_REG_12, "12"}, - { MIPS_REG_13, "t5"}, - //{ MIPS_REG_13, "13"}, - { MIPS_REG_14, "t6"}, - //{ MIPS_REG_14, "14"}, - { MIPS_REG_15, "t7"}, - //{ MIPS_REG_15, "15"}, - { MIPS_REG_16, "s0"}, - //{ MIPS_REG_16, "16"}, - { MIPS_REG_17, "s1"}, - //{ MIPS_REG_17, "17"}, - { MIPS_REG_18, "s2"}, - //{ MIPS_REG_18, "18"}, - { MIPS_REG_19, "s3"}, - //{ MIPS_REG_19, "19"}, - { MIPS_REG_20, "s4"}, - //{ MIPS_REG_20, "20"}, - { MIPS_REG_21, "s5"}, - //{ MIPS_REG_21, "21"}, - { MIPS_REG_22, "s6"}, - //{ MIPS_REG_22, "22"}, - { MIPS_REG_23, "s7"}, - //{ MIPS_REG_23, "23"}, - { MIPS_REG_24, "t8"}, - //{ MIPS_REG_24, "24"}, - { MIPS_REG_25, "t9"}, - //{ MIPS_REG_25, "25"}, - { MIPS_REG_26, "k0"}, - //{ MIPS_REG_26, "26"}, - { MIPS_REG_27, "k1"}, - //{ MIPS_REG_27, "27"}, - { MIPS_REG_28, "gp"}, - //{ MIPS_REG_28, "28"}, - { MIPS_REG_29, "sp"}, - //{ MIPS_REG_29, "29"}, - { MIPS_REG_30, "fp"}, - //{ MIPS_REG_30, "30"}, - { MIPS_REG_31, "ra"}, - //{ MIPS_REG_31, "31"}, - - { MIPS_REG_DSPCCOND, "dspccond"}, - { MIPS_REG_DSPCARRY, "dspcarry"}, - { MIPS_REG_DSPEFI, "dspefi"}, - { MIPS_REG_DSPOUTFLAG, "dspoutflag"}, - { MIPS_REG_DSPOUTFLAG16_19, "dspoutflag16_19"}, - { MIPS_REG_DSPOUTFLAG20, "dspoutflag20"}, - { MIPS_REG_DSPOUTFLAG21, "dspoutflag21"}, - { MIPS_REG_DSPOUTFLAG22, "dspoutflag22"}, - { MIPS_REG_DSPOUTFLAG23, "dspoutflag23"}, - { MIPS_REG_DSPPOS, "dsppos"}, - { MIPS_REG_DSPSCOUNT, "dspscount"}, - - { MIPS_REG_AC0, "ac0"}, - { MIPS_REG_AC1, "ac1"}, - { MIPS_REG_AC2, "ac2"}, - { MIPS_REG_AC3, "ac3"}, - - { MIPS_REG_CC0, "cc0"}, - { MIPS_REG_CC1, "cc1"}, - { MIPS_REG_CC2, "cc2"}, - { MIPS_REG_CC3, "cc3"}, - { MIPS_REG_CC4, "cc4"}, - { MIPS_REG_CC5, "cc5"}, - { MIPS_REG_CC6, "cc6"}, - { MIPS_REG_CC7, "cc7"}, - - { MIPS_REG_F0, "f0"}, - { MIPS_REG_F1, "f1"}, - { MIPS_REG_F2, "f2"}, - { MIPS_REG_F3, "f3"}, - { MIPS_REG_F4, "f4"}, - { MIPS_REG_F5, "f5"}, - { MIPS_REG_F6, "f6"}, - { MIPS_REG_F7, "f7"}, - { MIPS_REG_F8, "f8"}, - { MIPS_REG_F9, "f9"}, - { MIPS_REG_F10, "f10"}, - { MIPS_REG_F11, "f11"}, - { MIPS_REG_F12, "f12"}, - { MIPS_REG_F13, "f13"}, - { MIPS_REG_F14, "f14"}, - { MIPS_REG_F15, "f15"}, - { MIPS_REG_F16, "f16"}, - { MIPS_REG_F17, "f17"}, - { MIPS_REG_F18, "f18"}, - { MIPS_REG_F19, "f19"}, - { MIPS_REG_F20, "f20"}, - { MIPS_REG_F21, "f21"}, - { MIPS_REG_F22, "f22"}, - { MIPS_REG_F23, "f23"}, - { MIPS_REG_F24, "f24"}, - { MIPS_REG_F25, "f25"}, - { MIPS_REG_F26, "f26"}, - { MIPS_REG_F27, "f27"}, - { MIPS_REG_F28, "f28"}, - { MIPS_REG_F29, "f29"}, - { MIPS_REG_F30, "f30"}, - { MIPS_REG_F31, "f31"}, - - { MIPS_REG_FCC0, "fcc0"}, - { MIPS_REG_FCC1, "fcc1"}, - { MIPS_REG_FCC2, "fcc2"}, - { MIPS_REG_FCC3, "fcc3"}, - { MIPS_REG_FCC4, "fcc4"}, - { MIPS_REG_FCC5, "fcc5"}, - { MIPS_REG_FCC6, "fcc6"}, - { MIPS_REG_FCC7, "fcc7"}, - - { MIPS_REG_W0, "w0"}, - { MIPS_REG_W1, "w1"}, - { MIPS_REG_W2, "w2"}, - { MIPS_REG_W3, "w3"}, - { MIPS_REG_W4, "w4"}, - { MIPS_REG_W5, "w5"}, - { MIPS_REG_W6, "w6"}, - { MIPS_REG_W7, "w7"}, - { MIPS_REG_W8, "w8"}, - { MIPS_REG_W9, "w9"}, - { MIPS_REG_W10, "w10"}, - { MIPS_REG_W11, "w11"}, - { MIPS_REG_W12, "w12"}, - { MIPS_REG_W13, "w13"}, - { MIPS_REG_W14, "w14"}, - { MIPS_REG_W15, "w15"}, - { MIPS_REG_W16, "w16"}, - { MIPS_REG_W17, "w17"}, - { MIPS_REG_W18, "w18"}, - { MIPS_REG_W19, "w19"}, - { MIPS_REG_W20, "w20"}, - { MIPS_REG_W21, "w21"}, - { MIPS_REG_W22, "w22"}, - { MIPS_REG_W23, "w23"}, - { MIPS_REG_W24, "w24"}, - { MIPS_REG_W25, "w25"}, - { MIPS_REG_W26, "w26"}, - { MIPS_REG_W27, "w27"}, - { MIPS_REG_W28, "w28"}, - { MIPS_REG_W29, "w29"}, - { MIPS_REG_W30, "w30"}, - { MIPS_REG_W31, "w31"}, - - { MIPS_REG_HI, "hi"}, - { MIPS_REG_LO, "lo"}, - - { MIPS_REG_P0, "p0"}, - { MIPS_REG_P1, "p1"}, - { MIPS_REG_P2, "p2"}, - - { MIPS_REG_MPL0, "mpl0"}, - { MIPS_REG_MPL1, "mpl1"}, - { MIPS_REG_MPL2, "mpl2"}, -}; -#endif +void Mips_init_mri(MCRegisterInfo *MRI) +{ + MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, sizeof(MipsRegDesc), + 0, 0, MipsMCRegisterClasses, + ARR_SIZE(MipsMCRegisterClasses), 0, 0, + MipsRegDiffLists, 0, + MipsSubRegIdxLists, + ARR_SIZE(MipsSubRegIdxLists), 0); +} const char *Mips_reg_name(csh handle, unsigned int reg) { -#ifndef CAPSTONE_DIET - if (reg >= ARR_SIZE(reg_name_maps)) - return NULL; - - return reg_name_maps[reg].name; -#else - return NULL; -#endif + int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax; + return Mips_LLVM_getRegisterName(reg, + syntax_opt & CS_OPT_SYNTAX_NOREGNAME); } -static const insn_map insns[] = { - // dummy item - { - 0, 0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - -#include "MipsMappingInsn.inc" -}; - -// given internal insn id, return public instruction info void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { - unsigned int i; - - i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - insn->id = insns[i].mapid; - - if (h->detail_opt) { -#ifndef CAPSTONE_DIET - memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); - insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); - - memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); - insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); - - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); - - if (insns[i].branch || insns[i].indirect_branch) { - // this insn also belongs to JUMP group. add JUMP group - insn->detail->groups[insn->detail->groups_count] = MIPS_GRP_JUMP; - insn->detail->groups_count++; - } -#endif - } - } + // Not used by Mips. Information is set after disassembly. } -static const name_map insn_name_maps[] = { - { MIPS_INS_INVALID, NULL }, - - { MIPS_INS_ABSQ_S, "absq_s" }, - { MIPS_INS_ADD, "add" }, - { MIPS_INS_ADDIUPC, "addiupc" }, - { MIPS_INS_ADDIUR1SP, "addiur1sp" }, - { MIPS_INS_ADDIUR2, "addiur2" }, - { MIPS_INS_ADDIUS5, "addius5" }, - { MIPS_INS_ADDIUSP, "addiusp" }, - { MIPS_INS_ADDQH, "addqh" }, - { MIPS_INS_ADDQH_R, "addqh_r" }, - { MIPS_INS_ADDQ, "addq" }, - { MIPS_INS_ADDQ_S, "addq_s" }, - { MIPS_INS_ADDSC, "addsc" }, - { MIPS_INS_ADDS_A, "adds_a" }, - { MIPS_INS_ADDS_S, "adds_s" }, - { MIPS_INS_ADDS_U, "adds_u" }, - { MIPS_INS_ADDU16, "addu16" }, - { MIPS_INS_ADDUH, "adduh" }, - { MIPS_INS_ADDUH_R, "adduh_r" }, - { MIPS_INS_ADDU, "addu" }, - { MIPS_INS_ADDU_S, "addu_s" }, - { MIPS_INS_ADDVI, "addvi" }, - { MIPS_INS_ADDV, "addv" }, - { MIPS_INS_ADDWC, "addwc" }, - { MIPS_INS_ADD_A, "add_a" }, - { MIPS_INS_ADDI, "addi" }, - { MIPS_INS_ADDIU, "addiu" }, - { MIPS_INS_ALIGN, "align" }, - { MIPS_INS_ALUIPC, "aluipc" }, - { MIPS_INS_AND, "and" }, - { MIPS_INS_AND16, "and16" }, - { MIPS_INS_ANDI16, "andi16" }, - { MIPS_INS_ANDI, "andi" }, - { MIPS_INS_APPEND, "append" }, - { MIPS_INS_ASUB_S, "asub_s" }, - { MIPS_INS_ASUB_U, "asub_u" }, - { MIPS_INS_AUI, "aui" }, - { MIPS_INS_AUIPC, "auipc" }, - { MIPS_INS_AVER_S, "aver_s" }, - { MIPS_INS_AVER_U, "aver_u" }, - { MIPS_INS_AVE_S, "ave_s" }, - { MIPS_INS_AVE_U, "ave_u" }, - { MIPS_INS_B16, "b16" }, - { MIPS_INS_BADDU, "baddu" }, - { MIPS_INS_BAL, "bal" }, - { MIPS_INS_BALC, "balc" }, - { MIPS_INS_BALIGN, "balign" }, - { MIPS_INS_BBIT0, "bbit0" }, - { MIPS_INS_BBIT032, "bbit032" }, - { MIPS_INS_BBIT1, "bbit1" }, - { MIPS_INS_BBIT132, "bbit132" }, - { MIPS_INS_BC, "bc" }, - { MIPS_INS_BC0F, "bc0f" }, - { MIPS_INS_BC0FL, "bc0fl" }, - { MIPS_INS_BC0T, "bc0t" }, - { MIPS_INS_BC0TL, "bc0tl" }, - { MIPS_INS_BC1EQZ, "bc1eqz" }, - { MIPS_INS_BC1F, "bc1f" }, - { MIPS_INS_BC1FL, "bc1fl" }, - { MIPS_INS_BC1NEZ, "bc1nez" }, - { MIPS_INS_BC1T, "bc1t" }, - { MIPS_INS_BC1TL, "bc1tl" }, - { MIPS_INS_BC2EQZ, "bc2eqz" }, - { MIPS_INS_BC2F, "bc2f" }, - { MIPS_INS_BC2FL, "bc2fl" }, - { MIPS_INS_BC2NEZ, "bc2nez" }, - { MIPS_INS_BC2T, "bc2t" }, - { MIPS_INS_BC2TL, "bc2tl" }, - { MIPS_INS_BC3F, "bc3f" }, - { MIPS_INS_BC3FL, "bc3fl" }, - { MIPS_INS_BC3T, "bc3t" }, - { MIPS_INS_BC3TL, "bc3tl" }, - { MIPS_INS_BCLRI, "bclri" }, - { MIPS_INS_BCLR, "bclr" }, - { MIPS_INS_BEQ, "beq" }, - { MIPS_INS_BEQC, "beqc" }, - { MIPS_INS_BEQL, "beql" }, - { MIPS_INS_BEQZ16, "beqz16" }, - { MIPS_INS_BEQZALC, "beqzalc" }, - { MIPS_INS_BEQZC, "beqzc" }, - { MIPS_INS_BGEC, "bgec" }, - { MIPS_INS_BGEUC, "bgeuc" }, - { MIPS_INS_BGEZ, "bgez" }, - { MIPS_INS_BGEZAL, "bgezal" }, - { MIPS_INS_BGEZALC, "bgezalc" }, - { MIPS_INS_BGEZALL, "bgezall" }, - { MIPS_INS_BGEZALS, "bgezals" }, - { MIPS_INS_BGEZC, "bgezc" }, - { MIPS_INS_BGEZL, "bgezl" }, - { MIPS_INS_BGTZ, "bgtz" }, - { MIPS_INS_BGTZALC, "bgtzalc" }, - { MIPS_INS_BGTZC, "bgtzc" }, - { MIPS_INS_BGTZL, "bgtzl" }, - { MIPS_INS_BINSLI, "binsli" }, - { MIPS_INS_BINSL, "binsl" }, - { MIPS_INS_BINSRI, "binsri" }, - { MIPS_INS_BINSR, "binsr" }, - { MIPS_INS_BITREV, "bitrev" }, - { MIPS_INS_BITSWAP, "bitswap" }, - { MIPS_INS_BLEZ, "blez" }, - { MIPS_INS_BLEZALC, "blezalc" }, - { MIPS_INS_BLEZC, "blezc" }, - { MIPS_INS_BLEZL, "blezl" }, - { MIPS_INS_BLTC, "bltc" }, - { MIPS_INS_BLTUC, "bltuc" }, - { MIPS_INS_BLTZ, "bltz" }, - { MIPS_INS_BLTZAL, "bltzal" }, - { MIPS_INS_BLTZALC, "bltzalc" }, - { MIPS_INS_BLTZALL, "bltzall" }, - { MIPS_INS_BLTZALS, "bltzals" }, - { MIPS_INS_BLTZC, "bltzc" }, - { MIPS_INS_BLTZL, "bltzl" }, - { MIPS_INS_BMNZI, "bmnzi" }, - { MIPS_INS_BMNZ, "bmnz" }, - { MIPS_INS_BMZI, "bmzi" }, - { MIPS_INS_BMZ, "bmz" }, - { MIPS_INS_BNE, "bne" }, - { MIPS_INS_BNEC, "bnec" }, - { MIPS_INS_BNEGI, "bnegi" }, - { MIPS_INS_BNEG, "bneg" }, - { MIPS_INS_BNEL, "bnel" }, - { MIPS_INS_BNEZ16, "bnez16" }, - { MIPS_INS_BNEZALC, "bnezalc" }, - { MIPS_INS_BNEZC, "bnezc" }, - { MIPS_INS_BNVC, "bnvc" }, - { MIPS_INS_BNZ, "bnz" }, - { MIPS_INS_BOVC, "bovc" }, - { MIPS_INS_BPOSGE32, "bposge32" }, - { MIPS_INS_BREAK, "break" }, - { MIPS_INS_BREAK16, "break16" }, - { MIPS_INS_BSELI, "bseli" }, - { MIPS_INS_BSEL, "bsel" }, - { MIPS_INS_BSETI, "bseti" }, - { MIPS_INS_BSET, "bset" }, - { MIPS_INS_BZ, "bz" }, - { MIPS_INS_BEQZ, "beqz" }, - { MIPS_INS_B, "b" }, - { MIPS_INS_BNEZ, "bnez" }, - { MIPS_INS_BTEQZ, "bteqz" }, - { MIPS_INS_BTNEZ, "btnez" }, - { MIPS_INS_CACHE, "cache" }, - { MIPS_INS_CEIL, "ceil" }, - { MIPS_INS_CEQI, "ceqi" }, - { MIPS_INS_CEQ, "ceq" }, - { MIPS_INS_CFC1, "cfc1" }, - { MIPS_INS_CFCMSA, "cfcmsa" }, - { MIPS_INS_CINS, "cins" }, - { MIPS_INS_CINS32, "cins32" }, - { MIPS_INS_CLASS, "class" }, - { MIPS_INS_CLEI_S, "clei_s" }, - { MIPS_INS_CLEI_U, "clei_u" }, - { MIPS_INS_CLE_S, "cle_s" }, - { MIPS_INS_CLE_U, "cle_u" }, - { MIPS_INS_CLO, "clo" }, - { MIPS_INS_CLTI_S, "clti_s" }, - { MIPS_INS_CLTI_U, "clti_u" }, - { MIPS_INS_CLT_S, "clt_s" }, - { MIPS_INS_CLT_U, "clt_u" }, - { MIPS_INS_CLZ, "clz" }, - { MIPS_INS_CMPGDU, "cmpgdu" }, - { MIPS_INS_CMPGU, "cmpgu" }, - { MIPS_INS_CMPU, "cmpu" }, - { MIPS_INS_CMP, "cmp" }, - { MIPS_INS_COPY_S, "copy_s" }, - { MIPS_INS_COPY_U, "copy_u" }, - { MIPS_INS_CTC1, "ctc1" }, - { MIPS_INS_CTCMSA, "ctcmsa" }, - { MIPS_INS_CVT, "cvt" }, - { MIPS_INS_C, "c" }, - { MIPS_INS_CMPI, "cmpi" }, - { MIPS_INS_DADD, "dadd" }, - { MIPS_INS_DADDI, "daddi" }, - { MIPS_INS_DADDIU, "daddiu" }, - { MIPS_INS_DADDU, "daddu" }, - { MIPS_INS_DAHI, "dahi" }, - { MIPS_INS_DALIGN, "dalign" }, - { MIPS_INS_DATI, "dati" }, - { MIPS_INS_DAUI, "daui" }, - { MIPS_INS_DBITSWAP, "dbitswap" }, - { MIPS_INS_DCLO, "dclo" }, - { MIPS_INS_DCLZ, "dclz" }, - { MIPS_INS_DDIV, "ddiv" }, - { MIPS_INS_DDIVU, "ddivu" }, - { MIPS_INS_DERET, "deret" }, - { MIPS_INS_DEXT, "dext" }, - { MIPS_INS_DEXTM, "dextm" }, - { MIPS_INS_DEXTU, "dextu" }, - { MIPS_INS_DI, "di" }, - { MIPS_INS_DINS, "dins" }, - { MIPS_INS_DINSM, "dinsm" }, - { MIPS_INS_DINSU, "dinsu" }, - { MIPS_INS_DIV, "div" }, - { MIPS_INS_DIVU, "divu" }, - { MIPS_INS_DIV_S, "div_s" }, - { MIPS_INS_DIV_U, "div_u" }, - { MIPS_INS_DLSA, "dlsa" }, - { MIPS_INS_DMFC0, "dmfc0" }, - { MIPS_INS_DMFC1, "dmfc1" }, - { MIPS_INS_DMFC2, "dmfc2" }, - { MIPS_INS_DMOD, "dmod" }, - { MIPS_INS_DMODU, "dmodu" }, - { MIPS_INS_DMTC0, "dmtc0" }, - { MIPS_INS_DMTC1, "dmtc1" }, - { MIPS_INS_DMTC2, "dmtc2" }, - { MIPS_INS_DMUH, "dmuh" }, - { MIPS_INS_DMUHU, "dmuhu" }, - { MIPS_INS_DMUL, "dmul" }, - { MIPS_INS_DMULT, "dmult" }, - { MIPS_INS_DMULTU, "dmultu" }, - { MIPS_INS_DMULU, "dmulu" }, - { MIPS_INS_DOTP_S, "dotp_s" }, - { MIPS_INS_DOTP_U, "dotp_u" }, - { MIPS_INS_DPADD_S, "dpadd_s" }, - { MIPS_INS_DPADD_U, "dpadd_u" }, - { MIPS_INS_DPAQX_SA, "dpaqx_sa" }, - { MIPS_INS_DPAQX_S, "dpaqx_s" }, - { MIPS_INS_DPAQ_SA, "dpaq_sa" }, - { MIPS_INS_DPAQ_S, "dpaq_s" }, - { MIPS_INS_DPAU, "dpau" }, - { MIPS_INS_DPAX, "dpax" }, - { MIPS_INS_DPA, "dpa" }, - { MIPS_INS_DPOP, "dpop" }, - { MIPS_INS_DPSQX_SA, "dpsqx_sa" }, - { MIPS_INS_DPSQX_S, "dpsqx_s" }, - { MIPS_INS_DPSQ_SA, "dpsq_sa" }, - { MIPS_INS_DPSQ_S, "dpsq_s" }, - { MIPS_INS_DPSUB_S, "dpsub_s" }, - { MIPS_INS_DPSUB_U, "dpsub_u" }, - { MIPS_INS_DPSU, "dpsu" }, - { MIPS_INS_DPSX, "dpsx" }, - { MIPS_INS_DPS, "dps" }, - { MIPS_INS_DROTR, "drotr" }, - { MIPS_INS_DROTR32, "drotr32" }, - { MIPS_INS_DROTRV, "drotrv" }, - { MIPS_INS_DSBH, "dsbh" }, - { MIPS_INS_DSHD, "dshd" }, - { MIPS_INS_DSLL, "dsll" }, - { MIPS_INS_DSLL32, "dsll32" }, - { MIPS_INS_DSLLV, "dsllv" }, - { MIPS_INS_DSRA, "dsra" }, - { MIPS_INS_DSRA32, "dsra32" }, - { MIPS_INS_DSRAV, "dsrav" }, - { MIPS_INS_DSRL, "dsrl" }, - { MIPS_INS_DSRL32, "dsrl32" }, - { MIPS_INS_DSRLV, "dsrlv" }, - { MIPS_INS_DSUB, "dsub" }, - { MIPS_INS_DSUBU, "dsubu" }, - { MIPS_INS_EHB, "ehb" }, - { MIPS_INS_EI, "ei" }, - { MIPS_INS_ERET, "eret" }, - { MIPS_INS_EXT, "ext" }, - { MIPS_INS_EXTP, "extp" }, - { MIPS_INS_EXTPDP, "extpdp" }, - { MIPS_INS_EXTPDPV, "extpdpv" }, - { MIPS_INS_EXTPV, "extpv" }, - { MIPS_INS_EXTRV_RS, "extrv_rs" }, - { MIPS_INS_EXTRV_R, "extrv_r" }, - { MIPS_INS_EXTRV_S, "extrv_s" }, - { MIPS_INS_EXTRV, "extrv" }, - { MIPS_INS_EXTR_RS, "extr_rs" }, - { MIPS_INS_EXTR_R, "extr_r" }, - { MIPS_INS_EXTR_S, "extr_s" }, - { MIPS_INS_EXTR, "extr" }, - { MIPS_INS_EXTS, "exts" }, - { MIPS_INS_EXTS32, "exts32" }, - { MIPS_INS_ABS, "abs" }, - { MIPS_INS_FADD, "fadd" }, - { MIPS_INS_FCAF, "fcaf" }, - { MIPS_INS_FCEQ, "fceq" }, - { MIPS_INS_FCLASS, "fclass" }, - { MIPS_INS_FCLE, "fcle" }, - { MIPS_INS_FCLT, "fclt" }, - { MIPS_INS_FCNE, "fcne" }, - { MIPS_INS_FCOR, "fcor" }, - { MIPS_INS_FCUEQ, "fcueq" }, - { MIPS_INS_FCULE, "fcule" }, - { MIPS_INS_FCULT, "fcult" }, - { MIPS_INS_FCUNE, "fcune" }, - { MIPS_INS_FCUN, "fcun" }, - { MIPS_INS_FDIV, "fdiv" }, - { MIPS_INS_FEXDO, "fexdo" }, - { MIPS_INS_FEXP2, "fexp2" }, - { MIPS_INS_FEXUPL, "fexupl" }, - { MIPS_INS_FEXUPR, "fexupr" }, - { MIPS_INS_FFINT_S, "ffint_s" }, - { MIPS_INS_FFINT_U, "ffint_u" }, - { MIPS_INS_FFQL, "ffql" }, - { MIPS_INS_FFQR, "ffqr" }, - { MIPS_INS_FILL, "fill" }, - { MIPS_INS_FLOG2, "flog2" }, - { MIPS_INS_FLOOR, "floor" }, - { MIPS_INS_FMADD, "fmadd" }, - { MIPS_INS_FMAX_A, "fmax_a" }, - { MIPS_INS_FMAX, "fmax" }, - { MIPS_INS_FMIN_A, "fmin_a" }, - { MIPS_INS_FMIN, "fmin" }, - { MIPS_INS_MOV, "mov" }, - { MIPS_INS_FMSUB, "fmsub" }, - { MIPS_INS_FMUL, "fmul" }, - { MIPS_INS_MUL, "mul" }, - { MIPS_INS_NEG, "neg" }, - { MIPS_INS_FRCP, "frcp" }, - { MIPS_INS_FRINT, "frint" }, - { MIPS_INS_FRSQRT, "frsqrt" }, - { MIPS_INS_FSAF, "fsaf" }, - { MIPS_INS_FSEQ, "fseq" }, - { MIPS_INS_FSLE, "fsle" }, - { MIPS_INS_FSLT, "fslt" }, - { MIPS_INS_FSNE, "fsne" }, - { MIPS_INS_FSOR, "fsor" }, - { MIPS_INS_FSQRT, "fsqrt" }, - { MIPS_INS_SQRT, "sqrt" }, - { MIPS_INS_FSUB, "fsub" }, - { MIPS_INS_SUB, "sub" }, - { MIPS_INS_FSUEQ, "fsueq" }, - { MIPS_INS_FSULE, "fsule" }, - { MIPS_INS_FSULT, "fsult" }, - { MIPS_INS_FSUNE, "fsune" }, - { MIPS_INS_FSUN, "fsun" }, - { MIPS_INS_FTINT_S, "ftint_s" }, - { MIPS_INS_FTINT_U, "ftint_u" }, - { MIPS_INS_FTQ, "ftq" }, - { MIPS_INS_FTRUNC_S, "ftrunc_s" }, - { MIPS_INS_FTRUNC_U, "ftrunc_u" }, - { MIPS_INS_HADD_S, "hadd_s" }, - { MIPS_INS_HADD_U, "hadd_u" }, - { MIPS_INS_HSUB_S, "hsub_s" }, - { MIPS_INS_HSUB_U, "hsub_u" }, - { MIPS_INS_ILVEV, "ilvev" }, - { MIPS_INS_ILVL, "ilvl" }, - { MIPS_INS_ILVOD, "ilvod" }, - { MIPS_INS_ILVR, "ilvr" }, - { MIPS_INS_INS, "ins" }, - { MIPS_INS_INSERT, "insert" }, - { MIPS_INS_INSV, "insv" }, - { MIPS_INS_INSVE, "insve" }, - { MIPS_INS_J, "j" }, - { MIPS_INS_JAL, "jal" }, - { MIPS_INS_JALR, "jalr" }, - { MIPS_INS_JALRS16, "jalrs16" }, - { MIPS_INS_JALRS, "jalrs" }, - { MIPS_INS_JALS, "jals" }, - { MIPS_INS_JALX, "jalx" }, - { MIPS_INS_JIALC, "jialc" }, - { MIPS_INS_JIC, "jic" }, - { MIPS_INS_JR, "jr" }, - { MIPS_INS_JR16, "jr16" }, - { MIPS_INS_JRADDIUSP, "jraddiusp" }, - { MIPS_INS_JRC, "jrc" }, - { MIPS_INS_JALRC, "jalrc" }, - { MIPS_INS_LB, "lb" }, - { MIPS_INS_LBU16, "lbu16" }, - { MIPS_INS_LBUX, "lbux" }, - { MIPS_INS_LBU, "lbu" }, - { MIPS_INS_LD, "ld" }, - { MIPS_INS_LDC1, "ldc1" }, - { MIPS_INS_LDC2, "ldc2" }, - { MIPS_INS_LDC3, "ldc3" }, - { MIPS_INS_LDI, "ldi" }, - { MIPS_INS_LDL, "ldl" }, - { MIPS_INS_LDPC, "ldpc" }, - { MIPS_INS_LDR, "ldr" }, - { MIPS_INS_LDXC1, "ldxc1" }, - { MIPS_INS_LH, "lh" }, - { MIPS_INS_LHU16, "lhu16" }, - { MIPS_INS_LHX, "lhx" }, - { MIPS_INS_LHU, "lhu" }, - { MIPS_INS_LI16, "li16" }, - { MIPS_INS_LL, "ll" }, - { MIPS_INS_LLD, "lld" }, - { MIPS_INS_LSA, "lsa" }, - { MIPS_INS_LUXC1, "luxc1" }, - { MIPS_INS_LUI, "lui" }, - { MIPS_INS_LW, "lw" }, - { MIPS_INS_LW16, "lw16" }, - { MIPS_INS_LWC1, "lwc1" }, - { MIPS_INS_LWC2, "lwc2" }, - { MIPS_INS_LWC3, "lwc3" }, - { MIPS_INS_LWL, "lwl" }, - { MIPS_INS_LWM16, "lwm16" }, - { MIPS_INS_LWM32, "lwm32" }, - { MIPS_INS_LWPC, "lwpc" }, - { MIPS_INS_LWP, "lwp" }, - { MIPS_INS_LWR, "lwr" }, - { MIPS_INS_LWUPC, "lwupc" }, - { MIPS_INS_LWU, "lwu" }, - { MIPS_INS_LWX, "lwx" }, - { MIPS_INS_LWXC1, "lwxc1" }, - { MIPS_INS_LWXS, "lwxs" }, - { MIPS_INS_LI, "li" }, - { MIPS_INS_MADD, "madd" }, - { MIPS_INS_MADDF, "maddf" }, - { MIPS_INS_MADDR_Q, "maddr_q" }, - { MIPS_INS_MADDU, "maddu" }, - { MIPS_INS_MADDV, "maddv" }, - { MIPS_INS_MADD_Q, "madd_q" }, - { MIPS_INS_MAQ_SA, "maq_sa" }, - { MIPS_INS_MAQ_S, "maq_s" }, - { MIPS_INS_MAXA, "maxa" }, - { MIPS_INS_MAXI_S, "maxi_s" }, - { MIPS_INS_MAXI_U, "maxi_u" }, - { MIPS_INS_MAX_A, "max_a" }, - { MIPS_INS_MAX, "max" }, - { MIPS_INS_MAX_S, "max_s" }, - { MIPS_INS_MAX_U, "max_u" }, - { MIPS_INS_MFC0, "mfc0" }, - { MIPS_INS_MFC1, "mfc1" }, - { MIPS_INS_MFC2, "mfc2" }, - { MIPS_INS_MFHC1, "mfhc1" }, - { MIPS_INS_MFHI, "mfhi" }, - { MIPS_INS_MFLO, "mflo" }, - { MIPS_INS_MINA, "mina" }, - { MIPS_INS_MINI_S, "mini_s" }, - { MIPS_INS_MINI_U, "mini_u" }, - { MIPS_INS_MIN_A, "min_a" }, - { MIPS_INS_MIN, "min" }, - { MIPS_INS_MIN_S, "min_s" }, - { MIPS_INS_MIN_U, "min_u" }, - { MIPS_INS_MOD, "mod" }, - { MIPS_INS_MODSUB, "modsub" }, - { MIPS_INS_MODU, "modu" }, - { MIPS_INS_MOD_S, "mod_s" }, - { MIPS_INS_MOD_U, "mod_u" }, - { MIPS_INS_MOVE, "move" }, - { MIPS_INS_MOVEP, "movep" }, - { MIPS_INS_MOVF, "movf" }, - { MIPS_INS_MOVN, "movn" }, - { MIPS_INS_MOVT, "movt" }, - { MIPS_INS_MOVZ, "movz" }, - { MIPS_INS_MSUB, "msub" }, - { MIPS_INS_MSUBF, "msubf" }, - { MIPS_INS_MSUBR_Q, "msubr_q" }, - { MIPS_INS_MSUBU, "msubu" }, - { MIPS_INS_MSUBV, "msubv" }, - { MIPS_INS_MSUB_Q, "msub_q" }, - { MIPS_INS_MTC0, "mtc0" }, - { MIPS_INS_MTC1, "mtc1" }, - { MIPS_INS_MTC2, "mtc2" }, - { MIPS_INS_MTHC1, "mthc1" }, - { MIPS_INS_MTHI, "mthi" }, - { MIPS_INS_MTHLIP, "mthlip" }, - { MIPS_INS_MTLO, "mtlo" }, - { MIPS_INS_MTM0, "mtm0" }, - { MIPS_INS_MTM1, "mtm1" }, - { MIPS_INS_MTM2, "mtm2" }, - { MIPS_INS_MTP0, "mtp0" }, - { MIPS_INS_MTP1, "mtp1" }, - { MIPS_INS_MTP2, "mtp2" }, - { MIPS_INS_MUH, "muh" }, - { MIPS_INS_MUHU, "muhu" }, - { MIPS_INS_MULEQ_S, "muleq_s" }, - { MIPS_INS_MULEU_S, "muleu_s" }, - { MIPS_INS_MULQ_RS, "mulq_rs" }, - { MIPS_INS_MULQ_S, "mulq_s" }, - { MIPS_INS_MULR_Q, "mulr_q" }, - { MIPS_INS_MULSAQ_S, "mulsaq_s" }, - { MIPS_INS_MULSA, "mulsa" }, - { MIPS_INS_MULT, "mult" }, - { MIPS_INS_MULTU, "multu" }, - { MIPS_INS_MULU, "mulu" }, - { MIPS_INS_MULV, "mulv" }, - { MIPS_INS_MUL_Q, "mul_q" }, - { MIPS_INS_MUL_S, "mul_s" }, - { MIPS_INS_NLOC, "nloc" }, - { MIPS_INS_NLZC, "nlzc" }, - { MIPS_INS_NMADD, "nmadd" }, - { MIPS_INS_NMSUB, "nmsub" }, - { MIPS_INS_NOR, "nor" }, - { MIPS_INS_NORI, "nori" }, - { MIPS_INS_NOT16, "not16" }, - { MIPS_INS_NOT, "not" }, - { MIPS_INS_OR, "or" }, - { MIPS_INS_OR16, "or16" }, - { MIPS_INS_ORI, "ori" }, - { MIPS_INS_PACKRL, "packrl" }, - { MIPS_INS_PAUSE, "pause" }, - { MIPS_INS_PCKEV, "pckev" }, - { MIPS_INS_PCKOD, "pckod" }, - { MIPS_INS_PCNT, "pcnt" }, - { MIPS_INS_PICK, "pick" }, - { MIPS_INS_POP, "pop" }, - { MIPS_INS_PRECEQU, "precequ" }, - { MIPS_INS_PRECEQ, "preceq" }, - { MIPS_INS_PRECEU, "preceu" }, - { MIPS_INS_PRECRQU_S, "precrqu_s" }, - { MIPS_INS_PRECRQ, "precrq" }, - { MIPS_INS_PRECRQ_RS, "precrq_rs" }, - { MIPS_INS_PRECR, "precr" }, - { MIPS_INS_PRECR_SRA, "precr_sra" }, - { MIPS_INS_PRECR_SRA_R, "precr_sra_r" }, - { MIPS_INS_PREF, "pref" }, - { MIPS_INS_PREPEND, "prepend" }, - { MIPS_INS_RADDU, "raddu" }, - { MIPS_INS_RDDSP, "rddsp" }, - { MIPS_INS_RDHWR, "rdhwr" }, - { MIPS_INS_REPLV, "replv" }, - { MIPS_INS_REPL, "repl" }, - { MIPS_INS_RINT, "rint" }, - { MIPS_INS_ROTR, "rotr" }, - { MIPS_INS_ROTRV, "rotrv" }, - { MIPS_INS_ROUND, "round" }, - { MIPS_INS_SAT_S, "sat_s" }, - { MIPS_INS_SAT_U, "sat_u" }, - { MIPS_INS_SB, "sb" }, - { MIPS_INS_SB16, "sb16" }, - { MIPS_INS_SC, "sc" }, - { MIPS_INS_SCD, "scd" }, - { MIPS_INS_SD, "sd" }, - { MIPS_INS_SDBBP, "sdbbp" }, - { MIPS_INS_SDBBP16, "sdbbp16" }, - { MIPS_INS_SDC1, "sdc1" }, - { MIPS_INS_SDC2, "sdc2" }, - { MIPS_INS_SDC3, "sdc3" }, - { MIPS_INS_SDL, "sdl" }, - { MIPS_INS_SDR, "sdr" }, - { MIPS_INS_SDXC1, "sdxc1" }, - { MIPS_INS_SEB, "seb" }, - { MIPS_INS_SEH, "seh" }, - { MIPS_INS_SELEQZ, "seleqz" }, - { MIPS_INS_SELNEZ, "selnez" }, - { MIPS_INS_SEL, "sel" }, - { MIPS_INS_SEQ, "seq" }, - { MIPS_INS_SEQI, "seqi" }, - { MIPS_INS_SH, "sh" }, - { MIPS_INS_SH16, "sh16" }, - { MIPS_INS_SHF, "shf" }, - { MIPS_INS_SHILO, "shilo" }, - { MIPS_INS_SHILOV, "shilov" }, - { MIPS_INS_SHLLV, "shllv" }, - { MIPS_INS_SHLLV_S, "shllv_s" }, - { MIPS_INS_SHLL, "shll" }, - { MIPS_INS_SHLL_S, "shll_s" }, - { MIPS_INS_SHRAV, "shrav" }, - { MIPS_INS_SHRAV_R, "shrav_r" }, - { MIPS_INS_SHRA, "shra" }, - { MIPS_INS_SHRA_R, "shra_r" }, - { MIPS_INS_SHRLV, "shrlv" }, - { MIPS_INS_SHRL, "shrl" }, - { MIPS_INS_SLDI, "sldi" }, - { MIPS_INS_SLD, "sld" }, - { MIPS_INS_SLL, "sll" }, - { MIPS_INS_SLL16, "sll16" }, - { MIPS_INS_SLLI, "slli" }, - { MIPS_INS_SLLV, "sllv" }, - { MIPS_INS_SLT, "slt" }, - { MIPS_INS_SLTI, "slti" }, - { MIPS_INS_SLTIU, "sltiu" }, - { MIPS_INS_SLTU, "sltu" }, - { MIPS_INS_SNE, "sne" }, - { MIPS_INS_SNEI, "snei" }, - { MIPS_INS_SPLATI, "splati" }, - { MIPS_INS_SPLAT, "splat" }, - { MIPS_INS_SRA, "sra" }, - { MIPS_INS_SRAI, "srai" }, - { MIPS_INS_SRARI, "srari" }, - { MIPS_INS_SRAR, "srar" }, - { MIPS_INS_SRAV, "srav" }, - { MIPS_INS_SRL, "srl" }, - { MIPS_INS_SRL16, "srl16" }, - { MIPS_INS_SRLI, "srli" }, - { MIPS_INS_SRLRI, "srlri" }, - { MIPS_INS_SRLR, "srlr" }, - { MIPS_INS_SRLV, "srlv" }, - { MIPS_INS_SSNOP, "ssnop" }, - { MIPS_INS_ST, "st" }, - { MIPS_INS_SUBQH, "subqh" }, - { MIPS_INS_SUBQH_R, "subqh_r" }, - { MIPS_INS_SUBQ, "subq" }, - { MIPS_INS_SUBQ_S, "subq_s" }, - { MIPS_INS_SUBSUS_U, "subsus_u" }, - { MIPS_INS_SUBSUU_S, "subsuu_s" }, - { MIPS_INS_SUBS_S, "subs_s" }, - { MIPS_INS_SUBS_U, "subs_u" }, - { MIPS_INS_SUBU16, "subu16" }, - { MIPS_INS_SUBUH, "subuh" }, - { MIPS_INS_SUBUH_R, "subuh_r" }, - { MIPS_INS_SUBU, "subu" }, - { MIPS_INS_SUBU_S, "subu_s" }, - { MIPS_INS_SUBVI, "subvi" }, - { MIPS_INS_SUBV, "subv" }, - { MIPS_INS_SUXC1, "suxc1" }, - { MIPS_INS_SW, "sw" }, - { MIPS_INS_SW16, "sw16" }, - { MIPS_INS_SWC1, "swc1" }, - { MIPS_INS_SWC2, "swc2" }, - { MIPS_INS_SWC3, "swc3" }, - { MIPS_INS_SWL, "swl" }, - { MIPS_INS_SWM16, "swm16" }, - { MIPS_INS_SWM32, "swm32" }, - { MIPS_INS_SWP, "swp" }, - { MIPS_INS_SWR, "swr" }, - { MIPS_INS_SWXC1, "swxc1" }, - { MIPS_INS_SYNC, "sync" }, - { MIPS_INS_SYNCI, "synci" }, - { MIPS_INS_SYSCALL, "syscall" }, - { MIPS_INS_TEQ, "teq" }, - { MIPS_INS_TEQI, "teqi" }, - { MIPS_INS_TGE, "tge" }, - { MIPS_INS_TGEI, "tgei" }, - { MIPS_INS_TGEIU, "tgeiu" }, - { MIPS_INS_TGEU, "tgeu" }, - { MIPS_INS_TLBP, "tlbp" }, - { MIPS_INS_TLBR, "tlbr" }, - { MIPS_INS_TLBWI, "tlbwi" }, - { MIPS_INS_TLBWR, "tlbwr" }, - { MIPS_INS_TLT, "tlt" }, - { MIPS_INS_TLTI, "tlti" }, - { MIPS_INS_TLTIU, "tltiu" }, - { MIPS_INS_TLTU, "tltu" }, - { MIPS_INS_TNE, "tne" }, - { MIPS_INS_TNEI, "tnei" }, - { MIPS_INS_TRUNC, "trunc" }, - { MIPS_INS_V3MULU, "v3mulu" }, - { MIPS_INS_VMM0, "vmm0" }, - { MIPS_INS_VMULU, "vmulu" }, - { MIPS_INS_VSHF, "vshf" }, - { MIPS_INS_WAIT, "wait" }, - { MIPS_INS_WRDSP, "wrdsp" }, - { MIPS_INS_WSBH, "wsbh" }, - { MIPS_INS_XOR, "xor" }, - { MIPS_INS_XOR16, "xor16" }, - { MIPS_INS_XORI, "xori" }, - - // alias instructions - { MIPS_INS_NOP, "nop" }, - { MIPS_INS_NEGU, "negu" }, - - { MIPS_INS_JALR_HB, "jalr.hb" }, - { MIPS_INS_JR_HB, "jr.hb" }, +static const char *const insn_name_maps[] = { +#include "MipsGenCSMappingInsnName.inc" }; const char *Mips_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - if (id >= MIPS_INS_ENDING) - return NULL; - - return insn_name_maps[id].name; + if (id < ARR_SIZE(insn_name_maps)) + return insn_name_maps[id]; + // not found + return NULL; #else return NULL; #endif @@ -900,55 +65,18 @@ const char *Mips_insn_name(csh handle, unsigned int id) #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { - // generic groups { MIPS_GRP_INVALID, NULL }, + { MIPS_GRP_JUMP, "jump" }, { MIPS_GRP_CALL, "call" }, - { MIPS_GRP_RET, "ret" }, + { MIPS_GRP_RET, "return" }, { MIPS_GRP_INT, "int" }, { MIPS_GRP_IRET, "iret" }, - { MIPS_GRP_PRIVILEGE, "privileged" }, + { MIPS_GRP_PRIVILEGE, "privilege" }, { MIPS_GRP_BRANCH_RELATIVE, "branch_relative" }, - // architecture-specific groups - { MIPS_GRP_BITCOUNT, "bitcount" }, - { MIPS_GRP_DSP, "dsp" }, - { MIPS_GRP_DSPR2, "dspr2" }, - { MIPS_GRP_FPIDX, "fpidx" }, - { MIPS_GRP_MSA, "msa" }, - { MIPS_GRP_MIPS32R2, "mips32r2" }, - { MIPS_GRP_MIPS64, "mips64" }, - { MIPS_GRP_MIPS64R2, "mips64r2" }, - { MIPS_GRP_SEINREG, "seinreg" }, - { MIPS_GRP_STDENC, "stdenc" }, - { MIPS_GRP_SWAP, "swap" }, - { MIPS_GRP_MICROMIPS, "micromips" }, - { MIPS_GRP_MIPS16MODE, "mips16mode" }, - { MIPS_GRP_FP64BIT, "fp64bit" }, - { MIPS_GRP_NONANSFPMATH, "nonansfpmath" }, - { MIPS_GRP_NOTFP64BIT, "notfp64bit" }, - { MIPS_GRP_NOTINMICROMIPS, "notinmicromips" }, - { MIPS_GRP_NOTNACL, "notnacl" }, - - { MIPS_GRP_NOTMIPS32R6, "notmips32r6" }, - { MIPS_GRP_NOTMIPS64R6, "notmips64r6" }, - { MIPS_GRP_CNMIPS, "cnmips" }, - - { MIPS_GRP_MIPS32, "mips32" }, - { MIPS_GRP_MIPS32R6, "mips32r6" }, - { MIPS_GRP_MIPS64R6, "mips64r6" }, - - { MIPS_GRP_MIPS2, "mips2" }, - { MIPS_GRP_MIPS3, "mips3" }, - { MIPS_GRP_MIPS3_32, "mips3_32"}, - { MIPS_GRP_MIPS3_32R2, "mips3_32r2" }, - - { MIPS_GRP_MIPS4_32, "mips4_32" }, - { MIPS_GRP_MIPS4_32R2, "mips4_32r2" }, - { MIPS_GRP_MIPS5_32R2, "mips5_32r2" }, - - { MIPS_GRP_GP32BIT, "gp32bit" }, - { MIPS_GRP_GP64BIT, "gp64bit" }, +// architecture-specific groups +#include "MipsGenCSFeatureName.inc" }; #endif @@ -961,111 +89,379 @@ const char *Mips_group_name(csh handle, unsigned int id) #endif } -// map instruction name to public instruction ID -mips_reg Mips_map_insn(const char *name) +const insn_map mips_insns[] = { +#include "MipsGenCSMappingInsn.inc" +}; + +void Mips_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count) { - // handle special alias first - unsigned int i; + uint8_t i; + uint8_t read_count, write_count; + cs_mips *mips = &(insn->detail->mips); - // NOTE: skip first NULL name in insn_name_maps - i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); + read_count = insn->detail->regs_read_count; + write_count = insn->detail->regs_write_count; - return (i != -1)? i : MIPS_REG_INVALID; + // implicit registers + memcpy(regs_read, insn->detail->regs_read, + read_count * sizeof(insn->detail->regs_read[0])); + memcpy(regs_write, insn->detail->regs_write, + write_count * sizeof(insn->detail->regs_write[0])); + + // explicit registers + for (i = 0; i < mips->op_count; i++) { + cs_mips_op *op = &(mips->operands[i]); + switch ((int)op->type) { + case MIPS_OP_REG: + if ((op->access & CS_AC_READ) && + !arr_exist(regs_read, read_count, op->reg)) { + regs_read[read_count] = (uint16_t)op->reg; + read_count++; + } + if ((op->access & CS_AC_WRITE) && + !arr_exist(regs_write, write_count, op->reg)) { + regs_write[write_count] = (uint16_t)op->reg; + write_count++; + } + break; + case MIPS_OP_MEM: + // registers appeared in memory references always being read + if ((op->mem.base != MIPS_REG_INVALID) && + !arr_exist(regs_read, read_count, op->mem.base)) { + regs_read[read_count] = (uint16_t)op->mem.base; + read_count++; + } + if ((insn->detail->writeback) && + (op->mem.base != MIPS_REG_INVALID) && + !arr_exist(regs_write, write_count, op->mem.base)) { + regs_write[write_count] = + (uint16_t)op->mem.base; + write_count++; + } + default: + break; + } + } + + *regs_read_count = read_count; + *regs_write_count = write_count; } -// map internal raw register to 'public' register -mips_reg Mips_map_register(unsigned int r) +void Mips_set_instr_map_data(MCInst *MI) { - // for some reasons different Mips modes can map different register number to - // the same Mips register. this function handles the issue for exposing Mips - // operands by mapping internal registers to 'public' register. - static const unsigned int map[] = { 0, - MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG, - MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2, - MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5, - MIPS_REG_3, MIPS_REG_7, MIPS_REG_PC, MIPS_REG_RA, MIPS_REG_SP, - MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, - MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_AT, - MIPS_REG_CC0, MIPS_REG_CC1, MIPS_REG_CC2, MIPS_REG_CC3, MIPS_REG_CC4, - MIPS_REG_CC5, MIPS_REG_CC6, MIPS_REG_CC7, MIPS_REG_0, MIPS_REG_1, - MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, - MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_0, MIPS_REG_1, - MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, - MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, - MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, - MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, - MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, - MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, - MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, - MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, - MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, - MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, - MIPS_REG_30, MIPS_REG_31, MIPS_REG_F0, MIPS_REG_F2, MIPS_REG_F4, - MIPS_REG_F6, MIPS_REG_F8, MIPS_REG_F10, MIPS_REG_F12, MIPS_REG_F14, - MIPS_REG_F16, MIPS_REG_F18, MIPS_REG_F20, MIPS_REG_F22, MIPS_REG_F24, - MIPS_REG_F26, MIPS_REG_F28, MIPS_REG_F30, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21, - MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, - MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, - MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, - MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, - MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, - MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, - MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0, - MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5, - MIPS_REG_FCC6, MIPS_REG_FCC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, - MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, - MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, - MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, - MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, - MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, - MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_FP, - MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4, - MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9, - MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14, - MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19, - MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24, - MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29, - MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_GP, MIPS_REG_AC0, MIPS_REG_AC1, - MIPS_REG_AC2, MIPS_REG_AC3, 0, 0, 0, - 0, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, - MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, - MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, - MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, - MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, - MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_K0, - MIPS_REG_K1, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, - MIPS_REG_MPL0, MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, - MIPS_REG_P2, MIPS_REG_RA, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2, - MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, MIPS_REG_S7, - MIPS_REG_SP, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, - MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, - MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1, MIPS_REG_W0, MIPS_REG_W1, - MIPS_REG_W2, MIPS_REG_W3, MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6, - MIPS_REG_W7, MIPS_REG_W8, MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11, - MIPS_REG_W12, MIPS_REG_W13, MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16, - MIPS_REG_W17, MIPS_REG_W18, MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21, - MIPS_REG_W22, MIPS_REG_W23, MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26, - MIPS_REG_W27, MIPS_REG_W28, MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31, - MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, - MIPS_REG_AC0, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, - MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, - MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, - MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, - MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, - MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, - MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_HI, - MIPS_REG_K0, MIPS_REG_K1, MIPS_REG_LO, MIPS_REG_S0, MIPS_REG_S1, - MIPS_REG_S2, MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, - MIPS_REG_S7, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, - MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, - MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1 - }; + // Fixes for missing groups. + if (MCInst_getOpcode(MI) == Mips_JR) { + unsigned Reg = MCInst_getOpVal(MI, 0); + switch (Reg) { + case MIPS_REG_RA: + case MIPS_REG_RA_64: + add_group(MI, MIPS_GRP_RET); + break; + } + } - if (r < ARR_SIZE(map)) - return map[r]; + map_cs_id(MI, mips_insns, ARR_SIZE(mips_insns)); + map_implicit_reads(MI, mips_insns); + map_implicit_writes(MI, mips_insns); + map_groups(MI, mips_insns); +} - // cannot find this register - return 0; +bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info) +{ + uint64_t size64; + Mips_init_cs_detail(instr); + instr->MRI = (MCRegisterInfo *)info; + map_set_fill_detail_ops(instr, true); + + bool result = Mips_LLVM_getInstruction(instr, &size64, code, code_len, + address, + info) != MCDisassembler_Fail; + if (result) { + Mips_set_instr_map_data(instr); + } + *size = size64; + return result; +} + +void Mips_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info) +{ + MCRegisterInfo *MRI = (MCRegisterInfo *)info; + MI->MRI = MRI; + + Mips_LLVM_printInst(MI, MI->address, O); +} + +static void Mips_setup_op(cs_mips_op *op) +{ + memset(op, 0, sizeof(cs_mips_op)); + op->type = MIPS_OP_INVALID; +} + +void Mips_init_cs_detail(MCInst *MI) +{ + if (detail_is_set(MI)) { + unsigned int i; + + memset(get_detail(MI), 0, + offsetof(cs_detail, mips) + sizeof(cs_mips)); + + for (i = 0; i < ARR_SIZE(Mips_get_detail(MI)->operands); i++) + Mips_setup_op(&Mips_get_detail(MI)->operands[i]); + } +} + +static const map_insn_ops insn_operands[] = { +#include "MipsGenCSMappingInsnOp.inc" +}; + +static void Mips_set_detail_op_mem_reg(MCInst *MI, unsigned OpNum, mips_reg Reg) +{ + Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM; + Mips_get_detail_op(MI, 0)->mem.base = Reg; + Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); +} + +static void Mips_set_detail_op_mem_disp(MCInst *MI, unsigned OpNum, int64_t Imm) +{ + Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM; + Mips_get_detail_op(MI, 0)->mem.disp = Imm; + Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); +} + +static void Mips_set_detail_op_imm(MCInst *MI, unsigned OpNum, int64_t Imm) +{ + if (!detail_is_set(MI)) + return; + + if (doing_mem(MI)) { + Mips_set_detail_op_mem_disp(MI, OpNum, Imm); + return; + } + + Mips_get_detail_op(MI, 0)->type = MIPS_OP_IMM; + Mips_get_detail_op(MI, 0)->imm = Imm; + Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); + Mips_inc_op_count(MI); +} + +static void Mips_set_detail_op_uimm(MCInst *MI, unsigned OpNum, uint64_t Imm) +{ + if (!detail_is_set(MI)) + return; + + if (doing_mem(MI)) { + Mips_set_detail_op_mem_disp(MI, OpNum, Imm); + return; + } + + Mips_get_detail_op(MI, 0)->type = MIPS_OP_IMM; + Mips_get_detail_op(MI, 0)->uimm = Imm; + Mips_get_detail_op(MI, 0)->is_unsigned = true; + Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); + Mips_inc_op_count(MI); +} + +static void Mips_set_detail_op_reg(MCInst *MI, unsigned OpNum, mips_reg Reg, + bool is_reglist) +{ + if (!detail_is_set(MI)) + return; + + if (doing_mem(MI)) { + Mips_set_detail_op_mem_reg(MI, OpNum, Reg); + return; + } + + CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG); + Mips_get_detail_op(MI, 0)->type = MIPS_OP_REG; + Mips_get_detail_op(MI, 0)->reg = Reg; + Mips_get_detail_op(MI, 0)->is_reglist = is_reglist; + Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); + Mips_inc_op_count(MI); +} + +static void Mips_set_detail_op_operand(MCInst *MI, unsigned OpNum) +{ + cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM; + int64_t value = MCInst_getOpVal(MI, OpNum); + if (op_type == CS_OP_IMM) { + Mips_set_detail_op_imm(MI, OpNum, value); + } else if (op_type == CS_OP_REG) { + Mips_set_detail_op_reg(MI, OpNum, value, false); + } else + printf("Operand type %d not handled!\n", op_type); +} + +static void Mips_set_detail_op_branch(MCInst *MI, unsigned OpNum) +{ + cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM; + if (op_type == CS_OP_IMM) { + uint64_t Target = (uint64_t)MCInst_getOpVal(MI, OpNum); + Mips_set_detail_op_uimm(MI, OpNum, Target + MI->address); + } else if (op_type == CS_OP_REG) { + Mips_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum), + false); + } else + printf("Operand type %d not handled!\n", op_type); +} + +static void Mips_set_detail_op_unsigned(MCInst *MI, unsigned OpNum) +{ + Mips_set_detail_op_uimm(MI, OpNum, MCInst_getOpVal(MI, OpNum)); +} + +static void Mips_set_detail_op_unsigned_offset(MCInst *MI, unsigned OpNum, + unsigned Bits, uint64_t Offset) +{ + uint64_t Imm = MCInst_getOpVal(MI, OpNum); + Imm -= Offset; + Imm &= (((uint64_t)1) << Bits) - 1; + Imm += Offset; + Mips_set_detail_op_uimm(MI, OpNum, Imm); +} + +static void Mips_set_detail_op_mem_nanomips(MCInst *MI, unsigned OpNum) +{ + CS_ASSERT(doing_mem(MI)) + + MCOperand *Op = MCInst_getOperand(MI, OpNum); + Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM; + // Base is a register, but nanoMips uses the Imm value as register. + Mips_get_detail_op(MI, 0)->mem.base = MCOperand_getImm(Op); + Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); +} + +static void Mips_set_detail_op_reglist(MCInst *MI, unsigned OpNum, + bool isNanoMips) +{ + if (isNanoMips) { + for (unsigned i = OpNum; i < MCInst_getNumOperands(MI); i++) { + Mips_set_detail_op_reg(MI, i, MCInst_getOpVal(MI, i), + true); + } + return; + } + // -2 because register List is always first operand of instruction + // and it is always followed by memory operand (base + offset). + for (unsigned i = OpNum, e = MCInst_getNumOperands(MI) - 2; i != e; + ++i) { + Mips_set_detail_op_reg(MI, i, MCInst_getOpVal(MI, i), true); + } +} + +static void Mips_set_detail_op_unsigned_address(MCInst *MI, unsigned OpNum) +{ + uint64_t Target = MI->address + (uint64_t)MCInst_getOpVal(MI, OpNum); + Mips_set_detail_op_imm(MI, OpNum, Target); +} + +void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, va_list args) +{ + if (!detail_is_set(MI) || !map_fill_detail_ops(MI)) + return; + + unsigned OpNum = va_arg(args, unsigned); + + switch (op_group) { + default: + printf("Operand group %d not handled!\n", op_group); + return; + case Mips_OP_GROUP_MemOperand: + // this is only used by nanoMips. + return Mips_set_detail_op_mem_nanomips(MI, OpNum); + case Mips_OP_GROUP_BranchOperand: + /* fall-thru */ + case Mips_OP_GROUP_JumpOperand: + return Mips_set_detail_op_branch(MI, OpNum); + case Mips_OP_GROUP_Operand: + return Mips_set_detail_op_operand(MI, OpNum); + case Mips_OP_GROUP_UImm_1_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 1, 0); + case Mips_OP_GROUP_UImm_2_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 2, 0); + case Mips_OP_GROUP_UImm_3_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 3, 0); + case Mips_OP_GROUP_UImm_32_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 32, 0); + case Mips_OP_GROUP_UImm_16_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 16, 0); + case Mips_OP_GROUP_UImm_8_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 8, 0); + case Mips_OP_GROUP_UImm_5_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 0); + case Mips_OP_GROUP_UImm_6_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 0); + case Mips_OP_GROUP_UImm_4_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 4, 0); + case Mips_OP_GROUP_UImm_7_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 7, 0); + case Mips_OP_GROUP_UImm_10_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 10, 0); + case Mips_OP_GROUP_UImm_6_1: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 1); + case Mips_OP_GROUP_UImm_5_1: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 1); + case Mips_OP_GROUP_UImm_5_33: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 33); + case Mips_OP_GROUP_UImm_5_32: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 32); + case Mips_OP_GROUP_UImm_6_2: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 2); + case Mips_OP_GROUP_UImm_2_1: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 2, 1); + case Mips_OP_GROUP_UImm_0_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 0, 0); + case Mips_OP_GROUP_UImm_26_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 26, 0); + case Mips_OP_GROUP_UImm_12_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 12, 0); + case Mips_OP_GROUP_UImm_20_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 20, 0); + case Mips_OP_GROUP_RegisterList: + return Mips_set_detail_op_reglist(MI, OpNum, false); + case Mips_OP_GROUP_NanoMipsRegisterList: + return Mips_set_detail_op_reglist(MI, OpNum, true); + case Mips_OP_GROUP_PCRel: + /* fall-thru */ + case Mips_OP_GROUP_Hi20PCRel: + return Mips_set_detail_op_unsigned_address(MI, OpNum); + case Mips_OP_GROUP_Hi20: + return Mips_set_detail_op_unsigned(MI, OpNum); + } +} + +void Mips_set_mem_access(MCInst *MI, bool status) +{ + if (!detail_is_set(MI)) + return; + set_doing_mem(MI, status); + if (status) { + if (Mips_get_detail(MI)->op_count > 0 && + Mips_get_detail_op(MI, -1)->type == MIPS_OP_MEM && + Mips_get_detail_op(MI, -1)->mem.disp == 0) { + // Previous memory operand not done yet. Select it. + Mips_dec_op_count(MI); + return; + } + + // Init a new one. + Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM; + Mips_get_detail_op(MI, 0)->mem.base = MIPS_REG_INVALID; + Mips_get_detail_op(MI, 0)->mem.disp = 0; + +#ifndef CAPSTONE_DIET + uint8_t access = + map_get_op_access(MI, Mips_get_detail(MI)->op_count); + Mips_get_detail_op(MI, 0)->access = access; +#endif + } else { + // done, select the next operand slot + Mips_inc_op_count(MI); + } } #endif diff --git a/arch/Mips/MipsMapping.h b/arch/Mips/MipsMapping.h index 2b5c95dce..4f73be7fd 100644 --- a/arch/Mips/MipsMapping.h +++ b/arch/Mips/MipsMapping.h @@ -1,25 +1,62 @@ /* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* By Giovanni Dante Grazioli, deroad , 2024 */ -#ifndef CS_MIPS_MAP_H -#define CS_MIPS_MAP_H +#ifndef CS_MIPS_MAPPING_H +#define CS_MIPS_MAPPING_H -#include "capstone/capstone.h" +#include "../../include/capstone/capstone.h" +#include "../../utils.h" +#include "../../Mapping.h" + +typedef enum { +#include "MipsGenCSOpGroup.inc" +} mips_op_group; + +void Mips_init_mri(MCRegisterInfo *MRI); // return name of register in friendly string const char *Mips_reg_name(csh handle, unsigned int reg); -// given internal insn id, return public instruction info +void Mips_printer(MCInst *MI, SStream *O, + void * /* MCRegisterInfo* */ info); + +// given internal insn id, return public instruction ID void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *Mips_insn_name(csh handle, unsigned int id); const char *Mips_group_name(csh handle, unsigned int id); -// map instruction name to instruction ID -mips_reg Mips_map_insn(const char *name); +bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info); -// map internal raw register to 'public' register -mips_reg Mips_map_register(unsigned int r); +void Mips_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count); -#endif +// cs_detail related functions +void Mips_init_cs_detail(MCInst *MI); + +void Mips_set_mem_access(MCInst *MI, bool status); + +void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, va_list args); + +static inline void add_cs_detail(MCInst *MI, mips_op_group op_group, ...) +{ + if (!detail_is_set(MI)) + return; + va_list args; + va_start(args, op_group); + Mips_add_cs_detail(MI, op_group, args); + va_end(args); +} + +static inline void set_mem_access(MCInst *MI, bool status) +{ + if (!detail_is_set(MI)) + return; + Mips_set_mem_access(MI, status); +} + +#endif // CS_MIPS_MAPPING_H diff --git a/arch/Mips/MipsModule.c b/arch/Mips/MipsModule.c index e06871d3b..6a1a963cb 100644 --- a/arch/Mips/MipsModule.c +++ b/arch/Mips/MipsModule.c @@ -1,52 +1,52 @@ /* Capstone Disassembly Engine */ -/* By Dang Hoang Vu 2013 */ +/* By Giovanni Dante Grazioli, deroad , 2024 */ #ifdef CAPSTONE_HAS_MIPS -#include "../../utils.h" -#include "../../MCRegisterInfo.h" -#include "MipsDisassembler.h" -#include "MipsInstPrinter.h" -#include "MipsMapping.h" +#include + #include "MipsModule.h" - -// Returns mode value with implied bits set -static cs_mode updated_mode(cs_mode mode) -{ - if (mode & CS_MODE_MIPS32R6) { - mode |= CS_MODE_32; - } - - return mode; -} +#include "../../MCRegisterInfo.h" +#include "../../cs_priv.h" +#include "MipsMapping.h" cs_err Mips_global_init(cs_struct *ud) { MCRegisterInfo *mri; mri = cs_mem_malloc(sizeof(*mri)); - Mips_init(mri); - ud->printer = Mips_printInst; + Mips_init_mri(mri); + + ud->printer = Mips_printer; ud->printer_info = mri; ud->getinsn_info = mri; ud->reg_name = Mips_reg_name; ud->insn_id = Mips_get_insn_id; ud->insn_name = Mips_insn_name; ud->group_name = Mips_group_name; - ud->disasm = Mips_getInstruction; + ud->post_printer = NULL; +#ifndef CAPSTONE_DIET + ud->reg_access = Mips_reg_access; +#endif return CS_ERR_OK; } cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value) { - if (type == CS_OPT_MODE) { - handle->mode = updated_mode(value); - return CS_ERR_OK; + switch (type) { + case CS_OPT_MODE: + handle->mode = (cs_mode)value; + break; + case CS_OPT_SYNTAX: + handle->syntax |= (int)value; + break; + default: + break; } - return CS_ERR_OPTION; + return CS_ERR_OK; } #endif diff --git a/arch/Mips/MipsModule.h b/arch/Mips/MipsModule.h index d1aa2cfff..b404171dd 100644 --- a/arch/Mips/MipsModule.h +++ b/arch/Mips/MipsModule.h @@ -1,5 +1,5 @@ /* Capstone Disassembly Engine */ -/* By Travis Finkenauer , 2018 */ +/* By Giovanni Dante Grazioli, deroad , 2024 */ #ifndef CS_MIPS_MODULE_H #define CS_MIPS_MODULE_H @@ -9,4 +9,4 @@ cs_err Mips_global_init(cs_struct *ud); cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value); -#endif +#endif // CS_MIPS_MODULE_H diff --git a/bindings/java/capstone/Capstone.java b/bindings/java/capstone/Capstone.java index 1a37b5d40..8e5639b23 100644 --- a/bindings/java/capstone/Capstone.java +++ b/bindings/java/capstone/Capstone.java @@ -84,7 +84,7 @@ public class Capstone { public short[] regs_write = new short[20]; public byte regs_write_count; // list of semantic groups this instruction belongs to. - public byte[] groups = new byte[8]; + public byte[] groups = new byte[16]; public byte groups_count; public UnionArch arch; diff --git a/bindings/java/capstone/Mips_const.java b/bindings/java/capstone/Mips_const.java index 01f637f80..a1b66910c 100644 --- a/bindings/java/capstone/Mips_const.java +++ b/bindings/java/capstone/Mips_const.java @@ -9,816 +9,2111 @@ public class Mips_const { public static final int MIPS_OP_MEM = 3; public static final int MIPS_REG_INVALID = 0; - public static final int MIPS_REG_PC = 1; - public static final int MIPS_REG_0 = 2; - public static final int MIPS_REG_1 = 3; - public static final int MIPS_REG_2 = 4; - public static final int MIPS_REG_3 = 5; - public static final int MIPS_REG_4 = 6; - public static final int MIPS_REG_5 = 7; - public static final int MIPS_REG_6 = 8; - public static final int MIPS_REG_7 = 9; - public static final int MIPS_REG_8 = 10; - public static final int MIPS_REG_9 = 11; - public static final int MIPS_REG_10 = 12; - public static final int MIPS_REG_11 = 13; - public static final int MIPS_REG_12 = 14; - public static final int MIPS_REG_13 = 15; - public static final int MIPS_REG_14 = 16; - public static final int MIPS_REG_15 = 17; - public static final int MIPS_REG_16 = 18; - public static final int MIPS_REG_17 = 19; - public static final int MIPS_REG_18 = 20; - public static final int MIPS_REG_19 = 21; - public static final int MIPS_REG_20 = 22; - public static final int MIPS_REG_21 = 23; - public static final int MIPS_REG_22 = 24; - public static final int MIPS_REG_23 = 25; - public static final int MIPS_REG_24 = 26; - public static final int MIPS_REG_25 = 27; - public static final int MIPS_REG_26 = 28; - public static final int MIPS_REG_27 = 29; - public static final int MIPS_REG_28 = 30; - public static final int MIPS_REG_29 = 31; - public static final int MIPS_REG_30 = 32; - public static final int MIPS_REG_31 = 33; - public static final int MIPS_REG_DSPCCOND = 34; - public static final int MIPS_REG_DSPCARRY = 35; - public static final int MIPS_REG_DSPEFI = 36; - public static final int MIPS_REG_DSPOUTFLAG = 37; - public static final int MIPS_REG_DSPOUTFLAG16_19 = 38; - public static final int MIPS_REG_DSPOUTFLAG20 = 39; - public static final int MIPS_REG_DSPOUTFLAG21 = 40; - public static final int MIPS_REG_DSPOUTFLAG22 = 41; - public static final int MIPS_REG_DSPOUTFLAG23 = 42; - public static final int MIPS_REG_DSPPOS = 43; - public static final int MIPS_REG_DSPSCOUNT = 44; - public static final int MIPS_REG_AC0 = 45; - public static final int MIPS_REG_AC1 = 46; - public static final int MIPS_REG_AC2 = 47; - public static final int MIPS_REG_AC3 = 48; - public static final int MIPS_REG_CC0 = 49; - public static final int MIPS_REG_CC1 = 50; - public static final int MIPS_REG_CC2 = 51; - public static final int MIPS_REG_CC3 = 52; - public static final int MIPS_REG_CC4 = 53; - public static final int MIPS_REG_CC5 = 54; - public static final int MIPS_REG_CC6 = 55; - public static final int MIPS_REG_CC7 = 56; - public static final int MIPS_REG_F0 = 57; - public static final int MIPS_REG_F1 = 58; - public static final int MIPS_REG_F2 = 59; - public static final int MIPS_REG_F3 = 60; - public static final int MIPS_REG_F4 = 61; - public static final int MIPS_REG_F5 = 62; - public static final int MIPS_REG_F6 = 63; - public static final int MIPS_REG_F7 = 64; - public static final int MIPS_REG_F8 = 65; - public static final int MIPS_REG_F9 = 66; - public static final int MIPS_REG_F10 = 67; - public static final int MIPS_REG_F11 = 68; - public static final int MIPS_REG_F12 = 69; - public static final int MIPS_REG_F13 = 70; - public static final int MIPS_REG_F14 = 71; - public static final int MIPS_REG_F15 = 72; - public static final int MIPS_REG_F16 = 73; - public static final int MIPS_REG_F17 = 74; - public static final int MIPS_REG_F18 = 75; - public static final int MIPS_REG_F19 = 76; - public static final int MIPS_REG_F20 = 77; - public static final int MIPS_REG_F21 = 78; - public static final int MIPS_REG_F22 = 79; - public static final int MIPS_REG_F23 = 80; - public static final int MIPS_REG_F24 = 81; - public static final int MIPS_REG_F25 = 82; - public static final int MIPS_REG_F26 = 83; - public static final int MIPS_REG_F27 = 84; - public static final int MIPS_REG_F28 = 85; - public static final int MIPS_REG_F29 = 86; - public static final int MIPS_REG_F30 = 87; - public static final int MIPS_REG_F31 = 88; - public static final int MIPS_REG_FCC0 = 89; - public static final int MIPS_REG_FCC1 = 90; - public static final int MIPS_REG_FCC2 = 91; - public static final int MIPS_REG_FCC3 = 92; - public static final int MIPS_REG_FCC4 = 93; - public static final int MIPS_REG_FCC5 = 94; - public static final int MIPS_REG_FCC6 = 95; - public static final int MIPS_REG_FCC7 = 96; - public static final int MIPS_REG_W0 = 97; - public static final int MIPS_REG_W1 = 98; - public static final int MIPS_REG_W2 = 99; - public static final int MIPS_REG_W3 = 100; - public static final int MIPS_REG_W4 = 101; - public static final int MIPS_REG_W5 = 102; - public static final int MIPS_REG_W6 = 103; - public static final int MIPS_REG_W7 = 104; - public static final int MIPS_REG_W8 = 105; - public static final int MIPS_REG_W9 = 106; - public static final int MIPS_REG_W10 = 107; - public static final int MIPS_REG_W11 = 108; - public static final int MIPS_REG_W12 = 109; - public static final int MIPS_REG_W13 = 110; - public static final int MIPS_REG_W14 = 111; - public static final int MIPS_REG_W15 = 112; - public static final int MIPS_REG_W16 = 113; - public static final int MIPS_REG_W17 = 114; - public static final int MIPS_REG_W18 = 115; - public static final int MIPS_REG_W19 = 116; - public static final int MIPS_REG_W20 = 117; - public static final int MIPS_REG_W21 = 118; - public static final int MIPS_REG_W22 = 119; - public static final int MIPS_REG_W23 = 120; - public static final int MIPS_REG_W24 = 121; - public static final int MIPS_REG_W25 = 122; - public static final int MIPS_REG_W26 = 123; - public static final int MIPS_REG_W27 = 124; - public static final int MIPS_REG_W28 = 125; - public static final int MIPS_REG_W29 = 126; - public static final int MIPS_REG_W30 = 127; - public static final int MIPS_REG_W31 = 128; - public static final int MIPS_REG_HI = 129; - public static final int MIPS_REG_LO = 130; - public static final int MIPS_REG_P0 = 131; - public static final int MIPS_REG_P1 = 132; - public static final int MIPS_REG_P2 = 133; - public static final int MIPS_REG_MPL0 = 134; - public static final int MIPS_REG_MPL1 = 135; - public static final int MIPS_REG_MPL2 = 136; - public static final int MIPS_REG_ENDING = 137; - public static final int MIPS_REG_ZERO = MIPS_REG_0; - public static final int MIPS_REG_AT = MIPS_REG_1; - public static final int MIPS_REG_V0 = MIPS_REG_2; - public static final int MIPS_REG_V1 = MIPS_REG_3; - public static final int MIPS_REG_A0 = MIPS_REG_4; - public static final int MIPS_REG_A1 = MIPS_REG_5; - public static final int MIPS_REG_A2 = MIPS_REG_6; - public static final int MIPS_REG_A3 = MIPS_REG_7; - public static final int MIPS_REG_T0 = MIPS_REG_8; - public static final int MIPS_REG_T1 = MIPS_REG_9; - public static final int MIPS_REG_T2 = MIPS_REG_10; - public static final int MIPS_REG_T3 = MIPS_REG_11; - public static final int MIPS_REG_T4 = MIPS_REG_12; - public static final int MIPS_REG_T5 = MIPS_REG_13; - public static final int MIPS_REG_T6 = MIPS_REG_14; - public static final int MIPS_REG_T7 = MIPS_REG_15; - public static final int MIPS_REG_S0 = MIPS_REG_16; - public static final int MIPS_REG_S1 = MIPS_REG_17; - public static final int MIPS_REG_S2 = MIPS_REG_18; - public static final int MIPS_REG_S3 = MIPS_REG_19; - public static final int MIPS_REG_S4 = MIPS_REG_20; - public static final int MIPS_REG_S5 = MIPS_REG_21; - public static final int MIPS_REG_S6 = MIPS_REG_22; - public static final int MIPS_REG_S7 = MIPS_REG_23; - public static final int MIPS_REG_T8 = MIPS_REG_24; - public static final int MIPS_REG_T9 = MIPS_REG_25; - public static final int MIPS_REG_K0 = MIPS_REG_26; - public static final int MIPS_REG_K1 = MIPS_REG_27; - public static final int MIPS_REG_GP = MIPS_REG_28; - public static final int MIPS_REG_SP = MIPS_REG_29; - public static final int MIPS_REG_FP = MIPS_REG_30; - public static final int MIPS_REG_S8 = MIPS_REG_30; - public static final int MIPS_REG_RA = MIPS_REG_31; - public static final int MIPS_REG_HI0 = MIPS_REG_AC0; - public static final int MIPS_REG_HI1 = MIPS_REG_AC1; - public static final int MIPS_REG_HI2 = MIPS_REG_AC2; - public static final int MIPS_REG_HI3 = MIPS_REG_AC3; - public static final int MIPS_REG_LO0 = MIPS_REG_HI0; - public static final int MIPS_REG_LO1 = MIPS_REG_HI1; - public static final int MIPS_REG_LO2 = MIPS_REG_HI2; - public static final int MIPS_REG_LO3 = MIPS_REG_HI3; + public static final int MIPS_REG_AT = 1; + public static final int MIPS_REG_AT_NM = 2; + public static final int MIPS_REG_DSPCCOND = 3; + public static final int MIPS_REG_DSPCARRY = 4; + public static final int MIPS_REG_DSPEFI = 5; + public static final int MIPS_REG_DSPOUTFLAG = 6; + public static final int MIPS_REG_DSPPOS = 7; + public static final int MIPS_REG_DSPSCOUNT = 8; + public static final int MIPS_REG_FP = 9; + public static final int MIPS_REG_FP_NM = 10; + public static final int MIPS_REG_GP = 11; + public static final int MIPS_REG_GP_NM = 12; + public static final int MIPS_REG_MSAACCESS = 13; + public static final int MIPS_REG_MSACSR = 14; + public static final int MIPS_REG_MSAIR = 15; + public static final int MIPS_REG_MSAMAP = 16; + public static final int MIPS_REG_MSAMODIFY = 17; + public static final int MIPS_REG_MSAREQUEST = 18; + public static final int MIPS_REG_MSASAVE = 19; + public static final int MIPS_REG_MSAUNMAP = 20; + public static final int MIPS_REG_PC = 21; + public static final int MIPS_REG_RA = 22; + public static final int MIPS_REG_RA_NM = 23; + public static final int MIPS_REG_SP = 24; + public static final int MIPS_REG_SP_NM = 25; + public static final int MIPS_REG_ZERO = 26; + public static final int MIPS_REG_ZERO_NM = 27; + public static final int MIPS_REG_A0 = 28; + public static final int MIPS_REG_A1 = 29; + public static final int MIPS_REG_A2 = 30; + public static final int MIPS_REG_A3 = 31; + public static final int MIPS_REG_AC0 = 32; + public static final int MIPS_REG_AC1 = 33; + public static final int MIPS_REG_AC2 = 34; + public static final int MIPS_REG_AC3 = 35; + public static final int MIPS_REG_AT_64 = 36; + public static final int MIPS_REG_COP00 = 37; + public static final int MIPS_REG_COP01 = 38; + public static final int MIPS_REG_COP02 = 39; + public static final int MIPS_REG_COP03 = 40; + public static final int MIPS_REG_COP04 = 41; + public static final int MIPS_REG_COP05 = 42; + public static final int MIPS_REG_COP06 = 43; + public static final int MIPS_REG_COP07 = 44; + public static final int MIPS_REG_COP08 = 45; + public static final int MIPS_REG_COP09 = 46; + public static final int MIPS_REG_COP20 = 47; + public static final int MIPS_REG_COP21 = 48; + public static final int MIPS_REG_COP22 = 49; + public static final int MIPS_REG_COP23 = 50; + public static final int MIPS_REG_COP24 = 51; + public static final int MIPS_REG_COP25 = 52; + public static final int MIPS_REG_COP26 = 53; + public static final int MIPS_REG_COP27 = 54; + public static final int MIPS_REG_COP28 = 55; + public static final int MIPS_REG_COP29 = 56; + public static final int MIPS_REG_COP30 = 57; + public static final int MIPS_REG_COP31 = 58; + public static final int MIPS_REG_COP32 = 59; + public static final int MIPS_REG_COP33 = 60; + public static final int MIPS_REG_COP34 = 61; + public static final int MIPS_REG_COP35 = 62; + public static final int MIPS_REG_COP36 = 63; + public static final int MIPS_REG_COP37 = 64; + public static final int MIPS_REG_COP38 = 65; + public static final int MIPS_REG_COP39 = 66; + public static final int MIPS_REG_COP010 = 67; + public static final int MIPS_REG_COP011 = 68; + public static final int MIPS_REG_COP012 = 69; + public static final int MIPS_REG_COP013 = 70; + public static final int MIPS_REG_COP014 = 71; + public static final int MIPS_REG_COP015 = 72; + public static final int MIPS_REG_COP016 = 73; + public static final int MIPS_REG_COP017 = 74; + public static final int MIPS_REG_COP018 = 75; + public static final int MIPS_REG_COP019 = 76; + public static final int MIPS_REG_COP020 = 77; + public static final int MIPS_REG_COP021 = 78; + public static final int MIPS_REG_COP022 = 79; + public static final int MIPS_REG_COP023 = 80; + public static final int MIPS_REG_COP024 = 81; + public static final int MIPS_REG_COP025 = 82; + public static final int MIPS_REG_COP026 = 83; + public static final int MIPS_REG_COP027 = 84; + public static final int MIPS_REG_COP028 = 85; + public static final int MIPS_REG_COP029 = 86; + public static final int MIPS_REG_COP030 = 87; + public static final int MIPS_REG_COP031 = 88; + public static final int MIPS_REG_COP210 = 89; + public static final int MIPS_REG_COP211 = 90; + public static final int MIPS_REG_COP212 = 91; + public static final int MIPS_REG_COP213 = 92; + public static final int MIPS_REG_COP214 = 93; + public static final int MIPS_REG_COP215 = 94; + public static final int MIPS_REG_COP216 = 95; + public static final int MIPS_REG_COP217 = 96; + public static final int MIPS_REG_COP218 = 97; + public static final int MIPS_REG_COP219 = 98; + public static final int MIPS_REG_COP220 = 99; + public static final int MIPS_REG_COP221 = 100; + public static final int MIPS_REG_COP222 = 101; + public static final int MIPS_REG_COP223 = 102; + public static final int MIPS_REG_COP224 = 103; + public static final int MIPS_REG_COP225 = 104; + public static final int MIPS_REG_COP226 = 105; + public static final int MIPS_REG_COP227 = 106; + public static final int MIPS_REG_COP228 = 107; + public static final int MIPS_REG_COP229 = 108; + public static final int MIPS_REG_COP230 = 109; + public static final int MIPS_REG_COP231 = 110; + public static final int MIPS_REG_COP310 = 111; + public static final int MIPS_REG_COP311 = 112; + public static final int MIPS_REG_COP312 = 113; + public static final int MIPS_REG_COP313 = 114; + public static final int MIPS_REG_COP314 = 115; + public static final int MIPS_REG_COP315 = 116; + public static final int MIPS_REG_COP316 = 117; + public static final int MIPS_REG_COP317 = 118; + public static final int MIPS_REG_COP318 = 119; + public static final int MIPS_REG_COP319 = 120; + public static final int MIPS_REG_COP320 = 121; + public static final int MIPS_REG_COP321 = 122; + public static final int MIPS_REG_COP322 = 123; + public static final int MIPS_REG_COP323 = 124; + public static final int MIPS_REG_COP324 = 125; + public static final int MIPS_REG_COP325 = 126; + public static final int MIPS_REG_COP326 = 127; + public static final int MIPS_REG_COP327 = 128; + public static final int MIPS_REG_COP328 = 129; + public static final int MIPS_REG_COP329 = 130; + public static final int MIPS_REG_COP330 = 131; + public static final int MIPS_REG_COP331 = 132; + public static final int MIPS_REG_D0 = 133; + public static final int MIPS_REG_D1 = 134; + public static final int MIPS_REG_D2 = 135; + public static final int MIPS_REG_D3 = 136; + public static final int MIPS_REG_D4 = 137; + public static final int MIPS_REG_D5 = 138; + public static final int MIPS_REG_D6 = 139; + public static final int MIPS_REG_D7 = 140; + public static final int MIPS_REG_D8 = 141; + public static final int MIPS_REG_D9 = 142; + public static final int MIPS_REG_D10 = 143; + public static final int MIPS_REG_D11 = 144; + public static final int MIPS_REG_D12 = 145; + public static final int MIPS_REG_D13 = 146; + public static final int MIPS_REG_D14 = 147; + public static final int MIPS_REG_D15 = 148; + public static final int MIPS_REG_DSPOUTFLAG20 = 149; + public static final int MIPS_REG_DSPOUTFLAG21 = 150; + public static final int MIPS_REG_DSPOUTFLAG22 = 151; + public static final int MIPS_REG_DSPOUTFLAG23 = 152; + public static final int MIPS_REG_F0 = 153; + public static final int MIPS_REG_F1 = 154; + public static final int MIPS_REG_F2 = 155; + public static final int MIPS_REG_F3 = 156; + public static final int MIPS_REG_F4 = 157; + public static final int MIPS_REG_F5 = 158; + public static final int MIPS_REG_F6 = 159; + public static final int MIPS_REG_F7 = 160; + public static final int MIPS_REG_F8 = 161; + public static final int MIPS_REG_F9 = 162; + public static final int MIPS_REG_F10 = 163; + public static final int MIPS_REG_F11 = 164; + public static final int MIPS_REG_F12 = 165; + public static final int MIPS_REG_F13 = 166; + public static final int MIPS_REG_F14 = 167; + public static final int MIPS_REG_F15 = 168; + public static final int MIPS_REG_F16 = 169; + public static final int MIPS_REG_F17 = 170; + public static final int MIPS_REG_F18 = 171; + public static final int MIPS_REG_F19 = 172; + public static final int MIPS_REG_F20 = 173; + public static final int MIPS_REG_F21 = 174; + public static final int MIPS_REG_F22 = 175; + public static final int MIPS_REG_F23 = 176; + public static final int MIPS_REG_F24 = 177; + public static final int MIPS_REG_F25 = 178; + public static final int MIPS_REG_F26 = 179; + public static final int MIPS_REG_F27 = 180; + public static final int MIPS_REG_F28 = 181; + public static final int MIPS_REG_F29 = 182; + public static final int MIPS_REG_F30 = 183; + public static final int MIPS_REG_F31 = 184; + public static final int MIPS_REG_FCC0 = 185; + public static final int MIPS_REG_FCC1 = 186; + public static final int MIPS_REG_FCC2 = 187; + public static final int MIPS_REG_FCC3 = 188; + public static final int MIPS_REG_FCC4 = 189; + public static final int MIPS_REG_FCC5 = 190; + public static final int MIPS_REG_FCC6 = 191; + public static final int MIPS_REG_FCC7 = 192; + public static final int MIPS_REG_FCR0 = 193; + public static final int MIPS_REG_FCR1 = 194; + public static final int MIPS_REG_FCR2 = 195; + public static final int MIPS_REG_FCR3 = 196; + public static final int MIPS_REG_FCR4 = 197; + public static final int MIPS_REG_FCR5 = 198; + public static final int MIPS_REG_FCR6 = 199; + public static final int MIPS_REG_FCR7 = 200; + public static final int MIPS_REG_FCR8 = 201; + public static final int MIPS_REG_FCR9 = 202; + public static final int MIPS_REG_FCR10 = 203; + public static final int MIPS_REG_FCR11 = 204; + public static final int MIPS_REG_FCR12 = 205; + public static final int MIPS_REG_FCR13 = 206; + public static final int MIPS_REG_FCR14 = 207; + public static final int MIPS_REG_FCR15 = 208; + public static final int MIPS_REG_FCR16 = 209; + public static final int MIPS_REG_FCR17 = 210; + public static final int MIPS_REG_FCR18 = 211; + public static final int MIPS_REG_FCR19 = 212; + public static final int MIPS_REG_FCR20 = 213; + public static final int MIPS_REG_FCR21 = 214; + public static final int MIPS_REG_FCR22 = 215; + public static final int MIPS_REG_FCR23 = 216; + public static final int MIPS_REG_FCR24 = 217; + public static final int MIPS_REG_FCR25 = 218; + public static final int MIPS_REG_FCR26 = 219; + public static final int MIPS_REG_FCR27 = 220; + public static final int MIPS_REG_FCR28 = 221; + public static final int MIPS_REG_FCR29 = 222; + public static final int MIPS_REG_FCR30 = 223; + public static final int MIPS_REG_FCR31 = 224; + public static final int MIPS_REG_FP_64 = 225; + public static final int MIPS_REG_F_HI0 = 226; + public static final int MIPS_REG_F_HI1 = 227; + public static final int MIPS_REG_F_HI2 = 228; + public static final int MIPS_REG_F_HI3 = 229; + public static final int MIPS_REG_F_HI4 = 230; + public static final int MIPS_REG_F_HI5 = 231; + public static final int MIPS_REG_F_HI6 = 232; + public static final int MIPS_REG_F_HI7 = 233; + public static final int MIPS_REG_F_HI8 = 234; + public static final int MIPS_REG_F_HI9 = 235; + public static final int MIPS_REG_F_HI10 = 236; + public static final int MIPS_REG_F_HI11 = 237; + public static final int MIPS_REG_F_HI12 = 238; + public static final int MIPS_REG_F_HI13 = 239; + public static final int MIPS_REG_F_HI14 = 240; + public static final int MIPS_REG_F_HI15 = 241; + public static final int MIPS_REG_F_HI16 = 242; + public static final int MIPS_REG_F_HI17 = 243; + public static final int MIPS_REG_F_HI18 = 244; + public static final int MIPS_REG_F_HI19 = 245; + public static final int MIPS_REG_F_HI20 = 246; + public static final int MIPS_REG_F_HI21 = 247; + public static final int MIPS_REG_F_HI22 = 248; + public static final int MIPS_REG_F_HI23 = 249; + public static final int MIPS_REG_F_HI24 = 250; + public static final int MIPS_REG_F_HI25 = 251; + public static final int MIPS_REG_F_HI26 = 252; + public static final int MIPS_REG_F_HI27 = 253; + public static final int MIPS_REG_F_HI28 = 254; + public static final int MIPS_REG_F_HI29 = 255; + public static final int MIPS_REG_F_HI30 = 256; + public static final int MIPS_REG_F_HI31 = 257; + public static final int MIPS_REG_GP_64 = 258; + public static final int MIPS_REG_HI0 = 259; + public static final int MIPS_REG_HI1 = 260; + public static final int MIPS_REG_HI2 = 261; + public static final int MIPS_REG_HI3 = 262; + public static final int MIPS_REG_HWR0 = 263; + public static final int MIPS_REG_HWR1 = 264; + public static final int MIPS_REG_HWR2 = 265; + public static final int MIPS_REG_HWR3 = 266; + public static final int MIPS_REG_HWR4 = 267; + public static final int MIPS_REG_HWR5 = 268; + public static final int MIPS_REG_HWR6 = 269; + public static final int MIPS_REG_HWR7 = 270; + public static final int MIPS_REG_HWR8 = 271; + public static final int MIPS_REG_HWR9 = 272; + public static final int MIPS_REG_HWR10 = 273; + public static final int MIPS_REG_HWR11 = 274; + public static final int MIPS_REG_HWR12 = 275; + public static final int MIPS_REG_HWR13 = 276; + public static final int MIPS_REG_HWR14 = 277; + public static final int MIPS_REG_HWR15 = 278; + public static final int MIPS_REG_HWR16 = 279; + public static final int MIPS_REG_HWR17 = 280; + public static final int MIPS_REG_HWR18 = 281; + public static final int MIPS_REG_HWR19 = 282; + public static final int MIPS_REG_HWR20 = 283; + public static final int MIPS_REG_HWR21 = 284; + public static final int MIPS_REG_HWR22 = 285; + public static final int MIPS_REG_HWR23 = 286; + public static final int MIPS_REG_HWR24 = 287; + public static final int MIPS_REG_HWR25 = 288; + public static final int MIPS_REG_HWR26 = 289; + public static final int MIPS_REG_HWR27 = 290; + public static final int MIPS_REG_HWR28 = 291; + public static final int MIPS_REG_HWR29 = 292; + public static final int MIPS_REG_HWR30 = 293; + public static final int MIPS_REG_HWR31 = 294; + public static final int MIPS_REG_K0 = 295; + public static final int MIPS_REG_K1 = 296; + public static final int MIPS_REG_LO0 = 297; + public static final int MIPS_REG_LO1 = 298; + public static final int MIPS_REG_LO2 = 299; + public static final int MIPS_REG_LO3 = 300; + public static final int MIPS_REG_MPL0 = 301; + public static final int MIPS_REG_MPL1 = 302; + public static final int MIPS_REG_MPL2 = 303; + public static final int MIPS_REG_MSA8 = 304; + public static final int MIPS_REG_MSA9 = 305; + public static final int MIPS_REG_MSA10 = 306; + public static final int MIPS_REG_MSA11 = 307; + public static final int MIPS_REG_MSA12 = 308; + public static final int MIPS_REG_MSA13 = 309; + public static final int MIPS_REG_MSA14 = 310; + public static final int MIPS_REG_MSA15 = 311; + public static final int MIPS_REG_MSA16 = 312; + public static final int MIPS_REG_MSA17 = 313; + public static final int MIPS_REG_MSA18 = 314; + public static final int MIPS_REG_MSA19 = 315; + public static final int MIPS_REG_MSA20 = 316; + public static final int MIPS_REG_MSA21 = 317; + public static final int MIPS_REG_MSA22 = 318; + public static final int MIPS_REG_MSA23 = 319; + public static final int MIPS_REG_MSA24 = 320; + public static final int MIPS_REG_MSA25 = 321; + public static final int MIPS_REG_MSA26 = 322; + public static final int MIPS_REG_MSA27 = 323; + public static final int MIPS_REG_MSA28 = 324; + public static final int MIPS_REG_MSA29 = 325; + public static final int MIPS_REG_MSA30 = 326; + public static final int MIPS_REG_MSA31 = 327; + public static final int MIPS_REG_P0 = 328; + public static final int MIPS_REG_P1 = 329; + public static final int MIPS_REG_P2 = 330; + public static final int MIPS_REG_RA_64 = 331; + public static final int MIPS_REG_S0 = 332; + public static final int MIPS_REG_S1 = 333; + public static final int MIPS_REG_S2 = 334; + public static final int MIPS_REG_S3 = 335; + public static final int MIPS_REG_S4 = 336; + public static final int MIPS_REG_S5 = 337; + public static final int MIPS_REG_S6 = 338; + public static final int MIPS_REG_S7 = 339; + public static final int MIPS_REG_SP_64 = 340; + public static final int MIPS_REG_T0 = 341; + public static final int MIPS_REG_T1 = 342; + public static final int MIPS_REG_T2 = 343; + public static final int MIPS_REG_T3 = 344; + public static final int MIPS_REG_T4 = 345; + public static final int MIPS_REG_T5 = 346; + public static final int MIPS_REG_T6 = 347; + public static final int MIPS_REG_T7 = 348; + public static final int MIPS_REG_T8 = 349; + public static final int MIPS_REG_T9 = 350; + public static final int MIPS_REG_V0 = 351; + public static final int MIPS_REG_V1 = 352; + public static final int MIPS_REG_W0 = 353; + public static final int MIPS_REG_W1 = 354; + public static final int MIPS_REG_W2 = 355; + public static final int MIPS_REG_W3 = 356; + public static final int MIPS_REG_W4 = 357; + public static final int MIPS_REG_W5 = 358; + public static final int MIPS_REG_W6 = 359; + public static final int MIPS_REG_W7 = 360; + public static final int MIPS_REG_W8 = 361; + public static final int MIPS_REG_W9 = 362; + public static final int MIPS_REG_W10 = 363; + public static final int MIPS_REG_W11 = 364; + public static final int MIPS_REG_W12 = 365; + public static final int MIPS_REG_W13 = 366; + public static final int MIPS_REG_W14 = 367; + public static final int MIPS_REG_W15 = 368; + public static final int MIPS_REG_W16 = 369; + public static final int MIPS_REG_W17 = 370; + public static final int MIPS_REG_W18 = 371; + public static final int MIPS_REG_W19 = 372; + public static final int MIPS_REG_W20 = 373; + public static final int MIPS_REG_W21 = 374; + public static final int MIPS_REG_W22 = 375; + public static final int MIPS_REG_W23 = 376; + public static final int MIPS_REG_W24 = 377; + public static final int MIPS_REG_W25 = 378; + public static final int MIPS_REG_W26 = 379; + public static final int MIPS_REG_W27 = 380; + public static final int MIPS_REG_W28 = 381; + public static final int MIPS_REG_W29 = 382; + public static final int MIPS_REG_W30 = 383; + public static final int MIPS_REG_W31 = 384; + public static final int MIPS_REG_ZERO_64 = 385; + public static final int MIPS_REG_A0_NM = 386; + public static final int MIPS_REG_A1_NM = 387; + public static final int MIPS_REG_A2_NM = 388; + public static final int MIPS_REG_A3_NM = 389; + public static final int MIPS_REG_A4_NM = 390; + public static final int MIPS_REG_A5_NM = 391; + public static final int MIPS_REG_A6_NM = 392; + public static final int MIPS_REG_A7_NM = 393; + public static final int MIPS_REG_COP0SEL_BADINST = 394; + public static final int MIPS_REG_COP0SEL_BADINSTRP = 395; + public static final int MIPS_REG_COP0SEL_BADINSTRX = 396; + public static final int MIPS_REG_COP0SEL_BADVADDR = 397; + public static final int MIPS_REG_COP0SEL_BEVVA = 398; + public static final int MIPS_REG_COP0SEL_CACHEERR = 399; + public static final int MIPS_REG_COP0SEL_CAUSE = 400; + public static final int MIPS_REG_COP0SEL_CDMMBASE = 401; + public static final int MIPS_REG_COP0SEL_CMGCRBASE = 402; + public static final int MIPS_REG_COP0SEL_COMPARE = 403; + public static final int MIPS_REG_COP0SEL_CONFIG = 404; + public static final int MIPS_REG_COP0SEL_CONTEXT = 405; + public static final int MIPS_REG_COP0SEL_CONTEXTCONFIG = 406; + public static final int MIPS_REG_COP0SEL_COUNT = 407; + public static final int MIPS_REG_COP0SEL_DDATAHI = 408; + public static final int MIPS_REG_COP0SEL_DDATALO = 409; + public static final int MIPS_REG_COP0SEL_DEBUG = 410; + public static final int MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411; + public static final int MIPS_REG_COP0SEL_DEPC = 412; + public static final int MIPS_REG_COP0SEL_DESAVE = 413; + public static final int MIPS_REG_COP0SEL_DTAGHI = 414; + public static final int MIPS_REG_COP0SEL_DTAGLO = 415; + public static final int MIPS_REG_COP0SEL_EBASE = 416; + public static final int MIPS_REG_COP0SEL_ENTRYHI = 417; + public static final int MIPS_REG_COP0SEL_EPC = 418; + public static final int MIPS_REG_COP0SEL_ERRCTL = 419; + public static final int MIPS_REG_COP0SEL_ERROREPC = 420; + public static final int MIPS_REG_COP0SEL_GLOBALNUMBER = 421; + public static final int MIPS_REG_COP0SEL_GTOFFSET = 422; + public static final int MIPS_REG_COP0SEL_HWRENA = 423; + public static final int MIPS_REG_COP0SEL_IDATAHI = 424; + public static final int MIPS_REG_COP0SEL_IDATALO = 425; + public static final int MIPS_REG_COP0SEL_INDEX = 426; + public static final int MIPS_REG_COP0SEL_INTCTL = 427; + public static final int MIPS_REG_COP0SEL_ITAGHI = 428; + public static final int MIPS_REG_COP0SEL_ITAGLO = 429; + public static final int MIPS_REG_COP0SEL_LLADDR = 430; + public static final int MIPS_REG_COP0SEL_MAAR = 431; + public static final int MIPS_REG_COP0SEL_MAARI = 432; + public static final int MIPS_REG_COP0SEL_MEMORYMAPID = 433; + public static final int MIPS_REG_COP0SEL_MVPCONTROL = 434; + public static final int MIPS_REG_COP0SEL_NESTEDEPC = 435; + public static final int MIPS_REG_COP0SEL_NESTEDEXC = 436; + public static final int MIPS_REG_COP0SEL_PAGEGRAIN = 437; + public static final int MIPS_REG_COP0SEL_PAGEMASK = 438; + public static final int MIPS_REG_COP0SEL_PRID = 439; + public static final int MIPS_REG_COP0SEL_PWBASE = 440; + public static final int MIPS_REG_COP0SEL_PWCTL = 441; + public static final int MIPS_REG_COP0SEL_PWFIELD = 442; + public static final int MIPS_REG_COP0SEL_PWSIZE = 443; + public static final int MIPS_REG_COP0SEL_RANDOM = 444; + public static final int MIPS_REG_COP0SEL_SRSCTL = 445; + public static final int MIPS_REG_COP0SEL_SRSMAP = 446; + public static final int MIPS_REG_COP0SEL_STATUS = 447; + public static final int MIPS_REG_COP0SEL_TCBIND = 448; + public static final int MIPS_REG_COP0SEL_TCCONTEXT = 449; + public static final int MIPS_REG_COP0SEL_TCHALT = 450; + public static final int MIPS_REG_COP0SEL_TCOPT = 451; + public static final int MIPS_REG_COP0SEL_TCRESTART = 452; + public static final int MIPS_REG_COP0SEL_TCSCHEDULE = 453; + public static final int MIPS_REG_COP0SEL_TCSCHEFBACK = 454; + public static final int MIPS_REG_COP0SEL_TCSTATUS = 455; + public static final int MIPS_REG_COP0SEL_TRACECONTROL = 456; + public static final int MIPS_REG_COP0SEL_TRACEDBPC = 457; + public static final int MIPS_REG_COP0SEL_TRACEIBPC = 458; + public static final int MIPS_REG_COP0SEL_USERLOCAL = 459; + public static final int MIPS_REG_COP0SEL_VIEW_IPL = 460; + public static final int MIPS_REG_COP0SEL_VIEW_RIPL = 461; + public static final int MIPS_REG_COP0SEL_VPCONTROL = 462; + public static final int MIPS_REG_COP0SEL_VPECONTROL = 463; + public static final int MIPS_REG_COP0SEL_VPEOPT = 464; + public static final int MIPS_REG_COP0SEL_VPESCHEDULE = 465; + public static final int MIPS_REG_COP0SEL_VPESCHEFBACK = 466; + public static final int MIPS_REG_COP0SEL_WIRED = 467; + public static final int MIPS_REG_COP0SEL_XCONTEXT = 468; + public static final int MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469; + public static final int MIPS_REG_COP0SEL_YQMASK = 470; + public static final int MIPS_REG_K0_NM = 471; + public static final int MIPS_REG_K1_NM = 472; + public static final int MIPS_REG_S0_NM = 473; + public static final int MIPS_REG_S1_NM = 474; + public static final int MIPS_REG_S2_NM = 475; + public static final int MIPS_REG_S3_NM = 476; + public static final int MIPS_REG_S4_NM = 477; + public static final int MIPS_REG_S5_NM = 478; + public static final int MIPS_REG_S6_NM = 479; + public static final int MIPS_REG_S7_NM = 480; + public static final int MIPS_REG_T0_NM = 481; + public static final int MIPS_REG_T1_NM = 482; + public static final int MIPS_REG_T2_NM = 483; + public static final int MIPS_REG_T3_NM = 484; + public static final int MIPS_REG_T4_NM = 485; + public static final int MIPS_REG_T5_NM = 486; + public static final int MIPS_REG_T8_NM = 487; + public static final int MIPS_REG_T9_NM = 488; + public static final int MIPS_REG_A0_64 = 489; + public static final int MIPS_REG_A1_64 = 490; + public static final int MIPS_REG_A2_64 = 491; + public static final int MIPS_REG_A3_64 = 492; + public static final int MIPS_REG_AC0_64 = 493; + public static final int MIPS_REG_COP0SEL_CONFIG1 = 494; + public static final int MIPS_REG_COP0SEL_CONFIG2 = 495; + public static final int MIPS_REG_COP0SEL_CONFIG3 = 496; + public static final int MIPS_REG_COP0SEL_CONFIG4 = 497; + public static final int MIPS_REG_COP0SEL_CONFIG5 = 498; + public static final int MIPS_REG_COP0SEL_DEBUG2 = 499; + public static final int MIPS_REG_COP0SEL_ENTRYLO0 = 500; + public static final int MIPS_REG_COP0SEL_ENTRYLO1 = 501; + public static final int MIPS_REG_COP0SEL_GUESTCTL0 = 502; + public static final int MIPS_REG_COP0SEL_GUESTCTL1 = 503; + public static final int MIPS_REG_COP0SEL_GUESTCTL2 = 504; + public static final int MIPS_REG_COP0SEL_GUESTCTL3 = 505; + public static final int MIPS_REG_COP0SEL_KSCRATCH1 = 506; + public static final int MIPS_REG_COP0SEL_KSCRATCH2 = 507; + public static final int MIPS_REG_COP0SEL_KSCRATCH3 = 508; + public static final int MIPS_REG_COP0SEL_KSCRATCH4 = 509; + public static final int MIPS_REG_COP0SEL_KSCRATCH5 = 510; + public static final int MIPS_REG_COP0SEL_KSCRATCH6 = 511; + public static final int MIPS_REG_COP0SEL_MVPCONF0 = 512; + public static final int MIPS_REG_COP0SEL_MVPCONF1 = 513; + public static final int MIPS_REG_COP0SEL_PERFCNT0 = 514; + public static final int MIPS_REG_COP0SEL_PERFCNT1 = 515; + public static final int MIPS_REG_COP0SEL_PERFCNT2 = 516; + public static final int MIPS_REG_COP0SEL_PERFCNT3 = 517; + public static final int MIPS_REG_COP0SEL_PERFCNT4 = 518; + public static final int MIPS_REG_COP0SEL_PERFCNT5 = 519; + public static final int MIPS_REG_COP0SEL_PERFCNT6 = 520; + public static final int MIPS_REG_COP0SEL_PERFCNT7 = 521; + public static final int MIPS_REG_COP0SEL_PERFCTL0 = 522; + public static final int MIPS_REG_COP0SEL_PERFCTL1 = 523; + public static final int MIPS_REG_COP0SEL_PERFCTL2 = 524; + public static final int MIPS_REG_COP0SEL_PERFCTL3 = 525; + public static final int MIPS_REG_COP0SEL_PERFCTL4 = 526; + public static final int MIPS_REG_COP0SEL_PERFCTL5 = 527; + public static final int MIPS_REG_COP0SEL_PERFCTL6 = 528; + public static final int MIPS_REG_COP0SEL_PERFCTL7 = 529; + public static final int MIPS_REG_COP0SEL_SEGCTL0 = 530; + public static final int MIPS_REG_COP0SEL_SEGCTL1 = 531; + public static final int MIPS_REG_COP0SEL_SEGCTL2 = 532; + public static final int MIPS_REG_COP0SEL_SRSCONF0 = 533; + public static final int MIPS_REG_COP0SEL_SRSCONF1 = 534; + public static final int MIPS_REG_COP0SEL_SRSCONF2 = 535; + public static final int MIPS_REG_COP0SEL_SRSCONF3 = 536; + public static final int MIPS_REG_COP0SEL_SRSCONF4 = 537; + public static final int MIPS_REG_COP0SEL_SRSMAP2 = 538; + public static final int MIPS_REG_COP0SEL_TRACECONTROL2 = 539; + public static final int MIPS_REG_COP0SEL_TRACECONTROL3 = 540; + public static final int MIPS_REG_COP0SEL_USERTRACEDATA1 = 541; + public static final int MIPS_REG_COP0SEL_USERTRACEDATA2 = 542; + public static final int MIPS_REG_COP0SEL_VPECONF0 = 543; + public static final int MIPS_REG_COP0SEL_VPECONF1 = 544; + public static final int MIPS_REG_COP0SEL_WATCHHI0 = 545; + public static final int MIPS_REG_COP0SEL_WATCHHI1 = 546; + public static final int MIPS_REG_COP0SEL_WATCHHI2 = 547; + public static final int MIPS_REG_COP0SEL_WATCHHI3 = 548; + public static final int MIPS_REG_COP0SEL_WATCHHI4 = 549; + public static final int MIPS_REG_COP0SEL_WATCHHI5 = 550; + public static final int MIPS_REG_COP0SEL_WATCHHI6 = 551; + public static final int MIPS_REG_COP0SEL_WATCHHI7 = 552; + public static final int MIPS_REG_COP0SEL_WATCHHI8 = 553; + public static final int MIPS_REG_COP0SEL_WATCHHI9 = 554; + public static final int MIPS_REG_COP0SEL_WATCHHI10 = 555; + public static final int MIPS_REG_COP0SEL_WATCHHI11 = 556; + public static final int MIPS_REG_COP0SEL_WATCHHI12 = 557; + public static final int MIPS_REG_COP0SEL_WATCHHI13 = 558; + public static final int MIPS_REG_COP0SEL_WATCHHI14 = 559; + public static final int MIPS_REG_COP0SEL_WATCHHI15 = 560; + public static final int MIPS_REG_COP0SEL_WATCHLO0 = 561; + public static final int MIPS_REG_COP0SEL_WATCHLO1 = 562; + public static final int MIPS_REG_COP0SEL_WATCHLO2 = 563; + public static final int MIPS_REG_COP0SEL_WATCHLO3 = 564; + public static final int MIPS_REG_COP0SEL_WATCHLO4 = 565; + public static final int MIPS_REG_COP0SEL_WATCHLO5 = 566; + public static final int MIPS_REG_COP0SEL_WATCHLO6 = 567; + public static final int MIPS_REG_COP0SEL_WATCHLO7 = 568; + public static final int MIPS_REG_COP0SEL_WATCHLO8 = 569; + public static final int MIPS_REG_COP0SEL_WATCHLO9 = 570; + public static final int MIPS_REG_COP0SEL_WATCHLO10 = 571; + public static final int MIPS_REG_COP0SEL_WATCHLO11 = 572; + public static final int MIPS_REG_COP0SEL_WATCHLO12 = 573; + public static final int MIPS_REG_COP0SEL_WATCHLO13 = 574; + public static final int MIPS_REG_COP0SEL_WATCHLO14 = 575; + public static final int MIPS_REG_COP0SEL_WATCHLO15 = 576; + public static final int MIPS_REG_D0_64 = 577; + public static final int MIPS_REG_D1_64 = 578; + public static final int MIPS_REG_D2_64 = 579; + public static final int MIPS_REG_D3_64 = 580; + public static final int MIPS_REG_D4_64 = 581; + public static final int MIPS_REG_D5_64 = 582; + public static final int MIPS_REG_D6_64 = 583; + public static final int MIPS_REG_D7_64 = 584; + public static final int MIPS_REG_D8_64 = 585; + public static final int MIPS_REG_D9_64 = 586; + public static final int MIPS_REG_D10_64 = 587; + public static final int MIPS_REG_D11_64 = 588; + public static final int MIPS_REG_D12_64 = 589; + public static final int MIPS_REG_D13_64 = 590; + public static final int MIPS_REG_D14_64 = 591; + public static final int MIPS_REG_D15_64 = 592; + public static final int MIPS_REG_D16_64 = 593; + public static final int MIPS_REG_D17_64 = 594; + public static final int MIPS_REG_D18_64 = 595; + public static final int MIPS_REG_D19_64 = 596; + public static final int MIPS_REG_D20_64 = 597; + public static final int MIPS_REG_D21_64 = 598; + public static final int MIPS_REG_D22_64 = 599; + public static final int MIPS_REG_D23_64 = 600; + public static final int MIPS_REG_D24_64 = 601; + public static final int MIPS_REG_D25_64 = 602; + public static final int MIPS_REG_D26_64 = 603; + public static final int MIPS_REG_D27_64 = 604; + public static final int MIPS_REG_D28_64 = 605; + public static final int MIPS_REG_D29_64 = 606; + public static final int MIPS_REG_D30_64 = 607; + public static final int MIPS_REG_D31_64 = 608; + public static final int MIPS_REG_DSPOUTFLAG16_19 = 609; + public static final int MIPS_REG_HI0_64 = 610; + public static final int MIPS_REG_K0_64 = 611; + public static final int MIPS_REG_K1_64 = 612; + public static final int MIPS_REG_LO0_64 = 613; + public static final int MIPS_REG_S0_64 = 614; + public static final int MIPS_REG_S1_64 = 615; + public static final int MIPS_REG_S2_64 = 616; + public static final int MIPS_REG_S3_64 = 617; + public static final int MIPS_REG_S4_64 = 618; + public static final int MIPS_REG_S5_64 = 619; + public static final int MIPS_REG_S6_64 = 620; + public static final int MIPS_REG_S7_64 = 621; + public static final int MIPS_REG_T0_64 = 622; + public static final int MIPS_REG_T1_64 = 623; + public static final int MIPS_REG_T2_64 = 624; + public static final int MIPS_REG_T3_64 = 625; + public static final int MIPS_REG_T4_64 = 626; + public static final int MIPS_REG_T5_64 = 627; + public static final int MIPS_REG_T6_64 = 628; + public static final int MIPS_REG_T7_64 = 629; + public static final int MIPS_REG_T8_64 = 630; + public static final int MIPS_REG_T9_64 = 631; + public static final int MIPS_REG_V0_64 = 632; + public static final int MIPS_REG_V1_64 = 633; + public static final int MIPS_REG_COP0SEL_GUESTCTL0EXT = 634; + public static final int MIPS_REG_ENDING = 635; public static final int MIPS_INS_INVALID = 0; - public static final int MIPS_INS_ABSQ_S = 1; - public static final int MIPS_INS_ADD = 2; - public static final int MIPS_INS_ADDIUPC = 3; - public static final int MIPS_INS_ADDIUR1SP = 4; - public static final int MIPS_INS_ADDIUR2 = 5; - public static final int MIPS_INS_ADDIUS5 = 6; - public static final int MIPS_INS_ADDIUSP = 7; - public static final int MIPS_INS_ADDQH = 8; - public static final int MIPS_INS_ADDQH_R = 9; - public static final int MIPS_INS_ADDQ = 10; - public static final int MIPS_INS_ADDQ_S = 11; - public static final int MIPS_INS_ADDSC = 12; - public static final int MIPS_INS_ADDS_A = 13; - public static final int MIPS_INS_ADDS_S = 14; - public static final int MIPS_INS_ADDS_U = 15; - public static final int MIPS_INS_ADDU16 = 16; - public static final int MIPS_INS_ADDUH = 17; - public static final int MIPS_INS_ADDUH_R = 18; - public static final int MIPS_INS_ADDU = 19; - public static final int MIPS_INS_ADDU_S = 20; - public static final int MIPS_INS_ADDVI = 21; - public static final int MIPS_INS_ADDV = 22; - public static final int MIPS_INS_ADDWC = 23; - public static final int MIPS_INS_ADD_A = 24; - public static final int MIPS_INS_ADDI = 25; - public static final int MIPS_INS_ADDIU = 26; - public static final int MIPS_INS_ALIGN = 27; - public static final int MIPS_INS_ALUIPC = 28; - public static final int MIPS_INS_AND = 29; - public static final int MIPS_INS_AND16 = 30; - public static final int MIPS_INS_ANDI16 = 31; - public static final int MIPS_INS_ANDI = 32; - public static final int MIPS_INS_APPEND = 33; - public static final int MIPS_INS_ASUB_S = 34; - public static final int MIPS_INS_ASUB_U = 35; - public static final int MIPS_INS_AUI = 36; - public static final int MIPS_INS_AUIPC = 37; - public static final int MIPS_INS_AVER_S = 38; - public static final int MIPS_INS_AVER_U = 39; - public static final int MIPS_INS_AVE_S = 40; - public static final int MIPS_INS_AVE_U = 41; - public static final int MIPS_INS_B16 = 42; - public static final int MIPS_INS_BADDU = 43; - public static final int MIPS_INS_BAL = 44; - public static final int MIPS_INS_BALC = 45; - public static final int MIPS_INS_BALIGN = 46; - public static final int MIPS_INS_BBIT0 = 47; - public static final int MIPS_INS_BBIT032 = 48; - public static final int MIPS_INS_BBIT1 = 49; - public static final int MIPS_INS_BBIT132 = 50; - public static final int MIPS_INS_BC = 51; - public static final int MIPS_INS_BC0F = 52; - public static final int MIPS_INS_BC0FL = 53; - public static final int MIPS_INS_BC0T = 54; - public static final int MIPS_INS_BC0TL = 55; - public static final int MIPS_INS_BC1EQZ = 56; - public static final int MIPS_INS_BC1F = 57; - public static final int MIPS_INS_BC1FL = 58; - public static final int MIPS_INS_BC1NEZ = 59; - public static final int MIPS_INS_BC1T = 60; - public static final int MIPS_INS_BC1TL = 61; - public static final int MIPS_INS_BC2EQZ = 62; - public static final int MIPS_INS_BC2F = 63; - public static final int MIPS_INS_BC2FL = 64; - public static final int MIPS_INS_BC2NEZ = 65; - public static final int MIPS_INS_BC2T = 66; - public static final int MIPS_INS_BC2TL = 67; - public static final int MIPS_INS_BC3F = 68; - public static final int MIPS_INS_BC3FL = 69; - public static final int MIPS_INS_BC3T = 70; - public static final int MIPS_INS_BC3TL = 71; - public static final int MIPS_INS_BCLRI = 72; - public static final int MIPS_INS_BCLR = 73; - public static final int MIPS_INS_BEQ = 74; - public static final int MIPS_INS_BEQC = 75; - public static final int MIPS_INS_BEQL = 76; - public static final int MIPS_INS_BEQZ16 = 77; - public static final int MIPS_INS_BEQZALC = 78; - public static final int MIPS_INS_BEQZC = 79; - public static final int MIPS_INS_BGEC = 80; - public static final int MIPS_INS_BGEUC = 81; - public static final int MIPS_INS_BGEZ = 82; - public static final int MIPS_INS_BGEZAL = 83; - public static final int MIPS_INS_BGEZALC = 84; - public static final int MIPS_INS_BGEZALL = 85; - public static final int MIPS_INS_BGEZALS = 86; - public static final int MIPS_INS_BGEZC = 87; - public static final int MIPS_INS_BGEZL = 88; - public static final int MIPS_INS_BGTZ = 89; - public static final int MIPS_INS_BGTZALC = 90; - public static final int MIPS_INS_BGTZC = 91; - public static final int MIPS_INS_BGTZL = 92; - public static final int MIPS_INS_BINSLI = 93; - public static final int MIPS_INS_BINSL = 94; - public static final int MIPS_INS_BINSRI = 95; - public static final int MIPS_INS_BINSR = 96; - public static final int MIPS_INS_BITREV = 97; - public static final int MIPS_INS_BITSWAP = 98; - public static final int MIPS_INS_BLEZ = 99; - public static final int MIPS_INS_BLEZALC = 100; - public static final int MIPS_INS_BLEZC = 101; - public static final int MIPS_INS_BLEZL = 102; - public static final int MIPS_INS_BLTC = 103; - public static final int MIPS_INS_BLTUC = 104; - public static final int MIPS_INS_BLTZ = 105; - public static final int MIPS_INS_BLTZAL = 106; - public static final int MIPS_INS_BLTZALC = 107; - public static final int MIPS_INS_BLTZALL = 108; - public static final int MIPS_INS_BLTZALS = 109; - public static final int MIPS_INS_BLTZC = 110; - public static final int MIPS_INS_BLTZL = 111; - public static final int MIPS_INS_BMNZI = 112; - public static final int MIPS_INS_BMNZ = 113; - public static final int MIPS_INS_BMZI = 114; - public static final int MIPS_INS_BMZ = 115; - public static final int MIPS_INS_BNE = 116; - public static final int MIPS_INS_BNEC = 117; - public static final int MIPS_INS_BNEGI = 118; - public static final int MIPS_INS_BNEG = 119; - public static final int MIPS_INS_BNEL = 120; - public static final int MIPS_INS_BNEZ16 = 121; - public static final int MIPS_INS_BNEZALC = 122; - public static final int MIPS_INS_BNEZC = 123; - public static final int MIPS_INS_BNVC = 124; - public static final int MIPS_INS_BNZ = 125; - public static final int MIPS_INS_BOVC = 126; - public static final int MIPS_INS_BPOSGE32 = 127; - public static final int MIPS_INS_BREAK = 128; - public static final int MIPS_INS_BREAK16 = 129; - public static final int MIPS_INS_BSELI = 130; - public static final int MIPS_INS_BSEL = 131; - public static final int MIPS_INS_BSETI = 132; - public static final int MIPS_INS_BSET = 133; - public static final int MIPS_INS_BZ = 134; - public static final int MIPS_INS_BEQZ = 135; - public static final int MIPS_INS_B = 136; - public static final int MIPS_INS_BNEZ = 137; - public static final int MIPS_INS_BTEQZ = 138; - public static final int MIPS_INS_BTNEZ = 139; - public static final int MIPS_INS_CACHE = 140; - public static final int MIPS_INS_CEIL = 141; - public static final int MIPS_INS_CEQI = 142; - public static final int MIPS_INS_CEQ = 143; - public static final int MIPS_INS_CFC1 = 144; - public static final int MIPS_INS_CFCMSA = 145; - public static final int MIPS_INS_CINS = 146; - public static final int MIPS_INS_CINS32 = 147; - public static final int MIPS_INS_CLASS = 148; - public static final int MIPS_INS_CLEI_S = 149; - public static final int MIPS_INS_CLEI_U = 150; - public static final int MIPS_INS_CLE_S = 151; - public static final int MIPS_INS_CLE_U = 152; - public static final int MIPS_INS_CLO = 153; - public static final int MIPS_INS_CLTI_S = 154; - public static final int MIPS_INS_CLTI_U = 155; - public static final int MIPS_INS_CLT_S = 156; - public static final int MIPS_INS_CLT_U = 157; - public static final int MIPS_INS_CLZ = 158; - public static final int MIPS_INS_CMPGDU = 159; - public static final int MIPS_INS_CMPGU = 160; - public static final int MIPS_INS_CMPU = 161; - public static final int MIPS_INS_CMP = 162; - public static final int MIPS_INS_COPY_S = 163; - public static final int MIPS_INS_COPY_U = 164; - public static final int MIPS_INS_CTC1 = 165; - public static final int MIPS_INS_CTCMSA = 166; - public static final int MIPS_INS_CVT = 167; - public static final int MIPS_INS_C = 168; - public static final int MIPS_INS_CMPI = 169; - public static final int MIPS_INS_DADD = 170; - public static final int MIPS_INS_DADDI = 171; - public static final int MIPS_INS_DADDIU = 172; - public static final int MIPS_INS_DADDU = 173; - public static final int MIPS_INS_DAHI = 174; - public static final int MIPS_INS_DALIGN = 175; - public static final int MIPS_INS_DATI = 176; - public static final int MIPS_INS_DAUI = 177; - public static final int MIPS_INS_DBITSWAP = 178; - public static final int MIPS_INS_DCLO = 179; - public static final int MIPS_INS_DCLZ = 180; - public static final int MIPS_INS_DDIV = 181; - public static final int MIPS_INS_DDIVU = 182; - public static final int MIPS_INS_DERET = 183; - public static final int MIPS_INS_DEXT = 184; - public static final int MIPS_INS_DEXTM = 185; - public static final int MIPS_INS_DEXTU = 186; - public static final int MIPS_INS_DI = 187; - public static final int MIPS_INS_DINS = 188; - public static final int MIPS_INS_DINSM = 189; - public static final int MIPS_INS_DINSU = 190; - public static final int MIPS_INS_DIV = 191; - public static final int MIPS_INS_DIVU = 192; - public static final int MIPS_INS_DIV_S = 193; - public static final int MIPS_INS_DIV_U = 194; - public static final int MIPS_INS_DLSA = 195; - public static final int MIPS_INS_DMFC0 = 196; - public static final int MIPS_INS_DMFC1 = 197; - public static final int MIPS_INS_DMFC2 = 198; - public static final int MIPS_INS_DMOD = 199; - public static final int MIPS_INS_DMODU = 200; - public static final int MIPS_INS_DMTC0 = 201; - public static final int MIPS_INS_DMTC1 = 202; - public static final int MIPS_INS_DMTC2 = 203; - public static final int MIPS_INS_DMUH = 204; - public static final int MIPS_INS_DMUHU = 205; - public static final int MIPS_INS_DMUL = 206; - public static final int MIPS_INS_DMULT = 207; - public static final int MIPS_INS_DMULTU = 208; - public static final int MIPS_INS_DMULU = 209; - public static final int MIPS_INS_DOTP_S = 210; - public static final int MIPS_INS_DOTP_U = 211; - public static final int MIPS_INS_DPADD_S = 212; - public static final int MIPS_INS_DPADD_U = 213; - public static final int MIPS_INS_DPAQX_SA = 214; - public static final int MIPS_INS_DPAQX_S = 215; - public static final int MIPS_INS_DPAQ_SA = 216; - public static final int MIPS_INS_DPAQ_S = 217; - public static final int MIPS_INS_DPAU = 218; - public static final int MIPS_INS_DPAX = 219; - public static final int MIPS_INS_DPA = 220; - public static final int MIPS_INS_DPOP = 221; - public static final int MIPS_INS_DPSQX_SA = 222; - public static final int MIPS_INS_DPSQX_S = 223; - public static final int MIPS_INS_DPSQ_SA = 224; - public static final int MIPS_INS_DPSQ_S = 225; - public static final int MIPS_INS_DPSUB_S = 226; - public static final int MIPS_INS_DPSUB_U = 227; - public static final int MIPS_INS_DPSU = 228; - public static final int MIPS_INS_DPSX = 229; - public static final int MIPS_INS_DPS = 230; - public static final int MIPS_INS_DROTR = 231; - public static final int MIPS_INS_DROTR32 = 232; - public static final int MIPS_INS_DROTRV = 233; - public static final int MIPS_INS_DSBH = 234; - public static final int MIPS_INS_DSHD = 235; - public static final int MIPS_INS_DSLL = 236; - public static final int MIPS_INS_DSLL32 = 237; - public static final int MIPS_INS_DSLLV = 238; - public static final int MIPS_INS_DSRA = 239; - public static final int MIPS_INS_DSRA32 = 240; - public static final int MIPS_INS_DSRAV = 241; - public static final int MIPS_INS_DSRL = 242; - public static final int MIPS_INS_DSRL32 = 243; - public static final int MIPS_INS_DSRLV = 244; - public static final int MIPS_INS_DSUB = 245; - public static final int MIPS_INS_DSUBU = 246; - public static final int MIPS_INS_EHB = 247; - public static final int MIPS_INS_EI = 248; - public static final int MIPS_INS_ERET = 249; - public static final int MIPS_INS_EXT = 250; - public static final int MIPS_INS_EXTP = 251; - public static final int MIPS_INS_EXTPDP = 252; - public static final int MIPS_INS_EXTPDPV = 253; - public static final int MIPS_INS_EXTPV = 254; - public static final int MIPS_INS_EXTRV_RS = 255; - public static final int MIPS_INS_EXTRV_R = 256; - public static final int MIPS_INS_EXTRV_S = 257; - public static final int MIPS_INS_EXTRV = 258; - public static final int MIPS_INS_EXTR_RS = 259; - public static final int MIPS_INS_EXTR_R = 260; - public static final int MIPS_INS_EXTR_S = 261; - public static final int MIPS_INS_EXTR = 262; - public static final int MIPS_INS_EXTS = 263; - public static final int MIPS_INS_EXTS32 = 264; - public static final int MIPS_INS_ABS = 265; - public static final int MIPS_INS_FADD = 266; - public static final int MIPS_INS_FCAF = 267; - public static final int MIPS_INS_FCEQ = 268; - public static final int MIPS_INS_FCLASS = 269; - public static final int MIPS_INS_FCLE = 270; - public static final int MIPS_INS_FCLT = 271; - public static final int MIPS_INS_FCNE = 272; - public static final int MIPS_INS_FCOR = 273; - public static final int MIPS_INS_FCUEQ = 274; - public static final int MIPS_INS_FCULE = 275; - public static final int MIPS_INS_FCULT = 276; - public static final int MIPS_INS_FCUNE = 277; - public static final int MIPS_INS_FCUN = 278; - public static final int MIPS_INS_FDIV = 279; - public static final int MIPS_INS_FEXDO = 280; - public static final int MIPS_INS_FEXP2 = 281; - public static final int MIPS_INS_FEXUPL = 282; - public static final int MIPS_INS_FEXUPR = 283; - public static final int MIPS_INS_FFINT_S = 284; - public static final int MIPS_INS_FFINT_U = 285; - public static final int MIPS_INS_FFQL = 286; - public static final int MIPS_INS_FFQR = 287; - public static final int MIPS_INS_FILL = 288; - public static final int MIPS_INS_FLOG2 = 289; - public static final int MIPS_INS_FLOOR = 290; - public static final int MIPS_INS_FMADD = 291; - public static final int MIPS_INS_FMAX_A = 292; - public static final int MIPS_INS_FMAX = 293; - public static final int MIPS_INS_FMIN_A = 294; - public static final int MIPS_INS_FMIN = 295; - public static final int MIPS_INS_MOV = 296; - public static final int MIPS_INS_FMSUB = 297; - public static final int MIPS_INS_FMUL = 298; - public static final int MIPS_INS_MUL = 299; - public static final int MIPS_INS_NEG = 300; - public static final int MIPS_INS_FRCP = 301; - public static final int MIPS_INS_FRINT = 302; - public static final int MIPS_INS_FRSQRT = 303; - public static final int MIPS_INS_FSAF = 304; - public static final int MIPS_INS_FSEQ = 305; - public static final int MIPS_INS_FSLE = 306; - public static final int MIPS_INS_FSLT = 307; - public static final int MIPS_INS_FSNE = 308; - public static final int MIPS_INS_FSOR = 309; - public static final int MIPS_INS_FSQRT = 310; - public static final int MIPS_INS_SQRT = 311; - public static final int MIPS_INS_FSUB = 312; - public static final int MIPS_INS_SUB = 313; - public static final int MIPS_INS_FSUEQ = 314; - public static final int MIPS_INS_FSULE = 315; - public static final int MIPS_INS_FSULT = 316; - public static final int MIPS_INS_FSUNE = 317; - public static final int MIPS_INS_FSUN = 318; - public static final int MIPS_INS_FTINT_S = 319; - public static final int MIPS_INS_FTINT_U = 320; - public static final int MIPS_INS_FTQ = 321; - public static final int MIPS_INS_FTRUNC_S = 322; - public static final int MIPS_INS_FTRUNC_U = 323; - public static final int MIPS_INS_HADD_S = 324; - public static final int MIPS_INS_HADD_U = 325; - public static final int MIPS_INS_HSUB_S = 326; - public static final int MIPS_INS_HSUB_U = 327; - public static final int MIPS_INS_ILVEV = 328; - public static final int MIPS_INS_ILVL = 329; - public static final int MIPS_INS_ILVOD = 330; - public static final int MIPS_INS_ILVR = 331; - public static final int MIPS_INS_INS = 332; - public static final int MIPS_INS_INSERT = 333; - public static final int MIPS_INS_INSV = 334; - public static final int MIPS_INS_INSVE = 335; - public static final int MIPS_INS_J = 336; - public static final int MIPS_INS_JAL = 337; - public static final int MIPS_INS_JALR = 338; - public static final int MIPS_INS_JALRS16 = 339; - public static final int MIPS_INS_JALRS = 340; - public static final int MIPS_INS_JALS = 341; - public static final int MIPS_INS_JALX = 342; - public static final int MIPS_INS_JIALC = 343; - public static final int MIPS_INS_JIC = 344; - public static final int MIPS_INS_JR = 345; - public static final int MIPS_INS_JR16 = 346; - public static final int MIPS_INS_JRADDIUSP = 347; - public static final int MIPS_INS_JRC = 348; - public static final int MIPS_INS_JALRC = 349; - public static final int MIPS_INS_LB = 350; - public static final int MIPS_INS_LBU16 = 351; - public static final int MIPS_INS_LBUX = 352; - public static final int MIPS_INS_LBU = 353; - public static final int MIPS_INS_LD = 354; - public static final int MIPS_INS_LDC1 = 355; - public static final int MIPS_INS_LDC2 = 356; - public static final int MIPS_INS_LDC3 = 357; - public static final int MIPS_INS_LDI = 358; - public static final int MIPS_INS_LDL = 359; - public static final int MIPS_INS_LDPC = 360; - public static final int MIPS_INS_LDR = 361; - public static final int MIPS_INS_LDXC1 = 362; - public static final int MIPS_INS_LH = 363; - public static final int MIPS_INS_LHU16 = 364; - public static final int MIPS_INS_LHX = 365; - public static final int MIPS_INS_LHU = 366; - public static final int MIPS_INS_LI16 = 367; - public static final int MIPS_INS_LL = 368; - public static final int MIPS_INS_LLD = 369; - public static final int MIPS_INS_LSA = 370; - public static final int MIPS_INS_LUXC1 = 371; - public static final int MIPS_INS_LUI = 372; - public static final int MIPS_INS_LW = 373; - public static final int MIPS_INS_LW16 = 374; - public static final int MIPS_INS_LWC1 = 375; - public static final int MIPS_INS_LWC2 = 376; - public static final int MIPS_INS_LWC3 = 377; - public static final int MIPS_INS_LWL = 378; - public static final int MIPS_INS_LWM16 = 379; - public static final int MIPS_INS_LWM32 = 380; - public static final int MIPS_INS_LWPC = 381; - public static final int MIPS_INS_LWP = 382; - public static final int MIPS_INS_LWR = 383; - public static final int MIPS_INS_LWUPC = 384; - public static final int MIPS_INS_LWU = 385; - public static final int MIPS_INS_LWX = 386; - public static final int MIPS_INS_LWXC1 = 387; - public static final int MIPS_INS_LWXS = 388; - public static final int MIPS_INS_LI = 389; - public static final int MIPS_INS_MADD = 390; - public static final int MIPS_INS_MADDF = 391; - public static final int MIPS_INS_MADDR_Q = 392; - public static final int MIPS_INS_MADDU = 393; - public static final int MIPS_INS_MADDV = 394; - public static final int MIPS_INS_MADD_Q = 395; - public static final int MIPS_INS_MAQ_SA = 396; - public static final int MIPS_INS_MAQ_S = 397; - public static final int MIPS_INS_MAXA = 398; - public static final int MIPS_INS_MAXI_S = 399; - public static final int MIPS_INS_MAXI_U = 400; - public static final int MIPS_INS_MAX_A = 401; - public static final int MIPS_INS_MAX = 402; - public static final int MIPS_INS_MAX_S = 403; - public static final int MIPS_INS_MAX_U = 404; - public static final int MIPS_INS_MFC0 = 405; - public static final int MIPS_INS_MFC1 = 406; - public static final int MIPS_INS_MFC2 = 407; - public static final int MIPS_INS_MFHC1 = 408; - public static final int MIPS_INS_MFHI = 409; - public static final int MIPS_INS_MFLO = 410; - public static final int MIPS_INS_MINA = 411; - public static final int MIPS_INS_MINI_S = 412; - public static final int MIPS_INS_MINI_U = 413; - public static final int MIPS_INS_MIN_A = 414; - public static final int MIPS_INS_MIN = 415; - public static final int MIPS_INS_MIN_S = 416; - public static final int MIPS_INS_MIN_U = 417; - public static final int MIPS_INS_MOD = 418; - public static final int MIPS_INS_MODSUB = 419; - public static final int MIPS_INS_MODU = 420; - public static final int MIPS_INS_MOD_S = 421; - public static final int MIPS_INS_MOD_U = 422; - public static final int MIPS_INS_MOVE = 423; - public static final int MIPS_INS_MOVEP = 424; - public static final int MIPS_INS_MOVF = 425; - public static final int MIPS_INS_MOVN = 426; - public static final int MIPS_INS_MOVT = 427; - public static final int MIPS_INS_MOVZ = 428; - public static final int MIPS_INS_MSUB = 429; - public static final int MIPS_INS_MSUBF = 430; - public static final int MIPS_INS_MSUBR_Q = 431; - public static final int MIPS_INS_MSUBU = 432; - public static final int MIPS_INS_MSUBV = 433; - public static final int MIPS_INS_MSUB_Q = 434; - public static final int MIPS_INS_MTC0 = 435; - public static final int MIPS_INS_MTC1 = 436; - public static final int MIPS_INS_MTC2 = 437; - public static final int MIPS_INS_MTHC1 = 438; - public static final int MIPS_INS_MTHI = 439; - public static final int MIPS_INS_MTHLIP = 440; - public static final int MIPS_INS_MTLO = 441; - public static final int MIPS_INS_MTM0 = 442; - public static final int MIPS_INS_MTM1 = 443; - public static final int MIPS_INS_MTM2 = 444; - public static final int MIPS_INS_MTP0 = 445; - public static final int MIPS_INS_MTP1 = 446; - public static final int MIPS_INS_MTP2 = 447; - public static final int MIPS_INS_MUH = 448; - public static final int MIPS_INS_MUHU = 449; - public static final int MIPS_INS_MULEQ_S = 450; - public static final int MIPS_INS_MULEU_S = 451; - public static final int MIPS_INS_MULQ_RS = 452; - public static final int MIPS_INS_MULQ_S = 453; - public static final int MIPS_INS_MULR_Q = 454; - public static final int MIPS_INS_MULSAQ_S = 455; - public static final int MIPS_INS_MULSA = 456; - public static final int MIPS_INS_MULT = 457; - public static final int MIPS_INS_MULTU = 458; - public static final int MIPS_INS_MULU = 459; - public static final int MIPS_INS_MULV = 460; - public static final int MIPS_INS_MUL_Q = 461; - public static final int MIPS_INS_MUL_S = 462; - public static final int MIPS_INS_NLOC = 463; - public static final int MIPS_INS_NLZC = 464; - public static final int MIPS_INS_NMADD = 465; - public static final int MIPS_INS_NMSUB = 466; - public static final int MIPS_INS_NOR = 467; - public static final int MIPS_INS_NORI = 468; - public static final int MIPS_INS_NOT16 = 469; - public static final int MIPS_INS_NOT = 470; - public static final int MIPS_INS_OR = 471; - public static final int MIPS_INS_OR16 = 472; - public static final int MIPS_INS_ORI = 473; - public static final int MIPS_INS_PACKRL = 474; - public static final int MIPS_INS_PAUSE = 475; - public static final int MIPS_INS_PCKEV = 476; - public static final int MIPS_INS_PCKOD = 477; - public static final int MIPS_INS_PCNT = 478; - public static final int MIPS_INS_PICK = 479; - public static final int MIPS_INS_POP = 480; - public static final int MIPS_INS_PRECEQU = 481; - public static final int MIPS_INS_PRECEQ = 482; - public static final int MIPS_INS_PRECEU = 483; - public static final int MIPS_INS_PRECRQU_S = 484; - public static final int MIPS_INS_PRECRQ = 485; - public static final int MIPS_INS_PRECRQ_RS = 486; - public static final int MIPS_INS_PRECR = 487; - public static final int MIPS_INS_PRECR_SRA = 488; - public static final int MIPS_INS_PRECR_SRA_R = 489; - public static final int MIPS_INS_PREF = 490; - public static final int MIPS_INS_PREPEND = 491; - public static final int MIPS_INS_RADDU = 492; - public static final int MIPS_INS_RDDSP = 493; - public static final int MIPS_INS_RDHWR = 494; - public static final int MIPS_INS_REPLV = 495; - public static final int MIPS_INS_REPL = 496; - public static final int MIPS_INS_RINT = 497; - public static final int MIPS_INS_ROTR = 498; - public static final int MIPS_INS_ROTRV = 499; - public static final int MIPS_INS_ROUND = 500; - public static final int MIPS_INS_SAT_S = 501; - public static final int MIPS_INS_SAT_U = 502; - public static final int MIPS_INS_SB = 503; - public static final int MIPS_INS_SB16 = 504; - public static final int MIPS_INS_SC = 505; - public static final int MIPS_INS_SCD = 506; - public static final int MIPS_INS_SD = 507; - public static final int MIPS_INS_SDBBP = 508; - public static final int MIPS_INS_SDBBP16 = 509; - public static final int MIPS_INS_SDC1 = 510; - public static final int MIPS_INS_SDC2 = 511; - public static final int MIPS_INS_SDC3 = 512; - public static final int MIPS_INS_SDL = 513; - public static final int MIPS_INS_SDR = 514; - public static final int MIPS_INS_SDXC1 = 515; - public static final int MIPS_INS_SEB = 516; - public static final int MIPS_INS_SEH = 517; - public static final int MIPS_INS_SELEQZ = 518; - public static final int MIPS_INS_SELNEZ = 519; - public static final int MIPS_INS_SEL = 520; - public static final int MIPS_INS_SEQ = 521; - public static final int MIPS_INS_SEQI = 522; - public static final int MIPS_INS_SH = 523; - public static final int MIPS_INS_SH16 = 524; - public static final int MIPS_INS_SHF = 525; - public static final int MIPS_INS_SHILO = 526; - public static final int MIPS_INS_SHILOV = 527; - public static final int MIPS_INS_SHLLV = 528; - public static final int MIPS_INS_SHLLV_S = 529; - public static final int MIPS_INS_SHLL = 530; - public static final int MIPS_INS_SHLL_S = 531; - public static final int MIPS_INS_SHRAV = 532; - public static final int MIPS_INS_SHRAV_R = 533; - public static final int MIPS_INS_SHRA = 534; - public static final int MIPS_INS_SHRA_R = 535; - public static final int MIPS_INS_SHRLV = 536; - public static final int MIPS_INS_SHRL = 537; - public static final int MIPS_INS_SLDI = 538; - public static final int MIPS_INS_SLD = 539; - public static final int MIPS_INS_SLL = 540; - public static final int MIPS_INS_SLL16 = 541; - public static final int MIPS_INS_SLLI = 542; - public static final int MIPS_INS_SLLV = 543; - public static final int MIPS_INS_SLT = 544; - public static final int MIPS_INS_SLTI = 545; - public static final int MIPS_INS_SLTIU = 546; - public static final int MIPS_INS_SLTU = 547; - public static final int MIPS_INS_SNE = 548; - public static final int MIPS_INS_SNEI = 549; - public static final int MIPS_INS_SPLATI = 550; - public static final int MIPS_INS_SPLAT = 551; - public static final int MIPS_INS_SRA = 552; - public static final int MIPS_INS_SRAI = 553; - public static final int MIPS_INS_SRARI = 554; - public static final int MIPS_INS_SRAR = 555; - public static final int MIPS_INS_SRAV = 556; - public static final int MIPS_INS_SRL = 557; - public static final int MIPS_INS_SRL16 = 558; - public static final int MIPS_INS_SRLI = 559; - public static final int MIPS_INS_SRLRI = 560; - public static final int MIPS_INS_SRLR = 561; - public static final int MIPS_INS_SRLV = 562; - public static final int MIPS_INS_SSNOP = 563; - public static final int MIPS_INS_ST = 564; - public static final int MIPS_INS_SUBQH = 565; - public static final int MIPS_INS_SUBQH_R = 566; - public static final int MIPS_INS_SUBQ = 567; - public static final int MIPS_INS_SUBQ_S = 568; - public static final int MIPS_INS_SUBSUS_U = 569; - public static final int MIPS_INS_SUBSUU_S = 570; - public static final int MIPS_INS_SUBS_S = 571; - public static final int MIPS_INS_SUBS_U = 572; - public static final int MIPS_INS_SUBU16 = 573; - public static final int MIPS_INS_SUBUH = 574; - public static final int MIPS_INS_SUBUH_R = 575; - public static final int MIPS_INS_SUBU = 576; - public static final int MIPS_INS_SUBU_S = 577; - public static final int MIPS_INS_SUBVI = 578; - public static final int MIPS_INS_SUBV = 579; - public static final int MIPS_INS_SUXC1 = 580; - public static final int MIPS_INS_SW = 581; - public static final int MIPS_INS_SW16 = 582; - public static final int MIPS_INS_SWC1 = 583; - public static final int MIPS_INS_SWC2 = 584; - public static final int MIPS_INS_SWC3 = 585; - public static final int MIPS_INS_SWL = 586; - public static final int MIPS_INS_SWM16 = 587; - public static final int MIPS_INS_SWM32 = 588; - public static final int MIPS_INS_SWP = 589; - public static final int MIPS_INS_SWR = 590; - public static final int MIPS_INS_SWXC1 = 591; - public static final int MIPS_INS_SYNC = 592; - public static final int MIPS_INS_SYNCI = 593; - public static final int MIPS_INS_SYSCALL = 594; - public static final int MIPS_INS_TEQ = 595; - public static final int MIPS_INS_TEQI = 596; - public static final int MIPS_INS_TGE = 597; - public static final int MIPS_INS_TGEI = 598; - public static final int MIPS_INS_TGEIU = 599; - public static final int MIPS_INS_TGEU = 600; - public static final int MIPS_INS_TLBP = 601; - public static final int MIPS_INS_TLBR = 602; - public static final int MIPS_INS_TLBWI = 603; - public static final int MIPS_INS_TLBWR = 604; - public static final int MIPS_INS_TLT = 605; - public static final int MIPS_INS_TLTI = 606; - public static final int MIPS_INS_TLTIU = 607; - public static final int MIPS_INS_TLTU = 608; - public static final int MIPS_INS_TNE = 609; - public static final int MIPS_INS_TNEI = 610; - public static final int MIPS_INS_TRUNC = 611; - public static final int MIPS_INS_V3MULU = 612; - public static final int MIPS_INS_VMM0 = 613; - public static final int MIPS_INS_VMULU = 614; - public static final int MIPS_INS_VSHF = 615; - public static final int MIPS_INS_WAIT = 616; - public static final int MIPS_INS_WRDSP = 617; - public static final int MIPS_INS_WSBH = 618; - public static final int MIPS_INS_XOR = 619; - public static final int MIPS_INS_XOR16 = 620; - public static final int MIPS_INS_XORI = 621; - - // some alias instructions - public static final int MIPS_INS_NOP = 622; - public static final int MIPS_INS_NEGU = 623; - - // special instructions - public static final int MIPS_INS_JALR_HB = 624; - public static final int MIPS_INS_JR_HB = 625; - public static final int MIPS_INS_ENDING = 626; + public static final int MIPS_INS_ABS = 1; + public static final int MIPS_INS_ALIGN = 2; + public static final int MIPS_INS_BEQL = 3; + public static final int MIPS_INS_BGE = 4; + public static final int MIPS_INS_BGEL = 5; + public static final int MIPS_INS_BGEU = 6; + public static final int MIPS_INS_BGEUL = 7; + public static final int MIPS_INS_BGT = 8; + public static final int MIPS_INS_BGTL = 9; + public static final int MIPS_INS_BGTU = 10; + public static final int MIPS_INS_BGTUL = 11; + public static final int MIPS_INS_BLE = 12; + public static final int MIPS_INS_BLEL = 13; + public static final int MIPS_INS_BLEU = 14; + public static final int MIPS_INS_BLEUL = 15; + public static final int MIPS_INS_BLT = 16; + public static final int MIPS_INS_BLTL = 17; + public static final int MIPS_INS_BLTU = 18; + public static final int MIPS_INS_BLTUL = 19; + public static final int MIPS_INS_BNEL = 20; + public static final int MIPS_INS_B = 21; + public static final int MIPS_INS_BEQ = 22; + public static final int MIPS_INS_BNE = 23; + public static final int MIPS_INS_CFTC1 = 24; + public static final int MIPS_INS_CTTC1 = 25; + public static final int MIPS_INS_DMUL = 26; + public static final int MIPS_INS_DMULO = 27; + public static final int MIPS_INS_DMULOU = 28; + public static final int MIPS_INS_DROL = 29; + public static final int MIPS_INS_DROR = 30; + public static final int MIPS_INS_DDIV = 31; + public static final int MIPS_INS_DREM = 32; + public static final int MIPS_INS_DDIVU = 33; + public static final int MIPS_INS_DREMU = 34; + public static final int MIPS_INS_JAL = 35; + public static final int MIPS_INS_LD = 36; + public static final int MIPS_INS_LWM = 37; + public static final int MIPS_INS_LA = 38; + public static final int MIPS_INS_DLA = 39; + public static final int MIPS_INS_LI = 40; + public static final int MIPS_INS_DLI = 41; + public static final int MIPS_INS_LI_D = 42; + public static final int MIPS_INS_LI_S = 43; + public static final int MIPS_INS_MFTACX = 44; + public static final int MIPS_INS_MFTC0 = 45; + public static final int MIPS_INS_MFTC1 = 46; + public static final int MIPS_INS_MFTDSP = 47; + public static final int MIPS_INS_MFTGPR = 48; + public static final int MIPS_INS_MFTHC1 = 49; + public static final int MIPS_INS_MFTHI = 50; + public static final int MIPS_INS_MFTLO = 51; + public static final int MIPS_INS_MTTACX = 52; + public static final int MIPS_INS_MTTC0 = 53; + public static final int MIPS_INS_MTTC1 = 54; + public static final int MIPS_INS_MTTDSP = 55; + public static final int MIPS_INS_MTTGPR = 56; + public static final int MIPS_INS_MTTHC1 = 57; + public static final int MIPS_INS_MTTHI = 58; + public static final int MIPS_INS_MTTLO = 59; + public static final int MIPS_INS_MUL = 60; + public static final int MIPS_INS_MULO = 61; + public static final int MIPS_INS_MULOU = 62; + public static final int MIPS_INS_NOR = 63; + public static final int MIPS_INS_ADDIU = 64; + public static final int MIPS_INS_ANDI = 65; + public static final int MIPS_INS_SUBU = 66; + public static final int MIPS_INS_TRUNC_W_D = 67; + public static final int MIPS_INS_TRUNC_W_S = 68; + public static final int MIPS_INS_ROL = 69; + public static final int MIPS_INS_ROR = 70; + public static final int MIPS_INS_S_D = 71; + public static final int MIPS_INS_SD = 72; + public static final int MIPS_INS_DIV = 73; + public static final int MIPS_INS_SEQ = 74; + public static final int MIPS_INS_SGE = 75; + public static final int MIPS_INS_SGEU = 76; + public static final int MIPS_INS_SGT = 77; + public static final int MIPS_INS_SGTU = 78; + public static final int MIPS_INS_SLE = 79; + public static final int MIPS_INS_SLEU = 80; + public static final int MIPS_INS_SLT = 81; + public static final int MIPS_INS_SLTU = 82; + public static final int MIPS_INS_SNE = 83; + public static final int MIPS_INS_REM = 84; + public static final int MIPS_INS_SWM = 85; + public static final int MIPS_INS_SAA = 86; + public static final int MIPS_INS_SAAD = 87; + public static final int MIPS_INS_DIVU = 88; + public static final int MIPS_INS_REMU = 89; + public static final int MIPS_INS_ULH = 90; + public static final int MIPS_INS_ULHU = 91; + public static final int MIPS_INS_ULW = 92; + public static final int MIPS_INS_USH = 93; + public static final int MIPS_INS_USW = 94; + public static final int MIPS_INS_ABSQ_S_PH = 95; + public static final int MIPS_INS_ABSQ_S_QB = 96; + public static final int MIPS_INS_ABSQ_S_W = 97; + public static final int MIPS_INS_ADD = 98; + public static final int MIPS_INS_ADDIUPC = 99; + public static final int MIPS_INS_ADDIUR1SP = 100; + public static final int MIPS_INS_ADDIUR2 = 101; + public static final int MIPS_INS_ADDIUS5 = 102; + public static final int MIPS_INS_ADDIUSP = 103; + public static final int MIPS_INS_ADDQH_PH = 104; + public static final int MIPS_INS_ADDQH_R_PH = 105; + public static final int MIPS_INS_ADDQH_R_W = 106; + public static final int MIPS_INS_ADDQH_W = 107; + public static final int MIPS_INS_ADDQ_PH = 108; + public static final int MIPS_INS_ADDQ_S_PH = 109; + public static final int MIPS_INS_ADDQ_S_W = 110; + public static final int MIPS_INS_ADDR_PS = 111; + public static final int MIPS_INS_ADDSC = 112; + public static final int MIPS_INS_ADDS_A_B = 113; + public static final int MIPS_INS_ADDS_A_D = 114; + public static final int MIPS_INS_ADDS_A_H = 115; + public static final int MIPS_INS_ADDS_A_W = 116; + public static final int MIPS_INS_ADDS_S_B = 117; + public static final int MIPS_INS_ADDS_S_D = 118; + public static final int MIPS_INS_ADDS_S_H = 119; + public static final int MIPS_INS_ADDS_S_W = 120; + public static final int MIPS_INS_ADDS_U_B = 121; + public static final int MIPS_INS_ADDS_U_D = 122; + public static final int MIPS_INS_ADDS_U_H = 123; + public static final int MIPS_INS_ADDS_U_W = 124; + public static final int MIPS_INS_ADDU16 = 125; + public static final int MIPS_INS_ADDUH_QB = 126; + public static final int MIPS_INS_ADDUH_R_QB = 127; + public static final int MIPS_INS_ADDU = 128; + public static final int MIPS_INS_ADDU_PH = 129; + public static final int MIPS_INS_ADDU_QB = 130; + public static final int MIPS_INS_ADDU_S_PH = 131; + public static final int MIPS_INS_ADDU_S_QB = 132; + public static final int MIPS_INS_ADDVI_B = 133; + public static final int MIPS_INS_ADDVI_D = 134; + public static final int MIPS_INS_ADDVI_H = 135; + public static final int MIPS_INS_ADDVI_W = 136; + public static final int MIPS_INS_ADDV_B = 137; + public static final int MIPS_INS_ADDV_D = 138; + public static final int MIPS_INS_ADDV_H = 139; + public static final int MIPS_INS_ADDV_W = 140; + public static final int MIPS_INS_ADDWC = 141; + public static final int MIPS_INS_ADD_A_B = 142; + public static final int MIPS_INS_ADD_A_D = 143; + public static final int MIPS_INS_ADD_A_H = 144; + public static final int MIPS_INS_ADD_A_W = 145; + public static final int MIPS_INS_ADDI = 146; + public static final int MIPS_INS_ALUIPC = 147; + public static final int MIPS_INS_AND = 148; + public static final int MIPS_INS_AND16 = 149; + public static final int MIPS_INS_ANDI16 = 150; + public static final int MIPS_INS_ANDI_B = 151; + public static final int MIPS_INS_AND_V = 152; + public static final int MIPS_INS_APPEND = 153; + public static final int MIPS_INS_ASUB_S_B = 154; + public static final int MIPS_INS_ASUB_S_D = 155; + public static final int MIPS_INS_ASUB_S_H = 156; + public static final int MIPS_INS_ASUB_S_W = 157; + public static final int MIPS_INS_ASUB_U_B = 158; + public static final int MIPS_INS_ASUB_U_D = 159; + public static final int MIPS_INS_ASUB_U_H = 160; + public static final int MIPS_INS_ASUB_U_W = 161; + public static final int MIPS_INS_AUI = 162; + public static final int MIPS_INS_AUIPC = 163; + public static final int MIPS_INS_AVER_S_B = 164; + public static final int MIPS_INS_AVER_S_D = 165; + public static final int MIPS_INS_AVER_S_H = 166; + public static final int MIPS_INS_AVER_S_W = 167; + public static final int MIPS_INS_AVER_U_B = 168; + public static final int MIPS_INS_AVER_U_D = 169; + public static final int MIPS_INS_AVER_U_H = 170; + public static final int MIPS_INS_AVER_U_W = 171; + public static final int MIPS_INS_AVE_S_B = 172; + public static final int MIPS_INS_AVE_S_D = 173; + public static final int MIPS_INS_AVE_S_H = 174; + public static final int MIPS_INS_AVE_S_W = 175; + public static final int MIPS_INS_AVE_U_B = 176; + public static final int MIPS_INS_AVE_U_D = 177; + public static final int MIPS_INS_AVE_U_H = 178; + public static final int MIPS_INS_AVE_U_W = 179; + public static final int MIPS_INS_B16 = 180; + public static final int MIPS_INS_BADDU = 181; + public static final int MIPS_INS_BAL = 182; + public static final int MIPS_INS_BALC = 183; + public static final int MIPS_INS_BALIGN = 184; + public static final int MIPS_INS_BALRSC = 185; + public static final int MIPS_INS_BBEQZC = 186; + public static final int MIPS_INS_BBIT0 = 187; + public static final int MIPS_INS_BBIT032 = 188; + public static final int MIPS_INS_BBIT1 = 189; + public static final int MIPS_INS_BBIT132 = 190; + public static final int MIPS_INS_BBNEZC = 191; + public static final int MIPS_INS_BC = 192; + public static final int MIPS_INS_BC16 = 193; + public static final int MIPS_INS_BC1EQZ = 194; + public static final int MIPS_INS_BC1EQZC = 195; + public static final int MIPS_INS_BC1F = 196; + public static final int MIPS_INS_BC1FL = 197; + public static final int MIPS_INS_BC1NEZ = 198; + public static final int MIPS_INS_BC1NEZC = 199; + public static final int MIPS_INS_BC1T = 200; + public static final int MIPS_INS_BC1TL = 201; + public static final int MIPS_INS_BC2EQZ = 202; + public static final int MIPS_INS_BC2EQZC = 203; + public static final int MIPS_INS_BC2NEZ = 204; + public static final int MIPS_INS_BC2NEZC = 205; + public static final int MIPS_INS_BCLRI_B = 206; + public static final int MIPS_INS_BCLRI_D = 207; + public static final int MIPS_INS_BCLRI_H = 208; + public static final int MIPS_INS_BCLRI_W = 209; + public static final int MIPS_INS_BCLR_B = 210; + public static final int MIPS_INS_BCLR_D = 211; + public static final int MIPS_INS_BCLR_H = 212; + public static final int MIPS_INS_BCLR_W = 213; + public static final int MIPS_INS_BEQC = 214; + public static final int MIPS_INS_BEQIC = 215; + public static final int MIPS_INS_BEQZ16 = 216; + public static final int MIPS_INS_BEQZALC = 217; + public static final int MIPS_INS_BEQZC = 218; + public static final int MIPS_INS_BEQZC16 = 219; + public static final int MIPS_INS_BGEC = 220; + public static final int MIPS_INS_BGEIC = 221; + public static final int MIPS_INS_BGEIUC = 222; + public static final int MIPS_INS_BGEUC = 223; + public static final int MIPS_INS_BGEZ = 224; + public static final int MIPS_INS_BGEZAL = 225; + public static final int MIPS_INS_BGEZALC = 226; + public static final int MIPS_INS_BGEZALL = 227; + public static final int MIPS_INS_BGEZALS = 228; + public static final int MIPS_INS_BGEZC = 229; + public static final int MIPS_INS_BGEZL = 230; + public static final int MIPS_INS_BGTZ = 231; + public static final int MIPS_INS_BGTZALC = 232; + public static final int MIPS_INS_BGTZC = 233; + public static final int MIPS_INS_BGTZL = 234; + public static final int MIPS_INS_BINSLI_B = 235; + public static final int MIPS_INS_BINSLI_D = 236; + public static final int MIPS_INS_BINSLI_H = 237; + public static final int MIPS_INS_BINSLI_W = 238; + public static final int MIPS_INS_BINSL_B = 239; + public static final int MIPS_INS_BINSL_D = 240; + public static final int MIPS_INS_BINSL_H = 241; + public static final int MIPS_INS_BINSL_W = 242; + public static final int MIPS_INS_BINSRI_B = 243; + public static final int MIPS_INS_BINSRI_D = 244; + public static final int MIPS_INS_BINSRI_H = 245; + public static final int MIPS_INS_BINSRI_W = 246; + public static final int MIPS_INS_BINSR_B = 247; + public static final int MIPS_INS_BINSR_D = 248; + public static final int MIPS_INS_BINSR_H = 249; + public static final int MIPS_INS_BINSR_W = 250; + public static final int MIPS_INS_BITREV = 251; + public static final int MIPS_INS_BITREVW = 252; + public static final int MIPS_INS_BITSWAP = 253; + public static final int MIPS_INS_BLEZ = 254; + public static final int MIPS_INS_BLEZALC = 255; + public static final int MIPS_INS_BLEZC = 256; + public static final int MIPS_INS_BLEZL = 257; + public static final int MIPS_INS_BLTC = 258; + public static final int MIPS_INS_BLTIC = 259; + public static final int MIPS_INS_BLTIUC = 260; + public static final int MIPS_INS_BLTUC = 261; + public static final int MIPS_INS_BLTZ = 262; + public static final int MIPS_INS_BLTZAL = 263; + public static final int MIPS_INS_BLTZALC = 264; + public static final int MIPS_INS_BLTZALL = 265; + public static final int MIPS_INS_BLTZALS = 266; + public static final int MIPS_INS_BLTZC = 267; + public static final int MIPS_INS_BLTZL = 268; + public static final int MIPS_INS_BMNZI_B = 269; + public static final int MIPS_INS_BMNZ_V = 270; + public static final int MIPS_INS_BMZI_B = 271; + public static final int MIPS_INS_BMZ_V = 272; + public static final int MIPS_INS_BNEC = 273; + public static final int MIPS_INS_BNEGI_B = 274; + public static final int MIPS_INS_BNEGI_D = 275; + public static final int MIPS_INS_BNEGI_H = 276; + public static final int MIPS_INS_BNEGI_W = 277; + public static final int MIPS_INS_BNEG_B = 278; + public static final int MIPS_INS_BNEG_D = 279; + public static final int MIPS_INS_BNEG_H = 280; + public static final int MIPS_INS_BNEG_W = 281; + public static final int MIPS_INS_BNEIC = 282; + public static final int MIPS_INS_BNEZ16 = 283; + public static final int MIPS_INS_BNEZALC = 284; + public static final int MIPS_INS_BNEZC = 285; + public static final int MIPS_INS_BNEZC16 = 286; + public static final int MIPS_INS_BNVC = 287; + public static final int MIPS_INS_BNZ_B = 288; + public static final int MIPS_INS_BNZ_D = 289; + public static final int MIPS_INS_BNZ_H = 290; + public static final int MIPS_INS_BNZ_V = 291; + public static final int MIPS_INS_BNZ_W = 292; + public static final int MIPS_INS_BOVC = 293; + public static final int MIPS_INS_BPOSGE32 = 294; + public static final int MIPS_INS_BPOSGE32C = 295; + public static final int MIPS_INS_BREAK = 296; + public static final int MIPS_INS_BREAK16 = 297; + public static final int MIPS_INS_BRSC = 298; + public static final int MIPS_INS_BSELI_B = 299; + public static final int MIPS_INS_BSEL_V = 300; + public static final int MIPS_INS_BSETI_B = 301; + public static final int MIPS_INS_BSETI_D = 302; + public static final int MIPS_INS_BSETI_H = 303; + public static final int MIPS_INS_BSETI_W = 304; + public static final int MIPS_INS_BSET_B = 305; + public static final int MIPS_INS_BSET_D = 306; + public static final int MIPS_INS_BSET_H = 307; + public static final int MIPS_INS_BSET_W = 308; + public static final int MIPS_INS_BYTEREVW = 309; + public static final int MIPS_INS_BZ_B = 310; + public static final int MIPS_INS_BZ_D = 311; + public static final int MIPS_INS_BZ_H = 312; + public static final int MIPS_INS_BZ_V = 313; + public static final int MIPS_INS_BZ_W = 314; + public static final int MIPS_INS_BEQZ = 315; + public static final int MIPS_INS_BNEZ = 316; + public static final int MIPS_INS_BTEQZ = 317; + public static final int MIPS_INS_BTNEZ = 318; + public static final int MIPS_INS_CACHE = 319; + public static final int MIPS_INS_CACHEE = 320; + public static final int MIPS_INS_CEIL_L_D = 321; + public static final int MIPS_INS_CEIL_L_S = 322; + public static final int MIPS_INS_CEIL_W_D = 323; + public static final int MIPS_INS_CEIL_W_S = 324; + public static final int MIPS_INS_CEQI_B = 325; + public static final int MIPS_INS_CEQI_D = 326; + public static final int MIPS_INS_CEQI_H = 327; + public static final int MIPS_INS_CEQI_W = 328; + public static final int MIPS_INS_CEQ_B = 329; + public static final int MIPS_INS_CEQ_D = 330; + public static final int MIPS_INS_CEQ_H = 331; + public static final int MIPS_INS_CEQ_W = 332; + public static final int MIPS_INS_CFC1 = 333; + public static final int MIPS_INS_CFC2 = 334; + public static final int MIPS_INS_CFCMSA = 335; + public static final int MIPS_INS_CINS = 336; + public static final int MIPS_INS_CINS32 = 337; + public static final int MIPS_INS_CLASS_D = 338; + public static final int MIPS_INS_CLASS_S = 339; + public static final int MIPS_INS_CLEI_S_B = 340; + public static final int MIPS_INS_CLEI_S_D = 341; + public static final int MIPS_INS_CLEI_S_H = 342; + public static final int MIPS_INS_CLEI_S_W = 343; + public static final int MIPS_INS_CLEI_U_B = 344; + public static final int MIPS_INS_CLEI_U_D = 345; + public static final int MIPS_INS_CLEI_U_H = 346; + public static final int MIPS_INS_CLEI_U_W = 347; + public static final int MIPS_INS_CLE_S_B = 348; + public static final int MIPS_INS_CLE_S_D = 349; + public static final int MIPS_INS_CLE_S_H = 350; + public static final int MIPS_INS_CLE_S_W = 351; + public static final int MIPS_INS_CLE_U_B = 352; + public static final int MIPS_INS_CLE_U_D = 353; + public static final int MIPS_INS_CLE_U_H = 354; + public static final int MIPS_INS_CLE_U_W = 355; + public static final int MIPS_INS_CLO = 356; + public static final int MIPS_INS_CLTI_S_B = 357; + public static final int MIPS_INS_CLTI_S_D = 358; + public static final int MIPS_INS_CLTI_S_H = 359; + public static final int MIPS_INS_CLTI_S_W = 360; + public static final int MIPS_INS_CLTI_U_B = 361; + public static final int MIPS_INS_CLTI_U_D = 362; + public static final int MIPS_INS_CLTI_U_H = 363; + public static final int MIPS_INS_CLTI_U_W = 364; + public static final int MIPS_INS_CLT_S_B = 365; + public static final int MIPS_INS_CLT_S_D = 366; + public static final int MIPS_INS_CLT_S_H = 367; + public static final int MIPS_INS_CLT_S_W = 368; + public static final int MIPS_INS_CLT_U_B = 369; + public static final int MIPS_INS_CLT_U_D = 370; + public static final int MIPS_INS_CLT_U_H = 371; + public static final int MIPS_INS_CLT_U_W = 372; + public static final int MIPS_INS_CLZ = 373; + public static final int MIPS_INS_CMPGDU_EQ_QB = 374; + public static final int MIPS_INS_CMPGDU_LE_QB = 375; + public static final int MIPS_INS_CMPGDU_LT_QB = 376; + public static final int MIPS_INS_CMPGU_EQ_QB = 377; + public static final int MIPS_INS_CMPGU_LE_QB = 378; + public static final int MIPS_INS_CMPGU_LT_QB = 379; + public static final int MIPS_INS_CMPU_EQ_QB = 380; + public static final int MIPS_INS_CMPU_LE_QB = 381; + public static final int MIPS_INS_CMPU_LT_QB = 382; + public static final int MIPS_INS_CMP_AF_D = 383; + public static final int MIPS_INS_CMP_AF_S = 384; + public static final int MIPS_INS_CMP_EQ_D = 385; + public static final int MIPS_INS_CMP_EQ_PH = 386; + public static final int MIPS_INS_CMP_EQ_S = 387; + public static final int MIPS_INS_CMP_LE_D = 388; + public static final int MIPS_INS_CMP_LE_PH = 389; + public static final int MIPS_INS_CMP_LE_S = 390; + public static final int MIPS_INS_CMP_LT_D = 391; + public static final int MIPS_INS_CMP_LT_PH = 392; + public static final int MIPS_INS_CMP_LT_S = 393; + public static final int MIPS_INS_CMP_SAF_D = 394; + public static final int MIPS_INS_CMP_SAF_S = 395; + public static final int MIPS_INS_CMP_SEQ_D = 396; + public static final int MIPS_INS_CMP_SEQ_S = 397; + public static final int MIPS_INS_CMP_SLE_D = 398; + public static final int MIPS_INS_CMP_SLE_S = 399; + public static final int MIPS_INS_CMP_SLT_D = 400; + public static final int MIPS_INS_CMP_SLT_S = 401; + public static final int MIPS_INS_CMP_SUEQ_D = 402; + public static final int MIPS_INS_CMP_SUEQ_S = 403; + public static final int MIPS_INS_CMP_SULE_D = 404; + public static final int MIPS_INS_CMP_SULE_S = 405; + public static final int MIPS_INS_CMP_SULT_D = 406; + public static final int MIPS_INS_CMP_SULT_S = 407; + public static final int MIPS_INS_CMP_SUN_D = 408; + public static final int MIPS_INS_CMP_SUN_S = 409; + public static final int MIPS_INS_CMP_UEQ_D = 410; + public static final int MIPS_INS_CMP_UEQ_S = 411; + public static final int MIPS_INS_CMP_ULE_D = 412; + public static final int MIPS_INS_CMP_ULE_S = 413; + public static final int MIPS_INS_CMP_ULT_D = 414; + public static final int MIPS_INS_CMP_ULT_S = 415; + public static final int MIPS_INS_CMP_UN_D = 416; + public static final int MIPS_INS_CMP_UN_S = 417; + public static final int MIPS_INS_COPY_S_B = 418; + public static final int MIPS_INS_COPY_S_D = 419; + public static final int MIPS_INS_COPY_S_H = 420; + public static final int MIPS_INS_COPY_S_W = 421; + public static final int MIPS_INS_COPY_U_B = 422; + public static final int MIPS_INS_COPY_U_H = 423; + public static final int MIPS_INS_COPY_U_W = 424; + public static final int MIPS_INS_CRC32B = 425; + public static final int MIPS_INS_CRC32CB = 426; + public static final int MIPS_INS_CRC32CD = 427; + public static final int MIPS_INS_CRC32CH = 428; + public static final int MIPS_INS_CRC32CW = 429; + public static final int MIPS_INS_CRC32D = 430; + public static final int MIPS_INS_CRC32H = 431; + public static final int MIPS_INS_CRC32W = 432; + public static final int MIPS_INS_CTC1 = 433; + public static final int MIPS_INS_CTC2 = 434; + public static final int MIPS_INS_CTCMSA = 435; + public static final int MIPS_INS_CVT_D_S = 436; + public static final int MIPS_INS_CVT_D_W = 437; + public static final int MIPS_INS_CVT_D_L = 438; + public static final int MIPS_INS_CVT_L_D = 439; + public static final int MIPS_INS_CVT_L_S = 440; + public static final int MIPS_INS_CVT_PS_PW = 441; + public static final int MIPS_INS_CVT_PS_S = 442; + public static final int MIPS_INS_CVT_PW_PS = 443; + public static final int MIPS_INS_CVT_S_D = 444; + public static final int MIPS_INS_CVT_S_L = 445; + public static final int MIPS_INS_CVT_S_PL = 446; + public static final int MIPS_INS_CVT_S_PU = 447; + public static final int MIPS_INS_CVT_S_W = 448; + public static final int MIPS_INS_CVT_W_D = 449; + public static final int MIPS_INS_CVT_W_S = 450; + public static final int MIPS_INS_C_EQ_D = 451; + public static final int MIPS_INS_C_EQ_S = 452; + public static final int MIPS_INS_C_F_D = 453; + public static final int MIPS_INS_C_F_S = 454; + public static final int MIPS_INS_C_LE_D = 455; + public static final int MIPS_INS_C_LE_S = 456; + public static final int MIPS_INS_C_LT_D = 457; + public static final int MIPS_INS_C_LT_S = 458; + public static final int MIPS_INS_C_NGE_D = 459; + public static final int MIPS_INS_C_NGE_S = 460; + public static final int MIPS_INS_C_NGLE_D = 461; + public static final int MIPS_INS_C_NGLE_S = 462; + public static final int MIPS_INS_C_NGL_D = 463; + public static final int MIPS_INS_C_NGL_S = 464; + public static final int MIPS_INS_C_NGT_D = 465; + public static final int MIPS_INS_C_NGT_S = 466; + public static final int MIPS_INS_C_OLE_D = 467; + public static final int MIPS_INS_C_OLE_S = 468; + public static final int MIPS_INS_C_OLT_D = 469; + public static final int MIPS_INS_C_OLT_S = 470; + public static final int MIPS_INS_C_SEQ_D = 471; + public static final int MIPS_INS_C_SEQ_S = 472; + public static final int MIPS_INS_C_SF_D = 473; + public static final int MIPS_INS_C_SF_S = 474; + public static final int MIPS_INS_C_UEQ_D = 475; + public static final int MIPS_INS_C_UEQ_S = 476; + public static final int MIPS_INS_C_ULE_D = 477; + public static final int MIPS_INS_C_ULE_S = 478; + public static final int MIPS_INS_C_ULT_D = 479; + public static final int MIPS_INS_C_ULT_S = 480; + public static final int MIPS_INS_C_UN_D = 481; + public static final int MIPS_INS_C_UN_S = 482; + public static final int MIPS_INS_CMP = 483; + public static final int MIPS_INS_CMPI = 484; + public static final int MIPS_INS_DADD = 485; + public static final int MIPS_INS_DADDI = 486; + public static final int MIPS_INS_DADDIU = 487; + public static final int MIPS_INS_DADDU = 488; + public static final int MIPS_INS_DAHI = 489; + public static final int MIPS_INS_DALIGN = 490; + public static final int MIPS_INS_DATI = 491; + public static final int MIPS_INS_DAUI = 492; + public static final int MIPS_INS_DBITSWAP = 493; + public static final int MIPS_INS_DCLO = 494; + public static final int MIPS_INS_DCLZ = 495; + public static final int MIPS_INS_DERET = 496; + public static final int MIPS_INS_DEXT = 497; + public static final int MIPS_INS_DEXTM = 498; + public static final int MIPS_INS_DEXTU = 499; + public static final int MIPS_INS_DI = 500; + public static final int MIPS_INS_DINS = 501; + public static final int MIPS_INS_DINSM = 502; + public static final int MIPS_INS_DINSU = 503; + public static final int MIPS_INS_DIV_S_B = 504; + public static final int MIPS_INS_DIV_S_D = 505; + public static final int MIPS_INS_DIV_S_H = 506; + public static final int MIPS_INS_DIV_S_W = 507; + public static final int MIPS_INS_DIV_U_B = 508; + public static final int MIPS_INS_DIV_U_D = 509; + public static final int MIPS_INS_DIV_U_H = 510; + public static final int MIPS_INS_DIV_U_W = 511; + public static final int MIPS_INS_DLSA = 512; + public static final int MIPS_INS_DMFC0 = 513; + public static final int MIPS_INS_DMFC1 = 514; + public static final int MIPS_INS_DMFC2 = 515; + public static final int MIPS_INS_DMFGC0 = 516; + public static final int MIPS_INS_DMOD = 517; + public static final int MIPS_INS_DMODU = 518; + public static final int MIPS_INS_DMT = 519; + public static final int MIPS_INS_DMTC0 = 520; + public static final int MIPS_INS_DMTC1 = 521; + public static final int MIPS_INS_DMTC2 = 522; + public static final int MIPS_INS_DMTGC0 = 523; + public static final int MIPS_INS_DMUH = 524; + public static final int MIPS_INS_DMUHU = 525; + public static final int MIPS_INS_DMULT = 526; + public static final int MIPS_INS_DMULTU = 527; + public static final int MIPS_INS_DMULU = 528; + public static final int MIPS_INS_DOTP_S_D = 529; + public static final int MIPS_INS_DOTP_S_H = 530; + public static final int MIPS_INS_DOTP_S_W = 531; + public static final int MIPS_INS_DOTP_U_D = 532; + public static final int MIPS_INS_DOTP_U_H = 533; + public static final int MIPS_INS_DOTP_U_W = 534; + public static final int MIPS_INS_DPADD_S_D = 535; + public static final int MIPS_INS_DPADD_S_H = 536; + public static final int MIPS_INS_DPADD_S_W = 537; + public static final int MIPS_INS_DPADD_U_D = 538; + public static final int MIPS_INS_DPADD_U_H = 539; + public static final int MIPS_INS_DPADD_U_W = 540; + public static final int MIPS_INS_DPAQX_SA_W_PH = 541; + public static final int MIPS_INS_DPAQX_S_W_PH = 542; + public static final int MIPS_INS_DPAQ_SA_L_W = 543; + public static final int MIPS_INS_DPAQ_S_W_PH = 544; + public static final int MIPS_INS_DPAU_H_QBL = 545; + public static final int MIPS_INS_DPAU_H_QBR = 546; + public static final int MIPS_INS_DPAX_W_PH = 547; + public static final int MIPS_INS_DPA_W_PH = 548; + public static final int MIPS_INS_DPOP = 549; + public static final int MIPS_INS_DPSQX_SA_W_PH = 550; + public static final int MIPS_INS_DPSQX_S_W_PH = 551; + public static final int MIPS_INS_DPSQ_SA_L_W = 552; + public static final int MIPS_INS_DPSQ_S_W_PH = 553; + public static final int MIPS_INS_DPSUB_S_D = 554; + public static final int MIPS_INS_DPSUB_S_H = 555; + public static final int MIPS_INS_DPSUB_S_W = 556; + public static final int MIPS_INS_DPSUB_U_D = 557; + public static final int MIPS_INS_DPSUB_U_H = 558; + public static final int MIPS_INS_DPSUB_U_W = 559; + public static final int MIPS_INS_DPSU_H_QBL = 560; + public static final int MIPS_INS_DPSU_H_QBR = 561; + public static final int MIPS_INS_DPSX_W_PH = 562; + public static final int MIPS_INS_DPS_W_PH = 563; + public static final int MIPS_INS_DROTR = 564; + public static final int MIPS_INS_DROTR32 = 565; + public static final int MIPS_INS_DROTRV = 566; + public static final int MIPS_INS_DSBH = 567; + public static final int MIPS_INS_DSHD = 568; + public static final int MIPS_INS_DSLL = 569; + public static final int MIPS_INS_DSLL32 = 570; + public static final int MIPS_INS_DSLLV = 571; + public static final int MIPS_INS_DSRA = 572; + public static final int MIPS_INS_DSRA32 = 573; + public static final int MIPS_INS_DSRAV = 574; + public static final int MIPS_INS_DSRL = 575; + public static final int MIPS_INS_DSRL32 = 576; + public static final int MIPS_INS_DSRLV = 577; + public static final int MIPS_INS_DSUB = 578; + public static final int MIPS_INS_DSUBU = 579; + public static final int MIPS_INS_DVP = 580; + public static final int MIPS_INS_DVPE = 581; + public static final int MIPS_INS_EHB = 582; + public static final int MIPS_INS_EI = 583; + public static final int MIPS_INS_EMT = 584; + public static final int MIPS_INS_ERET = 585; + public static final int MIPS_INS_ERETNC = 586; + public static final int MIPS_INS_EVP = 587; + public static final int MIPS_INS_EVPE = 588; + public static final int MIPS_INS_EXT = 589; + public static final int MIPS_INS_EXTP = 590; + public static final int MIPS_INS_EXTPDP = 591; + public static final int MIPS_INS_EXTPDPV = 592; + public static final int MIPS_INS_EXTPV = 593; + public static final int MIPS_INS_EXTRV_RS_W = 594; + public static final int MIPS_INS_EXTRV_R_W = 595; + public static final int MIPS_INS_EXTRV_S_H = 596; + public static final int MIPS_INS_EXTRV_W = 597; + public static final int MIPS_INS_EXTR_RS_W = 598; + public static final int MIPS_INS_EXTR_R_W = 599; + public static final int MIPS_INS_EXTR_S_H = 600; + public static final int MIPS_INS_EXTR_W = 601; + public static final int MIPS_INS_EXTS = 602; + public static final int MIPS_INS_EXTS32 = 603; + public static final int MIPS_INS_EXTW = 604; + public static final int MIPS_INS_ABS_D = 605; + public static final int MIPS_INS_ABS_S = 606; + public static final int MIPS_INS_FADD_D = 607; + public static final int MIPS_INS_ADD_D = 608; + public static final int MIPS_INS_ADD_PS = 609; + public static final int MIPS_INS_ADD_S = 610; + public static final int MIPS_INS_FADD_W = 611; + public static final int MIPS_INS_FCAF_D = 612; + public static final int MIPS_INS_FCAF_W = 613; + public static final int MIPS_INS_FCEQ_D = 614; + public static final int MIPS_INS_FCEQ_W = 615; + public static final int MIPS_INS_FCLASS_D = 616; + public static final int MIPS_INS_FCLASS_W = 617; + public static final int MIPS_INS_FCLE_D = 618; + public static final int MIPS_INS_FCLE_W = 619; + public static final int MIPS_INS_FCLT_D = 620; + public static final int MIPS_INS_FCLT_W = 621; + public static final int MIPS_INS_FCNE_D = 622; + public static final int MIPS_INS_FCNE_W = 623; + public static final int MIPS_INS_FCOR_D = 624; + public static final int MIPS_INS_FCOR_W = 625; + public static final int MIPS_INS_FCUEQ_D = 626; + public static final int MIPS_INS_FCUEQ_W = 627; + public static final int MIPS_INS_FCULE_D = 628; + public static final int MIPS_INS_FCULE_W = 629; + public static final int MIPS_INS_FCULT_D = 630; + public static final int MIPS_INS_FCULT_W = 631; + public static final int MIPS_INS_FCUNE_D = 632; + public static final int MIPS_INS_FCUNE_W = 633; + public static final int MIPS_INS_FCUN_D = 634; + public static final int MIPS_INS_FCUN_W = 635; + public static final int MIPS_INS_FDIV_D = 636; + public static final int MIPS_INS_DIV_D = 637; + public static final int MIPS_INS_DIV_S = 638; + public static final int MIPS_INS_FDIV_W = 639; + public static final int MIPS_INS_FEXDO_H = 640; + public static final int MIPS_INS_FEXDO_W = 641; + public static final int MIPS_INS_FEXP2_D = 642; + public static final int MIPS_INS_FEXP2_W = 643; + public static final int MIPS_INS_FEXUPL_D = 644; + public static final int MIPS_INS_FEXUPL_W = 645; + public static final int MIPS_INS_FEXUPR_D = 646; + public static final int MIPS_INS_FEXUPR_W = 647; + public static final int MIPS_INS_FFINT_S_D = 648; + public static final int MIPS_INS_FFINT_S_W = 649; + public static final int MIPS_INS_FFINT_U_D = 650; + public static final int MIPS_INS_FFINT_U_W = 651; + public static final int MIPS_INS_FFQL_D = 652; + public static final int MIPS_INS_FFQL_W = 653; + public static final int MIPS_INS_FFQR_D = 654; + public static final int MIPS_INS_FFQR_W = 655; + public static final int MIPS_INS_FILL_B = 656; + public static final int MIPS_INS_FILL_D = 657; + public static final int MIPS_INS_FILL_H = 658; + public static final int MIPS_INS_FILL_W = 659; + public static final int MIPS_INS_FLOG2_D = 660; + public static final int MIPS_INS_FLOG2_W = 661; + public static final int MIPS_INS_FLOOR_L_D = 662; + public static final int MIPS_INS_FLOOR_L_S = 663; + public static final int MIPS_INS_FLOOR_W_D = 664; + public static final int MIPS_INS_FLOOR_W_S = 665; + public static final int MIPS_INS_FMADD_D = 666; + public static final int MIPS_INS_FMADD_W = 667; + public static final int MIPS_INS_FMAX_A_D = 668; + public static final int MIPS_INS_FMAX_A_W = 669; + public static final int MIPS_INS_FMAX_D = 670; + public static final int MIPS_INS_FMAX_W = 671; + public static final int MIPS_INS_FMIN_A_D = 672; + public static final int MIPS_INS_FMIN_A_W = 673; + public static final int MIPS_INS_FMIN_D = 674; + public static final int MIPS_INS_FMIN_W = 675; + public static final int MIPS_INS_MOV_D = 676; + public static final int MIPS_INS_MOV_S = 677; + public static final int MIPS_INS_FMSUB_D = 678; + public static final int MIPS_INS_FMSUB_W = 679; + public static final int MIPS_INS_FMUL_D = 680; + public static final int MIPS_INS_MUL_D = 681; + public static final int MIPS_INS_MUL_PS = 682; + public static final int MIPS_INS_MUL_S = 683; + public static final int MIPS_INS_FMUL_W = 684; + public static final int MIPS_INS_NEG_D = 685; + public static final int MIPS_INS_NEG_S = 686; + public static final int MIPS_INS_FORK = 687; + public static final int MIPS_INS_FRCP_D = 688; + public static final int MIPS_INS_FRCP_W = 689; + public static final int MIPS_INS_FRINT_D = 690; + public static final int MIPS_INS_FRINT_W = 691; + public static final int MIPS_INS_FRSQRT_D = 692; + public static final int MIPS_INS_FRSQRT_W = 693; + public static final int MIPS_INS_FSAF_D = 694; + public static final int MIPS_INS_FSAF_W = 695; + public static final int MIPS_INS_FSEQ_D = 696; + public static final int MIPS_INS_FSEQ_W = 697; + public static final int MIPS_INS_FSLE_D = 698; + public static final int MIPS_INS_FSLE_W = 699; + public static final int MIPS_INS_FSLT_D = 700; + public static final int MIPS_INS_FSLT_W = 701; + public static final int MIPS_INS_FSNE_D = 702; + public static final int MIPS_INS_FSNE_W = 703; + public static final int MIPS_INS_FSOR_D = 704; + public static final int MIPS_INS_FSOR_W = 705; + public static final int MIPS_INS_FSQRT_D = 706; + public static final int MIPS_INS_SQRT_D = 707; + public static final int MIPS_INS_SQRT_S = 708; + public static final int MIPS_INS_FSQRT_W = 709; + public static final int MIPS_INS_FSUB_D = 710; + public static final int MIPS_INS_SUB_D = 711; + public static final int MIPS_INS_SUB_PS = 712; + public static final int MIPS_INS_SUB_S = 713; + public static final int MIPS_INS_FSUB_W = 714; + public static final int MIPS_INS_FSUEQ_D = 715; + public static final int MIPS_INS_FSUEQ_W = 716; + public static final int MIPS_INS_FSULE_D = 717; + public static final int MIPS_INS_FSULE_W = 718; + public static final int MIPS_INS_FSULT_D = 719; + public static final int MIPS_INS_FSULT_W = 720; + public static final int MIPS_INS_FSUNE_D = 721; + public static final int MIPS_INS_FSUNE_W = 722; + public static final int MIPS_INS_FSUN_D = 723; + public static final int MIPS_INS_FSUN_W = 724; + public static final int MIPS_INS_FTINT_S_D = 725; + public static final int MIPS_INS_FTINT_S_W = 726; + public static final int MIPS_INS_FTINT_U_D = 727; + public static final int MIPS_INS_FTINT_U_W = 728; + public static final int MIPS_INS_FTQ_H = 729; + public static final int MIPS_INS_FTQ_W = 730; + public static final int MIPS_INS_FTRUNC_S_D = 731; + public static final int MIPS_INS_FTRUNC_S_W = 732; + public static final int MIPS_INS_FTRUNC_U_D = 733; + public static final int MIPS_INS_FTRUNC_U_W = 734; + public static final int MIPS_INS_GINVI = 735; + public static final int MIPS_INS_GINVT = 736; + public static final int MIPS_INS_HADD_S_D = 737; + public static final int MIPS_INS_HADD_S_H = 738; + public static final int MIPS_INS_HADD_S_W = 739; + public static final int MIPS_INS_HADD_U_D = 740; + public static final int MIPS_INS_HADD_U_H = 741; + public static final int MIPS_INS_HADD_U_W = 742; + public static final int MIPS_INS_HSUB_S_D = 743; + public static final int MIPS_INS_HSUB_S_H = 744; + public static final int MIPS_INS_HSUB_S_W = 745; + public static final int MIPS_INS_HSUB_U_D = 746; + public static final int MIPS_INS_HSUB_U_H = 747; + public static final int MIPS_INS_HSUB_U_W = 748; + public static final int MIPS_INS_HYPCALL = 749; + public static final int MIPS_INS_ILVEV_B = 750; + public static final int MIPS_INS_ILVEV_D = 751; + public static final int MIPS_INS_ILVEV_H = 752; + public static final int MIPS_INS_ILVEV_W = 753; + public static final int MIPS_INS_ILVL_B = 754; + public static final int MIPS_INS_ILVL_D = 755; + public static final int MIPS_INS_ILVL_H = 756; + public static final int MIPS_INS_ILVL_W = 757; + public static final int MIPS_INS_ILVOD_B = 758; + public static final int MIPS_INS_ILVOD_D = 759; + public static final int MIPS_INS_ILVOD_H = 760; + public static final int MIPS_INS_ILVOD_W = 761; + public static final int MIPS_INS_ILVR_B = 762; + public static final int MIPS_INS_ILVR_D = 763; + public static final int MIPS_INS_ILVR_H = 764; + public static final int MIPS_INS_ILVR_W = 765; + public static final int MIPS_INS_INS = 766; + public static final int MIPS_INS_INSERT_B = 767; + public static final int MIPS_INS_INSERT_D = 768; + public static final int MIPS_INS_INSERT_H = 769; + public static final int MIPS_INS_INSERT_W = 770; + public static final int MIPS_INS_INSV = 771; + public static final int MIPS_INS_INSVE_B = 772; + public static final int MIPS_INS_INSVE_D = 773; + public static final int MIPS_INS_INSVE_H = 774; + public static final int MIPS_INS_INSVE_W = 775; + public static final int MIPS_INS_J = 776; + public static final int MIPS_INS_JALR = 777; + public static final int MIPS_INS_JALRC = 778; + public static final int MIPS_INS_JALRC_HB = 779; + public static final int MIPS_INS_JALRS16 = 780; + public static final int MIPS_INS_JALRS = 781; + public static final int MIPS_INS_JALR_HB = 782; + public static final int MIPS_INS_JALS = 783; + public static final int MIPS_INS_JALX = 784; + public static final int MIPS_INS_JIALC = 785; + public static final int MIPS_INS_JIC = 786; + public static final int MIPS_INS_JR = 787; + public static final int MIPS_INS_JR16 = 788; + public static final int MIPS_INS_JRADDIUSP = 789; + public static final int MIPS_INS_JRC = 790; + public static final int MIPS_INS_JRC16 = 791; + public static final int MIPS_INS_JRCADDIUSP = 792; + public static final int MIPS_INS_JR_HB = 793; + public static final int MIPS_INS_LAPC_H = 794; + public static final int MIPS_INS_LAPC_B = 795; + public static final int MIPS_INS_LB = 796; + public static final int MIPS_INS_LBE = 797; + public static final int MIPS_INS_LBU16 = 798; + public static final int MIPS_INS_LBU = 799; + public static final int MIPS_INS_LBUX = 800; + public static final int MIPS_INS_LBX = 801; + public static final int MIPS_INS_LBUE = 802; + public static final int MIPS_INS_LDC1 = 803; + public static final int MIPS_INS_LDC2 = 804; + public static final int MIPS_INS_LDC3 = 805; + public static final int MIPS_INS_LDI_B = 806; + public static final int MIPS_INS_LDI_D = 807; + public static final int MIPS_INS_LDI_H = 808; + public static final int MIPS_INS_LDI_W = 809; + public static final int MIPS_INS_LDL = 810; + public static final int MIPS_INS_LDPC = 811; + public static final int MIPS_INS_LDR = 812; + public static final int MIPS_INS_LDXC1 = 813; + public static final int MIPS_INS_LD_B = 814; + public static final int MIPS_INS_LD_D = 815; + public static final int MIPS_INS_LD_H = 816; + public static final int MIPS_INS_LD_W = 817; + public static final int MIPS_INS_LH = 818; + public static final int MIPS_INS_LHE = 819; + public static final int MIPS_INS_LHU16 = 820; + public static final int MIPS_INS_LHU = 821; + public static final int MIPS_INS_LHUXS = 822; + public static final int MIPS_INS_LHUX = 823; + public static final int MIPS_INS_LHX = 824; + public static final int MIPS_INS_LHXS = 825; + public static final int MIPS_INS_LHUE = 826; + public static final int MIPS_INS_LI16 = 827; + public static final int MIPS_INS_LL = 828; + public static final int MIPS_INS_LLD = 829; + public static final int MIPS_INS_LLE = 830; + public static final int MIPS_INS_LLWP = 831; + public static final int MIPS_INS_LSA = 832; + public static final int MIPS_INS_LUI = 833; + public static final int MIPS_INS_LUXC1 = 834; + public static final int MIPS_INS_LW = 835; + public static final int MIPS_INS_LW16 = 836; + public static final int MIPS_INS_LWC1 = 837; + public static final int MIPS_INS_LWC2 = 838; + public static final int MIPS_INS_LWC3 = 839; + public static final int MIPS_INS_LWE = 840; + public static final int MIPS_INS_LWL = 841; + public static final int MIPS_INS_LWLE = 842; + public static final int MIPS_INS_LWM16 = 843; + public static final int MIPS_INS_LWM32 = 844; + public static final int MIPS_INS_LWPC = 845; + public static final int MIPS_INS_LWP = 846; + public static final int MIPS_INS_LWR = 847; + public static final int MIPS_INS_LWRE = 848; + public static final int MIPS_INS_LWUPC = 849; + public static final int MIPS_INS_LWU = 850; + public static final int MIPS_INS_LWX = 851; + public static final int MIPS_INS_LWXC1 = 852; + public static final int MIPS_INS_LWXS = 853; + public static final int MIPS_INS_MADD = 854; + public static final int MIPS_INS_MADDF_D = 855; + public static final int MIPS_INS_MADDF_S = 856; + public static final int MIPS_INS_MADDR_Q_H = 857; + public static final int MIPS_INS_MADDR_Q_W = 858; + public static final int MIPS_INS_MADDU = 859; + public static final int MIPS_INS_MADDV_B = 860; + public static final int MIPS_INS_MADDV_D = 861; + public static final int MIPS_INS_MADDV_H = 862; + public static final int MIPS_INS_MADDV_W = 863; + public static final int MIPS_INS_MADD_D = 864; + public static final int MIPS_INS_MADD_Q_H = 865; + public static final int MIPS_INS_MADD_Q_W = 866; + public static final int MIPS_INS_MADD_S = 867; + public static final int MIPS_INS_MAQ_SA_W_PHL = 868; + public static final int MIPS_INS_MAQ_SA_W_PHR = 869; + public static final int MIPS_INS_MAQ_S_W_PHL = 870; + public static final int MIPS_INS_MAQ_S_W_PHR = 871; + public static final int MIPS_INS_MAXA_D = 872; + public static final int MIPS_INS_MAXA_S = 873; + public static final int MIPS_INS_MAXI_S_B = 874; + public static final int MIPS_INS_MAXI_S_D = 875; + public static final int MIPS_INS_MAXI_S_H = 876; + public static final int MIPS_INS_MAXI_S_W = 877; + public static final int MIPS_INS_MAXI_U_B = 878; + public static final int MIPS_INS_MAXI_U_D = 879; + public static final int MIPS_INS_MAXI_U_H = 880; + public static final int MIPS_INS_MAXI_U_W = 881; + public static final int MIPS_INS_MAX_A_B = 882; + public static final int MIPS_INS_MAX_A_D = 883; + public static final int MIPS_INS_MAX_A_H = 884; + public static final int MIPS_INS_MAX_A_W = 885; + public static final int MIPS_INS_MAX_D = 886; + public static final int MIPS_INS_MAX_S = 887; + public static final int MIPS_INS_MAX_S_B = 888; + public static final int MIPS_INS_MAX_S_D = 889; + public static final int MIPS_INS_MAX_S_H = 890; + public static final int MIPS_INS_MAX_S_W = 891; + public static final int MIPS_INS_MAX_U_B = 892; + public static final int MIPS_INS_MAX_U_D = 893; + public static final int MIPS_INS_MAX_U_H = 894; + public static final int MIPS_INS_MAX_U_W = 895; + public static final int MIPS_INS_MFC0 = 896; + public static final int MIPS_INS_MFC1 = 897; + public static final int MIPS_INS_MFC2 = 898; + public static final int MIPS_INS_MFGC0 = 899; + public static final int MIPS_INS_MFHC0 = 900; + public static final int MIPS_INS_MFHC1 = 901; + public static final int MIPS_INS_MFHC2 = 902; + public static final int MIPS_INS_MFHGC0 = 903; + public static final int MIPS_INS_MFHI = 904; + public static final int MIPS_INS_MFHI16 = 905; + public static final int MIPS_INS_MFLO = 906; + public static final int MIPS_INS_MFLO16 = 907; + public static final int MIPS_INS_MFTR = 908; + public static final int MIPS_INS_MINA_D = 909; + public static final int MIPS_INS_MINA_S = 910; + public static final int MIPS_INS_MINI_S_B = 911; + public static final int MIPS_INS_MINI_S_D = 912; + public static final int MIPS_INS_MINI_S_H = 913; + public static final int MIPS_INS_MINI_S_W = 914; + public static final int MIPS_INS_MINI_U_B = 915; + public static final int MIPS_INS_MINI_U_D = 916; + public static final int MIPS_INS_MINI_U_H = 917; + public static final int MIPS_INS_MINI_U_W = 918; + public static final int MIPS_INS_MIN_A_B = 919; + public static final int MIPS_INS_MIN_A_D = 920; + public static final int MIPS_INS_MIN_A_H = 921; + public static final int MIPS_INS_MIN_A_W = 922; + public static final int MIPS_INS_MIN_D = 923; + public static final int MIPS_INS_MIN_S = 924; + public static final int MIPS_INS_MIN_S_B = 925; + public static final int MIPS_INS_MIN_S_D = 926; + public static final int MIPS_INS_MIN_S_H = 927; + public static final int MIPS_INS_MIN_S_W = 928; + public static final int MIPS_INS_MIN_U_B = 929; + public static final int MIPS_INS_MIN_U_D = 930; + public static final int MIPS_INS_MIN_U_H = 931; + public static final int MIPS_INS_MIN_U_W = 932; + public static final int MIPS_INS_MOD = 933; + public static final int MIPS_INS_MODSUB = 934; + public static final int MIPS_INS_MODU = 935; + public static final int MIPS_INS_MOD_S_B = 936; + public static final int MIPS_INS_MOD_S_D = 937; + public static final int MIPS_INS_MOD_S_H = 938; + public static final int MIPS_INS_MOD_S_W = 939; + public static final int MIPS_INS_MOD_U_B = 940; + public static final int MIPS_INS_MOD_U_D = 941; + public static final int MIPS_INS_MOD_U_H = 942; + public static final int MIPS_INS_MOD_U_W = 943; + public static final int MIPS_INS_MOVE = 944; + public static final int MIPS_INS_MOVE16 = 945; + public static final int MIPS_INS_MOVE_BALC = 946; + public static final int MIPS_INS_MOVEP = 947; + public static final int MIPS_INS_MOVE_V = 948; + public static final int MIPS_INS_MOVF_D = 949; + public static final int MIPS_INS_MOVF = 950; + public static final int MIPS_INS_MOVF_S = 951; + public static final int MIPS_INS_MOVN_D = 952; + public static final int MIPS_INS_MOVN = 953; + public static final int MIPS_INS_MOVN_S = 954; + public static final int MIPS_INS_MOVT_D = 955; + public static final int MIPS_INS_MOVT = 956; + public static final int MIPS_INS_MOVT_S = 957; + public static final int MIPS_INS_MOVZ_D = 958; + public static final int MIPS_INS_MOVZ = 959; + public static final int MIPS_INS_MOVZ_S = 960; + public static final int MIPS_INS_MSUB = 961; + public static final int MIPS_INS_MSUBF_D = 962; + public static final int MIPS_INS_MSUBF_S = 963; + public static final int MIPS_INS_MSUBR_Q_H = 964; + public static final int MIPS_INS_MSUBR_Q_W = 965; + public static final int MIPS_INS_MSUBU = 966; + public static final int MIPS_INS_MSUBV_B = 967; + public static final int MIPS_INS_MSUBV_D = 968; + public static final int MIPS_INS_MSUBV_H = 969; + public static final int MIPS_INS_MSUBV_W = 970; + public static final int MIPS_INS_MSUB_D = 971; + public static final int MIPS_INS_MSUB_Q_H = 972; + public static final int MIPS_INS_MSUB_Q_W = 973; + public static final int MIPS_INS_MSUB_S = 974; + public static final int MIPS_INS_MTC0 = 975; + public static final int MIPS_INS_MTC1 = 976; + public static final int MIPS_INS_MTC2 = 977; + public static final int MIPS_INS_MTGC0 = 978; + public static final int MIPS_INS_MTHC0 = 979; + public static final int MIPS_INS_MTHC1 = 980; + public static final int MIPS_INS_MTHC2 = 981; + public static final int MIPS_INS_MTHGC0 = 982; + public static final int MIPS_INS_MTHI = 983; + public static final int MIPS_INS_MTHLIP = 984; + public static final int MIPS_INS_MTLO = 985; + public static final int MIPS_INS_MTM0 = 986; + public static final int MIPS_INS_MTM1 = 987; + public static final int MIPS_INS_MTM2 = 988; + public static final int MIPS_INS_MTP0 = 989; + public static final int MIPS_INS_MTP1 = 990; + public static final int MIPS_INS_MTP2 = 991; + public static final int MIPS_INS_MTTR = 992; + public static final int MIPS_INS_MUH = 993; + public static final int MIPS_INS_MUHU = 994; + public static final int MIPS_INS_MULEQ_S_W_PHL = 995; + public static final int MIPS_INS_MULEQ_S_W_PHR = 996; + public static final int MIPS_INS_MULEU_S_PH_QBL = 997; + public static final int MIPS_INS_MULEU_S_PH_QBR = 998; + public static final int MIPS_INS_MULQ_RS_PH = 999; + public static final int MIPS_INS_MULQ_RS_W = 1000; + public static final int MIPS_INS_MULQ_S_PH = 1001; + public static final int MIPS_INS_MULQ_S_W = 1002; + public static final int MIPS_INS_MULR_PS = 1003; + public static final int MIPS_INS_MULR_Q_H = 1004; + public static final int MIPS_INS_MULR_Q_W = 1005; + public static final int MIPS_INS_MULSAQ_S_W_PH = 1006; + public static final int MIPS_INS_MULSA_W_PH = 1007; + public static final int MIPS_INS_MULT = 1008; + public static final int MIPS_INS_MULTU = 1009; + public static final int MIPS_INS_MULU = 1010; + public static final int MIPS_INS_MULV_B = 1011; + public static final int MIPS_INS_MULV_D = 1012; + public static final int MIPS_INS_MULV_H = 1013; + public static final int MIPS_INS_MULV_W = 1014; + public static final int MIPS_INS_MUL_PH = 1015; + public static final int MIPS_INS_MUL_Q_H = 1016; + public static final int MIPS_INS_MUL_Q_W = 1017; + public static final int MIPS_INS_MUL_S_PH = 1018; + public static final int MIPS_INS_NLOC_B = 1019; + public static final int MIPS_INS_NLOC_D = 1020; + public static final int MIPS_INS_NLOC_H = 1021; + public static final int MIPS_INS_NLOC_W = 1022; + public static final int MIPS_INS_NLZC_B = 1023; + public static final int MIPS_INS_NLZC_D = 1024; + public static final int MIPS_INS_NLZC_H = 1025; + public static final int MIPS_INS_NLZC_W = 1026; + public static final int MIPS_INS_NMADD_D = 1027; + public static final int MIPS_INS_NMADD_S = 1028; + public static final int MIPS_INS_NMSUB_D = 1029; + public static final int MIPS_INS_NMSUB_S = 1030; + public static final int MIPS_INS_NOP32 = 1031; + public static final int MIPS_INS_NOP = 1032; + public static final int MIPS_INS_NORI_B = 1033; + public static final int MIPS_INS_NOR_V = 1034; + public static final int MIPS_INS_NOT16 = 1035; + public static final int MIPS_INS_NOT = 1036; + public static final int MIPS_INS_NEG = 1037; + public static final int MIPS_INS_OR = 1038; + public static final int MIPS_INS_OR16 = 1039; + public static final int MIPS_INS_ORI_B = 1040; + public static final int MIPS_INS_ORI = 1041; + public static final int MIPS_INS_OR_V = 1042; + public static final int MIPS_INS_PACKRL_PH = 1043; + public static final int MIPS_INS_PAUSE = 1044; + public static final int MIPS_INS_PCKEV_B = 1045; + public static final int MIPS_INS_PCKEV_D = 1046; + public static final int MIPS_INS_PCKEV_H = 1047; + public static final int MIPS_INS_PCKEV_W = 1048; + public static final int MIPS_INS_PCKOD_B = 1049; + public static final int MIPS_INS_PCKOD_D = 1050; + public static final int MIPS_INS_PCKOD_H = 1051; + public static final int MIPS_INS_PCKOD_W = 1052; + public static final int MIPS_INS_PCNT_B = 1053; + public static final int MIPS_INS_PCNT_D = 1054; + public static final int MIPS_INS_PCNT_H = 1055; + public static final int MIPS_INS_PCNT_W = 1056; + public static final int MIPS_INS_PICK_PH = 1057; + public static final int MIPS_INS_PICK_QB = 1058; + public static final int MIPS_INS_PLL_PS = 1059; + public static final int MIPS_INS_PLU_PS = 1060; + public static final int MIPS_INS_POP = 1061; + public static final int MIPS_INS_PRECEQU_PH_QBL = 1062; + public static final int MIPS_INS_PRECEQU_PH_QBLA = 1063; + public static final int MIPS_INS_PRECEQU_PH_QBR = 1064; + public static final int MIPS_INS_PRECEQU_PH_QBRA = 1065; + public static final int MIPS_INS_PRECEQ_W_PHL = 1066; + public static final int MIPS_INS_PRECEQ_W_PHR = 1067; + public static final int MIPS_INS_PRECEU_PH_QBL = 1068; + public static final int MIPS_INS_PRECEU_PH_QBLA = 1069; + public static final int MIPS_INS_PRECEU_PH_QBR = 1070; + public static final int MIPS_INS_PRECEU_PH_QBRA = 1071; + public static final int MIPS_INS_PRECRQU_S_QB_PH = 1072; + public static final int MIPS_INS_PRECRQ_PH_W = 1073; + public static final int MIPS_INS_PRECRQ_QB_PH = 1074; + public static final int MIPS_INS_PRECRQ_RS_PH_W = 1075; + public static final int MIPS_INS_PRECR_QB_PH = 1076; + public static final int MIPS_INS_PRECR_SRA_PH_W = 1077; + public static final int MIPS_INS_PRECR_SRA_R_PH_W = 1078; + public static final int MIPS_INS_PREF = 1079; + public static final int MIPS_INS_PREFE = 1080; + public static final int MIPS_INS_PREFX = 1081; + public static final int MIPS_INS_PREPEND = 1082; + public static final int MIPS_INS_PUL_PS = 1083; + public static final int MIPS_INS_PUU_PS = 1084; + public static final int MIPS_INS_RADDU_W_QB = 1085; + public static final int MIPS_INS_RDDSP = 1086; + public static final int MIPS_INS_RDHWR = 1087; + public static final int MIPS_INS_RDPGPR = 1088; + public static final int MIPS_INS_RECIP_D = 1089; + public static final int MIPS_INS_RECIP_S = 1090; + public static final int MIPS_INS_REPLV_PH = 1091; + public static final int MIPS_INS_REPLV_QB = 1092; + public static final int MIPS_INS_REPL_PH = 1093; + public static final int MIPS_INS_REPL_QB = 1094; + public static final int MIPS_INS_RESTORE_JRC = 1095; + public static final int MIPS_INS_RESTORE = 1096; + public static final int MIPS_INS_RINT_D = 1097; + public static final int MIPS_INS_RINT_S = 1098; + public static final int MIPS_INS_ROTR = 1099; + public static final int MIPS_INS_ROTRV = 1100; + public static final int MIPS_INS_ROTX = 1101; + public static final int MIPS_INS_ROUND_L_D = 1102; + public static final int MIPS_INS_ROUND_L_S = 1103; + public static final int MIPS_INS_ROUND_W_D = 1104; + public static final int MIPS_INS_ROUND_W_S = 1105; + public static final int MIPS_INS_RSQRT_D = 1106; + public static final int MIPS_INS_RSQRT_S = 1107; + public static final int MIPS_INS_SAT_S_B = 1108; + public static final int MIPS_INS_SAT_S_D = 1109; + public static final int MIPS_INS_SAT_S_H = 1110; + public static final int MIPS_INS_SAT_S_W = 1111; + public static final int MIPS_INS_SAT_U_B = 1112; + public static final int MIPS_INS_SAT_U_D = 1113; + public static final int MIPS_INS_SAT_U_H = 1114; + public static final int MIPS_INS_SAT_U_W = 1115; + public static final int MIPS_INS_SAVE = 1116; + public static final int MIPS_INS_SB = 1117; + public static final int MIPS_INS_SB16 = 1118; + public static final int MIPS_INS_SBE = 1119; + public static final int MIPS_INS_SBX = 1120; + public static final int MIPS_INS_SC = 1121; + public static final int MIPS_INS_SCD = 1122; + public static final int MIPS_INS_SCE = 1123; + public static final int MIPS_INS_SCWP = 1124; + public static final int MIPS_INS_SDBBP = 1125; + public static final int MIPS_INS_SDBBP16 = 1126; + public static final int MIPS_INS_SDC1 = 1127; + public static final int MIPS_INS_SDC2 = 1128; + public static final int MIPS_INS_SDC3 = 1129; + public static final int MIPS_INS_SDL = 1130; + public static final int MIPS_INS_SDR = 1131; + public static final int MIPS_INS_SDXC1 = 1132; + public static final int MIPS_INS_SEB = 1133; + public static final int MIPS_INS_SEH = 1134; + public static final int MIPS_INS_SELEQZ = 1135; + public static final int MIPS_INS_SELEQZ_D = 1136; + public static final int MIPS_INS_SELEQZ_S = 1137; + public static final int MIPS_INS_SELNEZ = 1138; + public static final int MIPS_INS_SELNEZ_D = 1139; + public static final int MIPS_INS_SELNEZ_S = 1140; + public static final int MIPS_INS_SEL_D = 1141; + public static final int MIPS_INS_SEL_S = 1142; + public static final int MIPS_INS_SEQI = 1143; + public static final int MIPS_INS_SH = 1144; + public static final int MIPS_INS_SH16 = 1145; + public static final int MIPS_INS_SHE = 1146; + public static final int MIPS_INS_SHF_B = 1147; + public static final int MIPS_INS_SHF_H = 1148; + public static final int MIPS_INS_SHF_W = 1149; + public static final int MIPS_INS_SHILO = 1150; + public static final int MIPS_INS_SHILOV = 1151; + public static final int MIPS_INS_SHLLV_PH = 1152; + public static final int MIPS_INS_SHLLV_QB = 1153; + public static final int MIPS_INS_SHLLV_S_PH = 1154; + public static final int MIPS_INS_SHLLV_S_W = 1155; + public static final int MIPS_INS_SHLL_PH = 1156; + public static final int MIPS_INS_SHLL_QB = 1157; + public static final int MIPS_INS_SHLL_S_PH = 1158; + public static final int MIPS_INS_SHLL_S_W = 1159; + public static final int MIPS_INS_SHRAV_PH = 1160; + public static final int MIPS_INS_SHRAV_QB = 1161; + public static final int MIPS_INS_SHRAV_R_PH = 1162; + public static final int MIPS_INS_SHRAV_R_QB = 1163; + public static final int MIPS_INS_SHRAV_R_W = 1164; + public static final int MIPS_INS_SHRA_PH = 1165; + public static final int MIPS_INS_SHRA_QB = 1166; + public static final int MIPS_INS_SHRA_R_PH = 1167; + public static final int MIPS_INS_SHRA_R_QB = 1168; + public static final int MIPS_INS_SHRA_R_W = 1169; + public static final int MIPS_INS_SHRLV_PH = 1170; + public static final int MIPS_INS_SHRLV_QB = 1171; + public static final int MIPS_INS_SHRL_PH = 1172; + public static final int MIPS_INS_SHRL_QB = 1173; + public static final int MIPS_INS_SHXS = 1174; + public static final int MIPS_INS_SHX = 1175; + public static final int MIPS_INS_SIGRIE = 1176; + public static final int MIPS_INS_SLDI_B = 1177; + public static final int MIPS_INS_SLDI_D = 1178; + public static final int MIPS_INS_SLDI_H = 1179; + public static final int MIPS_INS_SLDI_W = 1180; + public static final int MIPS_INS_SLD_B = 1181; + public static final int MIPS_INS_SLD_D = 1182; + public static final int MIPS_INS_SLD_H = 1183; + public static final int MIPS_INS_SLD_W = 1184; + public static final int MIPS_INS_SLL = 1185; + public static final int MIPS_INS_SLL16 = 1186; + public static final int MIPS_INS_SLLI_B = 1187; + public static final int MIPS_INS_SLLI_D = 1188; + public static final int MIPS_INS_SLLI_H = 1189; + public static final int MIPS_INS_SLLI_W = 1190; + public static final int MIPS_INS_SLLV = 1191; + public static final int MIPS_INS_SLL_B = 1192; + public static final int MIPS_INS_SLL_D = 1193; + public static final int MIPS_INS_SLL_H = 1194; + public static final int MIPS_INS_SLL_W = 1195; + public static final int MIPS_INS_SLTIU = 1196; + public static final int MIPS_INS_SLTI = 1197; + public static final int MIPS_INS_SNEI = 1198; + public static final int MIPS_INS_SOV = 1199; + public static final int MIPS_INS_SPLATI_B = 1200; + public static final int MIPS_INS_SPLATI_D = 1201; + public static final int MIPS_INS_SPLATI_H = 1202; + public static final int MIPS_INS_SPLATI_W = 1203; + public static final int MIPS_INS_SPLAT_B = 1204; + public static final int MIPS_INS_SPLAT_D = 1205; + public static final int MIPS_INS_SPLAT_H = 1206; + public static final int MIPS_INS_SPLAT_W = 1207; + public static final int MIPS_INS_SRA = 1208; + public static final int MIPS_INS_SRAI_B = 1209; + public static final int MIPS_INS_SRAI_D = 1210; + public static final int MIPS_INS_SRAI_H = 1211; + public static final int MIPS_INS_SRAI_W = 1212; + public static final int MIPS_INS_SRARI_B = 1213; + public static final int MIPS_INS_SRARI_D = 1214; + public static final int MIPS_INS_SRARI_H = 1215; + public static final int MIPS_INS_SRARI_W = 1216; + public static final int MIPS_INS_SRAR_B = 1217; + public static final int MIPS_INS_SRAR_D = 1218; + public static final int MIPS_INS_SRAR_H = 1219; + public static final int MIPS_INS_SRAR_W = 1220; + public static final int MIPS_INS_SRAV = 1221; + public static final int MIPS_INS_SRA_B = 1222; + public static final int MIPS_INS_SRA_D = 1223; + public static final int MIPS_INS_SRA_H = 1224; + public static final int MIPS_INS_SRA_W = 1225; + public static final int MIPS_INS_SRL = 1226; + public static final int MIPS_INS_SRL16 = 1227; + public static final int MIPS_INS_SRLI_B = 1228; + public static final int MIPS_INS_SRLI_D = 1229; + public static final int MIPS_INS_SRLI_H = 1230; + public static final int MIPS_INS_SRLI_W = 1231; + public static final int MIPS_INS_SRLRI_B = 1232; + public static final int MIPS_INS_SRLRI_D = 1233; + public static final int MIPS_INS_SRLRI_H = 1234; + public static final int MIPS_INS_SRLRI_W = 1235; + public static final int MIPS_INS_SRLR_B = 1236; + public static final int MIPS_INS_SRLR_D = 1237; + public static final int MIPS_INS_SRLR_H = 1238; + public static final int MIPS_INS_SRLR_W = 1239; + public static final int MIPS_INS_SRLV = 1240; + public static final int MIPS_INS_SRL_B = 1241; + public static final int MIPS_INS_SRL_D = 1242; + public static final int MIPS_INS_SRL_H = 1243; + public static final int MIPS_INS_SRL_W = 1244; + public static final int MIPS_INS_SSNOP = 1245; + public static final int MIPS_INS_ST_B = 1246; + public static final int MIPS_INS_ST_D = 1247; + public static final int MIPS_INS_ST_H = 1248; + public static final int MIPS_INS_ST_W = 1249; + public static final int MIPS_INS_SUB = 1250; + public static final int MIPS_INS_SUBQH_PH = 1251; + public static final int MIPS_INS_SUBQH_R_PH = 1252; + public static final int MIPS_INS_SUBQH_R_W = 1253; + public static final int MIPS_INS_SUBQH_W = 1254; + public static final int MIPS_INS_SUBQ_PH = 1255; + public static final int MIPS_INS_SUBQ_S_PH = 1256; + public static final int MIPS_INS_SUBQ_S_W = 1257; + public static final int MIPS_INS_SUBSUS_U_B = 1258; + public static final int MIPS_INS_SUBSUS_U_D = 1259; + public static final int MIPS_INS_SUBSUS_U_H = 1260; + public static final int MIPS_INS_SUBSUS_U_W = 1261; + public static final int MIPS_INS_SUBSUU_S_B = 1262; + public static final int MIPS_INS_SUBSUU_S_D = 1263; + public static final int MIPS_INS_SUBSUU_S_H = 1264; + public static final int MIPS_INS_SUBSUU_S_W = 1265; + public static final int MIPS_INS_SUBS_S_B = 1266; + public static final int MIPS_INS_SUBS_S_D = 1267; + public static final int MIPS_INS_SUBS_S_H = 1268; + public static final int MIPS_INS_SUBS_S_W = 1269; + public static final int MIPS_INS_SUBS_U_B = 1270; + public static final int MIPS_INS_SUBS_U_D = 1271; + public static final int MIPS_INS_SUBS_U_H = 1272; + public static final int MIPS_INS_SUBS_U_W = 1273; + public static final int MIPS_INS_SUBU16 = 1274; + public static final int MIPS_INS_SUBUH_QB = 1275; + public static final int MIPS_INS_SUBUH_R_QB = 1276; + public static final int MIPS_INS_SUBU_PH = 1277; + public static final int MIPS_INS_SUBU_QB = 1278; + public static final int MIPS_INS_SUBU_S_PH = 1279; + public static final int MIPS_INS_SUBU_S_QB = 1280; + public static final int MIPS_INS_SUBVI_B = 1281; + public static final int MIPS_INS_SUBVI_D = 1282; + public static final int MIPS_INS_SUBVI_H = 1283; + public static final int MIPS_INS_SUBVI_W = 1284; + public static final int MIPS_INS_SUBV_B = 1285; + public static final int MIPS_INS_SUBV_D = 1286; + public static final int MIPS_INS_SUBV_H = 1287; + public static final int MIPS_INS_SUBV_W = 1288; + public static final int MIPS_INS_SUXC1 = 1289; + public static final int MIPS_INS_SW = 1290; + public static final int MIPS_INS_SW16 = 1291; + public static final int MIPS_INS_SWC1 = 1292; + public static final int MIPS_INS_SWC2 = 1293; + public static final int MIPS_INS_SWC3 = 1294; + public static final int MIPS_INS_SWE = 1295; + public static final int MIPS_INS_SWL = 1296; + public static final int MIPS_INS_SWLE = 1297; + public static final int MIPS_INS_SWM16 = 1298; + public static final int MIPS_INS_SWM32 = 1299; + public static final int MIPS_INS_SWPC = 1300; + public static final int MIPS_INS_SWP = 1301; + public static final int MIPS_INS_SWR = 1302; + public static final int MIPS_INS_SWRE = 1303; + public static final int MIPS_INS_SWSP = 1304; + public static final int MIPS_INS_SWXC1 = 1305; + public static final int MIPS_INS_SWXS = 1306; + public static final int MIPS_INS_SWX = 1307; + public static final int MIPS_INS_SYNC = 1308; + public static final int MIPS_INS_SYNCI = 1309; + public static final int MIPS_INS_SYSCALL = 1310; + public static final int MIPS_INS_TEQ = 1311; + public static final int MIPS_INS_TEQI = 1312; + public static final int MIPS_INS_TGE = 1313; + public static final int MIPS_INS_TGEI = 1314; + public static final int MIPS_INS_TGEIU = 1315; + public static final int MIPS_INS_TGEU = 1316; + public static final int MIPS_INS_TLBGINV = 1317; + public static final int MIPS_INS_TLBGINVF = 1318; + public static final int MIPS_INS_TLBGP = 1319; + public static final int MIPS_INS_TLBGR = 1320; + public static final int MIPS_INS_TLBGWI = 1321; + public static final int MIPS_INS_TLBGWR = 1322; + public static final int MIPS_INS_TLBINV = 1323; + public static final int MIPS_INS_TLBINVF = 1324; + public static final int MIPS_INS_TLBP = 1325; + public static final int MIPS_INS_TLBR = 1326; + public static final int MIPS_INS_TLBWI = 1327; + public static final int MIPS_INS_TLBWR = 1328; + public static final int MIPS_INS_TLT = 1329; + public static final int MIPS_INS_TLTI = 1330; + public static final int MIPS_INS_TLTIU = 1331; + public static final int MIPS_INS_TLTU = 1332; + public static final int MIPS_INS_TNE = 1333; + public static final int MIPS_INS_TNEI = 1334; + public static final int MIPS_INS_TRUNC_L_D = 1335; + public static final int MIPS_INS_TRUNC_L_S = 1336; + public static final int MIPS_INS_UALH = 1337; + public static final int MIPS_INS_UALWM = 1338; + public static final int MIPS_INS_UALW = 1339; + public static final int MIPS_INS_UASH = 1340; + public static final int MIPS_INS_UASWM = 1341; + public static final int MIPS_INS_UASW = 1342; + public static final int MIPS_INS_V3MULU = 1343; + public static final int MIPS_INS_VMM0 = 1344; + public static final int MIPS_INS_VMULU = 1345; + public static final int MIPS_INS_VSHF_B = 1346; + public static final int MIPS_INS_VSHF_D = 1347; + public static final int MIPS_INS_VSHF_H = 1348; + public static final int MIPS_INS_VSHF_W = 1349; + public static final int MIPS_INS_WAIT = 1350; + public static final int MIPS_INS_WRDSP = 1351; + public static final int MIPS_INS_WRPGPR = 1352; + public static final int MIPS_INS_WSBH = 1353; + public static final int MIPS_INS_XOR = 1354; + public static final int MIPS_INS_XOR16 = 1355; + public static final int MIPS_INS_XORI_B = 1356; + public static final int MIPS_INS_XORI = 1357; + public static final int MIPS_INS_XOR_V = 1358; + public static final int MIPS_INS_YIELD = 1359; + public static final int MIPS_INS_ENDING = 1360; + public static final int MIPS_INS_ALIAS_BEGIN = 1361; + public static final int MIPS_INS_ALIAS_ADDIU_B32 = 1362; + public static final int MIPS_INS_ALIAS_BITREVB = 1363; + public static final int MIPS_INS_ALIAS_BITREVH = 1364; + public static final int MIPS_INS_ALIAS_BYTEREVH = 1365; + public static final int MIPS_INS_ALIAS_NOT = 1366; + public static final int MIPS_INS_ALIAS_RESTORE_JRC = 1367; + public static final int MIPS_INS_ALIAS_RESTORE = 1368; + public static final int MIPS_INS_ALIAS_SAVE = 1369; + public static final int MIPS_INS_ALIAS_MOVE = 1370; + public static final int MIPS_INS_ALIAS_BAL = 1371; + public static final int MIPS_INS_ALIAS_JALR_HB = 1372; + public static final int MIPS_INS_ALIAS_NEG = 1373; + public static final int MIPS_INS_ALIAS_NEGU = 1374; + public static final int MIPS_INS_ALIAS_NOP = 1375; + public static final int MIPS_INS_ALIAS_BNEZL = 1376; + public static final int MIPS_INS_ALIAS_BEQZL = 1377; + public static final int MIPS_INS_ALIAS_SYSCALL = 1378; + public static final int MIPS_INS_ALIAS_BREAK = 1379; + public static final int MIPS_INS_ALIAS_EI = 1380; + public static final int MIPS_INS_ALIAS_DI = 1381; + public static final int MIPS_INS_ALIAS_TEQ = 1382; + public static final int MIPS_INS_ALIAS_TGE = 1383; + public static final int MIPS_INS_ALIAS_TGEU = 1384; + public static final int MIPS_INS_ALIAS_TLT = 1385; + public static final int MIPS_INS_ALIAS_TLTU = 1386; + public static final int MIPS_INS_ALIAS_TNE = 1387; + public static final int MIPS_INS_ALIAS_RDHWR = 1388; + public static final int MIPS_INS_ALIAS_SDBBP = 1389; + public static final int MIPS_INS_ALIAS_SYNC = 1390; + public static final int MIPS_INS_ALIAS_HYPCALL = 1391; + public static final int MIPS_INS_ALIAS_NOR = 1392; + public static final int MIPS_INS_ALIAS_C_F_S = 1393; + public static final int MIPS_INS_ALIAS_C_UN_S = 1394; + public static final int MIPS_INS_ALIAS_C_EQ_S = 1395; + public static final int MIPS_INS_ALIAS_C_UEQ_S = 1396; + public static final int MIPS_INS_ALIAS_C_OLT_S = 1397; + public static final int MIPS_INS_ALIAS_C_ULT_S = 1398; + public static final int MIPS_INS_ALIAS_C_OLE_S = 1399; + public static final int MIPS_INS_ALIAS_C_ULE_S = 1400; + public static final int MIPS_INS_ALIAS_C_SF_S = 1401; + public static final int MIPS_INS_ALIAS_C_NGLE_S = 1402; + public static final int MIPS_INS_ALIAS_C_SEQ_S = 1403; + public static final int MIPS_INS_ALIAS_C_NGL_S = 1404; + public static final int MIPS_INS_ALIAS_C_LT_S = 1405; + public static final int MIPS_INS_ALIAS_C_NGE_S = 1406; + public static final int MIPS_INS_ALIAS_C_LE_S = 1407; + public static final int MIPS_INS_ALIAS_C_NGT_S = 1408; + public static final int MIPS_INS_ALIAS_BC1T = 1409; + public static final int MIPS_INS_ALIAS_BC1F = 1410; + public static final int MIPS_INS_ALIAS_C_F_D = 1411; + public static final int MIPS_INS_ALIAS_C_UN_D = 1412; + public static final int MIPS_INS_ALIAS_C_EQ_D = 1413; + public static final int MIPS_INS_ALIAS_C_UEQ_D = 1414; + public static final int MIPS_INS_ALIAS_C_OLT_D = 1415; + public static final int MIPS_INS_ALIAS_C_ULT_D = 1416; + public static final int MIPS_INS_ALIAS_C_OLE_D = 1417; + public static final int MIPS_INS_ALIAS_C_ULE_D = 1418; + public static final int MIPS_INS_ALIAS_C_SF_D = 1419; + public static final int MIPS_INS_ALIAS_C_NGLE_D = 1420; + public static final int MIPS_INS_ALIAS_C_SEQ_D = 1421; + public static final int MIPS_INS_ALIAS_C_NGL_D = 1422; + public static final int MIPS_INS_ALIAS_C_LT_D = 1423; + public static final int MIPS_INS_ALIAS_C_NGE_D = 1424; + public static final int MIPS_INS_ALIAS_C_LE_D = 1425; + public static final int MIPS_INS_ALIAS_C_NGT_D = 1426; + public static final int MIPS_INS_ALIAS_BC1TL = 1427; + public static final int MIPS_INS_ALIAS_BC1FL = 1428; + public static final int MIPS_INS_ALIAS_DNEG = 1429; + public static final int MIPS_INS_ALIAS_DNEGU = 1430; + public static final int MIPS_INS_ALIAS_SLT = 1431; + public static final int MIPS_INS_ALIAS_SLTU = 1432; + public static final int MIPS_INS_ALIAS_SIGRIE = 1433; + public static final int MIPS_INS_ALIAS_JR = 1434; + public static final int MIPS_INS_ALIAS_JRC = 1435; + public static final int MIPS_INS_ALIAS_JALRC = 1436; + public static final int MIPS_INS_ALIAS_DIV = 1437; + public static final int MIPS_INS_ALIAS_DIVU = 1438; + public static final int MIPS_INS_ALIAS_LAPC = 1439; + public static final int MIPS_INS_ALIAS_WRDSP = 1440; + public static final int MIPS_INS_ALIAS_WAIT = 1441; + public static final int MIPS_INS_ALIAS_SW = 1442; + public static final int MIPS_INS_ALIAS_JALRC_HB = 1443; + public static final int MIPS_INS_ALIAS_ADDIU_B = 1444; + public static final int MIPS_INS_ALIAS_ADDIU_W = 1445; + public static final int MIPS_INS_ALIAS_JRC_HB = 1446; + public static final int MIPS_INS_ALIAS_BEQC = 1447; + public static final int MIPS_INS_ALIAS_BNEC = 1448; + public static final int MIPS_INS_ALIAS_BEQZC = 1449; + public static final int MIPS_INS_ALIAS_BNEZC = 1450; + public static final int MIPS_INS_ALIAS_MFC0 = 1451; + public static final int MIPS_INS_ALIAS_MFHC0 = 1452; + public static final int MIPS_INS_ALIAS_MTC0 = 1453; + public static final int MIPS_INS_ALIAS_MTHC0 = 1454; + public static final int MIPS_INS_ALIAS_DMT = 1455; + public static final int MIPS_INS_ALIAS_EMT = 1456; + public static final int MIPS_INS_ALIAS_DVPE = 1457; + public static final int MIPS_INS_ALIAS_EVPE = 1458; + public static final int MIPS_INS_ALIAS_YIELD = 1459; + public static final int MIPS_INS_ALIAS_MFTC0 = 1460; + public static final int MIPS_INS_ALIAS_MFTLO = 1461; + public static final int MIPS_INS_ALIAS_MFTHI = 1462; + public static final int MIPS_INS_ALIAS_MFTACX = 1463; + public static final int MIPS_INS_ALIAS_MTTC0 = 1464; + public static final int MIPS_INS_ALIAS_MTTLO = 1465; + public static final int MIPS_INS_ALIAS_MTTHI = 1466; + public static final int MIPS_INS_ALIAS_MTTACX = 1467; + public static final int MIPS_INS_ALIAS_END = 1468; public static final int MIPS_GRP_INVALID = 0; public static final int MIPS_GRP_JUMP = 1; @@ -828,38 +2123,61 @@ public class Mips_const { public static final int MIPS_GRP_IRET = 5; public static final int MIPS_GRP_PRIVILEGE = 6; public static final int MIPS_GRP_BRANCH_RELATIVE = 7; - public static final int MIPS_GRP_BITCOUNT = 128; - public static final int MIPS_GRP_DSP = 129; - public static final int MIPS_GRP_DSPR2 = 130; - public static final int MIPS_GRP_FPIDX = 131; - public static final int MIPS_GRP_MSA = 132; - public static final int MIPS_GRP_MIPS32R2 = 133; - public static final int MIPS_GRP_MIPS64 = 134; - public static final int MIPS_GRP_MIPS64R2 = 135; - public static final int MIPS_GRP_SEINREG = 136; - public static final int MIPS_GRP_STDENC = 137; - public static final int MIPS_GRP_SWAP = 138; - public static final int MIPS_GRP_MICROMIPS = 139; - public static final int MIPS_GRP_MIPS16MODE = 140; - public static final int MIPS_GRP_FP64BIT = 141; - public static final int MIPS_GRP_NONANSFPMATH = 142; - public static final int MIPS_GRP_NOTFP64BIT = 143; - public static final int MIPS_GRP_NOTINMICROMIPS = 144; - public static final int MIPS_GRP_NOTNACL = 145; - public static final int MIPS_GRP_NOTMIPS32R6 = 146; - public static final int MIPS_GRP_NOTMIPS64R6 = 147; - public static final int MIPS_GRP_CNMIPS = 148; - public static final int MIPS_GRP_MIPS32 = 149; - public static final int MIPS_GRP_MIPS32R6 = 150; - public static final int MIPS_GRP_MIPS64R6 = 151; - public static final int MIPS_GRP_MIPS2 = 152; - public static final int MIPS_GRP_MIPS3 = 153; - public static final int MIPS_GRP_MIPS3_32 = 154; - public static final int MIPS_GRP_MIPS3_32R2 = 155; - public static final int MIPS_GRP_MIPS4_32 = 156; - public static final int MIPS_GRP_MIPS4_32R2 = 157; - public static final int MIPS_GRP_MIPS5_32R2 = 158; - public static final int MIPS_GRP_GP32BIT = 159; - public static final int MIPS_GRP_GP64BIT = 160; - public static final int MIPS_GRP_ENDING = 161; + public static final int MIPS_FEATURE_HASMIPS2 = 128; + public static final int MIPS_FEATURE_HASMIPS3_32 = 129; + public static final int MIPS_FEATURE_HASMIPS3_32R2 = 130; + public static final int MIPS_FEATURE_HASMIPS3 = 131; + public static final int MIPS_FEATURE_NOTMIPS3 = 132; + public static final int MIPS_FEATURE_HASMIPS4_32 = 133; + public static final int MIPS_FEATURE_NOTMIPS4_32 = 134; + public static final int MIPS_FEATURE_HASMIPS4_32R2 = 135; + public static final int MIPS_FEATURE_HASMIPS5_32R2 = 136; + public static final int MIPS_FEATURE_HASMIPS32 = 137; + public static final int MIPS_FEATURE_HASMIPS32R2 = 138; + public static final int MIPS_FEATURE_HASMIPS32R5 = 139; + public static final int MIPS_FEATURE_HASMIPS32R6 = 140; + public static final int MIPS_FEATURE_NOTMIPS32R6 = 141; + public static final int MIPS_FEATURE_HASNANOMIPS = 142; + public static final int MIPS_FEATURE_NOTNANOMIPS = 143; + public static final int MIPS_FEATURE_ISGP64BIT = 144; + public static final int MIPS_FEATURE_ISGP32BIT = 145; + public static final int MIPS_FEATURE_ISPTR64BIT = 146; + public static final int MIPS_FEATURE_ISPTR32BIT = 147; + public static final int MIPS_FEATURE_HASMIPS64 = 148; + public static final int MIPS_FEATURE_NOTMIPS64 = 149; + public static final int MIPS_FEATURE_HASMIPS64R2 = 150; + public static final int MIPS_FEATURE_HASMIPS64R5 = 151; + public static final int MIPS_FEATURE_HASMIPS64R6 = 152; + public static final int MIPS_FEATURE_NOTMIPS64R6 = 153; + public static final int MIPS_FEATURE_INMIPS16MODE = 154; + public static final int MIPS_FEATURE_NOTINMIPS16MODE = 155; + public static final int MIPS_FEATURE_HASCNMIPS = 156; + public static final int MIPS_FEATURE_NOTCNMIPS = 157; + public static final int MIPS_FEATURE_HASCNMIPSP = 158; + public static final int MIPS_FEATURE_NOTCNMIPSP = 159; + public static final int MIPS_FEATURE_ISSYM32 = 160; + public static final int MIPS_FEATURE_ISSYM64 = 161; + public static final int MIPS_FEATURE_HASSTDENC = 162; + public static final int MIPS_FEATURE_INMICROMIPS = 163; + public static final int MIPS_FEATURE_NOTINMICROMIPS = 164; + public static final int MIPS_FEATURE_HASEVA = 165; + public static final int MIPS_FEATURE_HASMSA = 166; + public static final int MIPS_FEATURE_HASMADD4 = 167; + public static final int MIPS_FEATURE_HASMT = 168; + public static final int MIPS_FEATURE_USEINDIRECTJUMPSHAZARD = 169; + public static final int MIPS_FEATURE_NOINDIRECTJUMPGUARDS = 170; + public static final int MIPS_FEATURE_HASCRC = 171; + public static final int MIPS_FEATURE_HASVIRT = 172; + public static final int MIPS_FEATURE_HASGINV = 173; + public static final int MIPS_FEATURE_HASTLB = 174; + public static final int MIPS_FEATURE_ISFP64BIT = 175; + public static final int MIPS_FEATURE_NOTFP64BIT = 176; + public static final int MIPS_FEATURE_ISSINGLEFLOAT = 177; + public static final int MIPS_FEATURE_ISNOTSINGLEFLOAT = 178; + public static final int MIPS_FEATURE_ISNOTSOFTFLOAT = 179; + public static final int MIPS_FEATURE_HASMIPS3D = 180; + public static final int MIPS_FEATURE_HASDSP = 181; + public static final int MIPS_FEATURE_HASDSPR2 = 182; + public static final int MIPS_FEATURE_HASDSPR3 = 183; + public static final int MIPS_GRP_ENDING = 184; } \ No newline at end of file diff --git a/bindings/ocaml/mips_const.ml b/bindings/ocaml/mips_const.ml index e0b581be6..fed8ff15b 100644 --- a/bindings/ocaml/mips_const.ml +++ b/bindings/ocaml/mips_const.ml @@ -6,816 +6,2111 @@ let _MIPS_OP_IMM = 2;; let _MIPS_OP_MEM = 3;; let _MIPS_REG_INVALID = 0;; -let _MIPS_REG_PC = 1;; -let _MIPS_REG_0 = 2;; -let _MIPS_REG_1 = 3;; -let _MIPS_REG_2 = 4;; -let _MIPS_REG_3 = 5;; -let _MIPS_REG_4 = 6;; -let _MIPS_REG_5 = 7;; -let _MIPS_REG_6 = 8;; -let _MIPS_REG_7 = 9;; -let _MIPS_REG_8 = 10;; -let _MIPS_REG_9 = 11;; -let _MIPS_REG_10 = 12;; -let _MIPS_REG_11 = 13;; -let _MIPS_REG_12 = 14;; -let _MIPS_REG_13 = 15;; -let _MIPS_REG_14 = 16;; -let _MIPS_REG_15 = 17;; -let _MIPS_REG_16 = 18;; -let _MIPS_REG_17 = 19;; -let _MIPS_REG_18 = 20;; -let _MIPS_REG_19 = 21;; -let _MIPS_REG_20 = 22;; -let _MIPS_REG_21 = 23;; -let _MIPS_REG_22 = 24;; -let _MIPS_REG_23 = 25;; -let _MIPS_REG_24 = 26;; -let _MIPS_REG_25 = 27;; -let _MIPS_REG_26 = 28;; -let _MIPS_REG_27 = 29;; -let _MIPS_REG_28 = 30;; -let _MIPS_REG_29 = 31;; -let _MIPS_REG_30 = 32;; -let _MIPS_REG_31 = 33;; -let _MIPS_REG_DSPCCOND = 34;; -let _MIPS_REG_DSPCARRY = 35;; -let _MIPS_REG_DSPEFI = 36;; -let _MIPS_REG_DSPOUTFLAG = 37;; -let _MIPS_REG_DSPOUTFLAG16_19 = 38;; -let _MIPS_REG_DSPOUTFLAG20 = 39;; -let _MIPS_REG_DSPOUTFLAG21 = 40;; -let _MIPS_REG_DSPOUTFLAG22 = 41;; -let _MIPS_REG_DSPOUTFLAG23 = 42;; -let _MIPS_REG_DSPPOS = 43;; -let _MIPS_REG_DSPSCOUNT = 44;; -let _MIPS_REG_AC0 = 45;; -let _MIPS_REG_AC1 = 46;; -let _MIPS_REG_AC2 = 47;; -let _MIPS_REG_AC3 = 48;; -let _MIPS_REG_CC0 = 49;; -let _MIPS_REG_CC1 = 50;; -let _MIPS_REG_CC2 = 51;; -let _MIPS_REG_CC3 = 52;; -let _MIPS_REG_CC4 = 53;; -let _MIPS_REG_CC5 = 54;; -let _MIPS_REG_CC6 = 55;; -let _MIPS_REG_CC7 = 56;; -let _MIPS_REG_F0 = 57;; -let _MIPS_REG_F1 = 58;; -let _MIPS_REG_F2 = 59;; -let _MIPS_REG_F3 = 60;; -let _MIPS_REG_F4 = 61;; -let _MIPS_REG_F5 = 62;; -let _MIPS_REG_F6 = 63;; -let _MIPS_REG_F7 = 64;; -let _MIPS_REG_F8 = 65;; -let _MIPS_REG_F9 = 66;; -let _MIPS_REG_F10 = 67;; -let _MIPS_REG_F11 = 68;; -let _MIPS_REG_F12 = 69;; -let _MIPS_REG_F13 = 70;; -let _MIPS_REG_F14 = 71;; -let _MIPS_REG_F15 = 72;; -let _MIPS_REG_F16 = 73;; -let _MIPS_REG_F17 = 74;; -let _MIPS_REG_F18 = 75;; -let _MIPS_REG_F19 = 76;; -let _MIPS_REG_F20 = 77;; -let _MIPS_REG_F21 = 78;; -let _MIPS_REG_F22 = 79;; -let _MIPS_REG_F23 = 80;; -let _MIPS_REG_F24 = 81;; -let _MIPS_REG_F25 = 82;; -let _MIPS_REG_F26 = 83;; -let _MIPS_REG_F27 = 84;; -let _MIPS_REG_F28 = 85;; -let _MIPS_REG_F29 = 86;; -let _MIPS_REG_F30 = 87;; -let _MIPS_REG_F31 = 88;; -let _MIPS_REG_FCC0 = 89;; -let _MIPS_REG_FCC1 = 90;; -let _MIPS_REG_FCC2 = 91;; -let _MIPS_REG_FCC3 = 92;; -let _MIPS_REG_FCC4 = 93;; -let _MIPS_REG_FCC5 = 94;; -let _MIPS_REG_FCC6 = 95;; -let _MIPS_REG_FCC7 = 96;; -let _MIPS_REG_W0 = 97;; -let _MIPS_REG_W1 = 98;; -let _MIPS_REG_W2 = 99;; -let _MIPS_REG_W3 = 100;; -let _MIPS_REG_W4 = 101;; -let _MIPS_REG_W5 = 102;; -let _MIPS_REG_W6 = 103;; -let _MIPS_REG_W7 = 104;; -let _MIPS_REG_W8 = 105;; -let _MIPS_REG_W9 = 106;; -let _MIPS_REG_W10 = 107;; -let _MIPS_REG_W11 = 108;; -let _MIPS_REG_W12 = 109;; -let _MIPS_REG_W13 = 110;; -let _MIPS_REG_W14 = 111;; -let _MIPS_REG_W15 = 112;; -let _MIPS_REG_W16 = 113;; -let _MIPS_REG_W17 = 114;; -let _MIPS_REG_W18 = 115;; -let _MIPS_REG_W19 = 116;; -let _MIPS_REG_W20 = 117;; -let _MIPS_REG_W21 = 118;; -let _MIPS_REG_W22 = 119;; -let _MIPS_REG_W23 = 120;; -let _MIPS_REG_W24 = 121;; -let _MIPS_REG_W25 = 122;; -let _MIPS_REG_W26 = 123;; -let _MIPS_REG_W27 = 124;; -let _MIPS_REG_W28 = 125;; -let _MIPS_REG_W29 = 126;; -let _MIPS_REG_W30 = 127;; -let _MIPS_REG_W31 = 128;; -let _MIPS_REG_HI = 129;; -let _MIPS_REG_LO = 130;; -let _MIPS_REG_P0 = 131;; -let _MIPS_REG_P1 = 132;; -let _MIPS_REG_P2 = 133;; -let _MIPS_REG_MPL0 = 134;; -let _MIPS_REG_MPL1 = 135;; -let _MIPS_REG_MPL2 = 136;; -let _MIPS_REG_ENDING = 137;; -let _MIPS_REG_ZERO = _MIPS_REG_0;; -let _MIPS_REG_AT = _MIPS_REG_1;; -let _MIPS_REG_V0 = _MIPS_REG_2;; -let _MIPS_REG_V1 = _MIPS_REG_3;; -let _MIPS_REG_A0 = _MIPS_REG_4;; -let _MIPS_REG_A1 = _MIPS_REG_5;; -let _MIPS_REG_A2 = _MIPS_REG_6;; -let _MIPS_REG_A3 = _MIPS_REG_7;; -let _MIPS_REG_T0 = _MIPS_REG_8;; -let _MIPS_REG_T1 = _MIPS_REG_9;; -let _MIPS_REG_T2 = _MIPS_REG_10;; -let _MIPS_REG_T3 = _MIPS_REG_11;; -let _MIPS_REG_T4 = _MIPS_REG_12;; -let _MIPS_REG_T5 = _MIPS_REG_13;; -let _MIPS_REG_T6 = _MIPS_REG_14;; -let _MIPS_REG_T7 = _MIPS_REG_15;; -let _MIPS_REG_S0 = _MIPS_REG_16;; -let _MIPS_REG_S1 = _MIPS_REG_17;; -let _MIPS_REG_S2 = _MIPS_REG_18;; -let _MIPS_REG_S3 = _MIPS_REG_19;; -let _MIPS_REG_S4 = _MIPS_REG_20;; -let _MIPS_REG_S5 = _MIPS_REG_21;; -let _MIPS_REG_S6 = _MIPS_REG_22;; -let _MIPS_REG_S7 = _MIPS_REG_23;; -let _MIPS_REG_T8 = _MIPS_REG_24;; -let _MIPS_REG_T9 = _MIPS_REG_25;; -let _MIPS_REG_K0 = _MIPS_REG_26;; -let _MIPS_REG_K1 = _MIPS_REG_27;; -let _MIPS_REG_GP = _MIPS_REG_28;; -let _MIPS_REG_SP = _MIPS_REG_29;; -let _MIPS_REG_FP = _MIPS_REG_30;; -let _MIPS_REG_S8 = _MIPS_REG_30;; -let _MIPS_REG_RA = _MIPS_REG_31;; -let _MIPS_REG_HI0 = _MIPS_REG_AC0;; -let _MIPS_REG_HI1 = _MIPS_REG_AC1;; -let _MIPS_REG_HI2 = _MIPS_REG_AC2;; -let _MIPS_REG_HI3 = _MIPS_REG_AC3;; -let _MIPS_REG_LO0 = _MIPS_REG_HI0;; -let _MIPS_REG_LO1 = _MIPS_REG_HI1;; -let _MIPS_REG_LO2 = _MIPS_REG_HI2;; -let _MIPS_REG_LO3 = _MIPS_REG_HI3;; +let _MIPS_REG_AT = 1;; +let _MIPS_REG_AT_NM = 2;; +let _MIPS_REG_DSPCCOND = 3;; +let _MIPS_REG_DSPCARRY = 4;; +let _MIPS_REG_DSPEFI = 5;; +let _MIPS_REG_DSPOUTFLAG = 6;; +let _MIPS_REG_DSPPOS = 7;; +let _MIPS_REG_DSPSCOUNT = 8;; +let _MIPS_REG_FP = 9;; +let _MIPS_REG_FP_NM = 10;; +let _MIPS_REG_GP = 11;; +let _MIPS_REG_GP_NM = 12;; +let _MIPS_REG_MSAACCESS = 13;; +let _MIPS_REG_MSACSR = 14;; +let _MIPS_REG_MSAIR = 15;; +let _MIPS_REG_MSAMAP = 16;; +let _MIPS_REG_MSAMODIFY = 17;; +let _MIPS_REG_MSAREQUEST = 18;; +let _MIPS_REG_MSASAVE = 19;; +let _MIPS_REG_MSAUNMAP = 20;; +let _MIPS_REG_PC = 21;; +let _MIPS_REG_RA = 22;; +let _MIPS_REG_RA_NM = 23;; +let _MIPS_REG_SP = 24;; +let _MIPS_REG_SP_NM = 25;; +let _MIPS_REG_ZERO = 26;; +let _MIPS_REG_ZERO_NM = 27;; +let _MIPS_REG_A0 = 28;; +let _MIPS_REG_A1 = 29;; +let _MIPS_REG_A2 = 30;; +let _MIPS_REG_A3 = 31;; +let _MIPS_REG_AC0 = 32;; +let _MIPS_REG_AC1 = 33;; +let _MIPS_REG_AC2 = 34;; +let _MIPS_REG_AC3 = 35;; +let _MIPS_REG_AT_64 = 36;; +let _MIPS_REG_COP00 = 37;; +let _MIPS_REG_COP01 = 38;; +let _MIPS_REG_COP02 = 39;; +let _MIPS_REG_COP03 = 40;; +let _MIPS_REG_COP04 = 41;; +let _MIPS_REG_COP05 = 42;; +let _MIPS_REG_COP06 = 43;; +let _MIPS_REG_COP07 = 44;; +let _MIPS_REG_COP08 = 45;; +let _MIPS_REG_COP09 = 46;; +let _MIPS_REG_COP20 = 47;; +let _MIPS_REG_COP21 = 48;; +let _MIPS_REG_COP22 = 49;; +let _MIPS_REG_COP23 = 50;; +let _MIPS_REG_COP24 = 51;; +let _MIPS_REG_COP25 = 52;; +let _MIPS_REG_COP26 = 53;; +let _MIPS_REG_COP27 = 54;; +let _MIPS_REG_COP28 = 55;; +let _MIPS_REG_COP29 = 56;; +let _MIPS_REG_COP30 = 57;; +let _MIPS_REG_COP31 = 58;; +let _MIPS_REG_COP32 = 59;; +let _MIPS_REG_COP33 = 60;; +let _MIPS_REG_COP34 = 61;; +let _MIPS_REG_COP35 = 62;; +let _MIPS_REG_COP36 = 63;; +let _MIPS_REG_COP37 = 64;; +let _MIPS_REG_COP38 = 65;; +let _MIPS_REG_COP39 = 66;; +let _MIPS_REG_COP010 = 67;; +let _MIPS_REG_COP011 = 68;; +let _MIPS_REG_COP012 = 69;; +let _MIPS_REG_COP013 = 70;; +let _MIPS_REG_COP014 = 71;; +let _MIPS_REG_COP015 = 72;; +let _MIPS_REG_COP016 = 73;; +let _MIPS_REG_COP017 = 74;; +let _MIPS_REG_COP018 = 75;; +let _MIPS_REG_COP019 = 76;; +let _MIPS_REG_COP020 = 77;; +let _MIPS_REG_COP021 = 78;; +let _MIPS_REG_COP022 = 79;; +let _MIPS_REG_COP023 = 80;; +let _MIPS_REG_COP024 = 81;; +let _MIPS_REG_COP025 = 82;; +let _MIPS_REG_COP026 = 83;; +let _MIPS_REG_COP027 = 84;; +let _MIPS_REG_COP028 = 85;; +let _MIPS_REG_COP029 = 86;; +let _MIPS_REG_COP030 = 87;; +let _MIPS_REG_COP031 = 88;; +let _MIPS_REG_COP210 = 89;; +let _MIPS_REG_COP211 = 90;; +let _MIPS_REG_COP212 = 91;; +let _MIPS_REG_COP213 = 92;; +let _MIPS_REG_COP214 = 93;; +let _MIPS_REG_COP215 = 94;; +let _MIPS_REG_COP216 = 95;; +let _MIPS_REG_COP217 = 96;; +let _MIPS_REG_COP218 = 97;; +let _MIPS_REG_COP219 = 98;; +let _MIPS_REG_COP220 = 99;; +let _MIPS_REG_COP221 = 100;; +let _MIPS_REG_COP222 = 101;; +let _MIPS_REG_COP223 = 102;; +let _MIPS_REG_COP224 = 103;; +let _MIPS_REG_COP225 = 104;; +let _MIPS_REG_COP226 = 105;; +let _MIPS_REG_COP227 = 106;; +let _MIPS_REG_COP228 = 107;; +let _MIPS_REG_COP229 = 108;; +let _MIPS_REG_COP230 = 109;; +let _MIPS_REG_COP231 = 110;; +let _MIPS_REG_COP310 = 111;; +let _MIPS_REG_COP311 = 112;; +let _MIPS_REG_COP312 = 113;; +let _MIPS_REG_COP313 = 114;; +let _MIPS_REG_COP314 = 115;; +let _MIPS_REG_COP315 = 116;; +let _MIPS_REG_COP316 = 117;; +let _MIPS_REG_COP317 = 118;; +let _MIPS_REG_COP318 = 119;; +let _MIPS_REG_COP319 = 120;; +let _MIPS_REG_COP320 = 121;; +let _MIPS_REG_COP321 = 122;; +let _MIPS_REG_COP322 = 123;; +let _MIPS_REG_COP323 = 124;; +let _MIPS_REG_COP324 = 125;; +let _MIPS_REG_COP325 = 126;; +let _MIPS_REG_COP326 = 127;; +let _MIPS_REG_COP327 = 128;; +let _MIPS_REG_COP328 = 129;; +let _MIPS_REG_COP329 = 130;; +let _MIPS_REG_COP330 = 131;; +let _MIPS_REG_COP331 = 132;; +let _MIPS_REG_D0 = 133;; +let _MIPS_REG_D1 = 134;; +let _MIPS_REG_D2 = 135;; +let _MIPS_REG_D3 = 136;; +let _MIPS_REG_D4 = 137;; +let _MIPS_REG_D5 = 138;; +let _MIPS_REG_D6 = 139;; +let _MIPS_REG_D7 = 140;; +let _MIPS_REG_D8 = 141;; +let _MIPS_REG_D9 = 142;; +let _MIPS_REG_D10 = 143;; +let _MIPS_REG_D11 = 144;; +let _MIPS_REG_D12 = 145;; +let _MIPS_REG_D13 = 146;; +let _MIPS_REG_D14 = 147;; +let _MIPS_REG_D15 = 148;; +let _MIPS_REG_DSPOUTFLAG20 = 149;; +let _MIPS_REG_DSPOUTFLAG21 = 150;; +let _MIPS_REG_DSPOUTFLAG22 = 151;; +let _MIPS_REG_DSPOUTFLAG23 = 152;; +let _MIPS_REG_F0 = 153;; +let _MIPS_REG_F1 = 154;; +let _MIPS_REG_F2 = 155;; +let _MIPS_REG_F3 = 156;; +let _MIPS_REG_F4 = 157;; +let _MIPS_REG_F5 = 158;; +let _MIPS_REG_F6 = 159;; +let _MIPS_REG_F7 = 160;; +let _MIPS_REG_F8 = 161;; +let _MIPS_REG_F9 = 162;; +let _MIPS_REG_F10 = 163;; +let _MIPS_REG_F11 = 164;; +let _MIPS_REG_F12 = 165;; +let _MIPS_REG_F13 = 166;; +let _MIPS_REG_F14 = 167;; +let _MIPS_REG_F15 = 168;; +let _MIPS_REG_F16 = 169;; +let _MIPS_REG_F17 = 170;; +let _MIPS_REG_F18 = 171;; +let _MIPS_REG_F19 = 172;; +let _MIPS_REG_F20 = 173;; +let _MIPS_REG_F21 = 174;; +let _MIPS_REG_F22 = 175;; +let _MIPS_REG_F23 = 176;; +let _MIPS_REG_F24 = 177;; +let _MIPS_REG_F25 = 178;; +let _MIPS_REG_F26 = 179;; +let _MIPS_REG_F27 = 180;; +let _MIPS_REG_F28 = 181;; +let _MIPS_REG_F29 = 182;; +let _MIPS_REG_F30 = 183;; +let _MIPS_REG_F31 = 184;; +let _MIPS_REG_FCC0 = 185;; +let _MIPS_REG_FCC1 = 186;; +let _MIPS_REG_FCC2 = 187;; +let _MIPS_REG_FCC3 = 188;; +let _MIPS_REG_FCC4 = 189;; +let _MIPS_REG_FCC5 = 190;; +let _MIPS_REG_FCC6 = 191;; +let _MIPS_REG_FCC7 = 192;; +let _MIPS_REG_FCR0 = 193;; +let _MIPS_REG_FCR1 = 194;; +let _MIPS_REG_FCR2 = 195;; +let _MIPS_REG_FCR3 = 196;; +let _MIPS_REG_FCR4 = 197;; +let _MIPS_REG_FCR5 = 198;; +let _MIPS_REG_FCR6 = 199;; +let _MIPS_REG_FCR7 = 200;; +let _MIPS_REG_FCR8 = 201;; +let _MIPS_REG_FCR9 = 202;; +let _MIPS_REG_FCR10 = 203;; +let _MIPS_REG_FCR11 = 204;; +let _MIPS_REG_FCR12 = 205;; +let _MIPS_REG_FCR13 = 206;; +let _MIPS_REG_FCR14 = 207;; +let _MIPS_REG_FCR15 = 208;; +let _MIPS_REG_FCR16 = 209;; +let _MIPS_REG_FCR17 = 210;; +let _MIPS_REG_FCR18 = 211;; +let _MIPS_REG_FCR19 = 212;; +let _MIPS_REG_FCR20 = 213;; +let _MIPS_REG_FCR21 = 214;; +let _MIPS_REG_FCR22 = 215;; +let _MIPS_REG_FCR23 = 216;; +let _MIPS_REG_FCR24 = 217;; +let _MIPS_REG_FCR25 = 218;; +let _MIPS_REG_FCR26 = 219;; +let _MIPS_REG_FCR27 = 220;; +let _MIPS_REG_FCR28 = 221;; +let _MIPS_REG_FCR29 = 222;; +let _MIPS_REG_FCR30 = 223;; +let _MIPS_REG_FCR31 = 224;; +let _MIPS_REG_FP_64 = 225;; +let _MIPS_REG_F_HI0 = 226;; +let _MIPS_REG_F_HI1 = 227;; +let _MIPS_REG_F_HI2 = 228;; +let _MIPS_REG_F_HI3 = 229;; +let _MIPS_REG_F_HI4 = 230;; +let _MIPS_REG_F_HI5 = 231;; +let _MIPS_REG_F_HI6 = 232;; +let _MIPS_REG_F_HI7 = 233;; +let _MIPS_REG_F_HI8 = 234;; +let _MIPS_REG_F_HI9 = 235;; +let _MIPS_REG_F_HI10 = 236;; +let _MIPS_REG_F_HI11 = 237;; +let _MIPS_REG_F_HI12 = 238;; +let _MIPS_REG_F_HI13 = 239;; +let _MIPS_REG_F_HI14 = 240;; +let _MIPS_REG_F_HI15 = 241;; +let _MIPS_REG_F_HI16 = 242;; +let _MIPS_REG_F_HI17 = 243;; +let _MIPS_REG_F_HI18 = 244;; +let _MIPS_REG_F_HI19 = 245;; +let _MIPS_REG_F_HI20 = 246;; +let _MIPS_REG_F_HI21 = 247;; +let _MIPS_REG_F_HI22 = 248;; +let _MIPS_REG_F_HI23 = 249;; +let _MIPS_REG_F_HI24 = 250;; +let _MIPS_REG_F_HI25 = 251;; +let _MIPS_REG_F_HI26 = 252;; +let _MIPS_REG_F_HI27 = 253;; +let _MIPS_REG_F_HI28 = 254;; +let _MIPS_REG_F_HI29 = 255;; +let _MIPS_REG_F_HI30 = 256;; +let _MIPS_REG_F_HI31 = 257;; +let _MIPS_REG_GP_64 = 258;; +let _MIPS_REG_HI0 = 259;; +let _MIPS_REG_HI1 = 260;; +let _MIPS_REG_HI2 = 261;; +let _MIPS_REG_HI3 = 262;; +let _MIPS_REG_HWR0 = 263;; +let _MIPS_REG_HWR1 = 264;; +let _MIPS_REG_HWR2 = 265;; +let _MIPS_REG_HWR3 = 266;; +let _MIPS_REG_HWR4 = 267;; +let _MIPS_REG_HWR5 = 268;; +let _MIPS_REG_HWR6 = 269;; +let _MIPS_REG_HWR7 = 270;; +let _MIPS_REG_HWR8 = 271;; +let _MIPS_REG_HWR9 = 272;; +let _MIPS_REG_HWR10 = 273;; +let _MIPS_REG_HWR11 = 274;; +let _MIPS_REG_HWR12 = 275;; +let _MIPS_REG_HWR13 = 276;; +let _MIPS_REG_HWR14 = 277;; +let _MIPS_REG_HWR15 = 278;; +let _MIPS_REG_HWR16 = 279;; +let _MIPS_REG_HWR17 = 280;; +let _MIPS_REG_HWR18 = 281;; +let _MIPS_REG_HWR19 = 282;; +let _MIPS_REG_HWR20 = 283;; +let _MIPS_REG_HWR21 = 284;; +let _MIPS_REG_HWR22 = 285;; +let _MIPS_REG_HWR23 = 286;; +let _MIPS_REG_HWR24 = 287;; +let _MIPS_REG_HWR25 = 288;; +let _MIPS_REG_HWR26 = 289;; +let _MIPS_REG_HWR27 = 290;; +let _MIPS_REG_HWR28 = 291;; +let _MIPS_REG_HWR29 = 292;; +let _MIPS_REG_HWR30 = 293;; +let _MIPS_REG_HWR31 = 294;; +let _MIPS_REG_K0 = 295;; +let _MIPS_REG_K1 = 296;; +let _MIPS_REG_LO0 = 297;; +let _MIPS_REG_LO1 = 298;; +let _MIPS_REG_LO2 = 299;; +let _MIPS_REG_LO3 = 300;; +let _MIPS_REG_MPL0 = 301;; +let _MIPS_REG_MPL1 = 302;; +let _MIPS_REG_MPL2 = 303;; +let _MIPS_REG_MSA8 = 304;; +let _MIPS_REG_MSA9 = 305;; +let _MIPS_REG_MSA10 = 306;; +let _MIPS_REG_MSA11 = 307;; +let _MIPS_REG_MSA12 = 308;; +let _MIPS_REG_MSA13 = 309;; +let _MIPS_REG_MSA14 = 310;; +let _MIPS_REG_MSA15 = 311;; +let _MIPS_REG_MSA16 = 312;; +let _MIPS_REG_MSA17 = 313;; +let _MIPS_REG_MSA18 = 314;; +let _MIPS_REG_MSA19 = 315;; +let _MIPS_REG_MSA20 = 316;; +let _MIPS_REG_MSA21 = 317;; +let _MIPS_REG_MSA22 = 318;; +let _MIPS_REG_MSA23 = 319;; +let _MIPS_REG_MSA24 = 320;; +let _MIPS_REG_MSA25 = 321;; +let _MIPS_REG_MSA26 = 322;; +let _MIPS_REG_MSA27 = 323;; +let _MIPS_REG_MSA28 = 324;; +let _MIPS_REG_MSA29 = 325;; +let _MIPS_REG_MSA30 = 326;; +let _MIPS_REG_MSA31 = 327;; +let _MIPS_REG_P0 = 328;; +let _MIPS_REG_P1 = 329;; +let _MIPS_REG_P2 = 330;; +let _MIPS_REG_RA_64 = 331;; +let _MIPS_REG_S0 = 332;; +let _MIPS_REG_S1 = 333;; +let _MIPS_REG_S2 = 334;; +let _MIPS_REG_S3 = 335;; +let _MIPS_REG_S4 = 336;; +let _MIPS_REG_S5 = 337;; +let _MIPS_REG_S6 = 338;; +let _MIPS_REG_S7 = 339;; +let _MIPS_REG_SP_64 = 340;; +let _MIPS_REG_T0 = 341;; +let _MIPS_REG_T1 = 342;; +let _MIPS_REG_T2 = 343;; +let _MIPS_REG_T3 = 344;; +let _MIPS_REG_T4 = 345;; +let _MIPS_REG_T5 = 346;; +let _MIPS_REG_T6 = 347;; +let _MIPS_REG_T7 = 348;; +let _MIPS_REG_T8 = 349;; +let _MIPS_REG_T9 = 350;; +let _MIPS_REG_V0 = 351;; +let _MIPS_REG_V1 = 352;; +let _MIPS_REG_W0 = 353;; +let _MIPS_REG_W1 = 354;; +let _MIPS_REG_W2 = 355;; +let _MIPS_REG_W3 = 356;; +let _MIPS_REG_W4 = 357;; +let _MIPS_REG_W5 = 358;; +let _MIPS_REG_W6 = 359;; +let _MIPS_REG_W7 = 360;; +let _MIPS_REG_W8 = 361;; +let _MIPS_REG_W9 = 362;; +let _MIPS_REG_W10 = 363;; +let _MIPS_REG_W11 = 364;; +let _MIPS_REG_W12 = 365;; +let _MIPS_REG_W13 = 366;; +let _MIPS_REG_W14 = 367;; +let _MIPS_REG_W15 = 368;; +let _MIPS_REG_W16 = 369;; +let _MIPS_REG_W17 = 370;; +let _MIPS_REG_W18 = 371;; +let _MIPS_REG_W19 = 372;; +let _MIPS_REG_W20 = 373;; +let _MIPS_REG_W21 = 374;; +let _MIPS_REG_W22 = 375;; +let _MIPS_REG_W23 = 376;; +let _MIPS_REG_W24 = 377;; +let _MIPS_REG_W25 = 378;; +let _MIPS_REG_W26 = 379;; +let _MIPS_REG_W27 = 380;; +let _MIPS_REG_W28 = 381;; +let _MIPS_REG_W29 = 382;; +let _MIPS_REG_W30 = 383;; +let _MIPS_REG_W31 = 384;; +let _MIPS_REG_ZERO_64 = 385;; +let _MIPS_REG_A0_NM = 386;; +let _MIPS_REG_A1_NM = 387;; +let _MIPS_REG_A2_NM = 388;; +let _MIPS_REG_A3_NM = 389;; +let _MIPS_REG_A4_NM = 390;; +let _MIPS_REG_A5_NM = 391;; +let _MIPS_REG_A6_NM = 392;; +let _MIPS_REG_A7_NM = 393;; +let _MIPS_REG_COP0SEL_BADINST = 394;; +let _MIPS_REG_COP0SEL_BADINSTRP = 395;; +let _MIPS_REG_COP0SEL_BADINSTRX = 396;; +let _MIPS_REG_COP0SEL_BADVADDR = 397;; +let _MIPS_REG_COP0SEL_BEVVA = 398;; +let _MIPS_REG_COP0SEL_CACHEERR = 399;; +let _MIPS_REG_COP0SEL_CAUSE = 400;; +let _MIPS_REG_COP0SEL_CDMMBASE = 401;; +let _MIPS_REG_COP0SEL_CMGCRBASE = 402;; +let _MIPS_REG_COP0SEL_COMPARE = 403;; +let _MIPS_REG_COP0SEL_CONFIG = 404;; +let _MIPS_REG_COP0SEL_CONTEXT = 405;; +let _MIPS_REG_COP0SEL_CONTEXTCONFIG = 406;; +let _MIPS_REG_COP0SEL_COUNT = 407;; +let _MIPS_REG_COP0SEL_DDATAHI = 408;; +let _MIPS_REG_COP0SEL_DDATALO = 409;; +let _MIPS_REG_COP0SEL_DEBUG = 410;; +let _MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411;; +let _MIPS_REG_COP0SEL_DEPC = 412;; +let _MIPS_REG_COP0SEL_DESAVE = 413;; +let _MIPS_REG_COP0SEL_DTAGHI = 414;; +let _MIPS_REG_COP0SEL_DTAGLO = 415;; +let _MIPS_REG_COP0SEL_EBASE = 416;; +let _MIPS_REG_COP0SEL_ENTRYHI = 417;; +let _MIPS_REG_COP0SEL_EPC = 418;; +let _MIPS_REG_COP0SEL_ERRCTL = 419;; +let _MIPS_REG_COP0SEL_ERROREPC = 420;; +let _MIPS_REG_COP0SEL_GLOBALNUMBER = 421;; +let _MIPS_REG_COP0SEL_GTOFFSET = 422;; +let _MIPS_REG_COP0SEL_HWRENA = 423;; +let _MIPS_REG_COP0SEL_IDATAHI = 424;; +let _MIPS_REG_COP0SEL_IDATALO = 425;; +let _MIPS_REG_COP0SEL_INDEX = 426;; +let _MIPS_REG_COP0SEL_INTCTL = 427;; +let _MIPS_REG_COP0SEL_ITAGHI = 428;; +let _MIPS_REG_COP0SEL_ITAGLO = 429;; +let _MIPS_REG_COP0SEL_LLADDR = 430;; +let _MIPS_REG_COP0SEL_MAAR = 431;; +let _MIPS_REG_COP0SEL_MAARI = 432;; +let _MIPS_REG_COP0SEL_MEMORYMAPID = 433;; +let _MIPS_REG_COP0SEL_MVPCONTROL = 434;; +let _MIPS_REG_COP0SEL_NESTEDEPC = 435;; +let _MIPS_REG_COP0SEL_NESTEDEXC = 436;; +let _MIPS_REG_COP0SEL_PAGEGRAIN = 437;; +let _MIPS_REG_COP0SEL_PAGEMASK = 438;; +let _MIPS_REG_COP0SEL_PRID = 439;; +let _MIPS_REG_COP0SEL_PWBASE = 440;; +let _MIPS_REG_COP0SEL_PWCTL = 441;; +let _MIPS_REG_COP0SEL_PWFIELD = 442;; +let _MIPS_REG_COP0SEL_PWSIZE = 443;; +let _MIPS_REG_COP0SEL_RANDOM = 444;; +let _MIPS_REG_COP0SEL_SRSCTL = 445;; +let _MIPS_REG_COP0SEL_SRSMAP = 446;; +let _MIPS_REG_COP0SEL_STATUS = 447;; +let _MIPS_REG_COP0SEL_TCBIND = 448;; +let _MIPS_REG_COP0SEL_TCCONTEXT = 449;; +let _MIPS_REG_COP0SEL_TCHALT = 450;; +let _MIPS_REG_COP0SEL_TCOPT = 451;; +let _MIPS_REG_COP0SEL_TCRESTART = 452;; +let _MIPS_REG_COP0SEL_TCSCHEDULE = 453;; +let _MIPS_REG_COP0SEL_TCSCHEFBACK = 454;; +let _MIPS_REG_COP0SEL_TCSTATUS = 455;; +let _MIPS_REG_COP0SEL_TRACECONTROL = 456;; +let _MIPS_REG_COP0SEL_TRACEDBPC = 457;; +let _MIPS_REG_COP0SEL_TRACEIBPC = 458;; +let _MIPS_REG_COP0SEL_USERLOCAL = 459;; +let _MIPS_REG_COP0SEL_VIEW_IPL = 460;; +let _MIPS_REG_COP0SEL_VIEW_RIPL = 461;; +let _MIPS_REG_COP0SEL_VPCONTROL = 462;; +let _MIPS_REG_COP0SEL_VPECONTROL = 463;; +let _MIPS_REG_COP0SEL_VPEOPT = 464;; +let _MIPS_REG_COP0SEL_VPESCHEDULE = 465;; +let _MIPS_REG_COP0SEL_VPESCHEFBACK = 466;; +let _MIPS_REG_COP0SEL_WIRED = 467;; +let _MIPS_REG_COP0SEL_XCONTEXT = 468;; +let _MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469;; +let _MIPS_REG_COP0SEL_YQMASK = 470;; +let _MIPS_REG_K0_NM = 471;; +let _MIPS_REG_K1_NM = 472;; +let _MIPS_REG_S0_NM = 473;; +let _MIPS_REG_S1_NM = 474;; +let _MIPS_REG_S2_NM = 475;; +let _MIPS_REG_S3_NM = 476;; +let _MIPS_REG_S4_NM = 477;; +let _MIPS_REG_S5_NM = 478;; +let _MIPS_REG_S6_NM = 479;; +let _MIPS_REG_S7_NM = 480;; +let _MIPS_REG_T0_NM = 481;; +let _MIPS_REG_T1_NM = 482;; +let _MIPS_REG_T2_NM = 483;; +let _MIPS_REG_T3_NM = 484;; +let _MIPS_REG_T4_NM = 485;; +let _MIPS_REG_T5_NM = 486;; +let _MIPS_REG_T8_NM = 487;; +let _MIPS_REG_T9_NM = 488;; +let _MIPS_REG_A0_64 = 489;; +let _MIPS_REG_A1_64 = 490;; +let _MIPS_REG_A2_64 = 491;; +let _MIPS_REG_A3_64 = 492;; +let _MIPS_REG_AC0_64 = 493;; +let _MIPS_REG_COP0SEL_CONFIG1 = 494;; +let _MIPS_REG_COP0SEL_CONFIG2 = 495;; +let _MIPS_REG_COP0SEL_CONFIG3 = 496;; +let _MIPS_REG_COP0SEL_CONFIG4 = 497;; +let _MIPS_REG_COP0SEL_CONFIG5 = 498;; +let _MIPS_REG_COP0SEL_DEBUG2 = 499;; +let _MIPS_REG_COP0SEL_ENTRYLO0 = 500;; +let _MIPS_REG_COP0SEL_ENTRYLO1 = 501;; +let _MIPS_REG_COP0SEL_GUESTCTL0 = 502;; +let _MIPS_REG_COP0SEL_GUESTCTL1 = 503;; +let _MIPS_REG_COP0SEL_GUESTCTL2 = 504;; +let _MIPS_REG_COP0SEL_GUESTCTL3 = 505;; +let _MIPS_REG_COP0SEL_KSCRATCH1 = 506;; +let _MIPS_REG_COP0SEL_KSCRATCH2 = 507;; +let _MIPS_REG_COP0SEL_KSCRATCH3 = 508;; +let _MIPS_REG_COP0SEL_KSCRATCH4 = 509;; +let _MIPS_REG_COP0SEL_KSCRATCH5 = 510;; +let _MIPS_REG_COP0SEL_KSCRATCH6 = 511;; +let _MIPS_REG_COP0SEL_MVPCONF0 = 512;; +let _MIPS_REG_COP0SEL_MVPCONF1 = 513;; +let _MIPS_REG_COP0SEL_PERFCNT0 = 514;; +let _MIPS_REG_COP0SEL_PERFCNT1 = 515;; +let _MIPS_REG_COP0SEL_PERFCNT2 = 516;; +let _MIPS_REG_COP0SEL_PERFCNT3 = 517;; +let _MIPS_REG_COP0SEL_PERFCNT4 = 518;; +let _MIPS_REG_COP0SEL_PERFCNT5 = 519;; +let _MIPS_REG_COP0SEL_PERFCNT6 = 520;; +let _MIPS_REG_COP0SEL_PERFCNT7 = 521;; +let _MIPS_REG_COP0SEL_PERFCTL0 = 522;; +let _MIPS_REG_COP0SEL_PERFCTL1 = 523;; +let _MIPS_REG_COP0SEL_PERFCTL2 = 524;; +let _MIPS_REG_COP0SEL_PERFCTL3 = 525;; +let _MIPS_REG_COP0SEL_PERFCTL4 = 526;; +let _MIPS_REG_COP0SEL_PERFCTL5 = 527;; +let _MIPS_REG_COP0SEL_PERFCTL6 = 528;; +let _MIPS_REG_COP0SEL_PERFCTL7 = 529;; +let _MIPS_REG_COP0SEL_SEGCTL0 = 530;; +let _MIPS_REG_COP0SEL_SEGCTL1 = 531;; +let _MIPS_REG_COP0SEL_SEGCTL2 = 532;; +let _MIPS_REG_COP0SEL_SRSCONF0 = 533;; +let _MIPS_REG_COP0SEL_SRSCONF1 = 534;; +let _MIPS_REG_COP0SEL_SRSCONF2 = 535;; +let _MIPS_REG_COP0SEL_SRSCONF3 = 536;; +let _MIPS_REG_COP0SEL_SRSCONF4 = 537;; +let _MIPS_REG_COP0SEL_SRSMAP2 = 538;; +let _MIPS_REG_COP0SEL_TRACECONTROL2 = 539;; +let _MIPS_REG_COP0SEL_TRACECONTROL3 = 540;; +let _MIPS_REG_COP0SEL_USERTRACEDATA1 = 541;; +let _MIPS_REG_COP0SEL_USERTRACEDATA2 = 542;; +let _MIPS_REG_COP0SEL_VPECONF0 = 543;; +let _MIPS_REG_COP0SEL_VPECONF1 = 544;; +let _MIPS_REG_COP0SEL_WATCHHI0 = 545;; +let _MIPS_REG_COP0SEL_WATCHHI1 = 546;; +let _MIPS_REG_COP0SEL_WATCHHI2 = 547;; +let _MIPS_REG_COP0SEL_WATCHHI3 = 548;; +let _MIPS_REG_COP0SEL_WATCHHI4 = 549;; +let _MIPS_REG_COP0SEL_WATCHHI5 = 550;; +let _MIPS_REG_COP0SEL_WATCHHI6 = 551;; +let _MIPS_REG_COP0SEL_WATCHHI7 = 552;; +let _MIPS_REG_COP0SEL_WATCHHI8 = 553;; +let _MIPS_REG_COP0SEL_WATCHHI9 = 554;; +let _MIPS_REG_COP0SEL_WATCHHI10 = 555;; +let _MIPS_REG_COP0SEL_WATCHHI11 = 556;; +let _MIPS_REG_COP0SEL_WATCHHI12 = 557;; +let _MIPS_REG_COP0SEL_WATCHHI13 = 558;; +let _MIPS_REG_COP0SEL_WATCHHI14 = 559;; +let _MIPS_REG_COP0SEL_WATCHHI15 = 560;; +let _MIPS_REG_COP0SEL_WATCHLO0 = 561;; +let _MIPS_REG_COP0SEL_WATCHLO1 = 562;; +let _MIPS_REG_COP0SEL_WATCHLO2 = 563;; +let _MIPS_REG_COP0SEL_WATCHLO3 = 564;; +let _MIPS_REG_COP0SEL_WATCHLO4 = 565;; +let _MIPS_REG_COP0SEL_WATCHLO5 = 566;; +let _MIPS_REG_COP0SEL_WATCHLO6 = 567;; +let _MIPS_REG_COP0SEL_WATCHLO7 = 568;; +let _MIPS_REG_COP0SEL_WATCHLO8 = 569;; +let _MIPS_REG_COP0SEL_WATCHLO9 = 570;; +let _MIPS_REG_COP0SEL_WATCHLO10 = 571;; +let _MIPS_REG_COP0SEL_WATCHLO11 = 572;; +let _MIPS_REG_COP0SEL_WATCHLO12 = 573;; +let _MIPS_REG_COP0SEL_WATCHLO13 = 574;; +let _MIPS_REG_COP0SEL_WATCHLO14 = 575;; +let _MIPS_REG_COP0SEL_WATCHLO15 = 576;; +let _MIPS_REG_D0_64 = 577;; +let _MIPS_REG_D1_64 = 578;; +let _MIPS_REG_D2_64 = 579;; +let _MIPS_REG_D3_64 = 580;; +let _MIPS_REG_D4_64 = 581;; +let _MIPS_REG_D5_64 = 582;; +let _MIPS_REG_D6_64 = 583;; +let _MIPS_REG_D7_64 = 584;; +let _MIPS_REG_D8_64 = 585;; +let _MIPS_REG_D9_64 = 586;; +let _MIPS_REG_D10_64 = 587;; +let _MIPS_REG_D11_64 = 588;; +let _MIPS_REG_D12_64 = 589;; +let _MIPS_REG_D13_64 = 590;; +let _MIPS_REG_D14_64 = 591;; +let _MIPS_REG_D15_64 = 592;; +let _MIPS_REG_D16_64 = 593;; +let _MIPS_REG_D17_64 = 594;; +let _MIPS_REG_D18_64 = 595;; +let _MIPS_REG_D19_64 = 596;; +let _MIPS_REG_D20_64 = 597;; +let _MIPS_REG_D21_64 = 598;; +let _MIPS_REG_D22_64 = 599;; +let _MIPS_REG_D23_64 = 600;; +let _MIPS_REG_D24_64 = 601;; +let _MIPS_REG_D25_64 = 602;; +let _MIPS_REG_D26_64 = 603;; +let _MIPS_REG_D27_64 = 604;; +let _MIPS_REG_D28_64 = 605;; +let _MIPS_REG_D29_64 = 606;; +let _MIPS_REG_D30_64 = 607;; +let _MIPS_REG_D31_64 = 608;; +let _MIPS_REG_DSPOUTFLAG16_19 = 609;; +let _MIPS_REG_HI0_64 = 610;; +let _MIPS_REG_K0_64 = 611;; +let _MIPS_REG_K1_64 = 612;; +let _MIPS_REG_LO0_64 = 613;; +let _MIPS_REG_S0_64 = 614;; +let _MIPS_REG_S1_64 = 615;; +let _MIPS_REG_S2_64 = 616;; +let _MIPS_REG_S3_64 = 617;; +let _MIPS_REG_S4_64 = 618;; +let _MIPS_REG_S5_64 = 619;; +let _MIPS_REG_S6_64 = 620;; +let _MIPS_REG_S7_64 = 621;; +let _MIPS_REG_T0_64 = 622;; +let _MIPS_REG_T1_64 = 623;; +let _MIPS_REG_T2_64 = 624;; +let _MIPS_REG_T3_64 = 625;; +let _MIPS_REG_T4_64 = 626;; +let _MIPS_REG_T5_64 = 627;; +let _MIPS_REG_T6_64 = 628;; +let _MIPS_REG_T7_64 = 629;; +let _MIPS_REG_T8_64 = 630;; +let _MIPS_REG_T9_64 = 631;; +let _MIPS_REG_V0_64 = 632;; +let _MIPS_REG_V1_64 = 633;; +let _MIPS_REG_COP0SEL_GUESTCTL0EXT = 634;; +let _MIPS_REG_ENDING = 635;; let _MIPS_INS_INVALID = 0;; -let _MIPS_INS_ABSQ_S = 1;; -let _MIPS_INS_ADD = 2;; -let _MIPS_INS_ADDIUPC = 3;; -let _MIPS_INS_ADDIUR1SP = 4;; -let _MIPS_INS_ADDIUR2 = 5;; -let _MIPS_INS_ADDIUS5 = 6;; -let _MIPS_INS_ADDIUSP = 7;; -let _MIPS_INS_ADDQH = 8;; -let _MIPS_INS_ADDQH_R = 9;; -let _MIPS_INS_ADDQ = 10;; -let _MIPS_INS_ADDQ_S = 11;; -let _MIPS_INS_ADDSC = 12;; -let _MIPS_INS_ADDS_A = 13;; -let _MIPS_INS_ADDS_S = 14;; -let _MIPS_INS_ADDS_U = 15;; -let _MIPS_INS_ADDU16 = 16;; -let _MIPS_INS_ADDUH = 17;; -let _MIPS_INS_ADDUH_R = 18;; -let _MIPS_INS_ADDU = 19;; -let _MIPS_INS_ADDU_S = 20;; -let _MIPS_INS_ADDVI = 21;; -let _MIPS_INS_ADDV = 22;; -let _MIPS_INS_ADDWC = 23;; -let _MIPS_INS_ADD_A = 24;; -let _MIPS_INS_ADDI = 25;; -let _MIPS_INS_ADDIU = 26;; -let _MIPS_INS_ALIGN = 27;; -let _MIPS_INS_ALUIPC = 28;; -let _MIPS_INS_AND = 29;; -let _MIPS_INS_AND16 = 30;; -let _MIPS_INS_ANDI16 = 31;; -let _MIPS_INS_ANDI = 32;; -let _MIPS_INS_APPEND = 33;; -let _MIPS_INS_ASUB_S = 34;; -let _MIPS_INS_ASUB_U = 35;; -let _MIPS_INS_AUI = 36;; -let _MIPS_INS_AUIPC = 37;; -let _MIPS_INS_AVER_S = 38;; -let _MIPS_INS_AVER_U = 39;; -let _MIPS_INS_AVE_S = 40;; -let _MIPS_INS_AVE_U = 41;; -let _MIPS_INS_B16 = 42;; -let _MIPS_INS_BADDU = 43;; -let _MIPS_INS_BAL = 44;; -let _MIPS_INS_BALC = 45;; -let _MIPS_INS_BALIGN = 46;; -let _MIPS_INS_BBIT0 = 47;; -let _MIPS_INS_BBIT032 = 48;; -let _MIPS_INS_BBIT1 = 49;; -let _MIPS_INS_BBIT132 = 50;; -let _MIPS_INS_BC = 51;; -let _MIPS_INS_BC0F = 52;; -let _MIPS_INS_BC0FL = 53;; -let _MIPS_INS_BC0T = 54;; -let _MIPS_INS_BC0TL = 55;; -let _MIPS_INS_BC1EQZ = 56;; -let _MIPS_INS_BC1F = 57;; -let _MIPS_INS_BC1FL = 58;; -let _MIPS_INS_BC1NEZ = 59;; -let _MIPS_INS_BC1T = 60;; -let _MIPS_INS_BC1TL = 61;; -let _MIPS_INS_BC2EQZ = 62;; -let _MIPS_INS_BC2F = 63;; -let _MIPS_INS_BC2FL = 64;; -let _MIPS_INS_BC2NEZ = 65;; -let _MIPS_INS_BC2T = 66;; -let _MIPS_INS_BC2TL = 67;; -let _MIPS_INS_BC3F = 68;; -let _MIPS_INS_BC3FL = 69;; -let _MIPS_INS_BC3T = 70;; -let _MIPS_INS_BC3TL = 71;; -let _MIPS_INS_BCLRI = 72;; -let _MIPS_INS_BCLR = 73;; -let _MIPS_INS_BEQ = 74;; -let _MIPS_INS_BEQC = 75;; -let _MIPS_INS_BEQL = 76;; -let _MIPS_INS_BEQZ16 = 77;; -let _MIPS_INS_BEQZALC = 78;; -let _MIPS_INS_BEQZC = 79;; -let _MIPS_INS_BGEC = 80;; -let _MIPS_INS_BGEUC = 81;; -let _MIPS_INS_BGEZ = 82;; -let _MIPS_INS_BGEZAL = 83;; -let _MIPS_INS_BGEZALC = 84;; -let _MIPS_INS_BGEZALL = 85;; -let _MIPS_INS_BGEZALS = 86;; -let _MIPS_INS_BGEZC = 87;; -let _MIPS_INS_BGEZL = 88;; -let _MIPS_INS_BGTZ = 89;; -let _MIPS_INS_BGTZALC = 90;; -let _MIPS_INS_BGTZC = 91;; -let _MIPS_INS_BGTZL = 92;; -let _MIPS_INS_BINSLI = 93;; -let _MIPS_INS_BINSL = 94;; -let _MIPS_INS_BINSRI = 95;; -let _MIPS_INS_BINSR = 96;; -let _MIPS_INS_BITREV = 97;; -let _MIPS_INS_BITSWAP = 98;; -let _MIPS_INS_BLEZ = 99;; -let _MIPS_INS_BLEZALC = 100;; -let _MIPS_INS_BLEZC = 101;; -let _MIPS_INS_BLEZL = 102;; -let _MIPS_INS_BLTC = 103;; -let _MIPS_INS_BLTUC = 104;; -let _MIPS_INS_BLTZ = 105;; -let _MIPS_INS_BLTZAL = 106;; -let _MIPS_INS_BLTZALC = 107;; -let _MIPS_INS_BLTZALL = 108;; -let _MIPS_INS_BLTZALS = 109;; -let _MIPS_INS_BLTZC = 110;; -let _MIPS_INS_BLTZL = 111;; -let _MIPS_INS_BMNZI = 112;; -let _MIPS_INS_BMNZ = 113;; -let _MIPS_INS_BMZI = 114;; -let _MIPS_INS_BMZ = 115;; -let _MIPS_INS_BNE = 116;; -let _MIPS_INS_BNEC = 117;; -let _MIPS_INS_BNEGI = 118;; -let _MIPS_INS_BNEG = 119;; -let _MIPS_INS_BNEL = 120;; -let _MIPS_INS_BNEZ16 = 121;; -let _MIPS_INS_BNEZALC = 122;; -let _MIPS_INS_BNEZC = 123;; -let _MIPS_INS_BNVC = 124;; -let _MIPS_INS_BNZ = 125;; -let _MIPS_INS_BOVC = 126;; -let _MIPS_INS_BPOSGE32 = 127;; -let _MIPS_INS_BREAK = 128;; -let _MIPS_INS_BREAK16 = 129;; -let _MIPS_INS_BSELI = 130;; -let _MIPS_INS_BSEL = 131;; -let _MIPS_INS_BSETI = 132;; -let _MIPS_INS_BSET = 133;; -let _MIPS_INS_BZ = 134;; -let _MIPS_INS_BEQZ = 135;; -let _MIPS_INS_B = 136;; -let _MIPS_INS_BNEZ = 137;; -let _MIPS_INS_BTEQZ = 138;; -let _MIPS_INS_BTNEZ = 139;; -let _MIPS_INS_CACHE = 140;; -let _MIPS_INS_CEIL = 141;; -let _MIPS_INS_CEQI = 142;; -let _MIPS_INS_CEQ = 143;; -let _MIPS_INS_CFC1 = 144;; -let _MIPS_INS_CFCMSA = 145;; -let _MIPS_INS_CINS = 146;; -let _MIPS_INS_CINS32 = 147;; -let _MIPS_INS_CLASS = 148;; -let _MIPS_INS_CLEI_S = 149;; -let _MIPS_INS_CLEI_U = 150;; -let _MIPS_INS_CLE_S = 151;; -let _MIPS_INS_CLE_U = 152;; -let _MIPS_INS_CLO = 153;; -let _MIPS_INS_CLTI_S = 154;; -let _MIPS_INS_CLTI_U = 155;; -let _MIPS_INS_CLT_S = 156;; -let _MIPS_INS_CLT_U = 157;; -let _MIPS_INS_CLZ = 158;; -let _MIPS_INS_CMPGDU = 159;; -let _MIPS_INS_CMPGU = 160;; -let _MIPS_INS_CMPU = 161;; -let _MIPS_INS_CMP = 162;; -let _MIPS_INS_COPY_S = 163;; -let _MIPS_INS_COPY_U = 164;; -let _MIPS_INS_CTC1 = 165;; -let _MIPS_INS_CTCMSA = 166;; -let _MIPS_INS_CVT = 167;; -let _MIPS_INS_C = 168;; -let _MIPS_INS_CMPI = 169;; -let _MIPS_INS_DADD = 170;; -let _MIPS_INS_DADDI = 171;; -let _MIPS_INS_DADDIU = 172;; -let _MIPS_INS_DADDU = 173;; -let _MIPS_INS_DAHI = 174;; -let _MIPS_INS_DALIGN = 175;; -let _MIPS_INS_DATI = 176;; -let _MIPS_INS_DAUI = 177;; -let _MIPS_INS_DBITSWAP = 178;; -let _MIPS_INS_DCLO = 179;; -let _MIPS_INS_DCLZ = 180;; -let _MIPS_INS_DDIV = 181;; -let _MIPS_INS_DDIVU = 182;; -let _MIPS_INS_DERET = 183;; -let _MIPS_INS_DEXT = 184;; -let _MIPS_INS_DEXTM = 185;; -let _MIPS_INS_DEXTU = 186;; -let _MIPS_INS_DI = 187;; -let _MIPS_INS_DINS = 188;; -let _MIPS_INS_DINSM = 189;; -let _MIPS_INS_DINSU = 190;; -let _MIPS_INS_DIV = 191;; -let _MIPS_INS_DIVU = 192;; -let _MIPS_INS_DIV_S = 193;; -let _MIPS_INS_DIV_U = 194;; -let _MIPS_INS_DLSA = 195;; -let _MIPS_INS_DMFC0 = 196;; -let _MIPS_INS_DMFC1 = 197;; -let _MIPS_INS_DMFC2 = 198;; -let _MIPS_INS_DMOD = 199;; -let _MIPS_INS_DMODU = 200;; -let _MIPS_INS_DMTC0 = 201;; -let _MIPS_INS_DMTC1 = 202;; -let _MIPS_INS_DMTC2 = 203;; -let _MIPS_INS_DMUH = 204;; -let _MIPS_INS_DMUHU = 205;; -let _MIPS_INS_DMUL = 206;; -let _MIPS_INS_DMULT = 207;; -let _MIPS_INS_DMULTU = 208;; -let _MIPS_INS_DMULU = 209;; -let _MIPS_INS_DOTP_S = 210;; -let _MIPS_INS_DOTP_U = 211;; -let _MIPS_INS_DPADD_S = 212;; -let _MIPS_INS_DPADD_U = 213;; -let _MIPS_INS_DPAQX_SA = 214;; -let _MIPS_INS_DPAQX_S = 215;; -let _MIPS_INS_DPAQ_SA = 216;; -let _MIPS_INS_DPAQ_S = 217;; -let _MIPS_INS_DPAU = 218;; -let _MIPS_INS_DPAX = 219;; -let _MIPS_INS_DPA = 220;; -let _MIPS_INS_DPOP = 221;; -let _MIPS_INS_DPSQX_SA = 222;; -let _MIPS_INS_DPSQX_S = 223;; -let _MIPS_INS_DPSQ_SA = 224;; -let _MIPS_INS_DPSQ_S = 225;; -let _MIPS_INS_DPSUB_S = 226;; -let _MIPS_INS_DPSUB_U = 227;; -let _MIPS_INS_DPSU = 228;; -let _MIPS_INS_DPSX = 229;; -let _MIPS_INS_DPS = 230;; -let _MIPS_INS_DROTR = 231;; -let _MIPS_INS_DROTR32 = 232;; -let _MIPS_INS_DROTRV = 233;; -let _MIPS_INS_DSBH = 234;; -let _MIPS_INS_DSHD = 235;; -let _MIPS_INS_DSLL = 236;; -let _MIPS_INS_DSLL32 = 237;; -let _MIPS_INS_DSLLV = 238;; -let _MIPS_INS_DSRA = 239;; -let _MIPS_INS_DSRA32 = 240;; -let _MIPS_INS_DSRAV = 241;; -let _MIPS_INS_DSRL = 242;; -let _MIPS_INS_DSRL32 = 243;; -let _MIPS_INS_DSRLV = 244;; -let _MIPS_INS_DSUB = 245;; -let _MIPS_INS_DSUBU = 246;; -let _MIPS_INS_EHB = 247;; -let _MIPS_INS_EI = 248;; -let _MIPS_INS_ERET = 249;; -let _MIPS_INS_EXT = 250;; -let _MIPS_INS_EXTP = 251;; -let _MIPS_INS_EXTPDP = 252;; -let _MIPS_INS_EXTPDPV = 253;; -let _MIPS_INS_EXTPV = 254;; -let _MIPS_INS_EXTRV_RS = 255;; -let _MIPS_INS_EXTRV_R = 256;; -let _MIPS_INS_EXTRV_S = 257;; -let _MIPS_INS_EXTRV = 258;; -let _MIPS_INS_EXTR_RS = 259;; -let _MIPS_INS_EXTR_R = 260;; -let _MIPS_INS_EXTR_S = 261;; -let _MIPS_INS_EXTR = 262;; -let _MIPS_INS_EXTS = 263;; -let _MIPS_INS_EXTS32 = 264;; -let _MIPS_INS_ABS = 265;; -let _MIPS_INS_FADD = 266;; -let _MIPS_INS_FCAF = 267;; -let _MIPS_INS_FCEQ = 268;; -let _MIPS_INS_FCLASS = 269;; -let _MIPS_INS_FCLE = 270;; -let _MIPS_INS_FCLT = 271;; -let _MIPS_INS_FCNE = 272;; -let _MIPS_INS_FCOR = 273;; -let _MIPS_INS_FCUEQ = 274;; -let _MIPS_INS_FCULE = 275;; -let _MIPS_INS_FCULT = 276;; -let _MIPS_INS_FCUNE = 277;; -let _MIPS_INS_FCUN = 278;; -let _MIPS_INS_FDIV = 279;; -let _MIPS_INS_FEXDO = 280;; -let _MIPS_INS_FEXP2 = 281;; -let _MIPS_INS_FEXUPL = 282;; -let _MIPS_INS_FEXUPR = 283;; -let _MIPS_INS_FFINT_S = 284;; -let _MIPS_INS_FFINT_U = 285;; -let _MIPS_INS_FFQL = 286;; -let _MIPS_INS_FFQR = 287;; -let _MIPS_INS_FILL = 288;; -let _MIPS_INS_FLOG2 = 289;; -let _MIPS_INS_FLOOR = 290;; -let _MIPS_INS_FMADD = 291;; -let _MIPS_INS_FMAX_A = 292;; -let _MIPS_INS_FMAX = 293;; -let _MIPS_INS_FMIN_A = 294;; -let _MIPS_INS_FMIN = 295;; -let _MIPS_INS_MOV = 296;; -let _MIPS_INS_FMSUB = 297;; -let _MIPS_INS_FMUL = 298;; -let _MIPS_INS_MUL = 299;; -let _MIPS_INS_NEG = 300;; -let _MIPS_INS_FRCP = 301;; -let _MIPS_INS_FRINT = 302;; -let _MIPS_INS_FRSQRT = 303;; -let _MIPS_INS_FSAF = 304;; -let _MIPS_INS_FSEQ = 305;; -let _MIPS_INS_FSLE = 306;; -let _MIPS_INS_FSLT = 307;; -let _MIPS_INS_FSNE = 308;; -let _MIPS_INS_FSOR = 309;; -let _MIPS_INS_FSQRT = 310;; -let _MIPS_INS_SQRT = 311;; -let _MIPS_INS_FSUB = 312;; -let _MIPS_INS_SUB = 313;; -let _MIPS_INS_FSUEQ = 314;; -let _MIPS_INS_FSULE = 315;; -let _MIPS_INS_FSULT = 316;; -let _MIPS_INS_FSUNE = 317;; -let _MIPS_INS_FSUN = 318;; -let _MIPS_INS_FTINT_S = 319;; -let _MIPS_INS_FTINT_U = 320;; -let _MIPS_INS_FTQ = 321;; -let _MIPS_INS_FTRUNC_S = 322;; -let _MIPS_INS_FTRUNC_U = 323;; -let _MIPS_INS_HADD_S = 324;; -let _MIPS_INS_HADD_U = 325;; -let _MIPS_INS_HSUB_S = 326;; -let _MIPS_INS_HSUB_U = 327;; -let _MIPS_INS_ILVEV = 328;; -let _MIPS_INS_ILVL = 329;; -let _MIPS_INS_ILVOD = 330;; -let _MIPS_INS_ILVR = 331;; -let _MIPS_INS_INS = 332;; -let _MIPS_INS_INSERT = 333;; -let _MIPS_INS_INSV = 334;; -let _MIPS_INS_INSVE = 335;; -let _MIPS_INS_J = 336;; -let _MIPS_INS_JAL = 337;; -let _MIPS_INS_JALR = 338;; -let _MIPS_INS_JALRS16 = 339;; -let _MIPS_INS_JALRS = 340;; -let _MIPS_INS_JALS = 341;; -let _MIPS_INS_JALX = 342;; -let _MIPS_INS_JIALC = 343;; -let _MIPS_INS_JIC = 344;; -let _MIPS_INS_JR = 345;; -let _MIPS_INS_JR16 = 346;; -let _MIPS_INS_JRADDIUSP = 347;; -let _MIPS_INS_JRC = 348;; -let _MIPS_INS_JALRC = 349;; -let _MIPS_INS_LB = 350;; -let _MIPS_INS_LBU16 = 351;; -let _MIPS_INS_LBUX = 352;; -let _MIPS_INS_LBU = 353;; -let _MIPS_INS_LD = 354;; -let _MIPS_INS_LDC1 = 355;; -let _MIPS_INS_LDC2 = 356;; -let _MIPS_INS_LDC3 = 357;; -let _MIPS_INS_LDI = 358;; -let _MIPS_INS_LDL = 359;; -let _MIPS_INS_LDPC = 360;; -let _MIPS_INS_LDR = 361;; -let _MIPS_INS_LDXC1 = 362;; -let _MIPS_INS_LH = 363;; -let _MIPS_INS_LHU16 = 364;; -let _MIPS_INS_LHX = 365;; -let _MIPS_INS_LHU = 366;; -let _MIPS_INS_LI16 = 367;; -let _MIPS_INS_LL = 368;; -let _MIPS_INS_LLD = 369;; -let _MIPS_INS_LSA = 370;; -let _MIPS_INS_LUXC1 = 371;; -let _MIPS_INS_LUI = 372;; -let _MIPS_INS_LW = 373;; -let _MIPS_INS_LW16 = 374;; -let _MIPS_INS_LWC1 = 375;; -let _MIPS_INS_LWC2 = 376;; -let _MIPS_INS_LWC3 = 377;; -let _MIPS_INS_LWL = 378;; -let _MIPS_INS_LWM16 = 379;; -let _MIPS_INS_LWM32 = 380;; -let _MIPS_INS_LWPC = 381;; -let _MIPS_INS_LWP = 382;; -let _MIPS_INS_LWR = 383;; -let _MIPS_INS_LWUPC = 384;; -let _MIPS_INS_LWU = 385;; -let _MIPS_INS_LWX = 386;; -let _MIPS_INS_LWXC1 = 387;; -let _MIPS_INS_LWXS = 388;; -let _MIPS_INS_LI = 389;; -let _MIPS_INS_MADD = 390;; -let _MIPS_INS_MADDF = 391;; -let _MIPS_INS_MADDR_Q = 392;; -let _MIPS_INS_MADDU = 393;; -let _MIPS_INS_MADDV = 394;; -let _MIPS_INS_MADD_Q = 395;; -let _MIPS_INS_MAQ_SA = 396;; -let _MIPS_INS_MAQ_S = 397;; -let _MIPS_INS_MAXA = 398;; -let _MIPS_INS_MAXI_S = 399;; -let _MIPS_INS_MAXI_U = 400;; -let _MIPS_INS_MAX_A = 401;; -let _MIPS_INS_MAX = 402;; -let _MIPS_INS_MAX_S = 403;; -let _MIPS_INS_MAX_U = 404;; -let _MIPS_INS_MFC0 = 405;; -let _MIPS_INS_MFC1 = 406;; -let _MIPS_INS_MFC2 = 407;; -let _MIPS_INS_MFHC1 = 408;; -let _MIPS_INS_MFHI = 409;; -let _MIPS_INS_MFLO = 410;; -let _MIPS_INS_MINA = 411;; -let _MIPS_INS_MINI_S = 412;; -let _MIPS_INS_MINI_U = 413;; -let _MIPS_INS_MIN_A = 414;; -let _MIPS_INS_MIN = 415;; -let _MIPS_INS_MIN_S = 416;; -let _MIPS_INS_MIN_U = 417;; -let _MIPS_INS_MOD = 418;; -let _MIPS_INS_MODSUB = 419;; -let _MIPS_INS_MODU = 420;; -let _MIPS_INS_MOD_S = 421;; -let _MIPS_INS_MOD_U = 422;; -let _MIPS_INS_MOVE = 423;; -let _MIPS_INS_MOVEP = 424;; -let _MIPS_INS_MOVF = 425;; -let _MIPS_INS_MOVN = 426;; -let _MIPS_INS_MOVT = 427;; -let _MIPS_INS_MOVZ = 428;; -let _MIPS_INS_MSUB = 429;; -let _MIPS_INS_MSUBF = 430;; -let _MIPS_INS_MSUBR_Q = 431;; -let _MIPS_INS_MSUBU = 432;; -let _MIPS_INS_MSUBV = 433;; -let _MIPS_INS_MSUB_Q = 434;; -let _MIPS_INS_MTC0 = 435;; -let _MIPS_INS_MTC1 = 436;; -let _MIPS_INS_MTC2 = 437;; -let _MIPS_INS_MTHC1 = 438;; -let _MIPS_INS_MTHI = 439;; -let _MIPS_INS_MTHLIP = 440;; -let _MIPS_INS_MTLO = 441;; -let _MIPS_INS_MTM0 = 442;; -let _MIPS_INS_MTM1 = 443;; -let _MIPS_INS_MTM2 = 444;; -let _MIPS_INS_MTP0 = 445;; -let _MIPS_INS_MTP1 = 446;; -let _MIPS_INS_MTP2 = 447;; -let _MIPS_INS_MUH = 448;; -let _MIPS_INS_MUHU = 449;; -let _MIPS_INS_MULEQ_S = 450;; -let _MIPS_INS_MULEU_S = 451;; -let _MIPS_INS_MULQ_RS = 452;; -let _MIPS_INS_MULQ_S = 453;; -let _MIPS_INS_MULR_Q = 454;; -let _MIPS_INS_MULSAQ_S = 455;; -let _MIPS_INS_MULSA = 456;; -let _MIPS_INS_MULT = 457;; -let _MIPS_INS_MULTU = 458;; -let _MIPS_INS_MULU = 459;; -let _MIPS_INS_MULV = 460;; -let _MIPS_INS_MUL_Q = 461;; -let _MIPS_INS_MUL_S = 462;; -let _MIPS_INS_NLOC = 463;; -let _MIPS_INS_NLZC = 464;; -let _MIPS_INS_NMADD = 465;; -let _MIPS_INS_NMSUB = 466;; -let _MIPS_INS_NOR = 467;; -let _MIPS_INS_NORI = 468;; -let _MIPS_INS_NOT16 = 469;; -let _MIPS_INS_NOT = 470;; -let _MIPS_INS_OR = 471;; -let _MIPS_INS_OR16 = 472;; -let _MIPS_INS_ORI = 473;; -let _MIPS_INS_PACKRL = 474;; -let _MIPS_INS_PAUSE = 475;; -let _MIPS_INS_PCKEV = 476;; -let _MIPS_INS_PCKOD = 477;; -let _MIPS_INS_PCNT = 478;; -let _MIPS_INS_PICK = 479;; -let _MIPS_INS_POP = 480;; -let _MIPS_INS_PRECEQU = 481;; -let _MIPS_INS_PRECEQ = 482;; -let _MIPS_INS_PRECEU = 483;; -let _MIPS_INS_PRECRQU_S = 484;; -let _MIPS_INS_PRECRQ = 485;; -let _MIPS_INS_PRECRQ_RS = 486;; -let _MIPS_INS_PRECR = 487;; -let _MIPS_INS_PRECR_SRA = 488;; -let _MIPS_INS_PRECR_SRA_R = 489;; -let _MIPS_INS_PREF = 490;; -let _MIPS_INS_PREPEND = 491;; -let _MIPS_INS_RADDU = 492;; -let _MIPS_INS_RDDSP = 493;; -let _MIPS_INS_RDHWR = 494;; -let _MIPS_INS_REPLV = 495;; -let _MIPS_INS_REPL = 496;; -let _MIPS_INS_RINT = 497;; -let _MIPS_INS_ROTR = 498;; -let _MIPS_INS_ROTRV = 499;; -let _MIPS_INS_ROUND = 500;; -let _MIPS_INS_SAT_S = 501;; -let _MIPS_INS_SAT_U = 502;; -let _MIPS_INS_SB = 503;; -let _MIPS_INS_SB16 = 504;; -let _MIPS_INS_SC = 505;; -let _MIPS_INS_SCD = 506;; -let _MIPS_INS_SD = 507;; -let _MIPS_INS_SDBBP = 508;; -let _MIPS_INS_SDBBP16 = 509;; -let _MIPS_INS_SDC1 = 510;; -let _MIPS_INS_SDC2 = 511;; -let _MIPS_INS_SDC3 = 512;; -let _MIPS_INS_SDL = 513;; -let _MIPS_INS_SDR = 514;; -let _MIPS_INS_SDXC1 = 515;; -let _MIPS_INS_SEB = 516;; -let _MIPS_INS_SEH = 517;; -let _MIPS_INS_SELEQZ = 518;; -let _MIPS_INS_SELNEZ = 519;; -let _MIPS_INS_SEL = 520;; -let _MIPS_INS_SEQ = 521;; -let _MIPS_INS_SEQI = 522;; -let _MIPS_INS_SH = 523;; -let _MIPS_INS_SH16 = 524;; -let _MIPS_INS_SHF = 525;; -let _MIPS_INS_SHILO = 526;; -let _MIPS_INS_SHILOV = 527;; -let _MIPS_INS_SHLLV = 528;; -let _MIPS_INS_SHLLV_S = 529;; -let _MIPS_INS_SHLL = 530;; -let _MIPS_INS_SHLL_S = 531;; -let _MIPS_INS_SHRAV = 532;; -let _MIPS_INS_SHRAV_R = 533;; -let _MIPS_INS_SHRA = 534;; -let _MIPS_INS_SHRA_R = 535;; -let _MIPS_INS_SHRLV = 536;; -let _MIPS_INS_SHRL = 537;; -let _MIPS_INS_SLDI = 538;; -let _MIPS_INS_SLD = 539;; -let _MIPS_INS_SLL = 540;; -let _MIPS_INS_SLL16 = 541;; -let _MIPS_INS_SLLI = 542;; -let _MIPS_INS_SLLV = 543;; -let _MIPS_INS_SLT = 544;; -let _MIPS_INS_SLTI = 545;; -let _MIPS_INS_SLTIU = 546;; -let _MIPS_INS_SLTU = 547;; -let _MIPS_INS_SNE = 548;; -let _MIPS_INS_SNEI = 549;; -let _MIPS_INS_SPLATI = 550;; -let _MIPS_INS_SPLAT = 551;; -let _MIPS_INS_SRA = 552;; -let _MIPS_INS_SRAI = 553;; -let _MIPS_INS_SRARI = 554;; -let _MIPS_INS_SRAR = 555;; -let _MIPS_INS_SRAV = 556;; -let _MIPS_INS_SRL = 557;; -let _MIPS_INS_SRL16 = 558;; -let _MIPS_INS_SRLI = 559;; -let _MIPS_INS_SRLRI = 560;; -let _MIPS_INS_SRLR = 561;; -let _MIPS_INS_SRLV = 562;; -let _MIPS_INS_SSNOP = 563;; -let _MIPS_INS_ST = 564;; -let _MIPS_INS_SUBQH = 565;; -let _MIPS_INS_SUBQH_R = 566;; -let _MIPS_INS_SUBQ = 567;; -let _MIPS_INS_SUBQ_S = 568;; -let _MIPS_INS_SUBSUS_U = 569;; -let _MIPS_INS_SUBSUU_S = 570;; -let _MIPS_INS_SUBS_S = 571;; -let _MIPS_INS_SUBS_U = 572;; -let _MIPS_INS_SUBU16 = 573;; -let _MIPS_INS_SUBUH = 574;; -let _MIPS_INS_SUBUH_R = 575;; -let _MIPS_INS_SUBU = 576;; -let _MIPS_INS_SUBU_S = 577;; -let _MIPS_INS_SUBVI = 578;; -let _MIPS_INS_SUBV = 579;; -let _MIPS_INS_SUXC1 = 580;; -let _MIPS_INS_SW = 581;; -let _MIPS_INS_SW16 = 582;; -let _MIPS_INS_SWC1 = 583;; -let _MIPS_INS_SWC2 = 584;; -let _MIPS_INS_SWC3 = 585;; -let _MIPS_INS_SWL = 586;; -let _MIPS_INS_SWM16 = 587;; -let _MIPS_INS_SWM32 = 588;; -let _MIPS_INS_SWP = 589;; -let _MIPS_INS_SWR = 590;; -let _MIPS_INS_SWXC1 = 591;; -let _MIPS_INS_SYNC = 592;; -let _MIPS_INS_SYNCI = 593;; -let _MIPS_INS_SYSCALL = 594;; -let _MIPS_INS_TEQ = 595;; -let _MIPS_INS_TEQI = 596;; -let _MIPS_INS_TGE = 597;; -let _MIPS_INS_TGEI = 598;; -let _MIPS_INS_TGEIU = 599;; -let _MIPS_INS_TGEU = 600;; -let _MIPS_INS_TLBP = 601;; -let _MIPS_INS_TLBR = 602;; -let _MIPS_INS_TLBWI = 603;; -let _MIPS_INS_TLBWR = 604;; -let _MIPS_INS_TLT = 605;; -let _MIPS_INS_TLTI = 606;; -let _MIPS_INS_TLTIU = 607;; -let _MIPS_INS_TLTU = 608;; -let _MIPS_INS_TNE = 609;; -let _MIPS_INS_TNEI = 610;; -let _MIPS_INS_TRUNC = 611;; -let _MIPS_INS_V3MULU = 612;; -let _MIPS_INS_VMM0 = 613;; -let _MIPS_INS_VMULU = 614;; -let _MIPS_INS_VSHF = 615;; -let _MIPS_INS_WAIT = 616;; -let _MIPS_INS_WRDSP = 617;; -let _MIPS_INS_WSBH = 618;; -let _MIPS_INS_XOR = 619;; -let _MIPS_INS_XOR16 = 620;; -let _MIPS_INS_XORI = 621;; - -(* some alias instructions *) -let _MIPS_INS_NOP = 622;; -let _MIPS_INS_NEGU = 623;; - -(* special instructions *) -let _MIPS_INS_JALR_HB = 624;; -let _MIPS_INS_JR_HB = 625;; -let _MIPS_INS_ENDING = 626;; +let _MIPS_INS_ABS = 1;; +let _MIPS_INS_ALIGN = 2;; +let _MIPS_INS_BEQL = 3;; +let _MIPS_INS_BGE = 4;; +let _MIPS_INS_BGEL = 5;; +let _MIPS_INS_BGEU = 6;; +let _MIPS_INS_BGEUL = 7;; +let _MIPS_INS_BGT = 8;; +let _MIPS_INS_BGTL = 9;; +let _MIPS_INS_BGTU = 10;; +let _MIPS_INS_BGTUL = 11;; +let _MIPS_INS_BLE = 12;; +let _MIPS_INS_BLEL = 13;; +let _MIPS_INS_BLEU = 14;; +let _MIPS_INS_BLEUL = 15;; +let _MIPS_INS_BLT = 16;; +let _MIPS_INS_BLTL = 17;; +let _MIPS_INS_BLTU = 18;; +let _MIPS_INS_BLTUL = 19;; +let _MIPS_INS_BNEL = 20;; +let _MIPS_INS_B = 21;; +let _MIPS_INS_BEQ = 22;; +let _MIPS_INS_BNE = 23;; +let _MIPS_INS_CFTC1 = 24;; +let _MIPS_INS_CTTC1 = 25;; +let _MIPS_INS_DMUL = 26;; +let _MIPS_INS_DMULO = 27;; +let _MIPS_INS_DMULOU = 28;; +let _MIPS_INS_DROL = 29;; +let _MIPS_INS_DROR = 30;; +let _MIPS_INS_DDIV = 31;; +let _MIPS_INS_DREM = 32;; +let _MIPS_INS_DDIVU = 33;; +let _MIPS_INS_DREMU = 34;; +let _MIPS_INS_JAL = 35;; +let _MIPS_INS_LD = 36;; +let _MIPS_INS_LWM = 37;; +let _MIPS_INS_LA = 38;; +let _MIPS_INS_DLA = 39;; +let _MIPS_INS_LI = 40;; +let _MIPS_INS_DLI = 41;; +let _MIPS_INS_LI_D = 42;; +let _MIPS_INS_LI_S = 43;; +let _MIPS_INS_MFTACX = 44;; +let _MIPS_INS_MFTC0 = 45;; +let _MIPS_INS_MFTC1 = 46;; +let _MIPS_INS_MFTDSP = 47;; +let _MIPS_INS_MFTGPR = 48;; +let _MIPS_INS_MFTHC1 = 49;; +let _MIPS_INS_MFTHI = 50;; +let _MIPS_INS_MFTLO = 51;; +let _MIPS_INS_MTTACX = 52;; +let _MIPS_INS_MTTC0 = 53;; +let _MIPS_INS_MTTC1 = 54;; +let _MIPS_INS_MTTDSP = 55;; +let _MIPS_INS_MTTGPR = 56;; +let _MIPS_INS_MTTHC1 = 57;; +let _MIPS_INS_MTTHI = 58;; +let _MIPS_INS_MTTLO = 59;; +let _MIPS_INS_MUL = 60;; +let _MIPS_INS_MULO = 61;; +let _MIPS_INS_MULOU = 62;; +let _MIPS_INS_NOR = 63;; +let _MIPS_INS_ADDIU = 64;; +let _MIPS_INS_ANDI = 65;; +let _MIPS_INS_SUBU = 66;; +let _MIPS_INS_TRUNC_W_D = 67;; +let _MIPS_INS_TRUNC_W_S = 68;; +let _MIPS_INS_ROL = 69;; +let _MIPS_INS_ROR = 70;; +let _MIPS_INS_S_D = 71;; +let _MIPS_INS_SD = 72;; +let _MIPS_INS_DIV = 73;; +let _MIPS_INS_SEQ = 74;; +let _MIPS_INS_SGE = 75;; +let _MIPS_INS_SGEU = 76;; +let _MIPS_INS_SGT = 77;; +let _MIPS_INS_SGTU = 78;; +let _MIPS_INS_SLE = 79;; +let _MIPS_INS_SLEU = 80;; +let _MIPS_INS_SLT = 81;; +let _MIPS_INS_SLTU = 82;; +let _MIPS_INS_SNE = 83;; +let _MIPS_INS_REM = 84;; +let _MIPS_INS_SWM = 85;; +let _MIPS_INS_SAA = 86;; +let _MIPS_INS_SAAD = 87;; +let _MIPS_INS_DIVU = 88;; +let _MIPS_INS_REMU = 89;; +let _MIPS_INS_ULH = 90;; +let _MIPS_INS_ULHU = 91;; +let _MIPS_INS_ULW = 92;; +let _MIPS_INS_USH = 93;; +let _MIPS_INS_USW = 94;; +let _MIPS_INS_ABSQ_S_PH = 95;; +let _MIPS_INS_ABSQ_S_QB = 96;; +let _MIPS_INS_ABSQ_S_W = 97;; +let _MIPS_INS_ADD = 98;; +let _MIPS_INS_ADDIUPC = 99;; +let _MIPS_INS_ADDIUR1SP = 100;; +let _MIPS_INS_ADDIUR2 = 101;; +let _MIPS_INS_ADDIUS5 = 102;; +let _MIPS_INS_ADDIUSP = 103;; +let _MIPS_INS_ADDQH_PH = 104;; +let _MIPS_INS_ADDQH_R_PH = 105;; +let _MIPS_INS_ADDQH_R_W = 106;; +let _MIPS_INS_ADDQH_W = 107;; +let _MIPS_INS_ADDQ_PH = 108;; +let _MIPS_INS_ADDQ_S_PH = 109;; +let _MIPS_INS_ADDQ_S_W = 110;; +let _MIPS_INS_ADDR_PS = 111;; +let _MIPS_INS_ADDSC = 112;; +let _MIPS_INS_ADDS_A_B = 113;; +let _MIPS_INS_ADDS_A_D = 114;; +let _MIPS_INS_ADDS_A_H = 115;; +let _MIPS_INS_ADDS_A_W = 116;; +let _MIPS_INS_ADDS_S_B = 117;; +let _MIPS_INS_ADDS_S_D = 118;; +let _MIPS_INS_ADDS_S_H = 119;; +let _MIPS_INS_ADDS_S_W = 120;; +let _MIPS_INS_ADDS_U_B = 121;; +let _MIPS_INS_ADDS_U_D = 122;; +let _MIPS_INS_ADDS_U_H = 123;; +let _MIPS_INS_ADDS_U_W = 124;; +let _MIPS_INS_ADDU16 = 125;; +let _MIPS_INS_ADDUH_QB = 126;; +let _MIPS_INS_ADDUH_R_QB = 127;; +let _MIPS_INS_ADDU = 128;; +let _MIPS_INS_ADDU_PH = 129;; +let _MIPS_INS_ADDU_QB = 130;; +let _MIPS_INS_ADDU_S_PH = 131;; +let _MIPS_INS_ADDU_S_QB = 132;; +let _MIPS_INS_ADDVI_B = 133;; +let _MIPS_INS_ADDVI_D = 134;; +let _MIPS_INS_ADDVI_H = 135;; +let _MIPS_INS_ADDVI_W = 136;; +let _MIPS_INS_ADDV_B = 137;; +let _MIPS_INS_ADDV_D = 138;; +let _MIPS_INS_ADDV_H = 139;; +let _MIPS_INS_ADDV_W = 140;; +let _MIPS_INS_ADDWC = 141;; +let _MIPS_INS_ADD_A_B = 142;; +let _MIPS_INS_ADD_A_D = 143;; +let _MIPS_INS_ADD_A_H = 144;; +let _MIPS_INS_ADD_A_W = 145;; +let _MIPS_INS_ADDI = 146;; +let _MIPS_INS_ALUIPC = 147;; +let _MIPS_INS_AND = 148;; +let _MIPS_INS_AND16 = 149;; +let _MIPS_INS_ANDI16 = 150;; +let _MIPS_INS_ANDI_B = 151;; +let _MIPS_INS_AND_V = 152;; +let _MIPS_INS_APPEND = 153;; +let _MIPS_INS_ASUB_S_B = 154;; +let _MIPS_INS_ASUB_S_D = 155;; +let _MIPS_INS_ASUB_S_H = 156;; +let _MIPS_INS_ASUB_S_W = 157;; +let _MIPS_INS_ASUB_U_B = 158;; +let _MIPS_INS_ASUB_U_D = 159;; +let _MIPS_INS_ASUB_U_H = 160;; +let _MIPS_INS_ASUB_U_W = 161;; +let _MIPS_INS_AUI = 162;; +let _MIPS_INS_AUIPC = 163;; +let _MIPS_INS_AVER_S_B = 164;; +let _MIPS_INS_AVER_S_D = 165;; +let _MIPS_INS_AVER_S_H = 166;; +let _MIPS_INS_AVER_S_W = 167;; +let _MIPS_INS_AVER_U_B = 168;; +let _MIPS_INS_AVER_U_D = 169;; +let _MIPS_INS_AVER_U_H = 170;; +let _MIPS_INS_AVER_U_W = 171;; +let _MIPS_INS_AVE_S_B = 172;; +let _MIPS_INS_AVE_S_D = 173;; +let _MIPS_INS_AVE_S_H = 174;; +let _MIPS_INS_AVE_S_W = 175;; +let _MIPS_INS_AVE_U_B = 176;; +let _MIPS_INS_AVE_U_D = 177;; +let _MIPS_INS_AVE_U_H = 178;; +let _MIPS_INS_AVE_U_W = 179;; +let _MIPS_INS_B16 = 180;; +let _MIPS_INS_BADDU = 181;; +let _MIPS_INS_BAL = 182;; +let _MIPS_INS_BALC = 183;; +let _MIPS_INS_BALIGN = 184;; +let _MIPS_INS_BALRSC = 185;; +let _MIPS_INS_BBEQZC = 186;; +let _MIPS_INS_BBIT0 = 187;; +let _MIPS_INS_BBIT032 = 188;; +let _MIPS_INS_BBIT1 = 189;; +let _MIPS_INS_BBIT132 = 190;; +let _MIPS_INS_BBNEZC = 191;; +let _MIPS_INS_BC = 192;; +let _MIPS_INS_BC16 = 193;; +let _MIPS_INS_BC1EQZ = 194;; +let _MIPS_INS_BC1EQZC = 195;; +let _MIPS_INS_BC1F = 196;; +let _MIPS_INS_BC1FL = 197;; +let _MIPS_INS_BC1NEZ = 198;; +let _MIPS_INS_BC1NEZC = 199;; +let _MIPS_INS_BC1T = 200;; +let _MIPS_INS_BC1TL = 201;; +let _MIPS_INS_BC2EQZ = 202;; +let _MIPS_INS_BC2EQZC = 203;; +let _MIPS_INS_BC2NEZ = 204;; +let _MIPS_INS_BC2NEZC = 205;; +let _MIPS_INS_BCLRI_B = 206;; +let _MIPS_INS_BCLRI_D = 207;; +let _MIPS_INS_BCLRI_H = 208;; +let _MIPS_INS_BCLRI_W = 209;; +let _MIPS_INS_BCLR_B = 210;; +let _MIPS_INS_BCLR_D = 211;; +let _MIPS_INS_BCLR_H = 212;; +let _MIPS_INS_BCLR_W = 213;; +let _MIPS_INS_BEQC = 214;; +let _MIPS_INS_BEQIC = 215;; +let _MIPS_INS_BEQZ16 = 216;; +let _MIPS_INS_BEQZALC = 217;; +let _MIPS_INS_BEQZC = 218;; +let _MIPS_INS_BEQZC16 = 219;; +let _MIPS_INS_BGEC = 220;; +let _MIPS_INS_BGEIC = 221;; +let _MIPS_INS_BGEIUC = 222;; +let _MIPS_INS_BGEUC = 223;; +let _MIPS_INS_BGEZ = 224;; +let _MIPS_INS_BGEZAL = 225;; +let _MIPS_INS_BGEZALC = 226;; +let _MIPS_INS_BGEZALL = 227;; +let _MIPS_INS_BGEZALS = 228;; +let _MIPS_INS_BGEZC = 229;; +let _MIPS_INS_BGEZL = 230;; +let _MIPS_INS_BGTZ = 231;; +let _MIPS_INS_BGTZALC = 232;; +let _MIPS_INS_BGTZC = 233;; +let _MIPS_INS_BGTZL = 234;; +let _MIPS_INS_BINSLI_B = 235;; +let _MIPS_INS_BINSLI_D = 236;; +let _MIPS_INS_BINSLI_H = 237;; +let _MIPS_INS_BINSLI_W = 238;; +let _MIPS_INS_BINSL_B = 239;; +let _MIPS_INS_BINSL_D = 240;; +let _MIPS_INS_BINSL_H = 241;; +let _MIPS_INS_BINSL_W = 242;; +let _MIPS_INS_BINSRI_B = 243;; +let _MIPS_INS_BINSRI_D = 244;; +let _MIPS_INS_BINSRI_H = 245;; +let _MIPS_INS_BINSRI_W = 246;; +let _MIPS_INS_BINSR_B = 247;; +let _MIPS_INS_BINSR_D = 248;; +let _MIPS_INS_BINSR_H = 249;; +let _MIPS_INS_BINSR_W = 250;; +let _MIPS_INS_BITREV = 251;; +let _MIPS_INS_BITREVW = 252;; +let _MIPS_INS_BITSWAP = 253;; +let _MIPS_INS_BLEZ = 254;; +let _MIPS_INS_BLEZALC = 255;; +let _MIPS_INS_BLEZC = 256;; +let _MIPS_INS_BLEZL = 257;; +let _MIPS_INS_BLTC = 258;; +let _MIPS_INS_BLTIC = 259;; +let _MIPS_INS_BLTIUC = 260;; +let _MIPS_INS_BLTUC = 261;; +let _MIPS_INS_BLTZ = 262;; +let _MIPS_INS_BLTZAL = 263;; +let _MIPS_INS_BLTZALC = 264;; +let _MIPS_INS_BLTZALL = 265;; +let _MIPS_INS_BLTZALS = 266;; +let _MIPS_INS_BLTZC = 267;; +let _MIPS_INS_BLTZL = 268;; +let _MIPS_INS_BMNZI_B = 269;; +let _MIPS_INS_BMNZ_V = 270;; +let _MIPS_INS_BMZI_B = 271;; +let _MIPS_INS_BMZ_V = 272;; +let _MIPS_INS_BNEC = 273;; +let _MIPS_INS_BNEGI_B = 274;; +let _MIPS_INS_BNEGI_D = 275;; +let _MIPS_INS_BNEGI_H = 276;; +let _MIPS_INS_BNEGI_W = 277;; +let _MIPS_INS_BNEG_B = 278;; +let _MIPS_INS_BNEG_D = 279;; +let _MIPS_INS_BNEG_H = 280;; +let _MIPS_INS_BNEG_W = 281;; +let _MIPS_INS_BNEIC = 282;; +let _MIPS_INS_BNEZ16 = 283;; +let _MIPS_INS_BNEZALC = 284;; +let _MIPS_INS_BNEZC = 285;; +let _MIPS_INS_BNEZC16 = 286;; +let _MIPS_INS_BNVC = 287;; +let _MIPS_INS_BNZ_B = 288;; +let _MIPS_INS_BNZ_D = 289;; +let _MIPS_INS_BNZ_H = 290;; +let _MIPS_INS_BNZ_V = 291;; +let _MIPS_INS_BNZ_W = 292;; +let _MIPS_INS_BOVC = 293;; +let _MIPS_INS_BPOSGE32 = 294;; +let _MIPS_INS_BPOSGE32C = 295;; +let _MIPS_INS_BREAK = 296;; +let _MIPS_INS_BREAK16 = 297;; +let _MIPS_INS_BRSC = 298;; +let _MIPS_INS_BSELI_B = 299;; +let _MIPS_INS_BSEL_V = 300;; +let _MIPS_INS_BSETI_B = 301;; +let _MIPS_INS_BSETI_D = 302;; +let _MIPS_INS_BSETI_H = 303;; +let _MIPS_INS_BSETI_W = 304;; +let _MIPS_INS_BSET_B = 305;; +let _MIPS_INS_BSET_D = 306;; +let _MIPS_INS_BSET_H = 307;; +let _MIPS_INS_BSET_W = 308;; +let _MIPS_INS_BYTEREVW = 309;; +let _MIPS_INS_BZ_B = 310;; +let _MIPS_INS_BZ_D = 311;; +let _MIPS_INS_BZ_H = 312;; +let _MIPS_INS_BZ_V = 313;; +let _MIPS_INS_BZ_W = 314;; +let _MIPS_INS_BEQZ = 315;; +let _MIPS_INS_BNEZ = 316;; +let _MIPS_INS_BTEQZ = 317;; +let _MIPS_INS_BTNEZ = 318;; +let _MIPS_INS_CACHE = 319;; +let _MIPS_INS_CACHEE = 320;; +let _MIPS_INS_CEIL_L_D = 321;; +let _MIPS_INS_CEIL_L_S = 322;; +let _MIPS_INS_CEIL_W_D = 323;; +let _MIPS_INS_CEIL_W_S = 324;; +let _MIPS_INS_CEQI_B = 325;; +let _MIPS_INS_CEQI_D = 326;; +let _MIPS_INS_CEQI_H = 327;; +let _MIPS_INS_CEQI_W = 328;; +let _MIPS_INS_CEQ_B = 329;; +let _MIPS_INS_CEQ_D = 330;; +let _MIPS_INS_CEQ_H = 331;; +let _MIPS_INS_CEQ_W = 332;; +let _MIPS_INS_CFC1 = 333;; +let _MIPS_INS_CFC2 = 334;; +let _MIPS_INS_CFCMSA = 335;; +let _MIPS_INS_CINS = 336;; +let _MIPS_INS_CINS32 = 337;; +let _MIPS_INS_CLASS_D = 338;; +let _MIPS_INS_CLASS_S = 339;; +let _MIPS_INS_CLEI_S_B = 340;; +let _MIPS_INS_CLEI_S_D = 341;; +let _MIPS_INS_CLEI_S_H = 342;; +let _MIPS_INS_CLEI_S_W = 343;; +let _MIPS_INS_CLEI_U_B = 344;; +let _MIPS_INS_CLEI_U_D = 345;; +let _MIPS_INS_CLEI_U_H = 346;; +let _MIPS_INS_CLEI_U_W = 347;; +let _MIPS_INS_CLE_S_B = 348;; +let _MIPS_INS_CLE_S_D = 349;; +let _MIPS_INS_CLE_S_H = 350;; +let _MIPS_INS_CLE_S_W = 351;; +let _MIPS_INS_CLE_U_B = 352;; +let _MIPS_INS_CLE_U_D = 353;; +let _MIPS_INS_CLE_U_H = 354;; +let _MIPS_INS_CLE_U_W = 355;; +let _MIPS_INS_CLO = 356;; +let _MIPS_INS_CLTI_S_B = 357;; +let _MIPS_INS_CLTI_S_D = 358;; +let _MIPS_INS_CLTI_S_H = 359;; +let _MIPS_INS_CLTI_S_W = 360;; +let _MIPS_INS_CLTI_U_B = 361;; +let _MIPS_INS_CLTI_U_D = 362;; +let _MIPS_INS_CLTI_U_H = 363;; +let _MIPS_INS_CLTI_U_W = 364;; +let _MIPS_INS_CLT_S_B = 365;; +let _MIPS_INS_CLT_S_D = 366;; +let _MIPS_INS_CLT_S_H = 367;; +let _MIPS_INS_CLT_S_W = 368;; +let _MIPS_INS_CLT_U_B = 369;; +let _MIPS_INS_CLT_U_D = 370;; +let _MIPS_INS_CLT_U_H = 371;; +let _MIPS_INS_CLT_U_W = 372;; +let _MIPS_INS_CLZ = 373;; +let _MIPS_INS_CMPGDU_EQ_QB = 374;; +let _MIPS_INS_CMPGDU_LE_QB = 375;; +let _MIPS_INS_CMPGDU_LT_QB = 376;; +let _MIPS_INS_CMPGU_EQ_QB = 377;; +let _MIPS_INS_CMPGU_LE_QB = 378;; +let _MIPS_INS_CMPGU_LT_QB = 379;; +let _MIPS_INS_CMPU_EQ_QB = 380;; +let _MIPS_INS_CMPU_LE_QB = 381;; +let _MIPS_INS_CMPU_LT_QB = 382;; +let _MIPS_INS_CMP_AF_D = 383;; +let _MIPS_INS_CMP_AF_S = 384;; +let _MIPS_INS_CMP_EQ_D = 385;; +let _MIPS_INS_CMP_EQ_PH = 386;; +let _MIPS_INS_CMP_EQ_S = 387;; +let _MIPS_INS_CMP_LE_D = 388;; +let _MIPS_INS_CMP_LE_PH = 389;; +let _MIPS_INS_CMP_LE_S = 390;; +let _MIPS_INS_CMP_LT_D = 391;; +let _MIPS_INS_CMP_LT_PH = 392;; +let _MIPS_INS_CMP_LT_S = 393;; +let _MIPS_INS_CMP_SAF_D = 394;; +let _MIPS_INS_CMP_SAF_S = 395;; +let _MIPS_INS_CMP_SEQ_D = 396;; +let _MIPS_INS_CMP_SEQ_S = 397;; +let _MIPS_INS_CMP_SLE_D = 398;; +let _MIPS_INS_CMP_SLE_S = 399;; +let _MIPS_INS_CMP_SLT_D = 400;; +let _MIPS_INS_CMP_SLT_S = 401;; +let _MIPS_INS_CMP_SUEQ_D = 402;; +let _MIPS_INS_CMP_SUEQ_S = 403;; +let _MIPS_INS_CMP_SULE_D = 404;; +let _MIPS_INS_CMP_SULE_S = 405;; +let _MIPS_INS_CMP_SULT_D = 406;; +let _MIPS_INS_CMP_SULT_S = 407;; +let _MIPS_INS_CMP_SUN_D = 408;; +let _MIPS_INS_CMP_SUN_S = 409;; +let _MIPS_INS_CMP_UEQ_D = 410;; +let _MIPS_INS_CMP_UEQ_S = 411;; +let _MIPS_INS_CMP_ULE_D = 412;; +let _MIPS_INS_CMP_ULE_S = 413;; +let _MIPS_INS_CMP_ULT_D = 414;; +let _MIPS_INS_CMP_ULT_S = 415;; +let _MIPS_INS_CMP_UN_D = 416;; +let _MIPS_INS_CMP_UN_S = 417;; +let _MIPS_INS_COPY_S_B = 418;; +let _MIPS_INS_COPY_S_D = 419;; +let _MIPS_INS_COPY_S_H = 420;; +let _MIPS_INS_COPY_S_W = 421;; +let _MIPS_INS_COPY_U_B = 422;; +let _MIPS_INS_COPY_U_H = 423;; +let _MIPS_INS_COPY_U_W = 424;; +let _MIPS_INS_CRC32B = 425;; +let _MIPS_INS_CRC32CB = 426;; +let _MIPS_INS_CRC32CD = 427;; +let _MIPS_INS_CRC32CH = 428;; +let _MIPS_INS_CRC32CW = 429;; +let _MIPS_INS_CRC32D = 430;; +let _MIPS_INS_CRC32H = 431;; +let _MIPS_INS_CRC32W = 432;; +let _MIPS_INS_CTC1 = 433;; +let _MIPS_INS_CTC2 = 434;; +let _MIPS_INS_CTCMSA = 435;; +let _MIPS_INS_CVT_D_S = 436;; +let _MIPS_INS_CVT_D_W = 437;; +let _MIPS_INS_CVT_D_L = 438;; +let _MIPS_INS_CVT_L_D = 439;; +let _MIPS_INS_CVT_L_S = 440;; +let _MIPS_INS_CVT_PS_PW = 441;; +let _MIPS_INS_CVT_PS_S = 442;; +let _MIPS_INS_CVT_PW_PS = 443;; +let _MIPS_INS_CVT_S_D = 444;; +let _MIPS_INS_CVT_S_L = 445;; +let _MIPS_INS_CVT_S_PL = 446;; +let _MIPS_INS_CVT_S_PU = 447;; +let _MIPS_INS_CVT_S_W = 448;; +let _MIPS_INS_CVT_W_D = 449;; +let _MIPS_INS_CVT_W_S = 450;; +let _MIPS_INS_C_EQ_D = 451;; +let _MIPS_INS_C_EQ_S = 452;; +let _MIPS_INS_C_F_D = 453;; +let _MIPS_INS_C_F_S = 454;; +let _MIPS_INS_C_LE_D = 455;; +let _MIPS_INS_C_LE_S = 456;; +let _MIPS_INS_C_LT_D = 457;; +let _MIPS_INS_C_LT_S = 458;; +let _MIPS_INS_C_NGE_D = 459;; +let _MIPS_INS_C_NGE_S = 460;; +let _MIPS_INS_C_NGLE_D = 461;; +let _MIPS_INS_C_NGLE_S = 462;; +let _MIPS_INS_C_NGL_D = 463;; +let _MIPS_INS_C_NGL_S = 464;; +let _MIPS_INS_C_NGT_D = 465;; +let _MIPS_INS_C_NGT_S = 466;; +let _MIPS_INS_C_OLE_D = 467;; +let _MIPS_INS_C_OLE_S = 468;; +let _MIPS_INS_C_OLT_D = 469;; +let _MIPS_INS_C_OLT_S = 470;; +let _MIPS_INS_C_SEQ_D = 471;; +let _MIPS_INS_C_SEQ_S = 472;; +let _MIPS_INS_C_SF_D = 473;; +let _MIPS_INS_C_SF_S = 474;; +let _MIPS_INS_C_UEQ_D = 475;; +let _MIPS_INS_C_UEQ_S = 476;; +let _MIPS_INS_C_ULE_D = 477;; +let _MIPS_INS_C_ULE_S = 478;; +let _MIPS_INS_C_ULT_D = 479;; +let _MIPS_INS_C_ULT_S = 480;; +let _MIPS_INS_C_UN_D = 481;; +let _MIPS_INS_C_UN_S = 482;; +let _MIPS_INS_CMP = 483;; +let _MIPS_INS_CMPI = 484;; +let _MIPS_INS_DADD = 485;; +let _MIPS_INS_DADDI = 486;; +let _MIPS_INS_DADDIU = 487;; +let _MIPS_INS_DADDU = 488;; +let _MIPS_INS_DAHI = 489;; +let _MIPS_INS_DALIGN = 490;; +let _MIPS_INS_DATI = 491;; +let _MIPS_INS_DAUI = 492;; +let _MIPS_INS_DBITSWAP = 493;; +let _MIPS_INS_DCLO = 494;; +let _MIPS_INS_DCLZ = 495;; +let _MIPS_INS_DERET = 496;; +let _MIPS_INS_DEXT = 497;; +let _MIPS_INS_DEXTM = 498;; +let _MIPS_INS_DEXTU = 499;; +let _MIPS_INS_DI = 500;; +let _MIPS_INS_DINS = 501;; +let _MIPS_INS_DINSM = 502;; +let _MIPS_INS_DINSU = 503;; +let _MIPS_INS_DIV_S_B = 504;; +let _MIPS_INS_DIV_S_D = 505;; +let _MIPS_INS_DIV_S_H = 506;; +let _MIPS_INS_DIV_S_W = 507;; +let _MIPS_INS_DIV_U_B = 508;; +let _MIPS_INS_DIV_U_D = 509;; +let _MIPS_INS_DIV_U_H = 510;; +let _MIPS_INS_DIV_U_W = 511;; +let _MIPS_INS_DLSA = 512;; +let _MIPS_INS_DMFC0 = 513;; +let _MIPS_INS_DMFC1 = 514;; +let _MIPS_INS_DMFC2 = 515;; +let _MIPS_INS_DMFGC0 = 516;; +let _MIPS_INS_DMOD = 517;; +let _MIPS_INS_DMODU = 518;; +let _MIPS_INS_DMT = 519;; +let _MIPS_INS_DMTC0 = 520;; +let _MIPS_INS_DMTC1 = 521;; +let _MIPS_INS_DMTC2 = 522;; +let _MIPS_INS_DMTGC0 = 523;; +let _MIPS_INS_DMUH = 524;; +let _MIPS_INS_DMUHU = 525;; +let _MIPS_INS_DMULT = 526;; +let _MIPS_INS_DMULTU = 527;; +let _MIPS_INS_DMULU = 528;; +let _MIPS_INS_DOTP_S_D = 529;; +let _MIPS_INS_DOTP_S_H = 530;; +let _MIPS_INS_DOTP_S_W = 531;; +let _MIPS_INS_DOTP_U_D = 532;; +let _MIPS_INS_DOTP_U_H = 533;; +let _MIPS_INS_DOTP_U_W = 534;; +let _MIPS_INS_DPADD_S_D = 535;; +let _MIPS_INS_DPADD_S_H = 536;; +let _MIPS_INS_DPADD_S_W = 537;; +let _MIPS_INS_DPADD_U_D = 538;; +let _MIPS_INS_DPADD_U_H = 539;; +let _MIPS_INS_DPADD_U_W = 540;; +let _MIPS_INS_DPAQX_SA_W_PH = 541;; +let _MIPS_INS_DPAQX_S_W_PH = 542;; +let _MIPS_INS_DPAQ_SA_L_W = 543;; +let _MIPS_INS_DPAQ_S_W_PH = 544;; +let _MIPS_INS_DPAU_H_QBL = 545;; +let _MIPS_INS_DPAU_H_QBR = 546;; +let _MIPS_INS_DPAX_W_PH = 547;; +let _MIPS_INS_DPA_W_PH = 548;; +let _MIPS_INS_DPOP = 549;; +let _MIPS_INS_DPSQX_SA_W_PH = 550;; +let _MIPS_INS_DPSQX_S_W_PH = 551;; +let _MIPS_INS_DPSQ_SA_L_W = 552;; +let _MIPS_INS_DPSQ_S_W_PH = 553;; +let _MIPS_INS_DPSUB_S_D = 554;; +let _MIPS_INS_DPSUB_S_H = 555;; +let _MIPS_INS_DPSUB_S_W = 556;; +let _MIPS_INS_DPSUB_U_D = 557;; +let _MIPS_INS_DPSUB_U_H = 558;; +let _MIPS_INS_DPSUB_U_W = 559;; +let _MIPS_INS_DPSU_H_QBL = 560;; +let _MIPS_INS_DPSU_H_QBR = 561;; +let _MIPS_INS_DPSX_W_PH = 562;; +let _MIPS_INS_DPS_W_PH = 563;; +let _MIPS_INS_DROTR = 564;; +let _MIPS_INS_DROTR32 = 565;; +let _MIPS_INS_DROTRV = 566;; +let _MIPS_INS_DSBH = 567;; +let _MIPS_INS_DSHD = 568;; +let _MIPS_INS_DSLL = 569;; +let _MIPS_INS_DSLL32 = 570;; +let _MIPS_INS_DSLLV = 571;; +let _MIPS_INS_DSRA = 572;; +let _MIPS_INS_DSRA32 = 573;; +let _MIPS_INS_DSRAV = 574;; +let _MIPS_INS_DSRL = 575;; +let _MIPS_INS_DSRL32 = 576;; +let _MIPS_INS_DSRLV = 577;; +let _MIPS_INS_DSUB = 578;; +let _MIPS_INS_DSUBU = 579;; +let _MIPS_INS_DVP = 580;; +let _MIPS_INS_DVPE = 581;; +let _MIPS_INS_EHB = 582;; +let _MIPS_INS_EI = 583;; +let _MIPS_INS_EMT = 584;; +let _MIPS_INS_ERET = 585;; +let _MIPS_INS_ERETNC = 586;; +let _MIPS_INS_EVP = 587;; +let _MIPS_INS_EVPE = 588;; +let _MIPS_INS_EXT = 589;; +let _MIPS_INS_EXTP = 590;; +let _MIPS_INS_EXTPDP = 591;; +let _MIPS_INS_EXTPDPV = 592;; +let _MIPS_INS_EXTPV = 593;; +let _MIPS_INS_EXTRV_RS_W = 594;; +let _MIPS_INS_EXTRV_R_W = 595;; +let _MIPS_INS_EXTRV_S_H = 596;; +let _MIPS_INS_EXTRV_W = 597;; +let _MIPS_INS_EXTR_RS_W = 598;; +let _MIPS_INS_EXTR_R_W = 599;; +let _MIPS_INS_EXTR_S_H = 600;; +let _MIPS_INS_EXTR_W = 601;; +let _MIPS_INS_EXTS = 602;; +let _MIPS_INS_EXTS32 = 603;; +let _MIPS_INS_EXTW = 604;; +let _MIPS_INS_ABS_D = 605;; +let _MIPS_INS_ABS_S = 606;; +let _MIPS_INS_FADD_D = 607;; +let _MIPS_INS_ADD_D = 608;; +let _MIPS_INS_ADD_PS = 609;; +let _MIPS_INS_ADD_S = 610;; +let _MIPS_INS_FADD_W = 611;; +let _MIPS_INS_FCAF_D = 612;; +let _MIPS_INS_FCAF_W = 613;; +let _MIPS_INS_FCEQ_D = 614;; +let _MIPS_INS_FCEQ_W = 615;; +let _MIPS_INS_FCLASS_D = 616;; +let _MIPS_INS_FCLASS_W = 617;; +let _MIPS_INS_FCLE_D = 618;; +let _MIPS_INS_FCLE_W = 619;; +let _MIPS_INS_FCLT_D = 620;; +let _MIPS_INS_FCLT_W = 621;; +let _MIPS_INS_FCNE_D = 622;; +let _MIPS_INS_FCNE_W = 623;; +let _MIPS_INS_FCOR_D = 624;; +let _MIPS_INS_FCOR_W = 625;; +let _MIPS_INS_FCUEQ_D = 626;; +let _MIPS_INS_FCUEQ_W = 627;; +let _MIPS_INS_FCULE_D = 628;; +let _MIPS_INS_FCULE_W = 629;; +let _MIPS_INS_FCULT_D = 630;; +let _MIPS_INS_FCULT_W = 631;; +let _MIPS_INS_FCUNE_D = 632;; +let _MIPS_INS_FCUNE_W = 633;; +let _MIPS_INS_FCUN_D = 634;; +let _MIPS_INS_FCUN_W = 635;; +let _MIPS_INS_FDIV_D = 636;; +let _MIPS_INS_DIV_D = 637;; +let _MIPS_INS_DIV_S = 638;; +let _MIPS_INS_FDIV_W = 639;; +let _MIPS_INS_FEXDO_H = 640;; +let _MIPS_INS_FEXDO_W = 641;; +let _MIPS_INS_FEXP2_D = 642;; +let _MIPS_INS_FEXP2_W = 643;; +let _MIPS_INS_FEXUPL_D = 644;; +let _MIPS_INS_FEXUPL_W = 645;; +let _MIPS_INS_FEXUPR_D = 646;; +let _MIPS_INS_FEXUPR_W = 647;; +let _MIPS_INS_FFINT_S_D = 648;; +let _MIPS_INS_FFINT_S_W = 649;; +let _MIPS_INS_FFINT_U_D = 650;; +let _MIPS_INS_FFINT_U_W = 651;; +let _MIPS_INS_FFQL_D = 652;; +let _MIPS_INS_FFQL_W = 653;; +let _MIPS_INS_FFQR_D = 654;; +let _MIPS_INS_FFQR_W = 655;; +let _MIPS_INS_FILL_B = 656;; +let _MIPS_INS_FILL_D = 657;; +let _MIPS_INS_FILL_H = 658;; +let _MIPS_INS_FILL_W = 659;; +let _MIPS_INS_FLOG2_D = 660;; +let _MIPS_INS_FLOG2_W = 661;; +let _MIPS_INS_FLOOR_L_D = 662;; +let _MIPS_INS_FLOOR_L_S = 663;; +let _MIPS_INS_FLOOR_W_D = 664;; +let _MIPS_INS_FLOOR_W_S = 665;; +let _MIPS_INS_FMADD_D = 666;; +let _MIPS_INS_FMADD_W = 667;; +let _MIPS_INS_FMAX_A_D = 668;; +let _MIPS_INS_FMAX_A_W = 669;; +let _MIPS_INS_FMAX_D = 670;; +let _MIPS_INS_FMAX_W = 671;; +let _MIPS_INS_FMIN_A_D = 672;; +let _MIPS_INS_FMIN_A_W = 673;; +let _MIPS_INS_FMIN_D = 674;; +let _MIPS_INS_FMIN_W = 675;; +let _MIPS_INS_MOV_D = 676;; +let _MIPS_INS_MOV_S = 677;; +let _MIPS_INS_FMSUB_D = 678;; +let _MIPS_INS_FMSUB_W = 679;; +let _MIPS_INS_FMUL_D = 680;; +let _MIPS_INS_MUL_D = 681;; +let _MIPS_INS_MUL_PS = 682;; +let _MIPS_INS_MUL_S = 683;; +let _MIPS_INS_FMUL_W = 684;; +let _MIPS_INS_NEG_D = 685;; +let _MIPS_INS_NEG_S = 686;; +let _MIPS_INS_FORK = 687;; +let _MIPS_INS_FRCP_D = 688;; +let _MIPS_INS_FRCP_W = 689;; +let _MIPS_INS_FRINT_D = 690;; +let _MIPS_INS_FRINT_W = 691;; +let _MIPS_INS_FRSQRT_D = 692;; +let _MIPS_INS_FRSQRT_W = 693;; +let _MIPS_INS_FSAF_D = 694;; +let _MIPS_INS_FSAF_W = 695;; +let _MIPS_INS_FSEQ_D = 696;; +let _MIPS_INS_FSEQ_W = 697;; +let _MIPS_INS_FSLE_D = 698;; +let _MIPS_INS_FSLE_W = 699;; +let _MIPS_INS_FSLT_D = 700;; +let _MIPS_INS_FSLT_W = 701;; +let _MIPS_INS_FSNE_D = 702;; +let _MIPS_INS_FSNE_W = 703;; +let _MIPS_INS_FSOR_D = 704;; +let _MIPS_INS_FSOR_W = 705;; +let _MIPS_INS_FSQRT_D = 706;; +let _MIPS_INS_SQRT_D = 707;; +let _MIPS_INS_SQRT_S = 708;; +let _MIPS_INS_FSQRT_W = 709;; +let _MIPS_INS_FSUB_D = 710;; +let _MIPS_INS_SUB_D = 711;; +let _MIPS_INS_SUB_PS = 712;; +let _MIPS_INS_SUB_S = 713;; +let _MIPS_INS_FSUB_W = 714;; +let _MIPS_INS_FSUEQ_D = 715;; +let _MIPS_INS_FSUEQ_W = 716;; +let _MIPS_INS_FSULE_D = 717;; +let _MIPS_INS_FSULE_W = 718;; +let _MIPS_INS_FSULT_D = 719;; +let _MIPS_INS_FSULT_W = 720;; +let _MIPS_INS_FSUNE_D = 721;; +let _MIPS_INS_FSUNE_W = 722;; +let _MIPS_INS_FSUN_D = 723;; +let _MIPS_INS_FSUN_W = 724;; +let _MIPS_INS_FTINT_S_D = 725;; +let _MIPS_INS_FTINT_S_W = 726;; +let _MIPS_INS_FTINT_U_D = 727;; +let _MIPS_INS_FTINT_U_W = 728;; +let _MIPS_INS_FTQ_H = 729;; +let _MIPS_INS_FTQ_W = 730;; +let _MIPS_INS_FTRUNC_S_D = 731;; +let _MIPS_INS_FTRUNC_S_W = 732;; +let _MIPS_INS_FTRUNC_U_D = 733;; +let _MIPS_INS_FTRUNC_U_W = 734;; +let _MIPS_INS_GINVI = 735;; +let _MIPS_INS_GINVT = 736;; +let _MIPS_INS_HADD_S_D = 737;; +let _MIPS_INS_HADD_S_H = 738;; +let _MIPS_INS_HADD_S_W = 739;; +let _MIPS_INS_HADD_U_D = 740;; +let _MIPS_INS_HADD_U_H = 741;; +let _MIPS_INS_HADD_U_W = 742;; +let _MIPS_INS_HSUB_S_D = 743;; +let _MIPS_INS_HSUB_S_H = 744;; +let _MIPS_INS_HSUB_S_W = 745;; +let _MIPS_INS_HSUB_U_D = 746;; +let _MIPS_INS_HSUB_U_H = 747;; +let _MIPS_INS_HSUB_U_W = 748;; +let _MIPS_INS_HYPCALL = 749;; +let _MIPS_INS_ILVEV_B = 750;; +let _MIPS_INS_ILVEV_D = 751;; +let _MIPS_INS_ILVEV_H = 752;; +let _MIPS_INS_ILVEV_W = 753;; +let _MIPS_INS_ILVL_B = 754;; +let _MIPS_INS_ILVL_D = 755;; +let _MIPS_INS_ILVL_H = 756;; +let _MIPS_INS_ILVL_W = 757;; +let _MIPS_INS_ILVOD_B = 758;; +let _MIPS_INS_ILVOD_D = 759;; +let _MIPS_INS_ILVOD_H = 760;; +let _MIPS_INS_ILVOD_W = 761;; +let _MIPS_INS_ILVR_B = 762;; +let _MIPS_INS_ILVR_D = 763;; +let _MIPS_INS_ILVR_H = 764;; +let _MIPS_INS_ILVR_W = 765;; +let _MIPS_INS_INS = 766;; +let _MIPS_INS_INSERT_B = 767;; +let _MIPS_INS_INSERT_D = 768;; +let _MIPS_INS_INSERT_H = 769;; +let _MIPS_INS_INSERT_W = 770;; +let _MIPS_INS_INSV = 771;; +let _MIPS_INS_INSVE_B = 772;; +let _MIPS_INS_INSVE_D = 773;; +let _MIPS_INS_INSVE_H = 774;; +let _MIPS_INS_INSVE_W = 775;; +let _MIPS_INS_J = 776;; +let _MIPS_INS_JALR = 777;; +let _MIPS_INS_JALRC = 778;; +let _MIPS_INS_JALRC_HB = 779;; +let _MIPS_INS_JALRS16 = 780;; +let _MIPS_INS_JALRS = 781;; +let _MIPS_INS_JALR_HB = 782;; +let _MIPS_INS_JALS = 783;; +let _MIPS_INS_JALX = 784;; +let _MIPS_INS_JIALC = 785;; +let _MIPS_INS_JIC = 786;; +let _MIPS_INS_JR = 787;; +let _MIPS_INS_JR16 = 788;; +let _MIPS_INS_JRADDIUSP = 789;; +let _MIPS_INS_JRC = 790;; +let _MIPS_INS_JRC16 = 791;; +let _MIPS_INS_JRCADDIUSP = 792;; +let _MIPS_INS_JR_HB = 793;; +let _MIPS_INS_LAPC_H = 794;; +let _MIPS_INS_LAPC_B = 795;; +let _MIPS_INS_LB = 796;; +let _MIPS_INS_LBE = 797;; +let _MIPS_INS_LBU16 = 798;; +let _MIPS_INS_LBU = 799;; +let _MIPS_INS_LBUX = 800;; +let _MIPS_INS_LBX = 801;; +let _MIPS_INS_LBUE = 802;; +let _MIPS_INS_LDC1 = 803;; +let _MIPS_INS_LDC2 = 804;; +let _MIPS_INS_LDC3 = 805;; +let _MIPS_INS_LDI_B = 806;; +let _MIPS_INS_LDI_D = 807;; +let _MIPS_INS_LDI_H = 808;; +let _MIPS_INS_LDI_W = 809;; +let _MIPS_INS_LDL = 810;; +let _MIPS_INS_LDPC = 811;; +let _MIPS_INS_LDR = 812;; +let _MIPS_INS_LDXC1 = 813;; +let _MIPS_INS_LD_B = 814;; +let _MIPS_INS_LD_D = 815;; +let _MIPS_INS_LD_H = 816;; +let _MIPS_INS_LD_W = 817;; +let _MIPS_INS_LH = 818;; +let _MIPS_INS_LHE = 819;; +let _MIPS_INS_LHU16 = 820;; +let _MIPS_INS_LHU = 821;; +let _MIPS_INS_LHUXS = 822;; +let _MIPS_INS_LHUX = 823;; +let _MIPS_INS_LHX = 824;; +let _MIPS_INS_LHXS = 825;; +let _MIPS_INS_LHUE = 826;; +let _MIPS_INS_LI16 = 827;; +let _MIPS_INS_LL = 828;; +let _MIPS_INS_LLD = 829;; +let _MIPS_INS_LLE = 830;; +let _MIPS_INS_LLWP = 831;; +let _MIPS_INS_LSA = 832;; +let _MIPS_INS_LUI = 833;; +let _MIPS_INS_LUXC1 = 834;; +let _MIPS_INS_LW = 835;; +let _MIPS_INS_LW16 = 836;; +let _MIPS_INS_LWC1 = 837;; +let _MIPS_INS_LWC2 = 838;; +let _MIPS_INS_LWC3 = 839;; +let _MIPS_INS_LWE = 840;; +let _MIPS_INS_LWL = 841;; +let _MIPS_INS_LWLE = 842;; +let _MIPS_INS_LWM16 = 843;; +let _MIPS_INS_LWM32 = 844;; +let _MIPS_INS_LWPC = 845;; +let _MIPS_INS_LWP = 846;; +let _MIPS_INS_LWR = 847;; +let _MIPS_INS_LWRE = 848;; +let _MIPS_INS_LWUPC = 849;; +let _MIPS_INS_LWU = 850;; +let _MIPS_INS_LWX = 851;; +let _MIPS_INS_LWXC1 = 852;; +let _MIPS_INS_LWXS = 853;; +let _MIPS_INS_MADD = 854;; +let _MIPS_INS_MADDF_D = 855;; +let _MIPS_INS_MADDF_S = 856;; +let _MIPS_INS_MADDR_Q_H = 857;; +let _MIPS_INS_MADDR_Q_W = 858;; +let _MIPS_INS_MADDU = 859;; +let _MIPS_INS_MADDV_B = 860;; +let _MIPS_INS_MADDV_D = 861;; +let _MIPS_INS_MADDV_H = 862;; +let _MIPS_INS_MADDV_W = 863;; +let _MIPS_INS_MADD_D = 864;; +let _MIPS_INS_MADD_Q_H = 865;; +let _MIPS_INS_MADD_Q_W = 866;; +let _MIPS_INS_MADD_S = 867;; +let _MIPS_INS_MAQ_SA_W_PHL = 868;; +let _MIPS_INS_MAQ_SA_W_PHR = 869;; +let _MIPS_INS_MAQ_S_W_PHL = 870;; +let _MIPS_INS_MAQ_S_W_PHR = 871;; +let _MIPS_INS_MAXA_D = 872;; +let _MIPS_INS_MAXA_S = 873;; +let _MIPS_INS_MAXI_S_B = 874;; +let _MIPS_INS_MAXI_S_D = 875;; +let _MIPS_INS_MAXI_S_H = 876;; +let _MIPS_INS_MAXI_S_W = 877;; +let _MIPS_INS_MAXI_U_B = 878;; +let _MIPS_INS_MAXI_U_D = 879;; +let _MIPS_INS_MAXI_U_H = 880;; +let _MIPS_INS_MAXI_U_W = 881;; +let _MIPS_INS_MAX_A_B = 882;; +let _MIPS_INS_MAX_A_D = 883;; +let _MIPS_INS_MAX_A_H = 884;; +let _MIPS_INS_MAX_A_W = 885;; +let _MIPS_INS_MAX_D = 886;; +let _MIPS_INS_MAX_S = 887;; +let _MIPS_INS_MAX_S_B = 888;; +let _MIPS_INS_MAX_S_D = 889;; +let _MIPS_INS_MAX_S_H = 890;; +let _MIPS_INS_MAX_S_W = 891;; +let _MIPS_INS_MAX_U_B = 892;; +let _MIPS_INS_MAX_U_D = 893;; +let _MIPS_INS_MAX_U_H = 894;; +let _MIPS_INS_MAX_U_W = 895;; +let _MIPS_INS_MFC0 = 896;; +let _MIPS_INS_MFC1 = 897;; +let _MIPS_INS_MFC2 = 898;; +let _MIPS_INS_MFGC0 = 899;; +let _MIPS_INS_MFHC0 = 900;; +let _MIPS_INS_MFHC1 = 901;; +let _MIPS_INS_MFHC2 = 902;; +let _MIPS_INS_MFHGC0 = 903;; +let _MIPS_INS_MFHI = 904;; +let _MIPS_INS_MFHI16 = 905;; +let _MIPS_INS_MFLO = 906;; +let _MIPS_INS_MFLO16 = 907;; +let _MIPS_INS_MFTR = 908;; +let _MIPS_INS_MINA_D = 909;; +let _MIPS_INS_MINA_S = 910;; +let _MIPS_INS_MINI_S_B = 911;; +let _MIPS_INS_MINI_S_D = 912;; +let _MIPS_INS_MINI_S_H = 913;; +let _MIPS_INS_MINI_S_W = 914;; +let _MIPS_INS_MINI_U_B = 915;; +let _MIPS_INS_MINI_U_D = 916;; +let _MIPS_INS_MINI_U_H = 917;; +let _MIPS_INS_MINI_U_W = 918;; +let _MIPS_INS_MIN_A_B = 919;; +let _MIPS_INS_MIN_A_D = 920;; +let _MIPS_INS_MIN_A_H = 921;; +let _MIPS_INS_MIN_A_W = 922;; +let _MIPS_INS_MIN_D = 923;; +let _MIPS_INS_MIN_S = 924;; +let _MIPS_INS_MIN_S_B = 925;; +let _MIPS_INS_MIN_S_D = 926;; +let _MIPS_INS_MIN_S_H = 927;; +let _MIPS_INS_MIN_S_W = 928;; +let _MIPS_INS_MIN_U_B = 929;; +let _MIPS_INS_MIN_U_D = 930;; +let _MIPS_INS_MIN_U_H = 931;; +let _MIPS_INS_MIN_U_W = 932;; +let _MIPS_INS_MOD = 933;; +let _MIPS_INS_MODSUB = 934;; +let _MIPS_INS_MODU = 935;; +let _MIPS_INS_MOD_S_B = 936;; +let _MIPS_INS_MOD_S_D = 937;; +let _MIPS_INS_MOD_S_H = 938;; +let _MIPS_INS_MOD_S_W = 939;; +let _MIPS_INS_MOD_U_B = 940;; +let _MIPS_INS_MOD_U_D = 941;; +let _MIPS_INS_MOD_U_H = 942;; +let _MIPS_INS_MOD_U_W = 943;; +let _MIPS_INS_MOVE = 944;; +let _MIPS_INS_MOVE16 = 945;; +let _MIPS_INS_MOVE_BALC = 946;; +let _MIPS_INS_MOVEP = 947;; +let _MIPS_INS_MOVE_V = 948;; +let _MIPS_INS_MOVF_D = 949;; +let _MIPS_INS_MOVF = 950;; +let _MIPS_INS_MOVF_S = 951;; +let _MIPS_INS_MOVN_D = 952;; +let _MIPS_INS_MOVN = 953;; +let _MIPS_INS_MOVN_S = 954;; +let _MIPS_INS_MOVT_D = 955;; +let _MIPS_INS_MOVT = 956;; +let _MIPS_INS_MOVT_S = 957;; +let _MIPS_INS_MOVZ_D = 958;; +let _MIPS_INS_MOVZ = 959;; +let _MIPS_INS_MOVZ_S = 960;; +let _MIPS_INS_MSUB = 961;; +let _MIPS_INS_MSUBF_D = 962;; +let _MIPS_INS_MSUBF_S = 963;; +let _MIPS_INS_MSUBR_Q_H = 964;; +let _MIPS_INS_MSUBR_Q_W = 965;; +let _MIPS_INS_MSUBU = 966;; +let _MIPS_INS_MSUBV_B = 967;; +let _MIPS_INS_MSUBV_D = 968;; +let _MIPS_INS_MSUBV_H = 969;; +let _MIPS_INS_MSUBV_W = 970;; +let _MIPS_INS_MSUB_D = 971;; +let _MIPS_INS_MSUB_Q_H = 972;; +let _MIPS_INS_MSUB_Q_W = 973;; +let _MIPS_INS_MSUB_S = 974;; +let _MIPS_INS_MTC0 = 975;; +let _MIPS_INS_MTC1 = 976;; +let _MIPS_INS_MTC2 = 977;; +let _MIPS_INS_MTGC0 = 978;; +let _MIPS_INS_MTHC0 = 979;; +let _MIPS_INS_MTHC1 = 980;; +let _MIPS_INS_MTHC2 = 981;; +let _MIPS_INS_MTHGC0 = 982;; +let _MIPS_INS_MTHI = 983;; +let _MIPS_INS_MTHLIP = 984;; +let _MIPS_INS_MTLO = 985;; +let _MIPS_INS_MTM0 = 986;; +let _MIPS_INS_MTM1 = 987;; +let _MIPS_INS_MTM2 = 988;; +let _MIPS_INS_MTP0 = 989;; +let _MIPS_INS_MTP1 = 990;; +let _MIPS_INS_MTP2 = 991;; +let _MIPS_INS_MTTR = 992;; +let _MIPS_INS_MUH = 993;; +let _MIPS_INS_MUHU = 994;; +let _MIPS_INS_MULEQ_S_W_PHL = 995;; +let _MIPS_INS_MULEQ_S_W_PHR = 996;; +let _MIPS_INS_MULEU_S_PH_QBL = 997;; +let _MIPS_INS_MULEU_S_PH_QBR = 998;; +let _MIPS_INS_MULQ_RS_PH = 999;; +let _MIPS_INS_MULQ_RS_W = 1000;; +let _MIPS_INS_MULQ_S_PH = 1001;; +let _MIPS_INS_MULQ_S_W = 1002;; +let _MIPS_INS_MULR_PS = 1003;; +let _MIPS_INS_MULR_Q_H = 1004;; +let _MIPS_INS_MULR_Q_W = 1005;; +let _MIPS_INS_MULSAQ_S_W_PH = 1006;; +let _MIPS_INS_MULSA_W_PH = 1007;; +let _MIPS_INS_MULT = 1008;; +let _MIPS_INS_MULTU = 1009;; +let _MIPS_INS_MULU = 1010;; +let _MIPS_INS_MULV_B = 1011;; +let _MIPS_INS_MULV_D = 1012;; +let _MIPS_INS_MULV_H = 1013;; +let _MIPS_INS_MULV_W = 1014;; +let _MIPS_INS_MUL_PH = 1015;; +let _MIPS_INS_MUL_Q_H = 1016;; +let _MIPS_INS_MUL_Q_W = 1017;; +let _MIPS_INS_MUL_S_PH = 1018;; +let _MIPS_INS_NLOC_B = 1019;; +let _MIPS_INS_NLOC_D = 1020;; +let _MIPS_INS_NLOC_H = 1021;; +let _MIPS_INS_NLOC_W = 1022;; +let _MIPS_INS_NLZC_B = 1023;; +let _MIPS_INS_NLZC_D = 1024;; +let _MIPS_INS_NLZC_H = 1025;; +let _MIPS_INS_NLZC_W = 1026;; +let _MIPS_INS_NMADD_D = 1027;; +let _MIPS_INS_NMADD_S = 1028;; +let _MIPS_INS_NMSUB_D = 1029;; +let _MIPS_INS_NMSUB_S = 1030;; +let _MIPS_INS_NOP32 = 1031;; +let _MIPS_INS_NOP = 1032;; +let _MIPS_INS_NORI_B = 1033;; +let _MIPS_INS_NOR_V = 1034;; +let _MIPS_INS_NOT16 = 1035;; +let _MIPS_INS_NOT = 1036;; +let _MIPS_INS_NEG = 1037;; +let _MIPS_INS_OR = 1038;; +let _MIPS_INS_OR16 = 1039;; +let _MIPS_INS_ORI_B = 1040;; +let _MIPS_INS_ORI = 1041;; +let _MIPS_INS_OR_V = 1042;; +let _MIPS_INS_PACKRL_PH = 1043;; +let _MIPS_INS_PAUSE = 1044;; +let _MIPS_INS_PCKEV_B = 1045;; +let _MIPS_INS_PCKEV_D = 1046;; +let _MIPS_INS_PCKEV_H = 1047;; +let _MIPS_INS_PCKEV_W = 1048;; +let _MIPS_INS_PCKOD_B = 1049;; +let _MIPS_INS_PCKOD_D = 1050;; +let _MIPS_INS_PCKOD_H = 1051;; +let _MIPS_INS_PCKOD_W = 1052;; +let _MIPS_INS_PCNT_B = 1053;; +let _MIPS_INS_PCNT_D = 1054;; +let _MIPS_INS_PCNT_H = 1055;; +let _MIPS_INS_PCNT_W = 1056;; +let _MIPS_INS_PICK_PH = 1057;; +let _MIPS_INS_PICK_QB = 1058;; +let _MIPS_INS_PLL_PS = 1059;; +let _MIPS_INS_PLU_PS = 1060;; +let _MIPS_INS_POP = 1061;; +let _MIPS_INS_PRECEQU_PH_QBL = 1062;; +let _MIPS_INS_PRECEQU_PH_QBLA = 1063;; +let _MIPS_INS_PRECEQU_PH_QBR = 1064;; +let _MIPS_INS_PRECEQU_PH_QBRA = 1065;; +let _MIPS_INS_PRECEQ_W_PHL = 1066;; +let _MIPS_INS_PRECEQ_W_PHR = 1067;; +let _MIPS_INS_PRECEU_PH_QBL = 1068;; +let _MIPS_INS_PRECEU_PH_QBLA = 1069;; +let _MIPS_INS_PRECEU_PH_QBR = 1070;; +let _MIPS_INS_PRECEU_PH_QBRA = 1071;; +let _MIPS_INS_PRECRQU_S_QB_PH = 1072;; +let _MIPS_INS_PRECRQ_PH_W = 1073;; +let _MIPS_INS_PRECRQ_QB_PH = 1074;; +let _MIPS_INS_PRECRQ_RS_PH_W = 1075;; +let _MIPS_INS_PRECR_QB_PH = 1076;; +let _MIPS_INS_PRECR_SRA_PH_W = 1077;; +let _MIPS_INS_PRECR_SRA_R_PH_W = 1078;; +let _MIPS_INS_PREF = 1079;; +let _MIPS_INS_PREFE = 1080;; +let _MIPS_INS_PREFX = 1081;; +let _MIPS_INS_PREPEND = 1082;; +let _MIPS_INS_PUL_PS = 1083;; +let _MIPS_INS_PUU_PS = 1084;; +let _MIPS_INS_RADDU_W_QB = 1085;; +let _MIPS_INS_RDDSP = 1086;; +let _MIPS_INS_RDHWR = 1087;; +let _MIPS_INS_RDPGPR = 1088;; +let _MIPS_INS_RECIP_D = 1089;; +let _MIPS_INS_RECIP_S = 1090;; +let _MIPS_INS_REPLV_PH = 1091;; +let _MIPS_INS_REPLV_QB = 1092;; +let _MIPS_INS_REPL_PH = 1093;; +let _MIPS_INS_REPL_QB = 1094;; +let _MIPS_INS_RESTORE_JRC = 1095;; +let _MIPS_INS_RESTORE = 1096;; +let _MIPS_INS_RINT_D = 1097;; +let _MIPS_INS_RINT_S = 1098;; +let _MIPS_INS_ROTR = 1099;; +let _MIPS_INS_ROTRV = 1100;; +let _MIPS_INS_ROTX = 1101;; +let _MIPS_INS_ROUND_L_D = 1102;; +let _MIPS_INS_ROUND_L_S = 1103;; +let _MIPS_INS_ROUND_W_D = 1104;; +let _MIPS_INS_ROUND_W_S = 1105;; +let _MIPS_INS_RSQRT_D = 1106;; +let _MIPS_INS_RSQRT_S = 1107;; +let _MIPS_INS_SAT_S_B = 1108;; +let _MIPS_INS_SAT_S_D = 1109;; +let _MIPS_INS_SAT_S_H = 1110;; +let _MIPS_INS_SAT_S_W = 1111;; +let _MIPS_INS_SAT_U_B = 1112;; +let _MIPS_INS_SAT_U_D = 1113;; +let _MIPS_INS_SAT_U_H = 1114;; +let _MIPS_INS_SAT_U_W = 1115;; +let _MIPS_INS_SAVE = 1116;; +let _MIPS_INS_SB = 1117;; +let _MIPS_INS_SB16 = 1118;; +let _MIPS_INS_SBE = 1119;; +let _MIPS_INS_SBX = 1120;; +let _MIPS_INS_SC = 1121;; +let _MIPS_INS_SCD = 1122;; +let _MIPS_INS_SCE = 1123;; +let _MIPS_INS_SCWP = 1124;; +let _MIPS_INS_SDBBP = 1125;; +let _MIPS_INS_SDBBP16 = 1126;; +let _MIPS_INS_SDC1 = 1127;; +let _MIPS_INS_SDC2 = 1128;; +let _MIPS_INS_SDC3 = 1129;; +let _MIPS_INS_SDL = 1130;; +let _MIPS_INS_SDR = 1131;; +let _MIPS_INS_SDXC1 = 1132;; +let _MIPS_INS_SEB = 1133;; +let _MIPS_INS_SEH = 1134;; +let _MIPS_INS_SELEQZ = 1135;; +let _MIPS_INS_SELEQZ_D = 1136;; +let _MIPS_INS_SELEQZ_S = 1137;; +let _MIPS_INS_SELNEZ = 1138;; +let _MIPS_INS_SELNEZ_D = 1139;; +let _MIPS_INS_SELNEZ_S = 1140;; +let _MIPS_INS_SEL_D = 1141;; +let _MIPS_INS_SEL_S = 1142;; +let _MIPS_INS_SEQI = 1143;; +let _MIPS_INS_SH = 1144;; +let _MIPS_INS_SH16 = 1145;; +let _MIPS_INS_SHE = 1146;; +let _MIPS_INS_SHF_B = 1147;; +let _MIPS_INS_SHF_H = 1148;; +let _MIPS_INS_SHF_W = 1149;; +let _MIPS_INS_SHILO = 1150;; +let _MIPS_INS_SHILOV = 1151;; +let _MIPS_INS_SHLLV_PH = 1152;; +let _MIPS_INS_SHLLV_QB = 1153;; +let _MIPS_INS_SHLLV_S_PH = 1154;; +let _MIPS_INS_SHLLV_S_W = 1155;; +let _MIPS_INS_SHLL_PH = 1156;; +let _MIPS_INS_SHLL_QB = 1157;; +let _MIPS_INS_SHLL_S_PH = 1158;; +let _MIPS_INS_SHLL_S_W = 1159;; +let _MIPS_INS_SHRAV_PH = 1160;; +let _MIPS_INS_SHRAV_QB = 1161;; +let _MIPS_INS_SHRAV_R_PH = 1162;; +let _MIPS_INS_SHRAV_R_QB = 1163;; +let _MIPS_INS_SHRAV_R_W = 1164;; +let _MIPS_INS_SHRA_PH = 1165;; +let _MIPS_INS_SHRA_QB = 1166;; +let _MIPS_INS_SHRA_R_PH = 1167;; +let _MIPS_INS_SHRA_R_QB = 1168;; +let _MIPS_INS_SHRA_R_W = 1169;; +let _MIPS_INS_SHRLV_PH = 1170;; +let _MIPS_INS_SHRLV_QB = 1171;; +let _MIPS_INS_SHRL_PH = 1172;; +let _MIPS_INS_SHRL_QB = 1173;; +let _MIPS_INS_SHXS = 1174;; +let _MIPS_INS_SHX = 1175;; +let _MIPS_INS_SIGRIE = 1176;; +let _MIPS_INS_SLDI_B = 1177;; +let _MIPS_INS_SLDI_D = 1178;; +let _MIPS_INS_SLDI_H = 1179;; +let _MIPS_INS_SLDI_W = 1180;; +let _MIPS_INS_SLD_B = 1181;; +let _MIPS_INS_SLD_D = 1182;; +let _MIPS_INS_SLD_H = 1183;; +let _MIPS_INS_SLD_W = 1184;; +let _MIPS_INS_SLL = 1185;; +let _MIPS_INS_SLL16 = 1186;; +let _MIPS_INS_SLLI_B = 1187;; +let _MIPS_INS_SLLI_D = 1188;; +let _MIPS_INS_SLLI_H = 1189;; +let _MIPS_INS_SLLI_W = 1190;; +let _MIPS_INS_SLLV = 1191;; +let _MIPS_INS_SLL_B = 1192;; +let _MIPS_INS_SLL_D = 1193;; +let _MIPS_INS_SLL_H = 1194;; +let _MIPS_INS_SLL_W = 1195;; +let _MIPS_INS_SLTIU = 1196;; +let _MIPS_INS_SLTI = 1197;; +let _MIPS_INS_SNEI = 1198;; +let _MIPS_INS_SOV = 1199;; +let _MIPS_INS_SPLATI_B = 1200;; +let _MIPS_INS_SPLATI_D = 1201;; +let _MIPS_INS_SPLATI_H = 1202;; +let _MIPS_INS_SPLATI_W = 1203;; +let _MIPS_INS_SPLAT_B = 1204;; +let _MIPS_INS_SPLAT_D = 1205;; +let _MIPS_INS_SPLAT_H = 1206;; +let _MIPS_INS_SPLAT_W = 1207;; +let _MIPS_INS_SRA = 1208;; +let _MIPS_INS_SRAI_B = 1209;; +let _MIPS_INS_SRAI_D = 1210;; +let _MIPS_INS_SRAI_H = 1211;; +let _MIPS_INS_SRAI_W = 1212;; +let _MIPS_INS_SRARI_B = 1213;; +let _MIPS_INS_SRARI_D = 1214;; +let _MIPS_INS_SRARI_H = 1215;; +let _MIPS_INS_SRARI_W = 1216;; +let _MIPS_INS_SRAR_B = 1217;; +let _MIPS_INS_SRAR_D = 1218;; +let _MIPS_INS_SRAR_H = 1219;; +let _MIPS_INS_SRAR_W = 1220;; +let _MIPS_INS_SRAV = 1221;; +let _MIPS_INS_SRA_B = 1222;; +let _MIPS_INS_SRA_D = 1223;; +let _MIPS_INS_SRA_H = 1224;; +let _MIPS_INS_SRA_W = 1225;; +let _MIPS_INS_SRL = 1226;; +let _MIPS_INS_SRL16 = 1227;; +let _MIPS_INS_SRLI_B = 1228;; +let _MIPS_INS_SRLI_D = 1229;; +let _MIPS_INS_SRLI_H = 1230;; +let _MIPS_INS_SRLI_W = 1231;; +let _MIPS_INS_SRLRI_B = 1232;; +let _MIPS_INS_SRLRI_D = 1233;; +let _MIPS_INS_SRLRI_H = 1234;; +let _MIPS_INS_SRLRI_W = 1235;; +let _MIPS_INS_SRLR_B = 1236;; +let _MIPS_INS_SRLR_D = 1237;; +let _MIPS_INS_SRLR_H = 1238;; +let _MIPS_INS_SRLR_W = 1239;; +let _MIPS_INS_SRLV = 1240;; +let _MIPS_INS_SRL_B = 1241;; +let _MIPS_INS_SRL_D = 1242;; +let _MIPS_INS_SRL_H = 1243;; +let _MIPS_INS_SRL_W = 1244;; +let _MIPS_INS_SSNOP = 1245;; +let _MIPS_INS_ST_B = 1246;; +let _MIPS_INS_ST_D = 1247;; +let _MIPS_INS_ST_H = 1248;; +let _MIPS_INS_ST_W = 1249;; +let _MIPS_INS_SUB = 1250;; +let _MIPS_INS_SUBQH_PH = 1251;; +let _MIPS_INS_SUBQH_R_PH = 1252;; +let _MIPS_INS_SUBQH_R_W = 1253;; +let _MIPS_INS_SUBQH_W = 1254;; +let _MIPS_INS_SUBQ_PH = 1255;; +let _MIPS_INS_SUBQ_S_PH = 1256;; +let _MIPS_INS_SUBQ_S_W = 1257;; +let _MIPS_INS_SUBSUS_U_B = 1258;; +let _MIPS_INS_SUBSUS_U_D = 1259;; +let _MIPS_INS_SUBSUS_U_H = 1260;; +let _MIPS_INS_SUBSUS_U_W = 1261;; +let _MIPS_INS_SUBSUU_S_B = 1262;; +let _MIPS_INS_SUBSUU_S_D = 1263;; +let _MIPS_INS_SUBSUU_S_H = 1264;; +let _MIPS_INS_SUBSUU_S_W = 1265;; +let _MIPS_INS_SUBS_S_B = 1266;; +let _MIPS_INS_SUBS_S_D = 1267;; +let _MIPS_INS_SUBS_S_H = 1268;; +let _MIPS_INS_SUBS_S_W = 1269;; +let _MIPS_INS_SUBS_U_B = 1270;; +let _MIPS_INS_SUBS_U_D = 1271;; +let _MIPS_INS_SUBS_U_H = 1272;; +let _MIPS_INS_SUBS_U_W = 1273;; +let _MIPS_INS_SUBU16 = 1274;; +let _MIPS_INS_SUBUH_QB = 1275;; +let _MIPS_INS_SUBUH_R_QB = 1276;; +let _MIPS_INS_SUBU_PH = 1277;; +let _MIPS_INS_SUBU_QB = 1278;; +let _MIPS_INS_SUBU_S_PH = 1279;; +let _MIPS_INS_SUBU_S_QB = 1280;; +let _MIPS_INS_SUBVI_B = 1281;; +let _MIPS_INS_SUBVI_D = 1282;; +let _MIPS_INS_SUBVI_H = 1283;; +let _MIPS_INS_SUBVI_W = 1284;; +let _MIPS_INS_SUBV_B = 1285;; +let _MIPS_INS_SUBV_D = 1286;; +let _MIPS_INS_SUBV_H = 1287;; +let _MIPS_INS_SUBV_W = 1288;; +let _MIPS_INS_SUXC1 = 1289;; +let _MIPS_INS_SW = 1290;; +let _MIPS_INS_SW16 = 1291;; +let _MIPS_INS_SWC1 = 1292;; +let _MIPS_INS_SWC2 = 1293;; +let _MIPS_INS_SWC3 = 1294;; +let _MIPS_INS_SWE = 1295;; +let _MIPS_INS_SWL = 1296;; +let _MIPS_INS_SWLE = 1297;; +let _MIPS_INS_SWM16 = 1298;; +let _MIPS_INS_SWM32 = 1299;; +let _MIPS_INS_SWPC = 1300;; +let _MIPS_INS_SWP = 1301;; +let _MIPS_INS_SWR = 1302;; +let _MIPS_INS_SWRE = 1303;; +let _MIPS_INS_SWSP = 1304;; +let _MIPS_INS_SWXC1 = 1305;; +let _MIPS_INS_SWXS = 1306;; +let _MIPS_INS_SWX = 1307;; +let _MIPS_INS_SYNC = 1308;; +let _MIPS_INS_SYNCI = 1309;; +let _MIPS_INS_SYSCALL = 1310;; +let _MIPS_INS_TEQ = 1311;; +let _MIPS_INS_TEQI = 1312;; +let _MIPS_INS_TGE = 1313;; +let _MIPS_INS_TGEI = 1314;; +let _MIPS_INS_TGEIU = 1315;; +let _MIPS_INS_TGEU = 1316;; +let _MIPS_INS_TLBGINV = 1317;; +let _MIPS_INS_TLBGINVF = 1318;; +let _MIPS_INS_TLBGP = 1319;; +let _MIPS_INS_TLBGR = 1320;; +let _MIPS_INS_TLBGWI = 1321;; +let _MIPS_INS_TLBGWR = 1322;; +let _MIPS_INS_TLBINV = 1323;; +let _MIPS_INS_TLBINVF = 1324;; +let _MIPS_INS_TLBP = 1325;; +let _MIPS_INS_TLBR = 1326;; +let _MIPS_INS_TLBWI = 1327;; +let _MIPS_INS_TLBWR = 1328;; +let _MIPS_INS_TLT = 1329;; +let _MIPS_INS_TLTI = 1330;; +let _MIPS_INS_TLTIU = 1331;; +let _MIPS_INS_TLTU = 1332;; +let _MIPS_INS_TNE = 1333;; +let _MIPS_INS_TNEI = 1334;; +let _MIPS_INS_TRUNC_L_D = 1335;; +let _MIPS_INS_TRUNC_L_S = 1336;; +let _MIPS_INS_UALH = 1337;; +let _MIPS_INS_UALWM = 1338;; +let _MIPS_INS_UALW = 1339;; +let _MIPS_INS_UASH = 1340;; +let _MIPS_INS_UASWM = 1341;; +let _MIPS_INS_UASW = 1342;; +let _MIPS_INS_V3MULU = 1343;; +let _MIPS_INS_VMM0 = 1344;; +let _MIPS_INS_VMULU = 1345;; +let _MIPS_INS_VSHF_B = 1346;; +let _MIPS_INS_VSHF_D = 1347;; +let _MIPS_INS_VSHF_H = 1348;; +let _MIPS_INS_VSHF_W = 1349;; +let _MIPS_INS_WAIT = 1350;; +let _MIPS_INS_WRDSP = 1351;; +let _MIPS_INS_WRPGPR = 1352;; +let _MIPS_INS_WSBH = 1353;; +let _MIPS_INS_XOR = 1354;; +let _MIPS_INS_XOR16 = 1355;; +let _MIPS_INS_XORI_B = 1356;; +let _MIPS_INS_XORI = 1357;; +let _MIPS_INS_XOR_V = 1358;; +let _MIPS_INS_YIELD = 1359;; +let _MIPS_INS_ENDING = 1360;; +let _MIPS_INS_ALIAS_BEGIN = 1361;; +let _MIPS_INS_ALIAS_ADDIU_B32 = 1362;; +let _MIPS_INS_ALIAS_BITREVB = 1363;; +let _MIPS_INS_ALIAS_BITREVH = 1364;; +let _MIPS_INS_ALIAS_BYTEREVH = 1365;; +let _MIPS_INS_ALIAS_NOT = 1366;; +let _MIPS_INS_ALIAS_RESTORE_JRC = 1367;; +let _MIPS_INS_ALIAS_RESTORE = 1368;; +let _MIPS_INS_ALIAS_SAVE = 1369;; +let _MIPS_INS_ALIAS_MOVE = 1370;; +let _MIPS_INS_ALIAS_BAL = 1371;; +let _MIPS_INS_ALIAS_JALR_HB = 1372;; +let _MIPS_INS_ALIAS_NEG = 1373;; +let _MIPS_INS_ALIAS_NEGU = 1374;; +let _MIPS_INS_ALIAS_NOP = 1375;; +let _MIPS_INS_ALIAS_BNEZL = 1376;; +let _MIPS_INS_ALIAS_BEQZL = 1377;; +let _MIPS_INS_ALIAS_SYSCALL = 1378;; +let _MIPS_INS_ALIAS_BREAK = 1379;; +let _MIPS_INS_ALIAS_EI = 1380;; +let _MIPS_INS_ALIAS_DI = 1381;; +let _MIPS_INS_ALIAS_TEQ = 1382;; +let _MIPS_INS_ALIAS_TGE = 1383;; +let _MIPS_INS_ALIAS_TGEU = 1384;; +let _MIPS_INS_ALIAS_TLT = 1385;; +let _MIPS_INS_ALIAS_TLTU = 1386;; +let _MIPS_INS_ALIAS_TNE = 1387;; +let _MIPS_INS_ALIAS_RDHWR = 1388;; +let _MIPS_INS_ALIAS_SDBBP = 1389;; +let _MIPS_INS_ALIAS_SYNC = 1390;; +let _MIPS_INS_ALIAS_HYPCALL = 1391;; +let _MIPS_INS_ALIAS_NOR = 1392;; +let _MIPS_INS_ALIAS_C_F_S = 1393;; +let _MIPS_INS_ALIAS_C_UN_S = 1394;; +let _MIPS_INS_ALIAS_C_EQ_S = 1395;; +let _MIPS_INS_ALIAS_C_UEQ_S = 1396;; +let _MIPS_INS_ALIAS_C_OLT_S = 1397;; +let _MIPS_INS_ALIAS_C_ULT_S = 1398;; +let _MIPS_INS_ALIAS_C_OLE_S = 1399;; +let _MIPS_INS_ALIAS_C_ULE_S = 1400;; +let _MIPS_INS_ALIAS_C_SF_S = 1401;; +let _MIPS_INS_ALIAS_C_NGLE_S = 1402;; +let _MIPS_INS_ALIAS_C_SEQ_S = 1403;; +let _MIPS_INS_ALIAS_C_NGL_S = 1404;; +let _MIPS_INS_ALIAS_C_LT_S = 1405;; +let _MIPS_INS_ALIAS_C_NGE_S = 1406;; +let _MIPS_INS_ALIAS_C_LE_S = 1407;; +let _MIPS_INS_ALIAS_C_NGT_S = 1408;; +let _MIPS_INS_ALIAS_BC1T = 1409;; +let _MIPS_INS_ALIAS_BC1F = 1410;; +let _MIPS_INS_ALIAS_C_F_D = 1411;; +let _MIPS_INS_ALIAS_C_UN_D = 1412;; +let _MIPS_INS_ALIAS_C_EQ_D = 1413;; +let _MIPS_INS_ALIAS_C_UEQ_D = 1414;; +let _MIPS_INS_ALIAS_C_OLT_D = 1415;; +let _MIPS_INS_ALIAS_C_ULT_D = 1416;; +let _MIPS_INS_ALIAS_C_OLE_D = 1417;; +let _MIPS_INS_ALIAS_C_ULE_D = 1418;; +let _MIPS_INS_ALIAS_C_SF_D = 1419;; +let _MIPS_INS_ALIAS_C_NGLE_D = 1420;; +let _MIPS_INS_ALIAS_C_SEQ_D = 1421;; +let _MIPS_INS_ALIAS_C_NGL_D = 1422;; +let _MIPS_INS_ALIAS_C_LT_D = 1423;; +let _MIPS_INS_ALIAS_C_NGE_D = 1424;; +let _MIPS_INS_ALIAS_C_LE_D = 1425;; +let _MIPS_INS_ALIAS_C_NGT_D = 1426;; +let _MIPS_INS_ALIAS_BC1TL = 1427;; +let _MIPS_INS_ALIAS_BC1FL = 1428;; +let _MIPS_INS_ALIAS_DNEG = 1429;; +let _MIPS_INS_ALIAS_DNEGU = 1430;; +let _MIPS_INS_ALIAS_SLT = 1431;; +let _MIPS_INS_ALIAS_SLTU = 1432;; +let _MIPS_INS_ALIAS_SIGRIE = 1433;; +let _MIPS_INS_ALIAS_JR = 1434;; +let _MIPS_INS_ALIAS_JRC = 1435;; +let _MIPS_INS_ALIAS_JALRC = 1436;; +let _MIPS_INS_ALIAS_DIV = 1437;; +let _MIPS_INS_ALIAS_DIVU = 1438;; +let _MIPS_INS_ALIAS_LAPC = 1439;; +let _MIPS_INS_ALIAS_WRDSP = 1440;; +let _MIPS_INS_ALIAS_WAIT = 1441;; +let _MIPS_INS_ALIAS_SW = 1442;; +let _MIPS_INS_ALIAS_JALRC_HB = 1443;; +let _MIPS_INS_ALIAS_ADDIU_B = 1444;; +let _MIPS_INS_ALIAS_ADDIU_W = 1445;; +let _MIPS_INS_ALIAS_JRC_HB = 1446;; +let _MIPS_INS_ALIAS_BEQC = 1447;; +let _MIPS_INS_ALIAS_BNEC = 1448;; +let _MIPS_INS_ALIAS_BEQZC = 1449;; +let _MIPS_INS_ALIAS_BNEZC = 1450;; +let _MIPS_INS_ALIAS_MFC0 = 1451;; +let _MIPS_INS_ALIAS_MFHC0 = 1452;; +let _MIPS_INS_ALIAS_MTC0 = 1453;; +let _MIPS_INS_ALIAS_MTHC0 = 1454;; +let _MIPS_INS_ALIAS_DMT = 1455;; +let _MIPS_INS_ALIAS_EMT = 1456;; +let _MIPS_INS_ALIAS_DVPE = 1457;; +let _MIPS_INS_ALIAS_EVPE = 1458;; +let _MIPS_INS_ALIAS_YIELD = 1459;; +let _MIPS_INS_ALIAS_MFTC0 = 1460;; +let _MIPS_INS_ALIAS_MFTLO = 1461;; +let _MIPS_INS_ALIAS_MFTHI = 1462;; +let _MIPS_INS_ALIAS_MFTACX = 1463;; +let _MIPS_INS_ALIAS_MTTC0 = 1464;; +let _MIPS_INS_ALIAS_MTTLO = 1465;; +let _MIPS_INS_ALIAS_MTTHI = 1466;; +let _MIPS_INS_ALIAS_MTTACX = 1467;; +let _MIPS_INS_ALIAS_END = 1468;; let _MIPS_GRP_INVALID = 0;; let _MIPS_GRP_JUMP = 1;; @@ -825,37 +2120,60 @@ let _MIPS_GRP_INT = 4;; let _MIPS_GRP_IRET = 5;; let _MIPS_GRP_PRIVILEGE = 6;; let _MIPS_GRP_BRANCH_RELATIVE = 7;; -let _MIPS_GRP_BITCOUNT = 128;; -let _MIPS_GRP_DSP = 129;; -let _MIPS_GRP_DSPR2 = 130;; -let _MIPS_GRP_FPIDX = 131;; -let _MIPS_GRP_MSA = 132;; -let _MIPS_GRP_MIPS32R2 = 133;; -let _MIPS_GRP_MIPS64 = 134;; -let _MIPS_GRP_MIPS64R2 = 135;; -let _MIPS_GRP_SEINREG = 136;; -let _MIPS_GRP_STDENC = 137;; -let _MIPS_GRP_SWAP = 138;; -let _MIPS_GRP_MICROMIPS = 139;; -let _MIPS_GRP_MIPS16MODE = 140;; -let _MIPS_GRP_FP64BIT = 141;; -let _MIPS_GRP_NONANSFPMATH = 142;; -let _MIPS_GRP_NOTFP64BIT = 143;; -let _MIPS_GRP_NOTINMICROMIPS = 144;; -let _MIPS_GRP_NOTNACL = 145;; -let _MIPS_GRP_NOTMIPS32R6 = 146;; -let _MIPS_GRP_NOTMIPS64R6 = 147;; -let _MIPS_GRP_CNMIPS = 148;; -let _MIPS_GRP_MIPS32 = 149;; -let _MIPS_GRP_MIPS32R6 = 150;; -let _MIPS_GRP_MIPS64R6 = 151;; -let _MIPS_GRP_MIPS2 = 152;; -let _MIPS_GRP_MIPS3 = 153;; -let _MIPS_GRP_MIPS3_32 = 154;; -let _MIPS_GRP_MIPS3_32R2 = 155;; -let _MIPS_GRP_MIPS4_32 = 156;; -let _MIPS_GRP_MIPS4_32R2 = 157;; -let _MIPS_GRP_MIPS5_32R2 = 158;; -let _MIPS_GRP_GP32BIT = 159;; -let _MIPS_GRP_GP64BIT = 160;; -let _MIPS_GRP_ENDING = 161;; +let _MIPS_FEATURE_HASMIPS2 = 128;; +let _MIPS_FEATURE_HASMIPS3_32 = 129;; +let _MIPS_FEATURE_HASMIPS3_32R2 = 130;; +let _MIPS_FEATURE_HASMIPS3 = 131;; +let _MIPS_FEATURE_NOTMIPS3 = 132;; +let _MIPS_FEATURE_HASMIPS4_32 = 133;; +let _MIPS_FEATURE_NOTMIPS4_32 = 134;; +let _MIPS_FEATURE_HASMIPS4_32R2 = 135;; +let _MIPS_FEATURE_HASMIPS5_32R2 = 136;; +let _MIPS_FEATURE_HASMIPS32 = 137;; +let _MIPS_FEATURE_HASMIPS32R2 = 138;; +let _MIPS_FEATURE_HASMIPS32R5 = 139;; +let _MIPS_FEATURE_HASMIPS32R6 = 140;; +let _MIPS_FEATURE_NOTMIPS32R6 = 141;; +let _MIPS_FEATURE_HASNANOMIPS = 142;; +let _MIPS_FEATURE_NOTNANOMIPS = 143;; +let _MIPS_FEATURE_ISGP64BIT = 144;; +let _MIPS_FEATURE_ISGP32BIT = 145;; +let _MIPS_FEATURE_ISPTR64BIT = 146;; +let _MIPS_FEATURE_ISPTR32BIT = 147;; +let _MIPS_FEATURE_HASMIPS64 = 148;; +let _MIPS_FEATURE_NOTMIPS64 = 149;; +let _MIPS_FEATURE_HASMIPS64R2 = 150;; +let _MIPS_FEATURE_HASMIPS64R5 = 151;; +let _MIPS_FEATURE_HASMIPS64R6 = 152;; +let _MIPS_FEATURE_NOTMIPS64R6 = 153;; +let _MIPS_FEATURE_INMIPS16MODE = 154;; +let _MIPS_FEATURE_NOTINMIPS16MODE = 155;; +let _MIPS_FEATURE_HASCNMIPS = 156;; +let _MIPS_FEATURE_NOTCNMIPS = 157;; +let _MIPS_FEATURE_HASCNMIPSP = 158;; +let _MIPS_FEATURE_NOTCNMIPSP = 159;; +let _MIPS_FEATURE_ISSYM32 = 160;; +let _MIPS_FEATURE_ISSYM64 = 161;; +let _MIPS_FEATURE_HASSTDENC = 162;; +let _MIPS_FEATURE_INMICROMIPS = 163;; +let _MIPS_FEATURE_NOTINMICROMIPS = 164;; +let _MIPS_FEATURE_HASEVA = 165;; +let _MIPS_FEATURE_HASMSA = 166;; +let _MIPS_FEATURE_HASMADD4 = 167;; +let _MIPS_FEATURE_HASMT = 168;; +let _MIPS_FEATURE_USEINDIRECTJUMPSHAZARD = 169;; +let _MIPS_FEATURE_NOINDIRECTJUMPGUARDS = 170;; +let _MIPS_FEATURE_HASCRC = 171;; +let _MIPS_FEATURE_HASVIRT = 172;; +let _MIPS_FEATURE_HASGINV = 173;; +let _MIPS_FEATURE_HASTLB = 174;; +let _MIPS_FEATURE_ISFP64BIT = 175;; +let _MIPS_FEATURE_NOTFP64BIT = 176;; +let _MIPS_FEATURE_ISSINGLEFLOAT = 177;; +let _MIPS_FEATURE_ISNOTSINGLEFLOAT = 178;; +let _MIPS_FEATURE_ISNOTSOFTFLOAT = 179;; +let _MIPS_FEATURE_HASMIPS3D = 180;; +let _MIPS_FEATURE_HASDSP = 181;; +let _MIPS_FEATURE_HASDSPR2 = 182;; +let _MIPS_FEATURE_HASDSPR3 = 183;; +let _MIPS_GRP_ENDING = 184;; diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index f70c6e96e..b0102485f 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -51,24 +51,44 @@ __all__ = [ 'CS_MODE_ARM', 'CS_MODE_THUMB', 'CS_MODE_MCLASS', - 'CS_MODE_MICRO', - 'CS_MODE_MIPS3', - 'CS_MODE_MIPS32R6', - 'CS_MODE_MIPS2', 'CS_MODE_V8', 'CS_MODE_V9', 'CS_MODE_QPX', 'CS_MODE_SPE', 'CS_MODE_BOOKE', 'CS_MODE_PS', + 'CS_MODE_MIPS16', + 'CS_MODE_MIPS32', + 'CS_MODE_MIPS64', + 'CS_MODE_MICRO', + 'CS_MODE_MIPS1', + 'CS_MODE_MIPS2', + 'CS_MODE_MIPS32R2', + 'CS_MODE_MIPS32R3', + 'CS_MODE_MIPS32R5', + 'CS_MODE_MIPS32R6', + 'CS_MODE_MIPS3', + 'CS_MODE_MIPS4', + 'CS_MODE_MIPS5', + 'CS_MODE_MIPS64R2', + 'CS_MODE_MIPS64R3', + 'CS_MODE_MIPS64R5', + 'CS_MODE_MIPS64R6', + 'CS_MODE_OCTEON', + 'CS_MODE_OCTEONP', + 'CS_MODE_NANOMIPS', + 'CS_MODE_NMS1', + 'CS_MODE_I7200', + 'CS_MODE_MIPS_NOFLOAT', + 'CS_MODE_MIPS_PTR64', + 'CS_MODE_MICRO32R3', + 'CS_MODE_MICRO32R6', 'CS_MODE_M68K_000', 'CS_MODE_M68K_010', 'CS_MODE_M68K_020', 'CS_MODE_M68K_030', 'CS_MODE_M68K_040', 'CS_MODE_M68K_060', - 'CS_MODE_MIPS32', - 'CS_MODE_MIPS64', 'CS_MODE_M680X_6301', 'CS_MODE_M680X_6309', 'CS_MODE_M680X_6800', @@ -119,8 +139,10 @@ __all__ = [ 'CS_OPT_SYNTAX_MASM', 'CS_OPT_SYNTAX_MOTOROLA', 'CS_OPT_SYNTAX_CS_REG_ALIAS', + 'CS_OPT_SYNTAX_NO_DOLLAR', 'CS_OPT_DETAIL', + 'CS_OPT_DETAIL_REAL', 'CS_OPT_MODE', 'CS_OPT_ON', 'CS_OPT_OFF', @@ -257,8 +279,32 @@ CS_MODE_M68K_030 = (1 << 4) # M68K 68030 mode CS_MODE_M68K_040 = (1 << 5) # M68K 68040 mode CS_MODE_M68K_060 = (1 << 6) # M68K 68060 mode CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode -CS_MODE_MIPS32 = CS_MODE_32 # Mips32 ISA -CS_MODE_MIPS64 = CS_MODE_64 # Mips64 ISA +CS_MODE_MIPS16 = CS_MODE_16 # Generic mips16 +CS_MODE_MIPS32 = CS_MODE_32 # Generic mips32 +CS_MODE_MIPS64 = CS_MODE_64 # Generic mips64 +CS_MODE_MICRO = 1 << 4 # microMips +CS_MODE_MIPS1 = 1 << 5 # Mips I ISA Support +CS_MODE_MIPS2 = 1 << 6 # Mips II ISA Support +CS_MODE_MIPS32R2 = 1 << 7 # Mips32r2 ISA Support +CS_MODE_MIPS32R3 = 1 << 8 # Mips32r3 ISA Support +CS_MODE_MIPS32R5 = 1 << 9 # Mips32r5 ISA Support +CS_MODE_MIPS32R6 = 1 << 10 # Mips32r6 ISA Support +CS_MODE_MIPS3 = 1 << 11 # MIPS III ISA Support +CS_MODE_MIPS4 = 1 << 12 # MIPS IV ISA Support +CS_MODE_MIPS5 = 1 << 13 # MIPS V ISA Support +CS_MODE_MIPS64R2 = 1 << 14 # Mips64r2 ISA Support +CS_MODE_MIPS64R3 = 1 << 15 # Mips64r3 ISA Support +CS_MODE_MIPS64R5 = 1 << 16 # Mips64r5 ISA Support +CS_MODE_MIPS64R6 = 1 << 17 # Mips64r6 ISA Support +CS_MODE_OCTEON = 1 << 18 # Octeon cnMIPS Support +CS_MODE_OCTEONP = 1 << 19 # Octeon+ cnMIPS Support +CS_MODE_NANOMIPS = 1 << 20 # Generic nanomips +CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS) # nanoMips NMS1 +CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS) # nanoMips I7200 +CS_MODE_MIPS_NOFLOAT = 1 << 23 # Disable floating points ops +CS_MODE_MIPS_PTR64 = 1 << 24 # Mips pointers are 64-bit +CS_MODE_MICRO32R3 = (CS_MODE_MICRO | CS_MODE_MIPS32R3) # microMips32r3 +CS_MODE_MICRO32R6 = (CS_MODE_MICRO | CS_MODE_MIPS32R6) # microMips32r6 CS_MODE_M680X_6301 = (1 << 1) # M680X HD6301/3 mode CS_MODE_M680X_6309 = (1 << 2) # M680X HD6309 mode CS_MODE_M680X_6800 = (1 << 3) # M680X M6800/2 mode @@ -364,6 +410,7 @@ CS_OPT_SYNTAX_MASM = (1 << 5) # MASM syntax (CS_OPT_SYNTAX, CS_ARCH_X86) CS_OPT_SYNTAX_MOTOROLA = (1 << 6) # MOS65XX use $ as hex prefix CS_OPT_SYNTAX_CS_REG_ALIAS = (1 << 7) # Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.) CS_OPT_SYNTAX_PERCENT = (1 << 8) # Prints the % in front of PPC registers. +CS_OPT_SYNTAX_NO_DOLLAR = (1 << 9) # Does not print the $ in front of Mips registers. CS_OPT_DETAIL_REAL = (1 << 1) # If enabled, always sets the real instruction detail.Even if the instruction is an alias. # Capstone error type @@ -501,7 +548,7 @@ class _cs_detail(ctypes.Structure): ('regs_read_count', ctypes.c_ubyte), ('regs_write', ctypes.c_uint16 * 47), ('regs_write_count', ctypes.c_ubyte), - ('groups', ctypes.c_ubyte * 8), + ('groups', ctypes.c_ubyte * 16), ('groups_count', ctypes.c_ubyte), ('writeback', ctypes.c_bool), ('arch', _cs_arch), diff --git a/bindings/python/capstone/mips.py b/bindings/python/capstone/mips.py index 44513d252..df54fec22 100644 --- a/bindings/python/capstone/mips.py +++ b/bindings/python/capstone/mips.py @@ -15,6 +15,7 @@ class MipsOpValue(ctypes.Union): _fields_ = ( ('reg', ctypes.c_uint), ('imm', ctypes.c_int64), + ('uimm', ctypes.c_uint64), ('mem', MipsOpMem), ) @@ -22,6 +23,9 @@ class MipsOp(ctypes.Structure): _fields_ = ( ('type', ctypes.c_uint), ('value', MipsOpValue), + ('is_reglist', ctypes.c_bool), + ('is_unsigned', ctypes.c_bool), + ('access', ctypes.c_uint8), ) @property diff --git a/bindings/python/capstone/mips_const.py b/bindings/python/capstone/mips_const.py index f3f2f7388..b48b4ac55 100644 --- a/bindings/python/capstone/mips_const.py +++ b/bindings/python/capstone/mips_const.py @@ -7,816 +7,2111 @@ MIPS_OP_IMM = 2 MIPS_OP_MEM = 3 MIPS_REG_INVALID = 0 -MIPS_REG_PC = 1 -MIPS_REG_0 = 2 -MIPS_REG_1 = 3 -MIPS_REG_2 = 4 -MIPS_REG_3 = 5 -MIPS_REG_4 = 6 -MIPS_REG_5 = 7 -MIPS_REG_6 = 8 -MIPS_REG_7 = 9 -MIPS_REG_8 = 10 -MIPS_REG_9 = 11 -MIPS_REG_10 = 12 -MIPS_REG_11 = 13 -MIPS_REG_12 = 14 -MIPS_REG_13 = 15 -MIPS_REG_14 = 16 -MIPS_REG_15 = 17 -MIPS_REG_16 = 18 -MIPS_REG_17 = 19 -MIPS_REG_18 = 20 -MIPS_REG_19 = 21 -MIPS_REG_20 = 22 -MIPS_REG_21 = 23 -MIPS_REG_22 = 24 -MIPS_REG_23 = 25 -MIPS_REG_24 = 26 -MIPS_REG_25 = 27 -MIPS_REG_26 = 28 -MIPS_REG_27 = 29 -MIPS_REG_28 = 30 -MIPS_REG_29 = 31 -MIPS_REG_30 = 32 -MIPS_REG_31 = 33 -MIPS_REG_DSPCCOND = 34 -MIPS_REG_DSPCARRY = 35 -MIPS_REG_DSPEFI = 36 -MIPS_REG_DSPOUTFLAG = 37 -MIPS_REG_DSPOUTFLAG16_19 = 38 -MIPS_REG_DSPOUTFLAG20 = 39 -MIPS_REG_DSPOUTFLAG21 = 40 -MIPS_REG_DSPOUTFLAG22 = 41 -MIPS_REG_DSPOUTFLAG23 = 42 -MIPS_REG_DSPPOS = 43 -MIPS_REG_DSPSCOUNT = 44 -MIPS_REG_AC0 = 45 -MIPS_REG_AC1 = 46 -MIPS_REG_AC2 = 47 -MIPS_REG_AC3 = 48 -MIPS_REG_CC0 = 49 -MIPS_REG_CC1 = 50 -MIPS_REG_CC2 = 51 -MIPS_REG_CC3 = 52 -MIPS_REG_CC4 = 53 -MIPS_REG_CC5 = 54 -MIPS_REG_CC6 = 55 -MIPS_REG_CC7 = 56 -MIPS_REG_F0 = 57 -MIPS_REG_F1 = 58 -MIPS_REG_F2 = 59 -MIPS_REG_F3 = 60 -MIPS_REG_F4 = 61 -MIPS_REG_F5 = 62 -MIPS_REG_F6 = 63 -MIPS_REG_F7 = 64 -MIPS_REG_F8 = 65 -MIPS_REG_F9 = 66 -MIPS_REG_F10 = 67 -MIPS_REG_F11 = 68 -MIPS_REG_F12 = 69 -MIPS_REG_F13 = 70 -MIPS_REG_F14 = 71 -MIPS_REG_F15 = 72 -MIPS_REG_F16 = 73 -MIPS_REG_F17 = 74 -MIPS_REG_F18 = 75 -MIPS_REG_F19 = 76 -MIPS_REG_F20 = 77 -MIPS_REG_F21 = 78 -MIPS_REG_F22 = 79 -MIPS_REG_F23 = 80 -MIPS_REG_F24 = 81 -MIPS_REG_F25 = 82 -MIPS_REG_F26 = 83 -MIPS_REG_F27 = 84 -MIPS_REG_F28 = 85 -MIPS_REG_F29 = 86 -MIPS_REG_F30 = 87 -MIPS_REG_F31 = 88 -MIPS_REG_FCC0 = 89 -MIPS_REG_FCC1 = 90 -MIPS_REG_FCC2 = 91 -MIPS_REG_FCC3 = 92 -MIPS_REG_FCC4 = 93 -MIPS_REG_FCC5 = 94 -MIPS_REG_FCC6 = 95 -MIPS_REG_FCC7 = 96 -MIPS_REG_W0 = 97 -MIPS_REG_W1 = 98 -MIPS_REG_W2 = 99 -MIPS_REG_W3 = 100 -MIPS_REG_W4 = 101 -MIPS_REG_W5 = 102 -MIPS_REG_W6 = 103 -MIPS_REG_W7 = 104 -MIPS_REG_W8 = 105 -MIPS_REG_W9 = 106 -MIPS_REG_W10 = 107 -MIPS_REG_W11 = 108 -MIPS_REG_W12 = 109 -MIPS_REG_W13 = 110 -MIPS_REG_W14 = 111 -MIPS_REG_W15 = 112 -MIPS_REG_W16 = 113 -MIPS_REG_W17 = 114 -MIPS_REG_W18 = 115 -MIPS_REG_W19 = 116 -MIPS_REG_W20 = 117 -MIPS_REG_W21 = 118 -MIPS_REG_W22 = 119 -MIPS_REG_W23 = 120 -MIPS_REG_W24 = 121 -MIPS_REG_W25 = 122 -MIPS_REG_W26 = 123 -MIPS_REG_W27 = 124 -MIPS_REG_W28 = 125 -MIPS_REG_W29 = 126 -MIPS_REG_W30 = 127 -MIPS_REG_W31 = 128 -MIPS_REG_HI = 129 -MIPS_REG_LO = 130 -MIPS_REG_P0 = 131 -MIPS_REG_P1 = 132 -MIPS_REG_P2 = 133 -MIPS_REG_MPL0 = 134 -MIPS_REG_MPL1 = 135 -MIPS_REG_MPL2 = 136 -MIPS_REG_ENDING = 137 -MIPS_REG_ZERO = MIPS_REG_0 -MIPS_REG_AT = MIPS_REG_1 -MIPS_REG_V0 = MIPS_REG_2 -MIPS_REG_V1 = MIPS_REG_3 -MIPS_REG_A0 = MIPS_REG_4 -MIPS_REG_A1 = MIPS_REG_5 -MIPS_REG_A2 = MIPS_REG_6 -MIPS_REG_A3 = MIPS_REG_7 -MIPS_REG_T0 = MIPS_REG_8 -MIPS_REG_T1 = MIPS_REG_9 -MIPS_REG_T2 = MIPS_REG_10 -MIPS_REG_T3 = MIPS_REG_11 -MIPS_REG_T4 = MIPS_REG_12 -MIPS_REG_T5 = MIPS_REG_13 -MIPS_REG_T6 = MIPS_REG_14 -MIPS_REG_T7 = MIPS_REG_15 -MIPS_REG_S0 = MIPS_REG_16 -MIPS_REG_S1 = MIPS_REG_17 -MIPS_REG_S2 = MIPS_REG_18 -MIPS_REG_S3 = MIPS_REG_19 -MIPS_REG_S4 = MIPS_REG_20 -MIPS_REG_S5 = MIPS_REG_21 -MIPS_REG_S6 = MIPS_REG_22 -MIPS_REG_S7 = MIPS_REG_23 -MIPS_REG_T8 = MIPS_REG_24 -MIPS_REG_T9 = MIPS_REG_25 -MIPS_REG_K0 = MIPS_REG_26 -MIPS_REG_K1 = MIPS_REG_27 -MIPS_REG_GP = MIPS_REG_28 -MIPS_REG_SP = MIPS_REG_29 -MIPS_REG_FP = MIPS_REG_30 -MIPS_REG_S8 = MIPS_REG_30 -MIPS_REG_RA = MIPS_REG_31 -MIPS_REG_HI0 = MIPS_REG_AC0 -MIPS_REG_HI1 = MIPS_REG_AC1 -MIPS_REG_HI2 = MIPS_REG_AC2 -MIPS_REG_HI3 = MIPS_REG_AC3 -MIPS_REG_LO0 = MIPS_REG_HI0 -MIPS_REG_LO1 = MIPS_REG_HI1 -MIPS_REG_LO2 = MIPS_REG_HI2 -MIPS_REG_LO3 = MIPS_REG_HI3 +MIPS_REG_AT = 1 +MIPS_REG_AT_NM = 2 +MIPS_REG_DSPCCOND = 3 +MIPS_REG_DSPCARRY = 4 +MIPS_REG_DSPEFI = 5 +MIPS_REG_DSPOUTFLAG = 6 +MIPS_REG_DSPPOS = 7 +MIPS_REG_DSPSCOUNT = 8 +MIPS_REG_FP = 9 +MIPS_REG_FP_NM = 10 +MIPS_REG_GP = 11 +MIPS_REG_GP_NM = 12 +MIPS_REG_MSAACCESS = 13 +MIPS_REG_MSACSR = 14 +MIPS_REG_MSAIR = 15 +MIPS_REG_MSAMAP = 16 +MIPS_REG_MSAMODIFY = 17 +MIPS_REG_MSAREQUEST = 18 +MIPS_REG_MSASAVE = 19 +MIPS_REG_MSAUNMAP = 20 +MIPS_REG_PC = 21 +MIPS_REG_RA = 22 +MIPS_REG_RA_NM = 23 +MIPS_REG_SP = 24 +MIPS_REG_SP_NM = 25 +MIPS_REG_ZERO = 26 +MIPS_REG_ZERO_NM = 27 +MIPS_REG_A0 = 28 +MIPS_REG_A1 = 29 +MIPS_REG_A2 = 30 +MIPS_REG_A3 = 31 +MIPS_REG_AC0 = 32 +MIPS_REG_AC1 = 33 +MIPS_REG_AC2 = 34 +MIPS_REG_AC3 = 35 +MIPS_REG_AT_64 = 36 +MIPS_REG_COP00 = 37 +MIPS_REG_COP01 = 38 +MIPS_REG_COP02 = 39 +MIPS_REG_COP03 = 40 +MIPS_REG_COP04 = 41 +MIPS_REG_COP05 = 42 +MIPS_REG_COP06 = 43 +MIPS_REG_COP07 = 44 +MIPS_REG_COP08 = 45 +MIPS_REG_COP09 = 46 +MIPS_REG_COP20 = 47 +MIPS_REG_COP21 = 48 +MIPS_REG_COP22 = 49 +MIPS_REG_COP23 = 50 +MIPS_REG_COP24 = 51 +MIPS_REG_COP25 = 52 +MIPS_REG_COP26 = 53 +MIPS_REG_COP27 = 54 +MIPS_REG_COP28 = 55 +MIPS_REG_COP29 = 56 +MIPS_REG_COP30 = 57 +MIPS_REG_COP31 = 58 +MIPS_REG_COP32 = 59 +MIPS_REG_COP33 = 60 +MIPS_REG_COP34 = 61 +MIPS_REG_COP35 = 62 +MIPS_REG_COP36 = 63 +MIPS_REG_COP37 = 64 +MIPS_REG_COP38 = 65 +MIPS_REG_COP39 = 66 +MIPS_REG_COP010 = 67 +MIPS_REG_COP011 = 68 +MIPS_REG_COP012 = 69 +MIPS_REG_COP013 = 70 +MIPS_REG_COP014 = 71 +MIPS_REG_COP015 = 72 +MIPS_REG_COP016 = 73 +MIPS_REG_COP017 = 74 +MIPS_REG_COP018 = 75 +MIPS_REG_COP019 = 76 +MIPS_REG_COP020 = 77 +MIPS_REG_COP021 = 78 +MIPS_REG_COP022 = 79 +MIPS_REG_COP023 = 80 +MIPS_REG_COP024 = 81 +MIPS_REG_COP025 = 82 +MIPS_REG_COP026 = 83 +MIPS_REG_COP027 = 84 +MIPS_REG_COP028 = 85 +MIPS_REG_COP029 = 86 +MIPS_REG_COP030 = 87 +MIPS_REG_COP031 = 88 +MIPS_REG_COP210 = 89 +MIPS_REG_COP211 = 90 +MIPS_REG_COP212 = 91 +MIPS_REG_COP213 = 92 +MIPS_REG_COP214 = 93 +MIPS_REG_COP215 = 94 +MIPS_REG_COP216 = 95 +MIPS_REG_COP217 = 96 +MIPS_REG_COP218 = 97 +MIPS_REG_COP219 = 98 +MIPS_REG_COP220 = 99 +MIPS_REG_COP221 = 100 +MIPS_REG_COP222 = 101 +MIPS_REG_COP223 = 102 +MIPS_REG_COP224 = 103 +MIPS_REG_COP225 = 104 +MIPS_REG_COP226 = 105 +MIPS_REG_COP227 = 106 +MIPS_REG_COP228 = 107 +MIPS_REG_COP229 = 108 +MIPS_REG_COP230 = 109 +MIPS_REG_COP231 = 110 +MIPS_REG_COP310 = 111 +MIPS_REG_COP311 = 112 +MIPS_REG_COP312 = 113 +MIPS_REG_COP313 = 114 +MIPS_REG_COP314 = 115 +MIPS_REG_COP315 = 116 +MIPS_REG_COP316 = 117 +MIPS_REG_COP317 = 118 +MIPS_REG_COP318 = 119 +MIPS_REG_COP319 = 120 +MIPS_REG_COP320 = 121 +MIPS_REG_COP321 = 122 +MIPS_REG_COP322 = 123 +MIPS_REG_COP323 = 124 +MIPS_REG_COP324 = 125 +MIPS_REG_COP325 = 126 +MIPS_REG_COP326 = 127 +MIPS_REG_COP327 = 128 +MIPS_REG_COP328 = 129 +MIPS_REG_COP329 = 130 +MIPS_REG_COP330 = 131 +MIPS_REG_COP331 = 132 +MIPS_REG_D0 = 133 +MIPS_REG_D1 = 134 +MIPS_REG_D2 = 135 +MIPS_REG_D3 = 136 +MIPS_REG_D4 = 137 +MIPS_REG_D5 = 138 +MIPS_REG_D6 = 139 +MIPS_REG_D7 = 140 +MIPS_REG_D8 = 141 +MIPS_REG_D9 = 142 +MIPS_REG_D10 = 143 +MIPS_REG_D11 = 144 +MIPS_REG_D12 = 145 +MIPS_REG_D13 = 146 +MIPS_REG_D14 = 147 +MIPS_REG_D15 = 148 +MIPS_REG_DSPOUTFLAG20 = 149 +MIPS_REG_DSPOUTFLAG21 = 150 +MIPS_REG_DSPOUTFLAG22 = 151 +MIPS_REG_DSPOUTFLAG23 = 152 +MIPS_REG_F0 = 153 +MIPS_REG_F1 = 154 +MIPS_REG_F2 = 155 +MIPS_REG_F3 = 156 +MIPS_REG_F4 = 157 +MIPS_REG_F5 = 158 +MIPS_REG_F6 = 159 +MIPS_REG_F7 = 160 +MIPS_REG_F8 = 161 +MIPS_REG_F9 = 162 +MIPS_REG_F10 = 163 +MIPS_REG_F11 = 164 +MIPS_REG_F12 = 165 +MIPS_REG_F13 = 166 +MIPS_REG_F14 = 167 +MIPS_REG_F15 = 168 +MIPS_REG_F16 = 169 +MIPS_REG_F17 = 170 +MIPS_REG_F18 = 171 +MIPS_REG_F19 = 172 +MIPS_REG_F20 = 173 +MIPS_REG_F21 = 174 +MIPS_REG_F22 = 175 +MIPS_REG_F23 = 176 +MIPS_REG_F24 = 177 +MIPS_REG_F25 = 178 +MIPS_REG_F26 = 179 +MIPS_REG_F27 = 180 +MIPS_REG_F28 = 181 +MIPS_REG_F29 = 182 +MIPS_REG_F30 = 183 +MIPS_REG_F31 = 184 +MIPS_REG_FCC0 = 185 +MIPS_REG_FCC1 = 186 +MIPS_REG_FCC2 = 187 +MIPS_REG_FCC3 = 188 +MIPS_REG_FCC4 = 189 +MIPS_REG_FCC5 = 190 +MIPS_REG_FCC6 = 191 +MIPS_REG_FCC7 = 192 +MIPS_REG_FCR0 = 193 +MIPS_REG_FCR1 = 194 +MIPS_REG_FCR2 = 195 +MIPS_REG_FCR3 = 196 +MIPS_REG_FCR4 = 197 +MIPS_REG_FCR5 = 198 +MIPS_REG_FCR6 = 199 +MIPS_REG_FCR7 = 200 +MIPS_REG_FCR8 = 201 +MIPS_REG_FCR9 = 202 +MIPS_REG_FCR10 = 203 +MIPS_REG_FCR11 = 204 +MIPS_REG_FCR12 = 205 +MIPS_REG_FCR13 = 206 +MIPS_REG_FCR14 = 207 +MIPS_REG_FCR15 = 208 +MIPS_REG_FCR16 = 209 +MIPS_REG_FCR17 = 210 +MIPS_REG_FCR18 = 211 +MIPS_REG_FCR19 = 212 +MIPS_REG_FCR20 = 213 +MIPS_REG_FCR21 = 214 +MIPS_REG_FCR22 = 215 +MIPS_REG_FCR23 = 216 +MIPS_REG_FCR24 = 217 +MIPS_REG_FCR25 = 218 +MIPS_REG_FCR26 = 219 +MIPS_REG_FCR27 = 220 +MIPS_REG_FCR28 = 221 +MIPS_REG_FCR29 = 222 +MIPS_REG_FCR30 = 223 +MIPS_REG_FCR31 = 224 +MIPS_REG_FP_64 = 225 +MIPS_REG_F_HI0 = 226 +MIPS_REG_F_HI1 = 227 +MIPS_REG_F_HI2 = 228 +MIPS_REG_F_HI3 = 229 +MIPS_REG_F_HI4 = 230 +MIPS_REG_F_HI5 = 231 +MIPS_REG_F_HI6 = 232 +MIPS_REG_F_HI7 = 233 +MIPS_REG_F_HI8 = 234 +MIPS_REG_F_HI9 = 235 +MIPS_REG_F_HI10 = 236 +MIPS_REG_F_HI11 = 237 +MIPS_REG_F_HI12 = 238 +MIPS_REG_F_HI13 = 239 +MIPS_REG_F_HI14 = 240 +MIPS_REG_F_HI15 = 241 +MIPS_REG_F_HI16 = 242 +MIPS_REG_F_HI17 = 243 +MIPS_REG_F_HI18 = 244 +MIPS_REG_F_HI19 = 245 +MIPS_REG_F_HI20 = 246 +MIPS_REG_F_HI21 = 247 +MIPS_REG_F_HI22 = 248 +MIPS_REG_F_HI23 = 249 +MIPS_REG_F_HI24 = 250 +MIPS_REG_F_HI25 = 251 +MIPS_REG_F_HI26 = 252 +MIPS_REG_F_HI27 = 253 +MIPS_REG_F_HI28 = 254 +MIPS_REG_F_HI29 = 255 +MIPS_REG_F_HI30 = 256 +MIPS_REG_F_HI31 = 257 +MIPS_REG_GP_64 = 258 +MIPS_REG_HI0 = 259 +MIPS_REG_HI1 = 260 +MIPS_REG_HI2 = 261 +MIPS_REG_HI3 = 262 +MIPS_REG_HWR0 = 263 +MIPS_REG_HWR1 = 264 +MIPS_REG_HWR2 = 265 +MIPS_REG_HWR3 = 266 +MIPS_REG_HWR4 = 267 +MIPS_REG_HWR5 = 268 +MIPS_REG_HWR6 = 269 +MIPS_REG_HWR7 = 270 +MIPS_REG_HWR8 = 271 +MIPS_REG_HWR9 = 272 +MIPS_REG_HWR10 = 273 +MIPS_REG_HWR11 = 274 +MIPS_REG_HWR12 = 275 +MIPS_REG_HWR13 = 276 +MIPS_REG_HWR14 = 277 +MIPS_REG_HWR15 = 278 +MIPS_REG_HWR16 = 279 +MIPS_REG_HWR17 = 280 +MIPS_REG_HWR18 = 281 +MIPS_REG_HWR19 = 282 +MIPS_REG_HWR20 = 283 +MIPS_REG_HWR21 = 284 +MIPS_REG_HWR22 = 285 +MIPS_REG_HWR23 = 286 +MIPS_REG_HWR24 = 287 +MIPS_REG_HWR25 = 288 +MIPS_REG_HWR26 = 289 +MIPS_REG_HWR27 = 290 +MIPS_REG_HWR28 = 291 +MIPS_REG_HWR29 = 292 +MIPS_REG_HWR30 = 293 +MIPS_REG_HWR31 = 294 +MIPS_REG_K0 = 295 +MIPS_REG_K1 = 296 +MIPS_REG_LO0 = 297 +MIPS_REG_LO1 = 298 +MIPS_REG_LO2 = 299 +MIPS_REG_LO3 = 300 +MIPS_REG_MPL0 = 301 +MIPS_REG_MPL1 = 302 +MIPS_REG_MPL2 = 303 +MIPS_REG_MSA8 = 304 +MIPS_REG_MSA9 = 305 +MIPS_REG_MSA10 = 306 +MIPS_REG_MSA11 = 307 +MIPS_REG_MSA12 = 308 +MIPS_REG_MSA13 = 309 +MIPS_REG_MSA14 = 310 +MIPS_REG_MSA15 = 311 +MIPS_REG_MSA16 = 312 +MIPS_REG_MSA17 = 313 +MIPS_REG_MSA18 = 314 +MIPS_REG_MSA19 = 315 +MIPS_REG_MSA20 = 316 +MIPS_REG_MSA21 = 317 +MIPS_REG_MSA22 = 318 +MIPS_REG_MSA23 = 319 +MIPS_REG_MSA24 = 320 +MIPS_REG_MSA25 = 321 +MIPS_REG_MSA26 = 322 +MIPS_REG_MSA27 = 323 +MIPS_REG_MSA28 = 324 +MIPS_REG_MSA29 = 325 +MIPS_REG_MSA30 = 326 +MIPS_REG_MSA31 = 327 +MIPS_REG_P0 = 328 +MIPS_REG_P1 = 329 +MIPS_REG_P2 = 330 +MIPS_REG_RA_64 = 331 +MIPS_REG_S0 = 332 +MIPS_REG_S1 = 333 +MIPS_REG_S2 = 334 +MIPS_REG_S3 = 335 +MIPS_REG_S4 = 336 +MIPS_REG_S5 = 337 +MIPS_REG_S6 = 338 +MIPS_REG_S7 = 339 +MIPS_REG_SP_64 = 340 +MIPS_REG_T0 = 341 +MIPS_REG_T1 = 342 +MIPS_REG_T2 = 343 +MIPS_REG_T3 = 344 +MIPS_REG_T4 = 345 +MIPS_REG_T5 = 346 +MIPS_REG_T6 = 347 +MIPS_REG_T7 = 348 +MIPS_REG_T8 = 349 +MIPS_REG_T9 = 350 +MIPS_REG_V0 = 351 +MIPS_REG_V1 = 352 +MIPS_REG_W0 = 353 +MIPS_REG_W1 = 354 +MIPS_REG_W2 = 355 +MIPS_REG_W3 = 356 +MIPS_REG_W4 = 357 +MIPS_REG_W5 = 358 +MIPS_REG_W6 = 359 +MIPS_REG_W7 = 360 +MIPS_REG_W8 = 361 +MIPS_REG_W9 = 362 +MIPS_REG_W10 = 363 +MIPS_REG_W11 = 364 +MIPS_REG_W12 = 365 +MIPS_REG_W13 = 366 +MIPS_REG_W14 = 367 +MIPS_REG_W15 = 368 +MIPS_REG_W16 = 369 +MIPS_REG_W17 = 370 +MIPS_REG_W18 = 371 +MIPS_REG_W19 = 372 +MIPS_REG_W20 = 373 +MIPS_REG_W21 = 374 +MIPS_REG_W22 = 375 +MIPS_REG_W23 = 376 +MIPS_REG_W24 = 377 +MIPS_REG_W25 = 378 +MIPS_REG_W26 = 379 +MIPS_REG_W27 = 380 +MIPS_REG_W28 = 381 +MIPS_REG_W29 = 382 +MIPS_REG_W30 = 383 +MIPS_REG_W31 = 384 +MIPS_REG_ZERO_64 = 385 +MIPS_REG_A0_NM = 386 +MIPS_REG_A1_NM = 387 +MIPS_REG_A2_NM = 388 +MIPS_REG_A3_NM = 389 +MIPS_REG_A4_NM = 390 +MIPS_REG_A5_NM = 391 +MIPS_REG_A6_NM = 392 +MIPS_REG_A7_NM = 393 +MIPS_REG_COP0SEL_BADINST = 394 +MIPS_REG_COP0SEL_BADINSTRP = 395 +MIPS_REG_COP0SEL_BADINSTRX = 396 +MIPS_REG_COP0SEL_BADVADDR = 397 +MIPS_REG_COP0SEL_BEVVA = 398 +MIPS_REG_COP0SEL_CACHEERR = 399 +MIPS_REG_COP0SEL_CAUSE = 400 +MIPS_REG_COP0SEL_CDMMBASE = 401 +MIPS_REG_COP0SEL_CMGCRBASE = 402 +MIPS_REG_COP0SEL_COMPARE = 403 +MIPS_REG_COP0SEL_CONFIG = 404 +MIPS_REG_COP0SEL_CONTEXT = 405 +MIPS_REG_COP0SEL_CONTEXTCONFIG = 406 +MIPS_REG_COP0SEL_COUNT = 407 +MIPS_REG_COP0SEL_DDATAHI = 408 +MIPS_REG_COP0SEL_DDATALO = 409 +MIPS_REG_COP0SEL_DEBUG = 410 +MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411 +MIPS_REG_COP0SEL_DEPC = 412 +MIPS_REG_COP0SEL_DESAVE = 413 +MIPS_REG_COP0SEL_DTAGHI = 414 +MIPS_REG_COP0SEL_DTAGLO = 415 +MIPS_REG_COP0SEL_EBASE = 416 +MIPS_REG_COP0SEL_ENTRYHI = 417 +MIPS_REG_COP0SEL_EPC = 418 +MIPS_REG_COP0SEL_ERRCTL = 419 +MIPS_REG_COP0SEL_ERROREPC = 420 +MIPS_REG_COP0SEL_GLOBALNUMBER = 421 +MIPS_REG_COP0SEL_GTOFFSET = 422 +MIPS_REG_COP0SEL_HWRENA = 423 +MIPS_REG_COP0SEL_IDATAHI = 424 +MIPS_REG_COP0SEL_IDATALO = 425 +MIPS_REG_COP0SEL_INDEX = 426 +MIPS_REG_COP0SEL_INTCTL = 427 +MIPS_REG_COP0SEL_ITAGHI = 428 +MIPS_REG_COP0SEL_ITAGLO = 429 +MIPS_REG_COP0SEL_LLADDR = 430 +MIPS_REG_COP0SEL_MAAR = 431 +MIPS_REG_COP0SEL_MAARI = 432 +MIPS_REG_COP0SEL_MEMORYMAPID = 433 +MIPS_REG_COP0SEL_MVPCONTROL = 434 +MIPS_REG_COP0SEL_NESTEDEPC = 435 +MIPS_REG_COP0SEL_NESTEDEXC = 436 +MIPS_REG_COP0SEL_PAGEGRAIN = 437 +MIPS_REG_COP0SEL_PAGEMASK = 438 +MIPS_REG_COP0SEL_PRID = 439 +MIPS_REG_COP0SEL_PWBASE = 440 +MIPS_REG_COP0SEL_PWCTL = 441 +MIPS_REG_COP0SEL_PWFIELD = 442 +MIPS_REG_COP0SEL_PWSIZE = 443 +MIPS_REG_COP0SEL_RANDOM = 444 +MIPS_REG_COP0SEL_SRSCTL = 445 +MIPS_REG_COP0SEL_SRSMAP = 446 +MIPS_REG_COP0SEL_STATUS = 447 +MIPS_REG_COP0SEL_TCBIND = 448 +MIPS_REG_COP0SEL_TCCONTEXT = 449 +MIPS_REG_COP0SEL_TCHALT = 450 +MIPS_REG_COP0SEL_TCOPT = 451 +MIPS_REG_COP0SEL_TCRESTART = 452 +MIPS_REG_COP0SEL_TCSCHEDULE = 453 +MIPS_REG_COP0SEL_TCSCHEFBACK = 454 +MIPS_REG_COP0SEL_TCSTATUS = 455 +MIPS_REG_COP0SEL_TRACECONTROL = 456 +MIPS_REG_COP0SEL_TRACEDBPC = 457 +MIPS_REG_COP0SEL_TRACEIBPC = 458 +MIPS_REG_COP0SEL_USERLOCAL = 459 +MIPS_REG_COP0SEL_VIEW_IPL = 460 +MIPS_REG_COP0SEL_VIEW_RIPL = 461 +MIPS_REG_COP0SEL_VPCONTROL = 462 +MIPS_REG_COP0SEL_VPECONTROL = 463 +MIPS_REG_COP0SEL_VPEOPT = 464 +MIPS_REG_COP0SEL_VPESCHEDULE = 465 +MIPS_REG_COP0SEL_VPESCHEFBACK = 466 +MIPS_REG_COP0SEL_WIRED = 467 +MIPS_REG_COP0SEL_XCONTEXT = 468 +MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469 +MIPS_REG_COP0SEL_YQMASK = 470 +MIPS_REG_K0_NM = 471 +MIPS_REG_K1_NM = 472 +MIPS_REG_S0_NM = 473 +MIPS_REG_S1_NM = 474 +MIPS_REG_S2_NM = 475 +MIPS_REG_S3_NM = 476 +MIPS_REG_S4_NM = 477 +MIPS_REG_S5_NM = 478 +MIPS_REG_S6_NM = 479 +MIPS_REG_S7_NM = 480 +MIPS_REG_T0_NM = 481 +MIPS_REG_T1_NM = 482 +MIPS_REG_T2_NM = 483 +MIPS_REG_T3_NM = 484 +MIPS_REG_T4_NM = 485 +MIPS_REG_T5_NM = 486 +MIPS_REG_T8_NM = 487 +MIPS_REG_T9_NM = 488 +MIPS_REG_A0_64 = 489 +MIPS_REG_A1_64 = 490 +MIPS_REG_A2_64 = 491 +MIPS_REG_A3_64 = 492 +MIPS_REG_AC0_64 = 493 +MIPS_REG_COP0SEL_CONFIG1 = 494 +MIPS_REG_COP0SEL_CONFIG2 = 495 +MIPS_REG_COP0SEL_CONFIG3 = 496 +MIPS_REG_COP0SEL_CONFIG4 = 497 +MIPS_REG_COP0SEL_CONFIG5 = 498 +MIPS_REG_COP0SEL_DEBUG2 = 499 +MIPS_REG_COP0SEL_ENTRYLO0 = 500 +MIPS_REG_COP0SEL_ENTRYLO1 = 501 +MIPS_REG_COP0SEL_GUESTCTL0 = 502 +MIPS_REG_COP0SEL_GUESTCTL1 = 503 +MIPS_REG_COP0SEL_GUESTCTL2 = 504 +MIPS_REG_COP0SEL_GUESTCTL3 = 505 +MIPS_REG_COP0SEL_KSCRATCH1 = 506 +MIPS_REG_COP0SEL_KSCRATCH2 = 507 +MIPS_REG_COP0SEL_KSCRATCH3 = 508 +MIPS_REG_COP0SEL_KSCRATCH4 = 509 +MIPS_REG_COP0SEL_KSCRATCH5 = 510 +MIPS_REG_COP0SEL_KSCRATCH6 = 511 +MIPS_REG_COP0SEL_MVPCONF0 = 512 +MIPS_REG_COP0SEL_MVPCONF1 = 513 +MIPS_REG_COP0SEL_PERFCNT0 = 514 +MIPS_REG_COP0SEL_PERFCNT1 = 515 +MIPS_REG_COP0SEL_PERFCNT2 = 516 +MIPS_REG_COP0SEL_PERFCNT3 = 517 +MIPS_REG_COP0SEL_PERFCNT4 = 518 +MIPS_REG_COP0SEL_PERFCNT5 = 519 +MIPS_REG_COP0SEL_PERFCNT6 = 520 +MIPS_REG_COP0SEL_PERFCNT7 = 521 +MIPS_REG_COP0SEL_PERFCTL0 = 522 +MIPS_REG_COP0SEL_PERFCTL1 = 523 +MIPS_REG_COP0SEL_PERFCTL2 = 524 +MIPS_REG_COP0SEL_PERFCTL3 = 525 +MIPS_REG_COP0SEL_PERFCTL4 = 526 +MIPS_REG_COP0SEL_PERFCTL5 = 527 +MIPS_REG_COP0SEL_PERFCTL6 = 528 +MIPS_REG_COP0SEL_PERFCTL7 = 529 +MIPS_REG_COP0SEL_SEGCTL0 = 530 +MIPS_REG_COP0SEL_SEGCTL1 = 531 +MIPS_REG_COP0SEL_SEGCTL2 = 532 +MIPS_REG_COP0SEL_SRSCONF0 = 533 +MIPS_REG_COP0SEL_SRSCONF1 = 534 +MIPS_REG_COP0SEL_SRSCONF2 = 535 +MIPS_REG_COP0SEL_SRSCONF3 = 536 +MIPS_REG_COP0SEL_SRSCONF4 = 537 +MIPS_REG_COP0SEL_SRSMAP2 = 538 +MIPS_REG_COP0SEL_TRACECONTROL2 = 539 +MIPS_REG_COP0SEL_TRACECONTROL3 = 540 +MIPS_REG_COP0SEL_USERTRACEDATA1 = 541 +MIPS_REG_COP0SEL_USERTRACEDATA2 = 542 +MIPS_REG_COP0SEL_VPECONF0 = 543 +MIPS_REG_COP0SEL_VPECONF1 = 544 +MIPS_REG_COP0SEL_WATCHHI0 = 545 +MIPS_REG_COP0SEL_WATCHHI1 = 546 +MIPS_REG_COP0SEL_WATCHHI2 = 547 +MIPS_REG_COP0SEL_WATCHHI3 = 548 +MIPS_REG_COP0SEL_WATCHHI4 = 549 +MIPS_REG_COP0SEL_WATCHHI5 = 550 +MIPS_REG_COP0SEL_WATCHHI6 = 551 +MIPS_REG_COP0SEL_WATCHHI7 = 552 +MIPS_REG_COP0SEL_WATCHHI8 = 553 +MIPS_REG_COP0SEL_WATCHHI9 = 554 +MIPS_REG_COP0SEL_WATCHHI10 = 555 +MIPS_REG_COP0SEL_WATCHHI11 = 556 +MIPS_REG_COP0SEL_WATCHHI12 = 557 +MIPS_REG_COP0SEL_WATCHHI13 = 558 +MIPS_REG_COP0SEL_WATCHHI14 = 559 +MIPS_REG_COP0SEL_WATCHHI15 = 560 +MIPS_REG_COP0SEL_WATCHLO0 = 561 +MIPS_REG_COP0SEL_WATCHLO1 = 562 +MIPS_REG_COP0SEL_WATCHLO2 = 563 +MIPS_REG_COP0SEL_WATCHLO3 = 564 +MIPS_REG_COP0SEL_WATCHLO4 = 565 +MIPS_REG_COP0SEL_WATCHLO5 = 566 +MIPS_REG_COP0SEL_WATCHLO6 = 567 +MIPS_REG_COP0SEL_WATCHLO7 = 568 +MIPS_REG_COP0SEL_WATCHLO8 = 569 +MIPS_REG_COP0SEL_WATCHLO9 = 570 +MIPS_REG_COP0SEL_WATCHLO10 = 571 +MIPS_REG_COP0SEL_WATCHLO11 = 572 +MIPS_REG_COP0SEL_WATCHLO12 = 573 +MIPS_REG_COP0SEL_WATCHLO13 = 574 +MIPS_REG_COP0SEL_WATCHLO14 = 575 +MIPS_REG_COP0SEL_WATCHLO15 = 576 +MIPS_REG_D0_64 = 577 +MIPS_REG_D1_64 = 578 +MIPS_REG_D2_64 = 579 +MIPS_REG_D3_64 = 580 +MIPS_REG_D4_64 = 581 +MIPS_REG_D5_64 = 582 +MIPS_REG_D6_64 = 583 +MIPS_REG_D7_64 = 584 +MIPS_REG_D8_64 = 585 +MIPS_REG_D9_64 = 586 +MIPS_REG_D10_64 = 587 +MIPS_REG_D11_64 = 588 +MIPS_REG_D12_64 = 589 +MIPS_REG_D13_64 = 590 +MIPS_REG_D14_64 = 591 +MIPS_REG_D15_64 = 592 +MIPS_REG_D16_64 = 593 +MIPS_REG_D17_64 = 594 +MIPS_REG_D18_64 = 595 +MIPS_REG_D19_64 = 596 +MIPS_REG_D20_64 = 597 +MIPS_REG_D21_64 = 598 +MIPS_REG_D22_64 = 599 +MIPS_REG_D23_64 = 600 +MIPS_REG_D24_64 = 601 +MIPS_REG_D25_64 = 602 +MIPS_REG_D26_64 = 603 +MIPS_REG_D27_64 = 604 +MIPS_REG_D28_64 = 605 +MIPS_REG_D29_64 = 606 +MIPS_REG_D30_64 = 607 +MIPS_REG_D31_64 = 608 +MIPS_REG_DSPOUTFLAG16_19 = 609 +MIPS_REG_HI0_64 = 610 +MIPS_REG_K0_64 = 611 +MIPS_REG_K1_64 = 612 +MIPS_REG_LO0_64 = 613 +MIPS_REG_S0_64 = 614 +MIPS_REG_S1_64 = 615 +MIPS_REG_S2_64 = 616 +MIPS_REG_S3_64 = 617 +MIPS_REG_S4_64 = 618 +MIPS_REG_S5_64 = 619 +MIPS_REG_S6_64 = 620 +MIPS_REG_S7_64 = 621 +MIPS_REG_T0_64 = 622 +MIPS_REG_T1_64 = 623 +MIPS_REG_T2_64 = 624 +MIPS_REG_T3_64 = 625 +MIPS_REG_T4_64 = 626 +MIPS_REG_T5_64 = 627 +MIPS_REG_T6_64 = 628 +MIPS_REG_T7_64 = 629 +MIPS_REG_T8_64 = 630 +MIPS_REG_T9_64 = 631 +MIPS_REG_V0_64 = 632 +MIPS_REG_V1_64 = 633 +MIPS_REG_COP0SEL_GUESTCTL0EXT = 634 +MIPS_REG_ENDING = 635 MIPS_INS_INVALID = 0 -MIPS_INS_ABSQ_S = 1 -MIPS_INS_ADD = 2 -MIPS_INS_ADDIUPC = 3 -MIPS_INS_ADDIUR1SP = 4 -MIPS_INS_ADDIUR2 = 5 -MIPS_INS_ADDIUS5 = 6 -MIPS_INS_ADDIUSP = 7 -MIPS_INS_ADDQH = 8 -MIPS_INS_ADDQH_R = 9 -MIPS_INS_ADDQ = 10 -MIPS_INS_ADDQ_S = 11 -MIPS_INS_ADDSC = 12 -MIPS_INS_ADDS_A = 13 -MIPS_INS_ADDS_S = 14 -MIPS_INS_ADDS_U = 15 -MIPS_INS_ADDU16 = 16 -MIPS_INS_ADDUH = 17 -MIPS_INS_ADDUH_R = 18 -MIPS_INS_ADDU = 19 -MIPS_INS_ADDU_S = 20 -MIPS_INS_ADDVI = 21 -MIPS_INS_ADDV = 22 -MIPS_INS_ADDWC = 23 -MIPS_INS_ADD_A = 24 -MIPS_INS_ADDI = 25 -MIPS_INS_ADDIU = 26 -MIPS_INS_ALIGN = 27 -MIPS_INS_ALUIPC = 28 -MIPS_INS_AND = 29 -MIPS_INS_AND16 = 30 -MIPS_INS_ANDI16 = 31 -MIPS_INS_ANDI = 32 -MIPS_INS_APPEND = 33 -MIPS_INS_ASUB_S = 34 -MIPS_INS_ASUB_U = 35 -MIPS_INS_AUI = 36 -MIPS_INS_AUIPC = 37 -MIPS_INS_AVER_S = 38 -MIPS_INS_AVER_U = 39 -MIPS_INS_AVE_S = 40 -MIPS_INS_AVE_U = 41 -MIPS_INS_B16 = 42 -MIPS_INS_BADDU = 43 -MIPS_INS_BAL = 44 -MIPS_INS_BALC = 45 -MIPS_INS_BALIGN = 46 -MIPS_INS_BBIT0 = 47 -MIPS_INS_BBIT032 = 48 -MIPS_INS_BBIT1 = 49 -MIPS_INS_BBIT132 = 50 -MIPS_INS_BC = 51 -MIPS_INS_BC0F = 52 -MIPS_INS_BC0FL = 53 -MIPS_INS_BC0T = 54 -MIPS_INS_BC0TL = 55 -MIPS_INS_BC1EQZ = 56 -MIPS_INS_BC1F = 57 -MIPS_INS_BC1FL = 58 -MIPS_INS_BC1NEZ = 59 -MIPS_INS_BC1T = 60 -MIPS_INS_BC1TL = 61 -MIPS_INS_BC2EQZ = 62 -MIPS_INS_BC2F = 63 -MIPS_INS_BC2FL = 64 -MIPS_INS_BC2NEZ = 65 -MIPS_INS_BC2T = 66 -MIPS_INS_BC2TL = 67 -MIPS_INS_BC3F = 68 -MIPS_INS_BC3FL = 69 -MIPS_INS_BC3T = 70 -MIPS_INS_BC3TL = 71 -MIPS_INS_BCLRI = 72 -MIPS_INS_BCLR = 73 -MIPS_INS_BEQ = 74 -MIPS_INS_BEQC = 75 -MIPS_INS_BEQL = 76 -MIPS_INS_BEQZ16 = 77 -MIPS_INS_BEQZALC = 78 -MIPS_INS_BEQZC = 79 -MIPS_INS_BGEC = 80 -MIPS_INS_BGEUC = 81 -MIPS_INS_BGEZ = 82 -MIPS_INS_BGEZAL = 83 -MIPS_INS_BGEZALC = 84 -MIPS_INS_BGEZALL = 85 -MIPS_INS_BGEZALS = 86 -MIPS_INS_BGEZC = 87 -MIPS_INS_BGEZL = 88 -MIPS_INS_BGTZ = 89 -MIPS_INS_BGTZALC = 90 -MIPS_INS_BGTZC = 91 -MIPS_INS_BGTZL = 92 -MIPS_INS_BINSLI = 93 -MIPS_INS_BINSL = 94 -MIPS_INS_BINSRI = 95 -MIPS_INS_BINSR = 96 -MIPS_INS_BITREV = 97 -MIPS_INS_BITSWAP = 98 -MIPS_INS_BLEZ = 99 -MIPS_INS_BLEZALC = 100 -MIPS_INS_BLEZC = 101 -MIPS_INS_BLEZL = 102 -MIPS_INS_BLTC = 103 -MIPS_INS_BLTUC = 104 -MIPS_INS_BLTZ = 105 -MIPS_INS_BLTZAL = 106 -MIPS_INS_BLTZALC = 107 -MIPS_INS_BLTZALL = 108 -MIPS_INS_BLTZALS = 109 -MIPS_INS_BLTZC = 110 -MIPS_INS_BLTZL = 111 -MIPS_INS_BMNZI = 112 -MIPS_INS_BMNZ = 113 -MIPS_INS_BMZI = 114 -MIPS_INS_BMZ = 115 -MIPS_INS_BNE = 116 -MIPS_INS_BNEC = 117 -MIPS_INS_BNEGI = 118 -MIPS_INS_BNEG = 119 -MIPS_INS_BNEL = 120 -MIPS_INS_BNEZ16 = 121 -MIPS_INS_BNEZALC = 122 -MIPS_INS_BNEZC = 123 -MIPS_INS_BNVC = 124 -MIPS_INS_BNZ = 125 -MIPS_INS_BOVC = 126 -MIPS_INS_BPOSGE32 = 127 -MIPS_INS_BREAK = 128 -MIPS_INS_BREAK16 = 129 -MIPS_INS_BSELI = 130 -MIPS_INS_BSEL = 131 -MIPS_INS_BSETI = 132 -MIPS_INS_BSET = 133 -MIPS_INS_BZ = 134 -MIPS_INS_BEQZ = 135 -MIPS_INS_B = 136 -MIPS_INS_BNEZ = 137 -MIPS_INS_BTEQZ = 138 -MIPS_INS_BTNEZ = 139 -MIPS_INS_CACHE = 140 -MIPS_INS_CEIL = 141 -MIPS_INS_CEQI = 142 -MIPS_INS_CEQ = 143 -MIPS_INS_CFC1 = 144 -MIPS_INS_CFCMSA = 145 -MIPS_INS_CINS = 146 -MIPS_INS_CINS32 = 147 -MIPS_INS_CLASS = 148 -MIPS_INS_CLEI_S = 149 -MIPS_INS_CLEI_U = 150 -MIPS_INS_CLE_S = 151 -MIPS_INS_CLE_U = 152 -MIPS_INS_CLO = 153 -MIPS_INS_CLTI_S = 154 -MIPS_INS_CLTI_U = 155 -MIPS_INS_CLT_S = 156 -MIPS_INS_CLT_U = 157 -MIPS_INS_CLZ = 158 -MIPS_INS_CMPGDU = 159 -MIPS_INS_CMPGU = 160 -MIPS_INS_CMPU = 161 -MIPS_INS_CMP = 162 -MIPS_INS_COPY_S = 163 -MIPS_INS_COPY_U = 164 -MIPS_INS_CTC1 = 165 -MIPS_INS_CTCMSA = 166 -MIPS_INS_CVT = 167 -MIPS_INS_C = 168 -MIPS_INS_CMPI = 169 -MIPS_INS_DADD = 170 -MIPS_INS_DADDI = 171 -MIPS_INS_DADDIU = 172 -MIPS_INS_DADDU = 173 -MIPS_INS_DAHI = 174 -MIPS_INS_DALIGN = 175 -MIPS_INS_DATI = 176 -MIPS_INS_DAUI = 177 -MIPS_INS_DBITSWAP = 178 -MIPS_INS_DCLO = 179 -MIPS_INS_DCLZ = 180 -MIPS_INS_DDIV = 181 -MIPS_INS_DDIVU = 182 -MIPS_INS_DERET = 183 -MIPS_INS_DEXT = 184 -MIPS_INS_DEXTM = 185 -MIPS_INS_DEXTU = 186 -MIPS_INS_DI = 187 -MIPS_INS_DINS = 188 -MIPS_INS_DINSM = 189 -MIPS_INS_DINSU = 190 -MIPS_INS_DIV = 191 -MIPS_INS_DIVU = 192 -MIPS_INS_DIV_S = 193 -MIPS_INS_DIV_U = 194 -MIPS_INS_DLSA = 195 -MIPS_INS_DMFC0 = 196 -MIPS_INS_DMFC1 = 197 -MIPS_INS_DMFC2 = 198 -MIPS_INS_DMOD = 199 -MIPS_INS_DMODU = 200 -MIPS_INS_DMTC0 = 201 -MIPS_INS_DMTC1 = 202 -MIPS_INS_DMTC2 = 203 -MIPS_INS_DMUH = 204 -MIPS_INS_DMUHU = 205 -MIPS_INS_DMUL = 206 -MIPS_INS_DMULT = 207 -MIPS_INS_DMULTU = 208 -MIPS_INS_DMULU = 209 -MIPS_INS_DOTP_S = 210 -MIPS_INS_DOTP_U = 211 -MIPS_INS_DPADD_S = 212 -MIPS_INS_DPADD_U = 213 -MIPS_INS_DPAQX_SA = 214 -MIPS_INS_DPAQX_S = 215 -MIPS_INS_DPAQ_SA = 216 -MIPS_INS_DPAQ_S = 217 -MIPS_INS_DPAU = 218 -MIPS_INS_DPAX = 219 -MIPS_INS_DPA = 220 -MIPS_INS_DPOP = 221 -MIPS_INS_DPSQX_SA = 222 -MIPS_INS_DPSQX_S = 223 -MIPS_INS_DPSQ_SA = 224 -MIPS_INS_DPSQ_S = 225 -MIPS_INS_DPSUB_S = 226 -MIPS_INS_DPSUB_U = 227 -MIPS_INS_DPSU = 228 -MIPS_INS_DPSX = 229 -MIPS_INS_DPS = 230 -MIPS_INS_DROTR = 231 -MIPS_INS_DROTR32 = 232 -MIPS_INS_DROTRV = 233 -MIPS_INS_DSBH = 234 -MIPS_INS_DSHD = 235 -MIPS_INS_DSLL = 236 -MIPS_INS_DSLL32 = 237 -MIPS_INS_DSLLV = 238 -MIPS_INS_DSRA = 239 -MIPS_INS_DSRA32 = 240 -MIPS_INS_DSRAV = 241 -MIPS_INS_DSRL = 242 -MIPS_INS_DSRL32 = 243 -MIPS_INS_DSRLV = 244 -MIPS_INS_DSUB = 245 -MIPS_INS_DSUBU = 246 -MIPS_INS_EHB = 247 -MIPS_INS_EI = 248 -MIPS_INS_ERET = 249 -MIPS_INS_EXT = 250 -MIPS_INS_EXTP = 251 -MIPS_INS_EXTPDP = 252 -MIPS_INS_EXTPDPV = 253 -MIPS_INS_EXTPV = 254 -MIPS_INS_EXTRV_RS = 255 -MIPS_INS_EXTRV_R = 256 -MIPS_INS_EXTRV_S = 257 -MIPS_INS_EXTRV = 258 -MIPS_INS_EXTR_RS = 259 -MIPS_INS_EXTR_R = 260 -MIPS_INS_EXTR_S = 261 -MIPS_INS_EXTR = 262 -MIPS_INS_EXTS = 263 -MIPS_INS_EXTS32 = 264 -MIPS_INS_ABS = 265 -MIPS_INS_FADD = 266 -MIPS_INS_FCAF = 267 -MIPS_INS_FCEQ = 268 -MIPS_INS_FCLASS = 269 -MIPS_INS_FCLE = 270 -MIPS_INS_FCLT = 271 -MIPS_INS_FCNE = 272 -MIPS_INS_FCOR = 273 -MIPS_INS_FCUEQ = 274 -MIPS_INS_FCULE = 275 -MIPS_INS_FCULT = 276 -MIPS_INS_FCUNE = 277 -MIPS_INS_FCUN = 278 -MIPS_INS_FDIV = 279 -MIPS_INS_FEXDO = 280 -MIPS_INS_FEXP2 = 281 -MIPS_INS_FEXUPL = 282 -MIPS_INS_FEXUPR = 283 -MIPS_INS_FFINT_S = 284 -MIPS_INS_FFINT_U = 285 -MIPS_INS_FFQL = 286 -MIPS_INS_FFQR = 287 -MIPS_INS_FILL = 288 -MIPS_INS_FLOG2 = 289 -MIPS_INS_FLOOR = 290 -MIPS_INS_FMADD = 291 -MIPS_INS_FMAX_A = 292 -MIPS_INS_FMAX = 293 -MIPS_INS_FMIN_A = 294 -MIPS_INS_FMIN = 295 -MIPS_INS_MOV = 296 -MIPS_INS_FMSUB = 297 -MIPS_INS_FMUL = 298 -MIPS_INS_MUL = 299 -MIPS_INS_NEG = 300 -MIPS_INS_FRCP = 301 -MIPS_INS_FRINT = 302 -MIPS_INS_FRSQRT = 303 -MIPS_INS_FSAF = 304 -MIPS_INS_FSEQ = 305 -MIPS_INS_FSLE = 306 -MIPS_INS_FSLT = 307 -MIPS_INS_FSNE = 308 -MIPS_INS_FSOR = 309 -MIPS_INS_FSQRT = 310 -MIPS_INS_SQRT = 311 -MIPS_INS_FSUB = 312 -MIPS_INS_SUB = 313 -MIPS_INS_FSUEQ = 314 -MIPS_INS_FSULE = 315 -MIPS_INS_FSULT = 316 -MIPS_INS_FSUNE = 317 -MIPS_INS_FSUN = 318 -MIPS_INS_FTINT_S = 319 -MIPS_INS_FTINT_U = 320 -MIPS_INS_FTQ = 321 -MIPS_INS_FTRUNC_S = 322 -MIPS_INS_FTRUNC_U = 323 -MIPS_INS_HADD_S = 324 -MIPS_INS_HADD_U = 325 -MIPS_INS_HSUB_S = 326 -MIPS_INS_HSUB_U = 327 -MIPS_INS_ILVEV = 328 -MIPS_INS_ILVL = 329 -MIPS_INS_ILVOD = 330 -MIPS_INS_ILVR = 331 -MIPS_INS_INS = 332 -MIPS_INS_INSERT = 333 -MIPS_INS_INSV = 334 -MIPS_INS_INSVE = 335 -MIPS_INS_J = 336 -MIPS_INS_JAL = 337 -MIPS_INS_JALR = 338 -MIPS_INS_JALRS16 = 339 -MIPS_INS_JALRS = 340 -MIPS_INS_JALS = 341 -MIPS_INS_JALX = 342 -MIPS_INS_JIALC = 343 -MIPS_INS_JIC = 344 -MIPS_INS_JR = 345 -MIPS_INS_JR16 = 346 -MIPS_INS_JRADDIUSP = 347 -MIPS_INS_JRC = 348 -MIPS_INS_JALRC = 349 -MIPS_INS_LB = 350 -MIPS_INS_LBU16 = 351 -MIPS_INS_LBUX = 352 -MIPS_INS_LBU = 353 -MIPS_INS_LD = 354 -MIPS_INS_LDC1 = 355 -MIPS_INS_LDC2 = 356 -MIPS_INS_LDC3 = 357 -MIPS_INS_LDI = 358 -MIPS_INS_LDL = 359 -MIPS_INS_LDPC = 360 -MIPS_INS_LDR = 361 -MIPS_INS_LDXC1 = 362 -MIPS_INS_LH = 363 -MIPS_INS_LHU16 = 364 -MIPS_INS_LHX = 365 -MIPS_INS_LHU = 366 -MIPS_INS_LI16 = 367 -MIPS_INS_LL = 368 -MIPS_INS_LLD = 369 -MIPS_INS_LSA = 370 -MIPS_INS_LUXC1 = 371 -MIPS_INS_LUI = 372 -MIPS_INS_LW = 373 -MIPS_INS_LW16 = 374 -MIPS_INS_LWC1 = 375 -MIPS_INS_LWC2 = 376 -MIPS_INS_LWC3 = 377 -MIPS_INS_LWL = 378 -MIPS_INS_LWM16 = 379 -MIPS_INS_LWM32 = 380 -MIPS_INS_LWPC = 381 -MIPS_INS_LWP = 382 -MIPS_INS_LWR = 383 -MIPS_INS_LWUPC = 384 -MIPS_INS_LWU = 385 -MIPS_INS_LWX = 386 -MIPS_INS_LWXC1 = 387 -MIPS_INS_LWXS = 388 -MIPS_INS_LI = 389 -MIPS_INS_MADD = 390 -MIPS_INS_MADDF = 391 -MIPS_INS_MADDR_Q = 392 -MIPS_INS_MADDU = 393 -MIPS_INS_MADDV = 394 -MIPS_INS_MADD_Q = 395 -MIPS_INS_MAQ_SA = 396 -MIPS_INS_MAQ_S = 397 -MIPS_INS_MAXA = 398 -MIPS_INS_MAXI_S = 399 -MIPS_INS_MAXI_U = 400 -MIPS_INS_MAX_A = 401 -MIPS_INS_MAX = 402 -MIPS_INS_MAX_S = 403 -MIPS_INS_MAX_U = 404 -MIPS_INS_MFC0 = 405 -MIPS_INS_MFC1 = 406 -MIPS_INS_MFC2 = 407 -MIPS_INS_MFHC1 = 408 -MIPS_INS_MFHI = 409 -MIPS_INS_MFLO = 410 -MIPS_INS_MINA = 411 -MIPS_INS_MINI_S = 412 -MIPS_INS_MINI_U = 413 -MIPS_INS_MIN_A = 414 -MIPS_INS_MIN = 415 -MIPS_INS_MIN_S = 416 -MIPS_INS_MIN_U = 417 -MIPS_INS_MOD = 418 -MIPS_INS_MODSUB = 419 -MIPS_INS_MODU = 420 -MIPS_INS_MOD_S = 421 -MIPS_INS_MOD_U = 422 -MIPS_INS_MOVE = 423 -MIPS_INS_MOVEP = 424 -MIPS_INS_MOVF = 425 -MIPS_INS_MOVN = 426 -MIPS_INS_MOVT = 427 -MIPS_INS_MOVZ = 428 -MIPS_INS_MSUB = 429 -MIPS_INS_MSUBF = 430 -MIPS_INS_MSUBR_Q = 431 -MIPS_INS_MSUBU = 432 -MIPS_INS_MSUBV = 433 -MIPS_INS_MSUB_Q = 434 -MIPS_INS_MTC0 = 435 -MIPS_INS_MTC1 = 436 -MIPS_INS_MTC2 = 437 -MIPS_INS_MTHC1 = 438 -MIPS_INS_MTHI = 439 -MIPS_INS_MTHLIP = 440 -MIPS_INS_MTLO = 441 -MIPS_INS_MTM0 = 442 -MIPS_INS_MTM1 = 443 -MIPS_INS_MTM2 = 444 -MIPS_INS_MTP0 = 445 -MIPS_INS_MTP1 = 446 -MIPS_INS_MTP2 = 447 -MIPS_INS_MUH = 448 -MIPS_INS_MUHU = 449 -MIPS_INS_MULEQ_S = 450 -MIPS_INS_MULEU_S = 451 -MIPS_INS_MULQ_RS = 452 -MIPS_INS_MULQ_S = 453 -MIPS_INS_MULR_Q = 454 -MIPS_INS_MULSAQ_S = 455 -MIPS_INS_MULSA = 456 -MIPS_INS_MULT = 457 -MIPS_INS_MULTU = 458 -MIPS_INS_MULU = 459 -MIPS_INS_MULV = 460 -MIPS_INS_MUL_Q = 461 -MIPS_INS_MUL_S = 462 -MIPS_INS_NLOC = 463 -MIPS_INS_NLZC = 464 -MIPS_INS_NMADD = 465 -MIPS_INS_NMSUB = 466 -MIPS_INS_NOR = 467 -MIPS_INS_NORI = 468 -MIPS_INS_NOT16 = 469 -MIPS_INS_NOT = 470 -MIPS_INS_OR = 471 -MIPS_INS_OR16 = 472 -MIPS_INS_ORI = 473 -MIPS_INS_PACKRL = 474 -MIPS_INS_PAUSE = 475 -MIPS_INS_PCKEV = 476 -MIPS_INS_PCKOD = 477 -MIPS_INS_PCNT = 478 -MIPS_INS_PICK = 479 -MIPS_INS_POP = 480 -MIPS_INS_PRECEQU = 481 -MIPS_INS_PRECEQ = 482 -MIPS_INS_PRECEU = 483 -MIPS_INS_PRECRQU_S = 484 -MIPS_INS_PRECRQ = 485 -MIPS_INS_PRECRQ_RS = 486 -MIPS_INS_PRECR = 487 -MIPS_INS_PRECR_SRA = 488 -MIPS_INS_PRECR_SRA_R = 489 -MIPS_INS_PREF = 490 -MIPS_INS_PREPEND = 491 -MIPS_INS_RADDU = 492 -MIPS_INS_RDDSP = 493 -MIPS_INS_RDHWR = 494 -MIPS_INS_REPLV = 495 -MIPS_INS_REPL = 496 -MIPS_INS_RINT = 497 -MIPS_INS_ROTR = 498 -MIPS_INS_ROTRV = 499 -MIPS_INS_ROUND = 500 -MIPS_INS_SAT_S = 501 -MIPS_INS_SAT_U = 502 -MIPS_INS_SB = 503 -MIPS_INS_SB16 = 504 -MIPS_INS_SC = 505 -MIPS_INS_SCD = 506 -MIPS_INS_SD = 507 -MIPS_INS_SDBBP = 508 -MIPS_INS_SDBBP16 = 509 -MIPS_INS_SDC1 = 510 -MIPS_INS_SDC2 = 511 -MIPS_INS_SDC3 = 512 -MIPS_INS_SDL = 513 -MIPS_INS_SDR = 514 -MIPS_INS_SDXC1 = 515 -MIPS_INS_SEB = 516 -MIPS_INS_SEH = 517 -MIPS_INS_SELEQZ = 518 -MIPS_INS_SELNEZ = 519 -MIPS_INS_SEL = 520 -MIPS_INS_SEQ = 521 -MIPS_INS_SEQI = 522 -MIPS_INS_SH = 523 -MIPS_INS_SH16 = 524 -MIPS_INS_SHF = 525 -MIPS_INS_SHILO = 526 -MIPS_INS_SHILOV = 527 -MIPS_INS_SHLLV = 528 -MIPS_INS_SHLLV_S = 529 -MIPS_INS_SHLL = 530 -MIPS_INS_SHLL_S = 531 -MIPS_INS_SHRAV = 532 -MIPS_INS_SHRAV_R = 533 -MIPS_INS_SHRA = 534 -MIPS_INS_SHRA_R = 535 -MIPS_INS_SHRLV = 536 -MIPS_INS_SHRL = 537 -MIPS_INS_SLDI = 538 -MIPS_INS_SLD = 539 -MIPS_INS_SLL = 540 -MIPS_INS_SLL16 = 541 -MIPS_INS_SLLI = 542 -MIPS_INS_SLLV = 543 -MIPS_INS_SLT = 544 -MIPS_INS_SLTI = 545 -MIPS_INS_SLTIU = 546 -MIPS_INS_SLTU = 547 -MIPS_INS_SNE = 548 -MIPS_INS_SNEI = 549 -MIPS_INS_SPLATI = 550 -MIPS_INS_SPLAT = 551 -MIPS_INS_SRA = 552 -MIPS_INS_SRAI = 553 -MIPS_INS_SRARI = 554 -MIPS_INS_SRAR = 555 -MIPS_INS_SRAV = 556 -MIPS_INS_SRL = 557 -MIPS_INS_SRL16 = 558 -MIPS_INS_SRLI = 559 -MIPS_INS_SRLRI = 560 -MIPS_INS_SRLR = 561 -MIPS_INS_SRLV = 562 -MIPS_INS_SSNOP = 563 -MIPS_INS_ST = 564 -MIPS_INS_SUBQH = 565 -MIPS_INS_SUBQH_R = 566 -MIPS_INS_SUBQ = 567 -MIPS_INS_SUBQ_S = 568 -MIPS_INS_SUBSUS_U = 569 -MIPS_INS_SUBSUU_S = 570 -MIPS_INS_SUBS_S = 571 -MIPS_INS_SUBS_U = 572 -MIPS_INS_SUBU16 = 573 -MIPS_INS_SUBUH = 574 -MIPS_INS_SUBUH_R = 575 -MIPS_INS_SUBU = 576 -MIPS_INS_SUBU_S = 577 -MIPS_INS_SUBVI = 578 -MIPS_INS_SUBV = 579 -MIPS_INS_SUXC1 = 580 -MIPS_INS_SW = 581 -MIPS_INS_SW16 = 582 -MIPS_INS_SWC1 = 583 -MIPS_INS_SWC2 = 584 -MIPS_INS_SWC3 = 585 -MIPS_INS_SWL = 586 -MIPS_INS_SWM16 = 587 -MIPS_INS_SWM32 = 588 -MIPS_INS_SWP = 589 -MIPS_INS_SWR = 590 -MIPS_INS_SWXC1 = 591 -MIPS_INS_SYNC = 592 -MIPS_INS_SYNCI = 593 -MIPS_INS_SYSCALL = 594 -MIPS_INS_TEQ = 595 -MIPS_INS_TEQI = 596 -MIPS_INS_TGE = 597 -MIPS_INS_TGEI = 598 -MIPS_INS_TGEIU = 599 -MIPS_INS_TGEU = 600 -MIPS_INS_TLBP = 601 -MIPS_INS_TLBR = 602 -MIPS_INS_TLBWI = 603 -MIPS_INS_TLBWR = 604 -MIPS_INS_TLT = 605 -MIPS_INS_TLTI = 606 -MIPS_INS_TLTIU = 607 -MIPS_INS_TLTU = 608 -MIPS_INS_TNE = 609 -MIPS_INS_TNEI = 610 -MIPS_INS_TRUNC = 611 -MIPS_INS_V3MULU = 612 -MIPS_INS_VMM0 = 613 -MIPS_INS_VMULU = 614 -MIPS_INS_VSHF = 615 -MIPS_INS_WAIT = 616 -MIPS_INS_WRDSP = 617 -MIPS_INS_WSBH = 618 -MIPS_INS_XOR = 619 -MIPS_INS_XOR16 = 620 -MIPS_INS_XORI = 621 - -# some alias instructions -MIPS_INS_NOP = 622 -MIPS_INS_NEGU = 623 - -# special instructions -MIPS_INS_JALR_HB = 624 -MIPS_INS_JR_HB = 625 -MIPS_INS_ENDING = 626 +MIPS_INS_ABS = 1 +MIPS_INS_ALIGN = 2 +MIPS_INS_BEQL = 3 +MIPS_INS_BGE = 4 +MIPS_INS_BGEL = 5 +MIPS_INS_BGEU = 6 +MIPS_INS_BGEUL = 7 +MIPS_INS_BGT = 8 +MIPS_INS_BGTL = 9 +MIPS_INS_BGTU = 10 +MIPS_INS_BGTUL = 11 +MIPS_INS_BLE = 12 +MIPS_INS_BLEL = 13 +MIPS_INS_BLEU = 14 +MIPS_INS_BLEUL = 15 +MIPS_INS_BLT = 16 +MIPS_INS_BLTL = 17 +MIPS_INS_BLTU = 18 +MIPS_INS_BLTUL = 19 +MIPS_INS_BNEL = 20 +MIPS_INS_B = 21 +MIPS_INS_BEQ = 22 +MIPS_INS_BNE = 23 +MIPS_INS_CFTC1 = 24 +MIPS_INS_CTTC1 = 25 +MIPS_INS_DMUL = 26 +MIPS_INS_DMULO = 27 +MIPS_INS_DMULOU = 28 +MIPS_INS_DROL = 29 +MIPS_INS_DROR = 30 +MIPS_INS_DDIV = 31 +MIPS_INS_DREM = 32 +MIPS_INS_DDIVU = 33 +MIPS_INS_DREMU = 34 +MIPS_INS_JAL = 35 +MIPS_INS_LD = 36 +MIPS_INS_LWM = 37 +MIPS_INS_LA = 38 +MIPS_INS_DLA = 39 +MIPS_INS_LI = 40 +MIPS_INS_DLI = 41 +MIPS_INS_LI_D = 42 +MIPS_INS_LI_S = 43 +MIPS_INS_MFTACX = 44 +MIPS_INS_MFTC0 = 45 +MIPS_INS_MFTC1 = 46 +MIPS_INS_MFTDSP = 47 +MIPS_INS_MFTGPR = 48 +MIPS_INS_MFTHC1 = 49 +MIPS_INS_MFTHI = 50 +MIPS_INS_MFTLO = 51 +MIPS_INS_MTTACX = 52 +MIPS_INS_MTTC0 = 53 +MIPS_INS_MTTC1 = 54 +MIPS_INS_MTTDSP = 55 +MIPS_INS_MTTGPR = 56 +MIPS_INS_MTTHC1 = 57 +MIPS_INS_MTTHI = 58 +MIPS_INS_MTTLO = 59 +MIPS_INS_MUL = 60 +MIPS_INS_MULO = 61 +MIPS_INS_MULOU = 62 +MIPS_INS_NOR = 63 +MIPS_INS_ADDIU = 64 +MIPS_INS_ANDI = 65 +MIPS_INS_SUBU = 66 +MIPS_INS_TRUNC_W_D = 67 +MIPS_INS_TRUNC_W_S = 68 +MIPS_INS_ROL = 69 +MIPS_INS_ROR = 70 +MIPS_INS_S_D = 71 +MIPS_INS_SD = 72 +MIPS_INS_DIV = 73 +MIPS_INS_SEQ = 74 +MIPS_INS_SGE = 75 +MIPS_INS_SGEU = 76 +MIPS_INS_SGT = 77 +MIPS_INS_SGTU = 78 +MIPS_INS_SLE = 79 +MIPS_INS_SLEU = 80 +MIPS_INS_SLT = 81 +MIPS_INS_SLTU = 82 +MIPS_INS_SNE = 83 +MIPS_INS_REM = 84 +MIPS_INS_SWM = 85 +MIPS_INS_SAA = 86 +MIPS_INS_SAAD = 87 +MIPS_INS_DIVU = 88 +MIPS_INS_REMU = 89 +MIPS_INS_ULH = 90 +MIPS_INS_ULHU = 91 +MIPS_INS_ULW = 92 +MIPS_INS_USH = 93 +MIPS_INS_USW = 94 +MIPS_INS_ABSQ_S_PH = 95 +MIPS_INS_ABSQ_S_QB = 96 +MIPS_INS_ABSQ_S_W = 97 +MIPS_INS_ADD = 98 +MIPS_INS_ADDIUPC = 99 +MIPS_INS_ADDIUR1SP = 100 +MIPS_INS_ADDIUR2 = 101 +MIPS_INS_ADDIUS5 = 102 +MIPS_INS_ADDIUSP = 103 +MIPS_INS_ADDQH_PH = 104 +MIPS_INS_ADDQH_R_PH = 105 +MIPS_INS_ADDQH_R_W = 106 +MIPS_INS_ADDQH_W = 107 +MIPS_INS_ADDQ_PH = 108 +MIPS_INS_ADDQ_S_PH = 109 +MIPS_INS_ADDQ_S_W = 110 +MIPS_INS_ADDR_PS = 111 +MIPS_INS_ADDSC = 112 +MIPS_INS_ADDS_A_B = 113 +MIPS_INS_ADDS_A_D = 114 +MIPS_INS_ADDS_A_H = 115 +MIPS_INS_ADDS_A_W = 116 +MIPS_INS_ADDS_S_B = 117 +MIPS_INS_ADDS_S_D = 118 +MIPS_INS_ADDS_S_H = 119 +MIPS_INS_ADDS_S_W = 120 +MIPS_INS_ADDS_U_B = 121 +MIPS_INS_ADDS_U_D = 122 +MIPS_INS_ADDS_U_H = 123 +MIPS_INS_ADDS_U_W = 124 +MIPS_INS_ADDU16 = 125 +MIPS_INS_ADDUH_QB = 126 +MIPS_INS_ADDUH_R_QB = 127 +MIPS_INS_ADDU = 128 +MIPS_INS_ADDU_PH = 129 +MIPS_INS_ADDU_QB = 130 +MIPS_INS_ADDU_S_PH = 131 +MIPS_INS_ADDU_S_QB = 132 +MIPS_INS_ADDVI_B = 133 +MIPS_INS_ADDVI_D = 134 +MIPS_INS_ADDVI_H = 135 +MIPS_INS_ADDVI_W = 136 +MIPS_INS_ADDV_B = 137 +MIPS_INS_ADDV_D = 138 +MIPS_INS_ADDV_H = 139 +MIPS_INS_ADDV_W = 140 +MIPS_INS_ADDWC = 141 +MIPS_INS_ADD_A_B = 142 +MIPS_INS_ADD_A_D = 143 +MIPS_INS_ADD_A_H = 144 +MIPS_INS_ADD_A_W = 145 +MIPS_INS_ADDI = 146 +MIPS_INS_ALUIPC = 147 +MIPS_INS_AND = 148 +MIPS_INS_AND16 = 149 +MIPS_INS_ANDI16 = 150 +MIPS_INS_ANDI_B = 151 +MIPS_INS_AND_V = 152 +MIPS_INS_APPEND = 153 +MIPS_INS_ASUB_S_B = 154 +MIPS_INS_ASUB_S_D = 155 +MIPS_INS_ASUB_S_H = 156 +MIPS_INS_ASUB_S_W = 157 +MIPS_INS_ASUB_U_B = 158 +MIPS_INS_ASUB_U_D = 159 +MIPS_INS_ASUB_U_H = 160 +MIPS_INS_ASUB_U_W = 161 +MIPS_INS_AUI = 162 +MIPS_INS_AUIPC = 163 +MIPS_INS_AVER_S_B = 164 +MIPS_INS_AVER_S_D = 165 +MIPS_INS_AVER_S_H = 166 +MIPS_INS_AVER_S_W = 167 +MIPS_INS_AVER_U_B = 168 +MIPS_INS_AVER_U_D = 169 +MIPS_INS_AVER_U_H = 170 +MIPS_INS_AVER_U_W = 171 +MIPS_INS_AVE_S_B = 172 +MIPS_INS_AVE_S_D = 173 +MIPS_INS_AVE_S_H = 174 +MIPS_INS_AVE_S_W = 175 +MIPS_INS_AVE_U_B = 176 +MIPS_INS_AVE_U_D = 177 +MIPS_INS_AVE_U_H = 178 +MIPS_INS_AVE_U_W = 179 +MIPS_INS_B16 = 180 +MIPS_INS_BADDU = 181 +MIPS_INS_BAL = 182 +MIPS_INS_BALC = 183 +MIPS_INS_BALIGN = 184 +MIPS_INS_BALRSC = 185 +MIPS_INS_BBEQZC = 186 +MIPS_INS_BBIT0 = 187 +MIPS_INS_BBIT032 = 188 +MIPS_INS_BBIT1 = 189 +MIPS_INS_BBIT132 = 190 +MIPS_INS_BBNEZC = 191 +MIPS_INS_BC = 192 +MIPS_INS_BC16 = 193 +MIPS_INS_BC1EQZ = 194 +MIPS_INS_BC1EQZC = 195 +MIPS_INS_BC1F = 196 +MIPS_INS_BC1FL = 197 +MIPS_INS_BC1NEZ = 198 +MIPS_INS_BC1NEZC = 199 +MIPS_INS_BC1T = 200 +MIPS_INS_BC1TL = 201 +MIPS_INS_BC2EQZ = 202 +MIPS_INS_BC2EQZC = 203 +MIPS_INS_BC2NEZ = 204 +MIPS_INS_BC2NEZC = 205 +MIPS_INS_BCLRI_B = 206 +MIPS_INS_BCLRI_D = 207 +MIPS_INS_BCLRI_H = 208 +MIPS_INS_BCLRI_W = 209 +MIPS_INS_BCLR_B = 210 +MIPS_INS_BCLR_D = 211 +MIPS_INS_BCLR_H = 212 +MIPS_INS_BCLR_W = 213 +MIPS_INS_BEQC = 214 +MIPS_INS_BEQIC = 215 +MIPS_INS_BEQZ16 = 216 +MIPS_INS_BEQZALC = 217 +MIPS_INS_BEQZC = 218 +MIPS_INS_BEQZC16 = 219 +MIPS_INS_BGEC = 220 +MIPS_INS_BGEIC = 221 +MIPS_INS_BGEIUC = 222 +MIPS_INS_BGEUC = 223 +MIPS_INS_BGEZ = 224 +MIPS_INS_BGEZAL = 225 +MIPS_INS_BGEZALC = 226 +MIPS_INS_BGEZALL = 227 +MIPS_INS_BGEZALS = 228 +MIPS_INS_BGEZC = 229 +MIPS_INS_BGEZL = 230 +MIPS_INS_BGTZ = 231 +MIPS_INS_BGTZALC = 232 +MIPS_INS_BGTZC = 233 +MIPS_INS_BGTZL = 234 +MIPS_INS_BINSLI_B = 235 +MIPS_INS_BINSLI_D = 236 +MIPS_INS_BINSLI_H = 237 +MIPS_INS_BINSLI_W = 238 +MIPS_INS_BINSL_B = 239 +MIPS_INS_BINSL_D = 240 +MIPS_INS_BINSL_H = 241 +MIPS_INS_BINSL_W = 242 +MIPS_INS_BINSRI_B = 243 +MIPS_INS_BINSRI_D = 244 +MIPS_INS_BINSRI_H = 245 +MIPS_INS_BINSRI_W = 246 +MIPS_INS_BINSR_B = 247 +MIPS_INS_BINSR_D = 248 +MIPS_INS_BINSR_H = 249 +MIPS_INS_BINSR_W = 250 +MIPS_INS_BITREV = 251 +MIPS_INS_BITREVW = 252 +MIPS_INS_BITSWAP = 253 +MIPS_INS_BLEZ = 254 +MIPS_INS_BLEZALC = 255 +MIPS_INS_BLEZC = 256 +MIPS_INS_BLEZL = 257 +MIPS_INS_BLTC = 258 +MIPS_INS_BLTIC = 259 +MIPS_INS_BLTIUC = 260 +MIPS_INS_BLTUC = 261 +MIPS_INS_BLTZ = 262 +MIPS_INS_BLTZAL = 263 +MIPS_INS_BLTZALC = 264 +MIPS_INS_BLTZALL = 265 +MIPS_INS_BLTZALS = 266 +MIPS_INS_BLTZC = 267 +MIPS_INS_BLTZL = 268 +MIPS_INS_BMNZI_B = 269 +MIPS_INS_BMNZ_V = 270 +MIPS_INS_BMZI_B = 271 +MIPS_INS_BMZ_V = 272 +MIPS_INS_BNEC = 273 +MIPS_INS_BNEGI_B = 274 +MIPS_INS_BNEGI_D = 275 +MIPS_INS_BNEGI_H = 276 +MIPS_INS_BNEGI_W = 277 +MIPS_INS_BNEG_B = 278 +MIPS_INS_BNEG_D = 279 +MIPS_INS_BNEG_H = 280 +MIPS_INS_BNEG_W = 281 +MIPS_INS_BNEIC = 282 +MIPS_INS_BNEZ16 = 283 +MIPS_INS_BNEZALC = 284 +MIPS_INS_BNEZC = 285 +MIPS_INS_BNEZC16 = 286 +MIPS_INS_BNVC = 287 +MIPS_INS_BNZ_B = 288 +MIPS_INS_BNZ_D = 289 +MIPS_INS_BNZ_H = 290 +MIPS_INS_BNZ_V = 291 +MIPS_INS_BNZ_W = 292 +MIPS_INS_BOVC = 293 +MIPS_INS_BPOSGE32 = 294 +MIPS_INS_BPOSGE32C = 295 +MIPS_INS_BREAK = 296 +MIPS_INS_BREAK16 = 297 +MIPS_INS_BRSC = 298 +MIPS_INS_BSELI_B = 299 +MIPS_INS_BSEL_V = 300 +MIPS_INS_BSETI_B = 301 +MIPS_INS_BSETI_D = 302 +MIPS_INS_BSETI_H = 303 +MIPS_INS_BSETI_W = 304 +MIPS_INS_BSET_B = 305 +MIPS_INS_BSET_D = 306 +MIPS_INS_BSET_H = 307 +MIPS_INS_BSET_W = 308 +MIPS_INS_BYTEREVW = 309 +MIPS_INS_BZ_B = 310 +MIPS_INS_BZ_D = 311 +MIPS_INS_BZ_H = 312 +MIPS_INS_BZ_V = 313 +MIPS_INS_BZ_W = 314 +MIPS_INS_BEQZ = 315 +MIPS_INS_BNEZ = 316 +MIPS_INS_BTEQZ = 317 +MIPS_INS_BTNEZ = 318 +MIPS_INS_CACHE = 319 +MIPS_INS_CACHEE = 320 +MIPS_INS_CEIL_L_D = 321 +MIPS_INS_CEIL_L_S = 322 +MIPS_INS_CEIL_W_D = 323 +MIPS_INS_CEIL_W_S = 324 +MIPS_INS_CEQI_B = 325 +MIPS_INS_CEQI_D = 326 +MIPS_INS_CEQI_H = 327 +MIPS_INS_CEQI_W = 328 +MIPS_INS_CEQ_B = 329 +MIPS_INS_CEQ_D = 330 +MIPS_INS_CEQ_H = 331 +MIPS_INS_CEQ_W = 332 +MIPS_INS_CFC1 = 333 +MIPS_INS_CFC2 = 334 +MIPS_INS_CFCMSA = 335 +MIPS_INS_CINS = 336 +MIPS_INS_CINS32 = 337 +MIPS_INS_CLASS_D = 338 +MIPS_INS_CLASS_S = 339 +MIPS_INS_CLEI_S_B = 340 +MIPS_INS_CLEI_S_D = 341 +MIPS_INS_CLEI_S_H = 342 +MIPS_INS_CLEI_S_W = 343 +MIPS_INS_CLEI_U_B = 344 +MIPS_INS_CLEI_U_D = 345 +MIPS_INS_CLEI_U_H = 346 +MIPS_INS_CLEI_U_W = 347 +MIPS_INS_CLE_S_B = 348 +MIPS_INS_CLE_S_D = 349 +MIPS_INS_CLE_S_H = 350 +MIPS_INS_CLE_S_W = 351 +MIPS_INS_CLE_U_B = 352 +MIPS_INS_CLE_U_D = 353 +MIPS_INS_CLE_U_H = 354 +MIPS_INS_CLE_U_W = 355 +MIPS_INS_CLO = 356 +MIPS_INS_CLTI_S_B = 357 +MIPS_INS_CLTI_S_D = 358 +MIPS_INS_CLTI_S_H = 359 +MIPS_INS_CLTI_S_W = 360 +MIPS_INS_CLTI_U_B = 361 +MIPS_INS_CLTI_U_D = 362 +MIPS_INS_CLTI_U_H = 363 +MIPS_INS_CLTI_U_W = 364 +MIPS_INS_CLT_S_B = 365 +MIPS_INS_CLT_S_D = 366 +MIPS_INS_CLT_S_H = 367 +MIPS_INS_CLT_S_W = 368 +MIPS_INS_CLT_U_B = 369 +MIPS_INS_CLT_U_D = 370 +MIPS_INS_CLT_U_H = 371 +MIPS_INS_CLT_U_W = 372 +MIPS_INS_CLZ = 373 +MIPS_INS_CMPGDU_EQ_QB = 374 +MIPS_INS_CMPGDU_LE_QB = 375 +MIPS_INS_CMPGDU_LT_QB = 376 +MIPS_INS_CMPGU_EQ_QB = 377 +MIPS_INS_CMPGU_LE_QB = 378 +MIPS_INS_CMPGU_LT_QB = 379 +MIPS_INS_CMPU_EQ_QB = 380 +MIPS_INS_CMPU_LE_QB = 381 +MIPS_INS_CMPU_LT_QB = 382 +MIPS_INS_CMP_AF_D = 383 +MIPS_INS_CMP_AF_S = 384 +MIPS_INS_CMP_EQ_D = 385 +MIPS_INS_CMP_EQ_PH = 386 +MIPS_INS_CMP_EQ_S = 387 +MIPS_INS_CMP_LE_D = 388 +MIPS_INS_CMP_LE_PH = 389 +MIPS_INS_CMP_LE_S = 390 +MIPS_INS_CMP_LT_D = 391 +MIPS_INS_CMP_LT_PH = 392 +MIPS_INS_CMP_LT_S = 393 +MIPS_INS_CMP_SAF_D = 394 +MIPS_INS_CMP_SAF_S = 395 +MIPS_INS_CMP_SEQ_D = 396 +MIPS_INS_CMP_SEQ_S = 397 +MIPS_INS_CMP_SLE_D = 398 +MIPS_INS_CMP_SLE_S = 399 +MIPS_INS_CMP_SLT_D = 400 +MIPS_INS_CMP_SLT_S = 401 +MIPS_INS_CMP_SUEQ_D = 402 +MIPS_INS_CMP_SUEQ_S = 403 +MIPS_INS_CMP_SULE_D = 404 +MIPS_INS_CMP_SULE_S = 405 +MIPS_INS_CMP_SULT_D = 406 +MIPS_INS_CMP_SULT_S = 407 +MIPS_INS_CMP_SUN_D = 408 +MIPS_INS_CMP_SUN_S = 409 +MIPS_INS_CMP_UEQ_D = 410 +MIPS_INS_CMP_UEQ_S = 411 +MIPS_INS_CMP_ULE_D = 412 +MIPS_INS_CMP_ULE_S = 413 +MIPS_INS_CMP_ULT_D = 414 +MIPS_INS_CMP_ULT_S = 415 +MIPS_INS_CMP_UN_D = 416 +MIPS_INS_CMP_UN_S = 417 +MIPS_INS_COPY_S_B = 418 +MIPS_INS_COPY_S_D = 419 +MIPS_INS_COPY_S_H = 420 +MIPS_INS_COPY_S_W = 421 +MIPS_INS_COPY_U_B = 422 +MIPS_INS_COPY_U_H = 423 +MIPS_INS_COPY_U_W = 424 +MIPS_INS_CRC32B = 425 +MIPS_INS_CRC32CB = 426 +MIPS_INS_CRC32CD = 427 +MIPS_INS_CRC32CH = 428 +MIPS_INS_CRC32CW = 429 +MIPS_INS_CRC32D = 430 +MIPS_INS_CRC32H = 431 +MIPS_INS_CRC32W = 432 +MIPS_INS_CTC1 = 433 +MIPS_INS_CTC2 = 434 +MIPS_INS_CTCMSA = 435 +MIPS_INS_CVT_D_S = 436 +MIPS_INS_CVT_D_W = 437 +MIPS_INS_CVT_D_L = 438 +MIPS_INS_CVT_L_D = 439 +MIPS_INS_CVT_L_S = 440 +MIPS_INS_CVT_PS_PW = 441 +MIPS_INS_CVT_PS_S = 442 +MIPS_INS_CVT_PW_PS = 443 +MIPS_INS_CVT_S_D = 444 +MIPS_INS_CVT_S_L = 445 +MIPS_INS_CVT_S_PL = 446 +MIPS_INS_CVT_S_PU = 447 +MIPS_INS_CVT_S_W = 448 +MIPS_INS_CVT_W_D = 449 +MIPS_INS_CVT_W_S = 450 +MIPS_INS_C_EQ_D = 451 +MIPS_INS_C_EQ_S = 452 +MIPS_INS_C_F_D = 453 +MIPS_INS_C_F_S = 454 +MIPS_INS_C_LE_D = 455 +MIPS_INS_C_LE_S = 456 +MIPS_INS_C_LT_D = 457 +MIPS_INS_C_LT_S = 458 +MIPS_INS_C_NGE_D = 459 +MIPS_INS_C_NGE_S = 460 +MIPS_INS_C_NGLE_D = 461 +MIPS_INS_C_NGLE_S = 462 +MIPS_INS_C_NGL_D = 463 +MIPS_INS_C_NGL_S = 464 +MIPS_INS_C_NGT_D = 465 +MIPS_INS_C_NGT_S = 466 +MIPS_INS_C_OLE_D = 467 +MIPS_INS_C_OLE_S = 468 +MIPS_INS_C_OLT_D = 469 +MIPS_INS_C_OLT_S = 470 +MIPS_INS_C_SEQ_D = 471 +MIPS_INS_C_SEQ_S = 472 +MIPS_INS_C_SF_D = 473 +MIPS_INS_C_SF_S = 474 +MIPS_INS_C_UEQ_D = 475 +MIPS_INS_C_UEQ_S = 476 +MIPS_INS_C_ULE_D = 477 +MIPS_INS_C_ULE_S = 478 +MIPS_INS_C_ULT_D = 479 +MIPS_INS_C_ULT_S = 480 +MIPS_INS_C_UN_D = 481 +MIPS_INS_C_UN_S = 482 +MIPS_INS_CMP = 483 +MIPS_INS_CMPI = 484 +MIPS_INS_DADD = 485 +MIPS_INS_DADDI = 486 +MIPS_INS_DADDIU = 487 +MIPS_INS_DADDU = 488 +MIPS_INS_DAHI = 489 +MIPS_INS_DALIGN = 490 +MIPS_INS_DATI = 491 +MIPS_INS_DAUI = 492 +MIPS_INS_DBITSWAP = 493 +MIPS_INS_DCLO = 494 +MIPS_INS_DCLZ = 495 +MIPS_INS_DERET = 496 +MIPS_INS_DEXT = 497 +MIPS_INS_DEXTM = 498 +MIPS_INS_DEXTU = 499 +MIPS_INS_DI = 500 +MIPS_INS_DINS = 501 +MIPS_INS_DINSM = 502 +MIPS_INS_DINSU = 503 +MIPS_INS_DIV_S_B = 504 +MIPS_INS_DIV_S_D = 505 +MIPS_INS_DIV_S_H = 506 +MIPS_INS_DIV_S_W = 507 +MIPS_INS_DIV_U_B = 508 +MIPS_INS_DIV_U_D = 509 +MIPS_INS_DIV_U_H = 510 +MIPS_INS_DIV_U_W = 511 +MIPS_INS_DLSA = 512 +MIPS_INS_DMFC0 = 513 +MIPS_INS_DMFC1 = 514 +MIPS_INS_DMFC2 = 515 +MIPS_INS_DMFGC0 = 516 +MIPS_INS_DMOD = 517 +MIPS_INS_DMODU = 518 +MIPS_INS_DMT = 519 +MIPS_INS_DMTC0 = 520 +MIPS_INS_DMTC1 = 521 +MIPS_INS_DMTC2 = 522 +MIPS_INS_DMTGC0 = 523 +MIPS_INS_DMUH = 524 +MIPS_INS_DMUHU = 525 +MIPS_INS_DMULT = 526 +MIPS_INS_DMULTU = 527 +MIPS_INS_DMULU = 528 +MIPS_INS_DOTP_S_D = 529 +MIPS_INS_DOTP_S_H = 530 +MIPS_INS_DOTP_S_W = 531 +MIPS_INS_DOTP_U_D = 532 +MIPS_INS_DOTP_U_H = 533 +MIPS_INS_DOTP_U_W = 534 +MIPS_INS_DPADD_S_D = 535 +MIPS_INS_DPADD_S_H = 536 +MIPS_INS_DPADD_S_W = 537 +MIPS_INS_DPADD_U_D = 538 +MIPS_INS_DPADD_U_H = 539 +MIPS_INS_DPADD_U_W = 540 +MIPS_INS_DPAQX_SA_W_PH = 541 +MIPS_INS_DPAQX_S_W_PH = 542 +MIPS_INS_DPAQ_SA_L_W = 543 +MIPS_INS_DPAQ_S_W_PH = 544 +MIPS_INS_DPAU_H_QBL = 545 +MIPS_INS_DPAU_H_QBR = 546 +MIPS_INS_DPAX_W_PH = 547 +MIPS_INS_DPA_W_PH = 548 +MIPS_INS_DPOP = 549 +MIPS_INS_DPSQX_SA_W_PH = 550 +MIPS_INS_DPSQX_S_W_PH = 551 +MIPS_INS_DPSQ_SA_L_W = 552 +MIPS_INS_DPSQ_S_W_PH = 553 +MIPS_INS_DPSUB_S_D = 554 +MIPS_INS_DPSUB_S_H = 555 +MIPS_INS_DPSUB_S_W = 556 +MIPS_INS_DPSUB_U_D = 557 +MIPS_INS_DPSUB_U_H = 558 +MIPS_INS_DPSUB_U_W = 559 +MIPS_INS_DPSU_H_QBL = 560 +MIPS_INS_DPSU_H_QBR = 561 +MIPS_INS_DPSX_W_PH = 562 +MIPS_INS_DPS_W_PH = 563 +MIPS_INS_DROTR = 564 +MIPS_INS_DROTR32 = 565 +MIPS_INS_DROTRV = 566 +MIPS_INS_DSBH = 567 +MIPS_INS_DSHD = 568 +MIPS_INS_DSLL = 569 +MIPS_INS_DSLL32 = 570 +MIPS_INS_DSLLV = 571 +MIPS_INS_DSRA = 572 +MIPS_INS_DSRA32 = 573 +MIPS_INS_DSRAV = 574 +MIPS_INS_DSRL = 575 +MIPS_INS_DSRL32 = 576 +MIPS_INS_DSRLV = 577 +MIPS_INS_DSUB = 578 +MIPS_INS_DSUBU = 579 +MIPS_INS_DVP = 580 +MIPS_INS_DVPE = 581 +MIPS_INS_EHB = 582 +MIPS_INS_EI = 583 +MIPS_INS_EMT = 584 +MIPS_INS_ERET = 585 +MIPS_INS_ERETNC = 586 +MIPS_INS_EVP = 587 +MIPS_INS_EVPE = 588 +MIPS_INS_EXT = 589 +MIPS_INS_EXTP = 590 +MIPS_INS_EXTPDP = 591 +MIPS_INS_EXTPDPV = 592 +MIPS_INS_EXTPV = 593 +MIPS_INS_EXTRV_RS_W = 594 +MIPS_INS_EXTRV_R_W = 595 +MIPS_INS_EXTRV_S_H = 596 +MIPS_INS_EXTRV_W = 597 +MIPS_INS_EXTR_RS_W = 598 +MIPS_INS_EXTR_R_W = 599 +MIPS_INS_EXTR_S_H = 600 +MIPS_INS_EXTR_W = 601 +MIPS_INS_EXTS = 602 +MIPS_INS_EXTS32 = 603 +MIPS_INS_EXTW = 604 +MIPS_INS_ABS_D = 605 +MIPS_INS_ABS_S = 606 +MIPS_INS_FADD_D = 607 +MIPS_INS_ADD_D = 608 +MIPS_INS_ADD_PS = 609 +MIPS_INS_ADD_S = 610 +MIPS_INS_FADD_W = 611 +MIPS_INS_FCAF_D = 612 +MIPS_INS_FCAF_W = 613 +MIPS_INS_FCEQ_D = 614 +MIPS_INS_FCEQ_W = 615 +MIPS_INS_FCLASS_D = 616 +MIPS_INS_FCLASS_W = 617 +MIPS_INS_FCLE_D = 618 +MIPS_INS_FCLE_W = 619 +MIPS_INS_FCLT_D = 620 +MIPS_INS_FCLT_W = 621 +MIPS_INS_FCNE_D = 622 +MIPS_INS_FCNE_W = 623 +MIPS_INS_FCOR_D = 624 +MIPS_INS_FCOR_W = 625 +MIPS_INS_FCUEQ_D = 626 +MIPS_INS_FCUEQ_W = 627 +MIPS_INS_FCULE_D = 628 +MIPS_INS_FCULE_W = 629 +MIPS_INS_FCULT_D = 630 +MIPS_INS_FCULT_W = 631 +MIPS_INS_FCUNE_D = 632 +MIPS_INS_FCUNE_W = 633 +MIPS_INS_FCUN_D = 634 +MIPS_INS_FCUN_W = 635 +MIPS_INS_FDIV_D = 636 +MIPS_INS_DIV_D = 637 +MIPS_INS_DIV_S = 638 +MIPS_INS_FDIV_W = 639 +MIPS_INS_FEXDO_H = 640 +MIPS_INS_FEXDO_W = 641 +MIPS_INS_FEXP2_D = 642 +MIPS_INS_FEXP2_W = 643 +MIPS_INS_FEXUPL_D = 644 +MIPS_INS_FEXUPL_W = 645 +MIPS_INS_FEXUPR_D = 646 +MIPS_INS_FEXUPR_W = 647 +MIPS_INS_FFINT_S_D = 648 +MIPS_INS_FFINT_S_W = 649 +MIPS_INS_FFINT_U_D = 650 +MIPS_INS_FFINT_U_W = 651 +MIPS_INS_FFQL_D = 652 +MIPS_INS_FFQL_W = 653 +MIPS_INS_FFQR_D = 654 +MIPS_INS_FFQR_W = 655 +MIPS_INS_FILL_B = 656 +MIPS_INS_FILL_D = 657 +MIPS_INS_FILL_H = 658 +MIPS_INS_FILL_W = 659 +MIPS_INS_FLOG2_D = 660 +MIPS_INS_FLOG2_W = 661 +MIPS_INS_FLOOR_L_D = 662 +MIPS_INS_FLOOR_L_S = 663 +MIPS_INS_FLOOR_W_D = 664 +MIPS_INS_FLOOR_W_S = 665 +MIPS_INS_FMADD_D = 666 +MIPS_INS_FMADD_W = 667 +MIPS_INS_FMAX_A_D = 668 +MIPS_INS_FMAX_A_W = 669 +MIPS_INS_FMAX_D = 670 +MIPS_INS_FMAX_W = 671 +MIPS_INS_FMIN_A_D = 672 +MIPS_INS_FMIN_A_W = 673 +MIPS_INS_FMIN_D = 674 +MIPS_INS_FMIN_W = 675 +MIPS_INS_MOV_D = 676 +MIPS_INS_MOV_S = 677 +MIPS_INS_FMSUB_D = 678 +MIPS_INS_FMSUB_W = 679 +MIPS_INS_FMUL_D = 680 +MIPS_INS_MUL_D = 681 +MIPS_INS_MUL_PS = 682 +MIPS_INS_MUL_S = 683 +MIPS_INS_FMUL_W = 684 +MIPS_INS_NEG_D = 685 +MIPS_INS_NEG_S = 686 +MIPS_INS_FORK = 687 +MIPS_INS_FRCP_D = 688 +MIPS_INS_FRCP_W = 689 +MIPS_INS_FRINT_D = 690 +MIPS_INS_FRINT_W = 691 +MIPS_INS_FRSQRT_D = 692 +MIPS_INS_FRSQRT_W = 693 +MIPS_INS_FSAF_D = 694 +MIPS_INS_FSAF_W = 695 +MIPS_INS_FSEQ_D = 696 +MIPS_INS_FSEQ_W = 697 +MIPS_INS_FSLE_D = 698 +MIPS_INS_FSLE_W = 699 +MIPS_INS_FSLT_D = 700 +MIPS_INS_FSLT_W = 701 +MIPS_INS_FSNE_D = 702 +MIPS_INS_FSNE_W = 703 +MIPS_INS_FSOR_D = 704 +MIPS_INS_FSOR_W = 705 +MIPS_INS_FSQRT_D = 706 +MIPS_INS_SQRT_D = 707 +MIPS_INS_SQRT_S = 708 +MIPS_INS_FSQRT_W = 709 +MIPS_INS_FSUB_D = 710 +MIPS_INS_SUB_D = 711 +MIPS_INS_SUB_PS = 712 +MIPS_INS_SUB_S = 713 +MIPS_INS_FSUB_W = 714 +MIPS_INS_FSUEQ_D = 715 +MIPS_INS_FSUEQ_W = 716 +MIPS_INS_FSULE_D = 717 +MIPS_INS_FSULE_W = 718 +MIPS_INS_FSULT_D = 719 +MIPS_INS_FSULT_W = 720 +MIPS_INS_FSUNE_D = 721 +MIPS_INS_FSUNE_W = 722 +MIPS_INS_FSUN_D = 723 +MIPS_INS_FSUN_W = 724 +MIPS_INS_FTINT_S_D = 725 +MIPS_INS_FTINT_S_W = 726 +MIPS_INS_FTINT_U_D = 727 +MIPS_INS_FTINT_U_W = 728 +MIPS_INS_FTQ_H = 729 +MIPS_INS_FTQ_W = 730 +MIPS_INS_FTRUNC_S_D = 731 +MIPS_INS_FTRUNC_S_W = 732 +MIPS_INS_FTRUNC_U_D = 733 +MIPS_INS_FTRUNC_U_W = 734 +MIPS_INS_GINVI = 735 +MIPS_INS_GINVT = 736 +MIPS_INS_HADD_S_D = 737 +MIPS_INS_HADD_S_H = 738 +MIPS_INS_HADD_S_W = 739 +MIPS_INS_HADD_U_D = 740 +MIPS_INS_HADD_U_H = 741 +MIPS_INS_HADD_U_W = 742 +MIPS_INS_HSUB_S_D = 743 +MIPS_INS_HSUB_S_H = 744 +MIPS_INS_HSUB_S_W = 745 +MIPS_INS_HSUB_U_D = 746 +MIPS_INS_HSUB_U_H = 747 +MIPS_INS_HSUB_U_W = 748 +MIPS_INS_HYPCALL = 749 +MIPS_INS_ILVEV_B = 750 +MIPS_INS_ILVEV_D = 751 +MIPS_INS_ILVEV_H = 752 +MIPS_INS_ILVEV_W = 753 +MIPS_INS_ILVL_B = 754 +MIPS_INS_ILVL_D = 755 +MIPS_INS_ILVL_H = 756 +MIPS_INS_ILVL_W = 757 +MIPS_INS_ILVOD_B = 758 +MIPS_INS_ILVOD_D = 759 +MIPS_INS_ILVOD_H = 760 +MIPS_INS_ILVOD_W = 761 +MIPS_INS_ILVR_B = 762 +MIPS_INS_ILVR_D = 763 +MIPS_INS_ILVR_H = 764 +MIPS_INS_ILVR_W = 765 +MIPS_INS_INS = 766 +MIPS_INS_INSERT_B = 767 +MIPS_INS_INSERT_D = 768 +MIPS_INS_INSERT_H = 769 +MIPS_INS_INSERT_W = 770 +MIPS_INS_INSV = 771 +MIPS_INS_INSVE_B = 772 +MIPS_INS_INSVE_D = 773 +MIPS_INS_INSVE_H = 774 +MIPS_INS_INSVE_W = 775 +MIPS_INS_J = 776 +MIPS_INS_JALR = 777 +MIPS_INS_JALRC = 778 +MIPS_INS_JALRC_HB = 779 +MIPS_INS_JALRS16 = 780 +MIPS_INS_JALRS = 781 +MIPS_INS_JALR_HB = 782 +MIPS_INS_JALS = 783 +MIPS_INS_JALX = 784 +MIPS_INS_JIALC = 785 +MIPS_INS_JIC = 786 +MIPS_INS_JR = 787 +MIPS_INS_JR16 = 788 +MIPS_INS_JRADDIUSP = 789 +MIPS_INS_JRC = 790 +MIPS_INS_JRC16 = 791 +MIPS_INS_JRCADDIUSP = 792 +MIPS_INS_JR_HB = 793 +MIPS_INS_LAPC_H = 794 +MIPS_INS_LAPC_B = 795 +MIPS_INS_LB = 796 +MIPS_INS_LBE = 797 +MIPS_INS_LBU16 = 798 +MIPS_INS_LBU = 799 +MIPS_INS_LBUX = 800 +MIPS_INS_LBX = 801 +MIPS_INS_LBUE = 802 +MIPS_INS_LDC1 = 803 +MIPS_INS_LDC2 = 804 +MIPS_INS_LDC3 = 805 +MIPS_INS_LDI_B = 806 +MIPS_INS_LDI_D = 807 +MIPS_INS_LDI_H = 808 +MIPS_INS_LDI_W = 809 +MIPS_INS_LDL = 810 +MIPS_INS_LDPC = 811 +MIPS_INS_LDR = 812 +MIPS_INS_LDXC1 = 813 +MIPS_INS_LD_B = 814 +MIPS_INS_LD_D = 815 +MIPS_INS_LD_H = 816 +MIPS_INS_LD_W = 817 +MIPS_INS_LH = 818 +MIPS_INS_LHE = 819 +MIPS_INS_LHU16 = 820 +MIPS_INS_LHU = 821 +MIPS_INS_LHUXS = 822 +MIPS_INS_LHUX = 823 +MIPS_INS_LHX = 824 +MIPS_INS_LHXS = 825 +MIPS_INS_LHUE = 826 +MIPS_INS_LI16 = 827 +MIPS_INS_LL = 828 +MIPS_INS_LLD = 829 +MIPS_INS_LLE = 830 +MIPS_INS_LLWP = 831 +MIPS_INS_LSA = 832 +MIPS_INS_LUI = 833 +MIPS_INS_LUXC1 = 834 +MIPS_INS_LW = 835 +MIPS_INS_LW16 = 836 +MIPS_INS_LWC1 = 837 +MIPS_INS_LWC2 = 838 +MIPS_INS_LWC3 = 839 +MIPS_INS_LWE = 840 +MIPS_INS_LWL = 841 +MIPS_INS_LWLE = 842 +MIPS_INS_LWM16 = 843 +MIPS_INS_LWM32 = 844 +MIPS_INS_LWPC = 845 +MIPS_INS_LWP = 846 +MIPS_INS_LWR = 847 +MIPS_INS_LWRE = 848 +MIPS_INS_LWUPC = 849 +MIPS_INS_LWU = 850 +MIPS_INS_LWX = 851 +MIPS_INS_LWXC1 = 852 +MIPS_INS_LWXS = 853 +MIPS_INS_MADD = 854 +MIPS_INS_MADDF_D = 855 +MIPS_INS_MADDF_S = 856 +MIPS_INS_MADDR_Q_H = 857 +MIPS_INS_MADDR_Q_W = 858 +MIPS_INS_MADDU = 859 +MIPS_INS_MADDV_B = 860 +MIPS_INS_MADDV_D = 861 +MIPS_INS_MADDV_H = 862 +MIPS_INS_MADDV_W = 863 +MIPS_INS_MADD_D = 864 +MIPS_INS_MADD_Q_H = 865 +MIPS_INS_MADD_Q_W = 866 +MIPS_INS_MADD_S = 867 +MIPS_INS_MAQ_SA_W_PHL = 868 +MIPS_INS_MAQ_SA_W_PHR = 869 +MIPS_INS_MAQ_S_W_PHL = 870 +MIPS_INS_MAQ_S_W_PHR = 871 +MIPS_INS_MAXA_D = 872 +MIPS_INS_MAXA_S = 873 +MIPS_INS_MAXI_S_B = 874 +MIPS_INS_MAXI_S_D = 875 +MIPS_INS_MAXI_S_H = 876 +MIPS_INS_MAXI_S_W = 877 +MIPS_INS_MAXI_U_B = 878 +MIPS_INS_MAXI_U_D = 879 +MIPS_INS_MAXI_U_H = 880 +MIPS_INS_MAXI_U_W = 881 +MIPS_INS_MAX_A_B = 882 +MIPS_INS_MAX_A_D = 883 +MIPS_INS_MAX_A_H = 884 +MIPS_INS_MAX_A_W = 885 +MIPS_INS_MAX_D = 886 +MIPS_INS_MAX_S = 887 +MIPS_INS_MAX_S_B = 888 +MIPS_INS_MAX_S_D = 889 +MIPS_INS_MAX_S_H = 890 +MIPS_INS_MAX_S_W = 891 +MIPS_INS_MAX_U_B = 892 +MIPS_INS_MAX_U_D = 893 +MIPS_INS_MAX_U_H = 894 +MIPS_INS_MAX_U_W = 895 +MIPS_INS_MFC0 = 896 +MIPS_INS_MFC1 = 897 +MIPS_INS_MFC2 = 898 +MIPS_INS_MFGC0 = 899 +MIPS_INS_MFHC0 = 900 +MIPS_INS_MFHC1 = 901 +MIPS_INS_MFHC2 = 902 +MIPS_INS_MFHGC0 = 903 +MIPS_INS_MFHI = 904 +MIPS_INS_MFHI16 = 905 +MIPS_INS_MFLO = 906 +MIPS_INS_MFLO16 = 907 +MIPS_INS_MFTR = 908 +MIPS_INS_MINA_D = 909 +MIPS_INS_MINA_S = 910 +MIPS_INS_MINI_S_B = 911 +MIPS_INS_MINI_S_D = 912 +MIPS_INS_MINI_S_H = 913 +MIPS_INS_MINI_S_W = 914 +MIPS_INS_MINI_U_B = 915 +MIPS_INS_MINI_U_D = 916 +MIPS_INS_MINI_U_H = 917 +MIPS_INS_MINI_U_W = 918 +MIPS_INS_MIN_A_B = 919 +MIPS_INS_MIN_A_D = 920 +MIPS_INS_MIN_A_H = 921 +MIPS_INS_MIN_A_W = 922 +MIPS_INS_MIN_D = 923 +MIPS_INS_MIN_S = 924 +MIPS_INS_MIN_S_B = 925 +MIPS_INS_MIN_S_D = 926 +MIPS_INS_MIN_S_H = 927 +MIPS_INS_MIN_S_W = 928 +MIPS_INS_MIN_U_B = 929 +MIPS_INS_MIN_U_D = 930 +MIPS_INS_MIN_U_H = 931 +MIPS_INS_MIN_U_W = 932 +MIPS_INS_MOD = 933 +MIPS_INS_MODSUB = 934 +MIPS_INS_MODU = 935 +MIPS_INS_MOD_S_B = 936 +MIPS_INS_MOD_S_D = 937 +MIPS_INS_MOD_S_H = 938 +MIPS_INS_MOD_S_W = 939 +MIPS_INS_MOD_U_B = 940 +MIPS_INS_MOD_U_D = 941 +MIPS_INS_MOD_U_H = 942 +MIPS_INS_MOD_U_W = 943 +MIPS_INS_MOVE = 944 +MIPS_INS_MOVE16 = 945 +MIPS_INS_MOVE_BALC = 946 +MIPS_INS_MOVEP = 947 +MIPS_INS_MOVE_V = 948 +MIPS_INS_MOVF_D = 949 +MIPS_INS_MOVF = 950 +MIPS_INS_MOVF_S = 951 +MIPS_INS_MOVN_D = 952 +MIPS_INS_MOVN = 953 +MIPS_INS_MOVN_S = 954 +MIPS_INS_MOVT_D = 955 +MIPS_INS_MOVT = 956 +MIPS_INS_MOVT_S = 957 +MIPS_INS_MOVZ_D = 958 +MIPS_INS_MOVZ = 959 +MIPS_INS_MOVZ_S = 960 +MIPS_INS_MSUB = 961 +MIPS_INS_MSUBF_D = 962 +MIPS_INS_MSUBF_S = 963 +MIPS_INS_MSUBR_Q_H = 964 +MIPS_INS_MSUBR_Q_W = 965 +MIPS_INS_MSUBU = 966 +MIPS_INS_MSUBV_B = 967 +MIPS_INS_MSUBV_D = 968 +MIPS_INS_MSUBV_H = 969 +MIPS_INS_MSUBV_W = 970 +MIPS_INS_MSUB_D = 971 +MIPS_INS_MSUB_Q_H = 972 +MIPS_INS_MSUB_Q_W = 973 +MIPS_INS_MSUB_S = 974 +MIPS_INS_MTC0 = 975 +MIPS_INS_MTC1 = 976 +MIPS_INS_MTC2 = 977 +MIPS_INS_MTGC0 = 978 +MIPS_INS_MTHC0 = 979 +MIPS_INS_MTHC1 = 980 +MIPS_INS_MTHC2 = 981 +MIPS_INS_MTHGC0 = 982 +MIPS_INS_MTHI = 983 +MIPS_INS_MTHLIP = 984 +MIPS_INS_MTLO = 985 +MIPS_INS_MTM0 = 986 +MIPS_INS_MTM1 = 987 +MIPS_INS_MTM2 = 988 +MIPS_INS_MTP0 = 989 +MIPS_INS_MTP1 = 990 +MIPS_INS_MTP2 = 991 +MIPS_INS_MTTR = 992 +MIPS_INS_MUH = 993 +MIPS_INS_MUHU = 994 +MIPS_INS_MULEQ_S_W_PHL = 995 +MIPS_INS_MULEQ_S_W_PHR = 996 +MIPS_INS_MULEU_S_PH_QBL = 997 +MIPS_INS_MULEU_S_PH_QBR = 998 +MIPS_INS_MULQ_RS_PH = 999 +MIPS_INS_MULQ_RS_W = 1000 +MIPS_INS_MULQ_S_PH = 1001 +MIPS_INS_MULQ_S_W = 1002 +MIPS_INS_MULR_PS = 1003 +MIPS_INS_MULR_Q_H = 1004 +MIPS_INS_MULR_Q_W = 1005 +MIPS_INS_MULSAQ_S_W_PH = 1006 +MIPS_INS_MULSA_W_PH = 1007 +MIPS_INS_MULT = 1008 +MIPS_INS_MULTU = 1009 +MIPS_INS_MULU = 1010 +MIPS_INS_MULV_B = 1011 +MIPS_INS_MULV_D = 1012 +MIPS_INS_MULV_H = 1013 +MIPS_INS_MULV_W = 1014 +MIPS_INS_MUL_PH = 1015 +MIPS_INS_MUL_Q_H = 1016 +MIPS_INS_MUL_Q_W = 1017 +MIPS_INS_MUL_S_PH = 1018 +MIPS_INS_NLOC_B = 1019 +MIPS_INS_NLOC_D = 1020 +MIPS_INS_NLOC_H = 1021 +MIPS_INS_NLOC_W = 1022 +MIPS_INS_NLZC_B = 1023 +MIPS_INS_NLZC_D = 1024 +MIPS_INS_NLZC_H = 1025 +MIPS_INS_NLZC_W = 1026 +MIPS_INS_NMADD_D = 1027 +MIPS_INS_NMADD_S = 1028 +MIPS_INS_NMSUB_D = 1029 +MIPS_INS_NMSUB_S = 1030 +MIPS_INS_NOP32 = 1031 +MIPS_INS_NOP = 1032 +MIPS_INS_NORI_B = 1033 +MIPS_INS_NOR_V = 1034 +MIPS_INS_NOT16 = 1035 +MIPS_INS_NOT = 1036 +MIPS_INS_NEG = 1037 +MIPS_INS_OR = 1038 +MIPS_INS_OR16 = 1039 +MIPS_INS_ORI_B = 1040 +MIPS_INS_ORI = 1041 +MIPS_INS_OR_V = 1042 +MIPS_INS_PACKRL_PH = 1043 +MIPS_INS_PAUSE = 1044 +MIPS_INS_PCKEV_B = 1045 +MIPS_INS_PCKEV_D = 1046 +MIPS_INS_PCKEV_H = 1047 +MIPS_INS_PCKEV_W = 1048 +MIPS_INS_PCKOD_B = 1049 +MIPS_INS_PCKOD_D = 1050 +MIPS_INS_PCKOD_H = 1051 +MIPS_INS_PCKOD_W = 1052 +MIPS_INS_PCNT_B = 1053 +MIPS_INS_PCNT_D = 1054 +MIPS_INS_PCNT_H = 1055 +MIPS_INS_PCNT_W = 1056 +MIPS_INS_PICK_PH = 1057 +MIPS_INS_PICK_QB = 1058 +MIPS_INS_PLL_PS = 1059 +MIPS_INS_PLU_PS = 1060 +MIPS_INS_POP = 1061 +MIPS_INS_PRECEQU_PH_QBL = 1062 +MIPS_INS_PRECEQU_PH_QBLA = 1063 +MIPS_INS_PRECEQU_PH_QBR = 1064 +MIPS_INS_PRECEQU_PH_QBRA = 1065 +MIPS_INS_PRECEQ_W_PHL = 1066 +MIPS_INS_PRECEQ_W_PHR = 1067 +MIPS_INS_PRECEU_PH_QBL = 1068 +MIPS_INS_PRECEU_PH_QBLA = 1069 +MIPS_INS_PRECEU_PH_QBR = 1070 +MIPS_INS_PRECEU_PH_QBRA = 1071 +MIPS_INS_PRECRQU_S_QB_PH = 1072 +MIPS_INS_PRECRQ_PH_W = 1073 +MIPS_INS_PRECRQ_QB_PH = 1074 +MIPS_INS_PRECRQ_RS_PH_W = 1075 +MIPS_INS_PRECR_QB_PH = 1076 +MIPS_INS_PRECR_SRA_PH_W = 1077 +MIPS_INS_PRECR_SRA_R_PH_W = 1078 +MIPS_INS_PREF = 1079 +MIPS_INS_PREFE = 1080 +MIPS_INS_PREFX = 1081 +MIPS_INS_PREPEND = 1082 +MIPS_INS_PUL_PS = 1083 +MIPS_INS_PUU_PS = 1084 +MIPS_INS_RADDU_W_QB = 1085 +MIPS_INS_RDDSP = 1086 +MIPS_INS_RDHWR = 1087 +MIPS_INS_RDPGPR = 1088 +MIPS_INS_RECIP_D = 1089 +MIPS_INS_RECIP_S = 1090 +MIPS_INS_REPLV_PH = 1091 +MIPS_INS_REPLV_QB = 1092 +MIPS_INS_REPL_PH = 1093 +MIPS_INS_REPL_QB = 1094 +MIPS_INS_RESTORE_JRC = 1095 +MIPS_INS_RESTORE = 1096 +MIPS_INS_RINT_D = 1097 +MIPS_INS_RINT_S = 1098 +MIPS_INS_ROTR = 1099 +MIPS_INS_ROTRV = 1100 +MIPS_INS_ROTX = 1101 +MIPS_INS_ROUND_L_D = 1102 +MIPS_INS_ROUND_L_S = 1103 +MIPS_INS_ROUND_W_D = 1104 +MIPS_INS_ROUND_W_S = 1105 +MIPS_INS_RSQRT_D = 1106 +MIPS_INS_RSQRT_S = 1107 +MIPS_INS_SAT_S_B = 1108 +MIPS_INS_SAT_S_D = 1109 +MIPS_INS_SAT_S_H = 1110 +MIPS_INS_SAT_S_W = 1111 +MIPS_INS_SAT_U_B = 1112 +MIPS_INS_SAT_U_D = 1113 +MIPS_INS_SAT_U_H = 1114 +MIPS_INS_SAT_U_W = 1115 +MIPS_INS_SAVE = 1116 +MIPS_INS_SB = 1117 +MIPS_INS_SB16 = 1118 +MIPS_INS_SBE = 1119 +MIPS_INS_SBX = 1120 +MIPS_INS_SC = 1121 +MIPS_INS_SCD = 1122 +MIPS_INS_SCE = 1123 +MIPS_INS_SCWP = 1124 +MIPS_INS_SDBBP = 1125 +MIPS_INS_SDBBP16 = 1126 +MIPS_INS_SDC1 = 1127 +MIPS_INS_SDC2 = 1128 +MIPS_INS_SDC3 = 1129 +MIPS_INS_SDL = 1130 +MIPS_INS_SDR = 1131 +MIPS_INS_SDXC1 = 1132 +MIPS_INS_SEB = 1133 +MIPS_INS_SEH = 1134 +MIPS_INS_SELEQZ = 1135 +MIPS_INS_SELEQZ_D = 1136 +MIPS_INS_SELEQZ_S = 1137 +MIPS_INS_SELNEZ = 1138 +MIPS_INS_SELNEZ_D = 1139 +MIPS_INS_SELNEZ_S = 1140 +MIPS_INS_SEL_D = 1141 +MIPS_INS_SEL_S = 1142 +MIPS_INS_SEQI = 1143 +MIPS_INS_SH = 1144 +MIPS_INS_SH16 = 1145 +MIPS_INS_SHE = 1146 +MIPS_INS_SHF_B = 1147 +MIPS_INS_SHF_H = 1148 +MIPS_INS_SHF_W = 1149 +MIPS_INS_SHILO = 1150 +MIPS_INS_SHILOV = 1151 +MIPS_INS_SHLLV_PH = 1152 +MIPS_INS_SHLLV_QB = 1153 +MIPS_INS_SHLLV_S_PH = 1154 +MIPS_INS_SHLLV_S_W = 1155 +MIPS_INS_SHLL_PH = 1156 +MIPS_INS_SHLL_QB = 1157 +MIPS_INS_SHLL_S_PH = 1158 +MIPS_INS_SHLL_S_W = 1159 +MIPS_INS_SHRAV_PH = 1160 +MIPS_INS_SHRAV_QB = 1161 +MIPS_INS_SHRAV_R_PH = 1162 +MIPS_INS_SHRAV_R_QB = 1163 +MIPS_INS_SHRAV_R_W = 1164 +MIPS_INS_SHRA_PH = 1165 +MIPS_INS_SHRA_QB = 1166 +MIPS_INS_SHRA_R_PH = 1167 +MIPS_INS_SHRA_R_QB = 1168 +MIPS_INS_SHRA_R_W = 1169 +MIPS_INS_SHRLV_PH = 1170 +MIPS_INS_SHRLV_QB = 1171 +MIPS_INS_SHRL_PH = 1172 +MIPS_INS_SHRL_QB = 1173 +MIPS_INS_SHXS = 1174 +MIPS_INS_SHX = 1175 +MIPS_INS_SIGRIE = 1176 +MIPS_INS_SLDI_B = 1177 +MIPS_INS_SLDI_D = 1178 +MIPS_INS_SLDI_H = 1179 +MIPS_INS_SLDI_W = 1180 +MIPS_INS_SLD_B = 1181 +MIPS_INS_SLD_D = 1182 +MIPS_INS_SLD_H = 1183 +MIPS_INS_SLD_W = 1184 +MIPS_INS_SLL = 1185 +MIPS_INS_SLL16 = 1186 +MIPS_INS_SLLI_B = 1187 +MIPS_INS_SLLI_D = 1188 +MIPS_INS_SLLI_H = 1189 +MIPS_INS_SLLI_W = 1190 +MIPS_INS_SLLV = 1191 +MIPS_INS_SLL_B = 1192 +MIPS_INS_SLL_D = 1193 +MIPS_INS_SLL_H = 1194 +MIPS_INS_SLL_W = 1195 +MIPS_INS_SLTIU = 1196 +MIPS_INS_SLTI = 1197 +MIPS_INS_SNEI = 1198 +MIPS_INS_SOV = 1199 +MIPS_INS_SPLATI_B = 1200 +MIPS_INS_SPLATI_D = 1201 +MIPS_INS_SPLATI_H = 1202 +MIPS_INS_SPLATI_W = 1203 +MIPS_INS_SPLAT_B = 1204 +MIPS_INS_SPLAT_D = 1205 +MIPS_INS_SPLAT_H = 1206 +MIPS_INS_SPLAT_W = 1207 +MIPS_INS_SRA = 1208 +MIPS_INS_SRAI_B = 1209 +MIPS_INS_SRAI_D = 1210 +MIPS_INS_SRAI_H = 1211 +MIPS_INS_SRAI_W = 1212 +MIPS_INS_SRARI_B = 1213 +MIPS_INS_SRARI_D = 1214 +MIPS_INS_SRARI_H = 1215 +MIPS_INS_SRARI_W = 1216 +MIPS_INS_SRAR_B = 1217 +MIPS_INS_SRAR_D = 1218 +MIPS_INS_SRAR_H = 1219 +MIPS_INS_SRAR_W = 1220 +MIPS_INS_SRAV = 1221 +MIPS_INS_SRA_B = 1222 +MIPS_INS_SRA_D = 1223 +MIPS_INS_SRA_H = 1224 +MIPS_INS_SRA_W = 1225 +MIPS_INS_SRL = 1226 +MIPS_INS_SRL16 = 1227 +MIPS_INS_SRLI_B = 1228 +MIPS_INS_SRLI_D = 1229 +MIPS_INS_SRLI_H = 1230 +MIPS_INS_SRLI_W = 1231 +MIPS_INS_SRLRI_B = 1232 +MIPS_INS_SRLRI_D = 1233 +MIPS_INS_SRLRI_H = 1234 +MIPS_INS_SRLRI_W = 1235 +MIPS_INS_SRLR_B = 1236 +MIPS_INS_SRLR_D = 1237 +MIPS_INS_SRLR_H = 1238 +MIPS_INS_SRLR_W = 1239 +MIPS_INS_SRLV = 1240 +MIPS_INS_SRL_B = 1241 +MIPS_INS_SRL_D = 1242 +MIPS_INS_SRL_H = 1243 +MIPS_INS_SRL_W = 1244 +MIPS_INS_SSNOP = 1245 +MIPS_INS_ST_B = 1246 +MIPS_INS_ST_D = 1247 +MIPS_INS_ST_H = 1248 +MIPS_INS_ST_W = 1249 +MIPS_INS_SUB = 1250 +MIPS_INS_SUBQH_PH = 1251 +MIPS_INS_SUBQH_R_PH = 1252 +MIPS_INS_SUBQH_R_W = 1253 +MIPS_INS_SUBQH_W = 1254 +MIPS_INS_SUBQ_PH = 1255 +MIPS_INS_SUBQ_S_PH = 1256 +MIPS_INS_SUBQ_S_W = 1257 +MIPS_INS_SUBSUS_U_B = 1258 +MIPS_INS_SUBSUS_U_D = 1259 +MIPS_INS_SUBSUS_U_H = 1260 +MIPS_INS_SUBSUS_U_W = 1261 +MIPS_INS_SUBSUU_S_B = 1262 +MIPS_INS_SUBSUU_S_D = 1263 +MIPS_INS_SUBSUU_S_H = 1264 +MIPS_INS_SUBSUU_S_W = 1265 +MIPS_INS_SUBS_S_B = 1266 +MIPS_INS_SUBS_S_D = 1267 +MIPS_INS_SUBS_S_H = 1268 +MIPS_INS_SUBS_S_W = 1269 +MIPS_INS_SUBS_U_B = 1270 +MIPS_INS_SUBS_U_D = 1271 +MIPS_INS_SUBS_U_H = 1272 +MIPS_INS_SUBS_U_W = 1273 +MIPS_INS_SUBU16 = 1274 +MIPS_INS_SUBUH_QB = 1275 +MIPS_INS_SUBUH_R_QB = 1276 +MIPS_INS_SUBU_PH = 1277 +MIPS_INS_SUBU_QB = 1278 +MIPS_INS_SUBU_S_PH = 1279 +MIPS_INS_SUBU_S_QB = 1280 +MIPS_INS_SUBVI_B = 1281 +MIPS_INS_SUBVI_D = 1282 +MIPS_INS_SUBVI_H = 1283 +MIPS_INS_SUBVI_W = 1284 +MIPS_INS_SUBV_B = 1285 +MIPS_INS_SUBV_D = 1286 +MIPS_INS_SUBV_H = 1287 +MIPS_INS_SUBV_W = 1288 +MIPS_INS_SUXC1 = 1289 +MIPS_INS_SW = 1290 +MIPS_INS_SW16 = 1291 +MIPS_INS_SWC1 = 1292 +MIPS_INS_SWC2 = 1293 +MIPS_INS_SWC3 = 1294 +MIPS_INS_SWE = 1295 +MIPS_INS_SWL = 1296 +MIPS_INS_SWLE = 1297 +MIPS_INS_SWM16 = 1298 +MIPS_INS_SWM32 = 1299 +MIPS_INS_SWPC = 1300 +MIPS_INS_SWP = 1301 +MIPS_INS_SWR = 1302 +MIPS_INS_SWRE = 1303 +MIPS_INS_SWSP = 1304 +MIPS_INS_SWXC1 = 1305 +MIPS_INS_SWXS = 1306 +MIPS_INS_SWX = 1307 +MIPS_INS_SYNC = 1308 +MIPS_INS_SYNCI = 1309 +MIPS_INS_SYSCALL = 1310 +MIPS_INS_TEQ = 1311 +MIPS_INS_TEQI = 1312 +MIPS_INS_TGE = 1313 +MIPS_INS_TGEI = 1314 +MIPS_INS_TGEIU = 1315 +MIPS_INS_TGEU = 1316 +MIPS_INS_TLBGINV = 1317 +MIPS_INS_TLBGINVF = 1318 +MIPS_INS_TLBGP = 1319 +MIPS_INS_TLBGR = 1320 +MIPS_INS_TLBGWI = 1321 +MIPS_INS_TLBGWR = 1322 +MIPS_INS_TLBINV = 1323 +MIPS_INS_TLBINVF = 1324 +MIPS_INS_TLBP = 1325 +MIPS_INS_TLBR = 1326 +MIPS_INS_TLBWI = 1327 +MIPS_INS_TLBWR = 1328 +MIPS_INS_TLT = 1329 +MIPS_INS_TLTI = 1330 +MIPS_INS_TLTIU = 1331 +MIPS_INS_TLTU = 1332 +MIPS_INS_TNE = 1333 +MIPS_INS_TNEI = 1334 +MIPS_INS_TRUNC_L_D = 1335 +MIPS_INS_TRUNC_L_S = 1336 +MIPS_INS_UALH = 1337 +MIPS_INS_UALWM = 1338 +MIPS_INS_UALW = 1339 +MIPS_INS_UASH = 1340 +MIPS_INS_UASWM = 1341 +MIPS_INS_UASW = 1342 +MIPS_INS_V3MULU = 1343 +MIPS_INS_VMM0 = 1344 +MIPS_INS_VMULU = 1345 +MIPS_INS_VSHF_B = 1346 +MIPS_INS_VSHF_D = 1347 +MIPS_INS_VSHF_H = 1348 +MIPS_INS_VSHF_W = 1349 +MIPS_INS_WAIT = 1350 +MIPS_INS_WRDSP = 1351 +MIPS_INS_WRPGPR = 1352 +MIPS_INS_WSBH = 1353 +MIPS_INS_XOR = 1354 +MIPS_INS_XOR16 = 1355 +MIPS_INS_XORI_B = 1356 +MIPS_INS_XORI = 1357 +MIPS_INS_XOR_V = 1358 +MIPS_INS_YIELD = 1359 +MIPS_INS_ENDING = 1360 +MIPS_INS_ALIAS_BEGIN = 1361 +MIPS_INS_ALIAS_ADDIU_B32 = 1362 +MIPS_INS_ALIAS_BITREVB = 1363 +MIPS_INS_ALIAS_BITREVH = 1364 +MIPS_INS_ALIAS_BYTEREVH = 1365 +MIPS_INS_ALIAS_NOT = 1366 +MIPS_INS_ALIAS_RESTORE_JRC = 1367 +MIPS_INS_ALIAS_RESTORE = 1368 +MIPS_INS_ALIAS_SAVE = 1369 +MIPS_INS_ALIAS_MOVE = 1370 +MIPS_INS_ALIAS_BAL = 1371 +MIPS_INS_ALIAS_JALR_HB = 1372 +MIPS_INS_ALIAS_NEG = 1373 +MIPS_INS_ALIAS_NEGU = 1374 +MIPS_INS_ALIAS_NOP = 1375 +MIPS_INS_ALIAS_BNEZL = 1376 +MIPS_INS_ALIAS_BEQZL = 1377 +MIPS_INS_ALIAS_SYSCALL = 1378 +MIPS_INS_ALIAS_BREAK = 1379 +MIPS_INS_ALIAS_EI = 1380 +MIPS_INS_ALIAS_DI = 1381 +MIPS_INS_ALIAS_TEQ = 1382 +MIPS_INS_ALIAS_TGE = 1383 +MIPS_INS_ALIAS_TGEU = 1384 +MIPS_INS_ALIAS_TLT = 1385 +MIPS_INS_ALIAS_TLTU = 1386 +MIPS_INS_ALIAS_TNE = 1387 +MIPS_INS_ALIAS_RDHWR = 1388 +MIPS_INS_ALIAS_SDBBP = 1389 +MIPS_INS_ALIAS_SYNC = 1390 +MIPS_INS_ALIAS_HYPCALL = 1391 +MIPS_INS_ALIAS_NOR = 1392 +MIPS_INS_ALIAS_C_F_S = 1393 +MIPS_INS_ALIAS_C_UN_S = 1394 +MIPS_INS_ALIAS_C_EQ_S = 1395 +MIPS_INS_ALIAS_C_UEQ_S = 1396 +MIPS_INS_ALIAS_C_OLT_S = 1397 +MIPS_INS_ALIAS_C_ULT_S = 1398 +MIPS_INS_ALIAS_C_OLE_S = 1399 +MIPS_INS_ALIAS_C_ULE_S = 1400 +MIPS_INS_ALIAS_C_SF_S = 1401 +MIPS_INS_ALIAS_C_NGLE_S = 1402 +MIPS_INS_ALIAS_C_SEQ_S = 1403 +MIPS_INS_ALIAS_C_NGL_S = 1404 +MIPS_INS_ALIAS_C_LT_S = 1405 +MIPS_INS_ALIAS_C_NGE_S = 1406 +MIPS_INS_ALIAS_C_LE_S = 1407 +MIPS_INS_ALIAS_C_NGT_S = 1408 +MIPS_INS_ALIAS_BC1T = 1409 +MIPS_INS_ALIAS_BC1F = 1410 +MIPS_INS_ALIAS_C_F_D = 1411 +MIPS_INS_ALIAS_C_UN_D = 1412 +MIPS_INS_ALIAS_C_EQ_D = 1413 +MIPS_INS_ALIAS_C_UEQ_D = 1414 +MIPS_INS_ALIAS_C_OLT_D = 1415 +MIPS_INS_ALIAS_C_ULT_D = 1416 +MIPS_INS_ALIAS_C_OLE_D = 1417 +MIPS_INS_ALIAS_C_ULE_D = 1418 +MIPS_INS_ALIAS_C_SF_D = 1419 +MIPS_INS_ALIAS_C_NGLE_D = 1420 +MIPS_INS_ALIAS_C_SEQ_D = 1421 +MIPS_INS_ALIAS_C_NGL_D = 1422 +MIPS_INS_ALIAS_C_LT_D = 1423 +MIPS_INS_ALIAS_C_NGE_D = 1424 +MIPS_INS_ALIAS_C_LE_D = 1425 +MIPS_INS_ALIAS_C_NGT_D = 1426 +MIPS_INS_ALIAS_BC1TL = 1427 +MIPS_INS_ALIAS_BC1FL = 1428 +MIPS_INS_ALIAS_DNEG = 1429 +MIPS_INS_ALIAS_DNEGU = 1430 +MIPS_INS_ALIAS_SLT = 1431 +MIPS_INS_ALIAS_SLTU = 1432 +MIPS_INS_ALIAS_SIGRIE = 1433 +MIPS_INS_ALIAS_JR = 1434 +MIPS_INS_ALIAS_JRC = 1435 +MIPS_INS_ALIAS_JALRC = 1436 +MIPS_INS_ALIAS_DIV = 1437 +MIPS_INS_ALIAS_DIVU = 1438 +MIPS_INS_ALIAS_LAPC = 1439 +MIPS_INS_ALIAS_WRDSP = 1440 +MIPS_INS_ALIAS_WAIT = 1441 +MIPS_INS_ALIAS_SW = 1442 +MIPS_INS_ALIAS_JALRC_HB = 1443 +MIPS_INS_ALIAS_ADDIU_B = 1444 +MIPS_INS_ALIAS_ADDIU_W = 1445 +MIPS_INS_ALIAS_JRC_HB = 1446 +MIPS_INS_ALIAS_BEQC = 1447 +MIPS_INS_ALIAS_BNEC = 1448 +MIPS_INS_ALIAS_BEQZC = 1449 +MIPS_INS_ALIAS_BNEZC = 1450 +MIPS_INS_ALIAS_MFC0 = 1451 +MIPS_INS_ALIAS_MFHC0 = 1452 +MIPS_INS_ALIAS_MTC0 = 1453 +MIPS_INS_ALIAS_MTHC0 = 1454 +MIPS_INS_ALIAS_DMT = 1455 +MIPS_INS_ALIAS_EMT = 1456 +MIPS_INS_ALIAS_DVPE = 1457 +MIPS_INS_ALIAS_EVPE = 1458 +MIPS_INS_ALIAS_YIELD = 1459 +MIPS_INS_ALIAS_MFTC0 = 1460 +MIPS_INS_ALIAS_MFTLO = 1461 +MIPS_INS_ALIAS_MFTHI = 1462 +MIPS_INS_ALIAS_MFTACX = 1463 +MIPS_INS_ALIAS_MTTC0 = 1464 +MIPS_INS_ALIAS_MTTLO = 1465 +MIPS_INS_ALIAS_MTTHI = 1466 +MIPS_INS_ALIAS_MTTACX = 1467 +MIPS_INS_ALIAS_END = 1468 MIPS_GRP_INVALID = 0 MIPS_GRP_JUMP = 1 @@ -826,37 +2121,60 @@ MIPS_GRP_INT = 4 MIPS_GRP_IRET = 5 MIPS_GRP_PRIVILEGE = 6 MIPS_GRP_BRANCH_RELATIVE = 7 -MIPS_GRP_BITCOUNT = 128 -MIPS_GRP_DSP = 129 -MIPS_GRP_DSPR2 = 130 -MIPS_GRP_FPIDX = 131 -MIPS_GRP_MSA = 132 -MIPS_GRP_MIPS32R2 = 133 -MIPS_GRP_MIPS64 = 134 -MIPS_GRP_MIPS64R2 = 135 -MIPS_GRP_SEINREG = 136 -MIPS_GRP_STDENC = 137 -MIPS_GRP_SWAP = 138 -MIPS_GRP_MICROMIPS = 139 -MIPS_GRP_MIPS16MODE = 140 -MIPS_GRP_FP64BIT = 141 -MIPS_GRP_NONANSFPMATH = 142 -MIPS_GRP_NOTFP64BIT = 143 -MIPS_GRP_NOTINMICROMIPS = 144 -MIPS_GRP_NOTNACL = 145 -MIPS_GRP_NOTMIPS32R6 = 146 -MIPS_GRP_NOTMIPS64R6 = 147 -MIPS_GRP_CNMIPS = 148 -MIPS_GRP_MIPS32 = 149 -MIPS_GRP_MIPS32R6 = 150 -MIPS_GRP_MIPS64R6 = 151 -MIPS_GRP_MIPS2 = 152 -MIPS_GRP_MIPS3 = 153 -MIPS_GRP_MIPS3_32 = 154 -MIPS_GRP_MIPS3_32R2 = 155 -MIPS_GRP_MIPS4_32 = 156 -MIPS_GRP_MIPS4_32R2 = 157 -MIPS_GRP_MIPS5_32R2 = 158 -MIPS_GRP_GP32BIT = 159 -MIPS_GRP_GP64BIT = 160 -MIPS_GRP_ENDING = 161 +MIPS_FEATURE_HASMIPS2 = 128 +MIPS_FEATURE_HASMIPS3_32 = 129 +MIPS_FEATURE_HASMIPS3_32R2 = 130 +MIPS_FEATURE_HASMIPS3 = 131 +MIPS_FEATURE_NOTMIPS3 = 132 +MIPS_FEATURE_HASMIPS4_32 = 133 +MIPS_FEATURE_NOTMIPS4_32 = 134 +MIPS_FEATURE_HASMIPS4_32R2 = 135 +MIPS_FEATURE_HASMIPS5_32R2 = 136 +MIPS_FEATURE_HASMIPS32 = 137 +MIPS_FEATURE_HASMIPS32R2 = 138 +MIPS_FEATURE_HASMIPS32R5 = 139 +MIPS_FEATURE_HASMIPS32R6 = 140 +MIPS_FEATURE_NOTMIPS32R6 = 141 +MIPS_FEATURE_HASNANOMIPS = 142 +MIPS_FEATURE_NOTNANOMIPS = 143 +MIPS_FEATURE_ISGP64BIT = 144 +MIPS_FEATURE_ISGP32BIT = 145 +MIPS_FEATURE_ISPTR64BIT = 146 +MIPS_FEATURE_ISPTR32BIT = 147 +MIPS_FEATURE_HASMIPS64 = 148 +MIPS_FEATURE_NOTMIPS64 = 149 +MIPS_FEATURE_HASMIPS64R2 = 150 +MIPS_FEATURE_HASMIPS64R5 = 151 +MIPS_FEATURE_HASMIPS64R6 = 152 +MIPS_FEATURE_NOTMIPS64R6 = 153 +MIPS_FEATURE_INMIPS16MODE = 154 +MIPS_FEATURE_NOTINMIPS16MODE = 155 +MIPS_FEATURE_HASCNMIPS = 156 +MIPS_FEATURE_NOTCNMIPS = 157 +MIPS_FEATURE_HASCNMIPSP = 158 +MIPS_FEATURE_NOTCNMIPSP = 159 +MIPS_FEATURE_ISSYM32 = 160 +MIPS_FEATURE_ISSYM64 = 161 +MIPS_FEATURE_HASSTDENC = 162 +MIPS_FEATURE_INMICROMIPS = 163 +MIPS_FEATURE_NOTINMICROMIPS = 164 +MIPS_FEATURE_HASEVA = 165 +MIPS_FEATURE_HASMSA = 166 +MIPS_FEATURE_HASMADD4 = 167 +MIPS_FEATURE_HASMT = 168 +MIPS_FEATURE_USEINDIRECTJUMPSHAZARD = 169 +MIPS_FEATURE_NOINDIRECTJUMPGUARDS = 170 +MIPS_FEATURE_HASCRC = 171 +MIPS_FEATURE_HASVIRT = 172 +MIPS_FEATURE_HASGINV = 173 +MIPS_FEATURE_HASTLB = 174 +MIPS_FEATURE_ISFP64BIT = 175 +MIPS_FEATURE_NOTFP64BIT = 176 +MIPS_FEATURE_ISSINGLEFLOAT = 177 +MIPS_FEATURE_ISNOTSINGLEFLOAT = 178 +MIPS_FEATURE_ISNOTSOFTFLOAT = 179 +MIPS_FEATURE_HASMIPS3D = 180 +MIPS_FEATURE_HASDSP = 181 +MIPS_FEATURE_HASDSPR2 = 182 +MIPS_FEATURE_HASDSPR3 = 183 +MIPS_GRP_ENDING = 184 diff --git a/bindings/python/cstest_py/src/cstest_py/cs_modes.py b/bindings/python/cstest_py/src/cstest_py/cs_modes.py index 0290bca79..d8ef4219b 100644 --- a/bindings/python/cstest_py/src/cstest_py/cs_modes.py +++ b/bindings/python/cstest_py/src/cstest_py/cs_modes.py @@ -38,4 +38,8 @@ configs = { "type": cs.CS_OPT_SYNTAX, "val": cs.CS_OPT_SYNTAX_PERCENT, }, + "CS_OPT_SYNTAX_NO_DOLLAR": { + "type": cs.CS_OPT_SYNTAX, + "val": cs.CS_OPT_SYNTAX_NO_DOLLAR, + }, } diff --git a/cs.c b/cs.c index 4bb739a40..755b982cd 100644 --- a/cs.c +++ b/cs.c @@ -100,8 +100,33 @@ typedef struct cs_arch_config { { \ Mips_global_init, \ Mips_option, \ - ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_MICRO \ - | CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN | CS_MODE_MIPS2 | CS_MODE_MIPS3), \ + ~(CS_MODE_LITTLE_ENDIAN | \ + CS_MODE_BIG_ENDIAN | \ + CS_MODE_MIPS16 | \ + CS_MODE_MIPS32 | \ + CS_MODE_MIPS64 | \ + CS_MODE_MICRO | \ + CS_MODE_MIPS1 | \ + CS_MODE_MIPS2 | \ + CS_MODE_MIPS32R2 | \ + CS_MODE_MIPS32R3 | \ + CS_MODE_MIPS32R5 | \ + CS_MODE_MIPS32R6 | \ + CS_MODE_MIPS3 | \ + CS_MODE_MIPS4 | \ + CS_MODE_MIPS5 | \ + CS_MODE_MIPS64R2 | \ + CS_MODE_MIPS64R3 | \ + CS_MODE_MIPS64R5 | \ + CS_MODE_MIPS64R6 | \ + CS_MODE_OCTEON | \ + CS_MODE_OCTEONP | \ + CS_MODE_NANOMIPS | \ + CS_MODE_NMS1 | \ + CS_MODE_I7200 | \ + CS_MODE_MIPS_NOFLOAT | \ + CS_MODE_MIPS_PTR64 \ + ), \ } #define CS_ARCH_CONFIG_X86 \ { \ diff --git a/cstool/cstool.c b/cstool/cstool.c index 4951a237c..2dba612f3 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -9,121 +9,210 @@ #include #include "cstool.h" +#ifdef CAPSTONE_AARCH64_COMPAT_HEADER +#define CS_ARCH_AARCH64 CS_ARCH_ARM +#endif + void print_string_hex(const char *comment, unsigned char *str, size_t len); static struct { const char *name; + const char *desc; + cs_arch archs[CS_ARCH_MAX]; + cs_opt_value opt; + cs_mode mode; +} all_opts[] = { + // cs_opt_value only + { "+att", "ATT syntax", { + CS_ARCH_X86, CS_ARCH_MAX }, CS_OPT_SYNTAX_ATT, 0 }, + { "+intel", "Intel syntax", { + CS_ARCH_X86, CS_ARCH_MAX }, CS_OPT_SYNTAX_INTEL, 0 }, + { "+masm", "Intel MASM syntax", { + CS_ARCH_X86, CS_ARCH_MAX }, CS_OPT_SYNTAX_MASM, 0 }, + { "+noregname", "Number only registers", { + CS_ARCH_AARCH64, CS_ARCH_ARM, CS_ARCH_LOONGARCH, + CS_ARCH_MIPS, CS_ARCH_PPC, CS_ARCH_MAX }, + CS_OPT_SYNTAX_NOREGNAME, 0 }, + { "+moto", "Use $ as hex prefix", { + CS_ARCH_MOS65XX, CS_ARCH_MAX }, CS_OPT_SYNTAX_MOTOROLA, 0 }, + { "+regalias", "Use register aliases, like r9 > sb", { + CS_ARCH_ARM, CS_ARCH_AARCH64, CS_ARCH_MAX }, + CS_OPT_SYNTAX_CS_REG_ALIAS, 0 }, + { "+percentage", "Adds % in front of the registers", { + CS_ARCH_PPC, CS_ARCH_MAX }, CS_OPT_SYNTAX_PERCENT, 0 }, + { "+nodollar", "Removes $ in front of the registers", { + CS_ARCH_MIPS, CS_ARCH_MAX }, CS_OPT_SYNTAX_NO_DOLLAR, 0 }, + // cs_mode only + { "+nofloat", "Disables floating point support", { + CS_ARCH_MIPS, CS_ARCH_MAX }, 0, CS_MODE_MIPS_NOFLOAT }, + { "+ptr64", "Enables 64-bit pointers support", { + CS_ARCH_MIPS, CS_ARCH_MAX }, 0, CS_MODE_MIPS_PTR64 }, + { NULL } +}; + +static struct { + const char *name; + const char *desc; cs_arch arch; cs_mode mode; } all_archs[] = { - { "arm", CS_ARCH_ARM, CS_MODE_ARM }, - { "armb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN }, - { "armbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN }, - { "arml", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN }, - { "armle", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN }, - { "armv8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 }, - { "thumbv8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 }, - { "armv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 | CS_MODE_BIG_ENDIAN }, - { "thumbv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_BIG_ENDIAN }, - { "cortexm", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS }, - { "cortexv8m", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS | CS_MODE_V8 }, - { "thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB }, - { "thumbbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN }, - { "thumble", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN }, - { "aarch64", CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN }, - { "aarch64be", CS_ARCH_AARCH64, CS_MODE_BIG_ENDIAN }, - { "mips", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_LITTLE_ENDIAN }, - { "mipsmicro", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_MICRO }, - { "mipsbemicro", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_MICRO | CS_MODE_BIG_ENDIAN }, - { "mipsbe32r6", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN}, - { "mipsbe32r6micro", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN | CS_MODE_MICRO }, - { "mips32r6", CS_ARCH_MIPS, CS_MODE_MIPS32R6 }, - { "mips32r6micro", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_MICRO }, - { "mipsbe", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN }, - { "mips64", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN }, - { "mips64be", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN }, - { "x16", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 - { "x16att", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 , CS_OPT_SYNTAX_ATT - { "x32", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32 - { "x32att", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32, CS_OPT_SYNTAX_ATT - { "x64", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64 - { "x64att", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64, CS_OPT_SYNTAX_ATT - { "ppc32", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_LITTLE_ENDIAN }, - { "ppc32be", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN }, - { "ppc32qpx", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN }, - { "ppc32beqpx", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN }, - { "ppc32ps", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_LITTLE_ENDIAN }, - { "ppc32beps", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_BIG_ENDIAN }, - { "ppc64", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_LITTLE_ENDIAN }, - { "ppc64be", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN }, - { "ppc64qpx", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN }, - { "ppc64beqpx", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN }, - { "sparc", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN }, - { "sparcv9", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN | CS_MODE_V9 }, - { "systemz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, - { "sysz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, - { "s390x", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, - { "xcore", CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN }, - { "m68k", CS_ARCH_M68K, CS_MODE_BIG_ENDIAN }, - { "m68k40", CS_ARCH_M68K, CS_MODE_M68K_040 }, - { "tms320c64x", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN }, - { "m6800", CS_ARCH_M680X, CS_MODE_M680X_6800 }, - { "m6801", CS_ARCH_M680X, CS_MODE_M680X_6801 }, - { "m6805", CS_ARCH_M680X, CS_MODE_M680X_6805 }, - { "m6808", CS_ARCH_M680X, CS_MODE_M680X_6808 }, - { "m6809", CS_ARCH_M680X, CS_MODE_M680X_6809 }, - { "m6811", CS_ARCH_M680X, CS_MODE_M680X_6811 }, - { "cpu12", CS_ARCH_M680X, CS_MODE_M680X_CPU12 }, - { "hd6301", CS_ARCH_M680X, CS_MODE_M680X_6301 }, - { "hd6309", CS_ARCH_M680X, CS_MODE_M680X_6309 }, - { "hcs08", CS_ARCH_M680X, CS_MODE_M680X_HCS08 }, - { "evm", CS_ARCH_EVM, 0 }, - { "wasm", CS_ARCH_WASM, 0 }, - { "bpf", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC }, - { "bpfbe", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC }, - { "ebpf", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED }, - { "ebpfbe", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED }, - { "riscv32", CS_ARCH_RISCV, CS_MODE_RISCV32 | CS_MODE_RISCVC }, - { "riscv64", CS_ARCH_RISCV, CS_MODE_RISCV64 | CS_MODE_RISCVC }, - { "6502", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_6502 }, - { "65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65C02 }, - { "w65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_W65C02 }, - { "65816", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65816_LONG_MX }, - { "sh", CS_ARCH_SH, CS_MODE_BIG_ENDIAN }, - { "sh2", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_BIG_ENDIAN}, - { "sh2e", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN}, - { "sh-dsp", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHDSP | CS_MODE_BIG_ENDIAN}, - { "sh2a", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_BIG_ENDIAN}, - { "sh2a-fpu", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN}, - { "sh3", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 }, - { "sh3be", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 }, - { "sh3e", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU}, - { "sh3ebe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU}, - { "sh3-dsp", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP }, - { "sh3-dspbe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP }, - { "sh4", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU }, - { "sh4be", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU }, - { "sh4a", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU }, - { "sh4abe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU }, - { "sh4al-dsp", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU }, - { "sh4al-dspbe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU }, - { "tc110", CS_ARCH_TRICORE, CS_MODE_TRICORE_110 }, - { "tc120", CS_ARCH_TRICORE, CS_MODE_TRICORE_120 }, - { "tc130", CS_ARCH_TRICORE, CS_MODE_TRICORE_130 }, - { "tc131", CS_ARCH_TRICORE, CS_MODE_TRICORE_131 }, - { "tc160", CS_ARCH_TRICORE, CS_MODE_TRICORE_160 }, - { "tc161", CS_ARCH_TRICORE, CS_MODE_TRICORE_161 }, - { "tc162", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 }, - { "alpha", CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN }, - { "alphabe", CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN }, - { "hppa11", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_LITTLE_ENDIAN }, - { "hppa11be", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_BIG_ENDIAN }, - { "hppa20", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_LITTLE_ENDIAN }, - { "hppa20be", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_BIG_ENDIAN }, - { "hppa20w", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_LITTLE_ENDIAN }, - { "hppa20wbe", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_BIG_ENDIAN }, - { "loongarch32", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32 }, - { "loongarch64", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64 }, + { "arm", "ARM, little endian", CS_ARCH_ARM, CS_MODE_ARM }, + { "armle", "ARM, little endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN }, + { "armbe", "ARM, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN }, + { "armv8", "ARM v8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 }, + { "armv8be", "ARM v8, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 | CS_MODE_BIG_ENDIAN }, + { "cortexm", "ARM Cortex-M Thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS }, + { "cortexmv8", "ARM Cortex-M Thumb, v8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS | CS_MODE_V8 }, + { "thumb", "ARM Thumb mode, little endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB }, + { "thumble", "ARM Thumb mode, little endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN }, + { "thumbbe", "ARM Thumb mode, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN }, + { "thumbv8", "ARM Thumb v8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 }, + { "thumbv8be", "ARM Thumb v8, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_BIG_ENDIAN }, + + { "aarch64", "AArch64", CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN }, + { "aarch64be", "AArch64, big endian", CS_ARCH_AARCH64, CS_MODE_BIG_ENDIAN }, + + { "alpha", "Alpha, little endian", CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN }, + { "alphabe", "Alpha, big endian", CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN }, + + { "hppa11", "HPPA V1.1, little endian", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_LITTLE_ENDIAN }, + { "hppa11be", "HPPA V1.1, big endian", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_BIG_ENDIAN }, + { "hppa20", "HPPA V2.0, little endian", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_LITTLE_ENDIAN }, + { "hppa20be", "HPPA V2.0, big endian", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_BIG_ENDIAN }, + { "hppa20w", "HPPA V2.0 wide, little endian", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_LITTLE_ENDIAN }, + { "hppa20wbe", "HPPA V2.0 wide, big endian", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_BIG_ENDIAN }, + + { "mipsel16", "Mips 16-bit (generic), little endian", CS_ARCH_MIPS, CS_MODE_MIPS16 }, + { "mips16", "Mips 16-bit (generic)", CS_ARCH_MIPS, CS_MODE_MIPS16 | CS_MODE_BIG_ENDIAN }, + { "mipsel", "Mips 32-bit (generic), little endian", CS_ARCH_MIPS, CS_MODE_MIPS32 }, + { "mips", "Mips 32-bit (generic)", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN }, + { "mipsel64", "Mips 64-bit (generic), little endian", CS_ARCH_MIPS, CS_MODE_MIPS64 }, + { "mips64", "Mips 64-bit (generic)", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN }, + { "micromipsel", "MicroMips, little endian", CS_ARCH_MIPS, CS_MODE_MICRO }, + { "micromips", "MicroMips", CS_ARCH_MIPS, CS_MODE_MICRO | CS_MODE_BIG_ENDIAN }, + { "micromipselr3", "MicroMips32r3, little endian", CS_ARCH_MIPS, CS_MODE_MICRO32R3 }, + { "micromipsr3", "MicroMips32r3", CS_ARCH_MIPS, CS_MODE_MICRO32R3 | CS_MODE_BIG_ENDIAN }, + { "micromipselr6", "MicroMips32r6, little endian", CS_ARCH_MIPS, CS_MODE_MICRO32R6 }, + { "micromipsr6", "MicroMips32r6", CS_ARCH_MIPS, CS_MODE_MICRO32R6 | CS_MODE_BIG_ENDIAN }, + { "mipsel1", "Mips I ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS1 }, + { "mips1", "Mips I ISA", CS_ARCH_MIPS, CS_MODE_MIPS1 | CS_MODE_BIG_ENDIAN }, + { "mipsel2", "Mips II ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS2 }, + { "mips2", "Mips II ISA", CS_ARCH_MIPS, CS_MODE_MIPS2 | CS_MODE_BIG_ENDIAN }, + { "mipsel32r2", "Mips32 r2 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS32R2 }, + { "mips32r2", "Mips32 r2 ISA", CS_ARCH_MIPS, CS_MODE_MIPS32R2 | CS_MODE_BIG_ENDIAN }, + { "mipsel32r3", "Mips32 r3 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS32R3 }, + { "mips32r3", "Mips32 r3 ISA", CS_ARCH_MIPS, CS_MODE_MIPS32R3 | CS_MODE_BIG_ENDIAN }, + { "mipsel32r5", "Mips32 r5 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS32R5 }, + { "mips32r5", "Mips32 r5 ISA", CS_ARCH_MIPS, CS_MODE_MIPS32R5 | CS_MODE_BIG_ENDIAN }, + { "mipsel32r6", "Mips32 r6 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS32R6 }, + { "mips32r6", "Mips32 r6 ISA", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN }, + { "mipsel3", "Mips III ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS3 }, + { "mips3", "Mips III ISA", CS_ARCH_MIPS, CS_MODE_MIPS3 | CS_MODE_BIG_ENDIAN }, + { "mipsel4", "Mips IV ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS4 }, + { "mips4", "Mips IV ISA", CS_ARCH_MIPS, CS_MODE_MIPS4 | CS_MODE_BIG_ENDIAN }, + { "mipsel5", "Mips V ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS5 }, + { "mips5", "Mips V ISA", CS_ARCH_MIPS, CS_MODE_MIPS5 | CS_MODE_BIG_ENDIAN }, + { "mipsel64r2", "Mips64 r2 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS64R2 }, + { "mips64r2", "Mips64 r2 ISA", CS_ARCH_MIPS, CS_MODE_MIPS64R2 | CS_MODE_BIG_ENDIAN }, + { "mipsel64r3", "Mips64 r3 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS64R3 }, + { "mips64r3", "Mips64 r3 ISA", CS_ARCH_MIPS, CS_MODE_MIPS64R3 | CS_MODE_BIG_ENDIAN }, + { "mipsel64r5", "Mips64 r5 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS64R5 }, + { "mips64r5", "Mips64 r5 ISA", CS_ARCH_MIPS, CS_MODE_MIPS64R5 | CS_MODE_BIG_ENDIAN }, + { "mipsel64r6", "Mips64 r6 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS64R6 }, + { "mips64r6", "Mips64 r6 ISA", CS_ARCH_MIPS, CS_MODE_MIPS64R6 | CS_MODE_BIG_ENDIAN }, + { "octeonle", "Octeon cnMIPS, little endian", CS_ARCH_MIPS, CS_MODE_OCTEON }, + { "octeon", "Octeon cnMIPS", CS_ARCH_MIPS, CS_MODE_OCTEON | CS_MODE_BIG_ENDIAN }, + { "octeonple", "Octeon+ cnMIPS, little endian", CS_ARCH_MIPS, CS_MODE_OCTEONP }, + { "octeonp", "Octeon+ cnMIPS", CS_ARCH_MIPS, CS_MODE_OCTEONP | CS_MODE_BIG_ENDIAN }, + { "nanomips", "nanoMIPS", CS_ARCH_MIPS, CS_MODE_NANOMIPS }, + { "nms1", "nanoMIPS Subset", CS_ARCH_MIPS, CS_MODE_NMS1 }, + { "i7200", "nanoMIPS i7200", CS_ARCH_MIPS, CS_MODE_I7200 }, + + { "x16", "x86 16-bit mode", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 + { "x32", "x86 32-bit mode", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32 + { "x64", "x86 64-bit mode", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64 + + { "ppc32", "PowerPC 32-bit, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_LITTLE_ENDIAN }, + { "ppc32be", "PowerPC 32-bit, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN }, + { "ppc32qpx", "PowerPC 32-bit, qpx, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN }, + { "ppc32beqpx", "PowerPC 32-bit, qpx, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN }, + { "ppc32ps", "PowerPC 32-bit, ps, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_LITTLE_ENDIAN }, + { "ppc32beps", "PowerPC 32-bit, ps, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_BIG_ENDIAN }, + { "ppc64", "PowerPC 64-bit, little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_LITTLE_ENDIAN }, + { "ppc64be", "PowerPC 64-bit, big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN }, + { "ppc64qpx", "PowerPC 64-bit, qpx, little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN }, + { "ppc64beqpx", "PowerPC 64-bit, qpx, big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN }, + + { "sparc", "Sparc, big endian", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN }, + { "sparcv9", "Sparc v9, big endian", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN | CS_MODE_V9 }, + + { "systemz", "SystemZ, big endian", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, + { "s390x", "SystemZ s390x, big endian", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, + + { "xcore", "xcore, big endian", CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN }, + + { "m68k", "m68k + big endian", CS_ARCH_M68K, CS_MODE_BIG_ENDIAN }, + { "m68k40", "m68k40", CS_ARCH_M68K, CS_MODE_M68K_040 }, + + { "tms320c64x", "tms320c64x, big endian", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN }, + + { "m6800", "m680x, M6800/2", CS_ARCH_M680X, CS_MODE_M680X_6800 }, + { "m6801", "m680x, M6801/3", CS_ARCH_M680X, CS_MODE_M680X_6801 }, + { "m6805", "m680x, M6805", CS_ARCH_M680X, CS_MODE_M680X_6805 }, + { "m6808", "m680x, M68HC08", CS_ARCH_M680X, CS_MODE_M680X_6808 }, + { "m6809", "m680x, M6809", CS_ARCH_M680X, CS_MODE_M680X_6809 }, + { "m6811", "m680x, M68HC11", CS_ARCH_M680X, CS_MODE_M680X_6811 }, + { "cpu12", "m680x, M68HC12/HCS12", CS_ARCH_M680X, CS_MODE_M680X_CPU12 }, + { "hd6301", "m680x, HD6301/3", CS_ARCH_M680X, CS_MODE_M680X_6301 }, + { "hd6309", "m680x, HD6309", CS_ARCH_M680X, CS_MODE_M680X_6309 }, + { "hcs08", "m680x, HCS08", CS_ARCH_M680X, CS_MODE_M680X_HCS08 }, + + { "evm", "ethereum virtual machine", CS_ARCH_EVM, 0 }, + + { "wasm", "web assembly", CS_ARCH_WASM, 0 }, + + { "bpf", "Classic BPF, little endian", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC }, + { "bpfbe", "Classic BPF, big endian", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC }, + { "ebpf", "Extended BPF, little endian", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED }, + { "ebpfbe", "Extended BPF, big endian", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED }, + + { "riscv32", "Risc-V 32-bit, little endian", CS_ARCH_RISCV, CS_MODE_RISCV32 | CS_MODE_RISCVC }, + { "riscv64", "Risc-V 64-bit, little endian", CS_ARCH_RISCV, CS_MODE_RISCV64 | CS_MODE_RISCVC }, + + { "6502", "MOS 6502", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_6502 }, + { "65c02", "WDC 65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65C02 }, + { "w65c02", "WDC w65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_W65C02 }, + { "65816", "WDC 65816 (long m/x)", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65816_LONG_MX }, + + { "sh", "SuperH SH1", CS_ARCH_SH, CS_MODE_BIG_ENDIAN }, + { "sh2", "SuperH SH2", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_BIG_ENDIAN}, + { "sh2e", "SuperH SH2E", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN}, + { "sh-dsp", "SuperH SH2-DSP", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHDSP | CS_MODE_BIG_ENDIAN}, + { "sh2a", "SuperH SH2A", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_BIG_ENDIAN}, + { "sh2a-fpu", "SuperH SH2A-FPU", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN}, + { "sh3", "SuperH SH3", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 }, + { "sh3be", "SuperH SH3, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 }, + { "sh3e", "SuperH SH3E", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU}, + { "sh3ebe", "SuperH SH3E, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU}, + { "sh3-dsp", "SuperH SH3-DSP", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP }, + { "sh3-dspbe", "SuperH SH3-DSP, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP }, + { "sh4", "SuperH SH4", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU }, + { "sh4be", "SuperH SH4, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU }, + { "sh4a", "SuperH SH4A", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU }, + { "sh4abe", "SuperH SH4A, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU }, + { "sh4al-dsp", "SuperH SH4AL-DSP", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU }, + { "sh4al-dspbe", "SuperH SH4AL-DSP, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU }, + + { "tc110", "Tricore V1.1", CS_ARCH_TRICORE, CS_MODE_TRICORE_110 }, + { "tc120", "Tricore V1.2", CS_ARCH_TRICORE, CS_MODE_TRICORE_120 }, + { "tc130", "Tricore V1.3", CS_ARCH_TRICORE, CS_MODE_TRICORE_130 }, + { "tc131", "Tricore V1.3.1", CS_ARCH_TRICORE, CS_MODE_TRICORE_131 }, + { "tc160", "Tricore V1.6", CS_ARCH_TRICORE, CS_MODE_TRICORE_160 }, + { "tc161", "Tricore V1.6.1", CS_ARCH_TRICORE, CS_MODE_TRICORE_161 }, + { "tc162", "Tricore V1.6.2", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 }, + + { "loongarch32", "LoongArch 32-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32 }, + { "loongarch64", "LoongArch 64-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64 }, { NULL } }; @@ -185,168 +274,63 @@ static uint8_t *preprocess(char *code, size_t *size) return result; } +static const char *get_arch_name(cs_arch arch) +{ + switch(arch) { + case CS_ARCH_ARM: return "ARM"; + case CS_ARCH_AARCH64: return "Arm64"; + case CS_ARCH_MIPS: return "Mips"; + case CS_ARCH_X86: return "x86"; + case CS_ARCH_PPC: return "PowerPC"; + case CS_ARCH_SPARC: return "Sparc"; + case CS_ARCH_SYSZ: return "SysZ"; + case CS_ARCH_XCORE: return "Xcore"; + case CS_ARCH_M68K: return "M68K"; + case CS_ARCH_TMS320C64X: return "TMS320C64X"; + case CS_ARCH_M680X: return "M680X"; + case CS_ARCH_EVM: return "Evm"; + case CS_ARCH_MOS65XX: return "MOS65XX"; + case CS_ARCH_WASM: return "Wasm"; + case CS_ARCH_BPF: return "BPF"; + case CS_ARCH_RISCV: return "RiscV"; + case CS_ARCH_SH: return "SH"; + case CS_ARCH_TRICORE: return "TriCore"; + case CS_ARCH_ALPHA: return "Alpha"; + case CS_ARCH_HPPA: return "HPPA"; + case CS_ARCH_LOONGARCH: return "LoongArch"; + default: return NULL; + } +} + static void usage(char *prog) { + int i, j; printf("Cstool for Capstone Disassembler Engine v%u.%u.%u\n\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA); - printf("Syntax: %s [-d|-a|-r|-s|-u|-v] [start-address-in-hex-format]\n", prog); - printf("\nThe following options are supported:\n"); + printf("Syntax: %s [-d|-a|-r|-s|-u|-v] [start-address-in-hex-format]\n", prog); + printf("\nThe following options are supported:\n"); - if (cs_support(CS_ARCH_X86)) { - printf(" x16 16-bit mode (X86)\n"); - printf(" x32 32-bit mode (X86)\n"); - printf(" x64 64-bit mode (X86)\n"); - printf(" x16att 16-bit mode (X86), syntax AT&T\n"); - printf(" x32att 32-bit mode (X86), syntax AT&T\n"); - printf(" x64att 64-bit mode (X86), syntax AT&T\n"); + for (i = 0; all_archs[i].name; i++) { + if (cs_support(all_archs[i].arch)) { + printf(" %-16s %s\n", all_archs[i].name, all_archs[i].desc); + } } - if (cs_support(CS_ARCH_ARM)) { - printf(" arm arm\n"); - printf(" armbe arm + big endian\n"); - printf(" thumb thumb mode\n"); - printf(" thumbbe thumb + big endian\n"); - printf(" cortexm thumb + cortex-m extensions\n"); - printf(" cortexv8m thumb + cortex-m extensions + v8\n"); - printf(" armv8 arm v8\n"); - printf(" thumbv8 thumb v8\n"); - printf(" armv8be arm v8 + big endian\n"); - printf(" thumbv8be thumb v8 + big endian\n"); - } - - if (cs_support(CS_ARCH_AARCH64)) { - printf(" aarch64 aarch64 mode\n"); - printf(" aarch64be aarch64 + big endian\n"); - } - - if (cs_support(CS_ARCH_ALPHA)) { - printf(" alpha alpha + little endian\n"); - printf(" alphabe alpha + big endian\n"); - } - - if (cs_support(CS_ARCH_HPPA)) { - printf(" hppa11 hppa V1.1 + little endian\n"); - printf(" hppa11be hppa V1.1 + big endian\n"); - printf(" hppa20 hppa V2.0 + little endian\n"); - printf(" hppa20be hppa V2.0 + big endian\n"); - printf(" hppa20w hppa V2.0 wide + little endian\n"); - printf(" hppa20wbe hppa V2.0 wide + big endian\n"); - } - - if (cs_support(CS_ARCH_MIPS)) { - printf(" mips mips32 + little endian\n"); - printf(" mipsbe mips32 + big endian\n"); - printf(" mips64 mips64 + little endian\n"); - printf(" mips64be mips64 + big endian\n"); - } - - if (cs_support(CS_ARCH_PPC)) { - printf(" ppc32 ppc32 + little endian\n"); - printf(" ppc32be ppc32 + big endian\n"); - printf(" ppc32qpx ppc32 + qpx + little endian\n"); - printf(" ppc32beqpx ppc32 + qpx + big endian\n"); - printf(" ppc32ps ppc32 + ps + little endian\n"); - printf(" ppc32beps ppc32 + ps + big endian\n"); - printf(" ppc64 ppc64 + little endian\n"); - printf(" ppc64be ppc64 + big endian\n"); - printf(" ppc64qpx ppc64 + qpx + little endian\n"); - printf(" ppc64beqpx ppc64 + qpx + big endian\n"); - } - - if (cs_support(CS_ARCH_SPARC)) { - printf(" sparc sparc\n"); - } - - if (cs_support(CS_ARCH_SYSZ)) { - printf(" systemz systemz (s390x)\n"); - } - - if (cs_support(CS_ARCH_XCORE)) { - printf(" xcore xcore\n"); - } - - if (cs_support(CS_ARCH_M68K)) { - printf(" m68k m68k + big endian\n"); - printf(" m68k40 m68k_040\n"); - } - - if (cs_support(CS_ARCH_TMS320C64X)) { - printf(" tms320c64x TMS320C64x\n"); - } - - if (cs_support(CS_ARCH_M680X)) { - printf(" m6800 M6800/2\n"); - printf(" m6801 M6801/3\n"); - printf(" m6805 M6805\n"); - printf(" m6808 M68HC08\n"); - printf(" m6809 M6809\n"); - printf(" m6811 M68HC11\n"); - printf(" cpu12 M68HC12/HCS12\n"); - printf(" hd6301 HD6301/3\n"); - printf(" hd6309 HD6309\n"); - printf(" hcs08 HCS08\n"); - } - - if (cs_support(CS_ARCH_EVM)) { - printf(" evm Ethereum Virtual Machine\n"); - } - - if (cs_support(CS_ARCH_MOS65XX)) { - printf(" 6502 MOS 6502\n"); - printf(" 65c02 WDC 65c02\n"); - printf(" w65c02 WDC w65c02\n"); - printf(" 65816 WDC 65816 (long m/x)\n"); - } - - if (cs_support(CS_ARCH_WASM)) { - printf(" wasm: Web Assembly\n"); - } - - if (cs_support(CS_ARCH_BPF)) { - printf(" bpf Classic BPF\n"); - printf(" bpfbe Classic BPF + big endian\n"); - printf(" ebpf Extended BPF\n"); - printf(" ebpfbe Extended BPF + big endian\n"); - } - - if (cs_support(CS_ARCH_RISCV)) { - printf(" riscv32 riscv32\n"); - printf(" riscv64 riscv64\n"); - } - - if (cs_support(CS_ARCH_SH)) { - printf(" sh superh SH1\n"); - printf(" sh2 superh SH2\n"); - printf(" sh2e superh SH2E\n"); - printf(" sh2dsp superh SH2-DSP\n"); - printf(" sh2a superh SH2A\n"); - printf(" sh2afpu superh SH2A-FPU\n"); - printf(" sh3 superh SH3\n"); - printf(" sh3be superh SH3 big endian\n"); - printf(" sh3e superh SH3E\n"); - printf(" sh3ebe superh SH3E big endian\n"); - printf(" sh3-dsp superh SH3-DSP\n"); - printf(" sh3-dspbe superh SH3-DSP big endian\n"); - printf(" sh4 superh SH4\n"); - printf(" sh4be superh SH4 big endian\n"); - printf(" sh4a superh SH4A\n"); - printf(" sh4abe superh SH4A big endian\n"); - printf(" sh4al-dsp superh SH4AL-DSP\n"); - printf(" sh4al-dspbe superh SH4AL-DSP big endian\n"); - } - - if (cs_support(CS_ARCH_TRICORE)) { - printf(" tc110 tricore V1.1\n"); - printf(" tc120 tricore V1.2\n"); - printf(" tc130 tricore V1.3\n"); - printf(" tc131 tricore V1.3.1\n"); - printf(" tc160 tricore V1.6\n"); - printf(" tc161 tricore V1.6.1\n"); - printf(" tc162 tricore V1.6.2\n"); - } - - if (cs_support(CS_ARCH_LOONGARCH)) { - printf(" loongarch32 LoongArch32\n"); - printf(" loongarch64 LoongArch64\n"); + printf("\nArch specific options:\n"); + for (i = 0; all_opts[i].name; i++) { + printf(" %-16s %s (only: ", all_opts[i].name, all_opts[i].desc); + for (j = 0; j < CS_ARCH_MAX; j++) { + cs_arch arch = all_opts[i].archs[j]; + const char *name = get_arch_name(arch); + if (!name) { + break; + } + if (j > 0) { + printf(", %s", name); + } else { + printf("%s", name); + } + } + printf(")\n"); } printf("\nExtra options:\n"); @@ -494,17 +478,55 @@ static void run_dev_fuzz(csh handle, uint8_t *bytes, uint32_t size) { } } +static cs_mode find_additional_modes(const char *input, cs_arch arch) { + if (!input) { + return 0; + } + cs_mode mode = 0; + int i, j; + for (i = 0; all_opts[i].name; i++) { + if (all_opts[i].opt || !strstr(input, all_opts[i].name)) { + continue; + } + for (j = 0; j < CS_ARCH_MAX; j++) { + if (arch == all_opts[i].archs[j]) { + mode |= all_opts[i].mode; + break; + } + } + } + return mode; +} + +static void enable_additional_options(csh handle, const char *input, cs_arch arch) { + if (!input) { + return; + } + int i, j; + for (i = 0; all_opts[i].name; i++) { + if (all_opts[i].mode || !strstr(input, all_opts[i].name)) { + continue; + } + for (j = 0; j < CS_ARCH_MAX; j++) { + if (arch == all_opts[i].archs[j]) { + cs_option(handle, CS_OPT_SYNTAX, all_opts[i].opt); + break; + } + } + } +} + int main(int argc, char **argv) { int i, c; csh handle; - char *mode; + char *choosen_arch; uint8_t *assembly; size_t count, size; uint64_t address = 0LL; cs_insn *insn; cs_err err; - cs_mode md; + cs_mode mode; cs_arch arch = CS_ARCH_ALL; bool detail_flag = false; bool unsigned_flag = false; @@ -647,7 +669,7 @@ int main(int argc, char **argv) return -1; } - mode = argv[optind]; + choosen_arch = argv[optind]; assembly = preprocess(argv[optind + 1], &size); if (!assembly) { usage(argv[0]); @@ -658,37 +680,46 @@ int main(int argc, char **argv) char *temp, *src = argv[optind + 2]; address = strtoull(src, &temp, 16); if (temp == src || *temp != '\0' || errno == ERANGE) { - printf("ERROR: invalid address argument, quit!\n"); + fprintf(stderr, "ERROR: invalid address argument, quit!\n"); return -2; } } + size_t arch_len = strlen(choosen_arch); + const char *plus = strchr(choosen_arch, '+'); + if (plus) { + arch_len = plus - choosen_arch; + } + for (i = 0; all_archs[i].name; i++) { - if (!strcmp(all_archs[i].name, mode)) { + size_t len = strlen(all_archs[i].name); + if (len == arch_len && !strncmp(all_archs[i].name, choosen_arch, arch_len)) { arch = all_archs[i].arch; - err = cs_open(all_archs[i].arch, all_archs[i].mode, &handle); + mode = all_archs[i].mode; + mode |= find_additional_modes(plus, arch); + + err = cs_open(all_archs[i].arch, mode, &handle); if (!err) { - md = all_archs[i].mode; - if (strstr (mode, "att")) { - cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT); - } + enable_additional_options(handle, plus, arch); // turn on SKIPDATA mode - if (skipdata) + if (skipdata) { cs_option(handle, CS_OPT_SKIPDATA, CS_OPT_ON); + } } break; } } if (arch == CS_ARCH_ALL) { - printf("ERROR: Invalid : \"%s\", quit!\n", mode); + fprintf(stderr, "ERROR: Invalid : \"%s\", quit!\n", choosen_arch); usage(argv[0]); return -1; } if (err) { - printf("ERROR: Failed on cs_open(), quit!\n"); + const char *error = cs_strerror(err); + fprintf(stderr, "ERROR: Failed on cs_open(): %s\n", error); usage(argv[0]); return -1; } @@ -745,14 +776,14 @@ int main(int argc, char **argv) printf(" %s\t%s\n", insn[i].mnemonic, insn[i].op_str); if (detail_flag) { - print_details(handle, arch, md, &insn[i]); + print_details(handle, arch, mode, &insn[i]); } } cs_free(insn, count); free(assembly); } else { - printf("ERROR: invalid assembly code\n"); + fprintf(stderr, "ERROR: invalid assembly code\n"); cs_close(&handle); free(assembly); return(-4); diff --git a/cstool/cstool_mips.c b/cstool/cstool_mips.c index a2d7e35a0..8b133ea69 100644 --- a/cstool/cstool_mips.c +++ b/cstool/cstool_mips.c @@ -27,9 +27,11 @@ void print_insn_detail_mips(csh handle, cs_insn *ins) break; case MIPS_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + printf("\t\toperands[%u].is_reglist: %s\n", i, op->is_reglist ? "true" : "false"); break; case MIPS_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + printf("\t\toperands[%u].is_unsigned: %s\n", i, op->is_unsigned ? "true" : "false"); break; case MIPS_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); diff --git a/docs/cs_v6_release_guide.md b/docs/cs_v6_release_guide.md index bdaf37958..ee94914cd 100644 --- a/docs/cs_v6_release_guide.md +++ b/docs/cs_v6_release_guide.md @@ -167,6 +167,53 @@ sed -i "s|detail->arm64|detail->aarch64|g" $1 Write it into `rename_arm64.sh` and run it on files with `sh rename_arm64.sh ` + +**Mips** + +| Keyword | Change | Justification | Possible revert | +|---------|--------|---------------|-----------------| +| `CS_OPT_SYNTAX_NO_DOLLAR` | Adds options which removes the `$` (dollar sign) from the register name. | New Feature | Enable option. | +| `CS_OPT_SYNTAX_NOREGNAME` | Implements the options to output raw register numbers (only the standard GPR are numeric). | Was not implemented | Enable option. | +| `cs_mips_op.uimm` | Access for the unsigned immediate value of the IMM operand. | Was missing | None. | +| `cs_mips_op.is_unsigned` | Defines if the IMM operand is signed (when false) or unsigned (when true). | Was missing | None. | +| `cs_mips_op.is_reglist` | Defines if the REG operand is part of a list of registers. | Was missing | None. | +| `cs_mips_op.access` | Defines how is this operand accessed, i.e. READ, WRITE or READ & WRITE. | Was missing | None. | + +**Note about AArch64** + +in `capstone.h` new mips ISA has been added which can be used by themselves. + +``` + CS_MODE_MIPS16 = CS_MODE_16, ///< Generic mips16 + CS_MODE_MIPS32 = CS_MODE_32, ///< Generic mips32 + CS_MODE_MIPS64 = CS_MODE_64, ///< Generic mips64 + CS_MODE_MICRO = 1 << 4, ///< microMips + CS_MODE_MIPS1 = 1 << 5, ///< Mips I ISA Support + CS_MODE_MIPS2 = 1 << 6, ///< Mips II ISA Support + CS_MODE_MIPS32R2 = 1 << 7, ///< Mips32r2 ISA Support + CS_MODE_MIPS32R3 = 1 << 8, ///< Mips32r3 ISA Support + CS_MODE_MIPS32R5 = 1 << 9, ///< Mips32r5 ISA Support + CS_MODE_MIPS32R6 = 1 << 10, ///< Mips32r6 ISA Support + CS_MODE_MIPS3 = 1 << 11, ///< MIPS III ISA Support + CS_MODE_MIPS4 = 1 << 12, ///< MIPS IV ISA Support + CS_MODE_MIPS5 = 1 << 13, ///< MIPS V ISA Support + CS_MODE_MIPS64R2 = 1 << 14, ///< Mips64r2 ISA Support + CS_MODE_MIPS64R3 = 1 << 15, ///< Mips64r3 ISA Support + CS_MODE_MIPS64R5 = 1 << 16, ///< Mips64r5 ISA Support + CS_MODE_MIPS64R6 = 1 << 17, ///< Mips64r6 ISA Support + CS_MODE_OCTEON = 1 << 18, ///< Octeon cnMIPS Support + CS_MODE_OCTEONP = 1 << 19, ///< Octeon+ cnMIPS Support + CS_MODE_NANOMIPS = 1 << 20, ///< Generic nanomips + CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS), ///< nanoMips NMS1 + CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS), ///< nanoMips I7200 + CS_MODE_MICRO32R3 = (CS_MODE_MICRO | CS_MODE_MIPS32R3), ///< microMips32r3 + CS_MODE_MICRO32R6 = (CS_MODE_MICRO | CS_MODE_MIPS32R6), ///< microMips32r6 +``` + +It is also possible to disable floating point support by adding `CS_MODE_MIPS_NOFLOAT`. + +**`CS_MODE_MIPS_PTR64` is now required to decode 64-bit pointers**, like jumps and calls (for example: `jal $t0`). + ## New features These features are only supported by `auto-sync`-enabled architectures. @@ -250,3 +297,47 @@ Nonetheless, an alias should never be **decoded** as real instruction. If you find an alias which is decoded as a real instruction, please let us know. Such an instruction is ill-defined in LLVM and should be fixed upstream. + +### Refactoring of cstool + +`cstool` has been refactored to simplify its usage; before you needed to add extra options in the C code to enable features and recompile, but now you can easily decode instructions with different syntaxes or options, by appending after the arch one of the followings values: + +``` ++att ATT syntax (only: x86) ++intel Intel syntax (only: x86) ++masm Intel MASM syntax (only: x86) ++noregname Number only registers (only: Arm64, ARM, LoongArch, Mips, PowerPC) ++moto Use $ as hex prefix (only: MOS65XX) ++regalias Use register aliases, like r9 > sb (only: ARM, Arm64) ++percentage Adds % in front of the registers (only: PowerPC) ++nodollar Removes $ in front of the registers (only: Mips) ++nofloat Disables floating point support (only: Mips) ++ptr64 Enables 64-bit pointers support (only: Mips) +``` + +For example: +``` +$ cstool -s ppc32+percentage 0c100097 + 0 0c 10 00 97 stwu %r24, 0x100c(0) +$ cstool -s ppc32 0c100097 + 0 0c 10 00 97 stwu r24, 0x100c(0) +$ cstool -s x32+att 0c1097 + 0 0c 10 orb $0x10, %al + 2 97 xchgl %eax, %edi +$ cstool -s x32+intel 0c1097 + 0 0c 10 or al, 0x10 + 2 97 xchg edi, eax +$ cstool -s x32+masm 0c1097 + 0 0c 10 or al, 10h + 2 97 xchg edi, eax +$ cstool -s arm+regalias 0c100097000000008fa2000034213456 + 0 0c 10 00 97 strls r1, [r0, -ip] + 4 00 00 00 00 andeq r0, r0, r0 + 8 8f a2 00 00 andeq sl, r0, pc, lsl #5 +10 34 21 34 56 shasxpl r2, r4, r4 +$ cstool -s arm 0c100097000000008fa2000034213456 + 0 0c 10 00 97 strls r1, [r0, -r12] + 4 00 00 00 00 andeq r0, r0, r0 + 8 8f a2 00 00 andeq r10, r0, pc, lsl #5 +10 34 21 34 56 shasxpl r2, r4, r4 +``` \ No newline at end of file diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index 7de50bfd1..6fa23162e 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -183,10 +183,6 @@ typedef enum cs_mode { CS_MODE_THUMB = 1 << 4, ///< ARM's Thumb mode, including Thumb-2 CS_MODE_MCLASS = 1 << 5, ///< ARM's Cortex-M series CS_MODE_V8 = 1 << 6, ///< ARMv8 A32 encodings for ARM - CS_MODE_MICRO = 1 << 4, ///< MicroMips mode (MIPS) - CS_MODE_MIPS3 = 1 << 5, ///< Mips III ISA - CS_MODE_MIPS32R6 = 1 << 6, ///< Mips32r6 ISA - CS_MODE_MIPS2 = 1 << 7, ///< Mips II ISA CS_MODE_V9 = 1 << 4, ///< SparcV9 mode (Sparc) CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC) CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC) @@ -198,9 +194,33 @@ typedef enum cs_mode { CS_MODE_M68K_030 = 1 << 4, ///< M68K 68030 mode CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode - CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode - CS_MODE_MIPS32 = CS_MODE_32, ///< Mips32 ISA (Mips) - CS_MODE_MIPS64 = CS_MODE_64, ///< Mips64 ISA (Mips) + CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode + CS_MODE_MIPS16 = CS_MODE_16, ///< Generic mips16 + CS_MODE_MIPS32 = CS_MODE_32, ///< Generic mips32 + CS_MODE_MIPS64 = CS_MODE_64, ///< Generic mips64 + CS_MODE_MICRO = 1 << 4, ///< microMips + CS_MODE_MIPS1 = 1 << 5, ///< Mips I ISA Support + CS_MODE_MIPS2 = 1 << 6, ///< Mips II ISA Support + CS_MODE_MIPS32R2 = 1 << 7, ///< Mips32r2 ISA Support + CS_MODE_MIPS32R3 = 1 << 8, ///< Mips32r3 ISA Support + CS_MODE_MIPS32R5 = 1 << 9, ///< Mips32r5 ISA Support + CS_MODE_MIPS32R6 = 1 << 10, ///< Mips32r6 ISA Support + CS_MODE_MIPS3 = 1 << 11, ///< MIPS III ISA Support + CS_MODE_MIPS4 = 1 << 12, ///< MIPS IV ISA Support + CS_MODE_MIPS5 = 1 << 13, ///< MIPS V ISA Support + CS_MODE_MIPS64R2 = 1 << 14, ///< Mips64r2 ISA Support + CS_MODE_MIPS64R3 = 1 << 15, ///< Mips64r3 ISA Support + CS_MODE_MIPS64R5 = 1 << 16, ///< Mips64r5 ISA Support + CS_MODE_MIPS64R6 = 1 << 17, ///< Mips64r6 ISA Support + CS_MODE_OCTEON = 1 << 18, ///< Octeon cnMIPS Support + CS_MODE_OCTEONP = 1 << 19, ///< Octeon+ cnMIPS Support + CS_MODE_NANOMIPS = 1 << 20, ///< Generic nanomips + CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS), ///< nanoMips NMS1 + CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS), ///< nanoMips I7200 + CS_MODE_MIPS_NOFLOAT = 1 << 23, ///< Disable floating points ops + CS_MODE_MIPS_PTR64 = 1 << 24, ///< Mips pointers are 64-bit + CS_MODE_MICRO32R3 = (CS_MODE_MICRO | CS_MODE_MIPS32R3), ///< microMips32r3 + CS_MODE_MICRO32R6 = (CS_MODE_MICRO | CS_MODE_MIPS32R6), ///< microMips32r6 CS_MODE_M680X_6301 = 1 << 1, ///< M680X Hitachi 6301,6303 mode CS_MODE_M680X_6309 = 1 << 2, ///< M680X Hitachi 6309 mode CS_MODE_M680X_6800 = 1 << 3, ///< M680X Motorola 6800,6802 mode @@ -210,7 +230,7 @@ typedef enum cs_mode { CS_MODE_M680X_6809 = 1 << 7, ///< M680X Motorola 6809 mode CS_MODE_M680X_6811 = 1 << 8, ///< M680X Motorola/Freescale/NXP 68HC11 mode CS_MODE_M680X_CPU12 = 1 << 9, ///< M680X Motorola/Freescale/NXP CPU12 - ///< used on M68HC12/HCS12 + ///< used on M68HC12/HCS12 CS_MODE_M680X_HCS08 = 1 << 10, ///< M680X Freescale/NXP HCS08 mode CS_MODE_BPF_CLASSIC = 0, ///< Classic BPF mode (default) CS_MODE_BPF_EXTENDED = 1 << 0, ///< Extended BPF mode @@ -299,6 +319,7 @@ typedef enum cs_opt_value { CS_OPT_SYNTAX_MOTOROLA = 1 << 6, ///< MOS65XX use $ as hex prefix CS_OPT_SYNTAX_CS_REG_ALIAS = 1 << 7, ///< Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.) CS_OPT_SYNTAX_PERCENT = 1 << 8, ///< Prints the % in front of PPC registers. + CS_OPT_SYNTAX_NO_DOLLAR = 1 << 9, ///< Does not print the $ in front of Mips registers. CS_OPT_DETAIL_REAL = 1 << 1, ///< If enabled, always sets the real instruction detail. Even if the instruction is an alias. } cs_opt_value; @@ -401,7 +422,7 @@ typedef struct cs_opt_skipdata { #define MAX_IMPL_W_REGS 47 #define MAX_IMPL_R_REGS 20 -#define MAX_NUM_GROUPS 8 +#define MAX_NUM_GROUPS 16 /// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON /// Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH)) diff --git a/include/capstone/cs_operand.h b/include/capstone/cs_operand.h index 17ec7c72e..3c3f8a9cc 100644 --- a/include/capstone/cs_operand.h +++ b/include/capstone/cs_operand.h @@ -25,8 +25,7 @@ typedef enum cs_op_type { CS_OP_RESERVED_15 = 15, CS_OP_SPECIAL = 0x10, ///< Special operands from archs CS_OP_BOUND = 0x40, ///< Operand is associated with a previous operand. Used by AArch64 for SME operands. - CS_OP_MEM = - 0x80, ///< Memory operand. Can be ORed with another operand type. + CS_OP_MEM = 0x80, ///< Memory operand. Can be ORed with another operand type. CS_OP_MEM_REG = CS_OP_MEM | CS_OP_REG, ///< Memory referencing register operand. CS_OP_MEM_IMM = CS_OP_MEM | CS_OP_IMM, ///< Memory referencing immediate operand. diff --git a/include/capstone/mips.h b/include/capstone/mips.h index 339445611..5ab203c7d 100644 --- a/include/capstone/mips.h +++ b/include/capstone/mips.h @@ -28,205 +28,648 @@ typedef enum mips_op_type { /// MIPS registers typedef enum mips_reg { + // generated content begin + // clang-format off + MIPS_REG_INVALID = 0, - // General purpose registers - MIPS_REG_PC, + MIPS_REG_AT = 1, + MIPS_REG_AT_NM = 2, + MIPS_REG_DSPCCOND = 3, + MIPS_REG_DSPCARRY = 4, + MIPS_REG_DSPEFI = 5, + MIPS_REG_DSPOUTFLAG = 6, + MIPS_REG_DSPPOS = 7, + MIPS_REG_DSPSCOUNT = 8, + MIPS_REG_FP = 9, + MIPS_REG_FP_NM = 10, + MIPS_REG_GP = 11, + MIPS_REG_GP_NM = 12, + MIPS_REG_MSAACCESS = 13, + MIPS_REG_MSACSR = 14, + MIPS_REG_MSAIR = 15, + MIPS_REG_MSAMAP = 16, + MIPS_REG_MSAMODIFY = 17, + MIPS_REG_MSAREQUEST = 18, + MIPS_REG_MSASAVE = 19, + MIPS_REG_MSAUNMAP = 20, + MIPS_REG_PC = 21, + MIPS_REG_RA = 22, + MIPS_REG_RA_NM = 23, + MIPS_REG_SP = 24, + MIPS_REG_SP_NM = 25, + MIPS_REG_ZERO = 26, + MIPS_REG_ZERO_NM = 27, + MIPS_REG_A0 = 28, + MIPS_REG_A1 = 29, + MIPS_REG_A2 = 30, + MIPS_REG_A3 = 31, + MIPS_REG_AC0 = 32, + MIPS_REG_AC1 = 33, + MIPS_REG_AC2 = 34, + MIPS_REG_AC3 = 35, + MIPS_REG_AT_64 = 36, + MIPS_REG_COP00 = 37, + MIPS_REG_COP01 = 38, + MIPS_REG_COP02 = 39, + MIPS_REG_COP03 = 40, + MIPS_REG_COP04 = 41, + MIPS_REG_COP05 = 42, + MIPS_REG_COP06 = 43, + MIPS_REG_COP07 = 44, + MIPS_REG_COP08 = 45, + MIPS_REG_COP09 = 46, + MIPS_REG_COP20 = 47, + MIPS_REG_COP21 = 48, + MIPS_REG_COP22 = 49, + MIPS_REG_COP23 = 50, + MIPS_REG_COP24 = 51, + MIPS_REG_COP25 = 52, + MIPS_REG_COP26 = 53, + MIPS_REG_COP27 = 54, + MIPS_REG_COP28 = 55, + MIPS_REG_COP29 = 56, + MIPS_REG_COP30 = 57, + MIPS_REG_COP31 = 58, + MIPS_REG_COP32 = 59, + MIPS_REG_COP33 = 60, + MIPS_REG_COP34 = 61, + MIPS_REG_COP35 = 62, + MIPS_REG_COP36 = 63, + MIPS_REG_COP37 = 64, + MIPS_REG_COP38 = 65, + MIPS_REG_COP39 = 66, + MIPS_REG_COP010 = 67, + MIPS_REG_COP011 = 68, + MIPS_REG_COP012 = 69, + MIPS_REG_COP013 = 70, + MIPS_REG_COP014 = 71, + MIPS_REG_COP015 = 72, + MIPS_REG_COP016 = 73, + MIPS_REG_COP017 = 74, + MIPS_REG_COP018 = 75, + MIPS_REG_COP019 = 76, + MIPS_REG_COP020 = 77, + MIPS_REG_COP021 = 78, + MIPS_REG_COP022 = 79, + MIPS_REG_COP023 = 80, + MIPS_REG_COP024 = 81, + MIPS_REG_COP025 = 82, + MIPS_REG_COP026 = 83, + MIPS_REG_COP027 = 84, + MIPS_REG_COP028 = 85, + MIPS_REG_COP029 = 86, + MIPS_REG_COP030 = 87, + MIPS_REG_COP031 = 88, + MIPS_REG_COP210 = 89, + MIPS_REG_COP211 = 90, + MIPS_REG_COP212 = 91, + MIPS_REG_COP213 = 92, + MIPS_REG_COP214 = 93, + MIPS_REG_COP215 = 94, + MIPS_REG_COP216 = 95, + MIPS_REG_COP217 = 96, + MIPS_REG_COP218 = 97, + MIPS_REG_COP219 = 98, + MIPS_REG_COP220 = 99, + MIPS_REG_COP221 = 100, + MIPS_REG_COP222 = 101, + MIPS_REG_COP223 = 102, + MIPS_REG_COP224 = 103, + MIPS_REG_COP225 = 104, + MIPS_REG_COP226 = 105, + MIPS_REG_COP227 = 106, + MIPS_REG_COP228 = 107, + MIPS_REG_COP229 = 108, + MIPS_REG_COP230 = 109, + MIPS_REG_COP231 = 110, + MIPS_REG_COP310 = 111, + MIPS_REG_COP311 = 112, + MIPS_REG_COP312 = 113, + MIPS_REG_COP313 = 114, + MIPS_REG_COP314 = 115, + MIPS_REG_COP315 = 116, + MIPS_REG_COP316 = 117, + MIPS_REG_COP317 = 118, + MIPS_REG_COP318 = 119, + MIPS_REG_COP319 = 120, + MIPS_REG_COP320 = 121, + MIPS_REG_COP321 = 122, + MIPS_REG_COP322 = 123, + MIPS_REG_COP323 = 124, + MIPS_REG_COP324 = 125, + MIPS_REG_COP325 = 126, + MIPS_REG_COP326 = 127, + MIPS_REG_COP327 = 128, + MIPS_REG_COP328 = 129, + MIPS_REG_COP329 = 130, + MIPS_REG_COP330 = 131, + MIPS_REG_COP331 = 132, + MIPS_REG_D0 = 133, + MIPS_REG_D1 = 134, + MIPS_REG_D2 = 135, + MIPS_REG_D3 = 136, + MIPS_REG_D4 = 137, + MIPS_REG_D5 = 138, + MIPS_REG_D6 = 139, + MIPS_REG_D7 = 140, + MIPS_REG_D8 = 141, + MIPS_REG_D9 = 142, + MIPS_REG_D10 = 143, + MIPS_REG_D11 = 144, + MIPS_REG_D12 = 145, + MIPS_REG_D13 = 146, + MIPS_REG_D14 = 147, + MIPS_REG_D15 = 148, + MIPS_REG_DSPOUTFLAG20 = 149, + MIPS_REG_DSPOUTFLAG21 = 150, + MIPS_REG_DSPOUTFLAG22 = 151, + MIPS_REG_DSPOUTFLAG23 = 152, + MIPS_REG_F0 = 153, + MIPS_REG_F1 = 154, + MIPS_REG_F2 = 155, + MIPS_REG_F3 = 156, + MIPS_REG_F4 = 157, + MIPS_REG_F5 = 158, + MIPS_REG_F6 = 159, + MIPS_REG_F7 = 160, + MIPS_REG_F8 = 161, + MIPS_REG_F9 = 162, + MIPS_REG_F10 = 163, + MIPS_REG_F11 = 164, + MIPS_REG_F12 = 165, + MIPS_REG_F13 = 166, + MIPS_REG_F14 = 167, + MIPS_REG_F15 = 168, + MIPS_REG_F16 = 169, + MIPS_REG_F17 = 170, + MIPS_REG_F18 = 171, + MIPS_REG_F19 = 172, + MIPS_REG_F20 = 173, + MIPS_REG_F21 = 174, + MIPS_REG_F22 = 175, + MIPS_REG_F23 = 176, + MIPS_REG_F24 = 177, + MIPS_REG_F25 = 178, + MIPS_REG_F26 = 179, + MIPS_REG_F27 = 180, + MIPS_REG_F28 = 181, + MIPS_REG_F29 = 182, + MIPS_REG_F30 = 183, + MIPS_REG_F31 = 184, + MIPS_REG_FCC0 = 185, + MIPS_REG_FCC1 = 186, + MIPS_REG_FCC2 = 187, + MIPS_REG_FCC3 = 188, + MIPS_REG_FCC4 = 189, + MIPS_REG_FCC5 = 190, + MIPS_REG_FCC6 = 191, + MIPS_REG_FCC7 = 192, + MIPS_REG_FCR0 = 193, + MIPS_REG_FCR1 = 194, + MIPS_REG_FCR2 = 195, + MIPS_REG_FCR3 = 196, + MIPS_REG_FCR4 = 197, + MIPS_REG_FCR5 = 198, + MIPS_REG_FCR6 = 199, + MIPS_REG_FCR7 = 200, + MIPS_REG_FCR8 = 201, + MIPS_REG_FCR9 = 202, + MIPS_REG_FCR10 = 203, + MIPS_REG_FCR11 = 204, + MIPS_REG_FCR12 = 205, + MIPS_REG_FCR13 = 206, + MIPS_REG_FCR14 = 207, + MIPS_REG_FCR15 = 208, + MIPS_REG_FCR16 = 209, + MIPS_REG_FCR17 = 210, + MIPS_REG_FCR18 = 211, + MIPS_REG_FCR19 = 212, + MIPS_REG_FCR20 = 213, + MIPS_REG_FCR21 = 214, + MIPS_REG_FCR22 = 215, + MIPS_REG_FCR23 = 216, + MIPS_REG_FCR24 = 217, + MIPS_REG_FCR25 = 218, + MIPS_REG_FCR26 = 219, + MIPS_REG_FCR27 = 220, + MIPS_REG_FCR28 = 221, + MIPS_REG_FCR29 = 222, + MIPS_REG_FCR30 = 223, + MIPS_REG_FCR31 = 224, + MIPS_REG_FP_64 = 225, + MIPS_REG_F_HI0 = 226, + MIPS_REG_F_HI1 = 227, + MIPS_REG_F_HI2 = 228, + MIPS_REG_F_HI3 = 229, + MIPS_REG_F_HI4 = 230, + MIPS_REG_F_HI5 = 231, + MIPS_REG_F_HI6 = 232, + MIPS_REG_F_HI7 = 233, + MIPS_REG_F_HI8 = 234, + MIPS_REG_F_HI9 = 235, + MIPS_REG_F_HI10 = 236, + MIPS_REG_F_HI11 = 237, + MIPS_REG_F_HI12 = 238, + MIPS_REG_F_HI13 = 239, + MIPS_REG_F_HI14 = 240, + MIPS_REG_F_HI15 = 241, + MIPS_REG_F_HI16 = 242, + MIPS_REG_F_HI17 = 243, + MIPS_REG_F_HI18 = 244, + MIPS_REG_F_HI19 = 245, + MIPS_REG_F_HI20 = 246, + MIPS_REG_F_HI21 = 247, + MIPS_REG_F_HI22 = 248, + MIPS_REG_F_HI23 = 249, + MIPS_REG_F_HI24 = 250, + MIPS_REG_F_HI25 = 251, + MIPS_REG_F_HI26 = 252, + MIPS_REG_F_HI27 = 253, + MIPS_REG_F_HI28 = 254, + MIPS_REG_F_HI29 = 255, + MIPS_REG_F_HI30 = 256, + MIPS_REG_F_HI31 = 257, + MIPS_REG_GP_64 = 258, + MIPS_REG_HI0 = 259, + MIPS_REG_HI1 = 260, + MIPS_REG_HI2 = 261, + MIPS_REG_HI3 = 262, + MIPS_REG_HWR0 = 263, + MIPS_REG_HWR1 = 264, + MIPS_REG_HWR2 = 265, + MIPS_REG_HWR3 = 266, + MIPS_REG_HWR4 = 267, + MIPS_REG_HWR5 = 268, + MIPS_REG_HWR6 = 269, + MIPS_REG_HWR7 = 270, + MIPS_REG_HWR8 = 271, + MIPS_REG_HWR9 = 272, + MIPS_REG_HWR10 = 273, + MIPS_REG_HWR11 = 274, + MIPS_REG_HWR12 = 275, + MIPS_REG_HWR13 = 276, + MIPS_REG_HWR14 = 277, + MIPS_REG_HWR15 = 278, + MIPS_REG_HWR16 = 279, + MIPS_REG_HWR17 = 280, + MIPS_REG_HWR18 = 281, + MIPS_REG_HWR19 = 282, + MIPS_REG_HWR20 = 283, + MIPS_REG_HWR21 = 284, + MIPS_REG_HWR22 = 285, + MIPS_REG_HWR23 = 286, + MIPS_REG_HWR24 = 287, + MIPS_REG_HWR25 = 288, + MIPS_REG_HWR26 = 289, + MIPS_REG_HWR27 = 290, + MIPS_REG_HWR28 = 291, + MIPS_REG_HWR29 = 292, + MIPS_REG_HWR30 = 293, + MIPS_REG_HWR31 = 294, + MIPS_REG_K0 = 295, + MIPS_REG_K1 = 296, + MIPS_REG_LO0 = 297, + MIPS_REG_LO1 = 298, + MIPS_REG_LO2 = 299, + MIPS_REG_LO3 = 300, + MIPS_REG_MPL0 = 301, + MIPS_REG_MPL1 = 302, + MIPS_REG_MPL2 = 303, + MIPS_REG_MSA8 = 304, + MIPS_REG_MSA9 = 305, + MIPS_REG_MSA10 = 306, + MIPS_REG_MSA11 = 307, + MIPS_REG_MSA12 = 308, + MIPS_REG_MSA13 = 309, + MIPS_REG_MSA14 = 310, + MIPS_REG_MSA15 = 311, + MIPS_REG_MSA16 = 312, + MIPS_REG_MSA17 = 313, + MIPS_REG_MSA18 = 314, + MIPS_REG_MSA19 = 315, + MIPS_REG_MSA20 = 316, + MIPS_REG_MSA21 = 317, + MIPS_REG_MSA22 = 318, + MIPS_REG_MSA23 = 319, + MIPS_REG_MSA24 = 320, + MIPS_REG_MSA25 = 321, + MIPS_REG_MSA26 = 322, + MIPS_REG_MSA27 = 323, + MIPS_REG_MSA28 = 324, + MIPS_REG_MSA29 = 325, + MIPS_REG_MSA30 = 326, + MIPS_REG_MSA31 = 327, + MIPS_REG_P0 = 328, + MIPS_REG_P1 = 329, + MIPS_REG_P2 = 330, + MIPS_REG_RA_64 = 331, + MIPS_REG_S0 = 332, + MIPS_REG_S1 = 333, + MIPS_REG_S2 = 334, + MIPS_REG_S3 = 335, + MIPS_REG_S4 = 336, + MIPS_REG_S5 = 337, + MIPS_REG_S6 = 338, + MIPS_REG_S7 = 339, + MIPS_REG_SP_64 = 340, + MIPS_REG_T0 = 341, + MIPS_REG_T1 = 342, + MIPS_REG_T2 = 343, + MIPS_REG_T3 = 344, + MIPS_REG_T4 = 345, + MIPS_REG_T5 = 346, + MIPS_REG_T6 = 347, + MIPS_REG_T7 = 348, + MIPS_REG_T8 = 349, + MIPS_REG_T9 = 350, + MIPS_REG_V0 = 351, + MIPS_REG_V1 = 352, + MIPS_REG_W0 = 353, + MIPS_REG_W1 = 354, + MIPS_REG_W2 = 355, + MIPS_REG_W3 = 356, + MIPS_REG_W4 = 357, + MIPS_REG_W5 = 358, + MIPS_REG_W6 = 359, + MIPS_REG_W7 = 360, + MIPS_REG_W8 = 361, + MIPS_REG_W9 = 362, + MIPS_REG_W10 = 363, + MIPS_REG_W11 = 364, + MIPS_REG_W12 = 365, + MIPS_REG_W13 = 366, + MIPS_REG_W14 = 367, + MIPS_REG_W15 = 368, + MIPS_REG_W16 = 369, + MIPS_REG_W17 = 370, + MIPS_REG_W18 = 371, + MIPS_REG_W19 = 372, + MIPS_REG_W20 = 373, + MIPS_REG_W21 = 374, + MIPS_REG_W22 = 375, + MIPS_REG_W23 = 376, + MIPS_REG_W24 = 377, + MIPS_REG_W25 = 378, + MIPS_REG_W26 = 379, + MIPS_REG_W27 = 380, + MIPS_REG_W28 = 381, + MIPS_REG_W29 = 382, + MIPS_REG_W30 = 383, + MIPS_REG_W31 = 384, + MIPS_REG_ZERO_64 = 385, + MIPS_REG_A0_NM = 386, + MIPS_REG_A1_NM = 387, + MIPS_REG_A2_NM = 388, + MIPS_REG_A3_NM = 389, + MIPS_REG_A4_NM = 390, + MIPS_REG_A5_NM = 391, + MIPS_REG_A6_NM = 392, + MIPS_REG_A7_NM = 393, + MIPS_REG_COP0SEL_BADINST = 394, + MIPS_REG_COP0SEL_BADINSTRP = 395, + MIPS_REG_COP0SEL_BADINSTRX = 396, + MIPS_REG_COP0SEL_BADVADDR = 397, + MIPS_REG_COP0SEL_BEVVA = 398, + MIPS_REG_COP0SEL_CACHEERR = 399, + MIPS_REG_COP0SEL_CAUSE = 400, + MIPS_REG_COP0SEL_CDMMBASE = 401, + MIPS_REG_COP0SEL_CMGCRBASE = 402, + MIPS_REG_COP0SEL_COMPARE = 403, + MIPS_REG_COP0SEL_CONFIG = 404, + MIPS_REG_COP0SEL_CONTEXT = 405, + MIPS_REG_COP0SEL_CONTEXTCONFIG = 406, + MIPS_REG_COP0SEL_COUNT = 407, + MIPS_REG_COP0SEL_DDATAHI = 408, + MIPS_REG_COP0SEL_DDATALO = 409, + MIPS_REG_COP0SEL_DEBUG = 410, + MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411, + MIPS_REG_COP0SEL_DEPC = 412, + MIPS_REG_COP0SEL_DESAVE = 413, + MIPS_REG_COP0SEL_DTAGHI = 414, + MIPS_REG_COP0SEL_DTAGLO = 415, + MIPS_REG_COP0SEL_EBASE = 416, + MIPS_REG_COP0SEL_ENTRYHI = 417, + MIPS_REG_COP0SEL_EPC = 418, + MIPS_REG_COP0SEL_ERRCTL = 419, + MIPS_REG_COP0SEL_ERROREPC = 420, + MIPS_REG_COP0SEL_GLOBALNUMBER = 421, + MIPS_REG_COP0SEL_GTOFFSET = 422, + MIPS_REG_COP0SEL_HWRENA = 423, + MIPS_REG_COP0SEL_IDATAHI = 424, + MIPS_REG_COP0SEL_IDATALO = 425, + MIPS_REG_COP0SEL_INDEX = 426, + MIPS_REG_COP0SEL_INTCTL = 427, + MIPS_REG_COP0SEL_ITAGHI = 428, + MIPS_REG_COP0SEL_ITAGLO = 429, + MIPS_REG_COP0SEL_LLADDR = 430, + MIPS_REG_COP0SEL_MAAR = 431, + MIPS_REG_COP0SEL_MAARI = 432, + MIPS_REG_COP0SEL_MEMORYMAPID = 433, + MIPS_REG_COP0SEL_MVPCONTROL = 434, + MIPS_REG_COP0SEL_NESTEDEPC = 435, + MIPS_REG_COP0SEL_NESTEDEXC = 436, + MIPS_REG_COP0SEL_PAGEGRAIN = 437, + MIPS_REG_COP0SEL_PAGEMASK = 438, + MIPS_REG_COP0SEL_PRID = 439, + MIPS_REG_COP0SEL_PWBASE = 440, + MIPS_REG_COP0SEL_PWCTL = 441, + MIPS_REG_COP0SEL_PWFIELD = 442, + MIPS_REG_COP0SEL_PWSIZE = 443, + MIPS_REG_COP0SEL_RANDOM = 444, + MIPS_REG_COP0SEL_SRSCTL = 445, + MIPS_REG_COP0SEL_SRSMAP = 446, + MIPS_REG_COP0SEL_STATUS = 447, + MIPS_REG_COP0SEL_TCBIND = 448, + MIPS_REG_COP0SEL_TCCONTEXT = 449, + MIPS_REG_COP0SEL_TCHALT = 450, + MIPS_REG_COP0SEL_TCOPT = 451, + MIPS_REG_COP0SEL_TCRESTART = 452, + MIPS_REG_COP0SEL_TCSCHEDULE = 453, + MIPS_REG_COP0SEL_TCSCHEFBACK = 454, + MIPS_REG_COP0SEL_TCSTATUS = 455, + MIPS_REG_COP0SEL_TRACECONTROL = 456, + MIPS_REG_COP0SEL_TRACEDBPC = 457, + MIPS_REG_COP0SEL_TRACEIBPC = 458, + MIPS_REG_COP0SEL_USERLOCAL = 459, + MIPS_REG_COP0SEL_VIEW_IPL = 460, + MIPS_REG_COP0SEL_VIEW_RIPL = 461, + MIPS_REG_COP0SEL_VPCONTROL = 462, + MIPS_REG_COP0SEL_VPECONTROL = 463, + MIPS_REG_COP0SEL_VPEOPT = 464, + MIPS_REG_COP0SEL_VPESCHEDULE = 465, + MIPS_REG_COP0SEL_VPESCHEFBACK = 466, + MIPS_REG_COP0SEL_WIRED = 467, + MIPS_REG_COP0SEL_XCONTEXT = 468, + MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469, + MIPS_REG_COP0SEL_YQMASK = 470, + MIPS_REG_K0_NM = 471, + MIPS_REG_K1_NM = 472, + MIPS_REG_S0_NM = 473, + MIPS_REG_S1_NM = 474, + MIPS_REG_S2_NM = 475, + MIPS_REG_S3_NM = 476, + MIPS_REG_S4_NM = 477, + MIPS_REG_S5_NM = 478, + MIPS_REG_S6_NM = 479, + MIPS_REG_S7_NM = 480, + MIPS_REG_T0_NM = 481, + MIPS_REG_T1_NM = 482, + MIPS_REG_T2_NM = 483, + MIPS_REG_T3_NM = 484, + MIPS_REG_T4_NM = 485, + MIPS_REG_T5_NM = 486, + MIPS_REG_T8_NM = 487, + MIPS_REG_T9_NM = 488, + MIPS_REG_A0_64 = 489, + MIPS_REG_A1_64 = 490, + MIPS_REG_A2_64 = 491, + MIPS_REG_A3_64 = 492, + MIPS_REG_AC0_64 = 493, + MIPS_REG_COP0SEL_CONFIG1 = 494, + MIPS_REG_COP0SEL_CONFIG2 = 495, + MIPS_REG_COP0SEL_CONFIG3 = 496, + MIPS_REG_COP0SEL_CONFIG4 = 497, + MIPS_REG_COP0SEL_CONFIG5 = 498, + MIPS_REG_COP0SEL_DEBUG2 = 499, + MIPS_REG_COP0SEL_ENTRYLO0 = 500, + MIPS_REG_COP0SEL_ENTRYLO1 = 501, + MIPS_REG_COP0SEL_GUESTCTL0 = 502, + MIPS_REG_COP0SEL_GUESTCTL1 = 503, + MIPS_REG_COP0SEL_GUESTCTL2 = 504, + MIPS_REG_COP0SEL_GUESTCTL3 = 505, + MIPS_REG_COP0SEL_KSCRATCH1 = 506, + MIPS_REG_COP0SEL_KSCRATCH2 = 507, + MIPS_REG_COP0SEL_KSCRATCH3 = 508, + MIPS_REG_COP0SEL_KSCRATCH4 = 509, + MIPS_REG_COP0SEL_KSCRATCH5 = 510, + MIPS_REG_COP0SEL_KSCRATCH6 = 511, + MIPS_REG_COP0SEL_MVPCONF0 = 512, + MIPS_REG_COP0SEL_MVPCONF1 = 513, + MIPS_REG_COP0SEL_PERFCNT0 = 514, + MIPS_REG_COP0SEL_PERFCNT1 = 515, + MIPS_REG_COP0SEL_PERFCNT2 = 516, + MIPS_REG_COP0SEL_PERFCNT3 = 517, + MIPS_REG_COP0SEL_PERFCNT4 = 518, + MIPS_REG_COP0SEL_PERFCNT5 = 519, + MIPS_REG_COP0SEL_PERFCNT6 = 520, + MIPS_REG_COP0SEL_PERFCNT7 = 521, + MIPS_REG_COP0SEL_PERFCTL0 = 522, + MIPS_REG_COP0SEL_PERFCTL1 = 523, + MIPS_REG_COP0SEL_PERFCTL2 = 524, + MIPS_REG_COP0SEL_PERFCTL3 = 525, + MIPS_REG_COP0SEL_PERFCTL4 = 526, + MIPS_REG_COP0SEL_PERFCTL5 = 527, + MIPS_REG_COP0SEL_PERFCTL6 = 528, + MIPS_REG_COP0SEL_PERFCTL7 = 529, + MIPS_REG_COP0SEL_SEGCTL0 = 530, + MIPS_REG_COP0SEL_SEGCTL1 = 531, + MIPS_REG_COP0SEL_SEGCTL2 = 532, + MIPS_REG_COP0SEL_SRSCONF0 = 533, + MIPS_REG_COP0SEL_SRSCONF1 = 534, + MIPS_REG_COP0SEL_SRSCONF2 = 535, + MIPS_REG_COP0SEL_SRSCONF3 = 536, + MIPS_REG_COP0SEL_SRSCONF4 = 537, + MIPS_REG_COP0SEL_SRSMAP2 = 538, + MIPS_REG_COP0SEL_TRACECONTROL2 = 539, + MIPS_REG_COP0SEL_TRACECONTROL3 = 540, + MIPS_REG_COP0SEL_USERTRACEDATA1 = 541, + MIPS_REG_COP0SEL_USERTRACEDATA2 = 542, + MIPS_REG_COP0SEL_VPECONF0 = 543, + MIPS_REG_COP0SEL_VPECONF1 = 544, + MIPS_REG_COP0SEL_WATCHHI0 = 545, + MIPS_REG_COP0SEL_WATCHHI1 = 546, + MIPS_REG_COP0SEL_WATCHHI2 = 547, + MIPS_REG_COP0SEL_WATCHHI3 = 548, + MIPS_REG_COP0SEL_WATCHHI4 = 549, + MIPS_REG_COP0SEL_WATCHHI5 = 550, + MIPS_REG_COP0SEL_WATCHHI6 = 551, + MIPS_REG_COP0SEL_WATCHHI7 = 552, + MIPS_REG_COP0SEL_WATCHHI8 = 553, + MIPS_REG_COP0SEL_WATCHHI9 = 554, + MIPS_REG_COP0SEL_WATCHHI10 = 555, + MIPS_REG_COP0SEL_WATCHHI11 = 556, + MIPS_REG_COP0SEL_WATCHHI12 = 557, + MIPS_REG_COP0SEL_WATCHHI13 = 558, + MIPS_REG_COP0SEL_WATCHHI14 = 559, + MIPS_REG_COP0SEL_WATCHHI15 = 560, + MIPS_REG_COP0SEL_WATCHLO0 = 561, + MIPS_REG_COP0SEL_WATCHLO1 = 562, + MIPS_REG_COP0SEL_WATCHLO2 = 563, + MIPS_REG_COP0SEL_WATCHLO3 = 564, + MIPS_REG_COP0SEL_WATCHLO4 = 565, + MIPS_REG_COP0SEL_WATCHLO5 = 566, + MIPS_REG_COP0SEL_WATCHLO6 = 567, + MIPS_REG_COP0SEL_WATCHLO7 = 568, + MIPS_REG_COP0SEL_WATCHLO8 = 569, + MIPS_REG_COP0SEL_WATCHLO9 = 570, + MIPS_REG_COP0SEL_WATCHLO10 = 571, + MIPS_REG_COP0SEL_WATCHLO11 = 572, + MIPS_REG_COP0SEL_WATCHLO12 = 573, + MIPS_REG_COP0SEL_WATCHLO13 = 574, + MIPS_REG_COP0SEL_WATCHLO14 = 575, + MIPS_REG_COP0SEL_WATCHLO15 = 576, + MIPS_REG_D0_64 = 577, + MIPS_REG_D1_64 = 578, + MIPS_REG_D2_64 = 579, + MIPS_REG_D3_64 = 580, + MIPS_REG_D4_64 = 581, + MIPS_REG_D5_64 = 582, + MIPS_REG_D6_64 = 583, + MIPS_REG_D7_64 = 584, + MIPS_REG_D8_64 = 585, + MIPS_REG_D9_64 = 586, + MIPS_REG_D10_64 = 587, + MIPS_REG_D11_64 = 588, + MIPS_REG_D12_64 = 589, + MIPS_REG_D13_64 = 590, + MIPS_REG_D14_64 = 591, + MIPS_REG_D15_64 = 592, + MIPS_REG_D16_64 = 593, + MIPS_REG_D17_64 = 594, + MIPS_REG_D18_64 = 595, + MIPS_REG_D19_64 = 596, + MIPS_REG_D20_64 = 597, + MIPS_REG_D21_64 = 598, + MIPS_REG_D22_64 = 599, + MIPS_REG_D23_64 = 600, + MIPS_REG_D24_64 = 601, + MIPS_REG_D25_64 = 602, + MIPS_REG_D26_64 = 603, + MIPS_REG_D27_64 = 604, + MIPS_REG_D28_64 = 605, + MIPS_REG_D29_64 = 606, + MIPS_REG_D30_64 = 607, + MIPS_REG_D31_64 = 608, + MIPS_REG_DSPOUTFLAG16_19 = 609, + MIPS_REG_HI0_64 = 610, + MIPS_REG_K0_64 = 611, + MIPS_REG_K1_64 = 612, + MIPS_REG_LO0_64 = 613, + MIPS_REG_S0_64 = 614, + MIPS_REG_S1_64 = 615, + MIPS_REG_S2_64 = 616, + MIPS_REG_S3_64 = 617, + MIPS_REG_S4_64 = 618, + MIPS_REG_S5_64 = 619, + MIPS_REG_S6_64 = 620, + MIPS_REG_S7_64 = 621, + MIPS_REG_T0_64 = 622, + MIPS_REG_T1_64 = 623, + MIPS_REG_T2_64 = 624, + MIPS_REG_T3_64 = 625, + MIPS_REG_T4_64 = 626, + MIPS_REG_T5_64 = 627, + MIPS_REG_T6_64 = 628, + MIPS_REG_T7_64 = 629, + MIPS_REG_T8_64 = 630, + MIPS_REG_T9_64 = 631, + MIPS_REG_V0_64 = 632, + MIPS_REG_V1_64 = 633, + MIPS_REG_COP0SEL_GUESTCTL0EXT = 634, + MIPS_REG_ENDING, // 635 - MIPS_REG_0, - MIPS_REG_1, - MIPS_REG_2, - MIPS_REG_3, - MIPS_REG_4, - MIPS_REG_5, - MIPS_REG_6, - MIPS_REG_7, - MIPS_REG_8, - MIPS_REG_9, - MIPS_REG_10, - MIPS_REG_11, - MIPS_REG_12, - MIPS_REG_13, - MIPS_REG_14, - MIPS_REG_15, - MIPS_REG_16, - MIPS_REG_17, - MIPS_REG_18, - MIPS_REG_19, - MIPS_REG_20, - MIPS_REG_21, - MIPS_REG_22, - MIPS_REG_23, - MIPS_REG_24, - MIPS_REG_25, - MIPS_REG_26, - MIPS_REG_27, - MIPS_REG_28, - MIPS_REG_29, - MIPS_REG_30, - MIPS_REG_31, - - // DSP registers - MIPS_REG_DSPCCOND, - MIPS_REG_DSPCARRY, - MIPS_REG_DSPEFI, - MIPS_REG_DSPOUTFLAG, - MIPS_REG_DSPOUTFLAG16_19, - MIPS_REG_DSPOUTFLAG20, - MIPS_REG_DSPOUTFLAG21, - MIPS_REG_DSPOUTFLAG22, - MIPS_REG_DSPOUTFLAG23, - MIPS_REG_DSPPOS, - MIPS_REG_DSPSCOUNT, - - // ACC registers - MIPS_REG_AC0, - MIPS_REG_AC1, - MIPS_REG_AC2, - MIPS_REG_AC3, - - // COP registers - MIPS_REG_CC0, - MIPS_REG_CC1, - MIPS_REG_CC2, - MIPS_REG_CC3, - MIPS_REG_CC4, - MIPS_REG_CC5, - MIPS_REG_CC6, - MIPS_REG_CC7, - - // FPU registers - MIPS_REG_F0, - MIPS_REG_F1, - MIPS_REG_F2, - MIPS_REG_F3, - MIPS_REG_F4, - MIPS_REG_F5, - MIPS_REG_F6, - MIPS_REG_F7, - MIPS_REG_F8, - MIPS_REG_F9, - MIPS_REG_F10, - MIPS_REG_F11, - MIPS_REG_F12, - MIPS_REG_F13, - MIPS_REG_F14, - MIPS_REG_F15, - MIPS_REG_F16, - MIPS_REG_F17, - MIPS_REG_F18, - MIPS_REG_F19, - MIPS_REG_F20, - MIPS_REG_F21, - MIPS_REG_F22, - MIPS_REG_F23, - MIPS_REG_F24, - MIPS_REG_F25, - MIPS_REG_F26, - MIPS_REG_F27, - MIPS_REG_F28, - MIPS_REG_F29, - MIPS_REG_F30, - MIPS_REG_F31, - - MIPS_REG_FCC0, - MIPS_REG_FCC1, - MIPS_REG_FCC2, - MIPS_REG_FCC3, - MIPS_REG_FCC4, - MIPS_REG_FCC5, - MIPS_REG_FCC6, - MIPS_REG_FCC7, - - // AFPR128 - MIPS_REG_W0, - MIPS_REG_W1, - MIPS_REG_W2, - MIPS_REG_W3, - MIPS_REG_W4, - MIPS_REG_W5, - MIPS_REG_W6, - MIPS_REG_W7, - MIPS_REG_W8, - MIPS_REG_W9, - MIPS_REG_W10, - MIPS_REG_W11, - MIPS_REG_W12, - MIPS_REG_W13, - MIPS_REG_W14, - MIPS_REG_W15, - MIPS_REG_W16, - MIPS_REG_W17, - MIPS_REG_W18, - MIPS_REG_W19, - MIPS_REG_W20, - MIPS_REG_W21, - MIPS_REG_W22, - MIPS_REG_W23, - MIPS_REG_W24, - MIPS_REG_W25, - MIPS_REG_W26, - MIPS_REG_W27, - MIPS_REG_W28, - MIPS_REG_W29, - MIPS_REG_W30, - MIPS_REG_W31, - - MIPS_REG_HI, - MIPS_REG_LO, - - MIPS_REG_P0, - MIPS_REG_P1, - MIPS_REG_P2, - - MIPS_REG_MPL0, - MIPS_REG_MPL1, - MIPS_REG_MPL2, - - MIPS_REG_ENDING, // <-- mark the end of the list or registers - - // alias registers - MIPS_REG_ZERO = MIPS_REG_0, - MIPS_REG_AT = MIPS_REG_1, - MIPS_REG_V0 = MIPS_REG_2, - MIPS_REG_V1 = MIPS_REG_3, - MIPS_REG_A0 = MIPS_REG_4, - MIPS_REG_A1 = MIPS_REG_5, - MIPS_REG_A2 = MIPS_REG_6, - MIPS_REG_A3 = MIPS_REG_7, - MIPS_REG_T0 = MIPS_REG_8, - MIPS_REG_T1 = MIPS_REG_9, - MIPS_REG_T2 = MIPS_REG_10, - MIPS_REG_T3 = MIPS_REG_11, - MIPS_REG_T4 = MIPS_REG_12, - MIPS_REG_T5 = MIPS_REG_13, - MIPS_REG_T6 = MIPS_REG_14, - MIPS_REG_T7 = MIPS_REG_15, - MIPS_REG_S0 = MIPS_REG_16, - MIPS_REG_S1 = MIPS_REG_17, - MIPS_REG_S2 = MIPS_REG_18, - MIPS_REG_S3 = MIPS_REG_19, - MIPS_REG_S4 = MIPS_REG_20, - MIPS_REG_S5 = MIPS_REG_21, - MIPS_REG_S6 = MIPS_REG_22, - MIPS_REG_S7 = MIPS_REG_23, - MIPS_REG_T8 = MIPS_REG_24, - MIPS_REG_T9 = MIPS_REG_25, - MIPS_REG_K0 = MIPS_REG_26, - MIPS_REG_K1 = MIPS_REG_27, - MIPS_REG_GP = MIPS_REG_28, - MIPS_REG_SP = MIPS_REG_29, - MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30, - MIPS_REG_RA = MIPS_REG_31, - - MIPS_REG_HI0 = MIPS_REG_AC0, - MIPS_REG_HI1 = MIPS_REG_AC1, - MIPS_REG_HI2 = MIPS_REG_AC2, - MIPS_REG_HI3 = MIPS_REG_AC3, - - MIPS_REG_LO0 = MIPS_REG_HI0, - MIPS_REG_LO1 = MIPS_REG_HI1, - MIPS_REG_LO2 = MIPS_REG_HI2, - MIPS_REG_LO3 = MIPS_REG_HI3, + // clang-format on + // generated content end } mips_reg; /// Instruction's operand referring to memory @@ -241,9 +684,16 @@ typedef struct cs_mips_op { mips_op_type type; ///< operand type union { mips_reg reg; ///< register id for REG operand - int64_t imm; ///< immediate value for IMM operand + int64_t imm; ///< signed immediate value for IMM operand + uint64_t uimm; ///< unsigned immediate value for IMM operand mips_op_mem mem; ///< base/index/scale/disp value for MEM operand }; + bool is_reglist; ///< defines if the register is part of a list + bool is_unsigned; ///< when true, the immediate value is unsigned + + /// How is this operand accessed? (READ, WRITE or READ|WRITE) + /// NOTE: this field is irrelevant if engine is compiled in DIET mode. + uint8_t access; } cs_mips_op; /// Instruction structure @@ -256,88 +706,232 @@ typedef struct cs_mips { /// MIPS instruction typedef enum mips_insn { - MIPS_INS_INVALID = 0, + // generated content begin + // clang-format off - MIPS_INS_ABSQ_S, + MIPS_INS_INVALID, + MIPS_INS_ABS, + MIPS_INS_ALIGN, + MIPS_INS_BEQL, + MIPS_INS_BGE, + MIPS_INS_BGEL, + MIPS_INS_BGEU, + MIPS_INS_BGEUL, + MIPS_INS_BGT, + MIPS_INS_BGTL, + MIPS_INS_BGTU, + MIPS_INS_BGTUL, + MIPS_INS_BLE, + MIPS_INS_BLEL, + MIPS_INS_BLEU, + MIPS_INS_BLEUL, + MIPS_INS_BLT, + MIPS_INS_BLTL, + MIPS_INS_BLTU, + MIPS_INS_BLTUL, + MIPS_INS_BNEL, + MIPS_INS_B, + MIPS_INS_BEQ, + MIPS_INS_BNE, + MIPS_INS_CFTC1, + MIPS_INS_CTTC1, + MIPS_INS_DMUL, + MIPS_INS_DMULO, + MIPS_INS_DMULOU, + MIPS_INS_DROL, + MIPS_INS_DROR, + MIPS_INS_DDIV, + MIPS_INS_DREM, + MIPS_INS_DDIVU, + MIPS_INS_DREMU, + MIPS_INS_JAL, + MIPS_INS_LD, + MIPS_INS_LWM, + MIPS_INS_LA, + MIPS_INS_DLA, + MIPS_INS_LI, + MIPS_INS_DLI, + MIPS_INS_LI_D, + MIPS_INS_LI_S, + MIPS_INS_MFTACX, + MIPS_INS_MFTC0, + MIPS_INS_MFTC1, + MIPS_INS_MFTDSP, + MIPS_INS_MFTGPR, + MIPS_INS_MFTHC1, + MIPS_INS_MFTHI, + MIPS_INS_MFTLO, + MIPS_INS_MTTACX, + MIPS_INS_MTTC0, + MIPS_INS_MTTC1, + MIPS_INS_MTTDSP, + MIPS_INS_MTTGPR, + MIPS_INS_MTTHC1, + MIPS_INS_MTTHI, + MIPS_INS_MTTLO, + MIPS_INS_MUL, + MIPS_INS_MULO, + MIPS_INS_MULOU, + MIPS_INS_NOR, + MIPS_INS_ADDIU, + MIPS_INS_ANDI, + MIPS_INS_SUBU, + MIPS_INS_TRUNC_W_D, + MIPS_INS_TRUNC_W_S, + MIPS_INS_ROL, + MIPS_INS_ROR, + MIPS_INS_S_D, + MIPS_INS_SD, + MIPS_INS_DIV, + MIPS_INS_SEQ, + MIPS_INS_SGE, + MIPS_INS_SGEU, + MIPS_INS_SGT, + MIPS_INS_SGTU, + MIPS_INS_SLE, + MIPS_INS_SLEU, + MIPS_INS_SLT, + MIPS_INS_SLTU, + MIPS_INS_SNE, + MIPS_INS_REM, + MIPS_INS_SWM, + MIPS_INS_SAA, + MIPS_INS_SAAD, + MIPS_INS_DIVU, + MIPS_INS_REMU, + MIPS_INS_ULH, + MIPS_INS_ULHU, + MIPS_INS_ULW, + MIPS_INS_USH, + MIPS_INS_USW, + MIPS_INS_ABSQ_S_PH, + MIPS_INS_ABSQ_S_QB, + MIPS_INS_ABSQ_S_W, MIPS_INS_ADD, MIPS_INS_ADDIUPC, MIPS_INS_ADDIUR1SP, MIPS_INS_ADDIUR2, MIPS_INS_ADDIUS5, MIPS_INS_ADDIUSP, - MIPS_INS_ADDQH, - MIPS_INS_ADDQH_R, - MIPS_INS_ADDQ, - MIPS_INS_ADDQ_S, + MIPS_INS_ADDQH_PH, + MIPS_INS_ADDQH_R_PH, + MIPS_INS_ADDQH_R_W, + MIPS_INS_ADDQH_W, + MIPS_INS_ADDQ_PH, + MIPS_INS_ADDQ_S_PH, + MIPS_INS_ADDQ_S_W, + MIPS_INS_ADDR_PS, MIPS_INS_ADDSC, - MIPS_INS_ADDS_A, - MIPS_INS_ADDS_S, - MIPS_INS_ADDS_U, + MIPS_INS_ADDS_A_B, + MIPS_INS_ADDS_A_D, + MIPS_INS_ADDS_A_H, + MIPS_INS_ADDS_A_W, + MIPS_INS_ADDS_S_B, + MIPS_INS_ADDS_S_D, + MIPS_INS_ADDS_S_H, + MIPS_INS_ADDS_S_W, + MIPS_INS_ADDS_U_B, + MIPS_INS_ADDS_U_D, + MIPS_INS_ADDS_U_H, + MIPS_INS_ADDS_U_W, MIPS_INS_ADDU16, - MIPS_INS_ADDUH, - MIPS_INS_ADDUH_R, + MIPS_INS_ADDUH_QB, + MIPS_INS_ADDUH_R_QB, MIPS_INS_ADDU, - MIPS_INS_ADDU_S, - MIPS_INS_ADDVI, - MIPS_INS_ADDV, + MIPS_INS_ADDU_PH, + MIPS_INS_ADDU_QB, + MIPS_INS_ADDU_S_PH, + MIPS_INS_ADDU_S_QB, + MIPS_INS_ADDVI_B, + MIPS_INS_ADDVI_D, + MIPS_INS_ADDVI_H, + MIPS_INS_ADDVI_W, + MIPS_INS_ADDV_B, + MIPS_INS_ADDV_D, + MIPS_INS_ADDV_H, + MIPS_INS_ADDV_W, MIPS_INS_ADDWC, - MIPS_INS_ADD_A, + MIPS_INS_ADD_A_B, + MIPS_INS_ADD_A_D, + MIPS_INS_ADD_A_H, + MIPS_INS_ADD_A_W, MIPS_INS_ADDI, - MIPS_INS_ADDIU, - MIPS_INS_ALIGN, MIPS_INS_ALUIPC, MIPS_INS_AND, MIPS_INS_AND16, MIPS_INS_ANDI16, - MIPS_INS_ANDI, + MIPS_INS_ANDI_B, + MIPS_INS_AND_V, MIPS_INS_APPEND, - MIPS_INS_ASUB_S, - MIPS_INS_ASUB_U, + MIPS_INS_ASUB_S_B, + MIPS_INS_ASUB_S_D, + MIPS_INS_ASUB_S_H, + MIPS_INS_ASUB_S_W, + MIPS_INS_ASUB_U_B, + MIPS_INS_ASUB_U_D, + MIPS_INS_ASUB_U_H, + MIPS_INS_ASUB_U_W, MIPS_INS_AUI, MIPS_INS_AUIPC, - MIPS_INS_AVER_S, - MIPS_INS_AVER_U, - MIPS_INS_AVE_S, - MIPS_INS_AVE_U, + MIPS_INS_AVER_S_B, + MIPS_INS_AVER_S_D, + MIPS_INS_AVER_S_H, + MIPS_INS_AVER_S_W, + MIPS_INS_AVER_U_B, + MIPS_INS_AVER_U_D, + MIPS_INS_AVER_U_H, + MIPS_INS_AVER_U_W, + MIPS_INS_AVE_S_B, + MIPS_INS_AVE_S_D, + MIPS_INS_AVE_S_H, + MIPS_INS_AVE_S_W, + MIPS_INS_AVE_U_B, + MIPS_INS_AVE_U_D, + MIPS_INS_AVE_U_H, + MIPS_INS_AVE_U_W, MIPS_INS_B16, MIPS_INS_BADDU, MIPS_INS_BAL, MIPS_INS_BALC, MIPS_INS_BALIGN, + MIPS_INS_BALRSC, + MIPS_INS_BBEQZC, MIPS_INS_BBIT0, MIPS_INS_BBIT032, MIPS_INS_BBIT1, MIPS_INS_BBIT132, + MIPS_INS_BBNEZC, MIPS_INS_BC, - MIPS_INS_BC0F, - MIPS_INS_BC0FL, - MIPS_INS_BC0T, - MIPS_INS_BC0TL, + MIPS_INS_BC16, MIPS_INS_BC1EQZ, + MIPS_INS_BC1EQZC, MIPS_INS_BC1F, MIPS_INS_BC1FL, MIPS_INS_BC1NEZ, + MIPS_INS_BC1NEZC, MIPS_INS_BC1T, MIPS_INS_BC1TL, MIPS_INS_BC2EQZ, - MIPS_INS_BC2F, - MIPS_INS_BC2FL, + MIPS_INS_BC2EQZC, MIPS_INS_BC2NEZ, - MIPS_INS_BC2T, - MIPS_INS_BC2TL, - MIPS_INS_BC3F, - MIPS_INS_BC3FL, - MIPS_INS_BC3T, - MIPS_INS_BC3TL, - MIPS_INS_BCLRI, - MIPS_INS_BCLR, - MIPS_INS_BEQ, + MIPS_INS_BC2NEZC, + MIPS_INS_BCLRI_B, + MIPS_INS_BCLRI_D, + MIPS_INS_BCLRI_H, + MIPS_INS_BCLRI_W, + MIPS_INS_BCLR_B, + MIPS_INS_BCLR_D, + MIPS_INS_BCLR_H, + MIPS_INS_BCLR_W, MIPS_INS_BEQC, - MIPS_INS_BEQL, + MIPS_INS_BEQIC, MIPS_INS_BEQZ16, MIPS_INS_BEQZALC, MIPS_INS_BEQZC, + MIPS_INS_BEQZC16, MIPS_INS_BGEC, + MIPS_INS_BGEIC, + MIPS_INS_BGEIUC, MIPS_INS_BGEUC, MIPS_INS_BGEZ, MIPS_INS_BGEZAL, @@ -350,17 +944,32 @@ typedef enum mips_insn { MIPS_INS_BGTZALC, MIPS_INS_BGTZC, MIPS_INS_BGTZL, - MIPS_INS_BINSLI, - MIPS_INS_BINSL, - MIPS_INS_BINSRI, - MIPS_INS_BINSR, + MIPS_INS_BINSLI_B, + MIPS_INS_BINSLI_D, + MIPS_INS_BINSLI_H, + MIPS_INS_BINSLI_W, + MIPS_INS_BINSL_B, + MIPS_INS_BINSL_D, + MIPS_INS_BINSL_H, + MIPS_INS_BINSL_W, + MIPS_INS_BINSRI_B, + MIPS_INS_BINSRI_D, + MIPS_INS_BINSRI_H, + MIPS_INS_BINSRI_W, + MIPS_INS_BINSR_B, + MIPS_INS_BINSR_D, + MIPS_INS_BINSR_H, + MIPS_INS_BINSR_W, MIPS_INS_BITREV, + MIPS_INS_BITREVW, MIPS_INS_BITSWAP, MIPS_INS_BLEZ, MIPS_INS_BLEZALC, MIPS_INS_BLEZC, MIPS_INS_BLEZL, MIPS_INS_BLTC, + MIPS_INS_BLTIC, + MIPS_INS_BLTIUC, MIPS_INS_BLTUC, MIPS_INS_BLTZ, MIPS_INS_BLTZAL, @@ -369,63 +978,221 @@ typedef enum mips_insn { MIPS_INS_BLTZALS, MIPS_INS_BLTZC, MIPS_INS_BLTZL, - MIPS_INS_BMNZI, - MIPS_INS_BMNZ, - MIPS_INS_BMZI, - MIPS_INS_BMZ, - MIPS_INS_BNE, + MIPS_INS_BMNZI_B, + MIPS_INS_BMNZ_V, + MIPS_INS_BMZI_B, + MIPS_INS_BMZ_V, MIPS_INS_BNEC, - MIPS_INS_BNEGI, - MIPS_INS_BNEG, - MIPS_INS_BNEL, + MIPS_INS_BNEGI_B, + MIPS_INS_BNEGI_D, + MIPS_INS_BNEGI_H, + MIPS_INS_BNEGI_W, + MIPS_INS_BNEG_B, + MIPS_INS_BNEG_D, + MIPS_INS_BNEG_H, + MIPS_INS_BNEG_W, + MIPS_INS_BNEIC, MIPS_INS_BNEZ16, MIPS_INS_BNEZALC, MIPS_INS_BNEZC, + MIPS_INS_BNEZC16, MIPS_INS_BNVC, - MIPS_INS_BNZ, + MIPS_INS_BNZ_B, + MIPS_INS_BNZ_D, + MIPS_INS_BNZ_H, + MIPS_INS_BNZ_V, + MIPS_INS_BNZ_W, MIPS_INS_BOVC, MIPS_INS_BPOSGE32, + MIPS_INS_BPOSGE32C, MIPS_INS_BREAK, MIPS_INS_BREAK16, - MIPS_INS_BSELI, - MIPS_INS_BSEL, - MIPS_INS_BSETI, - MIPS_INS_BSET, - MIPS_INS_BZ, + MIPS_INS_BRSC, + MIPS_INS_BSELI_B, + MIPS_INS_BSEL_V, + MIPS_INS_BSETI_B, + MIPS_INS_BSETI_D, + MIPS_INS_BSETI_H, + MIPS_INS_BSETI_W, + MIPS_INS_BSET_B, + MIPS_INS_BSET_D, + MIPS_INS_BSET_H, + MIPS_INS_BSET_W, + MIPS_INS_BYTEREVW, + MIPS_INS_BZ_B, + MIPS_INS_BZ_D, + MIPS_INS_BZ_H, + MIPS_INS_BZ_V, + MIPS_INS_BZ_W, MIPS_INS_BEQZ, - MIPS_INS_B, MIPS_INS_BNEZ, MIPS_INS_BTEQZ, MIPS_INS_BTNEZ, MIPS_INS_CACHE, - MIPS_INS_CEIL, - MIPS_INS_CEQI, - MIPS_INS_CEQ, + MIPS_INS_CACHEE, + MIPS_INS_CEIL_L_D, + MIPS_INS_CEIL_L_S, + MIPS_INS_CEIL_W_D, + MIPS_INS_CEIL_W_S, + MIPS_INS_CEQI_B, + MIPS_INS_CEQI_D, + MIPS_INS_CEQI_H, + MIPS_INS_CEQI_W, + MIPS_INS_CEQ_B, + MIPS_INS_CEQ_D, + MIPS_INS_CEQ_H, + MIPS_INS_CEQ_W, MIPS_INS_CFC1, + MIPS_INS_CFC2, MIPS_INS_CFCMSA, MIPS_INS_CINS, MIPS_INS_CINS32, - MIPS_INS_CLASS, - MIPS_INS_CLEI_S, - MIPS_INS_CLEI_U, - MIPS_INS_CLE_S, - MIPS_INS_CLE_U, + MIPS_INS_CLASS_D, + MIPS_INS_CLASS_S, + MIPS_INS_CLEI_S_B, + MIPS_INS_CLEI_S_D, + MIPS_INS_CLEI_S_H, + MIPS_INS_CLEI_S_W, + MIPS_INS_CLEI_U_B, + MIPS_INS_CLEI_U_D, + MIPS_INS_CLEI_U_H, + MIPS_INS_CLEI_U_W, + MIPS_INS_CLE_S_B, + MIPS_INS_CLE_S_D, + MIPS_INS_CLE_S_H, + MIPS_INS_CLE_S_W, + MIPS_INS_CLE_U_B, + MIPS_INS_CLE_U_D, + MIPS_INS_CLE_U_H, + MIPS_INS_CLE_U_W, MIPS_INS_CLO, - MIPS_INS_CLTI_S, - MIPS_INS_CLTI_U, - MIPS_INS_CLT_S, - MIPS_INS_CLT_U, + MIPS_INS_CLTI_S_B, + MIPS_INS_CLTI_S_D, + MIPS_INS_CLTI_S_H, + MIPS_INS_CLTI_S_W, + MIPS_INS_CLTI_U_B, + MIPS_INS_CLTI_U_D, + MIPS_INS_CLTI_U_H, + MIPS_INS_CLTI_U_W, + MIPS_INS_CLT_S_B, + MIPS_INS_CLT_S_D, + MIPS_INS_CLT_S_H, + MIPS_INS_CLT_S_W, + MIPS_INS_CLT_U_B, + MIPS_INS_CLT_U_D, + MIPS_INS_CLT_U_H, + MIPS_INS_CLT_U_W, MIPS_INS_CLZ, - MIPS_INS_CMPGDU, - MIPS_INS_CMPGU, - MIPS_INS_CMPU, - MIPS_INS_CMP, - MIPS_INS_COPY_S, - MIPS_INS_COPY_U, + MIPS_INS_CMPGDU_EQ_QB, + MIPS_INS_CMPGDU_LE_QB, + MIPS_INS_CMPGDU_LT_QB, + MIPS_INS_CMPGU_EQ_QB, + MIPS_INS_CMPGU_LE_QB, + MIPS_INS_CMPGU_LT_QB, + MIPS_INS_CMPU_EQ_QB, + MIPS_INS_CMPU_LE_QB, + MIPS_INS_CMPU_LT_QB, + MIPS_INS_CMP_AF_D, + MIPS_INS_CMP_AF_S, + MIPS_INS_CMP_EQ_D, + MIPS_INS_CMP_EQ_PH, + MIPS_INS_CMP_EQ_S, + MIPS_INS_CMP_LE_D, + MIPS_INS_CMP_LE_PH, + MIPS_INS_CMP_LE_S, + MIPS_INS_CMP_LT_D, + MIPS_INS_CMP_LT_PH, + MIPS_INS_CMP_LT_S, + MIPS_INS_CMP_SAF_D, + MIPS_INS_CMP_SAF_S, + MIPS_INS_CMP_SEQ_D, + MIPS_INS_CMP_SEQ_S, + MIPS_INS_CMP_SLE_D, + MIPS_INS_CMP_SLE_S, + MIPS_INS_CMP_SLT_D, + MIPS_INS_CMP_SLT_S, + MIPS_INS_CMP_SUEQ_D, + MIPS_INS_CMP_SUEQ_S, + MIPS_INS_CMP_SULE_D, + MIPS_INS_CMP_SULE_S, + MIPS_INS_CMP_SULT_D, + MIPS_INS_CMP_SULT_S, + MIPS_INS_CMP_SUN_D, + MIPS_INS_CMP_SUN_S, + MIPS_INS_CMP_UEQ_D, + MIPS_INS_CMP_UEQ_S, + MIPS_INS_CMP_ULE_D, + MIPS_INS_CMP_ULE_S, + MIPS_INS_CMP_ULT_D, + MIPS_INS_CMP_ULT_S, + MIPS_INS_CMP_UN_D, + MIPS_INS_CMP_UN_S, + MIPS_INS_COPY_S_B, + MIPS_INS_COPY_S_D, + MIPS_INS_COPY_S_H, + MIPS_INS_COPY_S_W, + MIPS_INS_COPY_U_B, + MIPS_INS_COPY_U_H, + MIPS_INS_COPY_U_W, + MIPS_INS_CRC32B, + MIPS_INS_CRC32CB, + MIPS_INS_CRC32CD, + MIPS_INS_CRC32CH, + MIPS_INS_CRC32CW, + MIPS_INS_CRC32D, + MIPS_INS_CRC32H, + MIPS_INS_CRC32W, MIPS_INS_CTC1, + MIPS_INS_CTC2, MIPS_INS_CTCMSA, - MIPS_INS_CVT, - MIPS_INS_C, + MIPS_INS_CVT_D_S, + MIPS_INS_CVT_D_W, + MIPS_INS_CVT_D_L, + MIPS_INS_CVT_L_D, + MIPS_INS_CVT_L_S, + MIPS_INS_CVT_PS_PW, + MIPS_INS_CVT_PS_S, + MIPS_INS_CVT_PW_PS, + MIPS_INS_CVT_S_D, + MIPS_INS_CVT_S_L, + MIPS_INS_CVT_S_PL, + MIPS_INS_CVT_S_PU, + MIPS_INS_CVT_S_W, + MIPS_INS_CVT_W_D, + MIPS_INS_CVT_W_S, + MIPS_INS_C_EQ_D, + MIPS_INS_C_EQ_S, + MIPS_INS_C_F_D, + MIPS_INS_C_F_S, + MIPS_INS_C_LE_D, + MIPS_INS_C_LE_S, + MIPS_INS_C_LT_D, + MIPS_INS_C_LT_S, + MIPS_INS_C_NGE_D, + MIPS_INS_C_NGE_S, + MIPS_INS_C_NGLE_D, + MIPS_INS_C_NGLE_S, + MIPS_INS_C_NGL_D, + MIPS_INS_C_NGL_S, + MIPS_INS_C_NGT_D, + MIPS_INS_C_NGT_S, + MIPS_INS_C_OLE_D, + MIPS_INS_C_OLE_S, + MIPS_INS_C_OLT_D, + MIPS_INS_C_OLT_S, + MIPS_INS_C_SEQ_D, + MIPS_INS_C_SEQ_S, + MIPS_INS_C_SF_D, + MIPS_INS_C_SF_S, + MIPS_INS_C_UEQ_D, + MIPS_INS_C_UEQ_S, + MIPS_INS_C_ULE_D, + MIPS_INS_C_ULE_S, + MIPS_INS_C_ULT_D, + MIPS_INS_C_ULT_S, + MIPS_INS_C_UN_D, + MIPS_INS_C_UN_S, + MIPS_INS_CMP, MIPS_INS_CMPI, MIPS_INS_DADD, MIPS_INS_DADDI, @@ -438,8 +1205,6 @@ typedef enum mips_insn { MIPS_INS_DBITSWAP, MIPS_INS_DCLO, MIPS_INS_DCLZ, - MIPS_INS_DDIV, - MIPS_INS_DDIVU, MIPS_INS_DERET, MIPS_INS_DEXT, MIPS_INS_DEXTM, @@ -448,46 +1213,66 @@ typedef enum mips_insn { MIPS_INS_DINS, MIPS_INS_DINSM, MIPS_INS_DINSU, - MIPS_INS_DIV, - MIPS_INS_DIVU, - MIPS_INS_DIV_S, - MIPS_INS_DIV_U, + MIPS_INS_DIV_S_B, + MIPS_INS_DIV_S_D, + MIPS_INS_DIV_S_H, + MIPS_INS_DIV_S_W, + MIPS_INS_DIV_U_B, + MIPS_INS_DIV_U_D, + MIPS_INS_DIV_U_H, + MIPS_INS_DIV_U_W, MIPS_INS_DLSA, MIPS_INS_DMFC0, MIPS_INS_DMFC1, MIPS_INS_DMFC2, + MIPS_INS_DMFGC0, MIPS_INS_DMOD, MIPS_INS_DMODU, + MIPS_INS_DMT, MIPS_INS_DMTC0, MIPS_INS_DMTC1, MIPS_INS_DMTC2, + MIPS_INS_DMTGC0, MIPS_INS_DMUH, MIPS_INS_DMUHU, - MIPS_INS_DMUL, MIPS_INS_DMULT, MIPS_INS_DMULTU, MIPS_INS_DMULU, - MIPS_INS_DOTP_S, - MIPS_INS_DOTP_U, - MIPS_INS_DPADD_S, - MIPS_INS_DPADD_U, - MIPS_INS_DPAQX_SA, - MIPS_INS_DPAQX_S, - MIPS_INS_DPAQ_SA, - MIPS_INS_DPAQ_S, - MIPS_INS_DPAU, - MIPS_INS_DPAX, - MIPS_INS_DPA, + MIPS_INS_DOTP_S_D, + MIPS_INS_DOTP_S_H, + MIPS_INS_DOTP_S_W, + MIPS_INS_DOTP_U_D, + MIPS_INS_DOTP_U_H, + MIPS_INS_DOTP_U_W, + MIPS_INS_DPADD_S_D, + MIPS_INS_DPADD_S_H, + MIPS_INS_DPADD_S_W, + MIPS_INS_DPADD_U_D, + MIPS_INS_DPADD_U_H, + MIPS_INS_DPADD_U_W, + MIPS_INS_DPAQX_SA_W_PH, + MIPS_INS_DPAQX_S_W_PH, + MIPS_INS_DPAQ_SA_L_W, + MIPS_INS_DPAQ_S_W_PH, + MIPS_INS_DPAU_H_QBL, + MIPS_INS_DPAU_H_QBR, + MIPS_INS_DPAX_W_PH, + MIPS_INS_DPA_W_PH, MIPS_INS_DPOP, - MIPS_INS_DPSQX_SA, - MIPS_INS_DPSQX_S, - MIPS_INS_DPSQ_SA, - MIPS_INS_DPSQ_S, - MIPS_INS_DPSUB_S, - MIPS_INS_DPSUB_U, - MIPS_INS_DPSU, - MIPS_INS_DPSX, - MIPS_INS_DPS, + MIPS_INS_DPSQX_SA_W_PH, + MIPS_INS_DPSQX_S_W_PH, + MIPS_INS_DPSQ_SA_L_W, + MIPS_INS_DPSQ_S_W_PH, + MIPS_INS_DPSUB_S_D, + MIPS_INS_DPSUB_S_H, + MIPS_INS_DPSUB_S_W, + MIPS_INS_DPSUB_U_D, + MIPS_INS_DPSUB_U_H, + MIPS_INS_DPSUB_U_W, + MIPS_INS_DPSU_H_QBL, + MIPS_INS_DPSU_H_QBR, + MIPS_INS_DPSX_W_PH, + MIPS_INS_DPS_W_PH, MIPS_INS_DROTR, MIPS_INS_DROTR32, MIPS_INS_DROTRV, @@ -504,100 +1289,209 @@ typedef enum mips_insn { MIPS_INS_DSRLV, MIPS_INS_DSUB, MIPS_INS_DSUBU, + MIPS_INS_DVP, + MIPS_INS_DVPE, MIPS_INS_EHB, MIPS_INS_EI, + MIPS_INS_EMT, MIPS_INS_ERET, + MIPS_INS_ERETNC, + MIPS_INS_EVP, + MIPS_INS_EVPE, MIPS_INS_EXT, MIPS_INS_EXTP, MIPS_INS_EXTPDP, MIPS_INS_EXTPDPV, MIPS_INS_EXTPV, - MIPS_INS_EXTRV_RS, - MIPS_INS_EXTRV_R, - MIPS_INS_EXTRV_S, - MIPS_INS_EXTRV, - MIPS_INS_EXTR_RS, - MIPS_INS_EXTR_R, - MIPS_INS_EXTR_S, - MIPS_INS_EXTR, + MIPS_INS_EXTRV_RS_W, + MIPS_INS_EXTRV_R_W, + MIPS_INS_EXTRV_S_H, + MIPS_INS_EXTRV_W, + MIPS_INS_EXTR_RS_W, + MIPS_INS_EXTR_R_W, + MIPS_INS_EXTR_S_H, + MIPS_INS_EXTR_W, MIPS_INS_EXTS, MIPS_INS_EXTS32, - MIPS_INS_ABS, - MIPS_INS_FADD, - MIPS_INS_FCAF, - MIPS_INS_FCEQ, - MIPS_INS_FCLASS, - MIPS_INS_FCLE, - MIPS_INS_FCLT, - MIPS_INS_FCNE, - MIPS_INS_FCOR, - MIPS_INS_FCUEQ, - MIPS_INS_FCULE, - MIPS_INS_FCULT, - MIPS_INS_FCUNE, - MIPS_INS_FCUN, - MIPS_INS_FDIV, - MIPS_INS_FEXDO, - MIPS_INS_FEXP2, - MIPS_INS_FEXUPL, - MIPS_INS_FEXUPR, - MIPS_INS_FFINT_S, - MIPS_INS_FFINT_U, - MIPS_INS_FFQL, - MIPS_INS_FFQR, - MIPS_INS_FILL, - MIPS_INS_FLOG2, - MIPS_INS_FLOOR, - MIPS_INS_FMADD, - MIPS_INS_FMAX_A, - MIPS_INS_FMAX, - MIPS_INS_FMIN_A, - MIPS_INS_FMIN, - MIPS_INS_MOV, - MIPS_INS_FMSUB, - MIPS_INS_FMUL, - MIPS_INS_MUL, - MIPS_INS_NEG, - MIPS_INS_FRCP, - MIPS_INS_FRINT, - MIPS_INS_FRSQRT, - MIPS_INS_FSAF, - MIPS_INS_FSEQ, - MIPS_INS_FSLE, - MIPS_INS_FSLT, - MIPS_INS_FSNE, - MIPS_INS_FSOR, - MIPS_INS_FSQRT, - MIPS_INS_SQRT, - MIPS_INS_FSUB, - MIPS_INS_SUB, - MIPS_INS_FSUEQ, - MIPS_INS_FSULE, - MIPS_INS_FSULT, - MIPS_INS_FSUNE, - MIPS_INS_FSUN, - MIPS_INS_FTINT_S, - MIPS_INS_FTINT_U, - MIPS_INS_FTQ, - MIPS_INS_FTRUNC_S, - MIPS_INS_FTRUNC_U, - MIPS_INS_HADD_S, - MIPS_INS_HADD_U, - MIPS_INS_HSUB_S, - MIPS_INS_HSUB_U, - MIPS_INS_ILVEV, - MIPS_INS_ILVL, - MIPS_INS_ILVOD, - MIPS_INS_ILVR, + MIPS_INS_EXTW, + MIPS_INS_ABS_D, + MIPS_INS_ABS_S, + MIPS_INS_FADD_D, + MIPS_INS_ADD_D, + MIPS_INS_ADD_PS, + MIPS_INS_ADD_S, + MIPS_INS_FADD_W, + MIPS_INS_FCAF_D, + MIPS_INS_FCAF_W, + MIPS_INS_FCEQ_D, + MIPS_INS_FCEQ_W, + MIPS_INS_FCLASS_D, + MIPS_INS_FCLASS_W, + MIPS_INS_FCLE_D, + MIPS_INS_FCLE_W, + MIPS_INS_FCLT_D, + MIPS_INS_FCLT_W, + MIPS_INS_FCNE_D, + MIPS_INS_FCNE_W, + MIPS_INS_FCOR_D, + MIPS_INS_FCOR_W, + MIPS_INS_FCUEQ_D, + MIPS_INS_FCUEQ_W, + MIPS_INS_FCULE_D, + MIPS_INS_FCULE_W, + MIPS_INS_FCULT_D, + MIPS_INS_FCULT_W, + MIPS_INS_FCUNE_D, + MIPS_INS_FCUNE_W, + MIPS_INS_FCUN_D, + MIPS_INS_FCUN_W, + MIPS_INS_FDIV_D, + MIPS_INS_DIV_D, + MIPS_INS_DIV_S, + MIPS_INS_FDIV_W, + MIPS_INS_FEXDO_H, + MIPS_INS_FEXDO_W, + MIPS_INS_FEXP2_D, + MIPS_INS_FEXP2_W, + MIPS_INS_FEXUPL_D, + MIPS_INS_FEXUPL_W, + MIPS_INS_FEXUPR_D, + MIPS_INS_FEXUPR_W, + MIPS_INS_FFINT_S_D, + MIPS_INS_FFINT_S_W, + MIPS_INS_FFINT_U_D, + MIPS_INS_FFINT_U_W, + MIPS_INS_FFQL_D, + MIPS_INS_FFQL_W, + MIPS_INS_FFQR_D, + MIPS_INS_FFQR_W, + MIPS_INS_FILL_B, + MIPS_INS_FILL_D, + MIPS_INS_FILL_H, + MIPS_INS_FILL_W, + MIPS_INS_FLOG2_D, + MIPS_INS_FLOG2_W, + MIPS_INS_FLOOR_L_D, + MIPS_INS_FLOOR_L_S, + MIPS_INS_FLOOR_W_D, + MIPS_INS_FLOOR_W_S, + MIPS_INS_FMADD_D, + MIPS_INS_FMADD_W, + MIPS_INS_FMAX_A_D, + MIPS_INS_FMAX_A_W, + MIPS_INS_FMAX_D, + MIPS_INS_FMAX_W, + MIPS_INS_FMIN_A_D, + MIPS_INS_FMIN_A_W, + MIPS_INS_FMIN_D, + MIPS_INS_FMIN_W, + MIPS_INS_MOV_D, + MIPS_INS_MOV_S, + MIPS_INS_FMSUB_D, + MIPS_INS_FMSUB_W, + MIPS_INS_FMUL_D, + MIPS_INS_MUL_D, + MIPS_INS_MUL_PS, + MIPS_INS_MUL_S, + MIPS_INS_FMUL_W, + MIPS_INS_NEG_D, + MIPS_INS_NEG_S, + MIPS_INS_FORK, + MIPS_INS_FRCP_D, + MIPS_INS_FRCP_W, + MIPS_INS_FRINT_D, + MIPS_INS_FRINT_W, + MIPS_INS_FRSQRT_D, + MIPS_INS_FRSQRT_W, + MIPS_INS_FSAF_D, + MIPS_INS_FSAF_W, + MIPS_INS_FSEQ_D, + MIPS_INS_FSEQ_W, + MIPS_INS_FSLE_D, + MIPS_INS_FSLE_W, + MIPS_INS_FSLT_D, + MIPS_INS_FSLT_W, + MIPS_INS_FSNE_D, + MIPS_INS_FSNE_W, + MIPS_INS_FSOR_D, + MIPS_INS_FSOR_W, + MIPS_INS_FSQRT_D, + MIPS_INS_SQRT_D, + MIPS_INS_SQRT_S, + MIPS_INS_FSQRT_W, + MIPS_INS_FSUB_D, + MIPS_INS_SUB_D, + MIPS_INS_SUB_PS, + MIPS_INS_SUB_S, + MIPS_INS_FSUB_W, + MIPS_INS_FSUEQ_D, + MIPS_INS_FSUEQ_W, + MIPS_INS_FSULE_D, + MIPS_INS_FSULE_W, + MIPS_INS_FSULT_D, + MIPS_INS_FSULT_W, + MIPS_INS_FSUNE_D, + MIPS_INS_FSUNE_W, + MIPS_INS_FSUN_D, + MIPS_INS_FSUN_W, + MIPS_INS_FTINT_S_D, + MIPS_INS_FTINT_S_W, + MIPS_INS_FTINT_U_D, + MIPS_INS_FTINT_U_W, + MIPS_INS_FTQ_H, + MIPS_INS_FTQ_W, + MIPS_INS_FTRUNC_S_D, + MIPS_INS_FTRUNC_S_W, + MIPS_INS_FTRUNC_U_D, + MIPS_INS_FTRUNC_U_W, + MIPS_INS_GINVI, + MIPS_INS_GINVT, + MIPS_INS_HADD_S_D, + MIPS_INS_HADD_S_H, + MIPS_INS_HADD_S_W, + MIPS_INS_HADD_U_D, + MIPS_INS_HADD_U_H, + MIPS_INS_HADD_U_W, + MIPS_INS_HSUB_S_D, + MIPS_INS_HSUB_S_H, + MIPS_INS_HSUB_S_W, + MIPS_INS_HSUB_U_D, + MIPS_INS_HSUB_U_H, + MIPS_INS_HSUB_U_W, + MIPS_INS_HYPCALL, + MIPS_INS_ILVEV_B, + MIPS_INS_ILVEV_D, + MIPS_INS_ILVEV_H, + MIPS_INS_ILVEV_W, + MIPS_INS_ILVL_B, + MIPS_INS_ILVL_D, + MIPS_INS_ILVL_H, + MIPS_INS_ILVL_W, + MIPS_INS_ILVOD_B, + MIPS_INS_ILVOD_D, + MIPS_INS_ILVOD_H, + MIPS_INS_ILVOD_W, + MIPS_INS_ILVR_B, + MIPS_INS_ILVR_D, + MIPS_INS_ILVR_H, + MIPS_INS_ILVR_W, MIPS_INS_INS, - MIPS_INS_INSERT, + MIPS_INS_INSERT_B, + MIPS_INS_INSERT_D, + MIPS_INS_INSERT_H, + MIPS_INS_INSERT_W, MIPS_INS_INSV, - MIPS_INS_INSVE, + MIPS_INS_INSVE_B, + MIPS_INS_INSVE_D, + MIPS_INS_INSVE_H, + MIPS_INS_INSVE_W, MIPS_INS_J, - MIPS_INS_JAL, MIPS_INS_JALR, + MIPS_INS_JALRC, + MIPS_INS_JALRC_HB, MIPS_INS_JALRS16, MIPS_INS_JALRS, + MIPS_INS_JALR_HB, MIPS_INS_JALS, MIPS_INS_JALX, MIPS_INS_JIALC, @@ -606,96 +1500,198 @@ typedef enum mips_insn { MIPS_INS_JR16, MIPS_INS_JRADDIUSP, MIPS_INS_JRC, - MIPS_INS_JALRC, + MIPS_INS_JRC16, + MIPS_INS_JRCADDIUSP, + MIPS_INS_JR_HB, + MIPS_INS_LAPC_H, + MIPS_INS_LAPC_B, MIPS_INS_LB, + MIPS_INS_LBE, MIPS_INS_LBU16, - MIPS_INS_LBUX, MIPS_INS_LBU, - MIPS_INS_LD, + MIPS_INS_LBUX, + MIPS_INS_LBX, + MIPS_INS_LBUE, MIPS_INS_LDC1, MIPS_INS_LDC2, MIPS_INS_LDC3, - MIPS_INS_LDI, + MIPS_INS_LDI_B, + MIPS_INS_LDI_D, + MIPS_INS_LDI_H, + MIPS_INS_LDI_W, MIPS_INS_LDL, MIPS_INS_LDPC, MIPS_INS_LDR, MIPS_INS_LDXC1, + MIPS_INS_LD_B, + MIPS_INS_LD_D, + MIPS_INS_LD_H, + MIPS_INS_LD_W, MIPS_INS_LH, + MIPS_INS_LHE, MIPS_INS_LHU16, - MIPS_INS_LHX, MIPS_INS_LHU, + MIPS_INS_LHUXS, + MIPS_INS_LHUX, + MIPS_INS_LHX, + MIPS_INS_LHXS, + MIPS_INS_LHUE, MIPS_INS_LI16, MIPS_INS_LL, MIPS_INS_LLD, + MIPS_INS_LLE, + MIPS_INS_LLWP, MIPS_INS_LSA, - MIPS_INS_LUXC1, MIPS_INS_LUI, + MIPS_INS_LUXC1, MIPS_INS_LW, MIPS_INS_LW16, MIPS_INS_LWC1, MIPS_INS_LWC2, MIPS_INS_LWC3, + MIPS_INS_LWE, MIPS_INS_LWL, + MIPS_INS_LWLE, MIPS_INS_LWM16, MIPS_INS_LWM32, MIPS_INS_LWPC, MIPS_INS_LWP, MIPS_INS_LWR, + MIPS_INS_LWRE, MIPS_INS_LWUPC, MIPS_INS_LWU, MIPS_INS_LWX, MIPS_INS_LWXC1, MIPS_INS_LWXS, - MIPS_INS_LI, MIPS_INS_MADD, - MIPS_INS_MADDF, - MIPS_INS_MADDR_Q, + MIPS_INS_MADDF_D, + MIPS_INS_MADDF_S, + MIPS_INS_MADDR_Q_H, + MIPS_INS_MADDR_Q_W, MIPS_INS_MADDU, - MIPS_INS_MADDV, - MIPS_INS_MADD_Q, - MIPS_INS_MAQ_SA, - MIPS_INS_MAQ_S, - MIPS_INS_MAXA, - MIPS_INS_MAXI_S, - MIPS_INS_MAXI_U, - MIPS_INS_MAX_A, - MIPS_INS_MAX, + MIPS_INS_MADDV_B, + MIPS_INS_MADDV_D, + MIPS_INS_MADDV_H, + MIPS_INS_MADDV_W, + MIPS_INS_MADD_D, + MIPS_INS_MADD_Q_H, + MIPS_INS_MADD_Q_W, + MIPS_INS_MADD_S, + MIPS_INS_MAQ_SA_W_PHL, + MIPS_INS_MAQ_SA_W_PHR, + MIPS_INS_MAQ_S_W_PHL, + MIPS_INS_MAQ_S_W_PHR, + MIPS_INS_MAXA_D, + MIPS_INS_MAXA_S, + MIPS_INS_MAXI_S_B, + MIPS_INS_MAXI_S_D, + MIPS_INS_MAXI_S_H, + MIPS_INS_MAXI_S_W, + MIPS_INS_MAXI_U_B, + MIPS_INS_MAXI_U_D, + MIPS_INS_MAXI_U_H, + MIPS_INS_MAXI_U_W, + MIPS_INS_MAX_A_B, + MIPS_INS_MAX_A_D, + MIPS_INS_MAX_A_H, + MIPS_INS_MAX_A_W, + MIPS_INS_MAX_D, MIPS_INS_MAX_S, - MIPS_INS_MAX_U, + MIPS_INS_MAX_S_B, + MIPS_INS_MAX_S_D, + MIPS_INS_MAX_S_H, + MIPS_INS_MAX_S_W, + MIPS_INS_MAX_U_B, + MIPS_INS_MAX_U_D, + MIPS_INS_MAX_U_H, + MIPS_INS_MAX_U_W, MIPS_INS_MFC0, MIPS_INS_MFC1, MIPS_INS_MFC2, + MIPS_INS_MFGC0, + MIPS_INS_MFHC0, MIPS_INS_MFHC1, + MIPS_INS_MFHC2, + MIPS_INS_MFHGC0, MIPS_INS_MFHI, + MIPS_INS_MFHI16, MIPS_INS_MFLO, - MIPS_INS_MINA, - MIPS_INS_MINI_S, - MIPS_INS_MINI_U, - MIPS_INS_MIN_A, - MIPS_INS_MIN, + MIPS_INS_MFLO16, + MIPS_INS_MFTR, + MIPS_INS_MINA_D, + MIPS_INS_MINA_S, + MIPS_INS_MINI_S_B, + MIPS_INS_MINI_S_D, + MIPS_INS_MINI_S_H, + MIPS_INS_MINI_S_W, + MIPS_INS_MINI_U_B, + MIPS_INS_MINI_U_D, + MIPS_INS_MINI_U_H, + MIPS_INS_MINI_U_W, + MIPS_INS_MIN_A_B, + MIPS_INS_MIN_A_D, + MIPS_INS_MIN_A_H, + MIPS_INS_MIN_A_W, + MIPS_INS_MIN_D, MIPS_INS_MIN_S, - MIPS_INS_MIN_U, + MIPS_INS_MIN_S_B, + MIPS_INS_MIN_S_D, + MIPS_INS_MIN_S_H, + MIPS_INS_MIN_S_W, + MIPS_INS_MIN_U_B, + MIPS_INS_MIN_U_D, + MIPS_INS_MIN_U_H, + MIPS_INS_MIN_U_W, MIPS_INS_MOD, MIPS_INS_MODSUB, MIPS_INS_MODU, - MIPS_INS_MOD_S, - MIPS_INS_MOD_U, + MIPS_INS_MOD_S_B, + MIPS_INS_MOD_S_D, + MIPS_INS_MOD_S_H, + MIPS_INS_MOD_S_W, + MIPS_INS_MOD_U_B, + MIPS_INS_MOD_U_D, + MIPS_INS_MOD_U_H, + MIPS_INS_MOD_U_W, MIPS_INS_MOVE, + MIPS_INS_MOVE16, + MIPS_INS_MOVE_BALC, MIPS_INS_MOVEP, + MIPS_INS_MOVE_V, + MIPS_INS_MOVF_D, MIPS_INS_MOVF, + MIPS_INS_MOVF_S, + MIPS_INS_MOVN_D, MIPS_INS_MOVN, + MIPS_INS_MOVN_S, + MIPS_INS_MOVT_D, MIPS_INS_MOVT, + MIPS_INS_MOVT_S, + MIPS_INS_MOVZ_D, MIPS_INS_MOVZ, + MIPS_INS_MOVZ_S, MIPS_INS_MSUB, - MIPS_INS_MSUBF, - MIPS_INS_MSUBR_Q, + MIPS_INS_MSUBF_D, + MIPS_INS_MSUBF_S, + MIPS_INS_MSUBR_Q_H, + MIPS_INS_MSUBR_Q_W, MIPS_INS_MSUBU, - MIPS_INS_MSUBV, - MIPS_INS_MSUB_Q, + MIPS_INS_MSUBV_B, + MIPS_INS_MSUBV_D, + MIPS_INS_MSUBV_H, + MIPS_INS_MSUBV_W, + MIPS_INS_MSUB_D, + MIPS_INS_MSUB_Q_H, + MIPS_INS_MSUB_Q_W, + MIPS_INS_MSUB_S, MIPS_INS_MTC0, MIPS_INS_MTC1, MIPS_INS_MTC2, + MIPS_INS_MTGC0, + MIPS_INS_MTHC0, MIPS_INS_MTHC1, + MIPS_INS_MTHC2, + MIPS_INS_MTHGC0, MIPS_INS_MTHI, MIPS_INS_MTHLIP, MIPS_INS_MTLO, @@ -705,66 +1701,139 @@ typedef enum mips_insn { MIPS_INS_MTP0, MIPS_INS_MTP1, MIPS_INS_MTP2, + MIPS_INS_MTTR, MIPS_INS_MUH, MIPS_INS_MUHU, - MIPS_INS_MULEQ_S, - MIPS_INS_MULEU_S, - MIPS_INS_MULQ_RS, - MIPS_INS_MULQ_S, - MIPS_INS_MULR_Q, - MIPS_INS_MULSAQ_S, - MIPS_INS_MULSA, + MIPS_INS_MULEQ_S_W_PHL, + MIPS_INS_MULEQ_S_W_PHR, + MIPS_INS_MULEU_S_PH_QBL, + MIPS_INS_MULEU_S_PH_QBR, + MIPS_INS_MULQ_RS_PH, + MIPS_INS_MULQ_RS_W, + MIPS_INS_MULQ_S_PH, + MIPS_INS_MULQ_S_W, + MIPS_INS_MULR_PS, + MIPS_INS_MULR_Q_H, + MIPS_INS_MULR_Q_W, + MIPS_INS_MULSAQ_S_W_PH, + MIPS_INS_MULSA_W_PH, MIPS_INS_MULT, MIPS_INS_MULTU, MIPS_INS_MULU, - MIPS_INS_MULV, - MIPS_INS_MUL_Q, - MIPS_INS_MUL_S, - MIPS_INS_NLOC, - MIPS_INS_NLZC, - MIPS_INS_NMADD, - MIPS_INS_NMSUB, - MIPS_INS_NOR, - MIPS_INS_NORI, + MIPS_INS_MULV_B, + MIPS_INS_MULV_D, + MIPS_INS_MULV_H, + MIPS_INS_MULV_W, + MIPS_INS_MUL_PH, + MIPS_INS_MUL_Q_H, + MIPS_INS_MUL_Q_W, + MIPS_INS_MUL_S_PH, + MIPS_INS_NLOC_B, + MIPS_INS_NLOC_D, + MIPS_INS_NLOC_H, + MIPS_INS_NLOC_W, + MIPS_INS_NLZC_B, + MIPS_INS_NLZC_D, + MIPS_INS_NLZC_H, + MIPS_INS_NLZC_W, + MIPS_INS_NMADD_D, + MIPS_INS_NMADD_S, + MIPS_INS_NMSUB_D, + MIPS_INS_NMSUB_S, + MIPS_INS_NOP32, + MIPS_INS_NOP, + MIPS_INS_NORI_B, + MIPS_INS_NOR_V, MIPS_INS_NOT16, MIPS_INS_NOT, + MIPS_INS_NEG, MIPS_INS_OR, MIPS_INS_OR16, + MIPS_INS_ORI_B, MIPS_INS_ORI, - MIPS_INS_PACKRL, + MIPS_INS_OR_V, + MIPS_INS_PACKRL_PH, MIPS_INS_PAUSE, - MIPS_INS_PCKEV, - MIPS_INS_PCKOD, - MIPS_INS_PCNT, - MIPS_INS_PICK, + MIPS_INS_PCKEV_B, + MIPS_INS_PCKEV_D, + MIPS_INS_PCKEV_H, + MIPS_INS_PCKEV_W, + MIPS_INS_PCKOD_B, + MIPS_INS_PCKOD_D, + MIPS_INS_PCKOD_H, + MIPS_INS_PCKOD_W, + MIPS_INS_PCNT_B, + MIPS_INS_PCNT_D, + MIPS_INS_PCNT_H, + MIPS_INS_PCNT_W, + MIPS_INS_PICK_PH, + MIPS_INS_PICK_QB, + MIPS_INS_PLL_PS, + MIPS_INS_PLU_PS, MIPS_INS_POP, - MIPS_INS_PRECEQU, - MIPS_INS_PRECEQ, - MIPS_INS_PRECEU, - MIPS_INS_PRECRQU_S, - MIPS_INS_PRECRQ, - MIPS_INS_PRECRQ_RS, - MIPS_INS_PRECR, - MIPS_INS_PRECR_SRA, - MIPS_INS_PRECR_SRA_R, + MIPS_INS_PRECEQU_PH_QBL, + MIPS_INS_PRECEQU_PH_QBLA, + MIPS_INS_PRECEQU_PH_QBR, + MIPS_INS_PRECEQU_PH_QBRA, + MIPS_INS_PRECEQ_W_PHL, + MIPS_INS_PRECEQ_W_PHR, + MIPS_INS_PRECEU_PH_QBL, + MIPS_INS_PRECEU_PH_QBLA, + MIPS_INS_PRECEU_PH_QBR, + MIPS_INS_PRECEU_PH_QBRA, + MIPS_INS_PRECRQU_S_QB_PH, + MIPS_INS_PRECRQ_PH_W, + MIPS_INS_PRECRQ_QB_PH, + MIPS_INS_PRECRQ_RS_PH_W, + MIPS_INS_PRECR_QB_PH, + MIPS_INS_PRECR_SRA_PH_W, + MIPS_INS_PRECR_SRA_R_PH_W, MIPS_INS_PREF, + MIPS_INS_PREFE, + MIPS_INS_PREFX, MIPS_INS_PREPEND, - MIPS_INS_RADDU, + MIPS_INS_PUL_PS, + MIPS_INS_PUU_PS, + MIPS_INS_RADDU_W_QB, MIPS_INS_RDDSP, MIPS_INS_RDHWR, - MIPS_INS_REPLV, - MIPS_INS_REPL, - MIPS_INS_RINT, + MIPS_INS_RDPGPR, + MIPS_INS_RECIP_D, + MIPS_INS_RECIP_S, + MIPS_INS_REPLV_PH, + MIPS_INS_REPLV_QB, + MIPS_INS_REPL_PH, + MIPS_INS_REPL_QB, + MIPS_INS_RESTORE_JRC, + MIPS_INS_RESTORE, + MIPS_INS_RINT_D, + MIPS_INS_RINT_S, MIPS_INS_ROTR, MIPS_INS_ROTRV, - MIPS_INS_ROUND, - MIPS_INS_SAT_S, - MIPS_INS_SAT_U, + MIPS_INS_ROTX, + MIPS_INS_ROUND_L_D, + MIPS_INS_ROUND_L_S, + MIPS_INS_ROUND_W_D, + MIPS_INS_ROUND_W_S, + MIPS_INS_RSQRT_D, + MIPS_INS_RSQRT_S, + MIPS_INS_SAT_S_B, + MIPS_INS_SAT_S_D, + MIPS_INS_SAT_S_H, + MIPS_INS_SAT_S_W, + MIPS_INS_SAT_U_B, + MIPS_INS_SAT_U_D, + MIPS_INS_SAT_U_H, + MIPS_INS_SAT_U_W, + MIPS_INS_SAVE, MIPS_INS_SB, MIPS_INS_SB16, + MIPS_INS_SBE, + MIPS_INS_SBX, MIPS_INS_SC, MIPS_INS_SCD, - MIPS_INS_SD, + MIPS_INS_SCE, + MIPS_INS_SCWP, MIPS_INS_SDBBP, MIPS_INS_SDBBP16, MIPS_INS_SDC1, @@ -776,79 +1845,178 @@ typedef enum mips_insn { MIPS_INS_SEB, MIPS_INS_SEH, MIPS_INS_SELEQZ, + MIPS_INS_SELEQZ_D, + MIPS_INS_SELEQZ_S, MIPS_INS_SELNEZ, - MIPS_INS_SEL, - MIPS_INS_SEQ, + MIPS_INS_SELNEZ_D, + MIPS_INS_SELNEZ_S, + MIPS_INS_SEL_D, + MIPS_INS_SEL_S, MIPS_INS_SEQI, MIPS_INS_SH, MIPS_INS_SH16, - MIPS_INS_SHF, + MIPS_INS_SHE, + MIPS_INS_SHF_B, + MIPS_INS_SHF_H, + MIPS_INS_SHF_W, MIPS_INS_SHILO, MIPS_INS_SHILOV, - MIPS_INS_SHLLV, - MIPS_INS_SHLLV_S, - MIPS_INS_SHLL, - MIPS_INS_SHLL_S, - MIPS_INS_SHRAV, - MIPS_INS_SHRAV_R, - MIPS_INS_SHRA, - MIPS_INS_SHRA_R, - MIPS_INS_SHRLV, - MIPS_INS_SHRL, - MIPS_INS_SLDI, - MIPS_INS_SLD, + MIPS_INS_SHLLV_PH, + MIPS_INS_SHLLV_QB, + MIPS_INS_SHLLV_S_PH, + MIPS_INS_SHLLV_S_W, + MIPS_INS_SHLL_PH, + MIPS_INS_SHLL_QB, + MIPS_INS_SHLL_S_PH, + MIPS_INS_SHLL_S_W, + MIPS_INS_SHRAV_PH, + MIPS_INS_SHRAV_QB, + MIPS_INS_SHRAV_R_PH, + MIPS_INS_SHRAV_R_QB, + MIPS_INS_SHRAV_R_W, + MIPS_INS_SHRA_PH, + MIPS_INS_SHRA_QB, + MIPS_INS_SHRA_R_PH, + MIPS_INS_SHRA_R_QB, + MIPS_INS_SHRA_R_W, + MIPS_INS_SHRLV_PH, + MIPS_INS_SHRLV_QB, + MIPS_INS_SHRL_PH, + MIPS_INS_SHRL_QB, + MIPS_INS_SHXS, + MIPS_INS_SHX, + MIPS_INS_SIGRIE, + MIPS_INS_SLDI_B, + MIPS_INS_SLDI_D, + MIPS_INS_SLDI_H, + MIPS_INS_SLDI_W, + MIPS_INS_SLD_B, + MIPS_INS_SLD_D, + MIPS_INS_SLD_H, + MIPS_INS_SLD_W, MIPS_INS_SLL, MIPS_INS_SLL16, - MIPS_INS_SLLI, + MIPS_INS_SLLI_B, + MIPS_INS_SLLI_D, + MIPS_INS_SLLI_H, + MIPS_INS_SLLI_W, MIPS_INS_SLLV, - MIPS_INS_SLT, - MIPS_INS_SLTI, + MIPS_INS_SLL_B, + MIPS_INS_SLL_D, + MIPS_INS_SLL_H, + MIPS_INS_SLL_W, MIPS_INS_SLTIU, - MIPS_INS_SLTU, - MIPS_INS_SNE, + MIPS_INS_SLTI, MIPS_INS_SNEI, - MIPS_INS_SPLATI, - MIPS_INS_SPLAT, + MIPS_INS_SOV, + MIPS_INS_SPLATI_B, + MIPS_INS_SPLATI_D, + MIPS_INS_SPLATI_H, + MIPS_INS_SPLATI_W, + MIPS_INS_SPLAT_B, + MIPS_INS_SPLAT_D, + MIPS_INS_SPLAT_H, + MIPS_INS_SPLAT_W, MIPS_INS_SRA, - MIPS_INS_SRAI, - MIPS_INS_SRARI, - MIPS_INS_SRAR, + MIPS_INS_SRAI_B, + MIPS_INS_SRAI_D, + MIPS_INS_SRAI_H, + MIPS_INS_SRAI_W, + MIPS_INS_SRARI_B, + MIPS_INS_SRARI_D, + MIPS_INS_SRARI_H, + MIPS_INS_SRARI_W, + MIPS_INS_SRAR_B, + MIPS_INS_SRAR_D, + MIPS_INS_SRAR_H, + MIPS_INS_SRAR_W, MIPS_INS_SRAV, + MIPS_INS_SRA_B, + MIPS_INS_SRA_D, + MIPS_INS_SRA_H, + MIPS_INS_SRA_W, MIPS_INS_SRL, MIPS_INS_SRL16, - MIPS_INS_SRLI, - MIPS_INS_SRLRI, - MIPS_INS_SRLR, + MIPS_INS_SRLI_B, + MIPS_INS_SRLI_D, + MIPS_INS_SRLI_H, + MIPS_INS_SRLI_W, + MIPS_INS_SRLRI_B, + MIPS_INS_SRLRI_D, + MIPS_INS_SRLRI_H, + MIPS_INS_SRLRI_W, + MIPS_INS_SRLR_B, + MIPS_INS_SRLR_D, + MIPS_INS_SRLR_H, + MIPS_INS_SRLR_W, MIPS_INS_SRLV, + MIPS_INS_SRL_B, + MIPS_INS_SRL_D, + MIPS_INS_SRL_H, + MIPS_INS_SRL_W, MIPS_INS_SSNOP, - MIPS_INS_ST, - MIPS_INS_SUBQH, - MIPS_INS_SUBQH_R, - MIPS_INS_SUBQ, - MIPS_INS_SUBQ_S, - MIPS_INS_SUBSUS_U, - MIPS_INS_SUBSUU_S, - MIPS_INS_SUBS_S, - MIPS_INS_SUBS_U, + MIPS_INS_ST_B, + MIPS_INS_ST_D, + MIPS_INS_ST_H, + MIPS_INS_ST_W, + MIPS_INS_SUB, + MIPS_INS_SUBQH_PH, + MIPS_INS_SUBQH_R_PH, + MIPS_INS_SUBQH_R_W, + MIPS_INS_SUBQH_W, + MIPS_INS_SUBQ_PH, + MIPS_INS_SUBQ_S_PH, + MIPS_INS_SUBQ_S_W, + MIPS_INS_SUBSUS_U_B, + MIPS_INS_SUBSUS_U_D, + MIPS_INS_SUBSUS_U_H, + MIPS_INS_SUBSUS_U_W, + MIPS_INS_SUBSUU_S_B, + MIPS_INS_SUBSUU_S_D, + MIPS_INS_SUBSUU_S_H, + MIPS_INS_SUBSUU_S_W, + MIPS_INS_SUBS_S_B, + MIPS_INS_SUBS_S_D, + MIPS_INS_SUBS_S_H, + MIPS_INS_SUBS_S_W, + MIPS_INS_SUBS_U_B, + MIPS_INS_SUBS_U_D, + MIPS_INS_SUBS_U_H, + MIPS_INS_SUBS_U_W, MIPS_INS_SUBU16, - MIPS_INS_SUBUH, - MIPS_INS_SUBUH_R, - MIPS_INS_SUBU, - MIPS_INS_SUBU_S, - MIPS_INS_SUBVI, - MIPS_INS_SUBV, + MIPS_INS_SUBUH_QB, + MIPS_INS_SUBUH_R_QB, + MIPS_INS_SUBU_PH, + MIPS_INS_SUBU_QB, + MIPS_INS_SUBU_S_PH, + MIPS_INS_SUBU_S_QB, + MIPS_INS_SUBVI_B, + MIPS_INS_SUBVI_D, + MIPS_INS_SUBVI_H, + MIPS_INS_SUBVI_W, + MIPS_INS_SUBV_B, + MIPS_INS_SUBV_D, + MIPS_INS_SUBV_H, + MIPS_INS_SUBV_W, MIPS_INS_SUXC1, MIPS_INS_SW, MIPS_INS_SW16, MIPS_INS_SWC1, MIPS_INS_SWC2, MIPS_INS_SWC3, + MIPS_INS_SWE, MIPS_INS_SWL, + MIPS_INS_SWLE, MIPS_INS_SWM16, MIPS_INS_SWM32, + MIPS_INS_SWPC, MIPS_INS_SWP, MIPS_INS_SWR, + MIPS_INS_SWRE, + MIPS_INS_SWSP, MIPS_INS_SWXC1, + MIPS_INS_SWXS, + MIPS_INS_SWX, MIPS_INS_SYNC, MIPS_INS_SYNCI, MIPS_INS_SYSCALL, @@ -858,6 +2026,14 @@ typedef enum mips_insn { MIPS_INS_TGEI, MIPS_INS_TGEIU, MIPS_INS_TGEU, + MIPS_INS_TLBGINV, + MIPS_INS_TLBGINVF, + MIPS_INS_TLBGP, + MIPS_INS_TLBGR, + MIPS_INS_TLBGWI, + MIPS_INS_TLBGWR, + MIPS_INS_TLBINV, + MIPS_INS_TLBINVF, MIPS_INS_TLBP, MIPS_INS_TLBR, MIPS_INS_TLBWI, @@ -868,27 +2044,150 @@ typedef enum mips_insn { MIPS_INS_TLTU, MIPS_INS_TNE, MIPS_INS_TNEI, - MIPS_INS_TRUNC, + MIPS_INS_TRUNC_L_D, + MIPS_INS_TRUNC_L_S, + MIPS_INS_UALH, + MIPS_INS_UALWM, + MIPS_INS_UALW, + MIPS_INS_UASH, + MIPS_INS_UASWM, + MIPS_INS_UASW, MIPS_INS_V3MULU, MIPS_INS_VMM0, MIPS_INS_VMULU, - MIPS_INS_VSHF, + MIPS_INS_VSHF_B, + MIPS_INS_VSHF_D, + MIPS_INS_VSHF_H, + MIPS_INS_VSHF_W, MIPS_INS_WAIT, MIPS_INS_WRDSP, + MIPS_INS_WRPGPR, MIPS_INS_WSBH, MIPS_INS_XOR, MIPS_INS_XOR16, + MIPS_INS_XORI_B, MIPS_INS_XORI, + MIPS_INS_XOR_V, + MIPS_INS_YIELD, - //> some alias instructions - MIPS_INS_NOP, - MIPS_INS_NEGU, - - //> special instructions - MIPS_INS_JALR_HB, // jump and link with Hazard Barrier - MIPS_INS_JR_HB, // jump register with Hazard Barrier - + // clang-format on + // generated content end MIPS_INS_ENDING, + + MIPS_INS_ALIAS_BEGIN, + // generated content begin + // clang-format off + + MIPS_INS_ALIAS_ADDIU_B32, // Real instr.: MIPS_ADDIUGP48_NM + MIPS_INS_ALIAS_BITREVB, // Real instr.: MIPS_ROTX_NM + MIPS_INS_ALIAS_BITREVH, // Real instr.: MIPS_ROTX_NM + MIPS_INS_ALIAS_BYTEREVH, // Real instr.: MIPS_ROTX_NM + MIPS_INS_ALIAS_NOT, // Real instr.: MIPS_NOR_NM + MIPS_INS_ALIAS_RESTORE_JRC, // Real instr.: MIPS_RESTOREJRC16_NM + MIPS_INS_ALIAS_RESTORE, // Real instr.: MIPS_RESTORE_NM + MIPS_INS_ALIAS_SAVE, // Real instr.: MIPS_SAVE16_NM + MIPS_INS_ALIAS_MOVE, // Real instr.: MIPS_OR + MIPS_INS_ALIAS_BAL, // Real instr.: MIPS_BGEZAL + MIPS_INS_ALIAS_JALR_HB, // Real instr.: MIPS_JALR_HB + MIPS_INS_ALIAS_NEG, // Real instr.: MIPS_SUB + MIPS_INS_ALIAS_NEGU, // Real instr.: MIPS_SUBu + MIPS_INS_ALIAS_NOP, // Real instr.: MIPS_SLL + MIPS_INS_ALIAS_BNEZL, // Real instr.: MIPS_BNEL + MIPS_INS_ALIAS_BEQZL, // Real instr.: MIPS_BEQL + MIPS_INS_ALIAS_SYSCALL, // Real instr.: MIPS_SYSCALL + MIPS_INS_ALIAS_BREAK, // Real instr.: MIPS_BREAK + MIPS_INS_ALIAS_EI, // Real instr.: MIPS_EI + MIPS_INS_ALIAS_DI, // Real instr.: MIPS_DI + MIPS_INS_ALIAS_TEQ, // Real instr.: MIPS_TEQ + MIPS_INS_ALIAS_TGE, // Real instr.: MIPS_TGE + MIPS_INS_ALIAS_TGEU, // Real instr.: MIPS_TGEU + MIPS_INS_ALIAS_TLT, // Real instr.: MIPS_TLT + MIPS_INS_ALIAS_TLTU, // Real instr.: MIPS_TLTU + MIPS_INS_ALIAS_TNE, // Real instr.: MIPS_TNE + MIPS_INS_ALIAS_RDHWR, // Real instr.: MIPS_RDHWR + MIPS_INS_ALIAS_SDBBP, // Real instr.: MIPS_SDBBP + MIPS_INS_ALIAS_SYNC, // Real instr.: MIPS_SYNC + MIPS_INS_ALIAS_HYPCALL, // Real instr.: MIPS_HYPCALL + MIPS_INS_ALIAS_NOR, // Real instr.: MIPS_NORImm + MIPS_INS_ALIAS_C_F_S, // Real instr.: MIPS_C_F_S + MIPS_INS_ALIAS_C_UN_S, // Real instr.: MIPS_C_UN_S + MIPS_INS_ALIAS_C_EQ_S, // Real instr.: MIPS_C_EQ_S + MIPS_INS_ALIAS_C_UEQ_S, // Real instr.: MIPS_C_UEQ_S + MIPS_INS_ALIAS_C_OLT_S, // Real instr.: MIPS_C_OLT_S + MIPS_INS_ALIAS_C_ULT_S, // Real instr.: MIPS_C_ULT_S + MIPS_INS_ALIAS_C_OLE_S, // Real instr.: MIPS_C_OLE_S + MIPS_INS_ALIAS_C_ULE_S, // Real instr.: MIPS_C_ULE_S + MIPS_INS_ALIAS_C_SF_S, // Real instr.: MIPS_C_SF_S + MIPS_INS_ALIAS_C_NGLE_S, // Real instr.: MIPS_C_NGLE_S + MIPS_INS_ALIAS_C_SEQ_S, // Real instr.: MIPS_C_SEQ_S + MIPS_INS_ALIAS_C_NGL_S, // Real instr.: MIPS_C_NGL_S + MIPS_INS_ALIAS_C_LT_S, // Real instr.: MIPS_C_LT_S + MIPS_INS_ALIAS_C_NGE_S, // Real instr.: MIPS_C_NGE_S + MIPS_INS_ALIAS_C_LE_S, // Real instr.: MIPS_C_LE_S + MIPS_INS_ALIAS_C_NGT_S, // Real instr.: MIPS_C_NGT_S + MIPS_INS_ALIAS_BC1T, // Real instr.: MIPS_BC1T + MIPS_INS_ALIAS_BC1F, // Real instr.: MIPS_BC1F + MIPS_INS_ALIAS_C_F_D, // Real instr.: MIPS_C_F_D32 + MIPS_INS_ALIAS_C_UN_D, // Real instr.: MIPS_C_UN_D32 + MIPS_INS_ALIAS_C_EQ_D, // Real instr.: MIPS_C_EQ_D32 + MIPS_INS_ALIAS_C_UEQ_D, // Real instr.: MIPS_C_UEQ_D32 + MIPS_INS_ALIAS_C_OLT_D, // Real instr.: MIPS_C_OLT_D32 + MIPS_INS_ALIAS_C_ULT_D, // Real instr.: MIPS_C_ULT_D32 + MIPS_INS_ALIAS_C_OLE_D, // Real instr.: MIPS_C_OLE_D32 + MIPS_INS_ALIAS_C_ULE_D, // Real instr.: MIPS_C_ULE_D32 + MIPS_INS_ALIAS_C_SF_D, // Real instr.: MIPS_C_SF_D32 + MIPS_INS_ALIAS_C_NGLE_D, // Real instr.: MIPS_C_NGLE_D32 + MIPS_INS_ALIAS_C_SEQ_D, // Real instr.: MIPS_C_SEQ_D32 + MIPS_INS_ALIAS_C_NGL_D, // Real instr.: MIPS_C_NGL_D32 + MIPS_INS_ALIAS_C_LT_D, // Real instr.: MIPS_C_LT_D32 + MIPS_INS_ALIAS_C_NGE_D, // Real instr.: MIPS_C_NGE_D32 + MIPS_INS_ALIAS_C_LE_D, // Real instr.: MIPS_C_LE_D32 + MIPS_INS_ALIAS_C_NGT_D, // Real instr.: MIPS_C_NGT_D32 + MIPS_INS_ALIAS_BC1TL, // Real instr.: MIPS_BC1TL + MIPS_INS_ALIAS_BC1FL, // Real instr.: MIPS_BC1FL + MIPS_INS_ALIAS_DNEG, // Real instr.: MIPS_DSUB + MIPS_INS_ALIAS_DNEGU, // Real instr.: MIPS_DSUBu + MIPS_INS_ALIAS_SLT, // Real instr.: MIPS_SLTImm64 + MIPS_INS_ALIAS_SLTU, // Real instr.: MIPS_SLTUImm64 + MIPS_INS_ALIAS_SIGRIE, // Real instr.: MIPS_SIGRIE + MIPS_INS_ALIAS_JR, // Real instr.: MIPS_JALR + MIPS_INS_ALIAS_JRC, // Real instr.: MIPS_JIC + MIPS_INS_ALIAS_JALRC, // Real instr.: MIPS_JIALC + MIPS_INS_ALIAS_DIV, // Real instr.: MIPS_DIV + MIPS_INS_ALIAS_DIVU, // Real instr.: MIPS_DIVU + MIPS_INS_ALIAS_LAPC, // Real instr.: MIPS_ADDIUPC + MIPS_INS_ALIAS_WRDSP, // Real instr.: MIPS_WRDSP + MIPS_INS_ALIAS_WAIT, // Real instr.: MIPS_WAIT_MM + MIPS_INS_ALIAS_SW, // Real instr.: MIPS_SWSP_MM + MIPS_INS_ALIAS_JALRC_HB, // Real instr.: MIPS_JALRC_HB_MMR6 + MIPS_INS_ALIAS_ADDIU_B, // Real instr.: MIPS_ADDIUGPB_NM + MIPS_INS_ALIAS_ADDIU_W, // Real instr.: MIPS_ADDIUGPW_NM + MIPS_INS_ALIAS_JRC_HB, // Real instr.: MIPS_JALRCHB_NM + MIPS_INS_ALIAS_BEQC, // Real instr.: MIPS_BEQC16_NM + MIPS_INS_ALIAS_BNEC, // Real instr.: MIPS_BNEC16_NM + MIPS_INS_ALIAS_BEQZC, // Real instr.: MIPS_BEQC_NM + MIPS_INS_ALIAS_BNEZC, // Real instr.: MIPS_BNEC_NM + MIPS_INS_ALIAS_MFC0, // Real instr.: MIPS_MFC0_NM + MIPS_INS_ALIAS_MFHC0, // Real instr.: MIPS_MFHC0_NM + MIPS_INS_ALIAS_MTC0, // Real instr.: MIPS_MTC0_NM + MIPS_INS_ALIAS_MTHC0, // Real instr.: MIPS_MTHC0_NM + MIPS_INS_ALIAS_DMT, // Real instr.: MIPS_DMT + MIPS_INS_ALIAS_EMT, // Real instr.: MIPS_EMT + MIPS_INS_ALIAS_DVPE, // Real instr.: MIPS_DVPE + MIPS_INS_ALIAS_EVPE, // Real instr.: MIPS_EVPE + MIPS_INS_ALIAS_YIELD, // Real instr.: MIPS_YIELD + MIPS_INS_ALIAS_MFTC0, // Real instr.: MIPS_MFTC0 + MIPS_INS_ALIAS_MFTLO, // Real instr.: MIPS_MFTLO + MIPS_INS_ALIAS_MFTHI, // Real instr.: MIPS_MFTHI + MIPS_INS_ALIAS_MFTACX, // Real instr.: MIPS_MFTACX + MIPS_INS_ALIAS_MTTC0, // Real instr.: MIPS_MTTC0 + MIPS_INS_ALIAS_MTTLO, // Real instr.: MIPS_MTTLO + MIPS_INS_ALIAS_MTTHI, // Real instr.: MIPS_MTTHI + MIPS_INS_ALIAS_MTTACX, // Real instr.: MIPS_MTTACX + + // clang-format on + // generated content end + MIPS_INS_ALIAS_END, } mips_insn; /// Group of MIPS instructions @@ -912,39 +2211,68 @@ typedef enum mips_insn_group { MIPS_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE // Architecture-specific groups - MIPS_GRP_BITCOUNT = 128, - MIPS_GRP_DSP, - MIPS_GRP_DSPR2, - MIPS_GRP_FPIDX, - MIPS_GRP_MSA, - MIPS_GRP_MIPS32R2, - MIPS_GRP_MIPS64, - MIPS_GRP_MIPS64R2, - MIPS_GRP_SEINREG, - MIPS_GRP_STDENC, - MIPS_GRP_SWAP, - MIPS_GRP_MICROMIPS, - MIPS_GRP_MIPS16MODE, - MIPS_GRP_FP64BIT, - MIPS_GRP_NONANSFPMATH, - MIPS_GRP_NOTFP64BIT, - MIPS_GRP_NOTINMICROMIPS, - MIPS_GRP_NOTNACL, - MIPS_GRP_NOTMIPS32R6, - MIPS_GRP_NOTMIPS64R6, - MIPS_GRP_CNMIPS, - MIPS_GRP_MIPS32, - MIPS_GRP_MIPS32R6, - MIPS_GRP_MIPS64R6, - MIPS_GRP_MIPS2, - MIPS_GRP_MIPS3, - MIPS_GRP_MIPS3_32, - MIPS_GRP_MIPS3_32R2, - MIPS_GRP_MIPS4_32, - MIPS_GRP_MIPS4_32R2, - MIPS_GRP_MIPS5_32R2, - MIPS_GRP_GP32BIT, - MIPS_GRP_GP64BIT, + // generated content begin + // clang-format off + + MIPS_FEATURE_HASMIPS2 = 128, + MIPS_FEATURE_HASMIPS3_32, + MIPS_FEATURE_HASMIPS3_32R2, + MIPS_FEATURE_HASMIPS3, + MIPS_FEATURE_NOTMIPS3, + MIPS_FEATURE_HASMIPS4_32, + MIPS_FEATURE_NOTMIPS4_32, + MIPS_FEATURE_HASMIPS4_32R2, + MIPS_FEATURE_HASMIPS5_32R2, + MIPS_FEATURE_HASMIPS32, + MIPS_FEATURE_HASMIPS32R2, + MIPS_FEATURE_HASMIPS32R5, + MIPS_FEATURE_HASMIPS32R6, + MIPS_FEATURE_NOTMIPS32R6, + MIPS_FEATURE_HASNANOMIPS, + MIPS_FEATURE_NOTNANOMIPS, + MIPS_FEATURE_ISGP64BIT, + MIPS_FEATURE_ISGP32BIT, + MIPS_FEATURE_ISPTR64BIT, + MIPS_FEATURE_ISPTR32BIT, + MIPS_FEATURE_HASMIPS64, + MIPS_FEATURE_NOTMIPS64, + MIPS_FEATURE_HASMIPS64R2, + MIPS_FEATURE_HASMIPS64R5, + MIPS_FEATURE_HASMIPS64R6, + MIPS_FEATURE_NOTMIPS64R6, + MIPS_FEATURE_INMIPS16MODE, + MIPS_FEATURE_NOTINMIPS16MODE, + MIPS_FEATURE_HASCNMIPS, + MIPS_FEATURE_NOTCNMIPS, + MIPS_FEATURE_HASCNMIPSP, + MIPS_FEATURE_NOTCNMIPSP, + MIPS_FEATURE_ISSYM32, + MIPS_FEATURE_ISSYM64, + MIPS_FEATURE_HASSTDENC, + MIPS_FEATURE_INMICROMIPS, + MIPS_FEATURE_NOTINMICROMIPS, + MIPS_FEATURE_HASEVA, + MIPS_FEATURE_HASMSA, + MIPS_FEATURE_HASMADD4, + MIPS_FEATURE_HASMT, + MIPS_FEATURE_USEINDIRECTJUMPSHAZARD, + MIPS_FEATURE_NOINDIRECTJUMPGUARDS, + MIPS_FEATURE_HASCRC, + MIPS_FEATURE_HASVIRT, + MIPS_FEATURE_HASGINV, + MIPS_FEATURE_HASTLB, + MIPS_FEATURE_ISFP64BIT, + MIPS_FEATURE_NOTFP64BIT, + MIPS_FEATURE_ISSINGLEFLOAT, + MIPS_FEATURE_ISNOTSINGLEFLOAT, + MIPS_FEATURE_ISNOTSOFTFLOAT, + MIPS_FEATURE_HASMIPS3D, + MIPS_FEATURE_HASDSP, + MIPS_FEATURE_HASDSPR2, + MIPS_FEATURE_HASDSPR3, + + // clang-format on + // generated content end MIPS_GRP_ENDING, } mips_insn_group; diff --git a/suite/MC/Mips/micromips-alu-instructions-EB.s.cs b/suite/MC/Mips/micromips-alu-instructions-EB.s.cs index f4dbe7a8c..67c00277d 100644 --- a/suite/MC/Mips/micromips-alu-instructions-EB.s.cs +++ b/suite/MC/Mips/micromips-alu-instructions-EB.s.cs @@ -7,8 +7,8 @@ 0x00,0xe6,0x49,0x50 = addu $t1, $a2, $a3 0x00,0xe6,0x49,0x90 = sub $t1, $a2, $a3 0x00,0xa3,0x21,0xd0 = subu $a0, $v1, $a1 -0x00,0xe0,0x31,0x90 = sub $a2, $zero, $a3 -0x00,0xe0,0x31,0xd0 = subu $a2, $zero, $a3 +0x00,0xe0,0x31,0x90 = neg $a2, $a3 +0x00,0xe0,0x31,0xd0 = negu $a2, $a3 0x00,0x08,0x39,0x50 = addu $a3, $t0, $zero 0x00,0xa3,0x1b,0x50 = slt $v1, $v1, $a1 0x90,0x63,0x00,0x67 = slti $v1, $v1, 103 diff --git a/suite/MC/Mips/micromips-alu-instructions.s.cs b/suite/MC/Mips/micromips-alu-instructions.s.cs index 81fe6438c..2571f8b75 100644 --- a/suite/MC/Mips/micromips-alu-instructions.s.cs +++ b/suite/MC/Mips/micromips-alu-instructions.s.cs @@ -7,8 +7,8 @@ 0xe6,0x00,0x50,0x49 = addu $t1, $a2, $a3 0xe6,0x00,0x90,0x49 = sub $t1, $a2, $a3 0xa3,0x00,0xd0,0x21 = subu $a0, $v1, $a1 -0xe0,0x00,0x90,0x31 = sub $a2, $zero, $a3 -0xe0,0x00,0xd0,0x31 = subu $a2, $zero, $a3 +0xe0,0x00,0x90,0x31 = neg $a2, $a3 +0xe0,0x00,0xd0,0x31 = negu $a2, $a3 0x08,0x00,0x50,0x39 = addu $a3, $t0, $zero 0xa3,0x00,0x50,0x1b = slt $v1, $v1, $a1 0x63,0x90,0x67,0x00 = slti $v1, $v1, 103 diff --git a/suite/MC/Mips/micromips-branch-instructions-EB.s.cs b/suite/MC/Mips/micromips-branch-instructions-EB.s.cs index 947ea2500..be78bff18 100644 --- a/suite/MC/Mips/micromips-branch-instructions-EB.s.cs +++ b/suite/MC/Mips/micromips-branch-instructions-EB.s.cs @@ -1,11 +1,11 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None -0x94,0x00,0x02,0x9a = b 1332 -0x94,0xc9,0x02,0x9a = beq $t1, $a2, 1332 -0x40,0x46,0x02,0x9a = bgez $a2, 1332 -0x40,0x66,0x02,0x9a = bgezal $a2, 1332 -0x40,0x26,0x02,0x9a = bltzal $a2, 1332 -0x40,0xc6,0x02,0x9a = bgtz $a2, 1332 -0x40,0x86,0x02,0x9a = blez $a2, 1332 -0xb4,0xc9,0x02,0x9a = bne $t1, $a2, 1332 -// 0x40,0x60,0x02,0x9a = bal 1332 -0x40,0x06,0x02,0x9a = bltz $a2, 1332 +0x94,0x00,0x02,0x9a = b 0x538 +0x94,0xc9,0x02,0x9a = beq $t1, $a2, 0x538 +0x40,0x46,0x02,0x9a = bgez $a2, 0x538 +0x40,0x66,0x02,0x9a = bgezal $a2, 0x538 +0x40,0x26,0x02,0x9a = bltzal $a2, 0x538 +0x40,0xc6,0x02,0x9a = bgtz $a2, 0x538 +0x40,0x86,0x02,0x9a = blez $a2, 0x538 +0xb4,0xc9,0x02,0x9a = bne $t1, $a2, 0x538 +// 0x40,0x60,0x02,0x9a = bal 0x538 +0x40,0x06,0x02,0x9a = bltz $a2, 0x538 diff --git a/suite/MC/Mips/micromips-branch-instructions.s.cs b/suite/MC/Mips/micromips-branch-instructions.s.cs index 286bc0d94..43ba3ba0f 100644 --- a/suite/MC/Mips/micromips-branch-instructions.s.cs +++ b/suite/MC/Mips/micromips-branch-instructions.s.cs @@ -1,11 +1,11 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None -0x00,0x94,0x9a,0x02 = b 1332 -0xc9,0x94,0x9a,0x02 = beq $t1, $a2, 1332 -0x46,0x40,0x9a,0x02 = bgez $a2, 1332 -0x66,0x40,0x9a,0x02 = bgezal $a2, 1332 -0x26,0x40,0x9a,0x02 = bltzal $a2, 1332 -0xc6,0x40,0x9a,0x02 = bgtz $a2, 1332 -0x86,0x40,0x9a,0x02 = blez $a2, 1332 -0xc9,0xb4,0x9a,0x02 = bne $t1, $a2, 1332 -// 0x60,0x40,0x9a,0x02 = bal 1332 -0x06,0x40,0x9a,0x02 = bltz $a2, 1332 +0x00,0x94,0x9a,0x02 = b 0x538 +0xc9,0x94,0x9a,0x02 = beq $t1, $a2, 0x538 +0x46,0x40,0x9a,0x02 = bgez $a2, 0x538 +0x66,0x40,0x9a,0x02 = bgezal $a2, 0x538 +0x26,0x40,0x9a,0x02 = bltzal $a2, 0x538 +0xc6,0x40,0x9a,0x02 = bgtz $a2, 0x538 +0x86,0x40,0x9a,0x02 = blez $a2, 0x538 +0xc9,0xb4,0x9a,0x02 = bne $t1, $a2, 0x538 +// 0x60,0x40,0x9a,0x02 = bal 0x538 +0x06,0x40,0x9a,0x02 = bltz $a2, 0x538 diff --git a/suite/MC/Mips/micromips-expansions.s.cs b/suite/MC/Mips/micromips-expansions.s.cs index b16331bb2..c9a385561 100644 --- a/suite/MC/Mips/micromips-expansions.s.cs +++ b/suite/MC/Mips/micromips-expansions.s.cs @@ -1,20 +1,25 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None -0xa0,0x50,0x7b,0x00 = ori $a1, $zero, 123 -0xc0,0x30,0xd7,0xf6 = addiu $a2, $zero, -2345 -0xa7,0x41,0x01,0x00 = lui $a3, 1 -0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 -0x80,0x30,0x14,0x00 = addiu $a0, $zero, 20 -0xa7,0x41,0x01,0x00 = lui $a3, 1 -0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 -0x85,0x30,0x14,0x00 = addiu $a0, $a1, 20 -0xa7,0x41,0x01,0x00 = lui $a3, 1 -0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 -0x07,0x01,0x50,0x39 = addu $a3, $a3, $t0 -0x8a,0x00,0x50,0x51 = addu $t2, $t2, $a0 -0x21,0x01,0x50,0x09 = addu $at, $at, $t1 -0xaa,0x41,0x0a,0x00 = lui $t2, 10 -0x8a,0x00,0x50,0x51 = addu $t2, $t2, $a0 -0x4a,0xfd,0x7b,0x00 = lw $t2, 123($t2) -0xa1,0x41,0x02,0x00 = lui $at, 2 -0x21,0x01,0x50,0x09 = addu $at, $at, $t1 -// 0x41,0xf9,0x40,0xe2 = sw $t2, 57920($at) + +0xa0,0x30,0x7b,0x00 == addiu $5, $zero, 123 # encoding: [0xa0,0x30,0x7b,0x00] +0xc0,0x30,0xd7,0xf6 == addiu $6, $zero, -2345 # encoding: [0xc0,0x30,0xd7,0xf6] +0xa7,0x41,0x01,0x00 == lui $7, 1 # encoding: [0xa7,0x41,0x01,0x00] +0xe7,0x50,0x02,0x00 == ori $7, $7, 2 # encoding: [0xe7,0x50,0x02,0x00] +0x80,0x30,0x14,0x00 == addiu $4, $zero, 20 # encoding: [0x80,0x30,0x14,0x00] +0xa7,0x41,0x01,0x00 == lui $7, 1 # encoding: [0xa7,0x41,0x01,0x00] +0xe7,0x50,0x02,0x00 == ori $7, $7, 2 # encoding: [0xe7,0x50,0x02,0x00] +0x85,0x30,0x14,0x00 == addiu $4, $5, 20 # encoding: [0x85,0x30,0x14,0x00] +0xa7,0x41,0x01,0x00 == lui $7, 1 # encoding: [0xa7,0x41,0x01,0x00] +0xe7,0x50,0x02,0x00 == ori $7, $7, 2 # encoding: [0xe7,0x50,0x02,0x00] +0x07,0x01,0x50,0x39 == addu $7, $7, $8 # encoding: [0x07,0x01,0x50,0x39] +0xaa == lui $10, %hi(symbol) # encoding: [0xaa'A',0x41'A',0x00,0x00] +0x8a,0x00,0x50,0x51 == addu $10, $10, $4 # encoding: [0x8a,0x00,0x50,0x51] +0x4a == lw $10, %lo(symbol)($10) # encoding: [0x4a'A',0xfd'A',0x00,0x00] +0xa1 == lui $1, %hi(symbol) # encoding: [0xa1'A',0x41'A',0x00,0x00] +0x21,0x01,0x50,0x09 == addu $1, $1, $9 # encoding: [0x21,0x01,0x50,0x09] +0x41 == sw $10, %lo(symbol)($1) # encoding: [0x41'A',0xf9'A',0x00,0x00] +0xaa,0x41,0x0a,0x00 == lui $10, 10 # encoding: [0xaa,0x41,0x0a,0x00] +0x8a,0x00,0x50,0x51 == addu $10, $10, $4 # encoding: [0x8a,0x00,0x50,0x51] +0x4a,0xfd,0x7b,0x00 == lw $10, 123($10) # encoding: [0x4a,0xfd,0x7b,0x00] +0xa1,0x41,0x02,0x00 == lui $1, 2 # encoding: [0xa1,0x41,0x02,0x00] +0x21,0x01,0x50,0x09 == addu $1, $1, $9 # encoding: [0x21,0x01,0x50,0x09] +0x41,0xf9,0x40,0xe2 == sw $10, -7616($1) # encoding: [0x41,0xf9,0x40,0xe2] diff --git a/suite/MC/Mips/mips-alu-instructions.s.cs b/suite/MC/Mips/mips-alu-instructions.s.cs index 1ee3337f2..cfdf23e33 100644 --- a/suite/MC/Mips/mips-alu-instructions.s.cs +++ b/suite/MC/Mips/mips-alu-instructions.s.cs @@ -1,53 +1,67 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32, None -0x24,0x48,0xc7,0x00 = and $t1, $a2, $a3 -0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 -0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 -0x67,0x45,0x29,0x31 = andi $t1, $t1, 17767 -0x21,0x30,0xe6,0x70 = clo $a2, $a3 -0x20,0x30,0xe6,0x70 = clz $a2, $a3 -0x84,0x61,0x33,0x7d = ins $s3, $t1, 6, 7 -0x27,0x48,0xc7,0x00 = nor $t1, $a2, $a3 -0x25,0x18,0x65,0x00 = or $v1, $v1, $a1 -0x67,0x45,0xa4,0x34 = ori $a0, $a1, 17767 -0x67,0x45,0xc9,0x34 = ori $t1, $a2, 17767 -0x80,0x00,0x6b,0x35 = ori $t3, $t3, 128 -0xc2,0x49,0x26,0x00 = rotr $t1, $a2, 7 -0x46,0x48,0xe6,0x00 = rotrv $t1, $a2, $a3 -0xc0,0x21,0x03,0x00 = sll $a0, $v1, 7 -0x04,0x10,0xa3,0x00 = sllv $v0, $v1, $a1 -0x2a,0x18,0x65,0x00 = slt $v1, $v1, $a1 -0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 -0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 -0x67,0x00,0x63,0x2c = sltiu $v1, $v1, 103 -0x2b,0x18,0x65,0x00 = sltu $v1, $v1, $a1 -0xc3,0x21,0x03,0x00 = sra $a0, $v1, 7 -0x07,0x10,0xa3,0x00 = srav $v0, $v1, $a1 -0xc2,0x21,0x03,0x00 = srl $a0, $v1, 7 -0x06,0x10,0xa3,0x00 = srlv $v0, $v1, $a1 -0x26,0x18,0x65,0x00 = xor $v1, $v1, $a1 -0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 -0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 -0x0c,0x00,0x6b,0x39 = xori $t3, $t3, 12 -0xa0,0x30,0x07,0x7c = wsbh $a2, $a3 -0x27,0x38,0x00,0x01 = not $a3, $t0 -0x20,0x48,0xc7,0x00 = add $t1, $a2, $a3 -0x67,0x45,0xc9,0x20 = addi $t1, $a2, 17767 -0x67,0xc5,0xc9,0x24 = addiu $t1, $a2, -15001 -0x67,0x45,0xc9,0x20 = addi $t1, $a2, 17767 -0x67,0x45,0x29,0x21 = addi $t1, $t1, 17767 -0x67,0xc5,0xc9,0x24 = addiu $t1, $a2, -15001 -0x28,0x00,0x6b,0x25 = addiu $t3, $t3, 40 -0x21,0x48,0xc7,0x00 = addu $t1, $a2, $a3 -0x00,0x00,0xc7,0x70 = madd $a2, $a3 -0x01,0x00,0xc7,0x70 = maddu $a2, $a3 -0x04,0x00,0xc7,0x70 = msub $a2, $a3 -0x05,0x00,0xc7,0x70 = msubu $a2, $a3 -0x18,0x00,0x65,0x00 = mult $v1, $a1 -0x19,0x00,0x65,0x00 = multu $v1, $a1 -0x22,0x48,0xc7,0x00 = sub $t1, $a2, $a3 -0xc8,0xff,0xbd,0x23 = addi $sp, $sp, -56 -0x23,0x20,0x65,0x00 = subu $a0, $v1, $a1 -0xd8,0xff,0xbd,0x27 = addiu $sp, $sp, -40 -0x22,0x30,0x07,0x00 = neg $a2, $a3 -0x23,0x30,0x07,0x00 = negu $a2, $a3 -0x21,0x38,0x00,0x01 = move $a3, $t0 + +0x24,0x48,0xc7,0x00 == and $9, $6, $7 # encoding: [0x24,0x48,0xc7,0x00] +0x67,0x45,0xc9,0x30 == andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30] +0x67,0x45,0xc9,0x30 == andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30] +0x67,0x45,0x29,0x31 == andi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x31] +0x21,0x30,0xe6,0x70 == clo $6, $7 # encoding: [0x21,0x30,0xe6,0x70] +0x20,0x30,0xe6,0x70 == clz $6, $7 # encoding: [0x20,0x30,0xe6,0x70] +0x84,0x61,0x33,0x7d == ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d] +0x27,0x48,0xc7,0x00 == nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00] +0x25,0x18,0x65,0x00 == or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00] +0x67,0x45,0xa4,0x34 == ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34] +0x67,0x45,0xc9,0x34 == ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34] +0x80,0x00,0x6b,0x35 == ori $11, $11, 128 # encoding: [0x80,0x00,0x6b,0x35] +0xc2,0x49,0x26,0x00 == rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00] +0x46,0x48,0xe6,0x00 == rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00] +0xc0,0x21,0x03,0x00 == sll $4, $3, 7 # encoding: [0xc0,0x21,0x03,0x00] +0x04,0x10,0xa3,0x00 == sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00] +0x2a,0x18,0x65,0x00 == slt $3, $3, $5 # encoding: [0x2a,0x18,0x65,0x00] +0x67,0x00,0x63,0x28 == slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28] +0x67,0x00,0x63,0x28 == slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28] +0x67,0x00,0x63,0x2c == sltiu $3, $3, 103 # encoding: [0x67,0x00,0x63,0x2c] +0x2b,0x18,0x65,0x00 == sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00] +0xc3,0x21,0x03,0x00 == sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00] +0x07,0x10,0xa3,0x00 == srav $2, $3, $5 # encoding: [0x07,0x10,0xa3,0x00] +0xc2,0x21,0x03,0x00 == srl $4, $3, 7 # encoding: [0xc2,0x21,0x03,0x00] +0x06,0x10,0xa3,0x00 == srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00] +0x26,0x18,0x65,0x00 == xor $3, $3, $5 # encoding: [0x26,0x18,0x65,0x00] +0x67,0x45,0xc9,0x38 == xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38] +0x67,0x45,0xc9,0x38 == xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38] +0x0c,0x00,0x6b,0x39 == xori $11, $11, 12 # encoding: [0x0c,0x00,0x6b,0x39] +0xa0,0x30,0x07,0x7c == wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c] +0x27,0x38,0x00,0x01 == not $7, $8 # encoding: [0x27,0x38,0x00,0x01] +0x20,0x48,0xc7,0x00 == add $9, $6, $7 # encoding: [0x20,0x48,0xc7,0x00] +0x67,0x45,0xc9,0x20 == addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20] +0x67,0xc5,0xc9,0x24 == addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24] +0x67,0x45,0xc9,0x20 == addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20] +0x67,0x45,0x29,0x21 == addi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x21] +0x67,0xc5,0xc9,0x24 == addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24] +0x28,0x00,0x6b,0x25 == addiu $11, $11, 40 # encoding: [0x28,0x00,0x6b,0x25] +0x21,0x48,0xc7,0x00 == addu $9, $6, $7 # encoding: [0x21,0x48,0xc7,0x00] +0x00,0x00,0xc7,0x70 == madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70] +0x01,0x00,0xc7,0x70 == maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70] +0x04,0x00,0xc7,0x70 == msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70] +0x05,0x00,0xc7,0x70 == msubu $6, $7 # encoding: [0x05,0x00,0xc7,0x70] +0x18,0x00,0x65,0x00 == mult $3, $5 # encoding: [0x18,0x00,0x65,0x00] +0x19,0x00,0x65,0x00 == multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] +0x22,0x48,0xc7,0x00 == sub $9, $6, $7 # encoding: [0x22,0x48,0xc7,0x00] +0xc8,0xff,0xbd,0x23 == addi $sp, $sp, -56 # encoding: [0xc8,0xff,0xbd,0x23] +0x23,0x20,0x65,0x00 == subu $4, $3, $5 # encoding: [0x23,0x20,0x65,0x00] +0xd8,0xff,0xbd,0x27 == addiu $sp, $sp, -40 # encoding: [0xd8,0xff,0xbd,0x27] +0x22,0x30,0x07,0x00 == neg $6, $7 # encoding: [0x22,0x30,0x07,0x00] +0x23,0x30,0x07,0x00 == negu $6, $7 # encoding: [0x23,0x30,0x07,0x00] +0x25,0x38,0x00,0x01 == move $7, $8 # encoding: [0x25,0x38,0x00,0x01] +0x3b,0xe8,0x05,0x7c == .set pop # encoding: [0x3b,0xe8,0x05,0x7c] +0x20,0x48,0x23,0x01 == add $9, $9, $3 # encoding: [0x20,0x48,0x23,0x01] +0x21,0x48,0x23,0x01 == addu $9, $9, $3 # encoding: [0x21,0x48,0x23,0x01] +0x0a,0x00,0x29,0x21 == addi $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x21] +0x0a,0x00,0x29,0x25 == addiu $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x25] +0x24,0x28,0xa6,0x00 == and $5, $5, $6 # encoding: [0x24,0x28,0xa6,0x00] +0x02,0x48,0x23,0x71 == mul $9, $9, $3 # encoding: [0x02,0x48,0x23,0x71] +0x25,0x10,0x44,0x00 == or $2, $2, $4 # encoding: [0x25,0x10,0x44,0x00] +0x22,0x48,0x23,0x01 == sub $9, $9, $3 # encoding: [0x22,0x48,0x23,0x01] +0x23,0x48,0x23,0x01 == subu $9, $9, $3 # encoding: [0x23,0x48,0x23,0x01] +0xf6,0xff,0x29,0x21 == addi $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x21] +0xf6,0xff,0x29,0x25 == addiu $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x25] +0x26,0x48,0x2a,0x01 == xor $9, $9, $10 # encoding: [0x26,0x48,0x2a,0x01] diff --git a/suite/MC/Mips/mips-control-instructions-64.s.cs b/suite/MC/Mips/mips-control-instructions-64.s.cs index c3478da19..a0ed98c77 100644 --- a/suite/MC/Mips/mips-control-instructions-64.s.cs +++ b/suite/MC/Mips/mips-control-instructions-64.s.cs @@ -1,4 +1,4 @@ -# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None +# CS_ARCH_MIPS, CS_MODE_MIPS64R2+CS_MODE_BIG_ENDIAN, None 0x00,0x00,0x00,0x0d = break // 0x00,0x07,0x00,0x0d = break 7, 0 0x00,0x07,0x01,0x4d = break 7, 5 diff --git a/suite/MC/Mips/mips-control-instructions.s.cs b/suite/MC/Mips/mips-control-instructions.s.cs index 86c4ad82e..d2442f214 100644 --- a/suite/MC/Mips/mips-control-instructions.s.cs +++ b/suite/MC/Mips/mips-control-instructions.s.cs @@ -1,4 +1,4 @@ -# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +# CS_ARCH_MIPS, CS_MODE_MIPS32R2+CS_MODE_BIG_ENDIAN, None 0x00,0x00,0x00,0x0d = break // 0x00,0x07,0x00,0x0d = break 7, 0 0x00,0x07,0x01,0x4d = break 7, 5 diff --git a/suite/MC/Mips/mips-coprocessor-encodings.s.cs b/suite/MC/Mips/mips-coprocessor-encodings.s.cs index d14ddc3ba..c343c9a8f 100644 --- a/suite/MC/Mips/mips-coprocessor-encodings.s.cs +++ b/suite/MC/Mips/mips-coprocessor-encodings.s.cs @@ -1,17 +1,17 @@ # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None -0x40,0xac,0x80,0x02 = dmtc0 $t4, $s0, 2 -0x40,0xac,0x80,0x00 = dmtc0 $t4, $s0, 0 -0x40,0x8c,0x80,0x02 = mtc0 $t4, $s0, 2 -0x40,0x8c,0x80,0x00 = mtc0 $t4, $s0, 0 -0x40,0x2c,0x80,0x02 = dmfc0 $t4, $s0, 2 -0x40,0x2c,0x80,0x00 = dmfc0 $t4, $s0, 0 -0x40,0x0c,0x80,0x02 = mfc0 $t4, $s0, 2 -0x40,0x0c,0x80,0x00 = mfc0 $t4, $s0, 0 -0x48,0xac,0x80,0x02 = dmtc2 $t4, $s0, 2 -0x48,0xac,0x80,0x00 = dmtc2 $t4, $s0, 0 -0x48,0x8c,0x80,0x02 = mtc2 $t4, $s0, 2 -0x48,0x8c,0x80,0x00 = mtc2 $t4, $s0, 0 -0x48,0x2c,0x80,0x02 = dmfc2 $t4, $s0, 2 -0x48,0x2c,0x80,0x00 = dmfc2 $t4, $s0, 0 -0x48,0x0c,0x80,0x02 = mfc2 $t4, $s0, 2 -0x48,0x0c,0x80,0x00 = mfc2 $t4, $s0, 0 +0x40,0xac,0x80,0x02 = dmtc0 $t4, $16, 2 +0x40,0xac,0x80,0x00 = dmtc0 $t4, $16, 0 +0x40,0x8c,0x80,0x02 = mtc0 $t4, $16, 2 +0x40,0x8c,0x80,0x00 = mtc0 $t4, $16, 0 +0x40,0x2c,0x80,0x02 = dmfc0 $t4, $16, 2 +0x40,0x2c,0x80,0x00 = dmfc0 $t4, $16, 0 +0x40,0x0c,0x80,0x02 = mfc0 $t4, $16, 2 +0x40,0x0c,0x80,0x00 = mfc0 $t4, $16, 0 +0x48,0xac,0x80,0x02 = dmtc2 $t4, $16, 2 +0x48,0xac,0x80,0x00 = dmtc2 $t4, $16, 0 +0x48,0x8c,0x80,0x02 = mtc2 $t4, $16, 2 +0x48,0x8c,0x80,0x00 = mtc2 $t4, $16, 0 +0x48,0x2c,0x80,0x02 = dmfc2 $t4, $16, 2 +0x48,0x2c,0x80,0x00 = dmfc2 $t4, $16, 0 +0x48,0x0c,0x80,0x02 = mfc2 $t4, $16, 2 +0x48,0x0c,0x80,0x00 = mfc2 $t4, $16, 0 diff --git a/suite/MC/Mips/mips-fpu-instructions.s.cs b/suite/MC/Mips/mips-fpu-instructions.s.cs index 335cd0f2e..c3a922d79 100644 --- a/suite/MC/Mips/mips-fpu-instructions.s.cs +++ b/suite/MC/Mips/mips-fpu-instructions.s.cs @@ -1,93 +1,94 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32, None -0x05,0x73,0x20,0x46 = abs.d $f12, $f14 -0x85,0x39,0x00,0x46 = abs.s $f6, $f7 -0x00,0x62,0x2e,0x46 = add.d $f8, $f12, $f14 -0x40,0x32,0x07,0x46 = add.s $f9, $f6, $f7 -0x0f,0x73,0x20,0x46 = floor.w.d $f12, $f14 -0x8f,0x39,0x00,0x46 = floor.w.s $f6, $f7 -0x0e,0x73,0x20,0x46 = ceil.w.d $f12, $f14 -0x8e,0x39,0x00,0x46 = ceil.w.s $f6, $f7 -0x02,0x62,0x2e,0x46 = mul.d $f8, $f12, $f14 -0x42,0x32,0x07,0x46 = mul.s $f9, $f6, $f7 -0x07,0x73,0x20,0x46 = neg.d $f12, $f14 -0x87,0x39,0x00,0x46 = neg.s $f6, $f7 -0x0c,0x73,0x20,0x46 = round.w.d $f12, $f14 -0x8c,0x39,0x00,0x46 = round.w.s $f6, $f7 -0x04,0x73,0x20,0x46 = sqrt.d $f12, $f14 -0x84,0x39,0x00,0x46 = sqrt.s $f6, $f7 -0x01,0x62,0x2e,0x46 = sub.d $f8, $f12, $f14 -0x41,0x32,0x07,0x46 = sub.s $f9, $f6, $f7 -0x0d,0x73,0x20,0x46 = trunc.w.d $f12, $f14 -0x8d,0x39,0x00,0x46 = trunc.w.s $f6, $f7 -0x32,0x60,0x2e,0x46 = c.eq.d $f12, $f14 -0x32,0x30,0x07,0x46 = c.eq.s $f6, $f7 -0x30,0x60,0x2e,0x46 = c.f.d $f12, $f14 -0x30,0x30,0x07,0x46 = c.f.s $f6, $f7 -0x3e,0x60,0x2e,0x46 = c.le.d $f12, $f14 -0x3e,0x30,0x07,0x46 = c.le.s $f6, $f7 -0x3c,0x60,0x2e,0x46 = c.lt.d $f12, $f14 -0x3c,0x30,0x07,0x46 = c.lt.s $f6, $f7 -0x3d,0x60,0x2e,0x46 = c.nge.d $f12, $f14 -0x3d,0x30,0x07,0x46 = c.nge.s $f6, $f7 -0x3b,0x60,0x2e,0x46 = c.ngl.d $f12, $f14 -0x3b,0x30,0x07,0x46 = c.ngl.s $f6, $f7 -0x39,0x60,0x2e,0x46 = c.ngle.d $f12, $f14 -0x39,0x30,0x07,0x46 = c.ngle.s $f6, $f7 -0x3f,0x60,0x2e,0x46 = c.ngt.d $f12, $f14 -0x3f,0x30,0x07,0x46 = c.ngt.s $f6, $f7 -0x36,0x60,0x2e,0x46 = c.ole.d $f12, $f14 -0x36,0x30,0x07,0x46 = c.ole.s $f6, $f7 -0x34,0x60,0x2e,0x46 = c.olt.d $f12, $f14 -0x34,0x30,0x07,0x46 = c.olt.s $f6, $f7 -0x3a,0x60,0x2e,0x46 = c.seq.d $f12, $f14 -0x3a,0x30,0x07,0x46 = c.seq.s $f6, $f7 -0x38,0x60,0x2e,0x46 = c.sf.d $f12, $f14 -0x38,0x30,0x07,0x46 = c.sf.s $f6, $f7 -0x33,0x60,0x2e,0x46 = c.ueq.d $f12, $f14 -0x33,0xe0,0x12,0x46 = c.ueq.s $f28, $f18 -0x37,0x60,0x2e,0x46 = c.ule.d $f12, $f14 -0x37,0x30,0x07,0x46 = c.ule.s $f6, $f7 -0x35,0x60,0x2e,0x46 = c.ult.d $f12, $f14 -0x35,0x30,0x07,0x46 = c.ult.s $f6, $f7 -0x31,0x60,0x2e,0x46 = c.un.d $f12, $f14 -0x31,0x30,0x07,0x46 = c.un.s $f6, $f7 -0xa1,0x39,0x00,0x46 = cvt.d.s $f6, $f7 -0x21,0x73,0x80,0x46 = cvt.d.w $f12, $f14 -0x20,0x73,0x20,0x46 = cvt.s.d $f12, $f14 -0xa0,0x39,0x80,0x46 = cvt.s.w $f6, $f7 -0x24,0x73,0x20,0x46 = cvt.w.d $f12, $f14 -0xa4,0x39,0x00,0x46 = cvt.w.s $f6, $f7 -0x00,0x00,0x46,0x44 = cfc1 $a2, $0 -0x00,0xf8,0xca,0x44 = ctc1 $t2, $31 -0x00,0x38,0x06,0x44 = mfc1 $a2, $f7 -0x10,0x28,0x00,0x00 = mfhi $a1 -0x12,0x28,0x00,0x00 = mflo $a1 -0x86,0x41,0x20,0x46 = mov.d $f6, $f8 -0x86,0x39,0x00,0x46 = mov.s $f6, $f7 -0x00,0x38,0x86,0x44 = mtc1 $a2, $f7 -0x11,0x00,0xe0,0x00 = mthi $a3 -0x13,0x00,0xe0,0x00 = mtlo $a3 -0xc6,0x23,0xe9,0xe4 = swc1 $f9, 9158($a3) -0x00,0x38,0x06,0x40 = mfc0 $a2, $a3, 0 -0x00,0x40,0x89,0x40 = mtc0 $t1, $t0, 0 -0x00,0x38,0x05,0x48 = mfc2 $a1, $a3, 0 -0x00,0x20,0x89,0x48 = mtc2 $t1, $a0, 0 -0x02,0x38,0x06,0x40 = mfc0 $a2, $a3, 2 -0x03,0x40,0x89,0x40 = mtc0 $t1, $t0, 3 -0x04,0x38,0x05,0x48 = mfc2 $a1, $a3, 4 -0x05,0x20,0x89,0x48 = mtc2 $t1, $a0, 5 -0x01,0x10,0x20,0x00 = movf $v0, $at, $fcc0 -0x01,0x10,0x21,0x00 = movt $v0, $at, $fcc0 -0x01,0x20,0xb1,0x00 = movt $a0, $a1, $fcc4 -0x11,0x31,0x28,0x46 = movf.d $f4, $f6, $fcc2 -0x11,0x31,0x14,0x46 = movf.s $f4, $f6, $fcc5 -0x05,0x00,0xa6,0x4c = luxc1 $f0, $a2($a1) -0x0d,0x20,0xb8,0x4c = suxc1 $f4, $t8($a1) -0x00,0x05,0xcc,0x4d = lwxc1 $f20, $t4($t6) -0x08,0xd0,0xd2,0x4e = swxc1 $f26, $s2($s6) -0x00,0x20,0x71,0x44 = mfhc1 $s1, $f4 -0x00,0x30,0xf1,0x44 = mthc1 $s1, $f6 -0x10,0x00,0xa4,0xeb = swc2 $4, 16($sp) -0x10,0x00,0xa4,0xfb = sdc2 $4, 16($sp) -0x0c,0x00,0xeb,0xcb = lwc2 $11, 12($ra) -0x0c,0x00,0xeb,0xdb = ldc2 $11, 12($ra) + +0x05,0x73,0x20,0x46 == abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46] +0x85,0x39,0x00,0x46 == abs.s $f6, $f7 # encoding: [0x85,0x39,0x00,0x46] +0x00,0x62,0x2e,0x46 == add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46] +0x40,0x32,0x07,0x46 == add.s $f9, $f6, $f7 # encoding: [0x40,0x32,0x07,0x46] +0x0f,0x73,0x20,0x46 == floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46] +0x8f,0x39,0x00,0x46 == floor.w.s $f6, $f7 # encoding: [0x8f,0x39,0x00,0x46] +0x0e,0x73,0x20,0x46 == ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46] +0x8e,0x39,0x00,0x46 == ceil.w.s $f6, $f7 # encoding: [0x8e,0x39,0x00,0x46] +0x02,0x62,0x2e,0x46 == mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46] +0x42,0x32,0x07,0x46 == mul.s $f9, $f6, $f7 # encoding: [0x42,0x32,0x07,0x46] +0x07,0x73,0x20,0x46 == neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46] +0x87,0x39,0x00,0x46 == neg.s $f6, $f7 # encoding: [0x87,0x39,0x00,0x46] +0x0c,0x73,0x20,0x46 == round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46] +0x8c,0x39,0x00,0x46 == round.w.s $f6, $f7 # encoding: [0x8c,0x39,0x00,0x46] +0x04,0x73,0x20,0x46 == sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46] +0x84,0x39,0x00,0x46 == sqrt.s $f6, $f7 # encoding: [0x84,0x39,0x00,0x46] +0x01,0x62,0x2e,0x46 == sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46] +0x41,0x32,0x07,0x46 == sub.s $f9, $f6, $f7 # encoding: [0x41,0x32,0x07,0x46] +0x0d,0x73,0x20,0x46 == trunc.w.d $f12, $f14 # encoding: [0x0d,0x73,0x20,0x46] +0x8d,0x39,0x00,0x46 == trunc.w.s $f6, $f7 # encoding: [0x8d,0x39,0x00,0x46] +0x32,0x60,0x2e,0x46 == c.eq.d $f12, $f14 # encoding: [0x32,0x60,0x2e,0x46] +0x32,0x30,0x07,0x46 == c.eq.s $f6, $f7 # encoding: [0x32,0x30,0x07,0x46] +0x30,0x60,0x2e,0x46 == c.f.d $f12, $f14 # encoding: [0x30,0x60,0x2e,0x46] +0x30,0x30,0x07,0x46 == c.f.s $f6, $f7 # encoding: [0x30,0x30,0x07,0x46] +0x3e,0x60,0x2e,0x46 == c.le.d $f12, $f14 # encoding: [0x3e,0x60,0x2e,0x46] +0x3e,0x30,0x07,0x46 == c.le.s $f6, $f7 # encoding: [0x3e,0x30,0x07,0x46] +0x3c,0x60,0x2e,0x46 == c.lt.d $f12, $f14 # encoding: [0x3c,0x60,0x2e,0x46] +0x3c,0x30,0x07,0x46 == c.lt.s $f6, $f7 # encoding: [0x3c,0x30,0x07,0x46] +0x3d,0x60,0x2e,0x46 == c.nge.d $f12, $f14 # encoding: [0x3d,0x60,0x2e,0x46] +0x3d,0x30,0x07,0x46 == c.nge.s $f6, $f7 # encoding: [0x3d,0x30,0x07,0x46] +0x3b,0x60,0x2e,0x46 == c.ngl.d $f12, $f14 # encoding: [0x3b,0x60,0x2e,0x46] +0x3b,0x30,0x07,0x46 == c.ngl.s $f6, $f7 # encoding: [0x3b,0x30,0x07,0x46] +0x39,0x60,0x2e,0x46 == c.ngle.d $f12, $f14 # encoding: [0x39,0x60,0x2e,0x46] +0x39,0x30,0x07,0x46 == c.ngle.s $f6, $f7 # encoding: [0x39,0x30,0x07,0x46] +0x3f,0x60,0x2e,0x46 == c.ngt.d $f12, $f14 # encoding: [0x3f,0x60,0x2e,0x46] +0x3f,0x30,0x07,0x46 == c.ngt.s $f6, $f7 # encoding: [0x3f,0x30,0x07,0x46] +0x36,0x60,0x2e,0x46 == c.ole.d $f12, $f14 # encoding: [0x36,0x60,0x2e,0x46] +0x36,0x30,0x07,0x46 == c.ole.s $f6, $f7 # encoding: [0x36,0x30,0x07,0x46] +0x34,0x60,0x2e,0x46 == c.olt.d $f12, $f14 # encoding: [0x34,0x60,0x2e,0x46] +0x34,0x30,0x07,0x46 == c.olt.s $f6, $f7 # encoding: [0x34,0x30,0x07,0x46] +0x3a,0x60,0x2e,0x46 == c.seq.d $f12, $f14 # encoding: [0x3a,0x60,0x2e,0x46] +0x3a,0x30,0x07,0x46 == c.seq.s $f6, $f7 # encoding: [0x3a,0x30,0x07,0x46] +0x38,0x60,0x2e,0x46 == c.sf.d $f12, $f14 # encoding: [0x38,0x60,0x2e,0x46] +0x38,0x30,0x07,0x46 == c.sf.s $f6, $f7 # encoding: [0x38,0x30,0x07,0x46] +0x33,0x60,0x2e,0x46 == c.ueq.d $f12, $f14 # encoding: [0x33,0x60,0x2e,0x46] +0x33,0xe0,0x12,0x46 == c.ueq.s $f28, $f18 # encoding: [0x33,0xe0,0x12,0x46] +0x37,0x60,0x2e,0x46 == c.ule.d $f12, $f14 # encoding: [0x37,0x60,0x2e,0x46] +0x37,0x30,0x07,0x46 == c.ule.s $f6, $f7 # encoding: [0x37,0x30,0x07,0x46] +0x35,0x60,0x2e,0x46 == c.ult.d $f12, $f14 # encoding: [0x35,0x60,0x2e,0x46] +0x35,0x30,0x07,0x46 == c.ult.s $f6, $f7 # encoding: [0x35,0x30,0x07,0x46] +0x31,0x60,0x2e,0x46 == c.un.d $f12, $f14 # encoding: [0x31,0x60,0x2e,0x46] +0x31,0x30,0x07,0x46 == c.un.s $f6, $f7 # encoding: [0x31,0x30,0x07,0x46] +0xa1,0x39,0x00,0x46 == cvt.d.s $f6, $f7 # encoding: [0xa1,0x39,0x00,0x46] +0x21,0x73,0x80,0x46 == cvt.d.w $f12, $f14 # encoding: [0x21,0x73,0x80,0x46] +0x20,0x73,0x20,0x46 == cvt.s.d $f12, $f14 # encoding: [0x20,0x73,0x20,0x46] +0xa0,0x39,0x80,0x46 == cvt.s.w $f6, $f7 # encoding: [0xa0,0x39,0x80,0x46] +0x24,0x73,0x20,0x46 == cvt.w.d $f12, $f14 # encoding: [0x24,0x73,0x20,0x46] +0xa4,0x39,0x00,0x46 == cvt.w.s $f6, $f7 # encoding: [0xa4,0x39,0x00,0x46] +0x00,0x00,0x46,0x44 == cfc1 $6, $0 # encoding: [0x00,0x00,0x46,0x44] +0x00,0xf8,0xca,0x44 == ctc1 $10, $31 # encoding: [0x00,0xf8,0xca,0x44] +0x00,0x38,0x06,0x44 == mfc1 $6, $f7 # encoding: [0x00,0x38,0x06,0x44] +0x10,0x28,0x00,0x00 == mfhi $5 # encoding: [0x10,0x28,0x00,0x00] +0x12,0x28,0x00,0x00 == mflo $5 # encoding: [0x12,0x28,0x00,0x00] +0x86,0x41,0x20,0x46 == mov.d $f6, $f8 # encoding: [0x86,0x41,0x20,0x46] +0x86,0x39,0x00,0x46 == mov.s $f6, $f7 # encoding: [0x86,0x39,0x00,0x46] +0x00,0x38,0x86,0x44 == mtc1 $6, $f7 # encoding: [0x00,0x38,0x86,0x44] +0x11,0x00,0xe0,0x00 == mthi $7 # encoding: [0x11,0x00,0xe0,0x00] +0x13,0x00,0xe0,0x00 == mtlo $7 # encoding: [0x13,0x00,0xe0,0x00] +0xc6,0x23,0xe9,0xe4 == swc1 $f9, 9158($7) # encoding: [0xc6,0x23,0xe9,0xe4] +0x00,0x38,0x06,0x40 == mfc0 $6, $7, 0 # encoding: [0x00,0x38,0x06,0x40] +0x00,0x40,0x89,0x40 == mtc0 $9, $8, 0 # encoding: [0x00,0x40,0x89,0x40] +0x00,0x38,0x05,0x48 == mfc2 $5, $7, 0 # encoding: [0x00,0x38,0x05,0x48] +0x00,0x20,0x89,0x48 == mtc2 $9, $4, 0 # encoding: [0x00,0x20,0x89,0x48] +0x02,0x38,0x06,0x40 == mfc0 $6, $7, 2 # encoding: [0x02,0x38,0x06,0x40] +0x03,0x40,0x89,0x40 == mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40] +0x04,0x38,0x05,0x48 == mfc2 $5, $7, 4 # encoding: [0x04,0x38,0x05,0x48] +0x05,0x20,0x89,0x48 == mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48] +0x01,0x10,0x20,0x00 == movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00] +0x01,0x10,0x21,0x00 == movt $2, $1, $fcc0 # encoding: [0x01,0x10,0x21,0x00] +0x01,0x20,0xb1,0x00 == movt $4, $5, $fcc4 # encoding: [0x01,0x20,0xb1,0x00] +0x11,0x31,0x28,0x46 == movf.d $f4, $f6, $fcc2 # encoding: [0x11,0x31,0x28,0x46] +0x11,0x31,0x14,0x46 == movf.s $f4, $f6, $fcc5 # encoding: [0x11,0x31,0x14,0x46] +0x05,0x00,0xa6,0x4c == luxc1 $f0, $6($5) # encoding: [0x05,0x00,0xa6,0x4c] +0x0d,0x20,0xb8,0x4c == suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c] +0x00,0x05,0xcc,0x4d == lwxc1 $f20, $12($14) # encoding: [0x00,0x05,0xcc,0x4d] +0x08,0xd0,0xd2,0x4e == swxc1 $f26, $18($22) # encoding: [0x08,0xd0,0xd2,0x4e] +0x00,0x20,0x71,0x44 == mfhc1 $17, $f4 # encoding: [0x00,0x20,0x71,0x44] +0x00,0x30,0xf1,0x44 == mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44] +0x10,0x00,0xa4,0xeb == swc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xeb] +0x10,0x00,0xa4,0xfb == sdc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xfb] +0x0c,0x00,0xeb,0xcb == lwc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xcb] +0x0c,0x00,0xeb,0xdb == ldc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xdb] diff --git a/suite/MC/Mips/mips-memory-instructions.s.cs b/suite/MC/Mips/mips-memory-instructions.s.cs index ac5b3605c..365cae95e 100644 --- a/suite/MC/Mips/mips-memory-instructions.s.cs +++ b/suite/MC/Mips/mips-memory-instructions.s.cs @@ -1,17 +1,18 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32, None -0x10,0x00,0xa4,0xa0 = sb $a0, 16($a1) -0x10,0x00,0xa4,0xe0 = sc $a0, 16($a1) -0x10,0x00,0xa4,0xa4 = sh $a0, 16($a1) -0x10,0x00,0xa4,0xac = sw $a0, 16($a1) -0x00,0x00,0xa7,0xac = sw $a3, ($a1) -0x10,0x00,0xa2,0xe4 = swc1 $f2, 16($a1) -0x10,0x00,0xa4,0xa8 = swl $a0, 16($a1) -0x04,0x00,0xa4,0x80 = lb $a0, 4($a1) -0x04,0x00,0xa4,0x8c = lw $a0, 4($a1) -0x04,0x00,0xa4,0x90 = lbu $a0, 4($a1) -0x04,0x00,0xa4,0x84 = lh $a0, 4($a1) -0x04,0x00,0xa4,0x94 = lhu $a0, 4($a1) -0x04,0x00,0xa4,0xc0 = ll $a0, 4($a1) -0x04,0x00,0xa4,0x8c = lw $a0, 4($a1) -0x00,0x00,0xe7,0x8c = lw $a3, ($a3) -0x10,0x00,0xa2,0x8f = lw $v0, 16($sp) + +0x10,0x00,0xa4,0xa0 == sb $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa0] +0x10,0x00,0xa4,0xe0 == sc $4, 16($5) # encoding: [0x10,0x00,0xa4,0xe0] +0x10,0x00,0xa4,0xa4 == sh $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa4] +0x10,0x00,0xa4,0xac == sw $4, 16($5) # encoding: [0x10,0x00,0xa4,0xac] +0x00,0x00,0xa7,0xac == sw $7, 0($5) # encoding: [0x00,0x00,0xa7,0xac] +0x10,0x00,0xa2,0xe4 == swc1 $f2, 16($5) # encoding: [0x10,0x00,0xa2,0xe4] +0x10,0x00,0xa4,0xa8 == swl $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa8] +0x04,0x00,0xa4,0x80 == lb $4, 4($5) # encoding: [0x04,0x00,0xa4,0x80] +0x04,0x00,0xa4,0x8c == lw $4, 4($5) # encoding: [0x04,0x00,0xa4,0x8c] +0x04,0x00,0xa4,0x90 == lbu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x90] +0x04,0x00,0xa4,0x84 == lh $4, 4($5) # encoding: [0x04,0x00,0xa4,0x84] +0x04,0x00,0xa4,0x94 == lhu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x94] +0x04,0x00,0xa4,0xc0 == ll $4, 4($5) # encoding: [0x04,0x00,0xa4,0xc0] +0x04,0x00,0xa4,0x8c == lw $4, 4($5) # encoding: [0x04,0x00,0xa4,0x8c] +0x00,0x00,0xe7,0x8c == lw $7, 0($7) # encoding: [0x00,0x00,0xe7,0x8c] +0x10,0x00,0xa2,0x8f == lw $2, 16($sp) # encoding: [0x10,0x00,0xa2,0x8f] diff --git a/suite/MC/Mips/mips64-alu-instructions.s.cs b/suite/MC/Mips/mips64-alu-instructions.s.cs index eeac44e5e..aa50b816a 100644 --- a/suite/MC/Mips/mips64-alu-instructions.s.cs +++ b/suite/MC/Mips/mips64-alu-instructions.s.cs @@ -1,47 +1,66 @@ # CS_ARCH_MIPS, CS_MODE_MIPS64, None -0x24,0x48,0xc7,0x00 = and $t1, $a2, $a3 -0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 -0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 -0x21,0x30,0xe6,0x70 = clo $a2, $a3 -0x20,0x30,0xe6,0x70 = clz $a2, $a3 -0x84,0x61,0x33,0x7d = ins $s3, $t1, 6, 7 -0x27,0x48,0xc7,0x00 = nor $t1, $a2, $a3 -0x25,0x18,0x65,0x00 = or $v1, $v1, $a1 -0x67,0x45,0xa4,0x34 = ori $a0, $a1, 17767 -0x67,0x45,0xc9,0x34 = ori $t1, $a2, 17767 -0xc2,0x49,0x26,0x00 = rotr $t1, $a2, 7 -0x46,0x48,0xe6,0x00 = rotrv $t1, $a2, $a3 -0xc0,0x21,0x03,0x00 = sll $a0, $v1, 7 -0x04,0x10,0xa3,0x00 = sllv $v0, $v1, $a1 -0x2a,0x18,0x65,0x00 = slt $v1, $v1, $a1 -0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 -0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 -0x67,0x00,0x63,0x2c = sltiu $v1, $v1, 103 -0x2b,0x18,0x65,0x00 = sltu $v1, $v1, $a1 -0xc3,0x21,0x03,0x00 = sra $a0, $v1, 7 -0x07,0x10,0xa3,0x00 = srav $v0, $v1, $a1 -0xc2,0x21,0x03,0x00 = srl $a0, $v1, 7 -0x06,0x10,0xa3,0x00 = srlv $v0, $v1, $a1 -0x26,0x18,0x65,0x00 = xor $v1, $v1, $a1 -0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 -0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 -0xa0,0x30,0x07,0x7c = wsbh $a2, $a3 -0x27,0x38,0x00,0x01 = not $a3, $t0 -0x2c,0x48,0xc7,0x00 = dadd $t1, $a2, $a3 -0x67,0x45,0xc9,0x60 = daddi $t1, $a2, 17767 -0x67,0xc5,0xc9,0x64 = daddiu $t1, $a2, -15001 -0x67,0x45,0xc9,0x60 = daddi $t1, $a2, 17767 -0x67,0x45,0x29,0x61 = daddi $t1, $t1, 17767 -0x67,0xc5,0xc9,0x64 = daddiu $t1, $a2, -15001 -0x67,0xc5,0x29,0x65 = daddiu $t1, $t1, -15001 -0x2d,0x48,0xc7,0x00 = daddu $t1, $a2, $a3 -0x3a,0x4d,0x26,0x00 = drotr $t1, $a2, 20 -// 0x3e,0x4d,0x26,0x00 = drotr32 $t1, $a2, 52 -0x00,0x00,0xc7,0x70 = madd $a2, $a3 -0x01,0x00,0xc7,0x70 = maddu $a2, $a3 -0x04,0x00,0xc7,0x70 = msub $a2, $a3 -0x05,0x00,0xc7,0x70 = msubu $a2, $a3 -0x18,0x00,0x65,0x00 = mult $v1, $a1 -0x19,0x00,0x65,0x00 = multu $v1, $a1 -0x2f,0x20,0x65,0x00 = dsubu $a0, $v1, $a1 -0x2d,0x38,0x00,0x01 = move $a3, $t0 + +0x24,0x48,0xc7,0x00 == and $9, $6, $7 # encoding: [0x24,0x48,0xc7,0x00] +0x67,0x45,0xc9,0x30 == andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30] +0x67,0x45,0xc9,0x30 == andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30] +0x21,0x30,0xe6,0x70 == clo $6, $7 # encoding: [0x21,0x30,0xe6,0x70] +0x20,0x30,0xe6,0x70 == clz $6, $7 # encoding: [0x20,0x30,0xe6,0x70] +0x84,0x61,0x33,0x7d == ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d] +0x27,0x48,0xc7,0x00 == nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00] +0x25,0x18,0x65,0x00 == or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00] +0x67,0x45,0xa4,0x34 == ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34] +0x67,0x45,0xc9,0x34 == ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34] +0xc2,0x49,0x26,0x00 == rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00] +0x46,0x48,0xe6,0x00 == rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00] +0xc0,0x21,0x03,0x00 == sll $4, $3, 7 # encoding: [0xc0,0x21,0x03,0x00] +0x04,0x10,0xa3,0x00 == sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00] +0x2a,0x18,0x65,0x00 == slt $3, $3, $5 # encoding: [0x2a,0x18,0x65,0x00] +0x67,0x00,0x63,0x28 == slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28] +0x67,0x00,0x63,0x28 == slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28] +0x67,0x00,0x63,0x2c == sltiu $3, $3, 103 # encoding: [0x67,0x00,0x63,0x2c] +0x2b,0x18,0x65,0x00 == sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00] +0xc3,0x21,0x03,0x00 == sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00] +0x07,0x10,0xa3,0x00 == srav $2, $3, $5 # encoding: [0x07,0x10,0xa3,0x00] +0xc2,0x21,0x03,0x00 == srl $4, $3, 7 # encoding: [0xc2,0x21,0x03,0x00] +0x06,0x10,0xa3,0x00 == srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00] +0x26,0x18,0x65,0x00 == xor $3, $3, $5 # encoding: [0x26,0x18,0x65,0x00] +0x67,0x45,0xc9,0x38 == xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38] +0x67,0x45,0xc9,0x38 == xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38] +0xa0,0x30,0x07,0x7c == wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c] +0x27,0x38,0x00,0x01 == not $7, $8 # encoding: [0x27,0x38,0x00,0x01] +0x2c,0x48,0xc7,0x00 == dadd $9, $6, $7 # encoding: [0x2c,0x48,0xc7,0x00] +0x67,0x45,0xc9,0x60 == daddi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x60] +0x67,0xc5,0xc9,0x64 == daddiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x64] +0x67,0x45,0xc9,0x60 == daddi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x60] +0x67,0x45,0x29,0x61 == daddi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x61] +0x67,0xc5,0xc9,0x64 == daddiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x64] +0x67,0xc5,0x29,0x65 == daddiu $9, $9, -15001 # encoding: [0x67,0xc5,0x29,0x65] +0x2d,0x48,0xc7,0x00 == daddu $9, $6, $7 # encoding: [0x2d,0x48,0xc7,0x00] +0x3a,0x4d,0x26,0x00 == drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00] +0x3e,0x4d,0x26,0x00 == drotr32 $9, $6, 20 # encoding: [0x3e,0x4d,0x26,0x00] +0x00,0x00,0xc7,0x70 == madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70] +0x01,0x00,0xc7,0x70 == maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70] +0x04,0x00,0xc7,0x70 == msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70] +0x05,0x00,0xc7,0x70 == msubu $6, $7 # encoding: [0x05,0x00,0xc7,0x70] +0x18,0x00,0x65,0x00 == mult $3, $5 # encoding: [0x18,0x00,0x65,0x00] +0x19,0x00,0x65,0x00 == multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] +0x2e,0x48,0xc7,0x00 == dsub $9, $6, $7 # encoding: [0x2e,0x48,0xc7,0x00] +0x2f,0x20,0x65,0x00 == dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00] +0x99,0xba,0xc9,0x64 == daddiu $9, $6, -17767 # encoding: [0x99,0xba,0xc9,0x64] +0x25,0x38,0x00,0x01 == move $7, $8 # encoding: [0x25,0x38,0x00,0x01] +0x3b,0xe8,0x05,0x7c == .set pop # encoding: [0x3b,0xe8,0x05,0x7c] +0x24,0x48,0x23,0x01 == and $9, $9, $3 # encoding: [0x24,0x48,0x23,0x01] +0x2c,0x48,0x23,0x01 == dadd $9, $9, $3 # encoding: [0x2c,0x48,0x23,0x01] +0x2d,0x48,0x23,0x01 == daddu $9, $9, $3 # encoding: [0x2d,0x48,0x23,0x01] +0x0a,0x00,0x29,0x61 == daddi $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x61] +0x0a,0x00,0x29,0x65 == daddiu $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x65] +0x2e,0x48,0x23,0x01 == dsub $9, $9, $3 # encoding: [0x2e,0x48,0x23,0x01] +0x2f,0x48,0x23,0x01 == dsubu $9, $9, $3 # encoding: [0x2f,0x48,0x23,0x01] +0xf6,0xff,0x29,0x61 == daddi $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x61] +0xf6,0xff,0x29,0x65 == daddiu $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x65] +0x25,0x48,0x23,0x01 == or $9, $9, $3 # encoding: [0x25,0x48,0x23,0x01] +0x26,0x48,0x23,0x01 == xor $9, $9, $3 # encoding: [0x26,0x48,0x23,0x01] +0x20,0x00,0x69,0x64 == daddiu $9, $3, 32 # encoding: [0x20,0x00,0x69,0x64] +0x20,0x00,0x69,0x64 == daddiu $9, $3, 32 # encoding: [0x20,0x00,0x69,0x64] +0xe0,0xff,0x69,0x64 == daddiu $9, $3, -32 # encoding: [0xe0,0xff,0x69,0x64] +0xe0,0xff,0x69,0x64 == daddiu $9, $3, -32 # encoding: [0xe0,0xff,0x69,0x64] diff --git a/suite/MC/Mips/mips64-instructions.s.cs b/suite/MC/Mips/mips64-instructions.s.cs index be7cc23a1..85fe34a7d 100644 --- a/suite/MC/Mips/mips64-instructions.s.cs +++ b/suite/MC/Mips/mips64-instructions.s.cs @@ -1,3 +1,4 @@ # CS_ARCH_MIPS, CS_MODE_MIPS64, None -0x81,0x00,0x42,0x4d = ldxc1 $f2, $v0($t2) -0x09,0x40,0x24,0x4f = sdxc1 $f8, $a0($t9) + +0x81,0x00,0x42,0x4d == ldxc1 $f2, $2($10) # encoding: [0x81,0x00,0x42,0x4d] +0x09,0x40,0x24,0x4f == sdxc1 $f8, $4($25) # encoding: [0x09,0x40,0x24,0x4f] diff --git a/suite/MC/Mips/mips64-register-names-n32-n64.s.cs b/suite/MC/Mips/mips64-register-names-n32-n64.s.cs new file mode 100644 index 000000000..29ae367ab --- /dev/null +++ b/suite/MC/Mips/mips64-register-names-n32-n64.s.cs @@ -0,0 +1,33 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None +0x64,0x00,0x00,0x00 == daddiu $zero, $zero, 0 # encoding: [0x64,0x00,0x00,0x00] +0x64,0x01,0x00,0x00 == daddiu $at, $zero, 0 # encoding: [0x64,0x01,0x00,0x00] +0x64,0x02,0x00,0x00 == daddiu $v0, $zero, 0 # encoding: [0x64,0x02,0x00,0x00] +0x64,0x03,0x00,0x00 == daddiu $v1, $zero, 0 # encoding: [0x64,0x03,0x00,0x00] +0x64,0x04,0x00,0x00 == daddiu $a0, $zero, 0 # encoding: [0x64,0x04,0x00,0x00] +0x64,0x05,0x00,0x00 == daddiu $a1, $zero, 0 # encoding: [0x64,0x05,0x00,0x00] +0x64,0x06,0x00,0x00 == daddiu $a2, $zero, 0 # encoding: [0x64,0x06,0x00,0x00] +0x64,0x07,0x00,0x00 == daddiu $a2, $zero, 0 # encoding: [0x64,0x07,0x00,0x00] +0x64,0x08,0x00,0x00 == daddiu $a4, $zero, 0 # encoding: [0x64,0x08,0x00,0x00] +0x64,0x09,0x00,0x00 == daddiu $a5, $zero, 0 # encoding: [0x64,0x09,0x00,0x00] +0x64,0x0a,0x00,0x00 == daddiu $a6, $zero, 0 # encoding: [0x64,0x0a,0x00,0x00] +0x64,0x0b,0x00,0x00 == daddiu $a7, $zero, 0 # encoding: [0x64,0x0b,0x00,0x00] +0x64,0x0c,0x00,0x00 == daddiu $t4, $zero, 0 # encoding: [0x64,0x0c,0x00,0x00] +0x64,0x0d,0x00,0x00 == daddiu $t5, $zero, 0 # encoding: [0x64,0x0d,0x00,0x00] +0x64,0x0e,0x00,0x00 == daddiu $t6, $zero, 0 # encoding: [0x64,0x0e,0x00,0x00] +0x64,0x0f,0x00,0x00 == daddiu $t7, $zero, 0 # encoding: [0x64,0x0f,0x00,0x00] +0x64,0x10,0x00,0x00 == daddiu $s0, $zero, 0 # encoding: [0x64,0x10,0x00,0x00] +0x64,0x11,0x00,0x00 == daddiu $s1, $zero, 0 # encoding: [0x64,0x11,0x00,0x00] +0x64,0x12,0x00,0x00 == daddiu $s2, $zero, 0 # encoding: [0x64,0x12,0x00,0x00] +0x64,0x13,0x00,0x00 == daddiu $s3, $zero, 0 # encoding: [0x64,0x13,0x00,0x00] +0x64,0x14,0x00,0x00 == daddiu $s4, $zero, 0 # encoding: [0x64,0x14,0x00,0x00] +0x64,0x15,0x00,0x00 == daddiu $s5, $zero, 0 # encoding: [0x64,0x15,0x00,0x00] +0x64,0x16,0x00,0x00 == daddiu $s6, $zero, 0 # encoding: [0x64,0x16,0x00,0x00] +0x64,0x17,0x00,0x00 == daddiu $s7, $zero, 0 # encoding: [0x64,0x17,0x00,0x00] +0x64,0x18,0x00,0x00 == daddiu $t8, $zero, 0 # encoding: [0x64,0x18,0x00,0x00] +0x64,0x19,0x00,0x00 == daddiu $t9, $zero, 0 # encoding: [0x64,0x19,0x00,0x00] +0x64,0x1a,0x00,0x00 == daddiu $kt0, $zero, 0 # encoding: [0x64,0x1a,0x00,0x00] +0x64,0x1b,0x00,0x00 == daddiu $kt1, $zero, 0 # encoding: [0x64,0x1b,0x00,0x00] +0x64,0x1c,0x00,0x00 == daddiu $gp, $zero, 0 # encoding: [0x64,0x1c,0x00,0x00] +0x64,0x1d,0x00,0x00 == daddiu $sp, $zero, 0 # encoding: [0x64,0x1d,0x00,0x00] +0x64,0x1e,0x00,0x00 == daddiu $s8, $zero, 0 # encoding: [0x64,0x1e,0x00,0x00] +0x64,0x1f,0x00,0x00 == daddiu $ra, $zero, 0 # encoding: [0x64,0x1f,0x00,0x00] diff --git a/suite/MC/Mips/mips_directives.s.cs b/suite/MC/Mips/mips_directives.s.cs index 07d10c971..27428ab96 100644 --- a/suite/MC/Mips/mips_directives.s.cs +++ b/suite/MC/Mips/mips_directives.s.cs @@ -1,12 +1,21 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x10,0x00,0x01,0x4d = b 1336 -0x08,0x00,0x01,0x4c = j 1328 -0x0c,0x00,0x01,0x4c = jal 1328 -0x10,0x00,0x01,0x4d = b 1336 -0x00,0x00,0x00,0x00 = nop -0x08,0x00,0x01,0x4c = j 1328 -0x00,0x00,0x00,0x00 = nop -0x0c,0x00,0x01,0x4c = jal 1328 -0x00,0x00,0x00,0x00 = nop -0x46,0x00,0x39,0x85 = abs.s $f6, $f7 -0x01,0xef,0x18,0x24 = and $v1, $t7, $t7 + +0x10,0x00,0x01,0x4d == b 1332 # encoding: [0x10,0x00,0x01,0x4d] +0x08,0x00,0x01,0x4c == j 1328 # encoding: [0x08,0x00,0x01,0x4c] +0x0c,0x00,0x01,0x4c == jal 1328 # encoding: [0x0c,0x00,0x01,0x4c] +0x10,0x00,0x01,0x4d == b 1332 # encoding: [0x10,0x00,0x01,0x4d] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x08,0x00,0x01,0x4c == j 1328 # encoding: [0x08,0x00,0x01,0x4c] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x0c,0x00,0x01,0x4c == jal 1328 # encoding: [0x0c,0x00,0x01,0x4c] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x46,0x00,0x39,0x85 == abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85] +0x3c,0x01, == lui $1, %hi($tmp7) # encoding: [0x3c,0x01,A,A] +0x4c,0xa0,0x00,0x01 == ldxc1 $f0, $zero($5) # encoding: [0x4c,0xa0,0x00,0x01] +0x4c,0xa6,0x00,0x05 == luxc1 $f0, $6($5) # encoding: [0x4c,0xa6,0x00,0x05] +0x4c,0xa2,0x01,0x80 == lwxc1 $f6, $2($5) # encoding: [0x4c,0xa2,0x01,0x80] +0x00,0x26,0x4f,0xba == drotr $9, $6, 30 # encoding: [0x00,0x26,0x4f,0xba] +0x7d,0x6a,0x39,0x8a == lbux $7, $10($11) # encoding: [0x7d,0x6a,0x39,0x8a] +0x7c,0xe6,0x29,0x0a == lhx $5, $6($7) # encoding: [0x7c,0xe6,0x29,0x0a] +0x7d,0x47,0x10,0x31 == append $7, $10, 2 # encoding: [0x7d,0x47,0x10,0x31] +0x7c,0xc5,0x1c,0x31 == balign $5, $6, 3 # encoding: [0x7c,0xc5,0x1c,0x31] diff --git a/suite/MC/Mips/nabi-regs.s.cs b/suite/MC/Mips/nabi-regs.s.cs index 0d14e2935..4e56f803f 100644 --- a/suite/MC/Mips/nabi-regs.s.cs +++ b/suite/MC/Mips/nabi-regs.s.cs @@ -1,12 +1,13 @@ # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None -0x02,0x04,0x80,0x20 = add $s0, $s0, $a0 -0x02,0x06,0x80,0x20 = add $s0, $s0, $a2 -0x02,0x07,0x80,0x20 = add $s0, $s0, $a3 -0x02,0x08,0x80,0x20 = add $s0, $s0, $t0 -0x02,0x09,0x80,0x20 = add $s0, $s0, $t1 -0x02,0x0a,0x80,0x20 = add $s0, $s0, $t2 -0x02,0x0b,0x80,0x20 = add $s0, $s0, $t3 -0x02,0x0c,0x80,0x20 = add $s0, $s0, $t4 -0x02,0x0d,0x80,0x20 = add $s0, $s0, $t5 -0x02,0x0e,0x80,0x20 = add $s0, $s0, $t6 -0x02,0x0f,0x80,0x20 = add $s0, $s0, $t7 + +0x02,0x04,0x80,0x20 == add $16, $16, $4 # encoding: [0x02,0x04,0x80,0x20] +0x02,0x06,0x80,0x20 == add $16, $16, $6 # encoding: [0x02,0x06,0x80,0x20] +0x02,0x07,0x80,0x20 == add $16, $16, $7 # encoding: [0x02,0x07,0x80,0x20] +0x02,0x08,0x80,0x20 == add $16, $16, $8 # encoding: [0x02,0x08,0x80,0x20] +0x02,0x09,0x80,0x20 == add $16, $16, $9 # encoding: [0x02,0x09,0x80,0x20] +0x02,0x0a,0x80,0x20 == add $16, $16, $10 # encoding: [0x02,0x0a,0x80,0x20] +0x02,0x0b,0x80,0x20 == add $16, $16, $11 # encoding: [0x02,0x0b,0x80,0x20] +0x02,0x0c,0x80,0x20 == add $16, $16, $12 # encoding: [0x02,0x0c,0x80,0x20] +0x02,0x0d,0x80,0x20 == add $16, $16, $13 # encoding: [0x02,0x0d,0x80,0x20] +0x02,0x0e,0x80,0x20 == add $16, $16, $14 # encoding: [0x02,0x0e,0x80,0x20] +0x02,0x0f,0x80,0x20 == add $16, $16, $15 # encoding: [0x02,0x0f,0x80,0x20] diff --git a/suite/MC/Mips/test_2r.s.cs b/suite/MC/Mips/test_2r.s.cs index 94b37bc8e..0a88e00bc 100644 --- a/suite/MC/Mips/test_2r.s.cs +++ b/suite/MC/Mips/test_2r.s.cs @@ -1,16 +1,17 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x7b,0x00,0x4f,0x9e = fill.b $w30, $t1 -0x7b,0x01,0xbf,0xde = fill.h $w31, $s7 -0x7b,0x02,0xc4,0x1e = fill.w $w16, $t8 -0x7b,0x08,0x05,0x5e = nloc.b $w21, $w0 -0x7b,0x09,0xfc,0x9e = nloc.h $w18, $w31 -0x7b,0x0a,0xb8,0x9e = nloc.w $w2, $w23 -0x7b,0x0b,0x51,0x1e = nloc.d $w4, $w10 -0x7b,0x0c,0x17,0xde = nlzc.b $w31, $w2 -0x7b,0x0d,0xb6,0xde = nlzc.h $w27, $w22 -0x7b,0x0e,0xea,0x9e = nlzc.w $w10, $w29 -0x7b,0x0f,0x4e,0x5e = nlzc.d $w25, $w9 -0x7b,0x04,0x95,0x1e = pcnt.b $w20, $w18 -0x7b,0x05,0x40,0x1e = pcnt.h $w0, $w8 -0x7b,0x06,0x4d,0xde = pcnt.w $w23, $w9 -0x7b,0x07,0xc5,0x5e = pcnt.d $w21, $w24 + +0x7b,0x00,0x4f,0x9e == fill.b $w30, $9 # encoding: [0x7b,0x00,0x4f,0x9e] +0x7b,0x01,0xbf,0xde == fill.h $w31, $23 # encoding: [0x7b,0x01,0xbf,0xde] +0x7b,0x02,0xc4,0x1e == fill.w $w16, $24 # encoding: [0x7b,0x02,0xc4,0x1e] +0x7b,0x08,0x05,0x5e == nloc.b $w21, $w0 # encoding: [0x7b,0x08,0x05,0x5e] +0x7b,0x09,0xfc,0x9e == nloc.h $w18, $w31 # encoding: [0x7b,0x09,0xfc,0x9e] +0x7b,0x0a,0xb8,0x9e == nloc.w $w2, $w23 # encoding: [0x7b,0x0a,0xb8,0x9e] +0x7b,0x0b,0x51,0x1e == nloc.d $w4, $w10 # encoding: [0x7b,0x0b,0x51,0x1e] +0x7b,0x0c,0x17,0xde == nlzc.b $w31, $w2 # encoding: [0x7b,0x0c,0x17,0xde] +0x7b,0x0d,0xb6,0xde == nlzc.h $w27, $w22 # encoding: [0x7b,0x0d,0xb6,0xde] +0x7b,0x0e,0xea,0x9e == nlzc.w $w10, $w29 # encoding: [0x7b,0x0e,0xea,0x9e] +0x7b,0x0f,0x4e,0x5e == nlzc.d $w25, $w9 # encoding: [0x7b,0x0f,0x4e,0x5e] +0x7b,0x04,0x95,0x1e == pcnt.b $w20, $w18 # encoding: [0x7b,0x04,0x95,0x1e] +0x7b,0x05,0x40,0x1e == pcnt.h $w0, $w8 # encoding: [0x7b,0x05,0x40,0x1e] +0x7b,0x06,0x4d,0xde == pcnt.w $w23, $w9 # encoding: [0x7b,0x06,0x4d,0xde] +0x7b,0x07,0xc5,0x5e == pcnt.d $w21, $w24 # encoding: [0x7b,0x07,0xc5,0x5e] diff --git a/suite/MC/Mips/test_2rf.s.cs b/suite/MC/Mips/test_2rf.s.cs index 2e9560638..689e24c5d 100644 --- a/suite/MC/Mips/test_2rf.s.cs +++ b/suite/MC/Mips/test_2rf.s.cs @@ -1,33 +1,34 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x7b,0x20,0x66,0x9e = fclass.w $w26, $w12 -0x7b,0x21,0x8e,0x1e = fclass.d $w24, $w17 -0x7b,0x30,0x02,0x1e = fexupl.w $w8, $w0 -0x7b,0x31,0xec,0x5e = fexupl.d $w17, $w29 -0x7b,0x32,0x23,0x5e = fexupr.w $w13, $w4 -0x7b,0x33,0x11,0x5e = fexupr.d $w5, $w2 -0x7b,0x3c,0xed,0x1e = ffint_s.w $w20, $w29 -0x7b,0x3d,0x7b,0x1e = ffint_s.d $w12, $w15 -0x7b,0x3e,0xd9,0xde = ffint_u.w $w7, $w27 -0x7b,0x3f,0x84,0xde = ffint_u.d $w19, $w16 -0x7b,0x34,0x6f,0xde = ffql.w $w31, $w13 -0x7b,0x35,0x6b,0x1e = ffql.d $w12, $w13 -0x7b,0x36,0xf6,0xde = ffqr.w $w27, $w30 -0x7b,0x37,0x7f,0x9e = ffqr.d $w30, $w15 -0x7b,0x2e,0xfe,0x5e = flog2.w $w25, $w31 -0x7b,0x2f,0x54,0x9e = flog2.d $w18, $w10 -0x7b,0x2c,0x79,0xde = frint.w $w7, $w15 -0x7b,0x2d,0xb5,0x5e = frint.d $w21, $w22 -0x7b,0x2a,0x04,0xde = frcp.w $w19, $w0 -0x7b,0x2b,0x71,0x1e = frcp.d $w4, $w14 -0x7b,0x28,0x8b,0x1e = frsqrt.w $w12, $w17 -0x7b,0x29,0x5d,0xde = frsqrt.d $w23, $w11 -0x7b,0x26,0x58,0x1e = fsqrt.w $w0, $w11 -0x7b,0x27,0x63,0xde = fsqrt.d $w15, $w12 -0x7b,0x38,0x2f,0x9e = ftint_s.w $w30, $w5 -0x7b,0x39,0xb9,0x5e = ftint_s.d $w5, $w23 -0x7b,0x3a,0x75,0x1e = ftint_u.w $w20, $w14 -0x7b,0x3b,0xad,0xde = ftint_u.d $w23, $w21 -0x7b,0x22,0x8f,0x5e = ftrunc_s.w $w29, $w17 -0x7b,0x23,0xdb,0x1e = ftrunc_s.d $w12, $w27 -0x7b,0x24,0x7c,0x5e = ftrunc_u.w $w17, $w15 -0x7b,0x25,0xd9,0x5e = ftrunc_u.d $w5, $w27 + +0x7b,0x20,0x66,0x9e == fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e] +0x7b,0x21,0x8e,0x1e == fclass.d $w24, $w17 # encoding: [0x7b,0x21,0x8e,0x1e] +0x7b,0x30,0x02,0x1e == fexupl.w $w8, $w0 # encoding: [0x7b,0x30,0x02,0x1e] +0x7b,0x31,0xec,0x5e == fexupl.d $w17, $w29 # encoding: [0x7b,0x31,0xec,0x5e] +0x7b,0x32,0x23,0x5e == fexupr.w $w13, $w4 # encoding: [0x7b,0x32,0x23,0x5e] +0x7b,0x33,0x11,0x5e == fexupr.d $w5, $w2 # encoding: [0x7b,0x33,0x11,0x5e] +0x7b,0x3c,0xed,0x1e == ffint_s.w $w20, $w29 # encoding: [0x7b,0x3c,0xed,0x1e] +0x7b,0x3d,0x7b,0x1e == ffint_s.d $w12, $w15 # encoding: [0x7b,0x3d,0x7b,0x1e] +0x7b,0x3e,0xd9,0xde == ffint_u.w $w7, $w27 # encoding: [0x7b,0x3e,0xd9,0xde] +0x7b,0x3f,0x84,0xde == ffint_u.d $w19, $w16 # encoding: [0x7b,0x3f,0x84,0xde] +0x7b,0x34,0x6f,0xde == ffql.w $w31, $w13 # encoding: [0x7b,0x34,0x6f,0xde] +0x7b,0x35,0x6b,0x1e == ffql.d $w12, $w13 # encoding: [0x7b,0x35,0x6b,0x1e] +0x7b,0x36,0xf6,0xde == ffqr.w $w27, $w30 # encoding: [0x7b,0x36,0xf6,0xde] +0x7b,0x37,0x7f,0x9e == ffqr.d $w30, $w15 # encoding: [0x7b,0x37,0x7f,0x9e] +0x7b,0x2e,0xfe,0x5e == flog2.w $w25, $w31 # encoding: [0x7b,0x2e,0xfe,0x5e] +0x7b,0x2f,0x54,0x9e == flog2.d $w18, $w10 # encoding: [0x7b,0x2f,0x54,0x9e] +0x7b,0x2c,0x79,0xde == frint.w $w7, $w15 # encoding: [0x7b,0x2c,0x79,0xde] +0x7b,0x2d,0xb5,0x5e == frint.d $w21, $w22 # encoding: [0x7b,0x2d,0xb5,0x5e] +0x7b,0x2a,0x04,0xde == frcp.w $w19, $w0 # encoding: [0x7b,0x2a,0x04,0xde] +0x7b,0x2b,0x71,0x1e == frcp.d $w4, $w14 # encoding: [0x7b,0x2b,0x71,0x1e] +0x7b,0x28,0x8b,0x1e == frsqrt.w $w12, $w17 # encoding: [0x7b,0x28,0x8b,0x1e] +0x7b,0x29,0x5d,0xde == frsqrt.d $w23, $w11 # encoding: [0x7b,0x29,0x5d,0xde] +0x7b,0x26,0x58,0x1e == fsqrt.w $w0, $w11 # encoding: [0x7b,0x26,0x58,0x1e] +0x7b,0x27,0x63,0xde == fsqrt.d $w15, $w12 # encoding: [0x7b,0x27,0x63,0xde] +0x7b,0x38,0x2f,0x9e == ftint_s.w $w30, $w5 # encoding: [0x7b,0x38,0x2f,0x9e] +0x7b,0x39,0xb9,0x5e == ftint_s.d $w5, $w23 # encoding: [0x7b,0x39,0xb9,0x5e] +0x7b,0x3a,0x75,0x1e == ftint_u.w $w20, $w14 # encoding: [0x7b,0x3a,0x75,0x1e] +0x7b,0x3b,0xad,0xde == ftint_u.d $w23, $w21 # encoding: [0x7b,0x3b,0xad,0xde] +0x7b,0x22,0x8f,0x5e == ftrunc_s.w $w29, $w17 # encoding: [0x7b,0x22,0x8f,0x5e] +0x7b,0x23,0xdb,0x1e == ftrunc_s.d $w12, $w27 # encoding: [0x7b,0x23,0xdb,0x1e] +0x7b,0x24,0x7c,0x5e == ftrunc_u.w $w17, $w15 # encoding: [0x7b,0x24,0x7c,0x5e] +0x7b,0x25,0xd9,0x5e == ftrunc_u.d $w5, $w27 # encoding: [0x7b,0x25,0xd9,0x5e] diff --git a/suite/MC/Mips/test_3r.s.cs b/suite/MC/Mips/test_3r.s.cs index 99f5de917..0b9546713 100644 --- a/suite/MC/Mips/test_3r.s.cs +++ b/suite/MC/Mips/test_3r.s.cs @@ -1,243 +1,244 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x04,0x4e,0x90 = add_a.b $w26, $w9, $w4 -0x78,0x3f,0xdd,0xd0 = add_a.h $w23, $w27, $w31 -0x78,0x56,0x32,0xd0 = add_a.w $w11, $w6, $w22 -0x78,0x60,0x51,0x90 = add_a.d $w6, $w10, $w0 -0x78,0x93,0xc4,0xd0 = adds_a.b $w19, $w24, $w19 -0x78,0xa4,0x36,0x50 = adds_a.h $w25, $w6, $w4 -0x78,0xdb,0x8e,0x50 = adds_a.w $w25, $w17, $w27 -0x78,0xfa,0x93,0xd0 = adds_a.d $w15, $w18, $w26 -0x79,0x13,0x5f,0x50 = adds_s.b $w29, $w11, $w19 -0x79,0x3a,0xb9,0x50 = adds_s.h $w5, $w23, $w26 -0x79,0x4d,0x74,0x10 = adds_s.w $w16, $w14, $w13 -0x79,0x7c,0x70,0x90 = adds_s.d $w2, $w14, $w28 -0x79,0x8e,0x88,0xd0 = adds_u.b $w3, $w17, $w14 -0x79,0xa4,0xf2,0x90 = adds_u.h $w10, $w30, $w4 -0x79,0xd4,0x93,0xd0 = adds_u.w $w15, $w18, $w20 -0x79,0xe9,0x57,0x90 = adds_u.d $w30, $w10, $w9 -0x78,0x15,0xa6,0x0e = addv.b $w24, $w20, $w21 -0x78,0x3b,0x69,0x0e = addv.h $w4, $w13, $w27 -0x78,0x4e,0x5c,0xce = addv.w $w19, $w11, $w14 -0x78,0x7f,0xa8,0x8e = addv.d $w2, $w21, $w31 -0x7a,0x03,0x85,0xd1 = asub_s.b $w23, $w16, $w3 -0x7a,0x39,0x8d,0x91 = asub_s.h $w22, $w17, $w25 -0x7a,0x49,0x0e,0x11 = asub_s.w $w24, $w1, $w9 -0x7a,0x6c,0x63,0x51 = asub_s.d $w13, $w12, $w12 -0x7a,0x8b,0xea,0x91 = asub_u.b $w10, $w29, $w11 -0x7a,0xaf,0x4c,0x91 = asub_u.h $w18, $w9, $w15 -0x7a,0xdf,0x9a,0x91 = asub_u.w $w10, $w19, $w31 -0x7a,0xe0,0x54,0x51 = asub_u.d $w17, $w10, $w0 -0x7a,0x01,0x28,0x90 = ave_s.b $w2, $w5, $w1 -0x7a,0x29,0x9c,0x10 = ave_s.h $w16, $w19, $w9 -0x7a,0x45,0xfc,0x50 = ave_s.w $w17, $w31, $w5 -0x7a,0x6a,0xce,0xd0 = ave_s.d $w27, $w25, $w10 -0x7a,0x89,0x9c,0x10 = ave_u.b $w16, $w19, $w9 -0x7a,0xab,0xe7,0x10 = ave_u.h $w28, $w28, $w11 -0x7a,0xcb,0x62,0xd0 = ave_u.w $w11, $w12, $w11 -0x7a,0xfc,0x9f,0x90 = ave_u.d $w30, $w19, $w28 -0x7b,0x02,0x86,0x90 = aver_s.b $w26, $w16, $w2 -0x7b,0x3b,0xdf,0xd0 = aver_s.h $w31, $w27, $w27 -0x7b,0x59,0x97,0x10 = aver_s.w $w28, $w18, $w25 -0x7b,0x7b,0xaf,0x50 = aver_s.d $w29, $w21, $w27 -0x7b,0x83,0xd7,0x50 = aver_u.b $w29, $w26, $w3 -0x7b,0xa9,0x94,0x90 = aver_u.h $w18, $w18, $w9 -0x7b,0xdd,0xcc,0x50 = aver_u.w $w17, $w25, $w29 -0x7b,0xf3,0xb5,0x90 = aver_u.d $w22, $w22, $w19 -0x79,0x9d,0x78,0x8d = bclr.b $w2, $w15, $w29 -0x79,0xbc,0xac,0x0d = bclr.h $w16, $w21, $w28 -0x79,0xc9,0x14,0xcd = bclr.w $w19, $w2, $w9 -0x79,0xe4,0xfe,0xcd = bclr.d $w27, $w31, $w4 -0x7b,0x18,0x81,0x4d = binsl.b $w5, $w16, $w24 -0x7b,0x2a,0x2f,0x8d = binsl.h $w30, $w5, $w10 -0x7b,0x4d,0x7b,0x8d = binsl.w $w14, $w15, $w13 -0x7b,0x6c,0xa5,0xcd = binsl.d $w23, $w20, $w12 -0x7b,0x82,0x5d,0x8d = binsr.b $w22, $w11, $w2 -0x7b,0xa6,0xd0,0x0d = binsr.h $w0, $w26, $w6 -0x7b,0xdc,0x1e,0x8d = binsr.w $w26, $w3, $w28 -0x7b,0xf5,0x00,0x0d = binsr.d $w0, $w0, $w21 -0x7a,0x98,0x58,0x0d = bneg.b $w0, $w11, $w24 -0x7a,0xa4,0x87,0x0d = bneg.h $w28, $w16, $w4 -0x7a,0xd3,0xd0,0xcd = bneg.w $w3, $w26, $w19 -0x7a,0xef,0xeb,0x4d = bneg.d $w13, $w29, $w15 -0x7a,0x1f,0x2f,0xcd = bset.b $w31, $w5, $w31 -0x7a,0x26,0x63,0x8d = bset.h $w14, $w12, $w6 -0x7a,0x4c,0x4f,0xcd = bset.w $w31, $w9, $w12 -0x7a,0x65,0xb1,0x4d = bset.d $w5, $w22, $w5 -0x78,0x12,0xff,0xcf = ceq.b $w31, $w31, $w18 -0x78,0x29,0xda,0x8f = ceq.h $w10, $w27, $w9 -0x78,0x4e,0x2a,0x4f = ceq.w $w9, $w5, $w14 -0x78,0x60,0x89,0x4f = ceq.d $w5, $w17, $w0 -0x7a,0x09,0x25,0xcf = cle_s.b $w23, $w4, $w9 -0x7a,0x33,0xdd,0x8f = cle_s.h $w22, $w27, $w19 -0x7a,0x4a,0xd7,0x8f = cle_s.w $w30, $w26, $w10 -0x7a,0x6a,0x2c,0x8f = cle_s.d $w18, $w5, $w10 -0x7a,0x80,0xc8,0x4f = cle_u.b $w1, $w25, $w0 -0x7a,0xbd,0x01,0xcf = cle_u.h $w7, $w0, $w29 -0x7a,0xc1,0x96,0x4f = cle_u.w $w25, $w18, $w1 -0x7a,0xfe,0x01,0x8f = cle_u.d $w6, $w0, $w30 -0x79,0x15,0x16,0x4f = clt_s.b $w25, $w2, $w21 -0x79,0x29,0x98,0x8f = clt_s.h $w2, $w19, $w9 -0x79,0x50,0x45,0xcf = clt_s.w $w23, $w8, $w16 -0x79,0x6c,0xf1,0xcf = clt_s.d $w7, $w30, $w12 -0x79,0x8d,0xf8,0x8f = clt_u.b $w2, $w31, $w13 -0x79,0xb7,0xfc,0x0f = clt_u.h $w16, $w31, $w23 -0x79,0xc9,0xc0,0xcf = clt_u.w $w3, $w24, $w9 -0x79,0xe1,0x01,0xcf = clt_u.d $w7, $w0, $w1 -0x7a,0x12,0x1f,0x52 = div_s.b $w29, $w3, $w18 -0x7a,0x2d,0x84,0x52 = div_s.h $w17, $w16, $w13 -0x7a,0x5e,0xc9,0x12 = div_s.w $w4, $w25, $w30 -0x7a,0x74,0x4f,0xd2 = div_s.d $w31, $w9, $w20 -0x7a,0x8a,0xe9,0x92 = div_u.b $w6, $w29, $w10 -0x7a,0xae,0xae,0x12 = div_u.h $w24, $w21, $w14 -0x7a,0xd9,0x77,0x52 = div_u.w $w29, $w14, $w25 -0x7a,0xf5,0x0f,0xd2 = div_u.d $w31, $w1, $w21 -0x78,0x39,0xb5,0xd3 = dotp_s.h $w23, $w22, $w25 -0x78,0x45,0x75,0x13 = dotp_s.w $w20, $w14, $w5 -0x78,0x76,0x14,0x53 = dotp_s.d $w17, $w2, $w22 -0x78,0xa6,0x13,0x53 = dotp_u.h $w13, $w2, $w6 -0x78,0xd5,0xb3,0xd3 = dotp_u.w $w15, $w22, $w21 -0x78,0xfa,0x81,0x13 = dotp_u.d $w4, $w16, $w26 -0x79,0x36,0xe0,0x53 = dpadd_s.h $w1, $w28, $w22 -0x79,0x4c,0x0a,0x93 = dpadd_s.w $w10, $w1, $w12 -0x79,0x7b,0xa8,0xd3 = dpadd_s.d $w3, $w21, $w27 -0x79,0xb4,0x2c,0x53 = dpadd_u.h $w17, $w5, $w20 -0x79,0xd0,0x46,0x13 = dpadd_u.w $w24, $w8, $w16 -0x79,0xf0,0xeb,0xd3 = dpadd_u.d $w15, $w29, $w16 -0x7a,0x2c,0x59,0x13 = dpsub_s.h $w4, $w11, $w12 -0x7a,0x46,0x39,0x13 = dpsub_s.w $w4, $w7, $w6 -0x7a,0x7c,0x67,0xd3 = dpsub_s.d $w31, $w12, $w28 -0x7a,0xb1,0xc9,0x13 = dpsub_u.h $w4, $w25, $w17 -0x7a,0xd0,0xcc,0xd3 = dpsub_u.w $w19, $w25, $w16 -0x7a,0xfa,0x51,0xd3 = dpsub_u.d $w7, $w10, $w26 -0x7a,0x22,0xc7,0x15 = hadd_s.h $w28, $w24, $w2 -0x7a,0x4b,0x8e,0x15 = hadd_s.w $w24, $w17, $w11 -0x7a,0x74,0x7c,0x55 = hadd_s.d $w17, $w15, $w20 -0x7a,0xb1,0xeb,0x15 = hadd_u.h $w12, $w29, $w17 -0x7a,0xc6,0x2a,0x55 = hadd_u.w $w9, $w5, $w6 -0x7a,0xe6,0xa0,0x55 = hadd_u.d $w1, $w20, $w6 -0x7b,0x3d,0x74,0x15 = hsub_s.h $w16, $w14, $w29 -0x7b,0x4b,0x6a,0x55 = hsub_s.w $w9, $w13, $w11 -0x7b,0x6e,0x97,0x95 = hsub_s.d $w30, $w18, $w14 -0x7b,0xae,0x61,0xd5 = hsub_u.h $w7, $w12, $w14 -0x7b,0xc5,0x2d,0x55 = hsub_u.w $w21, $w5, $w5 -0x7b,0xff,0x62,0xd5 = hsub_u.d $w11, $w12, $w31 -0x7b,0x1e,0x84,0x94 = ilvev.b $w18, $w16, $w30 -0x7b,0x2d,0x03,0x94 = ilvev.h $w14, $w0, $w13 -0x7b,0x56,0xcb,0x14 = ilvev.w $w12, $w25, $w22 -0x7b,0x63,0xdf,0x94 = ilvev.d $w30, $w27, $w3 -0x7a,0x15,0x1f,0x54 = ilvl.b $w29, $w3, $w21 -0x7a,0x31,0x56,0xd4 = ilvl.h $w27, $w10, $w17 -0x7a,0x40,0x09,0x94 = ilvl.w $w6, $w1, $w0 -0x7a,0x78,0x80,0xd4 = ilvl.d $w3, $w16, $w24 -0x7b,0x94,0x2a,0xd4 = ilvod.b $w11, $w5, $w20 -0x7b,0xbf,0x6c,0x94 = ilvod.h $w18, $w13, $w31 -0x7b,0xd8,0x87,0x54 = ilvod.w $w29, $w16, $w24 -0x7b,0xfd,0x65,0x94 = ilvod.d $w22, $w12, $w29 -0x7a,0x86,0xf1,0x14 = ilvr.b $w4, $w30, $w6 -0x7a,0xbd,0x9f,0x14 = ilvr.h $w28, $w19, $w29 -0x7a,0xd5,0xa4,0x94 = ilvr.w $w18, $w20, $w21 -0x7a,0xec,0xf5,0xd4 = ilvr.d $w23, $w30, $w12 -0x78,0x9d,0xfc,0x52 = maddv.b $w17, $w31, $w29 -0x78,0xa9,0xc1,0xd2 = maddv.h $w7, $w24, $w9 -0x78,0xd4,0xb5,0x92 = maddv.w $w22, $w22, $w20 -0x78,0xf4,0xd7,0x92 = maddv.d $w30, $w26, $w20 -0x7b,0x17,0x5d,0xce = max_a.b $w23, $w11, $w23 -0x7b,0x3e,0x2d,0x0e = max_a.h $w20, $w5, $w30 -0x7b,0x5e,0x91,0xce = max_a.w $w7, $w18, $w30 -0x7b,0x7f,0x42,0x0e = max_a.d $w8, $w8, $w31 -0x79,0x13,0x0a,0x8e = max_s.b $w10, $w1, $w19 -0x79,0x31,0xeb,0xce = max_s.h $w15, $w29, $w17 -0x79,0x4e,0xeb,0xce = max_s.w $w15, $w29, $w14 -0x79,0x63,0xc6,0x4e = max_s.d $w25, $w24, $w3 -0x79,0x85,0xc3,0x0e = max_u.b $w12, $w24, $w5 -0x79,0xa7,0x31,0x4e = max_u.h $w5, $w6, $w7 -0x79,0xc7,0x24,0x0e = max_u.w $w16, $w4, $w7 -0x79,0xf8,0x66,0x8e = max_u.d $w26, $w12, $w24 -0x7b,0x81,0xd1,0x0e = min_a.b $w4, $w26, $w1 -0x7b,0xbf,0x6b,0x0e = min_a.h $w12, $w13, $w31 -0x7b,0xc0,0xa7,0x0e = min_a.w $w28, $w20, $w0 -0x7b,0xf3,0xa3,0x0e = min_a.d $w12, $w20, $w19 -0x7a,0x0e,0x1c,0xce = min_s.b $w19, $w3, $w14 -0x7a,0x28,0xae,0xce = min_s.h $w27, $w21, $w8 -0x7a,0x5e,0x70,0x0e = min_s.w $w0, $w14, $w30 -0x7a,0x75,0x41,0x8e = min_s.d $w6, $w8, $w21 -0x7a,0x88,0xd5,0x8e = min_u.b $w22, $w26, $w8 -0x7a,0xac,0xd9,0xce = min_u.h $w7, $w27, $w12 -0x7a,0xce,0xa2,0x0e = min_u.w $w8, $w20, $w14 -0x7a,0xef,0x76,0x8e = min_u.d $w26, $w14, $w15 -0x7b,0x1a,0x0c,0x92 = mod_s.b $w18, $w1, $w26 -0x7b,0x3c,0xf7,0xd2 = mod_s.h $w31, $w30, $w28 -0x7b,0x4d,0x30,0x92 = mod_s.w $w2, $w6, $w13 -0x7b,0x76,0xdd,0x52 = mod_s.d $w21, $w27, $w22 -0x7b,0x8d,0x3c,0x12 = mod_u.b $w16, $w7, $w13 -0x7b,0xa7,0x46,0x12 = mod_u.h $w24, $w8, $w7 -0x7b,0xd1,0x17,0x92 = mod_u.w $w30, $w2, $w17 -0x7b,0xf9,0x17,0xd2 = mod_u.d $w31, $w2, $w25 -0x79,0x0c,0x2b,0x92 = msubv.b $w14, $w5, $w12 -0x79,0x3e,0x39,0x92 = msubv.h $w6, $w7, $w30 -0x79,0x55,0x13,0x52 = msubv.w $w13, $w2, $w21 -0x79,0x7b,0x74,0x12 = msubv.d $w16, $w14, $w27 -0x78,0x0d,0x1d,0x12 = mulv.b $w20, $w3, $w13 -0x78,0x2e,0xd6,0xd2 = mulv.h $w27, $w26, $w14 -0x78,0x43,0xea,0x92 = mulv.w $w10, $w29, $w3 -0x78,0x7d,0x99,0xd2 = mulv.d $w7, $w19, $w29 -0x79,0x07,0xd9,0x54 = pckev.b $w5, $w27, $w7 -0x79,0x3b,0x20,0x54 = pckev.h $w1, $w4, $w27 -0x79,0x40,0xa7,0x94 = pckev.w $w30, $w20, $w0 -0x79,0x6f,0x09,0x94 = pckev.d $w6, $w1, $w15 -0x79,0x9e,0xe4,0x94 = pckod.b $w18, $w28, $w30 -0x79,0xa8,0x2e,0x94 = pckod.h $w26, $w5, $w8 -0x79,0xc2,0x22,0x54 = pckod.w $w9, $w4, $w2 -0x79,0xf4,0xb7,0x94 = pckod.d $w30, $w22, $w20 -0x78,0x0c,0xb9,0x54 = sld.b $w5, $w23[$t4] -0x78,0x23,0xb8,0x54 = sld.h $w1, $w23[$v1] -0x78,0x49,0x45,0x14 = sld.w $w20, $w8[$t1] -0x78,0x7e,0xb9,0xd4 = sld.d $w7, $w23[$fp] -0x78,0x11,0x00,0xcd = sll.b $w3, $w0, $w17 -0x78,0x23,0xdc,0x4d = sll.h $w17, $w27, $w3 -0x78,0x46,0x3c,0x0d = sll.w $w16, $w7, $w6 -0x78,0x7a,0x02,0x4d = sll.d $w9, $w0, $w26 -0x78,0x81,0x0f,0x14 = splat.b $w28, $w1[$at] -0x78,0xab,0x58,0x94 = splat.h $w2, $w11[$t3] -0x78,0xcb,0x05,0x94 = splat.w $w22, $w0[$t3] -0x78,0xe2,0x00,0x14 = splat.d $w0, $w0[$v0] -0x78,0x91,0x27,0x0d = sra.b $w28, $w4, $w17 -0x78,0xa3,0x4b,0x4d = sra.h $w13, $w9, $w3 -0x78,0xd3,0xae,0xcd = sra.w $w27, $w21, $w19 -0x78,0xf7,0x47,0x8d = sra.d $w30, $w8, $w23 -0x78,0x92,0x94,0xd5 = srar.b $w19, $w18, $w18 -0x78,0xa8,0xb9,0xd5 = srar.h $w7, $w23, $w8 -0x78,0xc2,0x60,0x55 = srar.w $w1, $w12, $w2 -0x78,0xee,0x3d,0x55 = srar.d $w21, $w7, $w14 -0x79,0x13,0x1b,0x0d = srl.b $w12, $w3, $w19 -0x79,0x34,0xfd,0xcd = srl.h $w23, $w31, $w20 -0x79,0x4b,0xdc,0x8d = srl.w $w18, $w27, $w11 -0x79,0x7a,0x60,0xcd = srl.d $w3, $w12, $w26 -0x79,0x0b,0xab,0xd5 = srlr.b $w15, $w21, $w11 -0x79,0x33,0x6d,0x55 = srlr.h $w21, $w13, $w19 -0x79,0x43,0xf1,0x95 = srlr.w $w6, $w30, $w3 -0x79,0x6e,0x10,0x55 = srlr.d $w1, $w2, $w14 -0x78,0x01,0x7e,0x51 = subs_s.b $w25, $w15, $w1 -0x78,0x36,0xcf,0x11 = subs_s.h $w28, $w25, $w22 -0x78,0x55,0x62,0x91 = subs_s.w $w10, $w12, $w21 -0x78,0x72,0xa1,0x11 = subs_s.d $w4, $w20, $w18 -0x78,0x99,0x35,0x51 = subs_u.b $w21, $w6, $w25 -0x78,0xa7,0x50,0xd1 = subs_u.h $w3, $w10, $w7 -0x78,0xca,0x7a,0x51 = subs_u.w $w9, $w15, $w10 -0x78,0xea,0x99,0xd1 = subs_u.d $w7, $w19, $w10 -0x79,0x0c,0x39,0x91 = subsus_u.b $w6, $w7, $w12 -0x79,0x33,0xe9,0x91 = subsus_u.h $w6, $w29, $w19 -0x79,0x47,0x79,0xd1 = subsus_u.w $w7, $w15, $w7 -0x79,0x6f,0x1a,0x51 = subsus_u.d $w9, $w3, $w15 -0x79,0x9f,0x1d,0x91 = subsuu_s.b $w22, $w3, $w31 -0x79,0xb6,0xbc,0xd1 = subsuu_s.h $w19, $w23, $w22 -0x79,0xcd,0x52,0x51 = subsuu_s.w $w9, $w10, $w13 -0x79,0xe0,0x31,0x51 = subsuu_s.d $w5, $w6, $w0 -0x78,0x93,0x69,0x8e = subv.b $w6, $w13, $w19 -0x78,0xac,0xc9,0x0e = subv.h $w4, $w25, $w12 -0x78,0xcb,0xde,0xce = subv.w $w27, $w27, $w11 -0x78,0xea,0xc2,0x4e = subv.d $w9, $w24, $w10 -0x78,0x05,0x80,0xd5 = vshf.b $w3, $w16, $w5 -0x78,0x28,0x9d,0x15 = vshf.h $w20, $w19, $w8 -0x78,0x59,0xf4,0x15 = vshf.w $w16, $w30, $w25 -0x78,0x6f,0x5c,0xd5 = vshf.d $w19, $w11, $w15 + +0x78,0x04,0x4e,0x90 == add_a.b $w26, $w9, $w4 # encoding: [0x78,0x04,0x4e,0x90] +0x78,0x3f,0xdd,0xd0 == add_a.h $w23, $w27, $w31 # encoding: [0x78,0x3f,0xdd,0xd0] +0x78,0x56,0x32,0xd0 == add_a.w $w11, $w6, $w22 # encoding: [0x78,0x56,0x32,0xd0] +0x78,0x60,0x51,0x90 == add_a.d $w6, $w10, $w0 # encoding: [0x78,0x60,0x51,0x90] +0x78,0x93,0xc4,0xd0 == adds_a.b $w19, $w24, $w19 # encoding: [0x78,0x93,0xc4,0xd0] +0x78,0xa4,0x36,0x50 == adds_a.h $w25, $w6, $w4 # encoding: [0x78,0xa4,0x36,0x50] +0x78,0xdb,0x8e,0x50 == adds_a.w $w25, $w17, $w27 # encoding: [0x78,0xdb,0x8e,0x50] +0x78,0xfa,0x93,0xd0 == adds_a.d $w15, $w18, $w26 # encoding: [0x78,0xfa,0x93,0xd0] +0x79,0x13,0x5f,0x50 == adds_s.b $w29, $w11, $w19 # encoding: [0x79,0x13,0x5f,0x50] +0x79,0x3a,0xb9,0x50 == adds_s.h $w5, $w23, $w26 # encoding: [0x79,0x3a,0xb9,0x50] +0x79,0x4d,0x74,0x10 == adds_s.w $w16, $w14, $w13 # encoding: [0x79,0x4d,0x74,0x10] +0x79,0x7c,0x70,0x90 == adds_s.d $w2, $w14, $w28 # encoding: [0x79,0x7c,0x70,0x90] +0x79,0x8e,0x88,0xd0 == adds_u.b $w3, $w17, $w14 # encoding: [0x79,0x8e,0x88,0xd0] +0x79,0xa4,0xf2,0x90 == adds_u.h $w10, $w30, $w4 # encoding: [0x79,0xa4,0xf2,0x90] +0x79,0xd4,0x93,0xd0 == adds_u.w $w15, $w18, $w20 # encoding: [0x79,0xd4,0x93,0xd0] +0x79,0xe9,0x57,0x90 == adds_u.d $w30, $w10, $w9 # encoding: [0x79,0xe9,0x57,0x90] +0x78,0x15,0xa6,0x0e == addv.b $w24, $w20, $w21 # encoding: [0x78,0x15,0xa6,0x0e] +0x78,0x3b,0x69,0x0e == addv.h $w4, $w13, $w27 # encoding: [0x78,0x3b,0x69,0x0e] +0x78,0x4e,0x5c,0xce == addv.w $w19, $w11, $w14 # encoding: [0x78,0x4e,0x5c,0xce] +0x78,0x7f,0xa8,0x8e == addv.d $w2, $w21, $w31 # encoding: [0x78,0x7f,0xa8,0x8e] +0x7a,0x03,0x85,0xd1 == asub_s.b $w23, $w16, $w3 # encoding: [0x7a,0x03,0x85,0xd1] +0x7a,0x39,0x8d,0x91 == asub_s.h $w22, $w17, $w25 # encoding: [0x7a,0x39,0x8d,0x91] +0x7a,0x49,0x0e,0x11 == asub_s.w $w24, $w1, $w9 # encoding: [0x7a,0x49,0x0e,0x11] +0x7a,0x6c,0x63,0x51 == asub_s.d $w13, $w12, $w12 # encoding: [0x7a,0x6c,0x63,0x51] +0x7a,0x8b,0xea,0x91 == asub_u.b $w10, $w29, $w11 # encoding: [0x7a,0x8b,0xea,0x91] +0x7a,0xaf,0x4c,0x91 == asub_u.h $w18, $w9, $w15 # encoding: [0x7a,0xaf,0x4c,0x91] +0x7a,0xdf,0x9a,0x91 == asub_u.w $w10, $w19, $w31 # encoding: [0x7a,0xdf,0x9a,0x91] +0x7a,0xe0,0x54,0x51 == asub_u.d $w17, $w10, $w0 # encoding: [0x7a,0xe0,0x54,0x51] +0x7a,0x01,0x28,0x90 == ave_s.b $w2, $w5, $w1 # encoding: [0x7a,0x01,0x28,0x90] +0x7a,0x29,0x9c,0x10 == ave_s.h $w16, $w19, $w9 # encoding: [0x7a,0x29,0x9c,0x10] +0x7a,0x45,0xfc,0x50 == ave_s.w $w17, $w31, $w5 # encoding: [0x7a,0x45,0xfc,0x50] +0x7a,0x6a,0xce,0xd0 == ave_s.d $w27, $w25, $w10 # encoding: [0x7a,0x6a,0xce,0xd0] +0x7a,0x89,0x9c,0x10 == ave_u.b $w16, $w19, $w9 # encoding: [0x7a,0x89,0x9c,0x10] +0x7a,0xab,0xe7,0x10 == ave_u.h $w28, $w28, $w11 # encoding: [0x7a,0xab,0xe7,0x10] +0x7a,0xcb,0x62,0xd0 == ave_u.w $w11, $w12, $w11 # encoding: [0x7a,0xcb,0x62,0xd0] +0x7a,0xfc,0x9f,0x90 == ave_u.d $w30, $w19, $w28 # encoding: [0x7a,0xfc,0x9f,0x90] +0x7b,0x02,0x86,0x90 == aver_s.b $w26, $w16, $w2 # encoding: [0x7b,0x02,0x86,0x90] +0x7b,0x3b,0xdf,0xd0 == aver_s.h $w31, $w27, $w27 # encoding: [0x7b,0x3b,0xdf,0xd0] +0x7b,0x59,0x97,0x10 == aver_s.w $w28, $w18, $w25 # encoding: [0x7b,0x59,0x97,0x10] +0x7b,0x7b,0xaf,0x50 == aver_s.d $w29, $w21, $w27 # encoding: [0x7b,0x7b,0xaf,0x50] +0x7b,0x83,0xd7,0x50 == aver_u.b $w29, $w26, $w3 # encoding: [0x7b,0x83,0xd7,0x50] +0x7b,0xa9,0x94,0x90 == aver_u.h $w18, $w18, $w9 # encoding: [0x7b,0xa9,0x94,0x90] +0x7b,0xdd,0xcc,0x50 == aver_u.w $w17, $w25, $w29 # encoding: [0x7b,0xdd,0xcc,0x50] +0x7b,0xf3,0xb5,0x90 == aver_u.d $w22, $w22, $w19 # encoding: [0x7b,0xf3,0xb5,0x90] +0x79,0x9d,0x78,0x8d == bclr.b $w2, $w15, $w29 # encoding: [0x79,0x9d,0x78,0x8d] +0x79,0xbc,0xac,0x0d == bclr.h $w16, $w21, $w28 # encoding: [0x79,0xbc,0xac,0x0d] +0x79,0xc9,0x14,0xcd == bclr.w $w19, $w2, $w9 # encoding: [0x79,0xc9,0x14,0xcd] +0x79,0xe4,0xfe,0xcd == bclr.d $w27, $w31, $w4 # encoding: [0x79,0xe4,0xfe,0xcd] +0x7b,0x18,0x81,0x4d == binsl.b $w5, $w16, $w24 # encoding: [0x7b,0x18,0x81,0x4d] +0x7b,0x2a,0x2f,0x8d == binsl.h $w30, $w5, $w10 # encoding: [0x7b,0x2a,0x2f,0x8d] +0x7b,0x4d,0x7b,0x8d == binsl.w $w14, $w15, $w13 # encoding: [0x7b,0x4d,0x7b,0x8d] +0x7b,0x6c,0xa5,0xcd == binsl.d $w23, $w20, $w12 # encoding: [0x7b,0x6c,0xa5,0xcd] +0x7b,0x82,0x5d,0x8d == binsr.b $w22, $w11, $w2 # encoding: [0x7b,0x82,0x5d,0x8d] +0x7b,0xa6,0xd0,0x0d == binsr.h $w0, $w26, $w6 # encoding: [0x7b,0xa6,0xd0,0x0d] +0x7b,0xdc,0x1e,0x8d == binsr.w $w26, $w3, $w28 # encoding: [0x7b,0xdc,0x1e,0x8d] +0x7b,0xf5,0x00,0x0d == binsr.d $w0, $w0, $w21 # encoding: [0x7b,0xf5,0x00,0x0d] +0x7a,0x98,0x58,0x0d == bneg.b $w0, $w11, $w24 # encoding: [0x7a,0x98,0x58,0x0d] +0x7a,0xa4,0x87,0x0d == bneg.h $w28, $w16, $w4 # encoding: [0x7a,0xa4,0x87,0x0d] +0x7a,0xd3,0xd0,0xcd == bneg.w $w3, $w26, $w19 # encoding: [0x7a,0xd3,0xd0,0xcd] +0x7a,0xef,0xeb,0x4d == bneg.d $w13, $w29, $w15 # encoding: [0x7a,0xef,0xeb,0x4d] +0x7a,0x1f,0x2f,0xcd == bset.b $w31, $w5, $w31 # encoding: [0x7a,0x1f,0x2f,0xcd] +0x7a,0x26,0x63,0x8d == bset.h $w14, $w12, $w6 # encoding: [0x7a,0x26,0x63,0x8d] +0x7a,0x4c,0x4f,0xcd == bset.w $w31, $w9, $w12 # encoding: [0x7a,0x4c,0x4f,0xcd] +0x7a,0x65,0xb1,0x4d == bset.d $w5, $w22, $w5 # encoding: [0x7a,0x65,0xb1,0x4d] +0x78,0x12,0xff,0xcf == ceq.b $w31, $w31, $w18 # encoding: [0x78,0x12,0xff,0xcf] +0x78,0x29,0xda,0x8f == ceq.h $w10, $w27, $w9 # encoding: [0x78,0x29,0xda,0x8f] +0x78,0x4e,0x2a,0x4f == ceq.w $w9, $w5, $w14 # encoding: [0x78,0x4e,0x2a,0x4f] +0x78,0x60,0x89,0x4f == ceq.d $w5, $w17, $w0 # encoding: [0x78,0x60,0x89,0x4f] +0x7a,0x09,0x25,0xcf == cle_s.b $w23, $w4, $w9 # encoding: [0x7a,0x09,0x25,0xcf] +0x7a,0x33,0xdd,0x8f == cle_s.h $w22, $w27, $w19 # encoding: [0x7a,0x33,0xdd,0x8f] +0x7a,0x4a,0xd7,0x8f == cle_s.w $w30, $w26, $w10 # encoding: [0x7a,0x4a,0xd7,0x8f] +0x7a,0x6a,0x2c,0x8f == cle_s.d $w18, $w5, $w10 # encoding: [0x7a,0x6a,0x2c,0x8f] +0x7a,0x80,0xc8,0x4f == cle_u.b $w1, $w25, $w0 # encoding: [0x7a,0x80,0xc8,0x4f] +0x7a,0xbd,0x01,0xcf == cle_u.h $w7, $w0, $w29 # encoding: [0x7a,0xbd,0x01,0xcf] +0x7a,0xc1,0x96,0x4f == cle_u.w $w25, $w18, $w1 # encoding: [0x7a,0xc1,0x96,0x4f] +0x7a,0xfe,0x01,0x8f == cle_u.d $w6, $w0, $w30 # encoding: [0x7a,0xfe,0x01,0x8f] +0x79,0x15,0x16,0x4f == clt_s.b $w25, $w2, $w21 # encoding: [0x79,0x15,0x16,0x4f] +0x79,0x29,0x98,0x8f == clt_s.h $w2, $w19, $w9 # encoding: [0x79,0x29,0x98,0x8f] +0x79,0x50,0x45,0xcf == clt_s.w $w23, $w8, $w16 # encoding: [0x79,0x50,0x45,0xcf] +0x79,0x6c,0xf1,0xcf == clt_s.d $w7, $w30, $w12 # encoding: [0x79,0x6c,0xf1,0xcf] +0x79,0x8d,0xf8,0x8f == clt_u.b $w2, $w31, $w13 # encoding: [0x79,0x8d,0xf8,0x8f] +0x79,0xb7,0xfc,0x0f == clt_u.h $w16, $w31, $w23 # encoding: [0x79,0xb7,0xfc,0x0f] +0x79,0xc9,0xc0,0xcf == clt_u.w $w3, $w24, $w9 # encoding: [0x79,0xc9,0xc0,0xcf] +0x79,0xe1,0x01,0xcf == clt_u.d $w7, $w0, $w1 # encoding: [0x79,0xe1,0x01,0xcf] +0x7a,0x12,0x1f,0x52 == div_s.b $w29, $w3, $w18 # encoding: [0x7a,0x12,0x1f,0x52] +0x7a,0x2d,0x84,0x52 == div_s.h $w17, $w16, $w13 # encoding: [0x7a,0x2d,0x84,0x52] +0x7a,0x5e,0xc9,0x12 == div_s.w $w4, $w25, $w30 # encoding: [0x7a,0x5e,0xc9,0x12] +0x7a,0x74,0x4f,0xd2 == div_s.d $w31, $w9, $w20 # encoding: [0x7a,0x74,0x4f,0xd2] +0x7a,0x8a,0xe9,0x92 == div_u.b $w6, $w29, $w10 # encoding: [0x7a,0x8a,0xe9,0x92] +0x7a,0xae,0xae,0x12 == div_u.h $w24, $w21, $w14 # encoding: [0x7a,0xae,0xae,0x12] +0x7a,0xd9,0x77,0x52 == div_u.w $w29, $w14, $w25 # encoding: [0x7a,0xd9,0x77,0x52] +0x7a,0xf5,0x0f,0xd2 == div_u.d $w31, $w1, $w21 # encoding: [0x7a,0xf5,0x0f,0xd2] +0x78,0x39,0xb5,0xd3 == dotp_s.h $w23, $w22, $w25 # encoding: [0x78,0x39,0xb5,0xd3] +0x78,0x45,0x75,0x13 == dotp_s.w $w20, $w14, $w5 # encoding: [0x78,0x45,0x75,0x13] +0x78,0x76,0x14,0x53 == dotp_s.d $w17, $w2, $w22 # encoding: [0x78,0x76,0x14,0x53] +0x78,0xa6,0x13,0x53 == dotp_u.h $w13, $w2, $w6 # encoding: [0x78,0xa6,0x13,0x53] +0x78,0xd5,0xb3,0xd3 == dotp_u.w $w15, $w22, $w21 # encoding: [0x78,0xd5,0xb3,0xd3] +0x78,0xfa,0x81,0x13 == dotp_u.d $w4, $w16, $w26 # encoding: [0x78,0xfa,0x81,0x13] +0x79,0x36,0xe0,0x53 == dpadd_s.h $w1, $w28, $w22 # encoding: [0x79,0x36,0xe0,0x53] +0x79,0x4c,0x0a,0x93 == dpadd_s.w $w10, $w1, $w12 # encoding: [0x79,0x4c,0x0a,0x93] +0x79,0x7b,0xa8,0xd3 == dpadd_s.d $w3, $w21, $w27 # encoding: [0x79,0x7b,0xa8,0xd3] +0x79,0xb4,0x2c,0x53 == dpadd_u.h $w17, $w5, $w20 # encoding: [0x79,0xb4,0x2c,0x53] +0x79,0xd0,0x46,0x13 == dpadd_u.w $w24, $w8, $w16 # encoding: [0x79,0xd0,0x46,0x13] +0x79,0xf0,0xeb,0xd3 == dpadd_u.d $w15, $w29, $w16 # encoding: [0x79,0xf0,0xeb,0xd3] +0x7a,0x2c,0x59,0x13 == dpsub_s.h $w4, $w11, $w12 # encoding: [0x7a,0x2c,0x59,0x13] +0x7a,0x46,0x39,0x13 == dpsub_s.w $w4, $w7, $w6 # encoding: [0x7a,0x46,0x39,0x13] +0x7a,0x7c,0x67,0xd3 == dpsub_s.d $w31, $w12, $w28 # encoding: [0x7a,0x7c,0x67,0xd3] +0x7a,0xb1,0xc9,0x13 == dpsub_u.h $w4, $w25, $w17 # encoding: [0x7a,0xb1,0xc9,0x13] +0x7a,0xd0,0xcc,0xd3 == dpsub_u.w $w19, $w25, $w16 # encoding: [0x7a,0xd0,0xcc,0xd3] +0x7a,0xfa,0x51,0xd3 == dpsub_u.d $w7, $w10, $w26 # encoding: [0x7a,0xfa,0x51,0xd3] +0x7a,0x22,0xc7,0x15 == hadd_s.h $w28, $w24, $w2 # encoding: [0x7a,0x22,0xc7,0x15] +0x7a,0x4b,0x8e,0x15 == hadd_s.w $w24, $w17, $w11 # encoding: [0x7a,0x4b,0x8e,0x15] +0x7a,0x74,0x7c,0x55 == hadd_s.d $w17, $w15, $w20 # encoding: [0x7a,0x74,0x7c,0x55] +0x7a,0xb1,0xeb,0x15 == hadd_u.h $w12, $w29, $w17 # encoding: [0x7a,0xb1,0xeb,0x15] +0x7a,0xc6,0x2a,0x55 == hadd_u.w $w9, $w5, $w6 # encoding: [0x7a,0xc6,0x2a,0x55] +0x7a,0xe6,0xa0,0x55 == hadd_u.d $w1, $w20, $w6 # encoding: [0x7a,0xe6,0xa0,0x55] +0x7b,0x3d,0x74,0x15 == hsub_s.h $w16, $w14, $w29 # encoding: [0x7b,0x3d,0x74,0x15] +0x7b,0x4b,0x6a,0x55 == hsub_s.w $w9, $w13, $w11 # encoding: [0x7b,0x4b,0x6a,0x55] +0x7b,0x6e,0x97,0x95 == hsub_s.d $w30, $w18, $w14 # encoding: [0x7b,0x6e,0x97,0x95] +0x7b,0xae,0x61,0xd5 == hsub_u.h $w7, $w12, $w14 # encoding: [0x7b,0xae,0x61,0xd5] +0x7b,0xc5,0x2d,0x55 == hsub_u.w $w21, $w5, $w5 # encoding: [0x7b,0xc5,0x2d,0x55] +0x7b,0xff,0x62,0xd5 == hsub_u.d $w11, $w12, $w31 # encoding: [0x7b,0xff,0x62,0xd5] +0x7b,0x1e,0x84,0x94 == ilvev.b $w18, $w16, $w30 # encoding: [0x7b,0x1e,0x84,0x94] +0x7b,0x2d,0x03,0x94 == ilvev.h $w14, $w0, $w13 # encoding: [0x7b,0x2d,0x03,0x94] +0x7b,0x56,0xcb,0x14 == ilvev.w $w12, $w25, $w22 # encoding: [0x7b,0x56,0xcb,0x14] +0x7b,0x63,0xdf,0x94 == ilvev.d $w30, $w27, $w3 # encoding: [0x7b,0x63,0xdf,0x94] +0x7a,0x15,0x1f,0x54 == ilvl.b $w29, $w3, $w21 # encoding: [0x7a,0x15,0x1f,0x54] +0x7a,0x31,0x56,0xd4 == ilvl.h $w27, $w10, $w17 # encoding: [0x7a,0x31,0x56,0xd4] +0x7a,0x40,0x09,0x94 == ilvl.w $w6, $w1, $w0 # encoding: [0x7a,0x40,0x09,0x94] +0x7a,0x78,0x80,0xd4 == ilvl.d $w3, $w16, $w24 # encoding: [0x7a,0x78,0x80,0xd4] +0x7b,0x94,0x2a,0xd4 == ilvod.b $w11, $w5, $w20 # encoding: [0x7b,0x94,0x2a,0xd4] +0x7b,0xbf,0x6c,0x94 == ilvod.h $w18, $w13, $w31 # encoding: [0x7b,0xbf,0x6c,0x94] +0x7b,0xd8,0x87,0x54 == ilvod.w $w29, $w16, $w24 # encoding: [0x7b,0xd8,0x87,0x54] +0x7b,0xfd,0x65,0x94 == ilvod.d $w22, $w12, $w29 # encoding: [0x7b,0xfd,0x65,0x94] +0x7a,0x86,0xf1,0x14 == ilvr.b $w4, $w30, $w6 # encoding: [0x7a,0x86,0xf1,0x14] +0x7a,0xbd,0x9f,0x14 == ilvr.h $w28, $w19, $w29 # encoding: [0x7a,0xbd,0x9f,0x14] +0x7a,0xd5,0xa4,0x94 == ilvr.w $w18, $w20, $w21 # encoding: [0x7a,0xd5,0xa4,0x94] +0x7a,0xec,0xf5,0xd4 == ilvr.d $w23, $w30, $w12 # encoding: [0x7a,0xec,0xf5,0xd4] +0x78,0x9d,0xfc,0x52 == maddv.b $w17, $w31, $w29 # encoding: [0x78,0x9d,0xfc,0x52] +0x78,0xa9,0xc1,0xd2 == maddv.h $w7, $w24, $w9 # encoding: [0x78,0xa9,0xc1,0xd2] +0x78,0xd4,0xb5,0x92 == maddv.w $w22, $w22, $w20 # encoding: [0x78,0xd4,0xb5,0x92] +0x78,0xf4,0xd7,0x92 == maddv.d $w30, $w26, $w20 # encoding: [0x78,0xf4,0xd7,0x92] +0x7b,0x17,0x5d,0xce == max_a.b $w23, $w11, $w23 # encoding: [0x7b,0x17,0x5d,0xce] +0x7b,0x3e,0x2d,0x0e == max_a.h $w20, $w5, $w30 # encoding: [0x7b,0x3e,0x2d,0x0e] +0x7b,0x5e,0x91,0xce == max_a.w $w7, $w18, $w30 # encoding: [0x7b,0x5e,0x91,0xce] +0x7b,0x7f,0x42,0x0e == max_a.d $w8, $w8, $w31 # encoding: [0x7b,0x7f,0x42,0x0e] +0x79,0x13,0x0a,0x8e == max_s.b $w10, $w1, $w19 # encoding: [0x79,0x13,0x0a,0x8e] +0x79,0x31,0xeb,0xce == max_s.h $w15, $w29, $w17 # encoding: [0x79,0x31,0xeb,0xce] +0x79,0x4e,0xeb,0xce == max_s.w $w15, $w29, $w14 # encoding: [0x79,0x4e,0xeb,0xce] +0x79,0x63,0xc6,0x4e == max_s.d $w25, $w24, $w3 # encoding: [0x79,0x63,0xc6,0x4e] +0x79,0x85,0xc3,0x0e == max_u.b $w12, $w24, $w5 # encoding: [0x79,0x85,0xc3,0x0e] +0x79,0xa7,0x31,0x4e == max_u.h $w5, $w6, $w7 # encoding: [0x79,0xa7,0x31,0x4e] +0x79,0xc7,0x24,0x0e == max_u.w $w16, $w4, $w7 # encoding: [0x79,0xc7,0x24,0x0e] +0x79,0xf8,0x66,0x8e == max_u.d $w26, $w12, $w24 # encoding: [0x79,0xf8,0x66,0x8e] +0x7b,0x81,0xd1,0x0e == min_a.b $w4, $w26, $w1 # encoding: [0x7b,0x81,0xd1,0x0e] +0x7b,0xbf,0x6b,0x0e == min_a.h $w12, $w13, $w31 # encoding: [0x7b,0xbf,0x6b,0x0e] +0x7b,0xc0,0xa7,0x0e == min_a.w $w28, $w20, $w0 # encoding: [0x7b,0xc0,0xa7,0x0e] +0x7b,0xf3,0xa3,0x0e == min_a.d $w12, $w20, $w19 # encoding: [0x7b,0xf3,0xa3,0x0e] +0x7a,0x0e,0x1c,0xce == min_s.b $w19, $w3, $w14 # encoding: [0x7a,0x0e,0x1c,0xce] +0x7a,0x28,0xae,0xce == min_s.h $w27, $w21, $w8 # encoding: [0x7a,0x28,0xae,0xce] +0x7a,0x5e,0x70,0x0e == min_s.w $w0, $w14, $w30 # encoding: [0x7a,0x5e,0x70,0x0e] +0x7a,0x75,0x41,0x8e == min_s.d $w6, $w8, $w21 # encoding: [0x7a,0x75,0x41,0x8e] +0x7a,0x88,0xd5,0x8e == min_u.b $w22, $w26, $w8 # encoding: [0x7a,0x88,0xd5,0x8e] +0x7a,0xac,0xd9,0xce == min_u.h $w7, $w27, $w12 # encoding: [0x7a,0xac,0xd9,0xce] +0x7a,0xce,0xa2,0x0e == min_u.w $w8, $w20, $w14 # encoding: [0x7a,0xce,0xa2,0x0e] +0x7a,0xef,0x76,0x8e == min_u.d $w26, $w14, $w15 # encoding: [0x7a,0xef,0x76,0x8e] +0x7b,0x1a,0x0c,0x92 == mod_s.b $w18, $w1, $w26 # encoding: [0x7b,0x1a,0x0c,0x92] +0x7b,0x3c,0xf7,0xd2 == mod_s.h $w31, $w30, $w28 # encoding: [0x7b,0x3c,0xf7,0xd2] +0x7b,0x4d,0x30,0x92 == mod_s.w $w2, $w6, $w13 # encoding: [0x7b,0x4d,0x30,0x92] +0x7b,0x76,0xdd,0x52 == mod_s.d $w21, $w27, $w22 # encoding: [0x7b,0x76,0xdd,0x52] +0x7b,0x8d,0x3c,0x12 == mod_u.b $w16, $w7, $w13 # encoding: [0x7b,0x8d,0x3c,0x12] +0x7b,0xa7,0x46,0x12 == mod_u.h $w24, $w8, $w7 # encoding: [0x7b,0xa7,0x46,0x12] +0x7b,0xd1,0x17,0x92 == mod_u.w $w30, $w2, $w17 # encoding: [0x7b,0xd1,0x17,0x92] +0x7b,0xf9,0x17,0xd2 == mod_u.d $w31, $w2, $w25 # encoding: [0x7b,0xf9,0x17,0xd2] +0x79,0x0c,0x2b,0x92 == msubv.b $w14, $w5, $w12 # encoding: [0x79,0x0c,0x2b,0x92] +0x79,0x3e,0x39,0x92 == msubv.h $w6, $w7, $w30 # encoding: [0x79,0x3e,0x39,0x92] +0x79,0x55,0x13,0x52 == msubv.w $w13, $w2, $w21 # encoding: [0x79,0x55,0x13,0x52] +0x79,0x7b,0x74,0x12 == msubv.d $w16, $w14, $w27 # encoding: [0x79,0x7b,0x74,0x12] +0x78,0x0d,0x1d,0x12 == mulv.b $w20, $w3, $w13 # encoding: [0x78,0x0d,0x1d,0x12] +0x78,0x2e,0xd6,0xd2 == mulv.h $w27, $w26, $w14 # encoding: [0x78,0x2e,0xd6,0xd2] +0x78,0x43,0xea,0x92 == mulv.w $w10, $w29, $w3 # encoding: [0x78,0x43,0xea,0x92] +0x78,0x7d,0x99,0xd2 == mulv.d $w7, $w19, $w29 # encoding: [0x78,0x7d,0x99,0xd2] +0x79,0x07,0xd9,0x54 == pckev.b $w5, $w27, $w7 # encoding: [0x79,0x07,0xd9,0x54] +0x79,0x3b,0x20,0x54 == pckev.h $w1, $w4, $w27 # encoding: [0x79,0x3b,0x20,0x54] +0x79,0x40,0xa7,0x94 == pckev.w $w30, $w20, $w0 # encoding: [0x79,0x40,0xa7,0x94] +0x79,0x6f,0x09,0x94 == pckev.d $w6, $w1, $w15 # encoding: [0x79,0x6f,0x09,0x94] +0x79,0x9e,0xe4,0x94 == pckod.b $w18, $w28, $w30 # encoding: [0x79,0x9e,0xe4,0x94] +0x79,0xa8,0x2e,0x94 == pckod.h $w26, $w5, $w8 # encoding: [0x79,0xa8,0x2e,0x94] +0x79,0xc2,0x22,0x54 == pckod.w $w9, $w4, $w2 # encoding: [0x79,0xc2,0x22,0x54] +0x79,0xf4,0xb7,0x94 == pckod.d $w30, $w22, $w20 # encoding: [0x79,0xf4,0xb7,0x94] +0x78,0x0c,0xb9,0x54 == sld.b $w5, $w23[$12] # encoding: [0x78,0x0c,0xb9,0x54] +0x78,0x23,0xb8,0x54 == sld.h $w1, $w23[$3] # encoding: [0x78,0x23,0xb8,0x54] +0x78,0x49,0x45,0x14 == sld.w $w20, $w8[$9] # encoding: [0x78,0x49,0x45,0x14] +0x78,0x7e,0xb9,0xd4 == sld.d $w7, $w23[$fp] # encoding: [0x78,0x7e,0xb9,0xd4] +0x78,0x11,0x00,0xcd == sll.b $w3, $w0, $w17 # encoding: [0x78,0x11,0x00,0xcd] +0x78,0x23,0xdc,0x4d == sll.h $w17, $w27, $w3 # encoding: [0x78,0x23,0xdc,0x4d] +0x78,0x46,0x3c,0x0d == sll.w $w16, $w7, $w6 # encoding: [0x78,0x46,0x3c,0x0d] +0x78,0x7a,0x02,0x4d == sll.d $w9, $w0, $w26 # encoding: [0x78,0x7a,0x02,0x4d] +0x78,0x81,0x0f,0x14 == splat.b $w28, $w1[$1] # encoding: [0x78,0x81,0x0f,0x14] +0x78,0xab,0x58,0x94 == splat.h $w2, $w11[$11] # encoding: [0x78,0xab,0x58,0x94] +0x78,0xcb,0x05,0x94 == splat.w $w22, $w0[$11] # encoding: [0x78,0xcb,0x05,0x94] +0x78,0xe2,0x00,0x14 == splat.d $w0, $w0[$2] # encoding: [0x78,0xe2,0x00,0x14] +0x78,0x91,0x27,0x0d == sra.b $w28, $w4, $w17 # encoding: [0x78,0x91,0x27,0x0d] +0x78,0xa3,0x4b,0x4d == sra.h $w13, $w9, $w3 # encoding: [0x78,0xa3,0x4b,0x4d] +0x78,0xd3,0xae,0xcd == sra.w $w27, $w21, $w19 # encoding: [0x78,0xd3,0xae,0xcd] +0x78,0xf7,0x47,0x8d == sra.d $w30, $w8, $w23 # encoding: [0x78,0xf7,0x47,0x8d] +0x78,0x92,0x94,0xd5 == srar.b $w19, $w18, $w18 # encoding: [0x78,0x92,0x94,0xd5] +0x78,0xa8,0xb9,0xd5 == srar.h $w7, $w23, $w8 # encoding: [0x78,0xa8,0xb9,0xd5] +0x78,0xc2,0x60,0x55 == srar.w $w1, $w12, $w2 # encoding: [0x78,0xc2,0x60,0x55] +0x78,0xee,0x3d,0x55 == srar.d $w21, $w7, $w14 # encoding: [0x78,0xee,0x3d,0x55] +0x79,0x13,0x1b,0x0d == srl.b $w12, $w3, $w19 # encoding: [0x79,0x13,0x1b,0x0d] +0x79,0x34,0xfd,0xcd == srl.h $w23, $w31, $w20 # encoding: [0x79,0x34,0xfd,0xcd] +0x79,0x4b,0xdc,0x8d == srl.w $w18, $w27, $w11 # encoding: [0x79,0x4b,0xdc,0x8d] +0x79,0x7a,0x60,0xcd == srl.d $w3, $w12, $w26 # encoding: [0x79,0x7a,0x60,0xcd] +0x79,0x0b,0xab,0xd5 == srlr.b $w15, $w21, $w11 # encoding: [0x79,0x0b,0xab,0xd5] +0x79,0x33,0x6d,0x55 == srlr.h $w21, $w13, $w19 # encoding: [0x79,0x33,0x6d,0x55] +0x79,0x43,0xf1,0x95 == srlr.w $w6, $w30, $w3 # encoding: [0x79,0x43,0xf1,0x95] +0x79,0x6e,0x10,0x55 == srlr.d $w1, $w2, $w14 # encoding: [0x79,0x6e,0x10,0x55] +0x78,0x01,0x7e,0x51 == subs_s.b $w25, $w15, $w1 # encoding: [0x78,0x01,0x7e,0x51] +0x78,0x36,0xcf,0x11 == subs_s.h $w28, $w25, $w22 # encoding: [0x78,0x36,0xcf,0x11] +0x78,0x55,0x62,0x91 == subs_s.w $w10, $w12, $w21 # encoding: [0x78,0x55,0x62,0x91] +0x78,0x72,0xa1,0x11 == subs_s.d $w4, $w20, $w18 # encoding: [0x78,0x72,0xa1,0x11] +0x78,0x99,0x35,0x51 == subs_u.b $w21, $w6, $w25 # encoding: [0x78,0x99,0x35,0x51] +0x78,0xa7,0x50,0xd1 == subs_u.h $w3, $w10, $w7 # encoding: [0x78,0xa7,0x50,0xd1] +0x78,0xca,0x7a,0x51 == subs_u.w $w9, $w15, $w10 # encoding: [0x78,0xca,0x7a,0x51] +0x78,0xea,0x99,0xd1 == subs_u.d $w7, $w19, $w10 # encoding: [0x78,0xea,0x99,0xd1] +0x79,0x0c,0x39,0x91 == subsus_u.b $w6, $w7, $w12 # encoding: [0x79,0x0c,0x39,0x91] +0x79,0x33,0xe9,0x91 == subsus_u.h $w6, $w29, $w19 # encoding: [0x79,0x33,0xe9,0x91] +0x79,0x47,0x79,0xd1 == subsus_u.w $w7, $w15, $w7 # encoding: [0x79,0x47,0x79,0xd1] +0x79,0x6f,0x1a,0x51 == subsus_u.d $w9, $w3, $w15 # encoding: [0x79,0x6f,0x1a,0x51] +0x79,0x9f,0x1d,0x91 == subsuu_s.b $w22, $w3, $w31 # encoding: [0x79,0x9f,0x1d,0x91] +0x79,0xb6,0xbc,0xd1 == subsuu_s.h $w19, $w23, $w22 # encoding: [0x79,0xb6,0xbc,0xd1] +0x79,0xcd,0x52,0x51 == subsuu_s.w $w9, $w10, $w13 # encoding: [0x79,0xcd,0x52,0x51] +0x79,0xe0,0x31,0x51 == subsuu_s.d $w5, $w6, $w0 # encoding: [0x79,0xe0,0x31,0x51] +0x78,0x93,0x69,0x8e == subv.b $w6, $w13, $w19 # encoding: [0x78,0x93,0x69,0x8e] +0x78,0xac,0xc9,0x0e == subv.h $w4, $w25, $w12 # encoding: [0x78,0xac,0xc9,0x0e] +0x78,0xcb,0xde,0xce == subv.w $w27, $w27, $w11 # encoding: [0x78,0xcb,0xde,0xce] +0x78,0xea,0xc2,0x4e == subv.d $w9, $w24, $w10 # encoding: [0x78,0xea,0xc2,0x4e] +0x78,0x05,0x80,0xd5 == vshf.b $w3, $w16, $w5 # encoding: [0x78,0x05,0x80,0xd5] +0x78,0x28,0x9d,0x15 == vshf.h $w20, $w19, $w8 # encoding: [0x78,0x28,0x9d,0x15] +0x78,0x59,0xf4,0x15 == vshf.w $w16, $w30, $w25 # encoding: [0x78,0x59,0xf4,0x15] +0x78,0x6f,0x5c,0xd5 == vshf.d $w19, $w11, $w15 # encoding: [0x78,0x6f,0x5c,0xd5] diff --git a/suite/MC/Mips/test_3rf.s.cs b/suite/MC/Mips/test_3rf.s.cs index 491162d48..7111745f2 100644 --- a/suite/MC/Mips/test_3rf.s.cs +++ b/suite/MC/Mips/test_3rf.s.cs @@ -1,83 +1,84 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x1c,0x9f,0x1b = fadd.w $w28, $w19, $w28 -0x78,0x3d,0x13,0x5b = fadd.d $w13, $w2, $w29 -0x78,0x19,0x5b,0x9a = fcaf.w $w14, $w11, $w25 -0x78,0x33,0x08,0x5a = fcaf.d $w1, $w1, $w19 -0x78,0x90,0xb8,0x5a = fceq.w $w1, $w23, $w16 -0x78,0xb0,0x40,0x1a = fceq.d $w0, $w8, $w16 -0x79,0x98,0x4c,0x1a = fcle.w $w16, $w9, $w24 -0x79,0xa1,0x76,0xda = fcle.d $w27, $w14, $w1 -0x79,0x08,0x47,0x1a = fclt.w $w28, $w8, $w8 -0x79,0x2b,0xcf,0x9a = fclt.d $w30, $w25, $w11 -0x78,0xd7,0x90,0x9c = fcne.w $w2, $w18, $w23 -0x78,0xef,0xa3,0x9c = fcne.d $w14, $w20, $w15 -0x78,0x59,0x92,0x9c = fcor.w $w10, $w18, $w25 -0x78,0x6b,0xcc,0x5c = fcor.d $w17, $w25, $w11 -0x78,0xd5,0x13,0x9a = fcueq.w $w14, $w2, $w21 -0x78,0xe7,0x1f,0x5a = fcueq.d $w29, $w3, $w7 -0x79,0xc3,0x2c,0x5a = fcule.w $w17, $w5, $w3 -0x79,0xfe,0x0f,0xda = fcule.d $w31, $w1, $w30 -0x79,0x49,0xc9,0x9a = fcult.w $w6, $w25, $w9 -0x79,0x71,0x46,0xda = fcult.d $w27, $w8, $w17 -0x78,0x48,0xa1,0x1a = fcun.w $w4, $w20, $w8 -0x78,0x63,0x5f,0x5a = fcun.d $w29, $w11, $w3 -0x78,0x93,0x93,0x5c = fcune.w $w13, $w18, $w19 -0x78,0xb5,0xd4,0x1c = fcune.d $w16, $w26, $w21 -0x78,0xc2,0xc3,0x5b = fdiv.w $w13, $w24, $w2 -0x78,0xf9,0x24,0xdb = fdiv.d $w19, $w4, $w25 -0x7a,0x10,0x02,0x1b = fexdo.h $w8, $w0, $w16 -0x7a,0x3b,0x68,0x1b = fexdo.w $w0, $w13, $w27 -0x79,0xc3,0x04,0x5b = fexp2.w $w17, $w0, $w3 -0x79,0xea,0x05,0x9b = fexp2.d $w22, $w0, $w10 -0x79,0x17,0x37,0x5b = fmadd.w $w29, $w6, $w23 -0x79,0x35,0xe2,0xdb = fmadd.d $w11, $w28, $w21 -0x7b,0x8d,0xb8,0x1b = fmax.w $w0, $w23, $w13 -0x7b,0xa8,0x96,0x9b = fmax.d $w26, $w18, $w8 -0x7b,0xca,0x82,0x9b = fmax_a.w $w10, $w16, $w10 -0x7b,0xf6,0x4f,0x9b = fmax_a.d $w30, $w9, $w22 -0x7b,0x1e,0x0e,0x1b = fmin.w $w24, $w1, $w30 -0x7b,0x2a,0xde,0xdb = fmin.d $w27, $w27, $w10 -0x7b,0x54,0xea,0x9b = fmin_a.w $w10, $w29, $w20 -0x7b,0x78,0xf3,0x5b = fmin_a.d $w13, $w30, $w24 -0x79,0x40,0xcc,0x5b = fmsub.w $w17, $w25, $w0 -0x79,0x70,0x92,0x1b = fmsub.d $w8, $w18, $w16 -0x78,0x8f,0x78,0xdb = fmul.w $w3, $w15, $w15 -0x78,0xaa,0xf2,0x5b = fmul.d $w9, $w30, $w10 -0x7a,0x0a,0x2e,0x5a = fsaf.w $w25, $w5, $w10 -0x7a,0x3d,0x1e,0x5a = fsaf.d $w25, $w3, $w29 -0x7a,0x8d,0x8a,0xda = fseq.w $w11, $w17, $w13 -0x7a,0xbf,0x07,0x5a = fseq.d $w29, $w0, $w31 -0x7b,0x9f,0xff,0x9a = fsle.w $w30, $w31, $w31 -0x7b,0xb8,0xbc,0x9a = fsle.d $w18, $w23, $w24 -0x7b,0x06,0x2b,0x1a = fslt.w $w12, $w5, $w6 -0x7b,0x35,0xd4,0x1a = fslt.d $w16, $w26, $w21 -0x7a,0xcc,0x0f,0x9c = fsne.w $w30, $w1, $w12 -0x7a,0xf7,0x6b,0x9c = fsne.d $w14, $w13, $w23 -0x7a,0x5b,0x6e,0xdc = fsor.w $w27, $w13, $w27 -0x7a,0x6b,0xc3,0x1c = fsor.d $w12, $w24, $w11 -0x78,0x41,0xd7,0xdb = fsub.w $w31, $w26, $w1 -0x78,0x7b,0x8c,0xdb = fsub.d $w19, $w17, $w27 -0x7a,0xd9,0xc4,0x1a = fsueq.w $w16, $w24, $w25 -0x7a,0xee,0x74,0x9a = fsueq.d $w18, $w14, $w14 -0x7b,0xcd,0xf5,0xda = fsule.w $w23, $w30, $w13 -0x7b,0xfa,0x58,0x9a = fsule.d $w2, $w11, $w26 -0x7b,0x56,0xd2,0xda = fsult.w $w11, $w26, $w22 -0x7b,0x7e,0xb9,0x9a = fsult.d $w6, $w23, $w30 -0x7a,0x5c,0x90,0xda = fsun.w $w3, $w18, $w28 -0x7a,0x73,0x5c,0x9a = fsun.d $w18, $w11, $w19 -0x7a,0x82,0xfc,0x1c = fsune.w $w16, $w31, $w2 -0x7a,0xb1,0xd0,0xdc = fsune.d $w3, $w26, $w17 -0x7a,0x98,0x24,0x1b = ftq.h $w16, $w4, $w24 -0x7a,0xb9,0x29,0x5b = ftq.w $w5, $w5, $w25 -0x79,0x4a,0xa4,0x1c = madd_q.h $w16, $w20, $w10 -0x79,0x69,0x17,0x1c = madd_q.w $w28, $w2, $w9 -0x7b,0x49,0x92,0x1c = maddr_q.h $w8, $w18, $w9 -0x7b,0x70,0x67,0x5c = maddr_q.w $w29, $w12, $w16 -0x79,0x8a,0xd6,0x1c = msub_q.h $w24, $w26, $w10 -0x79,0xbc,0xf3,0x5c = msub_q.w $w13, $w30, $w28 -0x7b,0x8b,0xab,0x1c = msubr_q.h $w12, $w21, $w11 -0x7b,0xb4,0x70,0x5c = msubr_q.w $w1, $w14, $w20 -0x79,0x1e,0x81,0x9c = mul_q.h $w6, $w16, $w30 -0x79,0x24,0x0c,0x1c = mul_q.w $w16, $w1, $w4 -0x7b,0x13,0xa1,0x9c = mulr_q.h $w6, $w20, $w19 -0x7b,0x34,0x0e,0xdc = mulr_q.w $w27, $w1, $w20 + +0x78,0x1c,0x9f,0x1b == fadd.w $w28, $w19, $w28 # encoding: [0x78,0x1c,0x9f,0x1b] +0x78,0x3d,0x13,0x5b == fadd.d $w13, $w2, $w29 # encoding: [0x78,0x3d,0x13,0x5b] +0x78,0x19,0x5b,0x9a == fcaf.w $w14, $w11, $w25 # encoding: [0x78,0x19,0x5b,0x9a] +0x78,0x33,0x08,0x5a == fcaf.d $w1, $w1, $w19 # encoding: [0x78,0x33,0x08,0x5a] +0x78,0x90,0xb8,0x5a == fceq.w $w1, $w23, $w16 # encoding: [0x78,0x90,0xb8,0x5a] +0x78,0xb0,0x40,0x1a == fceq.d $w0, $w8, $w16 # encoding: [0x78,0xb0,0x40,0x1a] +0x79,0x98,0x4c,0x1a == fcle.w $w16, $w9, $w24 # encoding: [0x79,0x98,0x4c,0x1a] +0x79,0xa1,0x76,0xda == fcle.d $w27, $w14, $w1 # encoding: [0x79,0xa1,0x76,0xda] +0x79,0x08,0x47,0x1a == fclt.w $w28, $w8, $w8 # encoding: [0x79,0x08,0x47,0x1a] +0x79,0x2b,0xcf,0x9a == fclt.d $w30, $w25, $w11 # encoding: [0x79,0x2b,0xcf,0x9a] +0x78,0xd7,0x90,0x9c == fcne.w $w2, $w18, $w23 # encoding: [0x78,0xd7,0x90,0x9c] +0x78,0xef,0xa3,0x9c == fcne.d $w14, $w20, $w15 # encoding: [0x78,0xef,0xa3,0x9c] +0x78,0x59,0x92,0x9c == fcor.w $w10, $w18, $w25 # encoding: [0x78,0x59,0x92,0x9c] +0x78,0x6b,0xcc,0x5c == fcor.d $w17, $w25, $w11 # encoding: [0x78,0x6b,0xcc,0x5c] +0x78,0xd5,0x13,0x9a == fcueq.w $w14, $w2, $w21 # encoding: [0x78,0xd5,0x13,0x9a] +0x78,0xe7,0x1f,0x5a == fcueq.d $w29, $w3, $w7 # encoding: [0x78,0xe7,0x1f,0x5a] +0x79,0xc3,0x2c,0x5a == fcule.w $w17, $w5, $w3 # encoding: [0x79,0xc3,0x2c,0x5a] +0x79,0xfe,0x0f,0xda == fcule.d $w31, $w1, $w30 # encoding: [0x79,0xfe,0x0f,0xda] +0x79,0x49,0xc9,0x9a == fcult.w $w6, $w25, $w9 # encoding: [0x79,0x49,0xc9,0x9a] +0x79,0x71,0x46,0xda == fcult.d $w27, $w8, $w17 # encoding: [0x79,0x71,0x46,0xda] +0x78,0x48,0xa1,0x1a == fcun.w $w4, $w20, $w8 # encoding: [0x78,0x48,0xa1,0x1a] +0x78,0x63,0x5f,0x5a == fcun.d $w29, $w11, $w3 # encoding: [0x78,0x63,0x5f,0x5a] +0x78,0x93,0x93,0x5c == fcune.w $w13, $w18, $w19 # encoding: [0x78,0x93,0x93,0x5c] +0x78,0xb5,0xd4,0x1c == fcune.d $w16, $w26, $w21 # encoding: [0x78,0xb5,0xd4,0x1c] +0x78,0xc2,0xc3,0x5b == fdiv.w $w13, $w24, $w2 # encoding: [0x78,0xc2,0xc3,0x5b] +0x78,0xf9,0x24,0xdb == fdiv.d $w19, $w4, $w25 # encoding: [0x78,0xf9,0x24,0xdb] +0x7a,0x10,0x02,0x1b == fexdo.h $w8, $w0, $w16 # encoding: [0x7a,0x10,0x02,0x1b] +0x7a,0x3b,0x68,0x1b == fexdo.w $w0, $w13, $w27 # encoding: [0x7a,0x3b,0x68,0x1b] +0x79,0xc3,0x04,0x5b == fexp2.w $w17, $w0, $w3 # encoding: [0x79,0xc3,0x04,0x5b] +0x79,0xea,0x05,0x9b == fexp2.d $w22, $w0, $w10 # encoding: [0x79,0xea,0x05,0x9b] +0x79,0x17,0x37,0x5b == fmadd.w $w29, $w6, $w23 # encoding: [0x79,0x17,0x37,0x5b] +0x79,0x35,0xe2,0xdb == fmadd.d $w11, $w28, $w21 # encoding: [0x79,0x35,0xe2,0xdb] +0x7b,0x8d,0xb8,0x1b == fmax.w $w0, $w23, $w13 # encoding: [0x7b,0x8d,0xb8,0x1b] +0x7b,0xa8,0x96,0x9b == fmax.d $w26, $w18, $w8 # encoding: [0x7b,0xa8,0x96,0x9b] +0x7b,0xca,0x82,0x9b == fmax_a.w $w10, $w16, $w10 # encoding: [0x7b,0xca,0x82,0x9b] +0x7b,0xf6,0x4f,0x9b == fmax_a.d $w30, $w9, $w22 # encoding: [0x7b,0xf6,0x4f,0x9b] +0x7b,0x1e,0x0e,0x1b == fmin.w $w24, $w1, $w30 # encoding: [0x7b,0x1e,0x0e,0x1b] +0x7b,0x2a,0xde,0xdb == fmin.d $w27, $w27, $w10 # encoding: [0x7b,0x2a,0xde,0xdb] +0x7b,0x54,0xea,0x9b == fmin_a.w $w10, $w29, $w20 # encoding: [0x7b,0x54,0xea,0x9b] +0x7b,0x78,0xf3,0x5b == fmin_a.d $w13, $w30, $w24 # encoding: [0x7b,0x78,0xf3,0x5b] +0x79,0x40,0xcc,0x5b == fmsub.w $w17, $w25, $w0 # encoding: [0x79,0x40,0xcc,0x5b] +0x79,0x70,0x92,0x1b == fmsub.d $w8, $w18, $w16 # encoding: [0x79,0x70,0x92,0x1b] +0x78,0x8f,0x78,0xdb == fmul.w $w3, $w15, $w15 # encoding: [0x78,0x8f,0x78,0xdb] +0x78,0xaa,0xf2,0x5b == fmul.d $w9, $w30, $w10 # encoding: [0x78,0xaa,0xf2,0x5b] +0x7a,0x0a,0x2e,0x5a == fsaf.w $w25, $w5, $w10 # encoding: [0x7a,0x0a,0x2e,0x5a] +0x7a,0x3d,0x1e,0x5a == fsaf.d $w25, $w3, $w29 # encoding: [0x7a,0x3d,0x1e,0x5a] +0x7a,0x8d,0x8a,0xda == fseq.w $w11, $w17, $w13 # encoding: [0x7a,0x8d,0x8a,0xda] +0x7a,0xbf,0x07,0x5a == fseq.d $w29, $w0, $w31 # encoding: [0x7a,0xbf,0x07,0x5a] +0x7b,0x9f,0xff,0x9a == fsle.w $w30, $w31, $w31 # encoding: [0x7b,0x9f,0xff,0x9a] +0x7b,0xb8,0xbc,0x9a == fsle.d $w18, $w23, $w24 # encoding: [0x7b,0xb8,0xbc,0x9a] +0x7b,0x06,0x2b,0x1a == fslt.w $w12, $w5, $w6 # encoding: [0x7b,0x06,0x2b,0x1a] +0x7b,0x35,0xd4,0x1a == fslt.d $w16, $w26, $w21 # encoding: [0x7b,0x35,0xd4,0x1a] +0x7a,0xcc,0x0f,0x9c == fsne.w $w30, $w1, $w12 # encoding: [0x7a,0xcc,0x0f,0x9c] +0x7a,0xf7,0x6b,0x9c == fsne.d $w14, $w13, $w23 # encoding: [0x7a,0xf7,0x6b,0x9c] +0x7a,0x5b,0x6e,0xdc == fsor.w $w27, $w13, $w27 # encoding: [0x7a,0x5b,0x6e,0xdc] +0x7a,0x6b,0xc3,0x1c == fsor.d $w12, $w24, $w11 # encoding: [0x7a,0x6b,0xc3,0x1c] +0x78,0x41,0xd7,0xdb == fsub.w $w31, $w26, $w1 # encoding: [0x78,0x41,0xd7,0xdb] +0x78,0x7b,0x8c,0xdb == fsub.d $w19, $w17, $w27 # encoding: [0x78,0x7b,0x8c,0xdb] +0x7a,0xd9,0xc4,0x1a == fsueq.w $w16, $w24, $w25 # encoding: [0x7a,0xd9,0xc4,0x1a] +0x7a,0xee,0x74,0x9a == fsueq.d $w18, $w14, $w14 # encoding: [0x7a,0xee,0x74,0x9a] +0x7b,0xcd,0xf5,0xda == fsule.w $w23, $w30, $w13 # encoding: [0x7b,0xcd,0xf5,0xda] +0x7b,0xfa,0x58,0x9a == fsule.d $w2, $w11, $w26 # encoding: [0x7b,0xfa,0x58,0x9a] +0x7b,0x56,0xd2,0xda == fsult.w $w11, $w26, $w22 # encoding: [0x7b,0x56,0xd2,0xda] +0x7b,0x7e,0xb9,0x9a == fsult.d $w6, $w23, $w30 # encoding: [0x7b,0x7e,0xb9,0x9a] +0x7a,0x5c,0x90,0xda == fsun.w $w3, $w18, $w28 # encoding: [0x7a,0x5c,0x90,0xda] +0x7a,0x73,0x5c,0x9a == fsun.d $w18, $w11, $w19 # encoding: [0x7a,0x73,0x5c,0x9a] +0x7a,0x82,0xfc,0x1c == fsune.w $w16, $w31, $w2 # encoding: [0x7a,0x82,0xfc,0x1c] +0x7a,0xb1,0xd0,0xdc == fsune.d $w3, $w26, $w17 # encoding: [0x7a,0xb1,0xd0,0xdc] +0x7a,0x98,0x24,0x1b == ftq.h $w16, $w4, $w24 # encoding: [0x7a,0x98,0x24,0x1b] +0x7a,0xb9,0x29,0x5b == ftq.w $w5, $w5, $w25 # encoding: [0x7a,0xb9,0x29,0x5b] +0x79,0x4a,0xa4,0x1c == madd_q.h $w16, $w20, $w10 # encoding: [0x79,0x4a,0xa4,0x1c] +0x79,0x69,0x17,0x1c == madd_q.w $w28, $w2, $w9 # encoding: [0x79,0x69,0x17,0x1c] +0x7b,0x49,0x92,0x1c == maddr_q.h $w8, $w18, $w9 # encoding: [0x7b,0x49,0x92,0x1c] +0x7b,0x70,0x67,0x5c == maddr_q.w $w29, $w12, $w16 # encoding: [0x7b,0x70,0x67,0x5c] +0x79,0x8a,0xd6,0x1c == msub_q.h $w24, $w26, $w10 # encoding: [0x79,0x8a,0xd6,0x1c] +0x79,0xbc,0xf3,0x5c == msub_q.w $w13, $w30, $w28 # encoding: [0x79,0xbc,0xf3,0x5c] +0x7b,0x8b,0xab,0x1c == msubr_q.h $w12, $w21, $w11 # encoding: [0x7b,0x8b,0xab,0x1c] +0x7b,0xb4,0x70,0x5c == msubr_q.w $w1, $w14, $w20 # encoding: [0x7b,0xb4,0x70,0x5c] +0x79,0x1e,0x81,0x9c == mul_q.h $w6, $w16, $w30 # encoding: [0x79,0x1e,0x81,0x9c] +0x79,0x24,0x0c,0x1c == mul_q.w $w16, $w1, $w4 # encoding: [0x79,0x24,0x0c,0x1c] +0x7b,0x13,0xa1,0x9c == mulr_q.h $w6, $w20, $w19 # encoding: [0x7b,0x13,0xa1,0x9c] +0x7b,0x34,0x0e,0xdc == mulr_q.w $w27, $w1, $w20 # encoding: [0x7b,0x34,0x0e,0xdc] diff --git a/suite/MC/Mips/test_bit.s.cs b/suite/MC/Mips/test_bit.s.cs index 882cd9020..1f714a5eb 100644 --- a/suite/MC/Mips/test_bit.s.cs +++ b/suite/MC/Mips/test_bit.s.cs @@ -1,49 +1,50 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x79,0xf2,0xf5,0x49 = bclri.b $w21, $w30, 2 -0x79,0xe0,0xae,0x09 = bclri.h $w24, $w21, 0 -0x79,0xc3,0xf5,0xc9 = bclri.w $w23, $w30, 3 -0x79,0x80,0x5a,0x49 = bclri.d $w9, $w11, 0 -0x7b,0x71,0x66,0x49 = binsli.b $w25, $w12, 1 -0x7b,0x60,0xb5,0x49 = binsli.h $w21, $w22, 0 -0x7b,0x40,0x25,0x89 = binsli.w $w22, $w4, 0 -0x7b,0x06,0x11,0x89 = binsli.d $w6, $w2, 6 -0x7b,0xf0,0x9b,0xc9 = binsri.b $w15, $w19, 0 -0x7b,0xe1,0xf2,0x09 = binsri.h $w8, $w30, 1 -0x7b,0xc5,0x98,0x89 = binsri.w $w2, $w19, 5 -0x7b,0x81,0xa4,0x89 = binsri.d $w18, $w20, 1 -0x7a,0xf0,0x9e,0x09 = bnegi.b $w24, $w19, 0 -0x7a,0xe3,0x5f,0x09 = bnegi.h $w28, $w11, 3 -0x7a,0xc5,0xd8,0x49 = bnegi.w $w1, $w27, 5 -0x7a,0x81,0xa9,0x09 = bnegi.d $w4, $w21, 1 -0x7a,0x70,0x44,0x89 = bseti.b $w18, $w8, 0 -0x7a,0x62,0x76,0x09 = bseti.h $w24, $w14, 2 -0x7a,0x44,0x92,0x49 = bseti.w $w9, $w18, 4 -0x7a,0x01,0x79,0xc9 = bseti.d $w7, $w15, 1 -0x78,0x72,0xff,0xca = sat_s.b $w31, $w31, 2 -0x78,0x60,0x9c,0xca = sat_s.h $w19, $w19, 0 -0x78,0x40,0xec,0xca = sat_s.w $w19, $w29, 0 -0x78,0x00,0xb2,0xca = sat_s.d $w11, $w22, 0 -0x78,0xf3,0x68,0x4a = sat_u.b $w1, $w13, 3 -0x78,0xe4,0xc7,0x8a = sat_u.h $w30, $w24, 4 -0x78,0xc0,0x6f,0xca = sat_u.w $w31, $w13, 0 -0x78,0x85,0x87,0x4a = sat_u.d $w29, $w16, 5 -0x78,0x71,0x55,0xc9 = slli.b $w23, $w10, 1 -0x78,0x61,0x92,0x49 = slli.h $w9, $w18, 1 -0x78,0x44,0xea,0xc9 = slli.w $w11, $w29, 4 -0x78,0x01,0xa6,0x49 = slli.d $w25, $w20, 1 -0x78,0xf1,0xee,0x09 = srai.b $w24, $w29, 1 -0x78,0xe0,0x30,0x49 = srai.h $w1, $w6, 0 -0x78,0xc1,0xd1,0xc9 = srai.w $w7, $w26, 1 -0x78,0x83,0xcd,0x09 = srai.d $w20, $w25, 3 -0x79,0x70,0xc9,0x4a = srari.b $w5, $w25, 0 -0x79,0x64,0x31,0xca = srari.h $w7, $w6, 4 -0x79,0x45,0x5c,0x4a = srari.w $w17, $w11, 5 -0x79,0x05,0xcd,0x4a = srari.d $w21, $w25, 5 -0x79,0x72,0x00,0x89 = srli.b $w2, $w0, 2 -0x79,0x62,0xff,0xc9 = srli.h $w31, $w31, 2 -0x79,0x44,0x49,0x49 = srli.w $w5, $w9, 4 -0x79,0x05,0xd6,0xc9 = srli.d $w27, $w26, 5 -0x79,0xf0,0x1c,0x8a = srlri.b $w18, $w3, 0 -0x79,0xe3,0x10,0x4a = srlri.h $w1, $w2, 3 -0x79,0xc2,0xb2,0xca = srlri.w $w11, $w22, 2 -0x79,0x86,0x56,0x0a = srlri.d $w24, $w10, 6 + +0x79,0xf2,0xf5,0x49 == bclri.b $w21, $w30, 2 # encoding: [0x79,0xf2,0xf5,0x49] +0x79,0xe0,0xae,0x09 == bclri.h $w24, $w21, 0 # encoding: [0x79,0xe0,0xae,0x09] +0x79,0xc3,0xf5,0xc9 == bclri.w $w23, $w30, 3 # encoding: [0x79,0xc3,0xf5,0xc9] +0x79,0x80,0x5a,0x49 == bclri.d $w9, $w11, 0 # encoding: [0x79,0x80,0x5a,0x49] +0x7b,0x71,0x66,0x49 == binsli.b $w25, $w12, 1 # encoding: [0x7b,0x71,0x66,0x49] +0x7b,0x60,0xb5,0x49 == binsli.h $w21, $w22, 0 # encoding: [0x7b,0x60,0xb5,0x49] +0x7b,0x40,0x25,0x89 == binsli.w $w22, $w4, 0 # encoding: [0x7b,0x40,0x25,0x89] +0x7b,0x06,0x11,0x89 == binsli.d $w6, $w2, 6 # encoding: [0x7b,0x06,0x11,0x89] +0x7b,0xf0,0x9b,0xc9 == binsri.b $w15, $w19, 0 # encoding: [0x7b,0xf0,0x9b,0xc9] +0x7b,0xe1,0xf2,0x09 == binsri.h $w8, $w30, 1 # encoding: [0x7b,0xe1,0xf2,0x09] +0x7b,0xc5,0x98,0x89 == binsri.w $w2, $w19, 5 # encoding: [0x7b,0xc5,0x98,0x89] +0x7b,0x81,0xa4,0x89 == binsri.d $w18, $w20, 1 # encoding: [0x7b,0x81,0xa4,0x89] +0x7a,0xf0,0x9e,0x09 == bnegi.b $w24, $w19, 0 # encoding: [0x7a,0xf0,0x9e,0x09] +0x7a,0xe3,0x5f,0x09 == bnegi.h $w28, $w11, 3 # encoding: [0x7a,0xe3,0x5f,0x09] +0x7a,0xc5,0xd8,0x49 == bnegi.w $w1, $w27, 5 # encoding: [0x7a,0xc5,0xd8,0x49] +0x7a,0x81,0xa9,0x09 == bnegi.d $w4, $w21, 1 # encoding: [0x7a,0x81,0xa9,0x09] +0x7a,0x70,0x44,0x89 == bseti.b $w18, $w8, 0 # encoding: [0x7a,0x70,0x44,0x89] +0x7a,0x62,0x76,0x09 == bseti.h $w24, $w14, 2 # encoding: [0x7a,0x62,0x76,0x09] +0x7a,0x44,0x92,0x49 == bseti.w $w9, $w18, 4 # encoding: [0x7a,0x44,0x92,0x49] +0x7a,0x01,0x79,0xc9 == bseti.d $w7, $w15, 1 # encoding: [0x7a,0x01,0x79,0xc9] +0x78,0x72,0xff,0xca == sat_s.b $w31, $w31, 2 # encoding: [0x78,0x72,0xff,0xca] +0x78,0x60,0x9c,0xca == sat_s.h $w19, $w19, 0 # encoding: [0x78,0x60,0x9c,0xca] +0x78,0x40,0xec,0xca == sat_s.w $w19, $w29, 0 # encoding: [0x78,0x40,0xec,0xca] +0x78,0x00,0xb2,0xca == sat_s.d $w11, $w22, 0 # encoding: [0x78,0x00,0xb2,0xca] +0x78,0xf3,0x68,0x4a == sat_u.b $w1, $w13, 3 # encoding: [0x78,0xf3,0x68,0x4a] +0x78,0xe4,0xc7,0x8a == sat_u.h $w30, $w24, 4 # encoding: [0x78,0xe4,0xc7,0x8a] +0x78,0xc0,0x6f,0xca == sat_u.w $w31, $w13, 0 # encoding: [0x78,0xc0,0x6f,0xca] +0x78,0x85,0x87,0x4a == sat_u.d $w29, $w16, 5 # encoding: [0x78,0x85,0x87,0x4a] +0x78,0x71,0x55,0xc9 == slli.b $w23, $w10, 1 # encoding: [0x78,0x71,0x55,0xc9] +0x78,0x61,0x92,0x49 == slli.h $w9, $w18, 1 # encoding: [0x78,0x61,0x92,0x49] +0x78,0x44,0xea,0xc9 == slli.w $w11, $w29, 4 # encoding: [0x78,0x44,0xea,0xc9] +0x78,0x01,0xa6,0x49 == slli.d $w25, $w20, 1 # encoding: [0x78,0x01,0xa6,0x49] +0x78,0xf1,0xee,0x09 == srai.b $w24, $w29, 1 # encoding: [0x78,0xf1,0xee,0x09] +0x78,0xe0,0x30,0x49 == srai.h $w1, $w6, 0 # encoding: [0x78,0xe0,0x30,0x49] +0x78,0xc1,0xd1,0xc9 == srai.w $w7, $w26, 1 # encoding: [0x78,0xc1,0xd1,0xc9] +0x78,0x83,0xcd,0x09 == srai.d $w20, $w25, 3 # encoding: [0x78,0x83,0xcd,0x09] +0x79,0x70,0xc9,0x4a == srari.b $w5, $w25, 0 # encoding: [0x79,0x70,0xc9,0x4a] +0x79,0x64,0x31,0xca == srari.h $w7, $w6, 4 # encoding: [0x79,0x64,0x31,0xca] +0x79,0x45,0x5c,0x4a == srari.w $w17, $w11, 5 # encoding: [0x79,0x45,0x5c,0x4a] +0x79,0x05,0xcd,0x4a == srari.d $w21, $w25, 5 # encoding: [0x79,0x05,0xcd,0x4a] +0x79,0x72,0x00,0x89 == srli.b $w2, $w0, 2 # encoding: [0x79,0x72,0x00,0x89] +0x79,0x62,0xff,0xc9 == srli.h $w31, $w31, 2 # encoding: [0x79,0x62,0xff,0xc9] +0x79,0x44,0x49,0x49 == srli.w $w5, $w9, 4 # encoding: [0x79,0x44,0x49,0x49] +0x79,0x05,0xd6,0xc9 == srli.d $w27, $w26, 5 # encoding: [0x79,0x05,0xd6,0xc9] +0x79,0xf0,0x1c,0x8a == srlri.b $w18, $w3, 0 # encoding: [0x79,0xf0,0x1c,0x8a] +0x79,0xe3,0x10,0x4a == srlri.h $w1, $w2, 3 # encoding: [0x79,0xe3,0x10,0x4a] +0x79,0xc2,0xb2,0xca == srlri.w $w11, $w22, 2 # encoding: [0x79,0xc2,0xb2,0xca] +0x79,0x86,0x56,0x0a == srlri.d $w24, $w10, 6 # encoding: [0x79,0x86,0x56,0x0a] diff --git a/suite/MC/Mips/test_cbranch.s.cs b/suite/MC/Mips/test_cbranch.s.cs index 92e7cdb04..ee57619c2 100644 --- a/suite/MC/Mips/test_cbranch.s.cs +++ b/suite/MC/Mips/test_cbranch.s.cs @@ -1,11 +1,41 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -// 0x47,0x80,0x00,0x01 = bnz.b $w0, 4 -// 0x47,0xa1,0x00,0x04 = bnz.h $w1, 16 -// 0x47,0xc2,0x00,0x20 = bnz.w $w2, 128 -// 0x47,0xe3,0xff,0xe0 = bnz.d $w3, -128 -// 0x45,0xe0,0x00,0x01 = bnz.v $w0, 4 -// 0x47,0x00,0x00,0x20 = bz.b $w0, 128 -// 0x47,0x21,0x00,0x40 = bz.h $w1, 256 -// 0x47,0x42,0x00,0x80 = bz.w $w2, 512 -// 0x47,0x63,0xff,0x00 = bz.d $w3, -1024 -// 0x45,0x60,0x00,0x01 = bz.v $w0, 4 + +0x47,0x80,0x00,0x01 == bnz.b $w0, 4 # encoding: [0x47,0x80,0x00,0x01] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0xa1,0x00,0x04 == bnz.h $w1, 16 # encoding: [0x47,0xa1,0x00,0x04] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0xc2,0x00,0x20 == bnz.w $w2, 128 # encoding: [0x47,0xc2,0x00,0x20] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0xe3,0xff,0xe0 == bnz.d $w3, -128 # encoding: [0x47,0xe3,0xff,0xe0] +0x47,0x80, == bnz.b $w0, SYMBOL0 # encoding: [0x47,0x80,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0xa1, == bnz.h $w1, SYMBOL1 # encoding: [0x47,0xa1,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0xc2, == bnz.w $w2, SYMBOL2 # encoding: [0x47,0xc2,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0xe3, == bnz.d $w3, SYMBOL3 # encoding: [0x47,0xe3,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x45,0xe0,0x00,0x01 == bnz.v $w0, 4 # encoding: [0x45,0xe0,0x00,0x01] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x45,0xe0, == bnz.v $w0, SYMBOL0 # encoding: [0x45,0xe0,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x00,0x00,0x20 == bz.b $w0, 128 # encoding: [0x47,0x00,0x00,0x20] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x21,0x00,0x40 == bz.h $w1, 256 # encoding: [0x47,0x21,0x00,0x40] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x42,0x00,0x80 == bz.w $w2, 512 # encoding: [0x47,0x42,0x00,0x80] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x63,0xff,0x00 == bz.d $w3, -1024 # encoding: [0x47,0x63,0xff,0x00] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x00, == bz.b $w0, SYMBOL0 # encoding: [0x47,0x00,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x21, == bz.h $w1, SYMBOL1 # encoding: [0x47,0x21,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x42, == bz.w $w2, SYMBOL2 # encoding: [0x47,0x42,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x63, == bz.d $w3, SYMBOL3 # encoding: [0x47,0x63,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x45,0x60,0x00,0x01 == bz.v $w0, 4 # encoding: [0x45,0x60,0x00,0x01] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x45,0x60, == bz.v $w0, SYMBOL0 # encoding: [0x45,0x60,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] diff --git a/suite/MC/Mips/test_ctrlregs.s.cs b/suite/MC/Mips/test_ctrlregs.s.cs index fb587a75f..555731a36 100644 --- a/suite/MC/Mips/test_ctrlregs.s.cs +++ b/suite/MC/Mips/test_ctrlregs.s.cs @@ -1,33 +1,34 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x7e,0x00,0x59 = cfcmsa $at, $0 -0x78,0x7e,0x00,0x59 = cfcmsa $at, $0 -0x78,0x7e,0x08,0x99 = cfcmsa $v0, $1 -0x78,0x7e,0x08,0x99 = cfcmsa $v0, $1 -0x78,0x7e,0x10,0xd9 = cfcmsa $v1, $2 -0x78,0x7e,0x10,0xd9 = cfcmsa $v1, $2 -0x78,0x7e,0x19,0x19 = cfcmsa $a0, $3 -0x78,0x7e,0x19,0x19 = cfcmsa $a0, $3 -0x78,0x7e,0x21,0x59 = cfcmsa $a1, $4 -0x78,0x7e,0x21,0x59 = cfcmsa $a1, $4 -0x78,0x7e,0x29,0x99 = cfcmsa $a2, $5 -0x78,0x7e,0x29,0x99 = cfcmsa $a2, $5 -0x78,0x7e,0x31,0xd9 = cfcmsa $a3, $6 -0x78,0x7e,0x31,0xd9 = cfcmsa $a3, $6 -0x78,0x7e,0x3a,0x19 = cfcmsa $t0, $7 -0x78,0x7e,0x3a,0x19 = cfcmsa $t0, $7 -0x78,0x3e,0x08,0x19 = ctcmsa $0, $at -0x78,0x3e,0x08,0x19 = ctcmsa $0, $at -0x78,0x3e,0x10,0x59 = ctcmsa $1, $v0 -0x78,0x3e,0x10,0x59 = ctcmsa $1, $v0 -0x78,0x3e,0x18,0x99 = ctcmsa $2, $v1 -0x78,0x3e,0x18,0x99 = ctcmsa $2, $v1 -0x78,0x3e,0x20,0xd9 = ctcmsa $3, $a0 -0x78,0x3e,0x20,0xd9 = ctcmsa $3, $a0 -0x78,0x3e,0x29,0x19 = ctcmsa $4, $a1 -0x78,0x3e,0x29,0x19 = ctcmsa $4, $a1 -0x78,0x3e,0x31,0x59 = ctcmsa $5, $a2 -0x78,0x3e,0x31,0x59 = ctcmsa $5, $a2 -0x78,0x3e,0x39,0x99 = ctcmsa $6, $a3 -0x78,0x3e,0x39,0x99 = ctcmsa $6, $a3 -0x78,0x3e,0x41,0xd9 = ctcmsa $7, $t0 -0x78,0x3e,0x41,0xd9 = ctcmsa $7, $t0 + +0x78,0x7e,0x00,0x59 == cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59] +0x78,0x7e,0x00,0x59 == cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59] +0x78,0x7e,0x08,0x99 == cfcmsa $2, $1 # encoding: [0x78,0x7e,0x08,0x99] +0x78,0x7e,0x08,0x99 == cfcmsa $2, $1 # encoding: [0x78,0x7e,0x08,0x99] +0x78,0x7e,0x10,0xd9 == cfcmsa $3, $2 # encoding: [0x78,0x7e,0x10,0xd9] +0x78,0x7e,0x10,0xd9 == cfcmsa $3, $2 # encoding: [0x78,0x7e,0x10,0xd9] +0x78,0x7e,0x19,0x19 == cfcmsa $4, $3 # encoding: [0x78,0x7e,0x19,0x19] +0x78,0x7e,0x19,0x19 == cfcmsa $4, $3 # encoding: [0x78,0x7e,0x19,0x19] +0x78,0x7e,0x21,0x59 == cfcmsa $5, $4 # encoding: [0x78,0x7e,0x21,0x59] +0x78,0x7e,0x21,0x59 == cfcmsa $5, $4 # encoding: [0x78,0x7e,0x21,0x59] +0x78,0x7e,0x29,0x99 == cfcmsa $6, $5 # encoding: [0x78,0x7e,0x29,0x99] +0x78,0x7e,0x29,0x99 == cfcmsa $6, $5 # encoding: [0x78,0x7e,0x29,0x99] +0x78,0x7e,0x31,0xd9 == cfcmsa $7, $6 # encoding: [0x78,0x7e,0x31,0xd9] +0x78,0x7e,0x31,0xd9 == cfcmsa $7, $6 # encoding: [0x78,0x7e,0x31,0xd9] +0x78,0x7e,0x3a,0x19 == cfcmsa $8, $7 # encoding: [0x78,0x7e,0x3a,0x19] +0x78,0x7e,0x3a,0x19 == cfcmsa $8, $7 # encoding: [0x78,0x7e,0x3a,0x19] +0x78,0x3e,0x08,0x19 == ctcmsa $0, $1 # encoding: [0x78,0x3e,0x08,0x19] +0x78,0x3e,0x08,0x19 == ctcmsa $0, $1 # encoding: [0x78,0x3e,0x08,0x19] +0x78,0x3e,0x10,0x59 == ctcmsa $1, $2 # encoding: [0x78,0x3e,0x10,0x59] +0x78,0x3e,0x10,0x59 == ctcmsa $1, $2 # encoding: [0x78,0x3e,0x10,0x59] +0x78,0x3e,0x18,0x99 == ctcmsa $2, $3 # encoding: [0x78,0x3e,0x18,0x99] +0x78,0x3e,0x18,0x99 == ctcmsa $2, $3 # encoding: [0x78,0x3e,0x18,0x99] +0x78,0x3e,0x20,0xd9 == ctcmsa $3, $4 # encoding: [0x78,0x3e,0x20,0xd9] +0x78,0x3e,0x20,0xd9 == ctcmsa $3, $4 # encoding: [0x78,0x3e,0x20,0xd9] +0x78,0x3e,0x29,0x19 == ctcmsa $4, $5 # encoding: [0x78,0x3e,0x29,0x19] +0x78,0x3e,0x29,0x19 == ctcmsa $4, $5 # encoding: [0x78,0x3e,0x29,0x19] +0x78,0x3e,0x31,0x59 == ctcmsa $5, $6 # encoding: [0x78,0x3e,0x31,0x59] +0x78,0x3e,0x31,0x59 == ctcmsa $5, $6 # encoding: [0x78,0x3e,0x31,0x59] +0x78,0x3e,0x39,0x99 == ctcmsa $6, $7 # encoding: [0x78,0x3e,0x39,0x99] +0x78,0x3e,0x39,0x99 == ctcmsa $6, $7 # encoding: [0x78,0x3e,0x39,0x99] +0x78,0x3e,0x41,0xd9 == ctcmsa $7, $8 # encoding: [0x78,0x3e,0x41,0xd9] +0x78,0x3e,0x41,0xd9 == ctcmsa $7, $8 # encoding: [0x78,0x3e,0x41,0xd9] diff --git a/suite/MC/Mips/test_elm.s.cs b/suite/MC/Mips/test_elm.s.cs index c2ba95257..6297cd700 100644 --- a/suite/MC/Mips/test_elm.s.cs +++ b/suite/MC/Mips/test_elm.s.cs @@ -1,16 +1,16 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x82,0x43,0x59 = copy_s.b $t5, $w8[2] -0x78,0xa0,0xc8,0x59 = copy_s.h $at, $w25[0] -0x78,0xb1,0x2d,0x99 = copy_s.w $s6, $w5[1] -0x78,0xc4,0xa5,0x99 = copy_u.b $s6, $w20[4] -0x78,0xe0,0x25,0x19 = copy_u.h $s4, $w4[0] -0x78,0xf2,0x6f,0x99 = copy_u.w $fp, $w13[2] -0x78,0x04,0xe8,0x19 = sldi.b $w0, $w29[4] -0x78,0x20,0x8a,0x19 = sldi.h $w8, $w17[0] -0x78,0x32,0xdd,0x19 = sldi.w $w20, $w27[2] -0x78,0x38,0x61,0x19 = sldi.d $w4, $w12[0] -0x78,0x42,0x1e,0x59 = splati.b $w25, $w3[2] -0x78,0x61,0xe6,0x19 = splati.h $w24, $w28[1] -0x78,0x70,0x93,0x59 = splati.w $w13, $w18[0] -0x78,0x78,0x0f,0x19 = splati.d $w28, $w1[0] -0x78,0xbe,0xc5,0xd9 = move.v $w23, $w24 + +0x78,0x82,0x43,0x59 == copy_s.b $13, $w8[2] # encoding: [0x78,0x82,0x43,0x59] +0x78,0xa0,0xc8,0x59 == copy_s.h $1, $w25[0] # encoding: [0x78,0xa0,0xc8,0x59] +0x78,0xb1,0x2d,0x99 == copy_s.w $22, $w5[1] # encoding: [0x78,0xb1,0x2d,0x99] +0x78,0xc4,0xa5,0x99 == copy_u.b $22, $w20[4] # encoding: [0x78,0xc4,0xa5,0x99] +0x78,0xe0,0x25,0x19 == copy_u.h $20, $w4[0] # encoding: [0x78,0xe0,0x25,0x19] +0x78,0x04,0xe8,0x19 == sldi.b $w0, $w29[4] # encoding: [0x78,0x04,0xe8,0x19] +0x78,0x20,0x8a,0x19 == sldi.h $w8, $w17[0] # encoding: [0x78,0x20,0x8a,0x19] +0x78,0x32,0xdd,0x19 == sldi.w $w20, $w27[2] # encoding: [0x78,0x32,0xdd,0x19] +0x78,0x38,0x61,0x19 == sldi.d $w4, $w12[0] # encoding: [0x78,0x38,0x61,0x19] +0x78,0x42,0x1e,0x59 == splati.b $w25, $w3[2] # encoding: [0x78,0x42,0x1e,0x59] +0x78,0x61,0xe6,0x19 == splati.h $w24, $w28[1] # encoding: [0x78,0x61,0xe6,0x19] +0x78,0x70,0x93,0x59 == splati.w $w13, $w18[0] # encoding: [0x78,0x70,0x93,0x59] +0x78,0x78,0x0f,0x19 == splati.d $w28, $w1[0] # encoding: [0x78,0x78,0x0f,0x19] +0x78,0xbe,0xc5,0xd9 == move.v $w23, $w24 # encoding: [0x78,0xbe,0xc5,0xd9] diff --git a/suite/MC/Mips/test_elm_insert.s.cs b/suite/MC/Mips/test_elm_insert.s.cs index c9edc8e5e..c5bb89e57 100644 --- a/suite/MC/Mips/test_elm_insert.s.cs +++ b/suite/MC/Mips/test_elm_insert.s.cs @@ -1,4 +1,5 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x79,0x03,0xed,0xd9 = insert.b $w23[3], $sp -0x79,0x22,0x2d,0x19 = insert.h $w20[2], $a1 -0x79,0x32,0x7a,0x19 = insert.w $w8[2], $t7 + +0x79,0x03,0xed,0xd9 == insert.b $w23[3], $sp # encoding: [0x79,0x03,0xed,0xd9] +0x79,0x22,0x2d,0x19 == insert.h $w20[2], $5 # encoding: [0x79,0x22,0x2d,0x19] +0x79,0x32,0x7a,0x19 == insert.w $w8[2], $15 # encoding: [0x79,0x32,0x7a,0x19] diff --git a/suite/MC/Mips/test_elm_insve.s.cs b/suite/MC/Mips/test_elm_insve.s.cs index 7657969b7..c4e0fff33 100644 --- a/suite/MC/Mips/test_elm_insve.s.cs +++ b/suite/MC/Mips/test_elm_insve.s.cs @@ -1,5 +1,6 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x79,0x43,0x4e,0x59 = insve.b $w25[3], $w9[0] -0x79,0x62,0x16,0x19 = insve.h $w24[2], $w2[0] -0x79,0x72,0x68,0x19 = insve.w $w0[2], $w13[0] -0x79,0x78,0x90,0xd9 = insve.d $w3[0], $w18[0] + +0x79,0x43,0x4e,0x59 == insve.b $w25[3], $w9[0] # encoding: [0x79,0x43,0x4e,0x59] +0x79,0x62,0x16,0x19 == insve.h $w24[2], $w2[0] # encoding: [0x79,0x62,0x16,0x19] +0x79,0x72,0x68,0x19 == insve.w $w0[2], $w13[0] # encoding: [0x79,0x72,0x68,0x19] +0x79,0x78,0x90,0xd9 == insve.d $w3[0], $w18[0] # encoding: [0x79,0x78,0x90,0xd9] diff --git a/suite/MC/Mips/test_i10.s.cs b/suite/MC/Mips/test_i10.s.cs index ba799f9d7..58f015d91 100644 --- a/suite/MC/Mips/test_i10.s.cs +++ b/suite/MC/Mips/test_i10.s.cs @@ -1,5 +1,6 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x7b,0x06,0x32,0x07 = ldi.b $w8, 198 -0x7b,0x29,0xcd,0x07 = ldi.h $w20, 313 -0x7b,0x4f,0x66,0x07 = ldi.w $w24, 492 -// 0x7b,0x7a,0x66,0xc7 = ldi.d $w27, -180 + +0x7b,0x06,0x32,0x07 == ldi.b $w8, 198 # encoding: [0x7b,0x06,0x32,0x07] +0x7b,0x29,0xcd,0x07 == ldi.h $w20, 313 # encoding: [0x7b,0x29,0xcd,0x07] +0x7b,0x4f,0x66,0x07 == ldi.w $w24, 492 # encoding: [0x7b,0x4f,0x66,0x07] +0x7b,0x7a,0x66,0xc7 == ldi.d $w27, -180 # encoding: [0x7b,0x7a,0x66,0xc7] diff --git a/suite/MC/Mips/test_i5.s.cs b/suite/MC/Mips/test_i5.s.cs index 57192231b..ba8825a13 100644 --- a/suite/MC/Mips/test_i5.s.cs +++ b/suite/MC/Mips/test_i5.s.cs @@ -1,45 +1,46 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x1e,0xf8,0xc6 = addvi.b $w3, $w31, 30 -0x78,0x3a,0x6e,0x06 = addvi.h $w24, $w13, 26 -0x78,0x5a,0xa6,0x86 = addvi.w $w26, $w20, 26 -0x78,0x75,0x0c,0x06 = addvi.d $w16, $w1, 21 -// 0x78,0x18,0xae,0x07 = ceqi.b $w24, $w21, -8 -0x78,0x22,0x7f,0xc7 = ceqi.h $w31, $w15, 2 -// 0x78,0x5f,0x0b,0x07 = ceqi.w $w12, $w1, -1 -0x78,0x67,0xb6,0x07 = ceqi.d $w24, $w22, 7 -0x7a,0x01,0x83,0x07 = clei_s.b $w12, $w16, 1 -// 0x7a,0x37,0x50,0x87 = clei_s.h $w2, $w10, -9 -// 0x7a,0x56,0x59,0x07 = clei_s.w $w4, $w11, -10 -// 0x7a,0x76,0xe8,0x07 = clei_s.d $w0, $w29, -10 -0x7a,0x83,0x8d,0x47 = clei_u.b $w21, $w17, 3 -0x7a,0xb1,0x3f,0x47 = clei_u.h $w29, $w7, 17 -0x7a,0xc2,0x08,0x47 = clei_u.w $w1, $w1, 2 -0x7a,0xfd,0xde,0xc7 = clei_u.d $w27, $w27, 29 -// 0x79,0x19,0x6c,0xc7 = clti_s.b $w19, $w13, -7 -// 0x79,0x34,0x53,0xc7 = clti_s.h $w15, $w10, -12 -0x79,0x4b,0x63,0x07 = clti_s.w $w12, $w12, 11 -// 0x79,0x71,0xa7,0x47 = clti_s.d $w29, $w20, -15 -0x79,0x9d,0x4b,0x87 = clti_u.b $w14, $w9, 29 -0x79,0xb9,0xce,0x07 = clti_u.h $w24, $w25, 25 -0x79,0xd6,0x08,0x47 = clti_u.w $w1, $w1, 22 -0x79,0xe1,0xcd,0x47 = clti_u.d $w21, $w25, 1 -0x79,0x01,0xad,0x86 = maxi_s.b $w22, $w21, 1 -// 0x79,0x38,0x2f,0x46 = maxi_s.h $w29, $w5, -8 -// 0x79,0x54,0x50,0x46 = maxi_s.w $w1, $w10, -12 -// 0x79,0x70,0xeb,0x46 = maxi_s.d $w13, $w29, -16 -0x79,0x8c,0x05,0x06 = maxi_u.b $w20, $w0, 12 -0x79,0xa3,0x70,0x46 = maxi_u.h $w1, $w14, 3 -0x79,0xcb,0xb6,0xc6 = maxi_u.w $w27, $w22, 11 -0x79,0xe4,0x36,0x86 = maxi_u.d $w26, $w6, 4 -0x7a,0x01,0x09,0x06 = mini_s.b $w4, $w1, 1 -// 0x7a,0x37,0xde,0xc6 = mini_s.h $w27, $w27, -9 -0x7a,0x49,0x5f,0x06 = mini_s.w $w28, $w11, 9 -0x7a,0x6a,0x52,0xc6 = mini_s.d $w11, $w10, 10 -0x7a,0x9b,0xbc,0x86 = mini_u.b $w18, $w23, 27 -0x7a,0xb2,0xd1,0xc6 = mini_u.h $w7, $w26, 18 -0x7a,0xda,0x62,0xc6 = mini_u.w $w11, $w12, 26 -0x7a,0xe2,0x7a,0xc6 = mini_u.d $w11, $w15, 2 -0x78,0x93,0xa6,0x06 = subvi.b $w24, $w20, 19 -0x78,0xa4,0x9a,0xc6 = subvi.h $w11, $w19, 4 -0x78,0xcb,0x53,0x06 = subvi.w $w12, $w10, 11 -0x78,0xe7,0x84,0xc6 = subvi.d $w19, $w16, 7 + +0x78,0x1e,0xf8,0xc6 == addvi.b $w3, $w31, 30 # encoding: [0x78,0x1e,0xf8,0xc6] +0x78,0x3a,0x6e,0x06 == addvi.h $w24, $w13, 26 # encoding: [0x78,0x3a,0x6e,0x06] +0x78,0x5a,0xa6,0x86 == addvi.w $w26, $w20, 26 # encoding: [0x78,0x5a,0xa6,0x86] +0x78,0x75,0x0c,0x06 == addvi.d $w16, $w1, 21 # encoding: [0x78,0x75,0x0c,0x06] +0x78,0x18,0xae,0x07 == ceqi.b $w24, $w21, -8 # encoding: [0x78,0x18,0xae,0x07] +0x78,0x22,0x7f,0xc7 == ceqi.h $w31, $w15, 2 # encoding: [0x78,0x22,0x7f,0xc7] +0x78,0x5f,0x0b,0x07 == ceqi.w $w12, $w1, -1 # encoding: [0x78,0x5f,0x0b,0x07] +0x78,0x67,0xb6,0x07 == ceqi.d $w24, $w22, 7 # encoding: [0x78,0x67,0xb6,0x07] +0x7a,0x01,0x83,0x07 == clei_s.b $w12, $w16, 1 # encoding: [0x7a,0x01,0x83,0x07] +0x7a,0x37,0x50,0x87 == clei_s.h $w2, $w10, -9 # encoding: [0x7a,0x37,0x50,0x87] +0x7a,0x56,0x59,0x07 == clei_s.w $w4, $w11, -10 # encoding: [0x7a,0x56,0x59,0x07] +0x7a,0x76,0xe8,0x07 == clei_s.d $w0, $w29, -10 # encoding: [0x7a,0x76,0xe8,0x07] +0x7a,0x83,0x8d,0x47 == clei_u.b $w21, $w17, 3 # encoding: [0x7a,0x83,0x8d,0x47] +0x7a,0xb1,0x3f,0x47 == clei_u.h $w29, $w7, 17 # encoding: [0x7a,0xb1,0x3f,0x47] +0x7a,0xc2,0x08,0x47 == clei_u.w $w1, $w1, 2 # encoding: [0x7a,0xc2,0x08,0x47] +0x7a,0xfd,0xde,0xc7 == clei_u.d $w27, $w27, 29 # encoding: [0x7a,0xfd,0xde,0xc7] +0x79,0x19,0x6c,0xc7 == clti_s.b $w19, $w13, -7 # encoding: [0x79,0x19,0x6c,0xc7] +0x79,0x34,0x53,0xc7 == clti_s.h $w15, $w10, -12 # encoding: [0x79,0x34,0x53,0xc7] +0x79,0x4b,0x63,0x07 == clti_s.w $w12, $w12, 11 # encoding: [0x79,0x4b,0x63,0x07] +0x79,0x71,0xa7,0x47 == clti_s.d $w29, $w20, -15 # encoding: [0x79,0x71,0xa7,0x47] +0x79,0x9d,0x4b,0x87 == clti_u.b $w14, $w9, 29 # encoding: [0x79,0x9d,0x4b,0x87] +0x79,0xb9,0xce,0x07 == clti_u.h $w24, $w25, 25 # encoding: [0x79,0xb9,0xce,0x07] +0x79,0xd6,0x08,0x47 == clti_u.w $w1, $w1, 22 # encoding: [0x79,0xd6,0x08,0x47] +0x79,0xe1,0xcd,0x47 == clti_u.d $w21, $w25, 1 # encoding: [0x79,0xe1,0xcd,0x47] +0x79,0x01,0xad,0x86 == maxi_s.b $w22, $w21, 1 # encoding: [0x79,0x01,0xad,0x86] +0x79,0x38,0x2f,0x46 == maxi_s.h $w29, $w5, -8 # encoding: [0x79,0x38,0x2f,0x46] +0x79,0x54,0x50,0x46 == maxi_s.w $w1, $w10, -12 # encoding: [0x79,0x54,0x50,0x46] +0x79,0x70,0xeb,0x46 == maxi_s.d $w13, $w29, -16 # encoding: [0x79,0x70,0xeb,0x46] +0x79,0x8c,0x05,0x06 == maxi_u.b $w20, $w0, 12 # encoding: [0x79,0x8c,0x05,0x06] +0x79,0xa3,0x70,0x46 == maxi_u.h $w1, $w14, 3 # encoding: [0x79,0xa3,0x70,0x46] +0x79,0xcb,0xb6,0xc6 == maxi_u.w $w27, $w22, 11 # encoding: [0x79,0xcb,0xb6,0xc6] +0x79,0xe4,0x36,0x86 == maxi_u.d $w26, $w6, 4 # encoding: [0x79,0xe4,0x36,0x86] +0x7a,0x01,0x09,0x06 == mini_s.b $w4, $w1, 1 # encoding: [0x7a,0x01,0x09,0x06] +0x7a,0x37,0xde,0xc6 == mini_s.h $w27, $w27, -9 # encoding: [0x7a,0x37,0xde,0xc6] +0x7a,0x49,0x5f,0x06 == mini_s.w $w28, $w11, 9 # encoding: [0x7a,0x49,0x5f,0x06] +0x7a,0x6a,0x52,0xc6 == mini_s.d $w11, $w10, 10 # encoding: [0x7a,0x6a,0x52,0xc6] +0x7a,0x9b,0xbc,0x86 == mini_u.b $w18, $w23, 27 # encoding: [0x7a,0x9b,0xbc,0x86] +0x7a,0xb2,0xd1,0xc6 == mini_u.h $w7, $w26, 18 # encoding: [0x7a,0xb2,0xd1,0xc6] +0x7a,0xda,0x62,0xc6 == mini_u.w $w11, $w12, 26 # encoding: [0x7a,0xda,0x62,0xc6] +0x7a,0xe2,0x7a,0xc6 == mini_u.d $w11, $w15, 2 # encoding: [0x7a,0xe2,0x7a,0xc6] +0x78,0x93,0xa6,0x06 == subvi.b $w24, $w20, 19 # encoding: [0x78,0x93,0xa6,0x06] +0x78,0xa4,0x9a,0xc6 == subvi.h $w11, $w19, 4 # encoding: [0x78,0xa4,0x9a,0xc6] +0x78,0xcb,0x53,0x06 == subvi.w $w12, $w10, 11 # encoding: [0x78,0xcb,0x53,0x06] +0x78,0xe7,0x84,0xc6 == subvi.d $w19, $w16, 7 # encoding: [0x78,0xe7,0x84,0xc6] diff --git a/suite/MC/Mips/test_i8.s.cs b/suite/MC/Mips/test_i8.s.cs index 0b08f63aa..d1dcb40bb 100644 --- a/suite/MC/Mips/test_i8.s.cs +++ b/suite/MC/Mips/test_i8.s.cs @@ -1,11 +1,12 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x30,0xe8,0x80 = andi.b $w2, $w29, 48 -0x78,0x7e,0xb1,0x81 = bmnzi.b $w6, $w22, 126 -0x79,0x58,0x0e,0xc1 = bmzi.b $w27, $w1, 88 -0x7a,0xbd,0x1f,0x41 = bseli.b $w29, $w3, 189 -0x7a,0x38,0x88,0x40 = nori.b $w1, $w17, 56 -0x79,0x87,0xa6,0x80 = ori.b $w26, $w20, 135 -0x78,0x69,0xf4,0xc2 = shf.b $w19, $w30, 105 -0x79,0x4c,0x44,0x42 = shf.h $w17, $w8, 76 -0x7a,0x5d,0x1b,0x82 = shf.w $w14, $w3, 93 -0x7b,0x14,0x54,0x00 = xori.b $w16, $w10, 20 + +0x78,0x30,0xe8,0x80 == andi.b $w2, $w29, 48 # encoding: [0x78,0x30,0xe8,0x80] +0x78,0x7e,0xb1,0x81 == bmnzi.b $w6, $w22, 126 # encoding: [0x78,0x7e,0xb1,0x81] +0x79,0x58,0x0e,0xc1 == bmzi.b $w27, $w1, 88 # encoding: [0x79,0x58,0x0e,0xc1] +0x7a,0xbd,0x1f,0x41 == bseli.b $w29, $w3, 189 # encoding: [0x7a,0xbd,0x1f,0x41] +0x7a,0x38,0x88,0x40 == nori.b $w1, $w17, 56 # encoding: [0x7a,0x38,0x88,0x40] +0x79,0x87,0xa6,0x80 == ori.b $w26, $w20, 135 # encoding: [0x79,0x87,0xa6,0x80] +0x78,0x69,0xf4,0xc2 == shf.b $w19, $w30, 105 # encoding: [0x78,0x69,0xf4,0xc2] +0x79,0x4c,0x44,0x42 == shf.h $w17, $w8, 76 # encoding: [0x79,0x4c,0x44,0x42] +0x7a,0x5d,0x1b,0x82 == shf.w $w14, $w3, 93 # encoding: [0x7a,0x5d,0x1b,0x82] +0x7b,0x14,0x54,0x00 == xori.b $w16, $w10, 20 # encoding: [0x7b,0x14,0x54,0x00] diff --git a/suite/MC/Mips/test_lsa.s.cs b/suite/MC/Mips/test_lsa.s.cs index 098775c04..c59d25ad2 100644 --- a/suite/MC/Mips/test_lsa.s.cs +++ b/suite/MC/Mips/test_lsa.s.cs @@ -1,5 +1,6 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x01,0x2a,0x40,0x05 = lsa $t0, $t1, $t2, 1 -0x01,0x2a,0x40,0x45 = lsa $t0, $t1, $t2, 2 -0x01,0x2a,0x40,0x85 = lsa $t0, $t1, $t2, 3 -0x01,0x2a,0x40,0xc5 = lsa $t0, $t1, $t2, 4 + +0x01,0x2a,0x40,0x05 == lsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x05] +0x01,0x2a,0x40,0x45 == lsa $8, $9, $10, 2 # encoding: [0x01,0x2a,0x40,0x45] +0x01,0x2a,0x40,0x85 == lsa $8, $9, $10, 3 # encoding: [0x01,0x2a,0x40,0x85] +0x01,0x2a,0x40,0xc5 == lsa $8, $9, $10, 4 # encoding: [0x01,0x2a,0x40,0xc5] diff --git a/suite/MC/Mips/test_mi10.s.cs b/suite/MC/Mips/test_mi10.s.cs index 54d62c469..0492cad38 100644 --- a/suite/MC/Mips/test_mi10.s.cs +++ b/suite/MC/Mips/test_mi10.s.cs @@ -1,24 +1,25 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x7a,0x00,0x08,0x20 = ld.b $w0, -512($at) -0x78,0x00,0x10,0x60 = ld.b $w1, ($v0) -0x79,0xff,0x18,0xa0 = ld.b $w2, 511($v1) -0x7a,0x00,0x20,0xe1 = ld.h $w3, -1024($a0) -0x7b,0x00,0x29,0x21 = ld.h $w4, -512($a1) -0x78,0x00,0x31,0x61 = ld.h $w5, ($a2) -0x79,0x00,0x39,0xa1 = ld.h $w6, 512($a3) -0x79,0xff,0x41,0xe1 = ld.h $w7, 1022($t0) -0x7a,0x00,0x4a,0x22 = ld.w $w8, -2048($t1) -0x7b,0x00,0x52,0x62 = ld.w $w9, -1024($t2) -0x7b,0x80,0x5a,0xa2 = ld.w $w10, -512($t3) -0x78,0x80,0x62,0xe2 = ld.w $w11, 512($t4) -0x79,0x00,0x6b,0x22 = ld.w $w12, 1024($t5) -0x79,0xff,0x73,0x62 = ld.w $w13, 2044($t6) -0x7a,0x00,0x7b,0xa3 = ld.d $w14, -4096($t7) -0x7b,0x00,0x83,0xe3 = ld.d $w15, -2048($s0) -0x7b,0x80,0x8c,0x23 = ld.d $w16, -1024($s1) -0x7b,0xc0,0x94,0x63 = ld.d $w17, -512($s2) -0x78,0x00,0x9c,0xa3 = ld.d $w18, ($s3) -0x78,0x40,0xa4,0xe3 = ld.d $w19, 512($s4) -0x78,0x80,0xad,0x23 = ld.d $w20, 1024($s5) -0x79,0x00,0xb5,0x63 = ld.d $w21, 2048($s6) -0x79,0xff,0xbd,0xa3 = ld.d $w22, 4088($s7) + +0x7a,0x00,0x08,0x20 == ld.b $w0, -512($1) # encoding: [0x7a,0x00,0x08,0x20] +0x78,0x00,0x10,0x60 == ld.b $w1, 0($2) # encoding: [0x78,0x00,0x10,0x60] +0x79,0xff,0x18,0xa0 == ld.b $w2, 511($3) # encoding: [0x79,0xff,0x18,0xa0] +0x7a,0x00,0x20,0xe1 == ld.h $w3, -1024($4) # encoding: [0x7a,0x00,0x20,0xe1] +0x7b,0x00,0x29,0x21 == ld.h $w4, -512($5) # encoding: [0x7b,0x00,0x29,0x21] +0x78,0x00,0x31,0x61 == ld.h $w5, 0($6) # encoding: [0x78,0x00,0x31,0x61] +0x79,0x00,0x39,0xa1 == ld.h $w6, 512($7) # encoding: [0x79,0x00,0x39,0xa1] +0x79,0xff,0x41,0xe1 == ld.h $w7, 1022($8) # encoding: [0x79,0xff,0x41,0xe1] +0x7a,0x00,0x4a,0x22 == ld.w $w8, -2048($9) # encoding: [0x7a,0x00,0x4a,0x22] +0x7b,0x00,0x52,0x62 == ld.w $w9, -1024($10) # encoding: [0x7b,0x00,0x52,0x62] +0x7b,0x80,0x5a,0xa2 == ld.w $w10, -512($11) # encoding: [0x7b,0x80,0x5a,0xa2] +0x78,0x80,0x62,0xe2 == ld.w $w11, 512($12) # encoding: [0x78,0x80,0x62,0xe2] +0x79,0x00,0x6b,0x22 == ld.w $w12, 1024($13) # encoding: [0x79,0x00,0x6b,0x22] +0x79,0xff,0x73,0x62 == ld.w $w13, 2044($14) # encoding: [0x79,0xff,0x73,0x62] +0x7a,0x00,0x7b,0xa3 == ld.d $w14, -4096($15) # encoding: [0x7a,0x00,0x7b,0xa3] +0x7b,0x00,0x83,0xe3 == ld.d $w15, -2048($16) # encoding: [0x7b,0x00,0x83,0xe3] +0x7b,0x80,0x8c,0x23 == ld.d $w16, -1024($17) # encoding: [0x7b,0x80,0x8c,0x23] +0x7b,0xc0,0x94,0x63 == ld.d $w17, -512($18) # encoding: [0x7b,0xc0,0x94,0x63] +0x78,0x00,0x9c,0xa3 == ld.d $w18, 0($19) # encoding: [0x78,0x00,0x9c,0xa3] +0x78,0x40,0xa4,0xe3 == ld.d $w19, 512($20) # encoding: [0x78,0x40,0xa4,0xe3] +0x78,0x80,0xad,0x23 == ld.d $w20, 1024($21) # encoding: [0x78,0x80,0xad,0x23] +0x79,0x00,0xb5,0x63 == ld.d $w21, 2048($22) # encoding: [0x79,0x00,0xb5,0x63] +0x79,0xff,0xbd,0xa3 == ld.d $w22, 4088($23) # encoding: [0x79,0xff,0xbd,0xa3] diff --git a/suite/MC/Mips/test_vec.s.cs b/suite/MC/Mips/test_vec.s.cs index 930386823..b2def5870 100644 --- a/suite/MC/Mips/test_vec.s.cs +++ b/suite/MC/Mips/test_vec.s.cs @@ -1,8 +1,9 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x1b,0xa6,0x5e = and.v $w25, $w20, $w27 -0x78,0x87,0x34,0x5e = bmnz.v $w17, $w6, $w7 -0x78,0xa9,0x88,0xde = bmz.v $w3, $w17, $w9 -0x78,0xce,0x02,0x1e = bsel.v $w8, $w0, $w14 -0x78,0x40,0xf9,0xde = nor.v $w7, $w31, $w0 -0x78,0x3e,0xd6,0x1e = or.v $w24, $w26, $w30 -0x78,0x6f,0xd9,0xde = xor.v $w7, $w27, $w15 + +0x78,0x1b,0xa6,0x5e == and.v $w25, $w20, $w27 # encoding: [0x78,0x1b,0xa6,0x5e] +0x78,0x87,0x34,0x5e == bmnz.v $w17, $w6, $w7 # encoding: [0x78,0x87,0x34,0x5e] +0x78,0xa9,0x88,0xde == bmz.v $w3, $w17, $w9 # encoding: [0x78,0xa9,0x88,0xde] +0x78,0xce,0x02,0x1e == bsel.v $w8, $w0, $w14 # encoding: [0x78,0xce,0x02,0x1e] +0x78,0x40,0xf9,0xde == nor.v $w7, $w31, $w0 # encoding: [0x78,0x40,0xf9,0xde] +0x78,0x3e,0xd6,0x1e == or.v $w24, $w26, $w30 # encoding: [0x78,0x3e,0xd6,0x1e] +0x78,0x6f,0xd9,0xde == xor.v $w7, $w27, $w15 # encoding: [0x78,0x6f,0xd9,0xde] diff --git a/suite/auto-sync/pyproject.toml b/suite/auto-sync/pyproject.toml index 907d88ada..cf560c27a 100644 --- a/suite/auto-sync/pyproject.toml +++ b/suite/auto-sync/pyproject.toml @@ -8,7 +8,7 @@ version = "0.1.0" dependencies = [ "termcolor >= 2.3.0", "tree_sitter == 0.22.3", - "tree-sitter-cpp >=0.22.0", + "tree-sitter-cpp == 0.22.3", "black >= 24.3.0", "usort >= 1.0.8", "setuptools >= 69.2.0", diff --git a/suite/auto-sync/src/autosync/ASUpdater.py b/suite/auto-sync/src/autosync/ASUpdater.py index a69803001..15ec43387 100755 --- a/suite/auto-sync/src/autosync/ASUpdater.py +++ b/suite/auto-sync/src/autosync/ASUpdater.py @@ -216,7 +216,7 @@ def parse_args() -> argparse.Namespace: "-a", dest="arch", help="Name of target architecture.", - choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch"], + choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch", "Mips"], required=True, ) parser.add_argument( diff --git a/suite/auto-sync/src/autosync/MCUpdater.py b/suite/auto-sync/src/autosync/MCUpdater.py index afc64873c..c8ee9f4e3 100755 --- a/suite/auto-sync/src/autosync/MCUpdater.py +++ b/suite/auto-sync/src/autosync/MCUpdater.py @@ -143,6 +143,8 @@ class TestFile: text_section = 0 # Counts the .text sections asm_pat = f"(?P.+)" enc_pat = r"(\[?(?P(?P((0x[a-fA-F0-9]{1,2}[, ]{0,2}))+)[^, ]?)\]?)" + + dups = [] for line in mc_output.stdout.splitlines(): line = line.decode("utf8") if ".text" in line: @@ -166,6 +168,10 @@ class TestFile: if not self.valid_byte_seq(enc_bytes): continue + if (enc_bytes + asm_text) in dups: + continue + + dups.append(enc_bytes + asm_text) if text_section in self.tests: if unified_test_cases: self.tests[text_section][0].extend(enc_bytes, asm_text) @@ -262,6 +268,20 @@ class MCUpdater: if self.arch in self.conf["mandatory_options"] else list() ) + self.remove_options: str = ( + self.conf["remove_options"][self.arch] + if self.arch in self.conf["remove_options"] + else list() + ) + self.remove_options = [x.lower() for x in self.remove_options] + self.replace_option_map: str = ( + self.conf["replace_option_map"][self.arch] + if self.arch in self.conf["replace_option_map"] + else {} + ) + self.replace_option_map = { + k.lower(): v for k, v in self.replace_option_map.items() + } self.multi_mode = multi_mode def check_prerequisites(self, paths): @@ -331,17 +351,30 @@ class MCUpdater: f"See also: https://github.com/capstone-engine/capstone/issues/1992" ) + def build_test_options(self, options): + new_options = [] + self.mandatory_options + for opt in options: + opt = opt.lower() + if opt in self.remove_options: + continue + elif opt in self.replace_option_map: + new_options.append(self.replace_option_map[opt]) + else: + new_options.append(opt) + return new_options + def build_test_files(self, mc_cmds: list[LLVM_MC_Command]) -> list[TestFile]: log.info("Build TestFile objects") test_files = list() n_all = len(mc_cmds) for i, mcc in enumerate(mc_cmds): print(f"{i + 1}/{n_all} {mcc.file.name}", flush=True, end="\r") + opts = self.build_test_options(mcc.get_opts_list()) test_files.append( TestFile( self.arch, mcc.file, - mcc.get_opts_list() + self.mandatory_options, + opts, mcc, self.unified_test_cases, ) diff --git a/suite/auto-sync/src/autosync/cpptranslator/Configurator.py b/suite/auto-sync/src/autosync/cpptranslator/Configurator.py index f50e9d692..e8e81cba6 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/Configurator.py +++ b/suite/auto-sync/src/autosync/cpptranslator/Configurator.py @@ -57,6 +57,12 @@ class Configurator: self.load_config() return self.config["General"] + def get_patch_config(self) -> dict: + if self.config: + return self.config["General"]["patching"] + self.load_config() + return self.config["General"]["patching"] + def load_config(self) -> None: if not Path.exists(self.config_path): fail_exit(f"Could not load arch config file at '{self.config_path}'") diff --git a/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py b/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py index 6e4992e7c..38d28adac 100755 --- a/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py +++ b/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py @@ -382,32 +382,16 @@ class Translator: def apply_patch(self, patch: Patch) -> bool: """Tests if the given patch should be applied for the current architecture or file.""" - has_apply_only = ( - len(patch.apply_only_to["files"]) > 0 - or len(patch.apply_only_to["archs"]) > 0 - ) - has_do_not_apply = ( - len(patch.do_not_apply["files"]) > 0 or len(patch.do_not_apply["archs"]) > 0 - ) - - if not (has_apply_only or has_do_not_apply): - # Lists empty. + apply_only_to = self.configurator.get_patch_config()["apply_patch_only_to"] + patch_name = patch.__class__.__name__ + if patch_name not in apply_only_to: + # No constraints return True - if has_apply_only: - if self.arch in patch.apply_only_to["archs"]: - return True - elif self.current_src_path_in.name in patch.apply_only_to["files"]: - return True - return False - elif has_do_not_apply: - if self.arch in patch.do_not_apply["archs"]: - return False - elif self.current_src_path_in.name in patch.do_not_apply["files"]: - return False + file_constraints = apply_only_to[patch_name] + if self.current_src_path_in.name in file_constraints["files"]: return True - log.fatal("Logical error.") - exit(1) + return False def translate(self) -> None: for self.current_src_path_in, self.current_src_path_out in zip( diff --git a/suite/auto-sync/src/autosync/cpptranslator/Differ.py b/suite/auto-sync/src/autosync/cpptranslator/Differ.py index 8cc2a39ad..b65c85b04 100755 --- a/suite/auto-sync/src/autosync/cpptranslator/Differ.py +++ b/suite/auto-sync/src/autosync/cpptranslator/Differ.py @@ -636,18 +636,21 @@ class Differ: j = old_node_ids.index(self.cur_nid) while j >= 0 and (old_node_ids[j] not in new_nodes.keys()): j -= 1 - ref_new: Node = ( - new_nodes[old_node_ids[j]] - if old_node_ids[j] in new_nodes.keys() - else new_nodes[0] - ) - ref_end_byte = ref_new.start_byte + if j < 0 or old_node_ids[j] not in new_nodes.keys(): + # No new node exists before the old node. + # So just put it to the very beginning. + ref_end_byte = 1 + ref_start_point = (1, 0) + else: + ref_new: Node = new_nodes[old_node_ids[j]] + ref_end_byte = ref_new.start_byte + ref_start_point = ref_new.start_point # We always write to the new file. So we always take he coordinates form it. patch_coord = PatchCoord( ref_end_byte - 1, ref_end_byte - 1, - ref_new.start_point, - ref_new.start_point, + ref_start_point, + ref_start_point, ) save_exists = False @@ -922,7 +925,7 @@ def parse_args() -> argparse.Namespace: "-a", dest="arch", help="Name of target architecture (ignored with -t option)", - choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch"], + choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch", "Mips"], required=True, ) parser.add_argument( diff --git a/suite/auto-sync/src/autosync/cpptranslator/TemplateCollector.py b/suite/auto-sync/src/autosync/cpptranslator/TemplateCollector.py index abab53dc5..24470aad7 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/TemplateCollector.py +++ b/suite/auto-sync/src/autosync/cpptranslator/TemplateCollector.py @@ -107,7 +107,6 @@ class TemplateCollector: tree = self.parser.parse(src, keep_text=True) query: Query = self.lang_cpp.query(self.get_template_pattern()) - self.get_capture_bundles(query, tree) capture_bundles = self.get_capture_bundles(query, tree) for cb in capture_bundles: diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json b/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json index 6fc12a614..276da32d3 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json @@ -5,7 +5,30 @@ "diff_color_saved": "yellow", "diff_color_edited": "light_magenta", "patch_editor": "vim", - "nodes_to_diff": [] + "nodes_to_diff": [], + "patching": { + "apply_patch_only_to": { + "AddCSDetail": { + "files": [ + "ARMInstPrinter.cpp", + "PPCInstPrinter.cpp", + "AArch64InstPrinter.cpp", + "LoongArchInstPrinter.cpp", + "MipsInstPrinter.cpp" + ] + }, + "InlineToStaticInline": { + "files": [ + "ARMAddressingModes.h" + ] + }, + "PrintRegImmShift": { + "files": [ + "ARMInstPrinter.cpp" + ] + } + } + } }, "ARCH": { "files_to_translate": [], diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/test_unit.py b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_unit.py new file mode 100644 index 000000000..ee069211b --- /dev/null +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_unit.py @@ -0,0 +1,44 @@ +# SPDX-FileCopyrightText: 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +import unittest +from pathlib import Path + +from autosync.Helper import get_path +from autosync.cpptranslator import CppTranslator +from autosync.cpptranslator.Configurator import Configurator +from autosync.cpptranslator.patches.AddCSDetail import AddCSDetail +from autosync.cpptranslator.patches.InlineToStaticInline import InlineToStaticInline +from autosync.cpptranslator.patches.PrintRegImmShift import PrintRegImmShift +from autosync.cpptranslator.patches.Data import Data + + +class TestCppTranslator(unittest.TestCase): + @classmethod + def setUpClass(cls): + configurator = Configurator("ARCH", get_path("{PATCHES_TEST_CONFIG}")) + cls.translator = CppTranslator.Translator(configurator, False) + + def test_patching_constraints(self): + self.translator.current_src_path_in = Path("Random_file.cpp") + patch_add_cs_detail = AddCSDetail(0, "ARCH") + patch_inline_to_static_inline = InlineToStaticInline(0) + patch_print_reg_imm_shift = PrintRegImmShift(0) + patch_data = Data(0) + + self.assertFalse(self.translator.apply_patch(patch_add_cs_detail)) + self.assertFalse(self.translator.apply_patch(patch_inline_to_static_inline)) + self.assertFalse(self.translator.apply_patch(patch_print_reg_imm_shift)) + self.assertTrue(self.translator.apply_patch(patch_data)) + + self.translator.current_src_path_in = Path("ARMInstPrinter.cpp") + self.assertTrue(self.translator.apply_patch(patch_add_cs_detail)) + self.assertFalse(self.translator.apply_patch(patch_inline_to_static_inline)) + self.assertTrue(self.translator.apply_patch(patch_print_reg_imm_shift)) + self.assertTrue(self.translator.apply_patch(patch_data)) + + self.translator.current_src_path_in = Path("ARMAddressingModes.h") + self.assertFalse(self.translator.apply_patch(patch_add_cs_detail)) + self.assertTrue(self.translator.apply_patch(patch_inline_to_static_inline)) + self.assertFalse(self.translator.apply_patch(patch_print_reg_imm_shift)) + self.assertTrue(self.translator.apply_patch(patch_data)) diff --git a/suite/auto-sync/src/autosync/cpptranslator/arch_config.json b/suite/auto-sync/src/autosync/cpptranslator/arch_config.json index 03e89797d..3de3c4efe 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/arch_config.json +++ b/suite/auto-sync/src/autosync/cpptranslator/arch_config.json @@ -5,6 +5,29 @@ "diff_color_saved": "yellow", "diff_color_edited": "light_magenta", "patch_editor": "vim", + "patching": { + "apply_patch_only_to": { + "AddCSDetail": { + "files": [ + "ARMInstPrinter.cpp", + "PPCInstPrinter.cpp", + "AArch64InstPrinter.cpp", + "LoongArchInstPrinter.cpp", + "MipsInstPrinter.cpp" + ] + }, + "InlineToStaticInline": { + "files": [ + "ARMAddressingModes.h" + ] + }, + "PrintRegImmShift": { + "files": [ + "ARMInstPrinter.cpp" + ] + } + } + }, "nodes_to_diff": [ { "node_type": "function_definition", @@ -51,7 +74,7 @@ "{LLVM_ROOT}/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h" ] }, - "PPC": { + "PPC": { "files_to_translate": [ { "in": "{LLVM_ROOT}/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp", @@ -147,7 +170,47 @@ "{LLVM_ROOT}/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp", "{LLVM_ROOT}/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp" ], + "templates_with_arg_deduction": [], + "manually_edited_files": [] + }, + "Mips": { + "files_to_translate": [ + { + "in": "{LLVM_ROOT}/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp", + "out": "MipsDisassembler.c" + },{ + "in": "{LLVM_ROOT}/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp", + "out": "MipsInstPrinter.c" + },{ + "in": "{LLVM_ROOT}/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h", + "out": "MipsInstPrinter.h" + } + ], + "files_for_template_search": [ + "{CPP_INC_OUT_DIR}/MipsGenDisassemblerTables.inc", + "{LLVM_ROOT}/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp", + "{CPP_INC_OUT_DIR}/MipsGenAsmWriter.inc" + ], "templates_with_arg_deduction": [ + "DecodeINSVE_DF", + "DecodeDAHIDATIMMR6", + "DecodeDAHIDATI", + "DecodeAddiGroupBranch", + "DecodePOP35GroupBranchMMR6", + "DecodeDaddiGroupBranch", + "DecodePOP37GroupBranchMMR6", + "DecodePOP65GroupBranchMMR6", + "DecodePOP75GroupBranchMMR6", + "DecodeBlezlGroupBranch", + "DecodeBgtzlGroupBranch", + "DecodeBgtzGroupBranch", + "DecodeBlezGroupBranch", + "DecodeBgtzGroupBranchMMR6", + "DecodeBlezGroupBranchMMR6", + "DecodeDINS", + "DecodeDEXT", + "DecodeCRC", + "isReg" ], "manually_edited_files": [] } diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py index fcb5f912b..84afa6952 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py @@ -31,6 +31,7 @@ class AddCSDetail(Patch): valid_param_lists = [ b"(MCInst*MI,unsignedOpNum,SStream*O)", # Default printOperand parameters. b"(MCInst*MI,unsignedOpNo,SStream*O)", # ARM - printComplexRotationOp / PPC default + b"(MCInst*MI,intopNum,SStream *O)", # Mips - printMemOperandEA and others b"(SStream*O,ARM_AM::ShiftOpcShOpc,unsignedShImm,boolgetUseMarkup())", # ARM - printRegImmShift b"(MCInst*MI,unsignedOpNo,SStream*O,constchar*Modifier)", # PPC - printPredicateOperand b"(MCInst*MI,uint64_tAddress,unsignedOpNo,SStream*O)", # PPC - printBranchOperand @@ -39,15 +40,6 @@ class AddCSDetail(Patch): def __init__(self, priority: int, arch: str): super().__init__(priority) self.arch = arch - self.apply_only_to = { - "files": [ - "ARMInstPrinter.cpp", - "PPCInstPrinter.cpp", - "AArch64InstPrinter.cpp", - "LoongArchInstPrinter.cpp", - ], - "archs": list(), - } def get_search_pattern(self) -> str: return ( @@ -88,11 +80,15 @@ class AddCSDetail(Patch): ) # Remove "print" from function id is_template = fcn_def.prev_sibling.type == "template_parameter_list" - op_num_var_name = ( - b"OpNum" - if b"OpNum" in params - else (b"OpNo" if b"OpNo" in params else b"-.-") - ) + if b"OpNum" in params: + op_num_var_name = b"OpNum" + elif b"OpNo" in params: + op_num_var_name = b"OpNo" + elif b"opNum" in params: + op_num_var_name = b"opNum" + else: + raise ValueError("OpNum parameter could not be identified.") + if not is_template and op_num_var_name in params: # Standard printOperand() parameters mcinst_var = get_MCInst_var_name(src, fcn_def) diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py b/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py index 8133e7b68..58092ea09 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py @@ -41,9 +41,9 @@ class FieldFromInstr(Patch): # Determine width of instruction by the variable name. if ffi_first_arg_text[-2:] == "32": - inst_width = 4 + inst_width = b"4" elif ffi_first_arg_text[-2:] == "16": - inst_width = 2 + inst_width = b"2" else: # Get the Val/Inst parameter. # Its type determines the instruction width. @@ -55,17 +55,38 @@ class FieldFromInstr(Patch): inst_type = inst_param_text.split(b" ")[0] if inst_type: if inst_type in [b"unsigned", b"uint32_t"]: - inst_width = 4 + inst_width = b"4" elif inst_type in [b"uint16_t"]: - inst_width = 2 + inst_width = b"2" + elif inst_type in [b"InsnType"]: + # Case means the decode function inherits the type from + # a template argument InsnType. The InsnType template argument + # is the type of integer holding the instruction bytes. + # This type is defined in ARCHDisassembler on calling the right macro. + # Hence, we do not know at this point of patching which type it might be. + # It needs to call fieldOfInstruction_X() which detects dynamically which + # integer type might hold the bytes (e.g. a uint32_t or uint16_t). + # You can check it manually in ARCHDisassembler.c, but the script can't. + # + # Here we just create a function with the postfix fieldFromInstruction_w (for width). + # This function must be implemented by hand, and check MCInst for the actual bit width. + # The bit width must be set in the ARCHDisassembler.c. Just add the code there by hand. + # Then call fieldFromInstruction_4, fieldFromInstruction_2 appropriately. + log.warning( + "Variable fieldFromInstruction width detected.\n" + "Please implement fieldFromInstruction_w() and call " + "fieldFromInstruction_4, fieldFromInstruction_2 appropriately.\n" + "In fieldFromInstruction_w() check MCInst for the actual bit width.\n" + "The bit width must be set in the ARCHDisassembler.c. Just add the code there by hand." + ) + inst_width = b"w" else: - log.fatal(f"Type {inst_type} no handled.") - exit(1) + raise ValueError(f"Type {inst_type} not handled.") else: # Needs manual fix return get_text(src, ffi_call.start_byte, ffi_call.end_byte) return re.sub( rb"fieldFromInstruction", - b"fieldFromInstruction_%d" % inst_width, + b"fieldFromInstruction_%s" % inst_width, get_text(src, ffi_call.start_byte, ffi_call.end_byte), ) diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py index d8bc3e1d6..01b69b5be 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py @@ -64,6 +64,8 @@ class Includes(Patch): return res + get_AArch64_includes(filename) + get_general_macros() case "LoongArch": return res + get_LoongArch_includes(filename) + get_general_macros() + case "Mips": + return res + get_Mips_includes(filename) + get_general_macros() case "TEST_ARCH": return res + b"test_output" case _: @@ -294,6 +296,43 @@ def get_LoongArch_includes(filename: str) -> bytes: exit(1) +def get_Mips_includes(filename: str) -> bytes: + match filename: + case "MipsDisassembler.cpp": + return ( + b'#include "../../MCInst.h"\n' + + b'#include "../../MathExtras.h"\n' + + b'#include "../../MCInstPrinter.h"\n' + + b'#include "../../MCDisassembler.h"\n' + + b'#include "../../MCFixedLenDisassembler.h"\n' + + b'#include "../../cs_priv.h"\n' + + b'#include "../../utils.h"\n' + + b"#define GET_SUBTARGETINFO_ENUM\n" + + b'#include "MipsGenSubtargetInfo.inc"\n\n' + + b"#define GET_INSTRINFO_ENUM\n" + + b'#include "MipsGenInstrInfo.inc"\n\n' + + b"#define GET_REGINFO_ENUM\n" + + b'#include "MipsGenRegisterInfo.inc"\n\n' + ) + case "MipsInstPrinter.cpp": + return ( + b'#include "MipsMapping.h"\n' + + b'#include "MipsInstPrinter.h"\n\n' + + b"#define GET_SUBTARGETINFO_ENUM\n" + + b'#include "MipsGenSubtargetInfo.inc"\n\n' + + b"#define GET_INSTRINFO_ENUM\n" + + b'#include "MipsGenInstrInfo.inc"\n\n' + + b"#define GET_REGINFO_ENUM\n" + + b'#include "MipsGenRegisterInfo.inc"\n\n' + ) + case "MipsInstPrinter.h": + return ( + b'#include "../../MCInstPrinter.h"\n' + b'#include "../../cs_priv.h"\n' + ) + log.fatal(f"No includes given for Mips source file: {filename}") + exit(1) + + def get_general_macros(): return ( b"#define CONCAT(a, b) CONCAT_(a, b)\n" b"#define CONCAT_(a, b) a ## _ ## b\n" diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/InlineToStaticInline.py b/suite/auto-sync/src/autosync/cpptranslator/patches/InlineToStaticInline.py index 8d07e8e09..9c267811a 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/InlineToStaticInline.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/InlineToStaticInline.py @@ -19,7 +19,6 @@ class InlineToStaticInline(Patch): def __init__(self, priority: int): super().__init__(priority) - self.apply_only_to = {"files": ["ARMAddressingModes.h"], "archs": list()} def get_search_pattern(self) -> str: return ( diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/Patch.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Patch.py index 6f82a0b49..a08cb72ea 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/Patch.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Patch.py @@ -9,17 +9,6 @@ from tree_sitter import Node class Patch: priority: int = None - # List of filenames and architectures this patch applies to or not. - # Order of testing: - # 1. apply_only_to.archs - # 2. apply_only_to.files - # 3. do_not_apply.archs - # 4. do_not_apply.files - # Contains the _in_ filenames and architectures this patch should be applied to. Empty list means all. - apply_only_to = {"files": list(), "archs": list()} - # Contains the _in_ filenames and architectures this patch should NOT be applied to. - do_not_apply = {"files": list(), "archs": list()} - def __init__(self, priority: int = 0): self.priority = priority diff --git a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json index ba5380dd0..6781acfaa 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json +++ b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json @@ -2408,5 +2408,887 @@ "new_hash": "02eaaa869cf975da8203666135470c113ad9246dd2f73061dbf6ee1706683299", "edit": "" } + }, + "MipsDisassembler.c": { + "\"../../MCRegisterInfo.h\"": { + "apply_type": "OLD", + "old_hash": "cd51ed81136ebf5690cdb06e839868574304a3f5c949cdde4fd43f2f994d5c17", + "new_hash": "", + "edit": "" + }, + "\"MipsCP0RegisterMap.h\"": { + "apply_type": "OLD", + "old_hash": "6fa698a4595e748650213e442280123e9f9b21e4976dd6280b9c72ecb82291ae", + "new_hash": "", + "edit": "" + }, + "DECLARE_DecodeAddressPCRelNM": { + "apply_type": "OLD", + "old_hash": "8215d7408ff03e7bd9ed6ff926196cd3dde50bb96592af192ebe47cbaf3b29bf", + "new_hash": "510d9061a3e26bc286a78133dc7de5fd2fd11bcc90916b622d31efc009665793", + "edit": "" + }, + "DECLARE_DecodeMemNM": { + "apply_type": "OLD", + "old_hash": "697b222065069d2a2062063433c966cabc56d465fd2d7bedf43d5cbd953c46ed", + "new_hash": "adb180eb4c1c51f21d4141fdf54052d57bc4da14a6a2e9414a55432b98dc0021", + "edit": "" + }, + "DECLARE_DecodeMemNMRX": { + "apply_type": "OLD", + "old_hash": "304e23ef1149f6caf88a506735d260c485919e17d4a05419deb1cc372a2eb617", + "new_hash": "fb669369d95102db3f864e2bcb803dae30bdb6a9888de97920e7d51a56c35f76", + "edit": "" + }, + "DECLARE_DecodeSImmWithOffsetAndScale": { + "apply_type": "OLD", + "old_hash": "7b167e19580fde8e315db8646851fcfd5cb9c1bced2c8fd21e25379902b43a39", + "new_hash": "475f9a4a5a719dce4c5f231aea96aac625d16875cdf60f616c6cafc96300d160", + "edit": "" + }, + "DECLARE_DecodeSImmWithOffsetAndScale_2": { + "apply_type": "OLD", + "old_hash": "3b71b6c2468671205e19f24ff7adda7c23be4924f364090065b86bdfacae0bfb", + "new_hash": "", + "edit": "" + }, + "DECLARE_DecodeSImmWithOffsetAndScale_3": { + "apply_type": "OLD", + "old_hash": "5eae2cb4e40b6f91fe1e5c99de86b78e0f1ed3ea31acbc7a79086d40916a6b17", + "new_hash": "", + "edit": "" + }, + "DEFINE_DecodeAddressPCRelNM": { + "apply_type": "OLD", + "old_hash": "abfdf6c9207a5a4a9815bfdaa41e557db8baa4150d145c58d52ea1cf56c9eac0", + "new_hash": "448430d34701d1787693b0fca831177cecaaf16aaca76028efd2d3fb02733dc7", + "edit": "" + }, + "DEFINE_DecodeBranchTargetNM": { + "apply_type": "OLD", + "old_hash": "4b1f3270e4a148ddbe4ea80cebbf7140ec397930143e752d063fcd357fbcb7ff", + "new_hash": "6ff1f355b42d33fbb7f7026b28a9aeccee84e5c2cab874581af81b6c76467a85", + "edit": "" + }, + "DEFINE_DecodeMemNM": { + "apply_type": "OLD", + "old_hash": "ea8ad745277c4f32b07c8fdc82c2771334b8b5e24385e78c16197ba3d7833705", + "new_hash": "9e19f7112d3fa3c8b594d05cb736c08fd483cb9c99d1089464622fd201695ffb", + "edit": "" + }, + "DEFINE_DecodeMemNMRX": { + "apply_type": "OLD", + "old_hash": "61cad03b197a4f155e6a7759b265e188885cf9c884462778e6de3c8fc08dad23", + "new_hash": "bcfb9fb6e4e037dbbb17475841219fa7ae8d7119845e7d68ebcba090998ca9d5", + "edit": "" + }, + "DEFINE_DecodeSImmWithOffsetAndScale_2": { + "apply_type": "OLD", + "old_hash": "fbc5d1b1da8dec91711025de976dde1384b2bae808cdc6133346ece154061392", + "new_hash": "", + "edit": "" + }, + "DEFINE_DecodeSImmWithOffsetAndScale_3": { + "apply_type": "OLD", + "old_hash": "d5db25ff0211c274440035c92e9b21795873b6c031c89f3e8375b42e437a41c1", + "new_hash": "", + "edit": "" + }, + "DecodeACC64DSPRegisterClass": { + "apply_type": "OLD", + "old_hash": "50b1a4607c3ff4b876ff4b2bb7beea5cbeb1c6a095127f631a915dbb02a87d04", + "new_hash": "76974afd5d6e304a422aace7f67390ce9c0c84dbff8eab04b14ed7ce8ce8111d", + "edit": "" + }, + "DecodeAFGR64RegisterClass": { + "apply_type": "OLD", + "old_hash": "2a056147501e4d5f1145853188536fbba956dd3836100fe5d78d5f59929d6c33", + "new_hash": "8e4a1bea8b089e93dee79cc31db2ed7d7aa0e7e489e4aa77430f169c3853e317", + "edit": "" + }, + "DecodeANDI16Imm": { + "apply_type": "OLD", + "old_hash": "8e5683e1b373c36db0dd7986f48106fbb3b5ca838a16f15a38f4ff8e314bd158", + "new_hash": "01a1ccd1faaa59286f22642aa253f0954edd7c99a9eca640ff1794dc69be7dd3", + "edit": "" + }, + "DecodeAddiGroupBranch": { + "apply_type": "OLD", + "old_hash": "09bade65e0befce00b53acb3f02d457ec2278cc46f0daa1190bca480655493d4", + "new_hash": "b43fc4d444b7d2f2ce3d8c8bdd6ad23d184564209c01ada6daf1b79eaef0be2a", + "edit": "" + }, + "DecodeBgtzGroupBranch": { + "apply_type": "OLD", + "old_hash": "48919afd95fa96acccc13339983e281ff8bfe70b5dbdd9478a304e048a263788", + "new_hash": "47188d8de7ccc86f3185b5ad77b7f4845efc9c9f54a39e9b01ee01ba191f6b0d", + "edit": "" + }, + "DecodeBgtzGroupBranchMMR6": { + "apply_type": "OLD", + "old_hash": "dfa41913e0654e9d1953eedbbec7a58de77200b22c81072fa663e8719a6a106e", + "new_hash": "437c10dd2bdd1491398dce2c0938802686659c485c302dcbd2380a1a4750c34f", + "edit": "" + }, + "DecodeBgtzlGroupBranch": { + "apply_type": "OLD", + "old_hash": "a2f93190037f79b6e8df1ab8a5dc65d2644c370c92351725d7d69c3073fb1a22", + "new_hash": "4a47c796517439f5de5b3e0deda2a4a1a72c03e40638564d24d49976cd2c2804", + "edit": "" + }, + "DecodeBlezGroupBranch": { + "apply_type": "OLD", + "old_hash": "881389b72656cfe8f41e6d56b58b0de97a27366c92099dd6655275e8d4f79d64", + "new_hash": "dc0a55c1a9551a8b7d956c529419b849f4fb658974a22546ed9f16a3541cc17b", + "edit": "" + }, + "DecodeBlezGroupBranchMMR6": { + "apply_type": "OLD", + "old_hash": "429dbed22e5fa2ecfaf2de4ee982b8ae786e6e2af15b9c4c857579bbcfbe4c28", + "new_hash": "1cf4577ffd64485bfcffaf9bf2e9f3d53eb9a39a516476595d1a3812c71f51b7", + "edit": "" + }, + "DecodeBlezlGroupBranch": { + "apply_type": "OLD", + "old_hash": "b458eb7370480f44c2cc21a34c8abd7122186d5fadc896bb95e0a0ab587e9e8c", + "new_hash": "e3cfabf394618d99c9b46a7619fc04425354af31c4f96841868308c3454ac4fe", + "edit": "" + }, + "DecodeBranchConflictNM": { + "apply_type": "OLD", + "old_hash": "4dcfebb897eb2f7e4f98bc962f070a385628c212d2439d6a24cab1f65060907d", + "new_hash": "3ae97ba3f294fcb6fdf7ed3e0c0903a5bdf497f67b74de385a17d60cee6209bd", + "edit": "" + }, + "DecodeCCRRegisterClass": { + "apply_type": "OLD", + "old_hash": "7537a7c8cb794bcbce23c25c14fdf5973978ca63dcc2ff907a6cb7dbfe179365", + "new_hash": "ef1a21490da18c7d3efab75e620ee7ac54f9c9786fb8acc75a874957ec9445bc", + "edit": "" + }, + "DecodeCOP0RegisterClass": { + "apply_type": "OLD", + "old_hash": "94a27091bd390ecd0e748c19b51595a32ddfde49eb909d71d124d8be3d325361", + "new_hash": "801f8333392af710747431f8ccdfeca99c9d8699cb3b89220c9fd448fea0298c", + "edit": "" + }, + "DecodeCOP0SelRegisterClass": { + "apply_type": "OLD", + "old_hash": "f5a63d8275a1decb9ba53dd1b5a91ef759108f0a45f0fe147152e12ca8585f2f", + "new_hash": "0ddaf2c039d0eedc9896553b3b690c5455c95f880ace756147d0ee5a97aa6d1e", + "edit": "" + }, + "DecodeCOP2RegisterClass": { + "apply_type": "OLD", + "old_hash": "7d09e567ed79598c6f93ab8e678ec1808aa4dccddae2cd2a6d09f9be8f8d8d81", + "new_hash": "6a86b848a18ab43fd3264f7f59966b376310ced22334abd943b9d3c8b31d3151", + "edit": "" + }, + "DecodeCRC": { + "apply_type": "OLD", + "old_hash": "83c959b6c4320ce29c93314c0ba0e9fca53d28604aacd0b983e8621f89251295", + "new_hash": "dcae12d771467e9460884070a059ead28fcf5af081f895a0426698bcca21d8e7", + "edit": "" + }, + "DecodeCacheOp": { + "apply_type": "OLD", + "old_hash": "e7a01cbfba43657e3d3a30f325c2264cc099ef86e3b5df00b58e1b87689982d1", + "new_hash": "fe6a8c08fe9336648e93488690d6f2f7d9ea71e0a3c1414fa5c7c52dd666d148", + "edit": "" + }, + "DecodeCacheOpMM": { + "apply_type": "OLD", + "old_hash": "40eb48f6ab8caba180df9a1e6981fbe8d3085c4ca6ceb587d6176decf576cf97", + "new_hash": "bef5a5f5370574821798ff32353999e15f8c7d8d1bba7e505134cdc95b3e3012", + "edit": "" + }, + "DecodeCacheeOp_CacheOpR6": { + "apply_type": "OLD", + "old_hash": "5c663ec5a7170ada94098367b760e0e59e136bba2081eccbf81a50542047d000", + "new_hash": "d7f032176fcdb9b572422396d34a7dfa542cd162f1293b636c1f7dfab647889f", + "edit": "" + }, + "DecodeDAHIDATI": { + "apply_type": "OLD", + "old_hash": "101bf5aed677836cafaa3815e8c13c187ccb8e765cb1f24b8f153225897eb465", + "new_hash": "6f04649744c05bb272e11854ae4025b40ef8af8342fa90bf5fc6d9577add83c0", + "edit": "" + }, + "DecodeDAHIDATIMMR6": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "d1d5a08fc3a0c15f1cc355de848ff0dcb8b55ccbc8bf0a6f7c166f82eb7f6ef7", + "edit": "" + }, + "DecodeDEXT": { + "apply_type": "OLD", + "old_hash": "85e57cd508578717942e5505055d4f68ada5e518ebe5981e9011a9c678681b5f", + "new_hash": "b43132bc601a931f5b319621b9b131b7c05e8a0afbd4e66d58a8e637781346b8", + "edit": "" + }, + "DecodeDINS": { + "apply_type": "OLD", + "old_hash": "c6a174da60d9fe2e1483b5fa12b8d38ed9ccbe6bc6af97ef915a13595b97b738", + "new_hash": "e6f3f842c133553372bba7e0951c187282865e8f6902e596259a09b965b99268", + "edit": "" + }, + "DecodeDaddiGroupBranch": { + "apply_type": "OLD", + "old_hash": "edd7d82241e74bafc0248ec43e87addd7ff2047c6c90c0c5c507306ce4b8734a", + "new_hash": "5bfb532a6c72924403ccd2dc2bf39b53dce36bcf9aa29867696220d3ee50c948", + "edit": "" + }, + "DecodeFCCRegisterClass": { + "apply_type": "OLD", + "old_hash": "8afd27cbb09289193ebf0bf207600cf59cbec2da3ba059dd27524e8aa23ee387", + "new_hash": "a570707a0c0499ac98e8b6c35b85d4dba5e8e0a6987566a899472b4cc5ceb0dc", + "edit": "" + }, + "DecodeFGR32RegisterClass": { + "apply_type": "OLD", + "old_hash": "d1558a16b6cadd0664e83c16ed2e13a85753246c1aac9e9c29866551deb01716", + "new_hash": "0bd9aa50728c2052ae0e7955337e5aca9418a15bd5cc50f4b8dc62aafabcbd74", + "edit": "" + }, + "DecodeFGR64RegisterClass": { + "apply_type": "OLD", + "old_hash": "886427c10e1d4beea2b72599021ee97332de7bcce5f229812f5452c1d34a11cd", + "new_hash": "dd6a5b96d743f6f2fe97473f7d9bf23b584a1fed9adf080cb94a3de87305c527", + "edit": "" + }, + "DecodeFGRCCRegisterClass": { + "apply_type": "OLD", + "old_hash": "0931e013ea0563b6390461fee1e65743dc14dc661113c04934aedb68a712442c", + "new_hash": "ac5d0e09e6f73c19200a3e39d40a3ecf0352667cad05b4011439b8203decc8bd", + "edit": "" + }, + "DecodeFIXMEInstruction": { + "apply_type": "OLD", + "old_hash": "1662f0a3f2d863ca6accd41cff2520a6cab91d2718387d3c50a4a91b0d0ffee0", + "new_hash": "86daf866c09624ad93a971ff3c83f9a5b4b1da23671fa3b3ea775c286cbb0851", + "edit": "" + }, + "DecodeFMem": { + "apply_type": "OLD", + "old_hash": "0622bfe67914aefbbfe7c0e707e0c02002ad6e121008a84bd027bbe56cc3dbc7", + "new_hash": "ce01734d25c2eb5b9c76237433f1a8e9a2d1d5bc9083539392cddf2f25dc2ab0", + "edit": "" + }, + "DecodeFMem2": { + "apply_type": "OLD", + "old_hash": "8aa77160a71cf966de56193a8a0856ff7c7cdc8fb1f33eb0b78ceadc92e18dc8", + "new_hash": "6ed8227bb07a26a147d0915e1cf75e1872b790f74271c52d894f9d713a48ad03", + "edit": "" + }, + "DecodeFMem3": { + "apply_type": "OLD", + "old_hash": "7de68fb557558781dce12417a4908c147f0151b78f13988f99aa1aad5d851ae2", + "new_hash": "b6bdf6a0cadd9e73963c8f77c52f95663c9af7088af555049c26d5b01cb07d38", + "edit": "" + }, + "DecodeFMemCop2MMR6": { + "apply_type": "OLD", + "old_hash": "72a284dcb454804d61a04427aa1fdebdafc1f9ad0ff37e6268b391a6e794f923", + "new_hash": "e02747533bfc65c4929ad44216df14f87a5e712a60386a1bb26a2134de80633f", + "edit": "" + }, + "DecodeFMemCop2R6": { + "apply_type": "OLD", + "old_hash": "e71ce24c072c55707ff0efef16bac1879899f6ac63859cb550ee384eb6024359", + "new_hash": "b4243228a19fd134232d52ec2d31d9599e7b1a775446c21b3af89cf262162597", + "edit": "" + }, + "DecodeFMemMMR2": { + "apply_type": "OLD", + "old_hash": "605544b7fdb0a2a0efcb79b41a7cc9185852234a2800286f8d23c6ad51ffdadb", + "new_hash": "e8b30b55428ae7965497b3d0cd659e19051a8f2cce74c200e6acb4d695b3d385", + "edit": "" + }, + "DecodeGPR32RegisterClass": { + "apply_type": "OLD", + "old_hash": "01fe48927278e9075f5a581553621f4a9dbf92d187eb7688103e008a63d2fd33", + "new_hash": "60c66ad7d0eb9567c0fd2c57adf68d0561f141f782b0f0ec00fca8f4afeb486c", + "edit": "" + }, + "DecodeGPR64RegisterClass": { + "apply_type": "OLD", + "old_hash": "21436e4ab5450d91cf1eaced506301b8f89c7454fca28786e6cb4ea0f3b678d4", + "new_hash": "bfc513cf62ecdc300d7587ccec4681697e716b1b2907ae791add867adea9a0cf", + "edit": "" + }, + "DecodeGPRMM16MovePRegisterClass": { + "apply_type": "OLD", + "old_hash": "f4c9cd17f3fa131e0c1cae7d4029c7f30481a5fd7cdcc203069ac448acd29c1e", + "new_hash": "67b715888f148b8db14ad1d15057054a2627d864960171edecffe65fd18ed289", + "edit": "" + }, + "DecodeGPRMM16RegisterClass": { + "apply_type": "OLD", + "old_hash": "9ff975b1b76c4d33c1e1b2539c9ba7e6fabd087ea0b0abd060b84f396321115b", + "new_hash": "34be26d66002e933e1a5f91c0af0327188101269673e29dd73b2d7f6dccf298c", + "edit": "" + }, + "DecodeGPRMM16ZeroRegisterClass": { + "apply_type": "OLD", + "old_hash": "e1e4b0b36c9a69e6d50ec874e5a3209928486a3774a406bf23377bd1c973183d", + "new_hash": "c55909fe1cb130d3367823187c5340da4f71d5a3b7b9a1705798a7cd130ee192", + "edit": "" + }, + "DecodeGPRNM1R1RegisterClass": { + "apply_type": "OLD", + "old_hash": "b7e713086c0503e8b53091c169d32011b2a8bc07c9827c185e4eeb7b16506c2e", + "new_hash": "4328db38bd47b66c3497b83d210ddae3b5ab3f7087f9d0003e977b23c2beea40", + "edit": "" + }, + "DecodeGPRNM2R1RegisterClass": { + "apply_type": "OLD", + "old_hash": "9009300dc9e11dbdff0644d1341e7820cfd500fb49501beb6c03a937b9ba3377", + "new_hash": "2f190511e928a65b20d65036239615588eaa07cb4e01634b286dad9638ba8969", + "edit": "" + }, + "DecodeGPRNM32NZRegisterClass": { + "apply_type": "OLD", + "old_hash": "0a87149ed0b369827e7a247dfff3a7ad0bed8343135fb42349d6e8bae6f819b5", + "new_hash": "5ee794ae59fca5b28c4221073242e0df99af78fd0e61fdb7cfa3715752b30c3a", + "edit": "" + }, + "DecodeGPRNM32RegisterClass": { + "apply_type": "OLD", + "old_hash": "ebadcfe00840f95ea448bdfe426c404c4e6ea61d7320d33346a0740de900a294", + "new_hash": "abc39a082a14fbe325ef37d65548cb0bae29fb3419a8467ee4492ed352c5943a", + "edit": "" + }, + "DecodeGPRNM3RegisterClass": { + "apply_type": "OLD", + "old_hash": "e19a92a144da863186c78b84cf63271d7b7d31c50e67754fb2ae49032da0115a", + "new_hash": "eb0f15f684e409c9aca72e9e0603eefcba2042eacdf2be40541e5a6cbfdf8084", + "edit": "" + }, + "DecodeGPRNM3ZRegisterClass": { + "apply_type": "OLD", + "old_hash": "6ebf274455dd1960747b9c859aa20aee54b5f36bc87a55a9eb964f676cf6f276", + "new_hash": "8789625cc7cf145f88541a14cd720aba0727d5d5e17d0415b9ed236a8467a9d3", + "edit": "" + }, + "DecodeGPRNM4RegisterClass": { + "apply_type": "OLD", + "old_hash": "ca5dc2096b2fbd356983abe307feea8159f61ebdb680e11ffc45c7b013b4cd4c", + "new_hash": "62455ebbd50323f9b31eeb1a625a008005d397d371e0a06de139f747ce96ea6c", + "edit": "" + }, + "DecodeGPRNM4ZRegisterClass": { + "apply_type": "OLD", + "old_hash": "5a4149c96e82da02bedabacda3feadd990058eb94f06c1b80408e9bc521fc296", + "new_hash": "7dd06b036e8808c5c0c78a56df9d5c9543926d63abec39e60ee9193a1fe5d02b", + "edit": "" + }, + "DecodeHI32DSPRegisterClass": { + "apply_type": "OLD", + "old_hash": "de0ccbf1bc814dc89cc5a46b229685f48a5c0e401dfd70fd9b82180496f33dae", + "new_hash": "2586a565685979245d5dad3499c9b530c1e6441e85ad738591b7994eb787736e", + "edit": "" + }, + "DecodeINSVE_DF": { + "apply_type": "OLD", + "old_hash": "ce6c3f16ea2b2363897a92cc3558793ef7fb039d229a7b27b63464ce01e895b2", + "new_hash": "442c000afb4bacbb41402ab649f6ddef973ba7596bc9ee87dcc51acb8414ef54", + "edit": "" + }, + "DecodeInsSize": { + "apply_type": "OLD", + "old_hash": "196732908c3ea812a585f4917c46529676c9583cb6b660e5dc8b61f55c57b239", + "new_hash": "4a68f7706deff574fd862541e1461b83abc3157afe666e38da9a590a99e4a25e", + "edit": "" + }, + "DecodeJumpTarget": { + "apply_type": "OLD", + "old_hash": "366940aaf77dec2847ea51cef4bc297f8d545d79040157e22ec82337d536e273", + "new_hash": "2e6bc1429c146b2b845a8f4c8f0608defc86796a869442302ceb6741217de4d9", + "edit": "" + }, + "DecodeJumpTargetMM": { + "apply_type": "OLD", + "old_hash": "7e72091982c6d7c26b521f1e9f117938acfd28ceaa6bc1dc070acdac2f92ad80", + "new_hash": "f59cbde6804c7437c267f0a85f620b21026142fc139e48a1cb48089db4b24ff0", + "edit": "" + }, + "DecodeJumpTargetXMM": { + "apply_type": "OLD", + "old_hash": "7cbce5cb38df425c1e5c7b5948d0d4a2db53ad013cd1626562a86f0dc09cd7b4", + "new_hash": "5a415ad2e0d33f700721371e20db013ce11b49fccb966d2dae97ca6b208e2f3e", + "edit": "" + }, + "DecodeLO32DSPRegisterClass": { + "apply_type": "OLD", + "old_hash": "36599d8def43d07474dba6fea03f8a9059d25d9a7e7bacd59749099ba4497c28", + "new_hash": "f4cfd1ca699075b1ca73f0c76e70aa4e8f1e6523c8e0b84d4eb06be697660067", + "edit": "" + }, + "DecodeLoadByte15": { + "apply_type": "OLD", + "old_hash": "f4538c0428b2aacc0f9ff1418022f3b55aa7f17a189734168710e01615dc83f2", + "new_hash": "5119e0e3d50b1dc2dc4dd8d2b54961f54fbf63858b92a3ab505d2b73da6bb76e", + "edit": "" + }, + "DecodeMSA128BRegisterClass": { + "apply_type": "OLD", + "old_hash": "45d120cc3c9a607c653cf6859833981ef0376af1366fefff56123e75496f86bd", + "new_hash": "e75ac1c584d02726e64870b089b9ceb98e52c75d349eb2c978ca0dd563ac1fd3", + "edit": "" + }, + "DecodeMSA128DRegisterClass": { + "apply_type": "OLD", + "old_hash": "ed8b07cdc72075e5084063e93b1caf84cf7b8429a11c81c516a1b9b13717bf2d", + "new_hash": "9e97999e5acfb898a2e020ff5c11669b1f9de64e98d80733637e95d92977a7f4", + "edit": "" + }, + "DecodeMSA128HRegisterClass": { + "apply_type": "OLD", + "old_hash": "6eb6a7417ec9cb16e195f639c5f706eda96d324fbdfc6c5ae309ec209a5162f7", + "new_hash": "d16bbc20bdec23289e1fdc2271b31526705a596e059e7aa88aea61e811c40247", + "edit": "" + }, + "DecodeMSA128Mem": { + "apply_type": "OLD", + "old_hash": "c11fdcb5609238c34be68f45be7467947ecbcbbb8ced8d04e89b602ee0cb264b", + "new_hash": "2dd37fc9932510d5f8c26eeea7394898a6c68c92a677c726f19945f2382abc35", + "edit": "" + }, + "DecodeMSA128WRegisterClass": { + "apply_type": "OLD", + "old_hash": "e511a7a791e8b9e1adf0616c7aaef1ee69e0bad38ce6e5026a03d759b1476c82", + "new_hash": "dc554b42f6644ec84d265c58e27bead8695c78abac63db7fb8ad022ab63fd2e2", + "edit": "" + }, + "DecodeMSACtrlRegisterClass": { + "apply_type": "OLD", + "old_hash": "0034af86fe06d553317b131fdc90acdf4e3b84ad364b43d431d8c7cecca93118", + "new_hash": "2327247593c5398fa3571621565bfdaaea31fcdf2d053634e1239f090571ef0a", + "edit": "" + }, + "DecodeMem": { + "apply_type": "OLD", + "old_hash": "2b98cf45026814c595d347020ecd6f5d4d6048bd8b8a7891c1a4c669e4de77aa", + "new_hash": "0ea280adaa1b01f7d95ca98029d53565cb657d56589d21597e0dfa9047f74120", + "edit": "" + }, + "DecodeMemEVA": { + "apply_type": "OLD", + "old_hash": "8078301d20e2b3ff72aa5dab4e6513d4f5ad7820887fefe66d319eb8ee9756cc", + "new_hash": "e2f1753fef99a6bd72b806d2191161486eb43d3181b323d19163d241f4fa2c47", + "edit": "" + }, + "DecodeMemMMGPImm7Lsl2": { + "apply_type": "OLD", + "old_hash": "b3887690da17e10aa339bb11ce9f9d93e187e18b8db7965204b4c6a0eb4ebdfc", + "new_hash": "2a99f5f060258909f8a06d02add9c67844031c102d038c9fc62e49df64af0600", + "edit": "" + }, + "DecodeMemMMImm12": { + "apply_type": "OLD", + "old_hash": "59685841408fdb829b77aca41b2622400995fc558c4873f9135f4c95b3a0e4e0", + "new_hash": "1e11b4b9d2fd54c66421697f2630bd7e2a40ddfb484330b608e5240177b2be6f", + "edit": "" + }, + "DecodeMemMMImm16": { + "apply_type": "OLD", + "old_hash": "24e106e9042361fb386dac3ce28284fd7b2f9e2c1ee137fd2f16027f21c7031a", + "new_hash": "c6f231225285b671b142dc4d7d649d8f64aec7469237dfdd8b8c384557dcf89a", + "edit": "" + }, + "DecodeMemMMImm4": { + "apply_type": "OLD", + "old_hash": "8aa87e4111ceae1017ceb5538ee43feb45eb5883dd6508efb41929c974cebe52", + "new_hash": "22749592c3f3add01b59416d57e2337b38123a2f294dfc6ae6b26da85a09d7b3", + "edit": "" + }, + "DecodeMemMMImm9": { + "apply_type": "OLD", + "old_hash": "39e56b2734e209fddd7419626e91e1445f668ce401c579476785937c181124df", + "new_hash": "3d59c74ca7f7608ea54b85ca2debc7121ea57a4a334f7aa7bc5f7e08af6c2f9e", + "edit": "" + }, + "DecodeMemMMReglistImm4Lsl2": { + "apply_type": "OLD", + "old_hash": "78b5d0b6414ccfc223c8a64113f18a80d2d1fd9243159dcfed731c80907000a5", + "new_hash": "83380670202831bb60ea31219e44657cd976e660bc3d671cc72e8a3307db5e51", + "edit": "" + }, + "DecodeMemMMSPImm5Lsl2": { + "apply_type": "OLD", + "old_hash": "7576ca4a302bc33532222531af62b87268bee679eb872caca8356eaeea5b0d98", + "new_hash": "3c4894151c6338b5bb6f6c255019f149a25da4e931d7ef0b8500bccb9db6e341", + "edit": "" + }, + "DecodeMemNM4x4": { + "apply_type": "OLD", + "old_hash": "bfa7ffe0ff6555952b796521a18a76592f3f06fec4a6ff2c5287e1ab054e6530", + "new_hash": "2f3a1675ad0c890387cb531b3af265ebb5ebe44a3b21b06cb17ea840a91b6854", + "edit": "" + }, + "DecodeMemZeroNM": { + "apply_type": "OLD", + "old_hash": "caa781e926f202d80a7b6b00271965272c3d6905a38de197bad2321865822eb4", + "new_hash": "7725f35131ddb3adfc509ffb5ad06cb67ba3c35aa0a9466c68fefd220ed70fad", + "edit": "" + }, + "DecodeMovePOperands": { + "apply_type": "OLD", + "old_hash": "a96bc6d32db269f13d8d060aa4d159690299a82cefe15ea03f05648b7d986e18", + "new_hash": "4e61793fc14e47113df183f724cd5f7f0d1583cb853065dbc8266f7b089bc632", + "edit": "" + }, + "DecodeNMRegList16Operand": { + "apply_type": "OLD", + "old_hash": "f96dcb8285057e580d1be6b4ede3179b7fc1be0f32c0696fe716e62b9ff04723", + "new_hash": "c7acc6beeba68228f433a8d3fc54c94844e457f8a94d05741ba7cd4a6f086039", + "edit": "" + }, + "DecodeNMRegListOperand": { + "apply_type": "OLD", + "old_hash": "0ba85031a34392847e9b0f499186c6ca365fea840baba36ca5ff27fb45663688", + "new_hash": "45842a384a2c20083c65b21515a3a00ded3ca2f8d59f5acb04e0733acc9a999c", + "edit": "" + }, + "DecodeNegImm12": { + "apply_type": "OLD", + "old_hash": "8ff14738e3919726cbaca7ca365d9f1c3178818a64f58158c4cacb9ecb2a687d", + "new_hash": "bb6252f2c15addaf059d1ba7b1f47d7cc02ae6238be92f647e4560770d335aa6", + "edit": "" + }, + "DecodePOP35GroupBranchMMR6": { + "apply_type": "OLD", + "old_hash": "53a498884fe3301cf09e112134e62771bae8bc3aa46db90272c35a9db5565915", + "new_hash": "73f446393c642b4617fe6efcb0ad080e991c4f7e1f641e083e4881026fb46445", + "edit": "" + }, + "DecodePOP37GroupBranchMMR6": { + "apply_type": "OLD", + "old_hash": "49d93b23a9580b2935c345c2b0466b6c47c59422d4265b09963bdada51441eae", + "new_hash": "c7ed1a1599bff2b9b87fff0a6549eec6ccc6207f4c5a5be290516ebcc7ee1a3e", + "edit": "" + }, + "DecodePOP65GroupBranchMMR6": { + "apply_type": "OLD", + "old_hash": "b926b6c5d0bfd54aa797a346f66000e8a1672f23d2e783abeea91428c100cba4", + "new_hash": "14f99fbf7d4c64ba69966b60d67ab8c8d5a2812cb061cd457c0fbd95f9df6bac", + "edit": "" + }, + "DecodePOP75GroupBranchMMR6": { + "apply_type": "OLD", + "old_hash": "6e301c1f6fcc6fd3d84926199cf4d3a978cdcc9d0e3dd9f417232a506dd6d430", + "new_hash": "f97a4f57fb762f815b6e889ac8e63e4a9b0c26ceda4b5aee1b64cfb918fb5a09", + "edit": "" + }, + "DecodePrefeOpMM": { + "apply_type": "OLD", + "old_hash": "8d23f8c770c7eacb7a3e41d7e4cd144c9ae2e9f2e0bc5dc4374d6ac8fc811a99", + "new_hash": "a098390f5c475243e3d381f7fe14e473028e0185da6ba48d6f65a6f31acf2656", + "edit": "" + }, + "DecodePtrRegisterClass": { + "apply_type": "OLD", + "old_hash": "c88ee12b61b52a617d424f5802b629f90fa2cb1ccf94a50576ef3bc439bcd8d9", + "new_hash": "ac817bd8c0b1d940301e2dd03f5a3babb4a9a3d500280d54b45a3c101cb5695a", + "edit": "" + }, + "DecodeRegListOperand": { + "apply_type": "OLD", + "old_hash": "fd09e16129914a6892242dd516f2aa9c49bb65e2d6f47ed95a35235a1b40d9ce", + "new_hash": "e3a30b6c2ffb91e465c0a3cbf227a2302c273e1f68fdd1e1e0dff4221b3b3f15", + "edit": "" + }, + "DecodeRegListOperand16": { + "apply_type": "OLD", + "old_hash": "c1b8a15998abe38932c5f229ac3bf260603ef16cf2929dc89628c83dbe633a45", + "new_hash": "d280ab0129dae87499bdbcd95c9c2276fbc9351b33f8b95c33a26fabf7b31dd6", + "edit": "" + }, + "DecodeSImm32s12": { + "apply_type": "OLD", + "old_hash": "29e42bdb00b5ec75c8ad8f96df5571d07c320529904525b0a5e91c4ea01d18f9", + "new_hash": "1c8a8f5fd8987adb84c1840d3a98551cc774008884509ba932583b1a6ec1875e", + "edit": "" + }, + "DecodeSimm18Lsl3": { + "apply_type": "OLD", + "old_hash": "337ec58cc4857ab001414417c4dbcd252ccbd44e35bfc64d14cf3600850436bc", + "new_hash": "bf5342e06889a8c23e4d193151a30a849c837562cde3199520222ff7cbbdd53f", + "edit": "" + }, + "DecodeSimm19Lsl2": { + "apply_type": "OLD", + "old_hash": "066a9fcc5a746333a55e424bef44d0fbf8c68ea3cefad4a4d55e34490d6211a6", + "new_hash": "4920c87be064b6486e63c1d10265a9a532c22938dd51075430684b3ebb0fa562", + "edit": "" + }, + "DecodeSimm23Lsl2": { + "apply_type": "OLD", + "old_hash": "b64237b78631a3465dc1ae2d19c65cf851451c080f312703d7a4dd2119e300b1", + "new_hash": "05e0eecb8bda7b20b70d96715a44d1483138ebfeb215820c75b0ce5fe8b9dec5", + "edit": "" + }, + "DecodeSimm9SP": { + "apply_type": "OLD", + "old_hash": "4c87e0a4198804e5e1fc2f0b1abbd23319abcfeae19052b95bf7b00a8d4df309", + "new_hash": "d98a0e6a5fc24103d3c78ebd8117b1ccd34a483e52074a078d2b11e25bb90780", + "edit": "" + }, + "DecodeSpecial3LlSc": { + "apply_type": "OLD", + "old_hash": "8752cf0cfa82a4d5ba0b82121520b29543dff239c6c7a957171a9cffd30e5314", + "new_hash": "25c7ccae2aff64329ff42d70fb056747fc4c7257ced2e26d51cba79c63f6024c", + "edit": "" + }, + "DecodeSyncI": { + "apply_type": "OLD", + "old_hash": "5bdb29a28762e42ef5ac19ba87e21d2c46ee2ddf3ed8c6b1e022ffa6752d5a48", + "new_hash": "af635d413628c225cdb262e1cd21dba41e171ebe0882e94521eb1cc93663705e", + "edit": "" + }, + "DecodeSyncI_MM": { + "apply_type": "OLD", + "old_hash": "681b11ef81a46fa521562d8c65cf672bd7c85c6d1bfeb44e43bd87e5e4b7ff00", + "new_hash": "e5cab30ec69fbd726bf6e56176d3408f8a6b7fbaef06539a394837ffbdbe22b3", + "edit": "" + }, + "DecodeSynciR6": { + "apply_type": "OLD", + "old_hash": "8b9fb69fe9e0b85ec096c69bc19ddcc47087d492b34079eaae7eeebab08568c0", + "new_hash": "6630651947b583a75c4f01c85ce8bd4b05c119608832963f3cdd56ad909ab08f", + "edit": "" + }, + "Mips_LLVM_getInstruction": { + "apply_type": "OLD", + "old_hash": "e27bddc566d186439317d346fc9166d3be001e3600a09f57da514cd94d34406b", + "new_hash": "", + "edit": "" + }, + "Mips_getFeatureBits": { + "apply_type": "OLD", + "old_hash": "2b6439bb0b486d29ff80b9d798e14de27cb3e9ef8d5c76c90c2535f1a82dfa0f", + "new_hash": "", + "edit": "" + }, + "createMipsDisassembler": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "70caa937fabe2a6724b7e1ea41f89f3d4f5dfe32587f8463296bd82404820166", + "edit": "" + }, + "createMipselDisassembler": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "288710a2c9d424fdf70bce7f865c3e45faf22be460241591e25b99d3c5b84ba4", + "edit": "" + }, + "getInstruction": { + "apply_type": "OLD", + "old_hash": "52fc65a707feef93d6bd7c7c6f55851d2c93be45650efe21fe031b8928f2eb4c", + "new_hash": "aca77782b4160891075cb2f890401385cde140c255d109d1ed08c693f2cc10ba", + "edit": "" + }, + "getReg": { + "apply_type": "OLD", + "old_hash": "ac19a0b9b4303b13c480b83f7b80058cc6e6614fc237b0bad40dfa90ef4b8b43", + "new_hash": "cec427f39760a8df832b75bf51b2b4714323fd3e1373e5a7d1ea7981c5d0d461", + "edit": "" + }, + "readInstruction16": { + "apply_type": "OLD", + "old_hash": "97a35e0038b8c65211b379e4056300253388880078f294554a66c24ad9098838", + "new_hash": "b557ab16a7fbf7deae9d94d0d0c27e0763c4aff63e7df8a26c25c2a9b574e24d", + "edit": "" + }, + "readInstruction32": { + "apply_type": "OLD", + "old_hash": "2c457bf651fe2170716e5db95b8f674e5b14c03e694a58832a47f543ade71687", + "new_hash": "b0605f16c54c20bdef3619448a56a99552a8b83c46f70b15b0fce4daa9023368", + "edit": "" + }, + "readInstruction48": { + "apply_type": "OLD", + "old_hash": "52da39fa622a75b02161317d6bd93b17bcca0fa9691e251e79fe4bb63f67785c", + "new_hash": "f680512de5c7f01db4fff30c051dbd924d9414b2111b2a9e40bd520e829588e4", + "edit": "" + } + }, + "MipsInstPrinter.c": { + "DEFINE_printUImm": { + "apply_type": "OLD", + "old_hash": "53ae0f1c9bc04d13f0d04872cf7967f3240239de0167e89a7bbb9c88f9693d7a", + "new_hash": "facdff402f9d252c808d90a54209081ef8cb55d89a44e0416f3e1b2f8875a925", + "edit": "" + }, + "DEFINE_printUImm_2": { + "apply_type": "OLD", + "old_hash": "6c19b6355fa6035f8c5ed42c829539e439024448c2cbb29673edafd6a2a52167", + "new_hash": "", + "edit": "" + }, + "MipsFCCToString": { + "apply_type": "OLD", + "old_hash": "7182d974e8a5d575736c86cc7a88bf59ff0bbae99cde83a72a4befeacae0b192", + "new_hash": "d2442362ae7a9c5a3edaecfacb6b2f198b4a64ab892eb8f4c94ca4164ce6df64", + "edit": "" + }, + "Mips_LLVM_getRegisterName": { + "apply_type": "OLD", + "old_hash": "df6019c36822141534647a1401f2ad35a93afd55850942f97b9142eb8c40f832", + "new_hash": "", + "edit": "" + }, + "Mips_LLVM_printInst": { + "apply_type": "OLD", + "old_hash": "660b5eba392f6b7738cb3f241e8ff34f2a0137b12c7ca36b1ccbe0832d345d1d", + "new_hash": "", + "edit": "" + }, + "isReg": { + "apply_type": "OLD", + "old_hash": "34203d392642dffc6802f8b83461970f5a2b494c0161e55e200b8c2c6bf7a54b", + "new_hash": "97981713a49723ff8194dffcb4cae77b8da54a5467320dbace0e30dcca3f62c2", + "edit": "" + }, + "printAlias": { + "apply_type": "OLD", + "old_hash": "3e91b4b218d68fbf5862e6f714320bf0c0292c1fe31fc039a1e2aac5b876d67b", + "new_hash": "", + "edit": "" + }, + "printAlias2": { + "apply_type": "OLD", + "old_hash": "6e3b2448fb62f2bbd6684652184b4e5adcba323318d73b7ee4aef4acc896f4c9", + "new_hash": "", + "edit": "" + }, + "printAlias3": { + "apply_type": "OLD", + "old_hash": "4eb79f76f7d84a89fb7db7259c2ba8903f0a426b0827da757338cf4a76686fa0", + "new_hash": "", + "edit": "" + }, + "printAlias4": { + "apply_type": "OLD", + "old_hash": "68e131d12b29b480dd0981ae73566892486f6cb947b9bc3d737801eed2a37808", + "new_hash": "", + "edit": "" + }, + "printAliasHex": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "1dd77aad2f90881b3df09dff4b624a3f1bd7842c59ed9215d8f864ed57edf69a", + "edit": "" + }, + "printBranchOperand": { + "apply_type": "OLD", + "old_hash": "55c249da72a1afe6c1fffa0df01e2f152b00e8db92b3bdff098c64021e639e07", + "new_hash": "ae3c09e80b494cf5f50f5635c100acc19e0aa2dbe45cc30fab652337deb35d03", + "edit": "" + }, + "printFCCOperand": { + "apply_type": "OLD", + "old_hash": "dca2d4e01ca07a1058df9e3b624aca7c56aece157c137d16cc709ac2e68ac3ba", + "new_hash": "d9c750542ff035652477778a34d7892f881088172d2787dd455320acb0334a5c", + "edit": "" + }, + "printHi20": { + "apply_type": "OLD", + "old_hash": "2964fb32cbd0f9508d6f62a372211f396eb11642f0e8ae3e8e2bf6926f090ada", + "new_hash": "2e048e424a08cb5f6781d7d92a507e111452ea34d0a2fbe8545716c6d3fdd70c", + "edit": "" + }, + "printHi20PCRel": { + "apply_type": "OLD", + "old_hash": "1e501b0a3f2fd3556a6ba59dcb70ea2b5de37060390d628e952f2fec787360eb", + "new_hash": "d5f95f06aba32b0f3a2920b319c33e69ec3ec1598a35b2462df419aa9a6841a6", + "edit": "" + }, + "printInst": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "3aec06d252656b5d52191046737785e713ba284069d7877b347c94e25b02a546", + "edit": "" + }, + "printJumpOperand": { + "apply_type": "OLD", + "old_hash": "6d084ada9b6feec97e1548800407bbbe428a8787c514992d9bf8efd73176f717", + "new_hash": "844ffab898f4ad38b9b9467897583d1b6c65cebdae729df0412af73537c97e64", + "edit": "" + }, + "printMemOperand": { + "apply_type": "OLD", + "old_hash": "0bee738dab28731710512bf16fa03f31f10209f777cea83f0d16aa66412e6201", + "new_hash": "b23d985030fe56708a6cb5bb6a433c24fbca10e89f094a24ebfeae33b65af0d3", + "edit": "" + }, + "printMemOperandEA": { + "apply_type": "OLD", + "old_hash": "0629eed2d2eee3a553c38cb62077ce29e4398f601afa06d0233f4cf70c976cea", + "new_hash": "615aacb0ba3bb7bc63c827aaef822bfb7552b9688408181f819a8aaa388dd123", + "edit": "" + }, + "printMemOperandGPRel": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "03a58352102b07f37da60354963648a2d0c383bfb3755aa06a33b85a0b81364c", + "edit": "" + }, + "printNanoMipsRegisterList": { + "apply_type": "OLD", + "old_hash": "d5e6ad71c9661c2996c8d3fd158d854c7968d994c2443cbb87db4eaf27b38602", + "new_hash": "93f0b35923e7f7079d1a4ad82b9b7bcf75f61bfa7c8b77f745954be739771e0d", + "edit": "" + }, + "printOperand": { + "apply_type": "OLD", + "old_hash": "f82a0d318d803c5e649a76333382391aaf33a5f70111d8097fd1a0e29806f25b", + "new_hash": "2b2d943eefb4583bd34b5019b60892078c38b58e9304d63927d9034ce5d8b2a9", + "edit": "" + }, + "printPCRel": { + "apply_type": "OLD", + "old_hash": "cbea0cd3eeece2e8e35a20a198c68f9dc8768e85225e71c22ec0b41a6fdd45e7", + "new_hash": "56fa496c7e24b743f39d041a74c8625d8c513c239112aff9b2097b5f9365ff46", + "edit": "" + }, + "printRegName": { + "apply_type": "OLD", + "old_hash": "2bb60804f739dbad89ceadcea389c7b4151a11feac690098942a28fc56288beb", + "new_hash": "229be3874bde1bf33bc0120c4b8c6134d789903c49fe21b2e3d33a4185854357", + "edit": "" + }, + "printRegisterList": { + "apply_type": "OLD", + "old_hash": "cbdbe99cacca7a7173ff929ef118be9f3968b1619c58f3f3cb20000a223d3770", + "new_hash": "774bbb5782799c798145d78be150dc2b2c7016ebf4723988122610d034402ada", + "edit": "" + }, + "printSHFMask": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "6a1963dc458109069478f4474a8158a025c3177263daac00c45504d5da042391", + "edit": "" + }, + "printSaveRestore": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "f5c17b2b290fa440877c0b85c85bcc9b050891db002932e0c6448b7f5649339d", + "edit": "" + } + }, + "MipsInstPrinter.h": { + "DECLARE_printUImm": { + "apply_type": "OLD", + "old_hash": "faefa6d7d623550d91fcf096238173c734b43b0717806ce8313f4c4ffb549cd8", + "new_hash": "6bae637a74ba6624001e568e7b960417c99cd2b8fa2d310bc30b1328585cd223", + "edit": "" + }, + "DECLARE_printUImm_2": { + "apply_type": "OLD", + "old_hash": "81028329d6713020ee9beb36a8a459f2672dd35838aa2f682f74407c9dda8dc0", + "new_hash": "", + "edit": "" + } } } \ No newline at end of file diff --git a/suite/auto-sync/src/autosync/mcupdater.json b/suite/auto-sync/src/autosync/mcupdater.json index 5e0e26618..71fb8218d 100644 --- a/suite/auto-sync/src/autosync/mcupdater.json +++ b/suite/auto-sync/src/autosync/mcupdater.json @@ -1,10 +1,79 @@ { - "additional_mattr": - { - "AArch64": [ "+all" ] - }, - "mandatory_options": - { - "SystemZ": [ "CS_MODE_BIG_ENDIAN" ] - } -} + "additional_mattr": + { + "AArch64": + [ + "+all" + ] + }, + "mandatory_options": + { + "SystemZ": + [ + "CS_MODE_BIG_ENDIAN" + ], + "Mips": + [ + "CS_OPT_SYNTAX_NOREGNAME" + ] + }, + "remove_options": + { + "Mips": + [ + "mips", + "dsp", + "dspr2", + "dspr3", + "mips3d", + "msa", + "eva", + "crc", + "virt", + "ginv", + "fp64", + "+virt", + "mt" + ] + }, + "replace_option_map": + { + "Mips": + { + "mips-unknown-linux": "CS_MODE_BIG_ENDIAN", + "mips-unknown-linux-gnu": "CS_MODE_BIG_ENDIAN", + "mips32-unknown-linux": "CS_MODE_BIG_ENDIAN", + "mips64-unknown-linux": "CS_MODE_BIG_ENDIAN", + "mips64-unknown-linux-gnu": "CS_MODE_BIG_ENDIAN", + "mips64el-unknown-linux": "CS_MODE_LITTLE_ENDIAN", + "mips64el-unknown-linux-gnu": "CS_MODE_LITTLE_ENDIAN", + "mipsel": "CS_MODE_LITTLE_ENDIAN", + "mipsel-unknown-linux": "CS_MODE_LITTLE_ENDIAN", + "mipsel-unknown-linux-gnu": "CS_MODE_LITTLE_ENDIAN", + "mips16": "CS_MODE_MIPS16", + "mips32": "CS_MODE_MIPS32", + "mips64": "CS_MODE_MIPS64", + "micromips": "CS_MODE_MICRO", + "mips1": "CS_MODE_MIPS1", + "mips2": "CS_MODE_MIPS2", + "mips32r2": "CS_MODE_MIPS32R2", + "mips32r3": "CS_MODE_MIPS32R3", + "mips32r5": "CS_MODE_MIPS32R5", + "mips32r6": "CS_MODE_MIPS32R6", + "mips3": "CS_MODE_MIPS3", + "mips4": "CS_MODE_MIPS4", + "mips5": "CS_MODE_MIPS5", + "mips64r2": "CS_MODE_MIPS64R2", + "mips64r3": "CS_MODE_MIPS64R3", + "mips64r5": "CS_MODE_MIPS64R5", + "mips64r6": "CS_MODE_MIPS64R6", + "octeon": "CS_MODE_OCTEON", + "octeon+": "CS_MODE_OCTEONP", + "nanomips": "CS_MODE_NANOMIPS", + "nms1": "CS_MODE_NMS1", + "i7200": "CS_MODE_I7200", + "mips_nofloat": "CS_MODE_MIPS_NOFLOAT", + "mips_ptr64": "CS_MODE_MIPS_PTR64" + } + } +} \ No newline at end of file diff --git a/suite/cstest/include/test_mapping.h b/suite/cstest/include/test_mapping.h index 7ef546b52..f796840b0 100644 --- a/suite/cstest/include/test_mapping.h +++ b/suite/cstest/include/test_mapping.h @@ -73,6 +73,7 @@ static const cs_enum_id_map test_mode_map[] = { { .str = "CS_MODE_HPPA_11", .val = CS_MODE_HPPA_11 }, { .str = "CS_MODE_HPPA_20", .val = CS_MODE_HPPA_20 }, { .str = "CS_MODE_HPPA_20W", .val = CS_MODE_HPPA_20W }, + { .str = "CS_MODE_I7200", .val = CS_MODE_I7200 }, { .str = "CS_MODE_LITTLE_ENDIAN", .val = CS_MODE_LITTLE_ENDIAN }, { .str = "CS_MODE_LOONGARCH32", .val = CS_MODE_LOONGARCH32 }, { .str = "CS_MODE_LOONGARCH64", .val = CS_MODE_LOONGARCH64 }, @@ -94,11 +95,26 @@ static const cs_enum_id_map test_mode_map[] = { { .str = "CS_MODE_M68K_060", .val = CS_MODE_M68K_060 }, { .str = "CS_MODE_MCLASS", .val = CS_MODE_MCLASS }, { .str = "CS_MODE_MICRO", .val = CS_MODE_MICRO }, + { .str = "CS_MODE_MICRO32R3", .val = CS_MODE_MICRO32R3 }, + { .str = "CS_MODE_MICRO32R6", .val = CS_MODE_MICRO32R6 }, + { .str = "CS_MODE_MIPS1", .val = CS_MODE_MIPS1 }, + { .str = "CS_MODE_MIPS16", .val = CS_MODE_MIPS16 }, { .str = "CS_MODE_MIPS2", .val = CS_MODE_MIPS2 }, { .str = "CS_MODE_MIPS3", .val = CS_MODE_MIPS3 }, { .str = "CS_MODE_MIPS32", .val = CS_MODE_MIPS32 }, + { .str = "CS_MODE_MIPS32R2", .val = CS_MODE_MIPS32R2 }, + { .str = "CS_MODE_MIPS32R3", .val = CS_MODE_MIPS32R3 }, + { .str = "CS_MODE_MIPS32R5", .val = CS_MODE_MIPS32R5 }, { .str = "CS_MODE_MIPS32R6", .val = CS_MODE_MIPS32R6 }, + { .str = "CS_MODE_MIPS4", .val = CS_MODE_MIPS4 }, + { .str = "CS_MODE_MIPS5", .val = CS_MODE_MIPS5 }, { .str = "CS_MODE_MIPS64", .val = CS_MODE_MIPS64 }, + { .str = "CS_MODE_MIPS64R2", .val = CS_MODE_MIPS64R2 }, + { .str = "CS_MODE_MIPS64R3", .val = CS_MODE_MIPS64R3 }, + { .str = "CS_MODE_MIPS64R5", .val = CS_MODE_MIPS64R5 }, + { .str = "CS_MODE_MIPS64R6", .val = CS_MODE_MIPS64R6 }, + { .str = "CS_MODE_MIPS_NOFLOAT", .val = CS_MODE_MIPS_NOFLOAT }, + { .str = "CS_MODE_MIPS_PTR64", .val = CS_MODE_MIPS_PTR64 }, { .str = "CS_MODE_MOS65XX_6502", .val = CS_MODE_MOS65XX_6502 }, { .str = "CS_MODE_MOS65XX_65816", .val = CS_MODE_MOS65XX_65816 }, { .str = "CS_MODE_MOS65XX_65816_LONG_M", @@ -109,6 +125,10 @@ static const cs_enum_id_map test_mode_map[] = { .val = CS_MODE_MOS65XX_65816_LONG_X }, { .str = "CS_MODE_MOS65XX_65C02", .val = CS_MODE_MOS65XX_65C02 }, { .str = "CS_MODE_MOS65XX_W65C02", .val = CS_MODE_MOS65XX_W65C02 }, + { .str = "CS_MODE_NANOMIPS", .val = CS_MODE_NANOMIPS }, + { .str = "CS_MODE_NMS1", .val = CS_MODE_NMS1 }, + { .str = "CS_MODE_OCTEON", .val = CS_MODE_OCTEON }, + { .str = "CS_MODE_OCTEONP", .val = CS_MODE_OCTEONP }, { .str = "CS_MODE_PS", .val = CS_MODE_PS }, { .str = "CS_MODE_QPX", .val = CS_MODE_QPX }, { .str = "CS_MODE_RISCV32", .val = CS_MODE_RISCV32 }, diff --git a/suite/cstest/src/test_run.c b/suite/cstest/src/test_run.c index 36e2b0a59..06919c6c3 100644 --- a/suite/cstest/src/test_run.c +++ b/suite/cstest/src/test_run.c @@ -102,17 +102,18 @@ static bool parse_input_options(const TestInput *input, cs_arch *arch, } *mode = 0; - bool mode_found = false; size_t opt_idx = 0; char **options = input->options; for (size_t i = 0; i < input->options_count; ++i) { + bool opt_found = false; opt_str = options[i]; val = enum_map_bin_search(test_mode_map, - ARR_SIZE(test_mode_map), opt_str, - &mode_found); - if (mode_found) { + ARR_SIZE(test_mode_map), + opt_str, &opt_found); + + if (opt_found) { *mode |= val; - goto next_option; + continue; } // Might be an option descriptor @@ -126,12 +127,12 @@ static bool parse_input_options(const TestInput *input, cs_arch *arch, return false; } opt_arr[opt_idx++] = test_option_map[k].opt; - goto next_option; + opt_found = true; } } - fprintf(stderr, "[!] Option: '%s' not used\n", opt_str); -next_option: - continue; + if (!opt_found) { + fprintf(stderr, "[!] Option: '%s' not used\n", opt_str); + } } *opt_set = opt_idx; return true; diff --git a/tests/MC/Mips/invalid-xfail.txt.yaml b/tests/MC/Mips/invalid-xfail.txt.yaml new file mode 100644 index 000000000..39dfbe442 --- /dev/null +++ b/tests/MC/Mips/invalid-xfail.txt.yaml @@ -0,0 +1,70 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x45, 0x06, 0x00, 0x83 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1fl $fcc1, 528" + + - + input: + bytes: [ 0x45, 0x07, 0xd8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1tl $fcc1, -40948" + + - + input: + bytes: [ 0x45, 0x08, 0x14, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc2, 20496" + + - + input: + bytes: [ 0x45, 0x09, 0x01, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc2, 1036" + + - + input: + bytes: [ 0x48, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc2 $zero, $0, 1" + + - + input: + bytes: [ 0x48, 0x86, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtc2 $6, $0, 4" diff --git a/tests/MC/Mips/invalid.txt.yaml b/tests/MC/Mips/invalid.txt.yaml new file mode 100644 index 000000000..f2ab6ba78 --- /dev/null +++ b/tests/MC/Mips/invalid.txt.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "nop" diff --git a/tests/MC/Mips/mftr-mttr-aliases.s.yaml b/tests/MC/Mips/mftr-mttr-aliases.s.yaml new file mode 100644 index 000000000..2b7009401 --- /dev/null +++ b/tests/MC/Mips/mftr-mttr-aliases.s.yaml @@ -0,0 +1,380 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 0, 0, 0" + + - + input: + bytes: [ 0x41, 0x07, 0x30, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $6, $7, 0, 1, 0" + + - + input: + bytes: [ 0x41, 0x09, 0x28, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $5, $9, 1, 0, 0" + + - + input: + bytes: [ 0x41, 0x00, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x04, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $4, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x08, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $8, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0c, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $12, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x01, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $1, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x05, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $5, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x09, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $9, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0d, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $13, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x02, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $2, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x06, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $6, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $10, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0e, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $14, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x10, 0x20, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $16, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 1, 2, 0" + + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 1, 2, 1" + + - + input: + bytes: [ 0x41, 0x09, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $9, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 0, 0, 0" + + - + input: + bytes: [ 0x41, 0x86, 0x38, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $6, $7, 0, 1, 0" + + - + input: + bytes: [ 0x41, 0x85, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $5, $9, 1, 0, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x20, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $4, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x40, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $8, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x60, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $12, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x08, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $1, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x28, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $5, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $9, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x68, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $13, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x10, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $2, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $6, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x50, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $10, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x70, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $14, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $16, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 1, 2, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 1, 2, 1" + + - + input: + bytes: [ 0x41, 0x84, 0x48, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $9, 1, 3, 0" diff --git a/tests/MC/Mips/mftr-mttr-reserved-valid.s.yaml b/tests/MC/Mips/mftr-mttr-reserved-valid.s.yaml new file mode 100644 index 000000000..cc551979c --- /dev/null +++ b/tests/MC/Mips/mftr-mttr-reserved-valid.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x1f, 0xf8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $ra, $ra, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x9f, 0xf8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $ra, $ra, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0d, 0xf8, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $ra, $13, 1, 6, 0" + + - + input: + bytes: [ 0x41, 0x9f, 0x68, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $ra, $13, 1, 6, 0" diff --git a/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml b/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml index 352ff3e9a..12e38c309 100644 --- a/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x49, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x11, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x31, 0x26, 0xc5, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x11, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x31, 0x26, 0xc5, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x49, 0x50 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x49, 0x90 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x00, 0xa3, 0x21, 0xd0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -75,25 +75,25 @@ test_cases: input: bytes: [ 0x00, 0xe0, 0x31, 0x90 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "sub $a2, $zero, $a3" + asm_text: "neg $a2, $a3" - input: bytes: [ 0x00, 0xe0, 0x31, 0xd0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "subu $a2, $zero, $a3" + asm_text: "negu $a2, $a3" - input: bytes: [ 0x00, 0x08, 0x39, 0x50 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0x00, 0xa3, 0x1b, 0x50 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0x90, 0x63, 0x00, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x90, 0x63, 0x00, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0xb0, 0x63, 0x00, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0x00, 0xa3, 0x1b, 0x90 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0x41, 0xa9, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x4a, 0x50 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0xd1, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0xd1, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0x00, 0xa4, 0x1a, 0x90 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0x51, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0x00, 0xa3, 0x1b, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0x71, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x71, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x4a, 0xd0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0x00, 0x08, 0x3a, 0xd0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x4a, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0x00, 0xe9, 0x8b, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0x00, 0xe9, 0x9b, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0x00, 0xe9, 0xab, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -282,7 +282,7 @@ test_cases: input: bytes: [ 0x00, 0xe9, 0xbb, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-alu-instructions.s.yaml b/tests/MC/Mips/micromips-alu-instructions.s.yaml index 116479a58..7550a57ae 100644 --- a/tests/MC/Mips/micromips-alu-instructions.s.yaml +++ b/tests/MC/Mips/micromips-alu-instructions.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0xe6, 0x00, 0x10, 0x49 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x26, 0x11, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x26, 0x31, 0x67, 0xc5 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x26, 0x11, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x26, 0x31, 0x67, 0xc5 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0xe6, 0x00, 0x50, 0x49 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0xe6, 0x00, 0x90, 0x49 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0xa3, 0x00, 0xd0, 0x21 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -75,25 +75,25 @@ test_cases: input: bytes: [ 0xe0, 0x00, 0x90, 0x31 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "sub $a2, $zero, $a3" + asm_text: "neg $a2, $a3" - input: bytes: [ 0xe0, 0x00, 0xd0, 0x31 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "subu $a2, $zero, $a3" + asm_text: "negu $a2, $a3" - input: bytes: [ 0x08, 0x00, 0x50, 0x39 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0xa3, 0x00, 0x50, 0x1b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0x63, 0x90, 0x67, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x63, 0x90, 0x67, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0x63, 0xb0, 0x67, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0xa3, 0x00, 0x90, 0x1b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0xa9, 0x41, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0xe6, 0x00, 0x50, 0x4a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0x26, 0xd1, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0x26, 0xd1, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0xa4, 0x00, 0x90, 0x1a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0x26, 0x51, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0xa3, 0x00, 0x10, 0x1b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0x26, 0x71, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x26, 0x71, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0xe6, 0x00, 0xd0, 0x4a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0x08, 0x00, 0xd0, 0x3a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0xe6, 0x00, 0x10, 0x4a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0xe9, 0x00, 0x3c, 0x8b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0xe9, 0x00, 0x3c, 0x9b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0xe9, 0x00, 0x3c, 0xab ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -282,7 +282,7 @@ test_cases: input: bytes: [ 0xe9, 0x00, 0x3c, 0xbb ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml b/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml index 019ad6229..0fc98c5b2 100644 --- a/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml @@ -3,80 +3,80 @@ test_cases: input: bytes: [ 0x94, 0x00, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "b 1332" + asm_text: "b 1336" - input: bytes: [ 0x94, 0xc9, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "beq $t1, $a2, 1332" + asm_text: "beq $t1, $a2, 1336" - input: bytes: [ 0x40, 0x46, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "bgez $a2, 1332" + asm_text: "bgez $a2, 1336" - input: bytes: [ 0x40, 0x66, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "bgezal $a2, 1332" + asm_text: "bgezal $a2, 1336" - input: bytes: [ 0x40, 0x26, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "bltzal $a2, 1332" + asm_text: "bltzal $a2, 1336" - input: bytes: [ 0x40, 0xc6, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "bgtz $a2, 1332" + asm_text: "bgtz $a2, 1336" - input: bytes: [ 0x40, 0x86, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "blez $a2, 1332" + asm_text: "blez $a2, 1336" - input: bytes: [ 0xb4, 0xc9, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "bne $t1, $a2, 1332" + asm_text: "bne $t1, $a2, 1336" - input: bytes: [ 0x40, 0x06, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "bltz $a2, 1332" + asm_text: "bltz $a2, 1336" diff --git a/tests/MC/Mips/micromips-branch-instructions.s.yaml b/tests/MC/Mips/micromips-branch-instructions.s.yaml index 7da105943..e117e5283 100644 --- a/tests/MC/Mips/micromips-branch-instructions.s.yaml +++ b/tests/MC/Mips/micromips-branch-instructions.s.yaml @@ -7,7 +7,7 @@ test_cases: expected: insns: - - asm_text: "b 1332" + asm_text: "b 1336" - input: bytes: [ 0xc9, 0x94, 0x9a, 0x02 ] @@ -16,7 +16,7 @@ test_cases: expected: insns: - - asm_text: "beq $t1, $a2, 1332" + asm_text: "beq $t1, $a2, 1336" - input: bytes: [ 0x46, 0x40, 0x9a, 0x02 ] @@ -25,7 +25,7 @@ test_cases: expected: insns: - - asm_text: "bgez $a2, 1332" + asm_text: "bgez $a2, 1336" - input: bytes: [ 0x66, 0x40, 0x9a, 0x02 ] @@ -34,7 +34,7 @@ test_cases: expected: insns: - - asm_text: "bgezal $a2, 1332" + asm_text: "bgezal $a2, 1336" - input: bytes: [ 0x26, 0x40, 0x9a, 0x02 ] @@ -43,7 +43,7 @@ test_cases: expected: insns: - - asm_text: "bltzal $a2, 1332" + asm_text: "bltzal $a2, 1336" - input: bytes: [ 0xc6, 0x40, 0x9a, 0x02 ] @@ -52,7 +52,7 @@ test_cases: expected: insns: - - asm_text: "bgtz $a2, 1332" + asm_text: "bgtz $a2, 1336" - input: bytes: [ 0x86, 0x40, 0x9a, 0x02 ] @@ -61,7 +61,7 @@ test_cases: expected: insns: - - asm_text: "blez $a2, 1332" + asm_text: "blez $a2, 1336" - input: bytes: [ 0xc9, 0xb4, 0x9a, 0x02 ] @@ -70,7 +70,7 @@ test_cases: expected: insns: - - asm_text: "bne $t1, $a2, 1332" + asm_text: "bne $t1, $a2, 1336" - input: bytes: [ 0x06, 0x40, 0x9a, 0x02 ] @@ -79,4 +79,4 @@ test_cases: expected: insns: - - asm_text: "bltz $a2, 1332" + asm_text: "bltz $a2, 1336" diff --git a/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml b/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml index b709a41cc..0278fcc0b 100644 --- a/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0xd4, 0x00, 0x02, 0x98 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0xf4, 0x00, 0x02, 0x98 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x00, 0x07, 0x0f, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml b/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml index 2040ea000..e769af947 100644 --- a/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x1c, 0xa4, 0x00, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x14, 0xc4, 0x00, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x3c, 0x44, 0x00, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x34, 0x82, 0x00, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0xfc, 0xc5, 0x00, 0x04 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x18, 0xa4, 0x00, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x38, 0x44, 0x00, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0xf8, 0xa6, 0x00, 0x04 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml b/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml index 897c1d18d..ca38b1edd 100644 --- a/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml +++ b/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x60, 0x85, 0x00, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x60, 0x85, 0x10, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x60, 0x85, 0x80, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x60, 0x85, 0x90, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml b/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml index 7559e3559..6a0722d01 100644 --- a/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x48, 0x58 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x48, 0x18 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x55, 0x26, 0x09, 0x7b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x55, 0x26, 0x01, 0x7b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml b/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml index f5d5e1ebd..7686b1c01 100644 --- a/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x00, 0xa4, 0xcb, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x00, 0xa4, 0xdb, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x00, 0xa4, 0xeb, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x00, 0xa4, 0xfb, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml b/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml index c833369cf..253c046dc 100644 --- a/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x00, 0x83, 0x38, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x00, 0x65, 0x10, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x00, 0x83, 0x38, 0x80 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x00, 0x65, 0x10, 0x90 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x00, 0x83, 0x38, 0x40 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x00, 0x65, 0x10, 0x50 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x01, 0x26, 0x38, 0xc0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x00, 0xc7, 0x48, 0xd0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml b/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml index 9f83c760d..3b31c55e3 100644 --- a/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x41, 0xc9, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x41, 0x29, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x41, 0x69, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x41, 0x09, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x41, 0x49, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x41, 0x89, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/mips-alu-instructions.s.yaml b/tests/MC/Mips/mips-alu-instructions.s.yaml index bf9dbc82c..37db7bab0 100644 --- a/tests/MC/Mips/mips-alu-instructions.s.yaml +++ b/tests/MC/Mips/mips-alu-instructions.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x24, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x30 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x30 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0x29, 0x31 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x21, 0x30, 0xe6, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x20, 0x30, 0xe6, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x84, 0x61, 0x33, 0x7d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x27, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -75,7 +75,7 @@ test_cases: input: bytes: [ 0x25, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -84,7 +84,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xa4, 0x34 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -93,7 +93,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x34 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0x80, 0x00, 0x6b, 0x35 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0xc2, 0x49, 0x26, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x46, 0x48, 0xe6, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0xc0, 0x21, 0x03, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0x04, 0x10, 0xa3, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0x2a, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0x67, 0x00, 0x63, 0x28 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0x67, 0x00, 0x63, 0x28 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0x67, 0x00, 0x63, 0x2c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0x2b, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0xc3, 0x21, 0x03, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0x07, 0x10, 0xa3, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0xc2, 0x21, 0x03, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x06, 0x10, 0xa3, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0x26, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x38 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x38 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0x0c, 0x00, 0x6b, 0x39 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0xa0, 0x30, 0x07, 0x7c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0x27, 0x38, 0x00, 0x01 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -282,7 +282,7 @@ test_cases: input: bytes: [ 0x20, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -291,7 +291,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -300,7 +300,7 @@ test_cases: input: bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -309,7 +309,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -318,7 +318,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0x29, 0x21 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -327,7 +327,7 @@ test_cases: input: bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -336,7 +336,7 @@ test_cases: input: bytes: [ 0x28, 0x00, 0x6b, 0x25 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -345,7 +345,7 @@ test_cases: input: bytes: [ 0x21, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -354,7 +354,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -363,7 +363,7 @@ test_cases: input: bytes: [ 0x01, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -372,7 +372,7 @@ test_cases: input: bytes: [ 0x04, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -381,7 +381,7 @@ test_cases: input: bytes: [ 0x05, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -390,7 +390,7 @@ test_cases: input: bytes: [ 0x18, 0x00, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -399,7 +399,7 @@ test_cases: input: bytes: [ 0x19, 0x00, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -408,7 +408,7 @@ test_cases: input: bytes: [ 0x22, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -417,7 +417,7 @@ test_cases: input: bytes: [ 0xc8, 0xff, 0xbd, 0x23 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -426,7 +426,7 @@ test_cases: input: bytes: [ 0x23, 0x20, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -435,7 +435,7 @@ test_cases: input: bytes: [ 0xd8, 0xff, 0xbd, 0x27 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -444,7 +444,7 @@ test_cases: input: bytes: [ 0x22, 0x30, 0x07, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -453,7 +453,7 @@ test_cases: input: bytes: [ 0x23, 0x30, 0x07, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -462,7 +462,7 @@ test_cases: input: bytes: [ 0x21, 0x38, 0x00, 0x01 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - diff --git a/tests/MC/Mips/mips-control-instructions-64.s.yaml b/tests/MC/Mips/mips-control-instructions-64.s.yaml index 4986ca48b..7980fd7a8 100644 --- a/tests/MC/Mips/mips-control-instructions-64.s.yaml +++ b/tests/MC/Mips/mips-control-instructions-64.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0x00, 0x0d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x00, 0x07, 0x01, 0x4d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0x00, 0x0c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x00, 0x0d, 0x15, 0x0c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x42, 0x00, 0x00, 0x18 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x42, 0x00, 0x00, 0x1f ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -75,7 +75,7 @@ test_cases: input: bytes: [ 0x41, 0x6a, 0x60, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -84,7 +84,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -93,7 +93,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0x41, 0x6a, 0x60, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0x42, 0x00, 0x00, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x34 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x74 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0x04, 0x6c, 0x00, 0x01 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x30 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0xf0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0x04, 0x68, 0x00, 0x03 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x31 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x01, 0xf1 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0x04, 0x69, 0x00, 0x07 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x32 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x07, 0xf2 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x04, 0x6a, 0x00, 0x1f ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x33 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x3f, 0xf3 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0x04, 0x6b, 0x00, 0xff ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x36 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0xff, 0xf6 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0x04, 0x6e, 0x03, 0xff ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - diff --git a/tests/MC/Mips/mips-control-instructions.s.yaml b/tests/MC/Mips/mips-control-instructions.s.yaml index b526a9833..f6db34404 100644 --- a/tests/MC/Mips/mips-control-instructions.s.yaml +++ b/tests/MC/Mips/mips-control-instructions.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0x00, 0x0d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x00, 0x07, 0x01, 0x4d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0x00, 0x0c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x00, 0x0d, 0x15, 0x0c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x42, 0x00, 0x00, 0x18 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x42, 0x00, 0x00, 0x1f ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -75,7 +75,7 @@ test_cases: input: bytes: [ 0x41, 0x6a, 0x60, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -84,7 +84,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -93,7 +93,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0x41, 0x6a, 0x60, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0x42, 0x00, 0x00, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x34 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x74 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0x04, 0x6c, 0x00, 0x01 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x30 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0xf0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0x04, 0x68, 0x00, 0x03 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x31 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x01, 0xf1 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0x04, 0x69, 0x00, 0x07 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x32 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x07, 0xf2 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x04, 0x6a, 0x00, 0x1f ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x33 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x3f, 0xf3 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0x04, 0x6b, 0x00, 0xff ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x36 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0xff, 0xf6 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0x04, 0x6e, 0x03, 0xff ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - diff --git a/tests/MC/Mips/mips-coprocessor-encodings.s.yaml b/tests/MC/Mips/mips-coprocessor-encodings.s.yaml index 805d490ac..063624f7b 100644 --- a/tests/MC/Mips/mips-coprocessor-encodings.s.yaml +++ b/tests/MC/Mips/mips-coprocessor-encodings.s.yaml @@ -7,7 +7,7 @@ test_cases: expected: insns: - - asm_text: "dmtc0 $t4, $s0, 2" + asm_text: "dmtc0 $t4, $16, 2" - input: bytes: [ 0x40, 0xac, 0x80, 0x00 ] @@ -16,7 +16,7 @@ test_cases: expected: insns: - - asm_text: "dmtc0 $t4, $s0, 0" + asm_text: "dmtc0 $t4, $16, 0" - input: bytes: [ 0x40, 0x8c, 0x80, 0x02 ] @@ -25,7 +25,7 @@ test_cases: expected: insns: - - asm_text: "mtc0 $t4, $s0, 2" + asm_text: "mtc0 $t4, $16, 2" - input: bytes: [ 0x40, 0x8c, 0x80, 0x00 ] @@ -34,7 +34,7 @@ test_cases: expected: insns: - - asm_text: "mtc0 $t4, $s0, 0" + asm_text: "mtc0 $t4, $16, 0" - input: bytes: [ 0x40, 0x2c, 0x80, 0x02 ] @@ -43,7 +43,7 @@ test_cases: expected: insns: - - asm_text: "dmfc0 $t4, $s0, 2" + asm_text: "dmfc0 $t4, $16, 2" - input: bytes: [ 0x40, 0x2c, 0x80, 0x00 ] @@ -52,7 +52,7 @@ test_cases: expected: insns: - - asm_text: "dmfc0 $t4, $s0, 0" + asm_text: "dmfc0 $t4, $16, 0" - input: bytes: [ 0x40, 0x0c, 0x80, 0x02 ] @@ -61,7 +61,7 @@ test_cases: expected: insns: - - asm_text: "mfc0 $t4, $s0, 2" + asm_text: "mfc0 $t4, $16, 2" - input: bytes: [ 0x40, 0x0c, 0x80, 0x00 ] @@ -70,7 +70,7 @@ test_cases: expected: insns: - - asm_text: "mfc0 $t4, $s0, 0" + asm_text: "mfc0 $t4, $16, 0" - input: bytes: [ 0x48, 0xac, 0x80, 0x02 ] @@ -79,7 +79,7 @@ test_cases: expected: insns: - - asm_text: "dmtc2 $t4, $s0, 2" + asm_text: "dmtc2 $t4, $16, 2" - input: bytes: [ 0x48, 0xac, 0x80, 0x00 ] @@ -88,7 +88,7 @@ test_cases: expected: insns: - - asm_text: "dmtc2 $t4, $s0, 0" + asm_text: "dmtc2 $t4, $16, 0" - input: bytes: [ 0x48, 0x8c, 0x80, 0x02 ] @@ -97,7 +97,7 @@ test_cases: expected: insns: - - asm_text: "mtc2 $t4, $s0, 2" + asm_text: "mtc2 $t4, $16, 2" - input: bytes: [ 0x48, 0x8c, 0x80, 0x00 ] @@ -106,7 +106,7 @@ test_cases: expected: insns: - - asm_text: "mtc2 $t4, $s0, 0" + asm_text: "mtc2 $t4, $16, 0" - input: bytes: [ 0x48, 0x2c, 0x80, 0x02 ] @@ -115,7 +115,7 @@ test_cases: expected: insns: - - asm_text: "dmfc2 $t4, $s0, 2" + asm_text: "dmfc2 $t4, $16, 2" - input: bytes: [ 0x48, 0x2c, 0x80, 0x00 ] @@ -124,7 +124,7 @@ test_cases: expected: insns: - - asm_text: "dmfc2 $t4, $s0, 0" + asm_text: "dmfc2 $t4, $16, 0" - input: bytes: [ 0x48, 0x0c, 0x80, 0x02 ] @@ -133,7 +133,7 @@ test_cases: expected: insns: - - asm_text: "mfc2 $t4, $s0, 2" + asm_text: "mfc2 $t4, $16, 2" - input: bytes: [ 0x48, 0x0c, 0x80, 0x00 ] @@ -142,4 +142,4 @@ test_cases: expected: insns: - - asm_text: "mfc2 $t4, $s0, 0" + asm_text: "mfc2 $t4, $16, 0" diff --git a/tests/MC/Mips/mips-fpu-instructions.s.yaml b/tests/MC/Mips/mips-fpu-instructions.s.yaml index 0ff331ea6..d17192562 100644 --- a/tests/MC/Mips/mips-fpu-instructions.s.yaml +++ b/tests/MC/Mips/mips-fpu-instructions.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x05, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x85, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x00, 0x62, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x40, 0x32, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x0f, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x8f, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x0e, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x8e, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -75,7 +75,7 @@ test_cases: input: bytes: [ 0x02, 0x62, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -84,7 +84,7 @@ test_cases: input: bytes: [ 0x42, 0x32, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -93,7 +93,7 @@ test_cases: input: bytes: [ 0x07, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0x87, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0x0c, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x8c, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0x04, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0x84, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0x01, 0x62, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0x41, 0x32, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0x0d, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0x8d, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0x32, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0x32, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0x30, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0x30, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0x3e, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0x3c, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0x3d, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -282,7 +282,7 @@ test_cases: input: bytes: [ 0x3b, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -291,7 +291,7 @@ test_cases: input: bytes: [ 0x39, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -300,7 +300,7 @@ test_cases: input: bytes: [ 0x39, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -309,7 +309,7 @@ test_cases: input: bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -318,7 +318,7 @@ test_cases: input: bytes: [ 0x3f, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -327,7 +327,7 @@ test_cases: input: bytes: [ 0x36, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -336,7 +336,7 @@ test_cases: input: bytes: [ 0x36, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -345,7 +345,7 @@ test_cases: input: bytes: [ 0x34, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -354,7 +354,7 @@ test_cases: input: bytes: [ 0x34, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -363,7 +363,7 @@ test_cases: input: bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -372,7 +372,7 @@ test_cases: input: bytes: [ 0x3a, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -381,7 +381,7 @@ test_cases: input: bytes: [ 0x38, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -390,7 +390,7 @@ test_cases: input: bytes: [ 0x38, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -399,7 +399,7 @@ test_cases: input: bytes: [ 0x33, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -408,7 +408,7 @@ test_cases: input: bytes: [ 0x33, 0xe0, 0x12, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -417,7 +417,7 @@ test_cases: input: bytes: [ 0x37, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -426,7 +426,7 @@ test_cases: input: bytes: [ 0x37, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -435,7 +435,7 @@ test_cases: input: bytes: [ 0x35, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -444,7 +444,7 @@ test_cases: input: bytes: [ 0x35, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -453,7 +453,7 @@ test_cases: input: bytes: [ 0x31, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -462,7 +462,7 @@ test_cases: input: bytes: [ 0x31, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -471,7 +471,7 @@ test_cases: input: bytes: [ 0xa1, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -480,7 +480,7 @@ test_cases: input: bytes: [ 0x21, 0x73, 0x80, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -489,7 +489,7 @@ test_cases: input: bytes: [ 0x20, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -498,7 +498,7 @@ test_cases: input: bytes: [ 0xa0, 0x39, 0x80, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -507,7 +507,7 @@ test_cases: input: bytes: [ 0x24, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -516,7 +516,7 @@ test_cases: input: bytes: [ 0xa4, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -525,7 +525,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0x46, 0x44 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -534,7 +534,7 @@ test_cases: input: bytes: [ 0x00, 0xf8, 0xca, 0x44 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -543,7 +543,7 @@ test_cases: input: bytes: [ 0x00, 0x38, 0x06, 0x44 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -552,7 +552,7 @@ test_cases: input: bytes: [ 0x10, 0x28, 0x00, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -561,7 +561,7 @@ test_cases: input: bytes: [ 0x12, 0x28, 0x00, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -570,7 +570,7 @@ test_cases: input: bytes: [ 0x86, 0x41, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -579,7 +579,7 @@ test_cases: input: bytes: [ 0x86, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -588,7 +588,7 @@ test_cases: input: bytes: [ 0x00, 0x38, 0x86, 0x44 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -597,7 +597,7 @@ test_cases: input: bytes: [ 0x11, 0x00, 0xe0, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -606,7 +606,7 @@ test_cases: input: bytes: [ 0x13, 0x00, 0xe0, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -615,7 +615,7 @@ test_cases: input: bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -624,79 +624,79 @@ test_cases: input: bytes: [ 0x00, 0x38, 0x06, 0x40 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mfc0 $a2, $a3, 0" + asm_text: "mfc0 $a2, $7, 0" - input: bytes: [ 0x00, 0x40, 0x89, 0x40 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mtc0 $t1, $t0, 0" + asm_text: "mtc0 $t1, $8, 0" - input: bytes: [ 0x00, 0x38, 0x05, 0x48 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mfc2 $a1, $a3, 0" + asm_text: "mfc2 $a1, $7, 0" - input: bytes: [ 0x00, 0x20, 0x89, 0x48 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mtc2 $t1, $a0, 0" + asm_text: "mtc2 $t1, $4, 0" - input: bytes: [ 0x02, 0x38, 0x06, 0x40 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mfc0 $a2, $a3, 2" + asm_text: "mfc0 $a2, $7, 2" - input: bytes: [ 0x03, 0x40, 0x89, 0x40 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mtc0 $t1, $t0, 3" + asm_text: "mtc0 $t1, $8, 3" - input: bytes: [ 0x04, 0x38, 0x05, 0x48 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mfc2 $a1, $a3, 4" + asm_text: "mfc2 $a1, $7, 4" - input: bytes: [ 0x05, 0x20, 0x89, 0x48 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mtc2 $t1, $a0, 5" + asm_text: "mtc2 $t1, $4, 5" - input: bytes: [ 0x01, 0x10, 0x20, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -705,7 +705,7 @@ test_cases: input: bytes: [ 0x01, 0x10, 0x21, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -714,7 +714,7 @@ test_cases: input: bytes: [ 0x01, 0x20, 0xb1, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -723,7 +723,7 @@ test_cases: input: bytes: [ 0x11, 0x31, 0x28, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -732,7 +732,7 @@ test_cases: input: bytes: [ 0x11, 0x31, 0x14, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -741,7 +741,7 @@ test_cases: input: bytes: [ 0x05, 0x00, 0xa6, 0x4c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -750,7 +750,7 @@ test_cases: input: bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -759,7 +759,7 @@ test_cases: input: bytes: [ 0x00, 0x05, 0xcc, 0x4d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -768,7 +768,7 @@ test_cases: input: bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -777,7 +777,7 @@ test_cases: input: bytes: [ 0x00, 0x20, 0x71, 0x44 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -786,7 +786,7 @@ test_cases: input: bytes: [ 0x00, 0x30, 0xf1, 0x44 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -795,7 +795,7 @@ test_cases: input: bytes: [ 0x10, 0x00, 0xa4, 0xeb ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -804,7 +804,7 @@ test_cases: input: bytes: [ 0x10, 0x00, 0xa4, 0xfb ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -813,7 +813,7 @@ test_cases: input: bytes: [ 0x0c, 0x00, 0xeb, 0xcb ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -822,7 +822,7 @@ test_cases: input: bytes: [ 0x0c, 0x00, 0xeb, 0xdb ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - diff --git a/tests/MC/Mips/mips-memory-instructions.s.yaml b/tests/MC/Mips/mips-memory-instructions.s.yaml index ab3997e12..d78335b66 100644 --- a/tests/MC/Mips/mips-memory-instructions.s.yaml +++ b/tests/MC/Mips/mips-memory-instructions.s.yaml @@ -43,7 +43,7 @@ test_cases: expected: insns: - - asm_text: "sw $a3, ($a1)" + asm_text: "sw $a3, 0($a1)" - input: bytes: [ 0x10, 0x00, 0xa2, 0xe4 ] @@ -133,7 +133,7 @@ test_cases: expected: insns: - - asm_text: "lw $a3, ($a3)" + asm_text: "lw $a3, 0($a3)" - input: bytes: [ 0x10, 0x00, 0xa2, 0x8f ] diff --git a/tests/MC/Mips/mips64-alu-instructions.s.yaml b/tests/MC/Mips/mips64-alu-instructions.s.yaml index 258f56830..2ff180dae 100644 --- a/tests/MC/Mips/mips64-alu-instructions.s.yaml +++ b/tests/MC/Mips/mips64-alu-instructions.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x24, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x30 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x30 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x21, 0x30, 0xe6, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x20, 0x30, 0xe6, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x84, 0x61, 0x33, 0x7d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x27, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x25, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -75,7 +75,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xa4, 0x34 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -84,7 +84,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x34 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -93,7 +93,7 @@ test_cases: input: bytes: [ 0xc2, 0x49, 0x26, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0x46, 0x48, 0xe6, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0xc0, 0x21, 0x03, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x04, 0x10, 0xa3, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0x2a, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0x67, 0x00, 0x63, 0x28 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0x67, 0x00, 0x63, 0x28 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0x67, 0x00, 0x63, 0x2c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0x2b, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0xc3, 0x21, 0x03, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0x07, 0x10, 0xa3, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0xc2, 0x21, 0x03, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0x06, 0x10, 0xa3, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0x26, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x38 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x38 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0xa0, 0x30, 0x07, 0x7c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0x27, 0x38, 0x00, 0x01 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0x2c, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x60 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0x67, 0xc5, 0xc9, 0x64 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -282,7 +282,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x60 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -291,7 +291,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0x29, 0x61 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -300,7 +300,7 @@ test_cases: input: bytes: [ 0x67, 0xc5, 0xc9, 0x64 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -309,7 +309,7 @@ test_cases: input: bytes: [ 0x67, 0xc5, 0x29, 0x65 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -318,7 +318,7 @@ test_cases: input: bytes: [ 0x2d, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -327,7 +327,7 @@ test_cases: input: bytes: [ 0x3a, 0x4d, 0x26, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -336,7 +336,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -345,7 +345,7 @@ test_cases: input: bytes: [ 0x01, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -354,7 +354,7 @@ test_cases: input: bytes: [ 0x04, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -363,7 +363,7 @@ test_cases: input: bytes: [ 0x05, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -372,7 +372,7 @@ test_cases: input: bytes: [ 0x18, 0x00, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -381,7 +381,7 @@ test_cases: input: bytes: [ 0x19, 0x00, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -390,7 +390,7 @@ test_cases: input: bytes: [ 0x2f, 0x20, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -399,7 +399,7 @@ test_cases: input: bytes: [ 0x2d, 0x38, 0x00, 0x01 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - diff --git a/tests/MC/Mips/test_2r.txt.yaml b/tests/MC/Mips/test_2r.txt.yaml new file mode 100644 index 000000000..de3aa2bc1 --- /dev/null +++ b/tests/MC/Mips/test_2r.txt.yaml @@ -0,0 +1,150 @@ +test_cases: + - + input: + bytes: [ 0x7b, 0x00, 0x4f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fill.b $w30, $9" + + - + input: + bytes: [ 0x7b, 0x01, 0xbf, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fill.h $w31, $23" + + - + input: + bytes: [ 0x7b, 0x02, 0xc4, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fill.w $w16, $24" + + - + input: + bytes: [ 0x7b, 0x08, 0x05, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nloc.b $w21, $w0" + + - + input: + bytes: [ 0x7b, 0x09, 0xfc, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nloc.h $w18, $w31" + + - + input: + bytes: [ 0x7b, 0x0a, 0xb8, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nloc.w $w2, $w23" + + - + input: + bytes: [ 0x7b, 0x0b, 0x51, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nloc.d $w4, $w10" + + - + input: + bytes: [ 0x7b, 0x0c, 0x17, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nlzc.b $w31, $w2" + + - + input: + bytes: [ 0x7b, 0x0d, 0xb6, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nlzc.h $w27, $w22" + + - + input: + bytes: [ 0x7b, 0x0e, 0xea, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nlzc.w $w10, $w29" + + - + input: + bytes: [ 0x7b, 0x0f, 0x4e, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nlzc.d $w25, $w9" + + - + input: + bytes: [ 0x7b, 0x04, 0x95, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pcnt.b $w20, $w18" + + - + input: + bytes: [ 0x7b, 0x05, 0x40, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pcnt.h $w0, $w8" + + - + input: + bytes: [ 0x7b, 0x06, 0x4d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pcnt.w $w23, $w9" + + - + input: + bytes: [ 0x7b, 0x07, 0xc5, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pcnt.d $w21, $w24" diff --git a/tests/MC/Mips/test_2r_msa64.txt.yaml b/tests/MC/Mips/test_2r_msa64.txt.yaml new file mode 100644 index 000000000..b9deacfcd --- /dev/null +++ b/tests/MC/Mips/test_2r_msa64.txt.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x7b, 0x03, 0x4e, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "fill.d $w27, $9" diff --git a/tests/MC/Mips/test_2rf.txt.yaml b/tests/MC/Mips/test_2rf.txt.yaml new file mode 100644 index 000000000..ae7476fc1 --- /dev/null +++ b/tests/MC/Mips/test_2rf.txt.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x7b, 0x20, 0x66, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fclass.w $w26, $w12" + + - + input: + bytes: [ 0x7b, 0x21, 0x8e, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fclass.d $w24, $w17" + + - + input: + bytes: [ 0x7b, 0x30, 0x02, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexupl.w $w8, $w0" + + - + input: + bytes: [ 0x7b, 0x31, 0xec, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexupl.d $w17, $w29" + + - + input: + bytes: [ 0x7b, 0x32, 0x23, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexupr.w $w13, $w4" + + - + input: + bytes: [ 0x7b, 0x33, 0x11, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexupr.d $w5, $w2" + + - + input: + bytes: [ 0x7b, 0x3c, 0xed, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffint_s.w $w20, $w29" + + - + input: + bytes: [ 0x7b, 0x3d, 0x7b, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffint_s.d $w12, $w15" + + - + input: + bytes: [ 0x7b, 0x3e, 0xd9, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffint_u.w $w7, $w27" + + - + input: + bytes: [ 0x7b, 0x3f, 0x84, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffint_u.d $w19, $w16" + + - + input: + bytes: [ 0x7b, 0x34, 0x6f, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffql.w $w31, $w13" + + - + input: + bytes: [ 0x7b, 0x35, 0x6b, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffql.d $w12, $w13" + + - + input: + bytes: [ 0x7b, 0x36, 0xf6, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffqr.w $w27, $w30" + + - + input: + bytes: [ 0x7b, 0x37, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffqr.d $w30, $w15" + + - + input: + bytes: [ 0x7b, 0x2e, 0xfe, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "flog2.w $w25, $w31" + + - + input: + bytes: [ 0x7b, 0x2f, 0x54, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "flog2.d $w18, $w10" + + - + input: + bytes: [ 0x7b, 0x2c, 0x79, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "frint.w $w7, $w15" + + - + input: + bytes: [ 0x7b, 0x2d, 0xb5, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "frint.d $w21, $w22" + + - + input: + bytes: [ 0x7b, 0x2a, 0x04, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "frcp.w $w19, $w0" + + - + input: + bytes: [ 0x7b, 0x2b, 0x71, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "frcp.d $w4, $w14" + + - + input: + bytes: [ 0x7b, 0x28, 0x8b, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "frsqrt.w $w12, $w17" + + - + input: + bytes: [ 0x7b, 0x29, 0x5d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "frsqrt.d $w23, $w11" + + - + input: + bytes: [ 0x7b, 0x26, 0x58, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsqrt.w $w0, $w11" + + - + input: + bytes: [ 0x7b, 0x27, 0x63, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsqrt.d $w15, $w12" + + - + input: + bytes: [ 0x7b, 0x38, 0x2f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftint_s.w $w30, $w5" + + - + input: + bytes: [ 0x7b, 0x39, 0xb9, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftint_s.d $w5, $w23" + + - + input: + bytes: [ 0x7b, 0x3a, 0x75, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftint_u.w $w20, $w14" + + - + input: + bytes: [ 0x7b, 0x3b, 0xad, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftint_u.d $w23, $w21" + + - + input: + bytes: [ 0x7b, 0x22, 0x8f, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftrunc_s.w $w29, $w17" + + - + input: + bytes: [ 0x7b, 0x23, 0xdb, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftrunc_s.d $w12, $w27" + + - + input: + bytes: [ 0x7b, 0x24, 0x7c, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftrunc_u.w $w17, $w15" + + - + input: + bytes: [ 0x7b, 0x25, 0xd9, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftrunc_u.d $w5, $w27" diff --git a/tests/MC/Mips/test_3r.txt.yaml b/tests/MC/Mips/test_3r.txt.yaml new file mode 100644 index 000000000..22bee8069 --- /dev/null +++ b/tests/MC/Mips/test_3r.txt.yaml @@ -0,0 +1,2420 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x04, 0x4e, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add_a.b $w26, $w9, $w4" + + - + input: + bytes: [ 0x78, 0x3f, 0xdd, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add_a.h $w23, $w27, $w31" + + - + input: + bytes: [ 0x78, 0x56, 0x32, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add_a.w $w11, $w6, $w22" + + - + input: + bytes: [ 0x78, 0x60, 0x51, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add_a.d $w6, $w10, $w0" + + - + input: + bytes: [ 0x78, 0x93, 0xc4, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_a.b $w19, $w24, $w19" + + - + input: + bytes: [ 0x78, 0xa4, 0x36, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_a.h $w25, $w6, $w4" + + - + input: + bytes: [ 0x78, 0xdb, 0x8e, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_a.w $w25, $w17, $w27" + + - + input: + bytes: [ 0x78, 0xfa, 0x93, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_a.d $w15, $w18, $w26" + + - + input: + bytes: [ 0x79, 0x13, 0x5f, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_s.b $w29, $w11, $w19" + + - + input: + bytes: [ 0x79, 0x3a, 0xb9, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_s.h $w5, $w23, $w26" + + - + input: + bytes: [ 0x79, 0x4d, 0x74, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_s.w $w16, $w14, $w13" + + - + input: + bytes: [ 0x79, 0x7c, 0x70, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_s.d $w2, $w14, $w28" + + - + input: + bytes: [ 0x79, 0x8e, 0x88, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_u.b $w3, $w17, $w14" + + - + input: + bytes: [ 0x79, 0xa4, 0xf2, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_u.h $w10, $w30, $w4" + + - + input: + bytes: [ 0x79, 0xd4, 0x93, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_u.w $w15, $w18, $w20" + + - + input: + bytes: [ 0x79, 0xe9, 0x57, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_u.d $w30, $w10, $w9" + + - + input: + bytes: [ 0x78, 0x15, 0xa6, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addv.b $w24, $w20, $w21" + + - + input: + bytes: [ 0x78, 0x3b, 0x69, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addv.h $w4, $w13, $w27" + + - + input: + bytes: [ 0x78, 0x4e, 0x5c, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addv.w $w19, $w11, $w14" + + - + input: + bytes: [ 0x78, 0x7f, 0xa8, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addv.d $w2, $w21, $w31" + + - + input: + bytes: [ 0x7a, 0x03, 0x85, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_s.b $w23, $w16, $w3" + + - + input: + bytes: [ 0x7a, 0x39, 0x8d, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_s.h $w22, $w17, $w25" + + - + input: + bytes: [ 0x7a, 0x49, 0x0e, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_s.w $w24, $w1, $w9" + + - + input: + bytes: [ 0x7a, 0x6c, 0x63, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_s.d $w13, $w12, $w12" + + - + input: + bytes: [ 0x7a, 0x8b, 0xea, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_u.b $w10, $w29, $w11" + + - + input: + bytes: [ 0x7a, 0xaf, 0x4c, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_u.h $w18, $w9, $w15" + + - + input: + bytes: [ 0x7a, 0xdf, 0x9a, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_u.w $w10, $w19, $w31" + + - + input: + bytes: [ 0x7a, 0xe0, 0x54, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_u.d $w17, $w10, $w0" + + - + input: + bytes: [ 0x7a, 0x01, 0x28, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_s.b $w2, $w5, $w1" + + - + input: + bytes: [ 0x7a, 0x29, 0x9c, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_s.h $w16, $w19, $w9" + + - + input: + bytes: [ 0x7a, 0x45, 0xfc, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_s.w $w17, $w31, $w5" + + - + input: + bytes: [ 0x7a, 0x6a, 0xce, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_s.d $w27, $w25, $w10" + + - + input: + bytes: [ 0x7a, 0x89, 0x9c, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_u.b $w16, $w19, $w9" + + - + input: + bytes: [ 0x7a, 0xab, 0xe7, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_u.h $w28, $w28, $w11" + + - + input: + bytes: [ 0x7a, 0xcb, 0x62, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_u.w $w11, $w12, $w11" + + - + input: + bytes: [ 0x7a, 0xfc, 0x9f, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_u.d $w30, $w19, $w28" + + - + input: + bytes: [ 0x7b, 0x02, 0x86, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_s.b $w26, $w16, $w2" + + - + input: + bytes: [ 0x7b, 0x3b, 0xdf, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_s.h $w31, $w27, $w27" + + - + input: + bytes: [ 0x7b, 0x59, 0x97, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_s.w $w28, $w18, $w25" + + - + input: + bytes: [ 0x7b, 0x7b, 0xaf, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_s.d $w29, $w21, $w27" + + - + input: + bytes: [ 0x7b, 0x83, 0xd7, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_u.b $w29, $w26, $w3" + + - + input: + bytes: [ 0x7b, 0xa9, 0x94, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_u.h $w18, $w18, $w9" + + - + input: + bytes: [ 0x7b, 0xdd, 0xcc, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_u.w $w17, $w25, $w29" + + - + input: + bytes: [ 0x7b, 0xf3, 0xb5, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_u.d $w22, $w22, $w19" + + - + input: + bytes: [ 0x79, 0x9d, 0x78, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclr.b $w2, $w15, $w29" + + - + input: + bytes: [ 0x79, 0xbc, 0xac, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclr.h $w16, $w21, $w28" + + - + input: + bytes: [ 0x79, 0xc9, 0x14, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclr.w $w19, $w2, $w9" + + - + input: + bytes: [ 0x79, 0xe4, 0xfe, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclr.d $w27, $w31, $w4" + + - + input: + bytes: [ 0x7b, 0x18, 0x81, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsl.b $w5, $w16, $w24" + + - + input: + bytes: [ 0x7b, 0x2a, 0x2f, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsl.h $w30, $w5, $w10" + + - + input: + bytes: [ 0x7b, 0x4d, 0x7b, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsl.w $w14, $w15, $w13" + + - + input: + bytes: [ 0x7b, 0x6c, 0xa5, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsl.d $w23, $w20, $w12" + + - + input: + bytes: [ 0x7b, 0x82, 0x5d, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsr.b $w22, $w11, $w2" + + - + input: + bytes: [ 0x7b, 0xa6, 0xd0, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsr.h $w0, $w26, $w6" + + - + input: + bytes: [ 0x7b, 0xdc, 0x1e, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsr.w $w26, $w3, $w28" + + - + input: + bytes: [ 0x7b, 0xf5, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsr.d $w0, $w0, $w21" + + - + input: + bytes: [ 0x7a, 0x98, 0x58, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bneg.b $w0, $w11, $w24" + + - + input: + bytes: [ 0x7a, 0xa4, 0x87, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bneg.h $w28, $w16, $w4" + + - + input: + bytes: [ 0x7a, 0xd3, 0xd0, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bneg.w $w3, $w26, $w19" + + - + input: + bytes: [ 0x7a, 0xef, 0xeb, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bneg.d $w13, $w29, $w15" + + - + input: + bytes: [ 0x7a, 0x1f, 0x2f, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bset.b $w31, $w5, $w31" + + - + input: + bytes: [ 0x7a, 0x26, 0x63, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bset.h $w14, $w12, $w6" + + - + input: + bytes: [ 0x7a, 0x4c, 0x4f, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bset.w $w31, $w9, $w12" + + - + input: + bytes: [ 0x7a, 0x65, 0xb1, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bset.d $w5, $w22, $w5" + + - + input: + bytes: [ 0x78, 0x12, 0xff, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceq.b $w31, $w31, $w18" + + - + input: + bytes: [ 0x78, 0x29, 0xda, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceq.h $w10, $w27, $w9" + + - + input: + bytes: [ 0x78, 0x4e, 0x2a, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceq.w $w9, $w5, $w14" + + - + input: + bytes: [ 0x78, 0x60, 0x89, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceq.d $w5, $w17, $w0" + + - + input: + bytes: [ 0x7a, 0x09, 0x25, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_s.b $w23, $w4, $w9" + + - + input: + bytes: [ 0x7a, 0x33, 0xdd, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_s.h $w22, $w27, $w19" + + - + input: + bytes: [ 0x7a, 0x4a, 0xd7, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_s.w $w30, $w26, $w10" + + - + input: + bytes: [ 0x7a, 0x6a, 0x2c, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_s.d $w18, $w5, $w10" + + - + input: + bytes: [ 0x7a, 0x80, 0xc8, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_u.b $w1, $w25, $w0" + + - + input: + bytes: [ 0x7a, 0xbd, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_u.h $w7, $w0, $w29" + + - + input: + bytes: [ 0x7a, 0xc1, 0x96, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_u.w $w25, $w18, $w1" + + - + input: + bytes: [ 0x7a, 0xfe, 0x01, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_u.d $w6, $w0, $w30" + + - + input: + bytes: [ 0x79, 0x15, 0x16, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_s.b $w25, $w2, $w21" + + - + input: + bytes: [ 0x79, 0x29, 0x98, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_s.h $w2, $w19, $w9" + + - + input: + bytes: [ 0x79, 0x50, 0x45, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_s.w $w23, $w8, $w16" + + - + input: + bytes: [ 0x79, 0x6c, 0xf1, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_s.d $w7, $w30, $w12" + + - + input: + bytes: [ 0x79, 0x8d, 0xf8, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_u.b $w2, $w31, $w13" + + - + input: + bytes: [ 0x79, 0xb7, 0xfc, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_u.h $w16, $w31, $w23" + + - + input: + bytes: [ 0x79, 0xc9, 0xc0, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_u.w $w3, $w24, $w9" + + - + input: + bytes: [ 0x79, 0xe1, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_u.d $w7, $w0, $w1" + + - + input: + bytes: [ 0x7a, 0x12, 0x1f, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_s.b $w29, $w3, $w18" + + - + input: + bytes: [ 0x7a, 0x2d, 0x84, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_s.h $w17, $w16, $w13" + + - + input: + bytes: [ 0x7a, 0x5e, 0xc9, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_s.w $w4, $w25, $w30" + + - + input: + bytes: [ 0x7a, 0x74, 0x4f, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_s.d $w31, $w9, $w20" + + - + input: + bytes: [ 0x7a, 0x8a, 0xe9, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_u.b $w6, $w29, $w10" + + - + input: + bytes: [ 0x7a, 0xae, 0xae, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_u.h $w24, $w21, $w14" + + - + input: + bytes: [ 0x7a, 0xd9, 0x77, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_u.w $w29, $w14, $w25" + + - + input: + bytes: [ 0x7a, 0xf5, 0x0f, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_u.d $w31, $w1, $w21" + + - + input: + bytes: [ 0x78, 0x39, 0xb5, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dotp_s.h $w23, $w22, $w25" + + - + input: + bytes: [ 0x78, 0x45, 0x75, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dotp_s.w $w20, $w14, $w5" + + - + input: + bytes: [ 0x78, 0x76, 0x14, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dotp_s.d $w17, $w2, $w22" + + - + input: + bytes: [ 0x78, 0xa6, 0x13, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dotp_u.h $w13, $w2, $w6" + + - + input: + bytes: [ 0x78, 0xd5, 0xb3, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dotp_u.w $w15, $w22, $w21" + + - + input: + bytes: [ 0x78, 0xfa, 0x81, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dotp_u.d $w4, $w16, $w26" + + - + input: + bytes: [ 0x79, 0x36, 0xe0, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpadd_s.h $w1, $w28, $w22" + + - + input: + bytes: [ 0x79, 0x4c, 0x0a, 0x93 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpadd_s.w $w10, $w1, $w12" + + - + input: + bytes: [ 0x79, 0x7b, 0xa8, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpadd_s.d $w3, $w21, $w27" + + - + input: + bytes: [ 0x79, 0xb4, 0x2c, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpadd_u.h $w17, $w5, $w20" + + - + input: + bytes: [ 0x79, 0xd0, 0x46, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpadd_u.w $w24, $w8, $w16" + + - + input: + bytes: [ 0x79, 0xf0, 0xeb, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpadd_u.d $w15, $w29, $w16" + + - + input: + bytes: [ 0x7a, 0x2c, 0x59, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpsub_s.h $w4, $w11, $w12" + + - + input: + bytes: [ 0x7a, 0x46, 0x39, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpsub_s.w $w4, $w7, $w6" + + - + input: + bytes: [ 0x7a, 0x7c, 0x67, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpsub_s.d $w31, $w12, $w28" + + - + input: + bytes: [ 0x7a, 0xb1, 0xc9, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpsub_u.h $w4, $w25, $w17" + + - + input: + bytes: [ 0x7a, 0xd0, 0xcc, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpsub_u.w $w19, $w25, $w16" + + - + input: + bytes: [ 0x7a, 0xfa, 0x51, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpsub_u.d $w7, $w10, $w26" + + - + input: + bytes: [ 0x7a, 0x22, 0xc7, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hadd_s.h $w28, $w24, $w2" + + - + input: + bytes: [ 0x7a, 0x4b, 0x8e, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hadd_s.w $w24, $w17, $w11" + + - + input: + bytes: [ 0x7a, 0x74, 0x7c, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hadd_s.d $w17, $w15, $w20" + + - + input: + bytes: [ 0x7a, 0xb1, 0xeb, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hadd_u.h $w12, $w29, $w17" + + - + input: + bytes: [ 0x7a, 0xc6, 0x2a, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hadd_u.w $w9, $w5, $w6" + + - + input: + bytes: [ 0x7a, 0xe6, 0xa0, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hadd_u.d $w1, $w20, $w6" + + - + input: + bytes: [ 0x7b, 0x3d, 0x74, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hsub_s.h $w16, $w14, $w29" + + - + input: + bytes: [ 0x7b, 0x4b, 0x6a, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hsub_s.w $w9, $w13, $w11" + + - + input: + bytes: [ 0x7b, 0x6e, 0x97, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hsub_s.d $w30, $w18, $w14" + + - + input: + bytes: [ 0x7b, 0xae, 0x61, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hsub_u.h $w7, $w12, $w14" + + - + input: + bytes: [ 0x7b, 0xc5, 0x2d, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hsub_u.w $w21, $w5, $w5" + + - + input: + bytes: [ 0x7b, 0xff, 0x62, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hsub_u.d $w11, $w12, $w31" + + - + input: + bytes: [ 0x7b, 0x1e, 0x84, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvev.b $w18, $w16, $w30" + + - + input: + bytes: [ 0x7b, 0x2d, 0x03, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvev.h $w14, $w0, $w13" + + - + input: + bytes: [ 0x7b, 0x56, 0xcb, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvev.w $w12, $w25, $w22" + + - + input: + bytes: [ 0x7b, 0x63, 0xdf, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvev.d $w30, $w27, $w3" + + - + input: + bytes: [ 0x7a, 0x15, 0x1f, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvl.b $w29, $w3, $w21" + + - + input: + bytes: [ 0x7a, 0x31, 0x56, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvl.h $w27, $w10, $w17" + + - + input: + bytes: [ 0x7a, 0x40, 0x09, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvl.w $w6, $w1, $w0" + + - + input: + bytes: [ 0x7a, 0x78, 0x80, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvl.d $w3, $w16, $w24" + + - + input: + bytes: [ 0x7b, 0x94, 0x2a, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvod.b $w11, $w5, $w20" + + - + input: + bytes: [ 0x7b, 0xbf, 0x6c, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvod.h $w18, $w13, $w31" + + - + input: + bytes: [ 0x7b, 0xd8, 0x87, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvod.w $w29, $w16, $w24" + + - + input: + bytes: [ 0x7b, 0xfd, 0x65, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvod.d $w22, $w12, $w29" + + - + input: + bytes: [ 0x7a, 0x86, 0xf1, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvr.b $w4, $w30, $w6" + + - + input: + bytes: [ 0x7a, 0xbd, 0x9f, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvr.h $w28, $w19, $w29" + + - + input: + bytes: [ 0x7a, 0xd5, 0xa4, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvr.w $w18, $w20, $w21" + + - + input: + bytes: [ 0x7a, 0xec, 0xf5, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvr.d $w23, $w30, $w12" + + - + input: + bytes: [ 0x78, 0x9d, 0xfc, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddv.b $w17, $w31, $w29" + + - + input: + bytes: [ 0x78, 0xa9, 0xc1, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddv.h $w7, $w24, $w9" + + - + input: + bytes: [ 0x78, 0xd4, 0xb5, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddv.w $w22, $w22, $w20" + + - + input: + bytes: [ 0x78, 0xf4, 0xd7, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddv.d $w30, $w26, $w20" + + - + input: + bytes: [ 0x7b, 0x17, 0x5d, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_a.b $w23, $w11, $w23" + + - + input: + bytes: [ 0x7b, 0x3e, 0x2d, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_a.h $w20, $w5, $w30" + + - + input: + bytes: [ 0x7b, 0x5e, 0x91, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_a.w $w7, $w18, $w30" + + - + input: + bytes: [ 0x7b, 0x7f, 0x42, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_a.d $w8, $w8, $w31" + + - + input: + bytes: [ 0x79, 0x13, 0x0a, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_s.b $w10, $w1, $w19" + + - + input: + bytes: [ 0x79, 0x31, 0xeb, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_s.h $w15, $w29, $w17" + + - + input: + bytes: [ 0x79, 0x4e, 0xeb, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_s.w $w15, $w29, $w14" + + - + input: + bytes: [ 0x79, 0x63, 0xc6, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_s.d $w25, $w24, $w3" + + - + input: + bytes: [ 0x79, 0x85, 0xc3, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_u.b $w12, $w24, $w5" + + - + input: + bytes: [ 0x79, 0xa7, 0x31, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_u.h $w5, $w6, $w7" + + - + input: + bytes: [ 0x79, 0xc7, 0x24, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_u.w $w16, $w4, $w7" + + - + input: + bytes: [ 0x79, 0xf8, 0x66, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_u.d $w26, $w12, $w24" + + - + input: + bytes: [ 0x7b, 0x81, 0xd1, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_a.b $w4, $w26, $w1" + + - + input: + bytes: [ 0x7b, 0xbf, 0x6b, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_a.h $w12, $w13, $w31" + + - + input: + bytes: [ 0x7b, 0xc0, 0xa7, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_a.w $w28, $w20, $w0" + + - + input: + bytes: [ 0x7b, 0xf3, 0xa3, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_a.d $w12, $w20, $w19" + + - + input: + bytes: [ 0x7a, 0x0e, 0x1c, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_s.b $w19, $w3, $w14" + + - + input: + bytes: [ 0x7a, 0x28, 0xae, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_s.h $w27, $w21, $w8" + + - + input: + bytes: [ 0x7a, 0x5e, 0x70, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_s.w $w0, $w14, $w30" + + - + input: + bytes: [ 0x7a, 0x75, 0x41, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_s.d $w6, $w8, $w21" + + - + input: + bytes: [ 0x7a, 0x88, 0xd5, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_u.b $w22, $w26, $w8" + + - + input: + bytes: [ 0x7a, 0xac, 0xd9, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_u.h $w7, $w27, $w12" + + - + input: + bytes: [ 0x7a, 0xce, 0xa2, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_u.w $w8, $w20, $w14" + + - + input: + bytes: [ 0x7a, 0xef, 0x76, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_u.d $w26, $w14, $w15" + + - + input: + bytes: [ 0x7b, 0x1a, 0x0c, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_s.b $w18, $w1, $w26" + + - + input: + bytes: [ 0x7b, 0x3c, 0xf7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_s.h $w31, $w30, $w28" + + - + input: + bytes: [ 0x7b, 0x4d, 0x30, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_s.w $w2, $w6, $w13" + + - + input: + bytes: [ 0x7b, 0x76, 0xdd, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_s.d $w21, $w27, $w22" + + - + input: + bytes: [ 0x7b, 0x8d, 0x3c, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_u.b $w16, $w7, $w13" + + - + input: + bytes: [ 0x7b, 0xa7, 0x46, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_u.h $w24, $w8, $w7" + + - + input: + bytes: [ 0x7b, 0xd1, 0x17, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_u.w $w30, $w2, $w17" + + - + input: + bytes: [ 0x7b, 0xf9, 0x17, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_u.d $w31, $w2, $w25" + + - + input: + bytes: [ 0x79, 0x0c, 0x2b, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubv.b $w14, $w5, $w12" + + - + input: + bytes: [ 0x79, 0x3e, 0x39, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubv.h $w6, $w7, $w30" + + - + input: + bytes: [ 0x79, 0x55, 0x13, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubv.w $w13, $w2, $w21" + + - + input: + bytes: [ 0x79, 0x7b, 0x74, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubv.d $w16, $w14, $w27" + + - + input: + bytes: [ 0x78, 0x0d, 0x1d, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mulv.b $w20, $w3, $w13" + + - + input: + bytes: [ 0x78, 0x2e, 0xd6, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mulv.h $w27, $w26, $w14" + + - + input: + bytes: [ 0x78, 0x43, 0xea, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mulv.w $w10, $w29, $w3" + + - + input: + bytes: [ 0x78, 0x7d, 0x99, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mulv.d $w7, $w19, $w29" + + - + input: + bytes: [ 0x79, 0x07, 0xd9, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckev.b $w5, $w27, $w7" + + - + input: + bytes: [ 0x79, 0x3b, 0x20, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckev.h $w1, $w4, $w27" + + - + input: + bytes: [ 0x79, 0x40, 0xa7, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckev.w $w30, $w20, $w0" + + - + input: + bytes: [ 0x79, 0x6f, 0x09, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckev.d $w6, $w1, $w15" + + - + input: + bytes: [ 0x79, 0x9e, 0xe4, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckod.b $w18, $w28, $w30" + + - + input: + bytes: [ 0x79, 0xa8, 0x2e, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckod.h $w26, $w5, $w8" + + - + input: + bytes: [ 0x79, 0xc2, 0x22, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckod.w $w9, $w4, $w2" + + - + input: + bytes: [ 0x79, 0xf4, 0xb7, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckod.d $w30, $w22, $w20" + + - + input: + bytes: [ 0x78, 0x0c, 0xb9, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sld.b $w5, $w23[$12]" + + - + input: + bytes: [ 0x78, 0x23, 0xb8, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sld.h $w1, $w23[$3]" + + - + input: + bytes: [ 0x78, 0x49, 0x45, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sld.w $w20, $w8[$9]" + + - + input: + bytes: [ 0x78, 0x7e, 0xb9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sld.d $w7, $w23[$fp]" + + - + input: + bytes: [ 0x78, 0x11, 0x00, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll.b $w3, $w0, $w17" + + - + input: + bytes: [ 0x78, 0x23, 0xdc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll.h $w17, $w27, $w3" + + - + input: + bytes: [ 0x78, 0x46, 0x3c, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll.w $w16, $w7, $w6" + + - + input: + bytes: [ 0x78, 0x7a, 0x02, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll.d $w9, $w0, $w26" + + - + input: + bytes: [ 0x78, 0x81, 0x0f, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splat.b $w28, $w1[$1]" + + - + input: + bytes: [ 0x78, 0xab, 0x58, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splat.h $w2, $w11[$11]" + + - + input: + bytes: [ 0x78, 0xcb, 0x05, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splat.w $w22, $w0[$11]" + + - + input: + bytes: [ 0x78, 0xe2, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splat.d $w0, $w0[$2]" + + - + input: + bytes: [ 0x78, 0x91, 0x27, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra.b $w28, $w4, $w17" + + - + input: + bytes: [ 0x78, 0xa3, 0x4b, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra.h $w13, $w9, $w3" + + - + input: + bytes: [ 0x78, 0xd3, 0xae, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra.w $w27, $w21, $w19" + + - + input: + bytes: [ 0x78, 0xf7, 0x47, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra.d $w30, $w8, $w23" + + - + input: + bytes: [ 0x78, 0x92, 0x94, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srar.b $w19, $w18, $w18" + + - + input: + bytes: [ 0x78, 0xa8, 0xb9, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srar.h $w7, $w23, $w8" + + - + input: + bytes: [ 0x78, 0xc2, 0x60, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srar.w $w1, $w12, $w2" + + - + input: + bytes: [ 0x78, 0xee, 0x3d, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srar.d $w21, $w7, $w14" + + - + input: + bytes: [ 0x79, 0x13, 0x1b, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl.b $w12, $w3, $w19" + + - + input: + bytes: [ 0x79, 0x34, 0xfd, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl.h $w23, $w31, $w20" + + - + input: + bytes: [ 0x79, 0x4b, 0xdc, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl.w $w18, $w27, $w11" + + - + input: + bytes: [ 0x79, 0x7a, 0x60, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl.d $w3, $w12, $w26" + + - + input: + bytes: [ 0x79, 0x0b, 0xab, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlr.b $w15, $w21, $w11" + + - + input: + bytes: [ 0x79, 0x33, 0x6d, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlr.h $w21, $w13, $w19" + + - + input: + bytes: [ 0x79, 0x43, 0xf1, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlr.w $w6, $w30, $w3" + + - + input: + bytes: [ 0x79, 0x6e, 0x10, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlr.d $w1, $w2, $w14" + + - + input: + bytes: [ 0x78, 0x01, 0x7e, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_s.b $w25, $w15, $w1" + + - + input: + bytes: [ 0x78, 0x36, 0xcf, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_s.h $w28, $w25, $w22" + + - + input: + bytes: [ 0x78, 0x55, 0x62, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_s.w $w10, $w12, $w21" + + - + input: + bytes: [ 0x78, 0x72, 0xa1, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_s.d $w4, $w20, $w18" + + - + input: + bytes: [ 0x78, 0x99, 0x35, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_u.b $w21, $w6, $w25" + + - + input: + bytes: [ 0x78, 0xa7, 0x50, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_u.h $w3, $w10, $w7" + + - + input: + bytes: [ 0x78, 0xca, 0x7a, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_u.w $w9, $w15, $w10" + + - + input: + bytes: [ 0x78, 0xea, 0x99, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_u.d $w7, $w19, $w10" + + - + input: + bytes: [ 0x79, 0x0c, 0x39, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsus_u.b $w6, $w7, $w12" + + - + input: + bytes: [ 0x79, 0x33, 0xe9, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsus_u.h $w6, $w29, $w19" + + - + input: + bytes: [ 0x79, 0x47, 0x79, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsus_u.w $w7, $w15, $w7" + + - + input: + bytes: [ 0x79, 0x6f, 0x1a, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsus_u.d $w9, $w3, $w15" + + - + input: + bytes: [ 0x79, 0x9f, 0x1d, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsuu_s.b $w22, $w3, $w31" + + - + input: + bytes: [ 0x79, 0xb6, 0xbc, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsuu_s.h $w19, $w23, $w22" + + - + input: + bytes: [ 0x79, 0xcd, 0x52, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsuu_s.w $w9, $w10, $w13" + + - + input: + bytes: [ 0x79, 0xe0, 0x31, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsuu_s.d $w5, $w6, $w0" + + - + input: + bytes: [ 0x78, 0x93, 0x69, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subv.b $w6, $w13, $w19" + + - + input: + bytes: [ 0x78, 0xac, 0xc9, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subv.h $w4, $w25, $w12" + + - + input: + bytes: [ 0x78, 0xcb, 0xde, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subv.w $w27, $w27, $w11" + + - + input: + bytes: [ 0x78, 0xea, 0xc2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subv.d $w9, $w24, $w10" + + - + input: + bytes: [ 0x78, 0x05, 0x80, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "vshf.b $w3, $w16, $w5" + + - + input: + bytes: [ 0x78, 0x28, 0x9d, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "vshf.h $w20, $w19, $w8" + + - + input: + bytes: [ 0x78, 0x59, 0xf4, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "vshf.w $w16, $w30, $w25" + + - + input: + bytes: [ 0x78, 0x6f, 0x5c, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "vshf.d $w19, $w11, $w15" diff --git a/tests/MC/Mips/test_3rf.txt.yaml b/tests/MC/Mips/test_3rf.txt.yaml new file mode 100644 index 000000000..feae05433 --- /dev/null +++ b/tests/MC/Mips/test_3rf.txt.yaml @@ -0,0 +1,820 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x1c, 0x9f, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fadd.w $w28, $w19, $w28" + + - + input: + bytes: [ 0x78, 0x3d, 0x13, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fadd.d $w13, $w2, $w29" + + - + input: + bytes: [ 0x78, 0x19, 0x5b, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcaf.w $w14, $w11, $w25" + + - + input: + bytes: [ 0x78, 0x33, 0x08, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcaf.d $w1, $w1, $w19" + + - + input: + bytes: [ 0x78, 0x90, 0xb8, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fceq.w $w1, $w23, $w16" + + - + input: + bytes: [ 0x78, 0xb0, 0x40, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fceq.d $w0, $w8, $w16" + + - + input: + bytes: [ 0x79, 0x98, 0x4c, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcle.w $w16, $w9, $w24" + + - + input: + bytes: [ 0x79, 0xa1, 0x76, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcle.d $w27, $w14, $w1" + + - + input: + bytes: [ 0x79, 0x08, 0x47, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fclt.w $w28, $w8, $w8" + + - + input: + bytes: [ 0x79, 0x2b, 0xcf, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fclt.d $w30, $w25, $w11" + + - + input: + bytes: [ 0x78, 0xd7, 0x90, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcne.w $w2, $w18, $w23" + + - + input: + bytes: [ 0x78, 0xef, 0xa3, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcne.d $w14, $w20, $w15" + + - + input: + bytes: [ 0x78, 0x59, 0x92, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcor.w $w10, $w18, $w25" + + - + input: + bytes: [ 0x78, 0x6b, 0xcc, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcor.d $w17, $w25, $w11" + + - + input: + bytes: [ 0x78, 0xd5, 0x13, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcueq.w $w14, $w2, $w21" + + - + input: + bytes: [ 0x78, 0xe7, 0x1f, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcueq.d $w29, $w3, $w7" + + - + input: + bytes: [ 0x79, 0xc3, 0x2c, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcule.w $w17, $w5, $w3" + + - + input: + bytes: [ 0x79, 0xfe, 0x0f, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcule.d $w31, $w1, $w30" + + - + input: + bytes: [ 0x79, 0x49, 0xc9, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcult.w $w6, $w25, $w9" + + - + input: + bytes: [ 0x79, 0x71, 0x46, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcult.d $w27, $w8, $w17" + + - + input: + bytes: [ 0x78, 0x48, 0xa1, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcun.w $w4, $w20, $w8" + + - + input: + bytes: [ 0x78, 0x63, 0x5f, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcun.d $w29, $w11, $w3" + + - + input: + bytes: [ 0x78, 0x93, 0x93, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcune.w $w13, $w18, $w19" + + - + input: + bytes: [ 0x78, 0xb5, 0xd4, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcune.d $w16, $w26, $w21" + + - + input: + bytes: [ 0x78, 0xc2, 0xc3, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fdiv.w $w13, $w24, $w2" + + - + input: + bytes: [ 0x78, 0xf9, 0x24, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fdiv.d $w19, $w4, $w25" + + - + input: + bytes: [ 0x7a, 0x10, 0x02, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexdo.h $w8, $w0, $w16" + + - + input: + bytes: [ 0x7a, 0x3b, 0x68, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexdo.w $w0, $w13, $w27" + + - + input: + bytes: [ 0x79, 0xc3, 0x04, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexp2.w $w17, $w0, $w3" + + - + input: + bytes: [ 0x79, 0xea, 0x05, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexp2.d $w22, $w0, $w10" + + - + input: + bytes: [ 0x79, 0x17, 0x37, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmadd.w $w29, $w6, $w23" + + - + input: + bytes: [ 0x79, 0x35, 0xe2, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmadd.d $w11, $w28, $w21" + + - + input: + bytes: [ 0x7b, 0x8d, 0xb8, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmax.w $w0, $w23, $w13" + + - + input: + bytes: [ 0x7b, 0xa8, 0x96, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmax.d $w26, $w18, $w8" + + - + input: + bytes: [ 0x7b, 0xca, 0x82, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmax_a.w $w10, $w16, $w10" + + - + input: + bytes: [ 0x7b, 0xf6, 0x4f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmax_a.d $w30, $w9, $w22" + + - + input: + bytes: [ 0x7b, 0x1e, 0x0e, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmin.w $w24, $w1, $w30" + + - + input: + bytes: [ 0x7b, 0x2a, 0xde, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmin.d $w27, $w27, $w10" + + - + input: + bytes: [ 0x7b, 0x54, 0xea, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmin_a.w $w10, $w29, $w20" + + - + input: + bytes: [ 0x7b, 0x78, 0xf3, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmin_a.d $w13, $w30, $w24" + + - + input: + bytes: [ 0x79, 0x40, 0xcc, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmsub.w $w17, $w25, $w0" + + - + input: + bytes: [ 0x79, 0x70, 0x92, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmsub.d $w8, $w18, $w16" + + - + input: + bytes: [ 0x78, 0x8f, 0x78, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmul.w $w3, $w15, $w15" + + - + input: + bytes: [ 0x78, 0xaa, 0xf2, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmul.d $w9, $w30, $w10" + + - + input: + bytes: [ 0x7a, 0x0a, 0x2e, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsaf.w $w25, $w5, $w10" + + - + input: + bytes: [ 0x7a, 0x3d, 0x1e, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsaf.d $w25, $w3, $w29" + + - + input: + bytes: [ 0x7a, 0x8d, 0x8a, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fseq.w $w11, $w17, $w13" + + - + input: + bytes: [ 0x7a, 0xbf, 0x07, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fseq.d $w29, $w0, $w31" + + - + input: + bytes: [ 0x7b, 0x9f, 0xff, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsle.w $w30, $w31, $w31" + + - + input: + bytes: [ 0x7b, 0xb8, 0xbc, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsle.d $w18, $w23, $w24" + + - + input: + bytes: [ 0x7b, 0x06, 0x2b, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fslt.w $w12, $w5, $w6" + + - + input: + bytes: [ 0x7b, 0x35, 0xd4, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fslt.d $w16, $w26, $w21" + + - + input: + bytes: [ 0x7a, 0xcc, 0x0f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsne.w $w30, $w1, $w12" + + - + input: + bytes: [ 0x7a, 0xf7, 0x6b, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsne.d $w14, $w13, $w23" + + - + input: + bytes: [ 0x7a, 0x5b, 0x6e, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsor.w $w27, $w13, $w27" + + - + input: + bytes: [ 0x7a, 0x6b, 0xc3, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsor.d $w12, $w24, $w11" + + - + input: + bytes: [ 0x78, 0x41, 0xd7, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsub.w $w31, $w26, $w1" + + - + input: + bytes: [ 0x78, 0x7b, 0x8c, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsub.d $w19, $w17, $w27" + + - + input: + bytes: [ 0x7a, 0xd9, 0xc4, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsueq.w $w16, $w24, $w25" + + - + input: + bytes: [ 0x7a, 0xee, 0x74, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsueq.d $w18, $w14, $w14" + + - + input: + bytes: [ 0x7b, 0xcd, 0xf5, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsule.w $w23, $w30, $w13" + + - + input: + bytes: [ 0x7b, 0xfa, 0x58, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsule.d $w2, $w11, $w26" + + - + input: + bytes: [ 0x7b, 0x56, 0xd2, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsult.w $w11, $w26, $w22" + + - + input: + bytes: [ 0x7b, 0x7e, 0xb9, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsult.d $w6, $w23, $w30" + + - + input: + bytes: [ 0x7a, 0x5c, 0x90, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsun.w $w3, $w18, $w28" + + - + input: + bytes: [ 0x7a, 0x73, 0x5c, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsun.d $w18, $w11, $w19" + + - + input: + bytes: [ 0x7a, 0x82, 0xfc, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsune.w $w16, $w31, $w2" + + - + input: + bytes: [ 0x7a, 0xb1, 0xd0, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsune.d $w3, $w26, $w17" + + - + input: + bytes: [ 0x7a, 0x98, 0x24, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftq.h $w16, $w4, $w24" + + - + input: + bytes: [ 0x7a, 0xb9, 0x29, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftq.w $w5, $w5, $w25" + + - + input: + bytes: [ 0x79, 0x4a, 0xa4, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd_q.h $w16, $w20, $w10" + + - + input: + bytes: [ 0x79, 0x69, 0x17, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd_q.w $w28, $w2, $w9" + + - + input: + bytes: [ 0x7b, 0x49, 0x92, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddr_q.h $w8, $w18, $w9" + + - + input: + bytes: [ 0x7b, 0x70, 0x67, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddr_q.w $w29, $w12, $w16" + + - + input: + bytes: [ 0x79, 0x8a, 0xd6, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub_q.h $w24, $w26, $w10" + + - + input: + bytes: [ 0x79, 0xbc, 0xf3, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub_q.w $w13, $w30, $w28" + + - + input: + bytes: [ 0x7b, 0x8b, 0xab, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubr_q.h $w12, $w21, $w11" + + - + input: + bytes: [ 0x7b, 0xb4, 0x70, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubr_q.w $w1, $w14, $w20" + + - + input: + bytes: [ 0x79, 0x1e, 0x81, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul_q.h $w6, $w16, $w30" + + - + input: + bytes: [ 0x79, 0x24, 0x0c, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul_q.w $w16, $w1, $w4" + + - + input: + bytes: [ 0x7b, 0x13, 0xa1, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mulr_q.h $w6, $w20, $w19" + + - + input: + bytes: [ 0x7b, 0x34, 0x0e, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mulr_q.w $w27, $w1, $w20" diff --git a/tests/MC/Mips/test_bit.txt.yaml b/tests/MC/Mips/test_bit.txt.yaml new file mode 100644 index 000000000..f6da52255 --- /dev/null +++ b/tests/MC/Mips/test_bit.txt.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x79, 0xf2, 0xf5, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclri.b $w21, $w30, 2" + + - + input: + bytes: [ 0x79, 0xe0, 0xae, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclri.h $w24, $w21, 0" + + - + input: + bytes: [ 0x79, 0xc3, 0xf5, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclri.w $w23, $w30, 3" + + - + input: + bytes: [ 0x79, 0x80, 0x5a, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclri.d $w9, $w11, 0" + + - + input: + bytes: [ 0x7b, 0x71, 0x66, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsli.b $w25, $w12, 1" + + - + input: + bytes: [ 0x7b, 0x60, 0xb5, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsli.h $w21, $w22, 0" + + - + input: + bytes: [ 0x7b, 0x40, 0x25, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsli.w $w22, $w4, 0" + + - + input: + bytes: [ 0x7b, 0x06, 0x11, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsli.d $w6, $w2, 6" + + - + input: + bytes: [ 0x7b, 0xf0, 0x9b, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsri.b $w15, $w19, 0" + + - + input: + bytes: [ 0x7b, 0xe1, 0xf2, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsri.h $w8, $w30, 1" + + - + input: + bytes: [ 0x7b, 0xc5, 0x98, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsri.w $w2, $w19, 5" + + - + input: + bytes: [ 0x7b, 0x81, 0xa4, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsri.d $w18, $w20, 1" + + - + input: + bytes: [ 0x7a, 0xf0, 0x9e, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnegi.b $w24, $w19, 0" + + - + input: + bytes: [ 0x7a, 0xe3, 0x5f, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnegi.h $w28, $w11, 3" + + - + input: + bytes: [ 0x7a, 0xc5, 0xd8, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnegi.w $w1, $w27, 5" + + - + input: + bytes: [ 0x7a, 0x81, 0xa9, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnegi.d $w4, $w21, 1" + + - + input: + bytes: [ 0x7a, 0x70, 0x44, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bseti.b $w18, $w8, 0" + + - + input: + bytes: [ 0x7a, 0x62, 0x76, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bseti.h $w24, $w14, 2" + + - + input: + bytes: [ 0x7a, 0x44, 0x92, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bseti.w $w9, $w18, 4" + + - + input: + bytes: [ 0x7a, 0x01, 0x79, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bseti.d $w7, $w15, 1" + + - + input: + bytes: [ 0x78, 0x72, 0xff, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_s.b $w31, $w31, 2" + + - + input: + bytes: [ 0x78, 0x60, 0x9c, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_s.h $w19, $w19, 0" + + - + input: + bytes: [ 0x78, 0x40, 0xec, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_s.w $w19, $w29, 0" + + - + input: + bytes: [ 0x78, 0x00, 0xb2, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_s.d $w11, $w22, 0" + + - + input: + bytes: [ 0x78, 0xf3, 0x68, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_u.b $w1, $w13, 3" + + - + input: + bytes: [ 0x78, 0xe4, 0xc7, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_u.h $w30, $w24, 4" + + - + input: + bytes: [ 0x78, 0xc0, 0x6f, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_u.w $w31, $w13, 0" + + - + input: + bytes: [ 0x78, 0x85, 0x87, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_u.d $w29, $w16, 5" + + - + input: + bytes: [ 0x78, 0x71, 0x55, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slli.b $w23, $w10, 1" + + - + input: + bytes: [ 0x78, 0x61, 0x92, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slli.h $w9, $w18, 1" + + - + input: + bytes: [ 0x78, 0x44, 0xea, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slli.w $w11, $w29, 4" + + - + input: + bytes: [ 0x78, 0x01, 0xa6, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slli.d $w25, $w20, 1" + + - + input: + bytes: [ 0x78, 0xf1, 0xee, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srai.b $w24, $w29, 1" + + - + input: + bytes: [ 0x78, 0xe0, 0x30, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srai.h $w1, $w6, 0" + + - + input: + bytes: [ 0x78, 0xc1, 0xd1, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srai.w $w7, $w26, 1" + + - + input: + bytes: [ 0x78, 0x83, 0xcd, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srai.d $w20, $w25, 3" + + - + input: + bytes: [ 0x79, 0x70, 0xc9, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srari.b $w5, $w25, 0" + + - + input: + bytes: [ 0x79, 0x64, 0x31, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srari.h $w7, $w6, 4" + + - + input: + bytes: [ 0x79, 0x45, 0x5c, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srari.w $w17, $w11, 5" + + - + input: + bytes: [ 0x79, 0x05, 0xcd, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srari.d $w21, $w25, 5" + + - + input: + bytes: [ 0x79, 0x72, 0x00, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srli.b $w2, $w0, 2" + + - + input: + bytes: [ 0x79, 0x62, 0xff, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srli.h $w31, $w31, 2" + + - + input: + bytes: [ 0x79, 0x44, 0x49, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srli.w $w5, $w9, 4" + + - + input: + bytes: [ 0x79, 0x05, 0xd6, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srli.d $w27, $w26, 5" + + - + input: + bytes: [ 0x79, 0xf0, 0x1c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlri.b $w18, $w3, 0" + + - + input: + bytes: [ 0x79, 0xe3, 0x10, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlri.h $w1, $w2, 3" + + - + input: + bytes: [ 0x79, 0xc2, 0xb2, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlri.w $w11, $w22, 2" + + - + input: + bytes: [ 0x79, 0x86, 0x56, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlri.d $w24, $w10, 6" diff --git a/tests/MC/Mips/test_ctrlregs.txt.yaml b/tests/MC/Mips/test_ctrlregs.txt.yaml new file mode 100644 index 000000000..475435b5d --- /dev/null +++ b/tests/MC/Mips/test_ctrlregs.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x7e, 0x00, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $1, $0" + + - + input: + bytes: [ 0x78, 0x7e, 0x08, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $2, $1" + + - + input: + bytes: [ 0x78, 0x7e, 0x10, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $3, $2" + + - + input: + bytes: [ 0x78, 0x7e, 0x19, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $4, $3" + + - + input: + bytes: [ 0x78, 0x7e, 0x21, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $5, $4" + + - + input: + bytes: [ 0x78, 0x7e, 0x29, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $6, $5" + + - + input: + bytes: [ 0x78, 0x7e, 0x31, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $7, $6" + + - + input: + bytes: [ 0x78, 0x7e, 0x3a, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $8, $7" + + - + input: + bytes: [ 0x78, 0x3e, 0x08, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $0, $1" + + - + input: + bytes: [ 0x78, 0x3e, 0x10, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $1, $2" + + - + input: + bytes: [ 0x78, 0x3e, 0x18, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $2, $3" + + - + input: + bytes: [ 0x78, 0x3e, 0x20, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $3, $4" + + - + input: + bytes: [ 0x78, 0x3e, 0x29, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $4, $5" + + - + input: + bytes: [ 0x78, 0x3e, 0x31, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $5, $6" + + - + input: + bytes: [ 0x78, 0x3e, 0x39, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $6, $7" + + - + input: + bytes: [ 0x78, 0x3e, 0x41, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $7, $8" diff --git a/tests/MC/Mips/test_dlsa.txt.yaml b/tests/MC/Mips/test_dlsa.txt.yaml new file mode 100644 index 000000000..251190837 --- /dev/null +++ b/tests/MC/Mips/test_dlsa.txt.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dlsa $8, $9, $10, 1" + + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dlsa $8, $9, $10, 2" + + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dlsa $8, $9, $10, 3" + + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dlsa $8, $9, $10, 4" diff --git a/tests/MC/Mips/test_elm.s.yaml b/tests/MC/Mips/test_elm.s.yaml index 9ad7c3d49..82b7a8f96 100644 --- a/tests/MC/Mips/test_elm.s.yaml +++ b/tests/MC/Mips/test_elm.s.yaml @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x78, 0xf2, 0x6f, 0x99 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS64", "CS_MODE_BIG_ENDIAN" ] expected: insns: - diff --git a/tests/MC/Mips/test_elm.txt.yaml b/tests/MC/Mips/test_elm.txt.yaml new file mode 100644 index 000000000..9eadb6a5c --- /dev/null +++ b/tests/MC/Mips/test_elm.txt.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x82, 0x43, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "copy_s.b $13, $w8[2]" + + - + input: + bytes: [ 0x78, 0xa0, 0xc8, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "copy_s.h $1, $w25[0]" + + - + input: + bytes: [ 0x78, 0xb1, 0x2d, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "copy_s.w $22, $w5[1]" + + - + input: + bytes: [ 0x78, 0xc4, 0xa5, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "copy_u.b $22, $w20[4]" + + - + input: + bytes: [ 0x78, 0xe0, 0x25, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "copy_u.h $20, $w4[0]" + + - + input: + bytes: [ 0x78, 0x04, 0xe8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sldi.b $w0, $w29[4]" + + - + input: + bytes: [ 0x78, 0x20, 0x8a, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sldi.h $w8, $w17[0]" + + - + input: + bytes: [ 0x78, 0x32, 0xdd, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sldi.w $w20, $w27[2]" + + - + input: + bytes: [ 0x78, 0x38, 0x61, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sldi.d $w4, $w12[0]" + + - + input: + bytes: [ 0x78, 0x42, 0x1e, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splati.b $w25, $w3[2]" + + - + input: + bytes: [ 0x78, 0x61, 0xe6, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splati.h $w24, $w28[1]" + + - + input: + bytes: [ 0x78, 0x70, 0x93, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splati.w $w13, $w18[0]" + + - + input: + bytes: [ 0x78, 0x78, 0x0f, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splati.d $w28, $w1[0]" + + - + input: + bytes: [ 0x78, 0xbe, 0xc5, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move.v $w23, $w24" diff --git a/tests/MC/Mips/test_elm_insert.txt.yaml b/tests/MC/Mips/test_elm_insert.txt.yaml new file mode 100644 index 000000000..92c185016 --- /dev/null +++ b/tests/MC/Mips/test_elm_insert.txt.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x79, 0x03, 0xed, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insert.b $w23[3], $sp" + + - + input: + bytes: [ 0x79, 0x22, 0x2d, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insert.h $w20[2], $5" + + - + input: + bytes: [ 0x79, 0x32, 0x7a, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insert.w $w8[2], $15" diff --git a/tests/MC/Mips/test_elm_insert_msa64.txt.yaml b/tests/MC/Mips/test_elm_insert_msa64.txt.yaml new file mode 100644 index 000000000..adcc11ac6 --- /dev/null +++ b/tests/MC/Mips/test_elm_insert_msa64.txt.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x79, 0x39, 0xe8, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "insert.d $w1[1], $sp" diff --git a/tests/MC/Mips/test_elm_insve.txt.yaml b/tests/MC/Mips/test_elm_insve.txt.yaml new file mode 100644 index 000000000..4fbec6986 --- /dev/null +++ b/tests/MC/Mips/test_elm_insve.txt.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x79, 0x43, 0x4e, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insve.b $w25[3], $w9[0]" + + - + input: + bytes: [ 0x79, 0x62, 0x16, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insve.h $w24[2], $w2[0]" + + - + input: + bytes: [ 0x79, 0x72, 0x68, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insve.w $w0[2], $w13[0]" + + - + input: + bytes: [ 0x79, 0x78, 0x90, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insve.d $w3[0], $w18[0]" diff --git a/tests/MC/Mips/test_elm_msa64.txt.yaml b/tests/MC/Mips/test_elm_msa64.txt.yaml new file mode 100644 index 000000000..818390f5b --- /dev/null +++ b/tests/MC/Mips/test_elm_msa64.txt.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x78, 0xb8, 0xfc, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "copy_s.d $19, $w31[0]" diff --git a/tests/MC/Mips/test_i10.txt.yaml b/tests/MC/Mips/test_i10.txt.yaml new file mode 100644 index 000000000..93223de21 --- /dev/null +++ b/tests/MC/Mips/test_i10.txt.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x7b, 0x06, 0x32, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldi.b $w8, 198" + + - + input: + bytes: [ 0x7b, 0x29, 0xcd, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldi.h $w20, 313" + + - + input: + bytes: [ 0x7b, 0x4f, 0x66, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldi.w $w24, 492" + + - + input: + bytes: [ 0x7b, 0x7a, 0x66, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldi.d $w27, 844" diff --git a/tests/MC/Mips/test_i5.txt.yaml b/tests/MC/Mips/test_i5.txt.yaml new file mode 100644 index 000000000..07e72f063 --- /dev/null +++ b/tests/MC/Mips/test_i5.txt.yaml @@ -0,0 +1,440 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x1e, 0xf8, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addvi.b $w3, $w31, 30" + + - + input: + bytes: [ 0x78, 0x3a, 0x6e, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addvi.h $w24, $w13, 26" + + - + input: + bytes: [ 0x78, 0x5a, 0xa6, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addvi.w $w26, $w20, 26" + + - + input: + bytes: [ 0x78, 0x75, 0x0c, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addvi.d $w16, $w1, 21" + + - + input: + bytes: [ 0x78, 0x18, 0xae, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceqi.b $w24, $w21, 24" + + - + input: + bytes: [ 0x78, 0x22, 0x7f, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceqi.h $w31, $w15, 2" + + - + input: + bytes: [ 0x78, 0x5f, 0x0b, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceqi.w $w12, $w1, 31" + + - + input: + bytes: [ 0x78, 0x67, 0xb6, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceqi.d $w24, $w22, 7" + + - + input: + bytes: [ 0x7a, 0x01, 0x83, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_s.b $w12, $w16, 1" + + - + input: + bytes: [ 0x7a, 0x37, 0x50, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_s.h $w2, $w10, 23" + + - + input: + bytes: [ 0x7a, 0x56, 0x59, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_s.w $w4, $w11, 22" + + - + input: + bytes: [ 0x7a, 0x76, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_s.d $w0, $w29, 22" + + - + input: + bytes: [ 0x7a, 0x83, 0x8d, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_u.b $w21, $w17, 3" + + - + input: + bytes: [ 0x7a, 0xb1, 0x3f, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_u.h $w29, $w7, 17" + + - + input: + bytes: [ 0x7a, 0xc2, 0x08, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_u.w $w1, $w1, 2" + + - + input: + bytes: [ 0x7a, 0xfd, 0xde, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_u.d $w27, $w27, 29" + + - + input: + bytes: [ 0x79, 0x19, 0x6c, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_s.b $w19, $w13, 25" + + - + input: + bytes: [ 0x79, 0x34, 0x53, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_s.h $w15, $w10, 20" + + - + input: + bytes: [ 0x79, 0x4b, 0x63, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_s.w $w12, $w12, 11" + + - + input: + bytes: [ 0x79, 0x71, 0xa7, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_s.d $w29, $w20, 17" + + - + input: + bytes: [ 0x79, 0x9d, 0x4b, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_u.b $w14, $w9, 29" + + - + input: + bytes: [ 0x79, 0xb9, 0xce, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_u.h $w24, $w25, 25" + + - + input: + bytes: [ 0x79, 0xd6, 0x08, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_u.w $w1, $w1, 22" + + - + input: + bytes: [ 0x79, 0xe1, 0xcd, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_u.d $w21, $w25, 1" + + - + input: + bytes: [ 0x79, 0x01, 0xad, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_s.b $w22, $w21, 1" + + - + input: + bytes: [ 0x79, 0x38, 0x2f, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_s.h $w29, $w5, 24" + + - + input: + bytes: [ 0x79, 0x54, 0x50, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_s.w $w1, $w10, 20" + + - + input: + bytes: [ 0x79, 0x70, 0xeb, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_s.d $w13, $w29, 16" + + - + input: + bytes: [ 0x79, 0x8c, 0x05, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_u.b $w20, $w0, 12" + + - + input: + bytes: [ 0x79, 0xa3, 0x70, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_u.h $w1, $w14, 3" + + - + input: + bytes: [ 0x79, 0xcb, 0xb6, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_u.w $w27, $w22, 11" + + - + input: + bytes: [ 0x79, 0xe4, 0x36, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_u.d $w26, $w6, 4" + + - + input: + bytes: [ 0x7a, 0x01, 0x09, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_s.b $w4, $w1, 1" + + - + input: + bytes: [ 0x7a, 0x37, 0xde, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_s.h $w27, $w27, 23" + + - + input: + bytes: [ 0x7a, 0x49, 0x5f, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_s.w $w28, $w11, 9" + + - + input: + bytes: [ 0x7a, 0x6a, 0x52, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_s.d $w11, $w10, 10" + + - + input: + bytes: [ 0x7a, 0x9b, 0xbc, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_u.b $w18, $w23, 27" + + - + input: + bytes: [ 0x7a, 0xb2, 0xd1, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_u.h $w7, $w26, 18" + + - + input: + bytes: [ 0x7a, 0xda, 0x62, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_u.w $w11, $w12, 26" + + - + input: + bytes: [ 0x7a, 0xe2, 0x7a, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_u.d $w11, $w15, 2" + + - + input: + bytes: [ 0x78, 0x93, 0xa6, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subvi.b $w24, $w20, 19" + + - + input: + bytes: [ 0x78, 0xa4, 0x9a, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subvi.h $w11, $w19, 4" + + - + input: + bytes: [ 0x78, 0xcb, 0x53, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subvi.w $w12, $w10, 11" + + - + input: + bytes: [ 0x78, 0xe7, 0x84, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subvi.d $w19, $w16, 7" diff --git a/tests/MC/Mips/test_i8.txt.yaml b/tests/MC/Mips/test_i8.txt.yaml new file mode 100644 index 000000000..eacde3ccf --- /dev/null +++ b/tests/MC/Mips/test_i8.txt.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x30, 0xe8, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "andi.b $w2, $w29, 48" + + - + input: + bytes: [ 0x78, 0x7e, 0xb1, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bmnzi.b $w6, $w22, 126" + + - + input: + bytes: [ 0x79, 0x58, 0x0e, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bmzi.b $w27, $w1, 88" + + - + input: + bytes: [ 0x7a, 0xbd, 0x1f, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bseli.b $w29, $w3, 189" + + - + input: + bytes: [ 0x7a, 0x38, 0x88, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nori.b $w1, $w17, 56" + + - + input: + bytes: [ 0x79, 0x87, 0xa6, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori.b $w26, $w20, 135" + + - + input: + bytes: [ 0x78, 0x69, 0xf4, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "shf.b $w19, $w30, 105" + + - + input: + bytes: [ 0x79, 0x4c, 0x44, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "shf.h $w17, $w8, 76" + + - + input: + bytes: [ 0x7a, 0x5d, 0x1b, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "shf.w $w14, $w3, 93" + + - + input: + bytes: [ 0x7b, 0x14, 0x54, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xori.b $w16, $w10, 20" diff --git a/tests/MC/Mips/test_lsa.txt.yaml b/tests/MC/Mips/test_lsa.txt.yaml new file mode 100644 index 000000000..9164cc8fa --- /dev/null +++ b/tests/MC/Mips/test_lsa.txt.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lsa $8, $9, $10, 1" + + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lsa $8, $9, $10, 2" + + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lsa $8, $9, $10, 3" + + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lsa $8, $9, $10, 4" diff --git a/tests/MC/Mips/test_mi10.s.yaml b/tests/MC/Mips/test_mi10.s.yaml index 83aeb82f7..b2646a284 100644 --- a/tests/MC/Mips/test_mi10.s.yaml +++ b/tests/MC/Mips/test_mi10.s.yaml @@ -16,7 +16,7 @@ test_cases: expected: insns: - - asm_text: "ld.b $w1, ($v0)" + asm_text: "ld.b $w1, 0($v0)" - input: bytes: [ 0x79, 0xff, 0x18, 0xa0 ] @@ -52,7 +52,7 @@ test_cases: expected: insns: - - asm_text: "ld.h $w5, ($a2)" + asm_text: "ld.h $w5, 0($a2)" - input: bytes: [ 0x79, 0x00, 0x39, 0xa1 ] @@ -169,7 +169,7 @@ test_cases: expected: insns: - - asm_text: "ld.d $w18, ($s3)" + asm_text: "ld.d $w18, 0($s3)" - input: bytes: [ 0x78, 0x40, 0xa4, 0xe3 ] diff --git a/tests/MC/Mips/test_mi10.txt.yaml b/tests/MC/Mips/test_mi10.txt.yaml new file mode 100644 index 000000000..5cb59273d --- /dev/null +++ b/tests/MC/Mips/test_mi10.txt.yaml @@ -0,0 +1,230 @@ +test_cases: + - + input: + bytes: [ 0x7a, 0x00, 0x08, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.b $w0, -512($1)" + + - + input: + bytes: [ 0x78, 0x00, 0x10, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.b $w1, 0($2)" + + - + input: + bytes: [ 0x79, 0xff, 0x18, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.b $w2, 511($3)" + + - + input: + bytes: [ 0x7a, 0x00, 0x20, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.h $w3, -1024($4)" + + - + input: + bytes: [ 0x7b, 0x00, 0x29, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.h $w4, -512($5)" + + - + input: + bytes: [ 0x78, 0x00, 0x31, 0x61 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.h $w5, 0($6)" + + - + input: + bytes: [ 0x79, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.h $w6, 512($7)" + + - + input: + bytes: [ 0x79, 0xff, 0x41, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.h $w7, 1022($8)" + + - + input: + bytes: [ 0x7a, 0x00, 0x4a, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.w $w8, -2048($9)" + + - + input: + bytes: [ 0x7b, 0x00, 0x52, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.w $w9, -1024($10)" + + - + input: + bytes: [ 0x7b, 0x80, 0x5a, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.w $w10, -512($11)" + + - + input: + bytes: [ 0x78, 0x80, 0x62, 0xe2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.w $w11, 512($12)" + + - + input: + bytes: [ 0x79, 0x00, 0x6b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.w $w12, 1024($13)" + + - + input: + bytes: [ 0x79, 0xff, 0x73, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.w $w13, 2044($14)" + + - + input: + bytes: [ 0x7a, 0x00, 0x7b, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w14, -4096($15)" + + - + input: + bytes: [ 0x7b, 0x00, 0x83, 0xe3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w15, -2048($16)" + + - + input: + bytes: [ 0x7b, 0x80, 0x8c, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w16, -1024($17)" + + - + input: + bytes: [ 0x7b, 0xc0, 0x94, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w17, -512($18)" + + - + input: + bytes: [ 0x78, 0x00, 0x9c, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w18, 0($19)" + + - + input: + bytes: [ 0x78, 0x40, 0xa4, 0xe3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w19, 512($20)" + + - + input: + bytes: [ 0x78, 0x80, 0xad, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w20, 1024($21)" + + - + input: + bytes: [ 0x79, 0x00, 0xb5, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w21, 2048($22)" + + - + input: + bytes: [ 0x79, 0xff, 0xbd, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w22, 4088($23)" diff --git a/tests/MC/Mips/test_vec.txt.yaml b/tests/MC/Mips/test_vec.txt.yaml new file mode 100644 index 000000000..ec90f0378 --- /dev/null +++ b/tests/MC/Mips/test_vec.txt.yaml @@ -0,0 +1,70 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x1b, 0xa6, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "and.v $w25, $w20, $w27" + + - + input: + bytes: [ 0x78, 0x87, 0x34, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bmnz.v $w17, $w6, $w7" + + - + input: + bytes: [ 0x78, 0xa9, 0x88, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bmz.v $w3, $w17, $w9" + + - + input: + bytes: [ 0x78, 0xce, 0x02, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bsel.v $w8, $w0, $w14" + + - + input: + bytes: [ 0x78, 0x40, 0xf9, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nor.v $w7, $w31, $w0" + + - + input: + bytes: [ 0x78, 0x3e, 0xd6, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "or.v $w24, $w26, $w30" + + - + input: + bytes: [ 0x78, 0x6f, 0xd9, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xor.v $w7, $w27, $w15" diff --git a/tests/MC/Mips/valid-32-el.txt.yaml b/tests/MC/Mips/valid-32-el.txt.yaml new file mode 100644 index 000000000..121fa6166 --- /dev/null +++ b/tests/MC/Mips/valid-32-el.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x28, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 0" + + - + input: + bytes: [ 0x02, 0x28, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 2" + + - + input: + bytes: [ 0x00, 0x2a, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtgc0 $4, $5, 0" + + - + input: + bytes: [ 0x02, 0x22, 0x65, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtgc0 $5, $4, 2" + + - + input: + bytes: [ 0x00, 0x2c, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 0" + + - + input: + bytes: [ 0x04, 0x2c, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 4" + + - + input: + bytes: [ 0x00, 0x2e, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthgc0 $4, $5, 0" + + - + input: + bytes: [ 0x04, 0x2e, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthgc0 $4, $5, 4" + + - + input: + bytes: [ 0x28, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "hypcall" + + - + input: + bytes: [ 0x28, 0x50, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "hypcall 10" + + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbginv" + + - + input: + bytes: [ 0x0c, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbginvf" + + - + input: + bytes: [ 0x10, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgp" + + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgr" + + - + input: + bytes: [ 0x0a, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgwi" + + - + input: + bytes: [ 0x0e, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgwr" diff --git a/tests/MC/Mips/valid-32.txt.yaml b/tests/MC/Mips/valid-32.txt.yaml new file mode 100644 index 000000000..7517b67b8 --- /dev/null +++ b/tests/MC/Mips/valid-32.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x64, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 0" + + - + input: + bytes: [ 0x40, 0x64, 0x28, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 2" + + - + input: + bytes: [ 0x40, 0x64, 0x2a, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtgc0 $4, $5, 0" + + - + input: + bytes: [ 0x40, 0x65, 0x22, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtgc0 $5, $4, 2" + + - + input: + bytes: [ 0x40, 0x64, 0x2c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 0" + + - + input: + bytes: [ 0x40, 0x64, 0x2c, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 4" + + - + input: + bytes: [ 0x40, 0x64, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthgc0 $4, $5, 0" + + - + input: + bytes: [ 0x40, 0x64, 0x2e, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthgc0 $4, $5, 4" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "hypcall" + + - + input: + bytes: [ 0x42, 0x00, 0x50, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "hypcall 10" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbginv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbginvf" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgwr" diff --git a/tests/MC/Mips/valid-32r6-el.txt.yaml b/tests/MC/Mips/valid-32r6-el.txt.yaml new file mode 100644 index 000000000..4929528bb --- /dev/null +++ b/tests/MC/Mips/valid-32r6-el.txt.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x0f, 0x00, 0x41, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32b $1, $2, $1" + + - + input: + bytes: [ 0x4f, 0x00, 0xa4, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32h $4, $5, $4" + + - + input: + bytes: [ 0x8f, 0x00, 0x07, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32w $7, $8, $7" + + - + input: + bytes: [ 0x0f, 0x01, 0x41, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32cb $1, $2, $1" + + - + input: + bytes: [ 0x4f, 0x01, 0xa4, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32ch $4, $5, $4" + + - + input: + bytes: [ 0x8f, 0x01, 0x07, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32cw $7, $8, $7" diff --git a/tests/MC/Mips/valid-32r6.txt.yaml b/tests/MC/Mips/valid-32r6.txt.yaml new file mode 100644 index 000000000..873f569a8 --- /dev/null +++ b/tests/MC/Mips/valid-32r6.txt.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x7c, 0x41, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32b $1, $2, $1" + + - + input: + bytes: [ 0x7c, 0xa4, 0x00, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32h $4, $5, $4" + + - + input: + bytes: [ 0x7d, 0x07, 0x00, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32w $7, $8, $7" + + - + input: + bytes: [ 0x7c, 0x41, 0x01, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32cb $1, $2, $1" + + - + input: + bytes: [ 0x7c, 0xa4, 0x01, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32ch $4, $5, $4" + + - + input: + bytes: [ 0x7d, 0x07, 0x01, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32cw $7, $8, $7" diff --git a/tests/MC/Mips/valid-64-el.txt.yaml b/tests/MC/Mips/valid-64-el.txt.yaml new file mode 100644 index 000000000..07424ab66 --- /dev/null +++ b/tests/MC/Mips/valid-64-el.txt.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x29, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfgc0 $4, $5, 0" + + - + input: + bytes: [ 0x04, 0x29, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfgc0 $4, $5, 4" + + - + input: + bytes: [ 0x00, 0x23, 0x65, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtgc0 $5, $4, 0" + + - + input: + bytes: [ 0x04, 0x2b, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtgc0 $4, $5, 4" diff --git a/tests/MC/Mips/valid-64.txt.yaml b/tests/MC/Mips/valid-64.txt.yaml new file mode 100644 index 000000000..fc4e7a691 --- /dev/null +++ b/tests/MC/Mips/valid-64.txt.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x64, 0x29, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfgc0 $4, $5, 0" + + - + input: + bytes: [ 0x40, 0x64, 0x29, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfgc0 $4, $5, 4" + + - + input: + bytes: [ 0x40, 0x65, 0x23, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtgc0 $5, $4, 0" + + - + input: + bytes: [ 0x40, 0x64, 0x2b, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtgc0 $4, $5, 4" diff --git a/tests/MC/Mips/valid-64r6-el.txt.yaml b/tests/MC/Mips/valid-64r6-el.txt.yaml new file mode 100644 index 000000000..ec0e642ea --- /dev/null +++ b/tests/MC/Mips/valid-64r6-el.txt.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x0f, 0x00, 0x41, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32b $1, $2, $1" + + - + input: + bytes: [ 0x4f, 0x00, 0xa4, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32h $4, $5, $4" + + - + input: + bytes: [ 0x8f, 0x00, 0x07, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32w $7, $8, $7" + + - + input: + bytes: [ 0xcf, 0x00, 0x6a, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32d $10, $11, $10" + + - + input: + bytes: [ 0x0f, 0x01, 0x41, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32cb $1, $2, $1" + + - + input: + bytes: [ 0x4f, 0x01, 0xa4, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32ch $4, $5, $4" + + - + input: + bytes: [ 0x8f, 0x01, 0x07, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32cw $7, $8, $7" + + - + input: + bytes: [ 0xcf, 0x01, 0x6a, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32cd $10, $11, $10" diff --git a/tests/MC/Mips/valid-64r6.txt.yaml b/tests/MC/Mips/valid-64r6.txt.yaml new file mode 100644 index 000000000..d268a21de --- /dev/null +++ b/tests/MC/Mips/valid-64r6.txt.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x7c, 0x41, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32b $1, $2, $1" + + - + input: + bytes: [ 0x7c, 0xa4, 0x00, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32h $4, $5, $4" + + - + input: + bytes: [ 0x7d, 0x07, 0x00, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32w $7, $8, $7" + + - + input: + bytes: [ 0x7d, 0x6a, 0x00, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32d $10, $11, $10" + + - + input: + bytes: [ 0x7c, 0x41, 0x01, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32cb $1, $2, $1" + + - + input: + bytes: [ 0x7c, 0xa4, 0x01, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32ch $4, $5, $4" + + - + input: + bytes: [ 0x7d, 0x07, 0x01, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32cw $7, $8, $7" + + - + input: + bytes: [ 0x7d, 0x6a, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32cd $10, $11, $10" diff --git a/tests/MC/Mips/valid-el.txt.yaml b/tests/MC/Mips/valid-el.txt.yaml new file mode 100644 index 000000000..34ad44435 --- /dev/null +++ b/tests/MC/Mips/valid-el.txt.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x00, 0x76, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit0 $19, 22, 8" + + - + input: + bytes: [ 0x28, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "baddu $9, $6, $7" + + - + input: + bytes: [ 0x01, 0x00, 0x0a, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit032 $8, 10, 8" + + - + input: + bytes: [ 0x01, 0x00, 0x7f, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit1 $3, 31, 8" + + - + input: + bytes: [ 0x01, 0x00, 0x0a, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit132 $24, 10, 8" + + - + input: + bytes: [ 0x72, 0xec, 0x29, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "cins $9, $9, 17, 29" + + - + input: + bytes: [ 0xb3, 0x44, 0x4f, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "cins32 $15, $2, 18, 8" + + - + input: + bytes: [ 0x03, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dmul $9, $6, $7" + + - + input: + bytes: [ 0x40, 0x00, 0x22, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dmfc2 $2, 64" + + - + input: + bytes: [ 0x47, 0x40, 0xa2, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dmtc2 $2, 16455" + + - + input: + bytes: [ 0x2d, 0x48, 0xc0, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dpop $9, $6" + + - + input: + bytes: [ 0x7a, 0x34, 0xef, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "exts $15, $15, 17, 6" + + - + input: + bytes: [ 0xbb, 0x42, 0xa4, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "exts32 $4, $13, 10, 8" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtm0 $15" + + - + input: + bytes: [ 0x0c, 0x00, 0x00, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtm1 $16" + + - + input: + bytes: [ 0x0d, 0x00, 0x20, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtm2 $17" + + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtp0 $18" + + - + input: + bytes: [ 0x0a, 0x00, 0x60, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtp1 $19" + + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtp2 $20" + + - + input: + bytes: [ 0x2c, 0x48, 0xc0, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "pop $9, $6" + + - + input: + bytes: [ 0x2a, 0xc8, 0xf8, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "seq $25, $23, $24" + + - + input: + bytes: [ 0xae, 0x09, 0x10, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "seqi $16, $16, 38" + + - + input: + bytes: [ 0x2b, 0xb8, 0xf4, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "sne $23, $23, $20" + + - + input: + bytes: [ 0xef, 0xb1, 0x04, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "snei $4, $16, -313" + + - + input: + bytes: [ 0x8f, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "sync 6" + + - + input: + bytes: [ 0x11, 0xa8, 0x55, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "v3mulu $21, $10, $21" + + - + input: + bytes: [ 0x10, 0x18, 0x70, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "vmm0 $3, $19, $16" + + - + input: + bytes: [ 0x0f, 0xd8, 0x66, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "vmulu $27, $27, $6" diff --git a/tests/MC/Mips/valid-fp64-el.txt.yaml b/tests/MC/Mips/valid-fp64-el.txt.yaml new file mode 100644 index 000000000..de98701ae --- /dev/null +++ b/tests/MC/Mips/valid-fp64-el.txt.yaml @@ -0,0 +1,260 @@ +test_cases: + - + input: + bytes: [ 0x04, 0x60, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f12" + + - + input: + bytes: [ 0x05, 0x60, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "abs.s $f0, $f12" + + - + input: + bytes: [ 0x04, 0x60, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sqrt.d $f0, $f12" + + - + input: + bytes: [ 0x05, 0x60, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "abs.d $f0, $f12" + + - + input: + bytes: [ 0x00, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "add.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x01, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sub.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x02, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mul.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x03, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "div.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x06, 0x10, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mov.d $f0, $f2" + + - + input: + bytes: [ 0x07, 0x10, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "neg.d $f0, $f2" + + - + input: + bytes: [ 0x24, 0x10, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cvt.w.d $f0, $f2" + + - + input: + bytes: [ 0x21, 0x10, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cvt.d.s $f0, $f2" + + - + input: + bytes: [ 0x21, 0x10, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cvt.d.w $f0, $f2" + + - + input: + bytes: [ 0x20, 0x10, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cvt.s.d $f0, $f2" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0xa0, 0xd3, 0xc0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.pu $f14, $f26" + + - + input: + bytes: [ 0xa6, 0x90, 0x14, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.ps.s $f2, $f18, $f20" + + - + input: + bytes: [ 0xa8, 0x17, 0xc0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.pl $f30, $f2" + + - + input: + bytes: [ 0x2c, 0x46, 0xde, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pll.ps $f24, $f8, $f30" + + - + input: + bytes: [ 0x2d, 0xd0, 0xdc, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "plu.ps $f0, $f26, $f28" + + - + input: + bytes: [ 0x00, 0x00, 0xe4, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mthc1 $4, $f0" + + - + input: + bytes: [ 0x00, 0x00, 0x64, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mfhc1 $4, $f0" + + - + input: + bytes: [ 0x00, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x02, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x01, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" diff --git a/tests/MC/Mips/valid-fp64.txt.yaml b/tests/MC/Mips/valid-fp64.txt.yaml new file mode 100644 index 000000000..347edd68f --- /dev/null +++ b/tests/MC/Mips/valid-fp64.txt.yaml @@ -0,0 +1,260 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f12" + + - + input: + bytes: [ 0x46, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f0, $f12" + + - + input: + bytes: [ 0x46, 0x20, 0x60, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f0, $f12" + + - + input: + bytes: [ 0x46, 0x20, 0x60, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f0, $f12" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f0, $f2" + + - + input: + bytes: [ 0x46, 0x20, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f0, $f2" + + - + input: + bytes: [ 0x46, 0x20, 0x10, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f0, $f2" + + - + input: + bytes: [ 0x46, 0x00, 0x10, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f0, $f2" + + - + input: + bytes: [ 0x46, 0x80, 0x10, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f0, $f2" + + - + input: + bytes: [ 0x46, 0x20, 0x10, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f0, $f2" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x46, 0xc0, 0xd3, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.pu $f14, $f26" + + - + input: + bytes: [ 0x46, 0x14, 0x90, 0xa6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.ps.s $f2, $f18, $f20" + + - + input: + bytes: [ 0x46, 0xc0, 0x17, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.pl $f30, $f2" + + - + input: + bytes: [ 0x46, 0xde, 0x46, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pll.ps $f24, $f8, $f30" + + - + input: + bytes: [ 0x46, 0xdc, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "plu.ps $f0, $f26, $f28" + + - + input: + bytes: [ 0x44, 0xe4, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthc1 $4, $f0" + + - + input: + bytes: [ 0x44, 0x64, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhc1 $4, $f0" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" diff --git a/tests/MC/Mips/valid-micromips-el.txt.yaml b/tests/MC/Mips/valid-micromips-el.txt.yaml new file mode 100644 index 000000000..799e5a223 --- /dev/null +++ b/tests/MC/Mips/valid-micromips-el.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x85, 0x00, 0xfc, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 0" + + - + input: + bytes: [ 0x85, 0x00, 0xfc, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 2" + + - + input: + bytes: [ 0xa4, 0x00, 0xfc, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mtgc0 $5, $4, 0" + + - + input: + bytes: [ 0xa4, 0x00, 0xfc, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mtgc0 $5, $4, 2" + + - + input: + bytes: [ 0x85, 0x00, 0xf4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 0" + + - + input: + bytes: [ 0x85, 0x00, 0xf4, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 2" + + - + input: + bytes: [ 0xa4, 0x00, 0xf4, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mthgc0 $5, $4, 0" + + - + input: + bytes: [ 0xa4, 0x00, 0xf4, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mthgc0 $5, $4, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "hypcall" + + - + input: + bytes: [ 0x0a, 0x00, 0x7c, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "hypcall 10" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbginv" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbginvf" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgp" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgr" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgwi" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgwr" diff --git a/tests/MC/Mips/valid-micromips.txt.yaml b/tests/MC/Mips/valid-micromips.txt.yaml new file mode 100644 index 000000000..8765a2560 --- /dev/null +++ b/tests/MC/Mips/valid-micromips.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x85, 0x04, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 0" + + - + input: + bytes: [ 0x00, 0x85, 0x14, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 2" + + - + input: + bytes: [ 0x00, 0xa4, 0x06, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mtgc0 $5, $4, 0" + + - + input: + bytes: [ 0x00, 0xa4, 0x16, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mtgc0 $5, $4, 2" + + - + input: + bytes: [ 0x00, 0x85, 0x04, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 0" + + - + input: + bytes: [ 0x00, 0x85, 0x14, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 2" + + - + input: + bytes: [ 0x00, 0xa4, 0x06, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mthgc0 $5, $4, 0" + + - + input: + bytes: [ 0x00, 0xa4, 0x16, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mthgc0 $5, $4, 2" + + - + input: + bytes: [ 0x00, 0x00, 0xc3, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "hypcall" + + - + input: + bytes: [ 0x00, 0x0a, 0xc3, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "hypcall 10" + + - + input: + bytes: [ 0x00, 0x00, 0x41, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbginv" + + - + input: + bytes: [ 0x00, 0x00, 0x51, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbginvf" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgp" + + - + input: + bytes: [ 0x00, 0x00, 0x11, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgr" + + - + input: + bytes: [ 0x00, 0x00, 0x21, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgwi" + + - + input: + bytes: [ 0x00, 0x00, 0x31, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgwr" diff --git a/tests/MC/Mips/valid-micromips32r3.txt.yaml b/tests/MC/Mips/valid-micromips32r3.txt.yaml new file mode 100644 index 000000000..58fda1ce4 --- /dev/null +++ b/tests/MC/Mips/valid-micromips32r3.txt.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x43, 0x60, 0x00, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bposge32 350" diff --git a/tests/MC/Mips/valid-mips1-el.txt.yaml b/tests/MC/Mips/valid-mips1-el.txt.yaml new file mode 100644 index 000000000..3bcd12634 --- /dev/null +++ b/tests/MC/Mips/valid-mips1-el.txt.yaml @@ -0,0 +1,1060 @@ +test_cases: + - + input: + bytes: [ 0x85, 0xc1, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x45, 0x82, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x20, 0xb8, 0x45, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x00, 0x30, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x00, 0xaa, 0x18, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0xd2, 0x66, 0x2d, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0xfe, 0xff, 0x08, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x48, 0x3b, 0xc9, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0xe7, 0xe3, 0x18, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x21, 0x48, 0x86, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x0a, 0x00, 0x29, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x24, 0xb8, 0x4c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x02, 0x00, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x9c, 0x14, 0x11, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x9c, 0x14, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x9c, 0x14, 0xd0, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x3b, 0xe0, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x39, 0x00, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x38, 0xf0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x38, 0x70, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x00, 0xa8, 0x51, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x00, 0xd0, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0xa1, 0xe5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0xa1, 0x5e, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0xa0, 0x46, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0xa0, 0x7d, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x24, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x24, 0xc5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x1a, 0x00, 0x2b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0xa7, 0x3a, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x03, 0x29, 0x0f, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x1b, 0x00, 0x2f, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x4d, 0xc7, 0x58, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0xf3, 0x75, 0x68, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x94, 0xde, 0xab, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0xbd, 0xa6, 0x53, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0xb3, 0x8b, 0x01, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x3f, 0x8b, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x2a, 0x16, 0xa8, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0xf1, 0x27, 0x50, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xb7, 0xfc, 0xd2, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xf7, 0x81, 0x4a, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwc3 $10, -32265($26)" + + - + input: + bytes: [ 0x79, 0xef, 0xf4, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x35, 0xb5, 0x80, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x00, 0xd8, 0x07, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x10, 0x98, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x10, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x12, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x06, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x86, 0xd8, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x25, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x25, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x21, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x21, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0x48, 0x9e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x11, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x02, 0xa5, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x82, 0x57, 0x02, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x18, 0x00, 0xb4, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x18, 0x00, 0xa2, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x19, 0x00, 0x9a, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x19, 0x00, 0x32, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x23, 0x10, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x23, 0x10, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x87, 0x96, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x47, 0x78, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x27, 0x38, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x25, 0x60, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x6f, 0xb2, 0xd6, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xd0, 0xe5, 0xee, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0x80, 0x3c, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x80, 0x3c, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x04, 0x38, 0x20, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x2a, 0xb8, 0x7b, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x11, 0x25, 0x51, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x55, 0xc3, 0x39, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x2b, 0xa0, 0xab, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x55, 0xc3, 0x38, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0xc3, 0x8b, 0x11, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0xc3, 0x8b, 0x17, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x07, 0x88, 0xb7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0xc2, 0x11, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x06, 0xc8, 0x94, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x22, 0xb0, 0x6c, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x36, 0x0c, 0x36, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x90, 0xe6, 0xad, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x81, 0x14, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0xc1, 0xb5, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x23, 0xe8, 0xd6, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x50, 0xd8, 0xbf, 0xaf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xef, 0xde, 0x06, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0x30, 0x61, 0x19, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0x7e, 0x35, 0x6f, 0xaa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0x22, 0x98, 0xd1, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x06, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x26, 0x90, 0x9e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" diff --git a/tests/MC/Mips/valid-mips1.txt.yaml b/tests/MC/Mips/valid-mips1.txt.yaml new file mode 100644 index 000000000..1e18a0e62 --- /dev/null +++ b/tests/MC/Mips/valid-mips1.txt.yaml @@ -0,0 +1,1090 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcf, 0x4a, 0x81, 0xf7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwc3 $10, -32265($26)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" diff --git a/tests/MC/Mips/valid-mips2-el.txt.yaml b/tests/MC/Mips/valid-mips2-el.txt.yaml new file mode 100644 index 000000000..11fa76b4d --- /dev/null +++ b/tests/MC/Mips/valid-mips2-el.txt.yaml @@ -0,0 +1,1550 @@ +test_cases: + - + input: + bytes: [ 0x85, 0xc1, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x45, 0x82, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x20, 0xb8, 0x45, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x48, 0x3b, 0xc9, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0xe7, 0xe3, 0x18, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x00, 0x30, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x00, 0xaa, 0x18, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0xd2, 0x66, 0x2d, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0xfe, 0xff, 0x08, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x48, 0x86, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x0a, 0x00, 0x29, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x24, 0xb8, 0x4c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x0d, 0x00, 0x02, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x02, 0x00, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0xf5, 0xf7, 0x03, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x9c, 0x14, 0x11, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x9c, 0x14, 0xd0, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x41, 0x0c, 0xd3, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x4e, 0x01, 0x20, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "beqzl $9, 1340" + + - + input: + bytes: [ 0x20, 0x07, 0x93, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x4e, 0xf9, 0x83, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x5a, 0xfc, 0x40, 0x5d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0xe8, 0x02, 0xc0, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x7b, 0x00, 0xd2, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x46, 0xf6, 0x22, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0xfd, 0x04, 0x94, 0x57 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x4e, 0x01, 0x20, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bnezl $9, 1340" + + - + input: + bytes: [ 0x3b, 0xe0, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x39, 0x00, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x38, 0xf0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x38, 0x70, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0xce, 0xc2, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x8e, 0xa1, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x00, 0xa8, 0x51, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x00, 0xd0, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0xa1, 0xe5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0xa1, 0x5e, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0xa0, 0x46, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0xa0, 0x7d, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x24, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x24, 0xc5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x1a, 0x00, 0x2b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0xa7, 0x3a, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x03, 0x29, 0x0f, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x1b, 0x00, 0x2f, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0xc0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x8f, 0x53, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x0f, 0x4a, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x4d, 0xc7, 0x58, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0xf3, 0x75, 0x68, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x07, 0x40, 0x0a, 0xd6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0x43, 0xad, 0x28, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0x1b, 0x90, 0x3d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc3 $29, -28645($17)" + + - + input: + bytes: [ 0x94, 0xde, 0xab, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0xbd, 0xa6, 0x53, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0xb3, 0x8b, 0x01, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x3f, 0x8b, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x67, 0xe3, 0x42, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0x2a, 0x16, 0xa8, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0xf1, 0x27, 0x50, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xb7, 0xfc, 0xd2, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xf7, 0x81, 0x4a, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc3 $10, -32265($26)" + + - + input: + bytes: [ 0x79, 0xef, 0xf4, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x35, 0xb5, 0x80, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x00, 0xd8, 0x07, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x10, 0x98, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x10, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x12, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x06, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x86, 0xd8, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x21, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x21, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x25, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x25, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0x48, 0x9e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x11, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x02, 0xa5, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x82, 0x57, 0x02, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x18, 0x00, 0xb4, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x18, 0x00, 0xa2, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x19, 0x00, 0x9a, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x19, 0x00, 0x32, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x23, 0x10, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x23, 0x10, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x87, 0x96, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x47, 0x78, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x27, 0x38, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x25, 0x60, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x8c, 0x21, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0xcc, 0xe6, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x6f, 0xb2, 0xd6, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xd8, 0x49, 0x6f, 0xe2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0x6e, 0x77, 0xbe, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0x75, 0x5a, 0x54, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc3 $12, 5835($10)" + + - + input: + bytes: [ 0xd0, 0xe5, 0xee, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0x80, 0x3c, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x80, 0x3c, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x04, 0x38, 0x20, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x2a, 0xb8, 0x7b, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x11, 0x25, 0x51, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x55, 0xc3, 0x39, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x2b, 0xa0, 0xab, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x55, 0xc3, 0x38, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x04, 0xb4, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x04, 0x08, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0xc3, 0x8b, 0x11, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0xc3, 0x8b, 0x17, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x07, 0x88, 0xb7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0xc2, 0x11, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x06, 0xc8, 0x94, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x22, 0xb0, 0x6c, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x36, 0x0c, 0x36, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x90, 0xe6, 0xad, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x81, 0x14, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0xc1, 0xb5, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x23, 0xe8, 0xd6, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x50, 0xd8, 0xbf, 0xaf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xef, 0xde, 0x06, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0x30, 0x61, 0x19, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf7, 0x81, 0x4a, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc3 $10, -32265($26)" + + - + input: + bytes: [ 0x7e, 0x35, 0x6f, 0xaa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0x22, 0x98, 0xd1, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0x34, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x34, 0x9b, 0xa7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0xa0, 0xbb, 0xac, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x30, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x30, 0x55, 0xb3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0xa1, 0x13, 0x28, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x33, 0x90, 0xa9, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x31, 0x00, 0xdc, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0xf1, 0x5e, 0x8e, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x06, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x32, 0x00, 0xed, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x72, 0x21, 0x53, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0xbd, 0xad, 0xca, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x2c, 0xec, 0xeb, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x33, 0x00, 0x70, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x33, 0xfe, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x36, 0x00, 0xd1, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x76, 0xdd, 0xe8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x31, 0x8c, 0x8e, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x8d, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x0d, 0xf7, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x26, 0x90, 0x9e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" diff --git a/tests/MC/Mips/valid-mips2.txt.yaml b/tests/MC/Mips/valid-mips2.txt.yaml new file mode 100644 index 000000000..fe170ba29 --- /dev/null +++ b/tests/MC/Mips/valid-mips2.txt.yaml @@ -0,0 +1,1760 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x51, 0x20, 0x01, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "beqzl $9, 1344" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x55, 0x20, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bnezl $9, 1340" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcd, 0x28, 0x23, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc3 $8, 9166($9)" + + - + input: + bytes: [ 0xcf, 0x4a, 0x81, 0xf7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc3 $10, -32265($26)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xdd, 0x07, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc3 $7, 9162($8)" + + - + input: + bytes: [ 0xde, 0x3d, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc3 $29, -28645($17)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xec, 0xe6, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc3 $6, 9158($7)" + + - + input: + bytes: [ 0xef, 0x4a, 0x81, 0xf7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc3 $10, -32265($26)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfc, 0xc5, 0x23, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc3 $5, 9154($6)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc3 $12, 5835($10)" diff --git a/tests/MC/Mips/valid-mips3-el.txt.yaml b/tests/MC/Mips/valid-mips3-el.txt.yaml new file mode 100644 index 000000000..20473f709 --- /dev/null +++ b/tests/MC/Mips/valid-mips3-el.txt.yaml @@ -0,0 +1,1960 @@ +test_cases: + - + input: + bytes: [ 0x85, 0xc1, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x45, 0x82, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x20, 0xb8, 0x45, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x48, 0x3b, 0xc9, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0xe7, 0xe3, 0x18, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x00, 0x30, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x00, 0xaa, 0x18, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0xd2, 0x66, 0x2d, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0xfe, 0xff, 0x08, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x48, 0x86, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x0a, 0x00, 0x29, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x24, 0xb8, 0x4c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x0d, 0x00, 0x02, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x02, 0x00, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0xf5, 0xf7, 0x03, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x9c, 0x14, 0x11, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x9c, 0x14, 0xd0, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x41, 0x0c, 0xd3, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x20, 0x07, 0x93, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x4e, 0xf9, 0x83, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x5a, 0xfc, 0x40, 0x5d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0xe8, 0x02, 0xc0, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x7b, 0x00, 0xd2, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x46, 0xf6, 0x22, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0xfd, 0x04, 0x94, 0x57 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x08, 0x00, 0xa1, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0x3b, 0xe0, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x39, 0x00, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x38, 0xf0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x38, 0x70, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0xce, 0xc2, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x8e, 0xa1, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x00, 0xa8, 0x51, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x00, 0xd0, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0xa1, 0xe5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0xa1, 0x5e, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x25, 0x7e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f24, $f15" + + - + input: + bytes: [ 0xe5, 0xea, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f11, $f29" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0xa0, 0x46, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0xa0, 0x7d, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x24, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x24, 0xc5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x1a, 0x00, 0x2b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0xa7, 0x3a, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x03, 0x29, 0x0f, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x1b, 0x00, 0x2f, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0xc0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x18, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x8f, 0x53, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x0f, 0x4a, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x4d, 0xc7, 0x58, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0xf3, 0x75, 0x68, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x07, 0x40, 0x0a, 0xd6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0x43, 0xad, 0x28, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0x94, 0xde, 0xab, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0xbd, 0xa6, 0x53, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0xb3, 0x8b, 0x01, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x3f, 0x8b, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x67, 0xe3, 0x42, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0x2a, 0x16, 0xa8, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0xf1, 0x27, 0x50, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xb7, 0xfc, 0xd2, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0x79, 0xef, 0xf4, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x35, 0xb5, 0x80, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x00, 0xd8, 0x07, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x10, 0x98, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x10, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x12, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x06, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x86, 0xd8, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x21, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x21, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x25, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x25, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0x48, 0x9e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x11, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x02, 0xa5, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x82, 0x57, 0x02, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x18, 0x00, 0xb4, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x18, 0x00, 0xa2, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x19, 0x00, 0x9a, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x19, 0x00, 0x32, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x23, 0x10, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x23, 0x10, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x87, 0x96, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x47, 0x78, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x27, 0x38, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x25, 0x60, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x8c, 0x21, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0xcc, 0xe6, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x6f, 0xb2, 0xd6, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xd8, 0x49, 0x6f, 0xe2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x6e, 0x77, 0xbe, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0x75, 0x5a, 0x54, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xd0, 0xe5, 0xee, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0x80, 0x3c, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x80, 0x3c, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x04, 0x38, 0x20, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x2a, 0xb8, 0x7b, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x11, 0x25, 0x51, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x55, 0xc3, 0x39, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x2b, 0xa0, 0xab, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x55, 0xc3, 0x38, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x04, 0xb4, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x04, 0x08, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0xc3, 0x8b, 0x11, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0xc3, 0x8b, 0x17, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x07, 0x88, 0xb7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0xc2, 0x11, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x06, 0xc8, 0x94, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x22, 0xb0, 0x6c, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x36, 0x0c, 0x36, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x90, 0xe6, 0xad, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x81, 0x14, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0xc1, 0xb5, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x23, 0xe8, 0xd6, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x50, 0xd8, 0xbf, 0xaf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xef, 0xde, 0x06, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0x30, 0x61, 0x19, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0x7e, 0x35, 0x6f, 0xaa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0x22, 0x98, 0xd1, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0x34, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x34, 0x9b, 0xa7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0xa0, 0xbb, 0xac, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x30, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x30, 0x55, 0xb3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0xa1, 0x13, 0x28, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x33, 0x90, 0xa9, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x31, 0x00, 0xdc, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0xf1, 0x5e, 0x8e, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x06, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x32, 0x00, 0xed, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x72, 0x21, 0x53, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0xbd, 0xad, 0xca, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x2c, 0xec, 0xeb, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x33, 0x00, 0x70, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x33, 0xfe, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x36, 0x00, 0xd1, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x76, 0xdd, 0xe8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x31, 0x8c, 0x8e, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x8d, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x0d, 0xf7, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x26, 0x90, 0x9e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" diff --git a/tests/MC/Mips/valid-mips3.txt.yaml b/tests/MC/Mips/valid-mips3.txt.yaml new file mode 100644 index 000000000..0d2b71010 --- /dev/null +++ b/tests/MC/Mips/valid-mips3.txt.yaml @@ -0,0 +1,2210 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x3a, 0x00, 0x27, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "xori $zero, $16, 10002" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xea, 0xe5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f11, $f29" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x7e, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f24, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0xa1, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0xbf, 0x00, 0xe2, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cache 0, -7652($24)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" diff --git a/tests/MC/Mips/valid-mips32-el.txt.yaml b/tests/MC/Mips/valid-mips32-el.txt.yaml new file mode 100644 index 000000000..a7cf8282f --- /dev/null +++ b/tests/MC/Mips/valid-mips32-el.txt.yaml @@ -0,0 +1,1560 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x21, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x25, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x04, 0x80, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x25, 0x38, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $7, $8" + + - + input: + bytes: [ 0x25, 0x18, 0x40, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $3, $2" + + - + input: + bytes: [ 0x01, 0x18, 0x5c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x11, 0x11, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x11, 0x11, 0x1c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x01, 0x18, 0x5d, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x11, 0x11, 0x3d, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x11, 0x11, 0x1d, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3b, 0xe8, 0x05, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x02, 0x00, 0x61, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0x04, 0x00, 0x43, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xca, 0x23, 0xc8, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" diff --git a/tests/MC/Mips/valid-mips32.txt.yaml b/tests/MC/Mips/valid-mips32.txt.yaml new file mode 100644 index 000000000..5a19d69b7 --- /dev/null +++ b/tests/MC/Mips/valid-mips32.txt.yaml @@ -0,0 +1,3270 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" diff --git a/tests/MC/Mips/valid-mips32r2-el.txt.yaml b/tests/MC/Mips/valid-mips32r2-el.txt.yaml new file mode 100644 index 000000000..5aa6cc3e5 --- /dev/null +++ b/tests/MC/Mips/valid-mips32r2-el.txt.yaml @@ -0,0 +1,5250 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x04, 0x80, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x4c, 0x1d, 0x7f, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "synci 7500($19)" + + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x04, 0x80, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x4c, 0x1d, 0x7f, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "synci 7500($19)" + + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x04, 0x80, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x4c, 0x1d, 0x7f, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "synci 7500($19)" diff --git a/tests/MC/Mips/valid-mips32r2.txt.yaml b/tests/MC/Mips/valid-mips32r2.txt.yaml new file mode 100644 index 000000000..092d00706 --- /dev/null +++ b/tests/MC/Mips/valid-mips32r2.txt.yaml @@ -0,0 +1,10830 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" diff --git a/tests/MC/Mips/valid-mips32r3-el.txt.yaml b/tests/MC/Mips/valid-mips32r3-el.txt.yaml new file mode 100644 index 000000000..ece49526a --- /dev/null +++ b/tests/MC/Mips/valid-mips32r3-el.txt.yaml @@ -0,0 +1,3460 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" diff --git a/tests/MC/Mips/valid-mips32r3.txt.yaml b/tests/MC/Mips/valid-mips32r3.txt.yaml new file mode 100644 index 000000000..36a7d4e95 --- /dev/null +++ b/tests/MC/Mips/valid-mips32r3.txt.yaml @@ -0,0 +1,7220 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" diff --git a/tests/MC/Mips/valid-mips32r5-el.txt.yaml b/tests/MC/Mips/valid-mips32r5-el.txt.yaml new file mode 100644 index 000000000..e102187d1 --- /dev/null +++ b/tests/MC/Mips/valid-mips32r5-el.txt.yaml @@ -0,0 +1,3460 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" diff --git a/tests/MC/Mips/valid-mips32r5.txt.yaml b/tests/MC/Mips/valid-mips32r5.txt.yaml new file mode 100644 index 000000000..8b105f270 --- /dev/null +++ b/tests/MC/Mips/valid-mips32r5.txt.yaml @@ -0,0 +1,7240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "eretnc" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "eretnc" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" diff --git a/tests/MC/Mips/valid-mips32r6-el.txt.yaml b/tests/MC/Mips/valid-mips32r6-el.txt.yaml new file mode 100644 index 000000000..2588f3da0 --- /dev/null +++ b/tests/MC/Mips/valid-mips32r6-el.txt.yaml @@ -0,0 +1,1730 @@ +test_cases: + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x19, 0x00, 0x80, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lapc $4, 100" + + - + input: + bytes: [ 0x0a, 0x00, 0x29, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0xa0, 0x22, 0x43, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "align $4, $2, $3, 2" + + - + input: + bytes: [ 0x38, 0x00, 0x7f, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "aluipc $3, 56" + + - + input: + bytes: [ 0xe9, 0xff, 0x43, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "aui $3, $2, 65513" + + - + input: + bytes: [ 0xff, 0xff, 0x7e, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "auipc $3, -1" + + - + input: + bytes: [ 0x9c, 0x14, 0x11, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0xb9, 0x96, 0x37, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "balc 14572264" + + - + input: + bytes: [ 0xb9, 0x96, 0x37, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc 14572264" + + - + input: + bytes: [ 0x02, 0x00, 0x20, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f0, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x3f, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f31, 12" + + - + input: + bytes: [ 0x02, 0x00, 0xa0, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1nez $f0, 12" + + - + input: + bytes: [ 0x02, 0x00, 0xbf, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1nez $f31, 12" + + - + input: + bytes: [ 0x03, 0x00, 0x20, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2eqz $0, 16" + + - + input: + bytes: [ 0x03, 0x00, 0x3f, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2eqz $31, 16" + + - + input: + bytes: [ 0x03, 0x00, 0xa0, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2nez $0, 16" + + - + input: + bytes: [ 0x03, 0x00, 0xbf, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2nez $31, 16" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqc $5, $6, 264" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqzalc $2, 1340" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnec $5, $6, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x43, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnec $2, $3, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnezalc $2, 1340" + + - + input: + bytes: [ 0x91, 0x46, 0xa0, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqzc $5, 72264" + + - + input: + bytes: [ 0x41, 0x00, 0x43, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x43, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x43, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x43, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x42, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x42, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, -16" + + - + input: + bytes: [ 0x91, 0x46, 0xa0, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnezc $5, 72264" + + - + input: + bytes: [ 0x41, 0x00, 0xa5, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa5, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzc $5, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa5, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa5, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezc $5, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x02, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x05, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x05, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezc $5, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x42, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x42, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x05, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x05, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, -16" + + - + input: + bytes: [ 0x20, 0x20, 0x02, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bitswap $4, $2" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x02, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa6, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa6, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, -16" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $zero, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x40, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $2, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x82, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $4, $2, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $zero, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x40, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $2, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x82, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $4, $2, 12" + + - + input: + bytes: [ 0x80, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.af.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x80, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.af.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x81, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.un.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x81, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.un.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x82, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.eq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x82, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.eq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x83, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x83, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x84, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.lt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x84, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.lt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x85, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x85, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x86, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.le.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x86, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.le.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x87, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x87, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x88, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.saf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x88, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.saf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x89, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sun.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x89, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sun.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8a, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.seq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8a, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.seq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8b, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8b, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8c, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.slt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8c, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.slt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8d, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8d, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8e, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sle.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8e, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sle.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8f, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8f, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x24, 0x00, 0x71, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "dvp $17" + + - + input: + bytes: [ 0x24, 0x00, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "dvp $zero" + + - + input: + bytes: [ 0x9a, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "div $2, $3, $4" + + - + input: + bytes: [ 0x9b, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "divu $2, $3, $4" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x04, 0x00, 0x70, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "evp $16" + + - + input: + bytes: [ 0x04, 0x00, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "evp $zero" + + - + input: + bytes: [ 0xc5, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lsa $2, $3, $4, 4" + + - + input: + bytes: [ 0x43, 0x00, 0x48, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lwpc $2, 268" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0xda, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mod $2, $3, $4" + + - + input: + bytes: [ 0xdb, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "modu $2, $3, $4" + + - + input: + bytes: [ 0x98, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mul $2, $3, $4" + + - + input: + bytes: [ 0xd8, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "muh $2, $3, $4" + + - + input: + bytes: [ 0x99, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mulu $2, $3, $4" + + - + input: + bytes: [ 0xd9, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "muhu $2, $3, $4" + + - + input: + bytes: [ 0x98, 0x18, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maddf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x98, 0x18, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maddf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x99, 0x18, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "msubf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x99, 0x18, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "msubf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x10, 0x08, 0x22, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sel.d $f0, $f1, $f2" + + - + input: + bytes: [ 0x10, 0x08, 0x02, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sel.s $f0, $f1, $f2" + + - + input: + bytes: [ 0x35, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "seleqz $2, $3, $4" + + - + input: + bytes: [ 0x37, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "selnez $2, $3, $4" + + - + input: + bytes: [ 0x1d, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "max.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x1d, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "max.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x1c, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "min.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x1c, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "min.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x1f, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maxa.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x1f, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maxa.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x1e, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mina.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x1e, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mina.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x14, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "seleqz.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x14, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "seleqz.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x17, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "selnez.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x17, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "selnez.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x9a, 0x20, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rint.s $f2, $f4" + + - + input: + bytes: [ 0x9a, 0x20, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rint.d $f2, $f4" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x9b, 0x20, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "class.s $f2, $f4" + + - + input: + bytes: [ 0x9b, 0x20, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "class.d $f2, $f4" + + - + input: + bytes: [ 0x09, 0x04, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jr.hb $4" + + - + input: + bytes: [ 0x00, 0x00, 0x1b, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jrc $27" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0x00, 0x19, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jalrc $25" + + - + input: + bytes: [ 0xb6, 0xb3, 0x42, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ll $2, -153($18)" + + - + input: + bytes: [ 0x26, 0xec, 0x6f, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sc $15, -40($19)" + + - + input: + bytes: [ 0x51, 0x58, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "clo $11, $5" + + - + input: + bytes: [ 0x50, 0xe8, 0x80, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "clz $sp, $gp" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x0e, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sdbbp" + + - + input: + bytes: [ 0x8e, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sdbbp 34" + + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x4f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sync 1" + + - + input: + bytes: [ 0x34, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x34, 0x9b, 0xa7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x30, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x30, 0x55, 0xb3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x31, 0x00, 0xdc, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0xf1, 0x5e, 0x8e, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x32, 0x00, 0xed, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x72, 0x21, 0x53, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x33, 0x00, 0x70, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x33, 0xfe, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x36, 0x00, 0xd1, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x76, 0xdd, 0xe8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x43, 0x0d, 0xc8, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ldc2 $8, -701($1)" + + - + input: + bytes: [ 0xb7, 0x34, 0x52, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0x75, 0x92, 0xf4, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sdc2 $20, 629($18)" + + - + input: + bytes: [ 0x30, 0x81, 0x79, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "swc2 $25, 304($16)" + + - + input: + bytes: [ 0x00, 0x01, 0x05, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jialc $5, 256" + + - + input: + bytes: [ 0x00, 0x01, 0x05, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jic $5, 256" + + - + input: + bytes: [ 0x25, 0x04, 0xa1, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0x35, 0x04, 0xa1, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "pref 1, 8($5)" + + - + input: + bytes: [ 0x05, 0x00, 0x17, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sigrie 5" diff --git a/tests/MC/Mips/valid-mips32r6.txt.yaml b/tests/MC/Mips/valid-mips32r6.txt.yaml new file mode 100644 index 000000000..476827278 --- /dev/null +++ b/tests/MC/Mips/valid-mips32r6.txt.yaml @@ -0,0 +1,1780 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sdbbp" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sync 1" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x08, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sdbbp 34" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "seleqz $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "selnez $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mul $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mulu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "div $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "divu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lsa $2, $3, $4, 4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "muh $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "muhu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mod $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "modu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x80, 0x04, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jr.hb $4" + + - + input: + bytes: [ 0xd8, 0x1b, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jrc $27" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0xf8, 0x19, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jalrc $25" + + - + input: + bytes: [ 0x00, 0xa0, 0x58, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "clo $11, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x80, 0xe8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "clz $sp, $gp" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x18, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezalc $2, 1340" + + - + input: + bytes: [ 0x18, 0x02, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezalc $2, -16" + + - + input: + bytes: [ 0x18, 0x42, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, 1340" + + - + input: + bytes: [ 0x18, 0x42, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, -16" + + - + input: + bytes: [ 0x18, 0x43, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, 264" + + - + input: + bytes: [ 0x18, 0x43, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, -16" + + - + input: + bytes: [ 0x1c, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, 1340" + + - + input: + bytes: [ 0x1c, 0x02, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, -16" + + - + input: + bytes: [ 0x1c, 0x42, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, 1340" + + - + input: + bytes: [ 0x1c, 0x42, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, -16" + + - + input: + bytes: [ 0x1c, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, 264" + + - + input: + bytes: [ 0x1c, 0xa6, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, -16" + + - + input: + bytes: [ 0x20, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $zero, $zero, 12" + + - + input: + bytes: [ 0x20, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqzalc $2, 1340" + + - + input: + bytes: [ 0x20, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $2, $zero, 12" + + - + input: + bytes: [ 0x20, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $4, $2, 12" + + - + input: + bytes: [ 0x20, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqc $5, $6, 264" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x3c, 0x43, 0xff, 0xe9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "aui $3, $2, 65513" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 3" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "dvp $zero" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "evp $zero" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x70, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "evp $16" + + - + input: + bytes: [ 0x41, 0x71, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "dvp $17" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x45, 0x20, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f0, 12" + + - + input: + bytes: [ 0x45, 0x3f, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f31, 12" + + - + input: + bytes: [ 0x45, 0xa0, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1nez $f0, 12" + + - + input: + bytes: [ 0x45, 0xbf, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1nez $f31, 12" + + - + input: + bytes: [ 0x46, 0x00, 0x20, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rint.s $f2, $f4" + + - + input: + bytes: [ 0x46, 0x00, 0x20, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "class.s $f2, $f4" + + - + input: + bytes: [ 0x46, 0x02, 0x08, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sel.s $f0, $f1, $f2" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "seleqz.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "selnez.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "min.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "max.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mina.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maxa.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x18, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maddf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x18, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "msubf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x20, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rint.d $f2, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x20, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "class.d $f2, $f4" + + - + input: + bytes: [ 0x46, 0x22, 0x08, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sel.d $f0, $f1, $f2" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "seleqz.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "selnez.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "min.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "max.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mina.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maxa.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x18, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maddf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x18, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "msubf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.af.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.un.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.eq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x83 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.lt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.le.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.saf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sun.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.seq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.slt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sle.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.af.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.un.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.eq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x83 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.lt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.le.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.saf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sun.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.seq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.slt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sle.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "eretnc" + + - + input: + bytes: [ 0x49, 0x20, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2eqz $0, 16" + + - + input: + bytes: [ 0x49, 0x3f, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2eqz $31, 16" + + - + input: + bytes: [ 0x49, 0x52, 0x34, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0x49, 0x79, 0x81, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "swc2 $25, 304($16)" + + - + input: + bytes: [ 0x49, 0xa0, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2nez $0, 16" + + - + input: + bytes: [ 0x49, 0xbf, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2nez $31, 16" + + - + input: + bytes: [ 0x49, 0xc8, 0x0d, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ldc2 $8, -701($1)" + + - + input: + bytes: [ 0x49, 0xf4, 0x92, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sdc2 $20, 629($18)" + + - + input: + bytes: [ 0x58, 0x05, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezc $5, 264" + + - + input: + bytes: [ 0x58, 0x05, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezc $5, -16" + + - + input: + bytes: [ 0x58, 0x43, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, 264" + + - + input: + bytes: [ 0x58, 0x43, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, -16" + + - + input: + bytes: [ 0x58, 0xa5, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezc $5, 264" + + - + input: + bytes: [ 0x58, 0xa5, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezc $5, -16" + + - + input: + bytes: [ 0x5c, 0x05, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, 264" + + - + input: + bytes: [ 0x5c, 0x05, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, -16" + + - + input: + bytes: [ 0x5c, 0xa5, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzc $5, 264" + + - + input: + bytes: [ 0x5c, 0xa5, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzc $5, -16" + + - + input: + bytes: [ 0x5c, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, 264" + + - + input: + bytes: [ 0x5c, 0xa6, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, -16" + + - + input: + bytes: [ 0x60, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $zero, $zero, 12" + + - + input: + bytes: [ 0x60, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnezalc $2, 1340" + + - + input: + bytes: [ 0x60, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $2, $zero, 12" + + - + input: + bytes: [ 0x60, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $4, $2, 12" + + - + input: + bytes: [ 0x60, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnec $5, $6, 264" + + - + input: + bytes: [ 0x60, 0x43, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnec $2, $3, -16" + + - + input: + bytes: [ 0x7c, 0x02, 0x20, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bitswap $4, $2" + + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "align $4, $2, $3, 2" + + - + input: + bytes: [ 0x7c, 0xa1, 0x04, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0x7c, 0xa1, 0x04, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "pref 1, 8($5)" + + - + input: + bytes: [ 0x7e, 0x42, 0xb3, 0xb6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ll $2, -153($18)" + + - + input: + bytes: [ 0x7e, 0x6f, 0xec, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sc $15, -40($19)" + + - + input: + bytes: [ 0xc8, 0x37, 0x96, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc 14572264" + + - + input: + bytes: [ 0xd8, 0x05, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jic $5, 256" + + - + input: + bytes: [ 0xd8, 0xa0, 0x46, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqzc $5, 72264" + + - + input: + bytes: [ 0xd8, 0x5f, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqzc $2, -16" + + - + input: + bytes: [ 0xe8, 0x37, 0x96, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "balc 14572264" + + - + input: + bytes: [ 0xec, 0x48, 0x00, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lwpc $2, 268" + + - + input: + bytes: [ 0xec, 0x7e, 0xff, 0xff ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "auipc $3, -1" + + - + input: + bytes: [ 0xec, 0x7f, 0x00, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "aluipc $3, 56" + + - + input: + bytes: [ 0xec, 0x80, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lapc $4, 100" + + - + input: + bytes: [ 0xf8, 0x05, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jialc $5, 256" + + - + input: + bytes: [ 0xf8, 0xa0, 0x46, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnezc $5, 72264" + + - + input: + bytes: [ 0xf8, 0x5f, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnezc $2, -16" + + - + input: + bytes: [ 0x04, 0x17, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sigrie 5" diff --git a/tests/MC/Mips/valid-mips4-el.txt.yaml b/tests/MC/Mips/valid-mips4-el.txt.yaml new file mode 100644 index 000000000..ca46997e3 --- /dev/null +++ b/tests/MC/Mips/valid-mips4-el.txt.yaml @@ -0,0 +1,2200 @@ +test_cases: + - + input: + bytes: [ 0x85, 0xc1, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x45, 0x82, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x20, 0xb8, 0x45, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x48, 0x3b, 0xc9, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0xe7, 0xe3, 0x18, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x00, 0x30, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x00, 0xaa, 0x18, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0xd2, 0x66, 0x2d, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0xfe, 0xff, 0x08, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x48, 0x86, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x0a, 0x00, 0x29, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x24, 0xb8, 0x4c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x01, 0x00, 0x04, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1f $fcc1, 8" + + - + input: + bytes: [ 0x07, 0x00, 0x1e, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1fl $fcc7, 32" + + - + input: + bytes: [ 0x0d, 0x00, 0x02, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x02, 0x00, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x01, 0x00, 0x05, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1t $fcc1, 8" + + - + input: + bytes: [ 0xf5, 0xf7, 0x03, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x07, 0x00, 0x1f, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1tl $fcc7, 32" + + - + input: + bytes: [ 0x9c, 0x14, 0x11, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x9c, 0x14, 0xd0, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x41, 0x0c, 0xd3, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x20, 0x07, 0x93, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x4e, 0xf9, 0x83, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x5a, 0xfc, 0x40, 0x5d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0xe8, 0x02, 0xc0, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x7b, 0x00, 0xd2, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x46, 0xf6, 0x22, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0xfd, 0x04, 0x94, 0x57 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x08, 0x00, 0xa1, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0x3b, 0xe0, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x39, 0x00, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x38, 0xf0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x38, 0x70, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0xce, 0xc2, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x8e, 0xa1, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x00, 0xa8, 0x51, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x00, 0xd0, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0xa1, 0xe5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0xa1, 0x5e, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x25, 0x7e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.l.d $f24, $f15" + + - + input: + bytes: [ 0xe5, 0xea, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.l.s $f11, $f29" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0xa0, 0x46, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0xa0, 0x7d, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x24, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x24, 0xc5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x1a, 0x00, 0x2b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0xa7, 0x3a, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x03, 0x29, 0x0f, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x1b, 0x00, 0x2f, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0xc0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x18, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x8f, 0x53, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x0f, 0x4a, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x4d, 0xc7, 0x58, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0xf3, 0x75, 0x68, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x07, 0x40, 0x0a, 0xd6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0x43, 0xad, 0x28, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0x94, 0xde, 0xab, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0xbd, 0xa6, 0x53, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0xb3, 0x8b, 0x01, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x3f, 0x8b, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x67, 0xe3, 0x42, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0x2a, 0x16, 0xa8, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0xf1, 0x27, 0x50, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xb7, 0xfc, 0xd2, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0x79, 0xef, 0xf4, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x35, 0xb5, 0x80, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x00, 0x03, 0xd1, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x00, 0xd8, 0x07, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x10, 0x98, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x10, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x12, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x06, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x86, 0xd8, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x01, 0xe0, 0x1c, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movf $gp, $8, $fcc7" + + - + input: + bytes: [ 0x91, 0x59, 0x34, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movf.d $f6, $f11, $fcc5" + + - + input: + bytes: [ 0xd1, 0x2d, 0x18, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movf.s $f23, $f5, $fcc6" + + - + input: + bytes: [ 0x21, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x21, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x25, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x25, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x0b, 0x18, 0x30, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movn $3, $17, $16" + + - + input: + bytes: [ 0xd3, 0xae, 0x3a, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movn.d $f27, $f21, $26" + + - + input: + bytes: [ 0x13, 0x03, 0x17, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movn.s $f12, $f0, $23" + + - + input: + bytes: [ 0x01, 0x00, 0x95, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movt $zero, $20, $fcc5" + + - + input: + bytes: [ 0x11, 0x10, 0x21, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movt.d $f0, $f2, $fcc0" + + - + input: + bytes: [ 0x91, 0x17, 0x05, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movt.s $f30, $f2, $fcc1" + + - + input: + bytes: [ 0x0a, 0x28, 0xc9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movz $5, $22, $9" + + - + input: + bytes: [ 0x12, 0xeb, 0x29, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movz.d $f12, $f29, $9" + + - + input: + bytes: [ 0x52, 0x3e, 0x03, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movz.s $f25, $f7, $3" + + - + input: + bytes: [ 0x00, 0x48, 0x9e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x11, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x02, 0xa5, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x82, 0x57, 0x02, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x18, 0x00, 0xb4, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x18, 0x00, 0xa2, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x19, 0x00, 0x9a, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x19, 0x00, 0x32, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x23, 0x10, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x23, 0x10, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x87, 0x96, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x47, 0x78, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x27, 0x38, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x25, 0x60, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x08, 0x00, 0xa1, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "pref 1, 8($5)" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x8c, 0x21, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0xcc, 0xe6, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x6f, 0xb2, 0xd6, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xd8, 0x49, 0x6f, 0xe2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x6e, 0x77, 0xbe, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0x75, 0x5a, 0x54, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0x09, 0x58, 0xca, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0xd0, 0xe5, 0xee, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0x80, 0x3c, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x80, 0x3c, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x04, 0x38, 0x20, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x2a, 0xb8, 0x7b, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x11, 0x25, 0x51, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x55, 0xc3, 0x39, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x2b, 0xa0, 0xab, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x55, 0xc3, 0x38, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x04, 0xb4, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x04, 0x08, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0xc3, 0x8b, 0x11, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0xc3, 0x8b, 0x17, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x07, 0x88, 0xb7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0xc2, 0x11, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x06, 0xc8, 0x94, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x22, 0xb0, 0x6c, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x36, 0x0c, 0x36, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x90, 0xe6, 0xad, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x81, 0x14, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0xc1, 0xb5, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x23, 0xe8, 0xd6, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x50, 0xd8, 0xbf, 0xaf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xef, 0xde, 0x06, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0x30, 0x61, 0x19, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0x7e, 0x35, 0x6f, 0xaa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0x22, 0x98, 0xd1, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0x08, 0x98, 0x4c, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x34, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x34, 0x9b, 0xa7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0xa0, 0xbb, 0xac, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x30, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x30, 0x55, 0xb3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0xa1, 0x13, 0x28, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x33, 0x90, 0xa9, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x31, 0x00, 0xdc, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0xf1, 0x5e, 0x8e, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x06, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x32, 0x00, 0xed, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x72, 0x21, 0x53, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0xbd, 0xad, 0xca, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x2c, 0xec, 0xeb, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x33, 0x00, 0x70, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x33, 0xfe, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x36, 0x00, 0xd1, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x76, 0xdd, 0xe8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x31, 0x8c, 0x8e, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x8d, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x0d, 0xf7, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x26, 0x90, 0x9e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" diff --git a/tests/MC/Mips/valid-mips4.txt.yaml b/tests/MC/Mips/valid-mips4.txt.yaml new file mode 100644 index 000000000..9fb9a5415 --- /dev/null +++ b/tests/MC/Mips/valid-mips4.txt.yaml @@ -0,0 +1,2490 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $5, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x1c, 0xe0, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movf $gp, $8, $fcc7" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x30, 0x18, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movn $3, $17, $16" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0x95, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movt $zero, $20, $fcc5" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xc9, 0x28, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movz $5, $22, $9" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x3a, 0x00, 0x27, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "xori $zero, $16, 10002" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x04, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1f $fcc1, 8" + + - + input: + bytes: [ 0x45, 0x05, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1t $fcc1, 8" + + - + input: + bytes: [ 0x45, 0x1e, 0x00, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1fl $fcc7, 32" + + - + input: + bytes: [ 0x45, 0x1f, 0x00, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1tl $fcc7, 32" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xea, 0xe5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.l.s $f11, $f29" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x03, 0x3e, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movz.s $f25, $f7, $3" + + - + input: + bytes: [ 0x46, 0x05, 0x17, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movt.s $f30, $f2, $fcc1" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x17, 0x03, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movn.s $f12, $f0, $23" + + - + input: + bytes: [ 0x46, 0x18, 0x2d, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movf.s $f23, $f5, $fcc6" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x7e, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.l.d $f24, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x21, 0x10, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movt.d $f0, $f2, $fcc0" + + - + input: + bytes: [ 0x46, 0x29, 0xeb, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movz.d $f12, $f29, $9" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x34, 0x59, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movf.d $f6, $f11, $fcc5" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xae, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movn.d $f27, $f21, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x4c, 0x20, 0x01, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ldxc1 $f4, $zero($1)" + + - + input: + bytes: [ 0x4c, 0x21, 0x00, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "msub.s $f0, $f1, $f0, $f1" + + - + input: + bytes: [ 0x4d, 0xca, 0x58, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0x4e, 0x20, 0x3e, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "nmsub.d $f26, $f17, $f7, $f0" + + - + input: + bytes: [ 0x4f, 0x4c, 0x98, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x4f, 0xd1, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0xa1, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0xbf, 0x00, 0xe2, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cache 0, -7652($24)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x20, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "pref 0, 0($1)" + + - + input: + bytes: [ 0xcc, 0xa1, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "pref 1, 8($5)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "recip.d $f19, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0xd6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "rsqrt.d $f3, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" diff --git a/tests/MC/Mips/valid-mips64-el.txt.yaml b/tests/MC/Mips/valid-mips64-el.txt.yaml new file mode 100644 index 000000000..9d89955c8 --- /dev/null +++ b/tests/MC/Mips/valid-mips64-el.txt.yaml @@ -0,0 +1,2420 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x25, 0x90, 0xd2, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x24, 0x80, 0x30, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x00, 0x50, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x50, 0xa4, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x39, 0x6c, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x39, 0x6c, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x5f, 0xec, 0x6f, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0xea, 0x11, 0xce, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xf8, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x1b, 0x90, 0x3d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xb9, 0xef, 0x18, 0x6b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6a, 0x89, 0x8e, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x70, 0xc6, 0xe0, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0xc5, 0x04, 0xb6, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "luxc1 $f19, $22($21)" + + - + input: + bytes: [ 0xea, 0xa1, 0x73, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0x00, 0x03, 0xd1, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x25, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x2d, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x09, 0x58, 0xca, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x0d, 0x60, 0xbb, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "suxc1 $f12, $27($13)" + + - + input: + bytes: [ 0x08, 0x98, 0x4c, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3b, 0xe8, 0x05, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x02, 0x00, 0x61, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0x04, 0x00, 0x43, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xca, 0x23, 0xc8, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xcd, 0x7c, 0x4b, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x2d, 0xd0, 0x2b, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x1e, 0x00, 0x56, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x1f, 0x00, 0x38, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x00, 0x70, 0x22, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x00, 0x28, 0xb7, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x1c, 0x00, 0x7a, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x1d, 0x00, 0xed, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x78, 0x1c, 0x18, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x14, 0xe0, 0x1b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0xbb, 0x0f, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x17, 0x08, 0xc1, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x3a, 0x56, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x16, 0xe0, 0xea, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x2f, 0xe0, 0x78, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0xcd, 0xc4, 0x3b, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x01, 0x00, 0x01, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x2e, 0xf9, 0x63, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x01, 0x00, 0x1f, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0xc9, 0xc4, 0x3a, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0x76, 0x0f, 0x1a, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x81, 0x00, 0x42, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $2($10)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" diff --git a/tests/MC/Mips/valid-mips64-xfail.txt.yaml b/tests/MC/Mips/valid-mips64-xfail.txt.yaml new file mode 100644 index 000000000..4fb4de011 --- /dev/null +++ b/tests/MC/Mips/valid-mips64-xfail.txt.yaml @@ -0,0 +1,150 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" diff --git a/tests/MC/Mips/valid-mips64.txt.yaml b/tests/MC/Mips/valid-mips64.txt.yaml new file mode 100644 index 000000000..27056a05a --- /dev/null +++ b/tests/MC/Mips/valid-mips64.txt.yaml @@ -0,0 +1,4350 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $5, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x01, 0x0f, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x18, 0x1c, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x00, 0x1c, 0x56, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x2b, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x38, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7a, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x02, 0xea, 0xe0, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x02, 0xed, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x03, 0x1b, 0xe0, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x56, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x03, 0x78, 0xe0, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xc1, 0x08, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x01, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x3c, 0x1f, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x38, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x40, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x22, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xb7, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x46, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.l.s $f26, $f8" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "recip.d $f19, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0xd6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rsqrt.d $f3, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x48, 0x20, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc2 $zero, $10, 0" + + - + input: + bytes: [ 0x48, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc2 $4, $10, 0" + + - + input: + bytes: [ 0x4d, 0x0c, 0xe0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "madd.d $f0, $f8, $f28, $f12" + + - + input: + bytes: [ 0x4d, 0xbb, 0x0d, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "madd.s $f23, $f13, $f1, $f27" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x42, 0x00, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $2($10)" + + - + input: + bytes: [ 0x4d, 0xbb, 0x60, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "suxc1 $f12, $27($13)" + + - + input: + bytes: [ 0x4d, 0xca, 0x58, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0xb6, 0x04, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "luxc1 $f19, $22($21)" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0x4c, 0x98, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x4f, 0xd1, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x62, 0x9d, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x65, 0x6f, 0xec, 0x5f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0x65, 0xce, 0x11, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x67, 0x4b, 0x7c, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x67, 0xbd, 0xff, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $sp, $sp, -32" + + - + input: + bytes: [ 0x6b, 0x18, 0xef, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6e, 0x8e, 0x89, 0x6a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xd2, 0x90, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x73, 0x30, 0x80, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0x3b, 0xc4, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x9c, 0x63, 0xf9, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x9c, 0x73, 0xa1, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0x3a, 0xc4, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd3, 0xe0, 0xc6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xd9, 0x03, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldc2 $3, 9162($8)" + + - + input: + bytes: [ 0xdc, 0x1a, 0x0f, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0xde, 0x3d, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xf8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdc2 $9, 9158($7)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfc, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" diff --git a/tests/MC/Mips/valid-mips64r2-el.txt.yaml b/tests/MC/Mips/valid-mips64r2-el.txt.yaml new file mode 100644 index 000000000..1e39241a7 --- /dev/null +++ b/tests/MC/Mips/valid-mips64r2-el.txt.yaml @@ -0,0 +1,5360 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x00, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x25, 0x90, 0xd2, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x24, 0x80, 0x30, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x00, 0x50, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x50, 0xa4, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0xa4, 0x18, 0x0e, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x64, 0x11, 0x1d, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x39, 0x6c, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x39, 0x6c, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x5f, 0xec, 0x6f, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0xea, 0x11, 0xce, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0xfa, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0xfa, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x56, 0x08, 0xee, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x1b, 0x90, 0x3d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xb9, 0xef, 0x18, 0x6b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6a, 0x89, 0x8e, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x70, 0xc6, 0xe0, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0xea, 0xa1, 0x73, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x25, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x2d, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x02, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x01, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0xcd, 0x7c, 0x4b, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x2d, 0xd0, 0x2b, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x1e, 0x00, 0x56, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x1f, 0x00, 0x38, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x00, 0x70, 0x22, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x00, 0x28, 0xb7, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x1c, 0x00, 0x7a, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x1d, 0x00, 0xed, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x78, 0x1c, 0x18, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x14, 0xe0, 0x1b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0xbb, 0x0f, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x17, 0x08, 0xc1, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x3a, 0x56, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x16, 0xe0, 0xea, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x2f, 0xe0, 0x78, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0xcd, 0xc4, 0x3b, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x01, 0x00, 0x01, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x2e, 0xf9, 0x63, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x01, 0x00, 0x1f, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0xc9, 0xc4, 0x3a, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0x76, 0x0f, 0x1a, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0x25, 0x48, 0x09, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $9, $24" + + - + input: + bytes: [ 0x24, 0xd0, 0x3a, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $26, $9" + + - + input: + bytes: [ 0x43, 0xf7, 0x87, 0x7f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dext $7, $gp, 29, 31" + + - + input: + bytes: [ 0xc7, 0x7b, 0x94, 0x7f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dins $20, $gp, 15, 1" + + - + input: + bytes: [ 0xa4, 0x38, 0x1c, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $7, $gp" + + - + input: + bytes: [ 0x64, 0x19, 0x0e, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $3, $14" + + - + input: + bytes: [ 0xba, 0xa1, 0x3b, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $20, $27, 6" + + - + input: + bytes: [ 0x56, 0xc0, 0xb7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $24, $23, $5" + + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x00, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x25, 0x90, 0xd2, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x24, 0x80, 0x30, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x00, 0x50, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x50, 0xa4, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0xa4, 0x18, 0x0e, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x64, 0x11, 0x1d, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x39, 0x6c, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x39, 0x6c, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x5f, 0xec, 0x6f, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0xea, 0x11, 0xce, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0xfa, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0xfa, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x56, 0x08, 0xee, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x1b, 0x90, 0x3d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xb9, 0xef, 0x18, 0x6b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6a, 0x89, 0x8e, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x70, 0xc6, 0xe0, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0xea, 0xa1, 0x73, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x25, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x2d, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x02, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x01, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0xcd, 0x7c, 0x4b, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x2d, 0xd0, 0x2b, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x1e, 0x00, 0x56, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x1f, 0x00, 0x38, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x00, 0x70, 0x22, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x00, 0x28, 0xb7, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x1c, 0x00, 0x7a, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x1d, 0x00, 0xed, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x78, 0x1c, 0x18, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x14, 0xe0, 0x1b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0xbb, 0x0f, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x17, 0x08, 0xc1, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x3a, 0x56, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x16, 0xe0, 0xea, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x2f, 0xe0, 0x78, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0xcd, 0xc4, 0x3b, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x01, 0x00, 0x01, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x2e, 0xf9, 0x63, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x01, 0x00, 0x1f, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0xc9, 0xc4, 0x3a, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0x76, 0x0f, 0x1a, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0x25, 0x48, 0x09, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $9, $24" + + - + input: + bytes: [ 0x24, 0xd0, 0x3a, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $26, $9" + + - + input: + bytes: [ 0x43, 0xf7, 0x87, 0x7f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dext $7, $gp, 29, 31" + + - + input: + bytes: [ 0xc7, 0x7b, 0x94, 0x7f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dins $20, $gp, 15, 1" + + - + input: + bytes: [ 0xa4, 0x38, 0x1c, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $7, $gp" + + - + input: + bytes: [ 0x64, 0x19, 0x0e, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $3, $14" + + - + input: + bytes: [ 0xba, 0xa1, 0x3b, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $20, $27, 6" + + - + input: + bytes: [ 0x56, 0xc0, 0xb7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $24, $23, $5" diff --git a/tests/MC/Mips/valid-mips64r2.txt.yaml b/tests/MC/Mips/valid-mips64r2.txt.yaml new file mode 100644 index 000000000..855dd869d --- /dev/null +++ b/tests/MC/Mips/valid-mips64r2.txt.yaml @@ -0,0 +1,9440 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $5, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x01, 0x0f, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x18, 0x1c, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x00, 0x1c, 0x56, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x2b, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3b, 0xa1, 0xba ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $20, $27, 6" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xb7, 0xc0, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $24, $23, $5" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x38, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7a, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x01, 0xee, 0x08, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x02, 0xea, 0xe0, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x02, 0xed, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x03, 0x1b, 0xe0, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x56, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x03, 0x78, 0xe0, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xc1, 0x08, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x7f, 0x47, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "synci 18368($3)" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x01, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x3c, 0x1f, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x38, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x40, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x22, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xb7, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x46, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f26, $f8" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x48, 0x20, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc2 $zero, $10, 0" + + - + input: + bytes: [ 0x48, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc2 $4, $10, 0" + + - + input: + bytes: [ 0x4d, 0x0c, 0xe0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.d $f0, $f8, $f28, $f12" + + - + input: + bytes: [ 0x4d, 0xbb, 0x0d, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.s $f23, $f13, $f1, $f27" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x42, 0x00, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $2($10)" + + - + input: + bytes: [ 0x4d, 0xbb, 0x60, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "suxc1 $f12, $27($13)" + + - + input: + bytes: [ 0x4d, 0xca, 0x58, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0xb6, 0x04, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "luxc1 $f19, $22($21)" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0x4c, 0x98, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x4f, 0xd1, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x62, 0x9d, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x65, 0x6f, 0xec, 0x5f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0x65, 0xce, 0x11, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x67, 0x4b, 0x7c, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x67, 0xbd, 0xff, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $sp, $sp, -32" + + - + input: + bytes: [ 0x6b, 0x18, 0xef, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6e, 0x8e, 0x89, 0x6a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xd2, 0x90, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x71, 0x3a, 0xd0, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $26, $9" + + - + input: + bytes: [ 0x73, 0x09, 0x48, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $9, $24" + + - + input: + bytes: [ 0x73, 0x30, 0x80, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7c, 0x0e, 0x18, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x7c, 0x0e, 0x19, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $3, $14" + + - + input: + bytes: [ 0x7c, 0x1c, 0x38, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $7, $gp" + + - + input: + bytes: [ 0x7c, 0x1d, 0x11, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x7f, 0x87, 0xf7, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dext $7, $gp, 29, 31" + + - + input: + bytes: [ 0x7f, 0x94, 0x7b, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dins $20, $gp, 15, 1" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0x3b, 0xc4, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x9c, 0x63, 0xf9, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x9c, 0x73, 0xa1, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0x3a, 0xc4, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd3, 0xe0, 0xc6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xd9, 0x03, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc2 $3, 9162($8)" + + - + input: + bytes: [ 0xdc, 0x1a, 0x0f, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0xde, 0x3d, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xf8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc2 $9, 9158($7)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfc, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x01, 0x0f, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x18, 0x1c, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x00, 0x1c, 0x56, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x2b, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3b, 0xa1, 0xba ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $20, $27, 6" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xb7, 0xc0, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $24, $23, $5" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x38, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7a, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x01, 0xee, 0x08, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x02, 0xea, 0xe0, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x02, 0xed, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x03, 0x1b, 0xe0, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x56, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x03, 0x78, 0xe0, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xc1, 0x08, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x7f, 0x47, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "synci 18368($3)" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x01, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x3c, 0x1f, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x38, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x40, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x22, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xb7, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x46, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f26, $f8" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x48, 0x20, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc2 $zero, $10, 0" + + - + input: + bytes: [ 0x48, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc2 $4, $10, 0" + + - + input: + bytes: [ 0x4d, 0x0c, 0xe0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.d $f0, $f8, $f28, $f12" + + - + input: + bytes: [ 0x4d, 0xbb, 0x0d, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.s $f23, $f13, $f1, $f27" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x42, 0x00, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $2($10)" + + - + input: + bytes: [ 0x4d, 0xbb, 0x60, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "suxc1 $f12, $27($13)" + + - + input: + bytes: [ 0x4d, 0xca, 0x58, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0xb6, 0x04, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "luxc1 $f19, $22($21)" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0x4c, 0x98, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x4f, 0xd1, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x62, 0x9d, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x65, 0x6f, 0xec, 0x5f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0x65, 0xce, 0x11, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x67, 0x4b, 0x7c, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x67, 0xbd, 0xff, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $sp, $sp, -32" + + - + input: + bytes: [ 0x6b, 0x18, 0xef, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6e, 0x8e, 0x89, 0x6a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xd2, 0x90, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x71, 0x3a, 0xd0, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $26, $9" + + - + input: + bytes: [ 0x73, 0x09, 0x48, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $9, $24" + + - + input: + bytes: [ 0x73, 0x30, 0x80, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7c, 0x0e, 0x18, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x7c, 0x0e, 0x19, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $3, $14" + + - + input: + bytes: [ 0x7c, 0x1c, 0x38, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $7, $gp" + + - + input: + bytes: [ 0x7c, 0x1d, 0x11, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x7f, 0x87, 0xf7, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dext $7, $gp, 29, 31" + + - + input: + bytes: [ 0x7f, 0x94, 0x7b, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dins $20, $gp, 15, 1" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0x3b, 0xc4, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x9c, 0x63, 0xf9, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x9c, 0x73, 0xa1, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0x3a, 0xc4, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd3, 0xe0, 0xc6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xd9, 0x03, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc2 $3, 9162($8)" + + - + input: + bytes: [ 0xdc, 0x1a, 0x0f, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0xde, 0x3d, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xf8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc2 $9, 9158($7)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfc, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" diff --git a/tests/MC/Mips/valid-mips64r3-el.txt.yaml b/tests/MC/Mips/valid-mips64r3-el.txt.yaml new file mode 100644 index 000000000..cc69d2d7c --- /dev/null +++ b/tests/MC/Mips/valid-mips64r3-el.txt.yaml @@ -0,0 +1,2380 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x00, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x25, 0x90, 0xd2, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x24, 0x80, 0x30, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x00, 0x50, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x50, 0xa4, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0xa4, 0x18, 0x0e, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x64, 0x11, 0x1d, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x39, 0x6c, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x39, 0x6c, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x5f, 0xec, 0x6f, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0xea, 0x11, 0xce, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0xfa, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0xfa, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x56, 0x08, 0xee, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xf8, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x1b, 0x90, 0x3d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xb9, 0xef, 0x18, 0x6b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6a, 0x89, 0x8e, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x70, 0xc6, 0xe0, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0xea, 0xa1, 0x73, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x25, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x2d, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x02, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x01, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" diff --git a/tests/MC/Mips/valid-mips64r3.txt.yaml b/tests/MC/Mips/valid-mips64r3.txt.yaml new file mode 100644 index 000000000..3b9c3c607 --- /dev/null +++ b/tests/MC/Mips/valid-mips64r3.txt.yaml @@ -0,0 +1,4740 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $5, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x01, 0x0f, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x18, 0x1c, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x00, 0x1c, 0x56, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x2b, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3b, 0xa1, 0xba ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr $20, $27, 6" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xb7, 0xc0, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotrv $24, $23, $5" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x38, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7a, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x01, 0xee, 0x08, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x02, 0xea, 0xe0, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x02, 0xed, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x03, 0x1b, 0xe0, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x56, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x03, 0x78, 0xe0, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xc1, 0x08, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x7f, 0x47, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "synci 18368($3)" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3a, 0x00, 0x3a, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "xori $zero, $16, 14881" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x01, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x3c, 0x1f, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x38, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x40, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x22, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xb7, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x46, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f26, $f8" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x48, 0x20, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmfc2 $zero, $10, 0" + + - + input: + bytes: [ 0x48, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmtc2 $4, $10, 0" + + - + input: + bytes: [ 0x4d, 0x0c, 0xe0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd.d $f0, $f8, $f28, $f12" + + - + input: + bytes: [ 0x4d, 0xbb, 0x0d, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd.s $f23, $f13, $f1, $f27" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x42, 0x00, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $2($10)" + + - + input: + bytes: [ 0x4d, 0xbb, 0x60, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "suxc1 $f12, $27($13)" + + - + input: + bytes: [ 0x4d, 0xca, 0x58, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0xb6, 0x04, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "luxc1 $f19, $22($21)" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0x4c, 0x98, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x4f, 0xd1, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x62, 0x9d, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x65, 0x6f, 0xec, 0x5f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0x65, 0xce, 0x11, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x67, 0x4b, 0x7c, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x67, 0xbd, 0xff, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $sp, $sp, -32" + + - + input: + bytes: [ 0x6b, 0x18, 0xef, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6e, 0x8e, 0x89, 0x6a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xd2, 0x90, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x71, 0x3a, 0xd0, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dclz $26, $9" + + - + input: + bytes: [ 0x73, 0x09, 0x48, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dclo $9, $24" + + - + input: + bytes: [ 0x73, 0x30, 0x80, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7c, 0x0e, 0x18, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x7c, 0x0e, 0x19, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dshd $3, $14" + + - + input: + bytes: [ 0x7c, 0x1c, 0x38, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsbh $7, $gp" + + - + input: + bytes: [ 0x7c, 0x1d, 0x11, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x7f, 0x87, 0xf7, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dext $7, $gp, 29, 31" + + - + input: + bytes: [ 0x7f, 0x94, 0x7b, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dins $20, $gp, 15, 1" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0x3b, 0xc4, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x9c, 0x63, 0xf9, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x9c, 0x73, 0xa1, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0x3a, 0xc4, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd3, 0xe0, 0xc6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xd9, 0x03, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldc2 $3, 9162($8)" + + - + input: + bytes: [ 0xdc, 0x1a, 0x0f, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0xde, 0x3d, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xf8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdc2 $9, 9158($7)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfc, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" diff --git a/tests/MC/Mips/valid-mips64r5-el.txt.yaml b/tests/MC/Mips/valid-mips64r5-el.txt.yaml new file mode 100644 index 000000000..3aa307a40 --- /dev/null +++ b/tests/MC/Mips/valid-mips64r5-el.txt.yaml @@ -0,0 +1,2380 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x00, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x25, 0x90, 0xd2, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x24, 0x80, 0x30, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x00, 0x50, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x50, 0xa4, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0xa4, 0x18, 0x0e, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x64, 0x11, 0x1d, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x39, 0x6c, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x39, 0x6c, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x5f, 0xec, 0x6f, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0xea, 0x11, 0xce, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0xfa, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0xfa, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x56, 0x08, 0xee, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xf8, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x1b, 0x90, 0x3d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xb9, 0xef, 0x18, 0x6b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6a, 0x89, 0x8e, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x70, 0xc6, 0xe0, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0xea, 0xa1, 0x73, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x25, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x2d, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x02, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x01, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" diff --git a/tests/MC/Mips/valid-mips64r5.txt.yaml b/tests/MC/Mips/valid-mips64r5.txt.yaml new file mode 100644 index 000000000..f1788e926 --- /dev/null +++ b/tests/MC/Mips/valid-mips64r5.txt.yaml @@ -0,0 +1,4750 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $5, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x01, 0x0f, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x18, 0x1c, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x00, 0x1c, 0x56, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x2b, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3b, 0xa1, 0xba ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr $20, $27, 6" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xb7, 0xc0, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotrv $24, $23, $5" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x38, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7a, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x01, 0xee, 0x08, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x02, 0xea, 0xe0, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x02, 0xed, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x03, 0x1b, 0xe0, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x56, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x03, 0x78, 0xe0, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xc1, 0x08, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x7f, 0x47, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "synci 18368($3)" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x01, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x3c, 0x1f, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x38, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x40, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x22, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xb7, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x46, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f26, $f8" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "eretnc" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x48, 0x20, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfc2 $zero, $10, 0" + + - + input: + bytes: [ 0x48, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtc2 $4, $10, 0" + + - + input: + bytes: [ 0x4d, 0x0c, 0xe0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd.d $f0, $f8, $f28, $f12" + + - + input: + bytes: [ 0x4d, 0xbb, 0x0d, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd.s $f23, $f13, $f1, $f27" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x42, 0x00, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $2($10)" + + - + input: + bytes: [ 0x4d, 0xbb, 0x60, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "suxc1 $f12, $27($13)" + + - + input: + bytes: [ 0x4d, 0xca, 0x58, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0xb6, 0x04, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "luxc1 $f19, $22($21)" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0x4c, 0x98, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x4f, 0xd1, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x62, 0x9d, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x65, 0x6f, 0xec, 0x5f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0x65, 0xce, 0x11, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x67, 0x4b, 0x7c, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x67, 0xbd, 0xff, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $sp, $sp, -32" + + - + input: + bytes: [ 0x6b, 0x18, 0xef, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6e, 0x8e, 0x89, 0x6a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xd2, 0x90, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x71, 0x3a, 0xd0, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dclz $26, $9" + + - + input: + bytes: [ 0x73, 0x09, 0x48, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dclo $9, $24" + + - + input: + bytes: [ 0x73, 0x30, 0x80, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7c, 0x0e, 0x18, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x7c, 0x0e, 0x19, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dshd $3, $14" + + - + input: + bytes: [ 0x7c, 0x1c, 0x38, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsbh $7, $gp" + + - + input: + bytes: [ 0x7c, 0x1d, 0x11, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x7f, 0x87, 0xf7, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dext $7, $gp, 29, 31" + + - + input: + bytes: [ 0x7f, 0x94, 0x7b, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dins $20, $gp, 15, 1" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0x3b, 0xc4, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x9c, 0x63, 0xf9, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x9c, 0x73, 0xa1, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0x3a, 0xc4, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd3, 0xe0, 0xc6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldc2 $7, 13344($zero)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xd9, 0x03, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldc2 $3, 9162($8)" + + - + input: + bytes: [ 0xdc, 0x1a, 0x0f, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0xde, 0x3d, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xf8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdc2 $9, 9158($7)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfc, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" diff --git a/tests/MC/Mips/valid-mips64r6-el.txt.yaml b/tests/MC/Mips/valid-mips64r6-el.txt.yaml new file mode 100644 index 000000000..46b8921b2 --- /dev/null +++ b/tests/MC/Mips/valid-mips64r6-el.txt.yaml @@ -0,0 +1,1950 @@ +test_cases: + - + input: + bytes: [ 0x0a, 0x00, 0x29, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0xa0, 0x22, 0x43, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "align $4, $2, $3, 2" + + - + input: + bytes: [ 0x38, 0x00, 0x7f, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "aluipc $3, 56" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0xe9, 0xff, 0x43, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "aui $3, $2, 65513" + + - + input: + bytes: [ 0xff, 0xff, 0x7e, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "auipc $3, -1" + + - + input: + bytes: [ 0x9c, 0x14, 0x11, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0xb9, 0x96, 0x37, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "balc 14572264" + + - + input: + bytes: [ 0xb9, 0x96, 0x37, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc 14572264" + + - + input: + bytes: [ 0x02, 0x00, 0x20, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f0, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x3f, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f31, 12" + + - + input: + bytes: [ 0x02, 0x00, 0xa0, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1nez $f0, 12" + + - + input: + bytes: [ 0x02, 0x00, 0xbf, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1nez $f31, 12" + + - + input: + bytes: [ 0x03, 0x00, 0x20, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2eqz $0, 16" + + - + input: + bytes: [ 0x03, 0x00, 0x3f, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2eqz $31, 16" + + - + input: + bytes: [ 0x03, 0x00, 0xa0, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2nez $0, 16" + + - + input: + bytes: [ 0x03, 0x00, 0xbf, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2nez $31, 16" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqc $5, $6, 264" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqzalc $2, 1340" + + - + input: + bytes: [ 0x91, 0x46, 0xa0, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqzc $5, 72264" + + - + input: + bytes: [ 0xfb, 0xff, 0x5f, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqzc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x43, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x43, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x43, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x43, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x42, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x42, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa5, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa5, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezc $5, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x02, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x05, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x05, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, -16" + + - + input: + bytes: [ 0x20, 0x20, 0x02, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bitswap $4, $2" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x02, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x05, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x05, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezc $5, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa6, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa6, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x42, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x42, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa5, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa5, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzc $5, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnec $5, $6, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x43, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnec $2, $3, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnezalc $2, 1340" + + - + input: + bytes: [ 0x91, 0x46, 0xa0, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnezc $5, 72264" + + - + input: + bytes: [ 0xfb, 0xff, 0x5f, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnezc $2, -16" + + - + input: + bytes: [ 0x02, 0x00, 0x40, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $2, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x82, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $4, $2, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $zero, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x40, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $2, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x82, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $4, $2, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $zero, $zero, 12" + + - + input: + bytes: [ 0x25, 0x04, 0xa1, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0x9b, 0x20, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "class.d $f2, $f4" + + - + input: + bytes: [ 0x9b, 0x20, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "class.s $f2, $f4" + + - + input: + bytes: [ 0x51, 0x58, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "clo $11, $5" + + - + input: + bytes: [ 0x50, 0xe8, 0x80, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "clz $sp, $gp" + + - + input: + bytes: [ 0x80, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.af.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x80, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.af.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x82, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.eq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x82, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.eq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x86, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.le.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x86, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.le.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x84, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.lt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x84, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.lt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x88, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.saf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x88, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.saf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8a, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.seq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8a, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.seq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8e, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sle.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8e, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sle.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8c, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.slt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8c, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.slt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8b, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8b, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8f, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8f, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8d, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8d, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x89, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sun.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x89, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sun.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x83, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x83, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x87, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x87, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x85, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x85, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x81, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.un.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x81, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.un.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x64, 0x23, 0x43, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dalign $4, $2, $3, 5" + + - + input: + bytes: [ 0x34, 0x12, 0x43, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "daui $3, $2, 4660" + + - + input: + bytes: [ 0x24, 0x20, 0x02, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dbitswap $4, $2" + + - + input: + bytes: [ 0x53, 0x90, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x52, 0x80, 0x20, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x9e, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ddiv $2, $3, $4" + + - + input: + bytes: [ 0x9f, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ddivu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x9a, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "div $2, $3, $4" + + - + input: + bytes: [ 0x9b, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "divu $2, $3, $4" + + - + input: + bytes: [ 0xd5, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dlsa $2, $3, $4, 4" + + - + input: + bytes: [ 0x00, 0x50, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0xde, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmod $2, $3, $4" + + - + input: + bytes: [ 0xdf, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmodu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x50, 0xa4, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0xdc, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmuh $2, $3, $4" + + - + input: + bytes: [ 0xdd, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmuhu $2, $3, $4" + + - + input: + bytes: [ 0x9c, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmul $2, $3, $4" + + - + input: + bytes: [ 0x9d, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmulu $2, $3, $4" + + - + input: + bytes: [ 0x24, 0x00, 0x71, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dvp $17" + + - + input: + bytes: [ 0x24, 0x00, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dvp $zero" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x04, 0x00, 0x70, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "evp $16" + + - + input: + bytes: [ 0x04, 0x00, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "evp $zero" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0x00, 0x19, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jalrc $25" + + - + input: + bytes: [ 0x00, 0x01, 0x05, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jialc $5, 256" + + - + input: + bytes: [ 0x00, 0x01, 0x05, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jic $5, 256" + + - + input: + bytes: [ 0x00, 0x00, 0x1b, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jrc $27" + + - + input: + bytes: [ 0x09, 0x04, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jr.hb $4" + + - + input: + bytes: [ 0x19, 0x00, 0x80, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lapc $4, 100" + + - + input: + bytes: [ 0x43, 0x0d, 0xc8, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ldc2 $8, -701($1)" + + - + input: + bytes: [ 0x48, 0x3c, 0x58, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ldpc $2, 123456" + + - + input: + bytes: [ 0xb6, 0xb3, 0x42, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ll $2, -153($18)" + + - + input: + bytes: [ 0x37, 0x38, 0xe0, 0x7f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lld $zero, 112($ra)" + + - + input: + bytes: [ 0xc5, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lsa $2, $3, $4, 4" + + - + input: + bytes: [ 0xb7, 0x34, 0x52, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0x43, 0x00, 0x48, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lwpc $2, 268" + + - + input: + bytes: [ 0x43, 0x00, 0x50, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lwupc $2, 268" + + - + input: + bytes: [ 0x98, 0x18, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maddf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x98, 0x18, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maddf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x1f, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maxa.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x1f, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maxa.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x1c, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "min.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x1c, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "min.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x1e, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mina.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x1e, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mina.s $f0, $f2, $f4" + + - + input: + bytes: [ 0xda, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mod $2, $3, $4" + + - + input: + bytes: [ 0xdb, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "modu $2, $3, $4" + + - + input: + bytes: [ 0x25, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x2d, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x99, 0x18, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "msubf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x99, 0x18, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "msubf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0xd8, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "muh $2, $3, $4" + + - + input: + bytes: [ 0xd9, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "muhu $2, $3, $4" + + - + input: + bytes: [ 0x98, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mul $2, $3, $4" + + - + input: + bytes: [ 0x99, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mulu $2, $3, $4" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x35, 0x04, 0xa1, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "pref 1, 8($5)" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x9a, 0x20, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rint.d $f2, $f4" + + - + input: + bytes: [ 0x9a, 0x20, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rint.s $f2, $f4" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x26, 0xec, 0x6f, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sc $15, -40($19)" + + - + input: + bytes: [ 0xa7, 0xe6, 0xaf, 0x7f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "scd $15, -51($sp)" + + - + input: + bytes: [ 0x0e, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sdbbp" + + - + input: + bytes: [ 0x8e, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sdbbp 34" + + - + input: + bytes: [ 0x75, 0x92, 0xf4, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sdc2 $20, 629($18)" + + - + input: + bytes: [ 0x10, 0x08, 0x22, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sel.d $f0, $f1, $f2" + + - + input: + bytes: [ 0x10, 0x08, 0x02, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sel.s $f0, $f1, $f2" + + - + input: + bytes: [ 0x35, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "seleqz $2, $3, $4" + + - + input: + bytes: [ 0x14, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "seleqz.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x14, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "seleqz.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x37, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "selnez $2, $3, $4" + + - + input: + bytes: [ 0x17, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "selnez.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x17, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "selnez.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x30, 0x81, 0x79, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "swc2 $25, 304($16)" + + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x4f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sync 1" + + - + input: + bytes: [ 0x34, 0x9b, 0xa7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x34, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x30, 0x55, 0xb3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x30, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0xf1, 0x5e, 0x8e, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x31, 0x00, 0xdc, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x32, 0x00, 0xed, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x72, 0x21, 0x53, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x33, 0x00, 0x70, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x33, 0xfe, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x36, 0x00, 0xd1, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x76, 0xdd, 0xe8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x05, 0x00, 0x17, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sigrie 5" diff --git a/tests/MC/Mips/valid-mips64r6.txt.yaml b/tests/MC/Mips/valid-mips64r6.txt.yaml new file mode 100644 index 000000000..d30f308d3 --- /dev/null +++ b/tests/MC/Mips/valid-mips64r6.txt.yaml @@ -0,0 +1,2040 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sdbbp" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sync 1" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x08, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sdbbp 34" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "seleqz $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "selnez $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mul $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mulu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "div $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "divu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmul $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmulu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ddiv $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ddivu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lsa $2, $3, $4, 4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dlsa $2, $3, $4, 4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "muh $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "muhu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mod $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "modu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmuh $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xdd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmuhu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmod $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xdf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmodu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x80, 0x04, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jr.hb $4" + + - + input: + bytes: [ 0xd8, 0x1b, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jrc $27" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0xf8, 0x19, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jalrc $25" + + - + input: + bytes: [ 0x00, 0xa0, 0x58, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "clo $11, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0x90, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x80, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x03, 0x80, 0xe8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "clz $sp, $gp" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x66, 0x56, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dahi $3, $3, 22136" + + - + input: + bytes: [ 0x04, 0x7e, 0xab, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dati $3, $3, 43981" + + - + input: + bytes: [ 0x18, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezalc $2, 1340" + + - + input: + bytes: [ 0x18, 0x02, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezalc $2, -16" + + - + input: + bytes: [ 0x18, 0x42, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, 1340" + + - + input: + bytes: [ 0x18, 0x42, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, -16" + + - + input: + bytes: [ 0x18, 0x43, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, 264" + + - + input: + bytes: [ 0x18, 0x43, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, -16" + + - + input: + bytes: [ 0x1c, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, 1340" + + - + input: + bytes: [ 0x1c, 0x02, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, -16" + + - + input: + bytes: [ 0x1c, 0x42, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, 1340" + + - + input: + bytes: [ 0x1c, 0x42, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, -16" + + - + input: + bytes: [ 0x1c, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, 264" + + - + input: + bytes: [ 0x1c, 0xa6, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, -16" + + - + input: + bytes: [ 0x20, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $zero, $zero, 12" + + - + input: + bytes: [ 0x20, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqzalc $2, 1340" + + - + input: + bytes: [ 0x20, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $2, $zero, 12" + + - + input: + bytes: [ 0x20, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $4, $2, 12" + + - + input: + bytes: [ 0x20, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqc $5, $6, 264" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x3c, 0x43, 0xff, 0xe9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "aui $3, $2, 65513" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 3" + + - + input: + bytes: [ 0x40, 0x38, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x40, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dvp $zero" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "evp $zero" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x70, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "evp $16" + + - + input: + bytes: [ 0x41, 0x71, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dvp $17" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x45, 0x20, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f0, 12" + + - + input: + bytes: [ 0x45, 0x3f, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f31, 12" + + - + input: + bytes: [ 0x45, 0xa0, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1nez $f0, 12" + + - + input: + bytes: [ 0x45, 0xbf, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1nez $f31, 12" + + - + input: + bytes: [ 0x46, 0x00, 0x20, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rint.s $f2, $f4" + + - + input: + bytes: [ 0x46, 0x00, 0x20, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "class.s $f2, $f4" + + - + input: + bytes: [ 0x46, 0x02, 0x08, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sel.s $f0, $f1, $f2" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "seleqz.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "selnez.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "min.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "max.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mina.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maxa.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x18, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maddf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x18, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "msubf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x20, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rint.d $f2, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x20, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "class.d $f2, $f4" + + - + input: + bytes: [ 0x46, 0x22, 0x08, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sel.d $f0, $f1, $f2" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "seleqz.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "selnez.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "min.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "max.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mina.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maxa.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x18, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maddf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x18, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "msubf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.af.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.un.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.eq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x83 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.lt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.le.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.saf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sun.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.seq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.slt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sle.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.af.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.un.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.eq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x83 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.lt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.le.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.saf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sun.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.seq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.slt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sle.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "eretnc" + + - + input: + bytes: [ 0x49, 0x20, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2eqz $0, 16" + + - + input: + bytes: [ 0x49, 0x3f, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2eqz $31, 16" + + - + input: + bytes: [ 0x49, 0x52, 0x34, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0x49, 0x79, 0x81, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "swc2 $25, 304($16)" + + - + input: + bytes: [ 0x49, 0xa0, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2nez $0, 16" + + - + input: + bytes: [ 0x49, 0xbf, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2nez $31, 16" + + - + input: + bytes: [ 0x49, 0xc8, 0x0d, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ldc2 $8, -701($1)" + + - + input: + bytes: [ 0x49, 0xf4, 0x92, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sdc2 $20, 629($18)" + + - + input: + bytes: [ 0x58, 0x05, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezc $5, 264" + + - + input: + bytes: [ 0x58, 0x05, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezc $5, -16" + + - + input: + bytes: [ 0x58, 0x43, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, 264" + + - + input: + bytes: [ 0x58, 0x43, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, -16" + + - + input: + bytes: [ 0x58, 0xa5, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezc $5, 264" + + - + input: + bytes: [ 0x58, 0xa5, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezc $5, -16" + + - + input: + bytes: [ 0x5c, 0x05, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, 264" + + - + input: + bytes: [ 0x5c, 0x05, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, -16" + + - + input: + bytes: [ 0x5c, 0xa5, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzc $5, 264" + + - + input: + bytes: [ 0x5c, 0xa5, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzc $5, -16" + + - + input: + bytes: [ 0x5c, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, 264" + + - + input: + bytes: [ 0x5c, 0xa6, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, -16" + + - + input: + bytes: [ 0x60, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $zero, $zero, 12" + + - + input: + bytes: [ 0x60, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnezalc $2, 1340" + + - + input: + bytes: [ 0x60, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $2, $zero, 12" + + - + input: + bytes: [ 0x60, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $4, $2, 12" + + - + input: + bytes: [ 0x60, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnec $5, $6, 264" + + - + input: + bytes: [ 0x60, 0x43, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnec $2, $3, -16" + + - + input: + bytes: [ 0x74, 0x43, 0x12, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "daui $3, $2, 4660" + + - + input: + bytes: [ 0x7c, 0x02, 0x20, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bitswap $4, $2" + + - + input: + bytes: [ 0x7c, 0x02, 0x20, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dbitswap $4, $2" + + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "align $4, $2, $3, 2" + + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dalign $4, $2, $3, 5" + + - + input: + bytes: [ 0x7c, 0xa1, 0x04, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0x7c, 0xa1, 0x04, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "pref 1, 8($5)" + + - + input: + bytes: [ 0x7e, 0x42, 0xb3, 0xb6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ll $2, -153($18)" + + - + input: + bytes: [ 0x7e, 0x6f, 0xec, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sc $15, -40($19)" + + - + input: + bytes: [ 0x7f, 0xaf, 0xe6, 0xa7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "scd $15, -51($sp)" + + - + input: + bytes: [ 0x7f, 0xe0, 0x38, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lld $zero, 112($ra)" + + - + input: + bytes: [ 0xc8, 0x37, 0x96, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc 14572264" + + - + input: + bytes: [ 0xd8, 0x05, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jic $5, 256" + + - + input: + bytes: [ 0xd8, 0xa0, 0x46, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqzc $5, 72264" + + - + input: + bytes: [ 0xd8, 0x5f, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqzc $2, -16" + + - + input: + bytes: [ 0xe8, 0x37, 0x96, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "balc 14572264" + + - + input: + bytes: [ 0xec, 0x48, 0x00, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lwpc $2, 268" + + - + input: + bytes: [ 0xec, 0x50, 0x00, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lwupc $2, 268" + + - + input: + bytes: [ 0xec, 0x58, 0x3c, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ldpc $2, 123456" + + - + input: + bytes: [ 0xec, 0x7e, 0xff, 0xff ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "auipc $3, -1" + + - + input: + bytes: [ 0xec, 0x7f, 0x00, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "aluipc $3, 56" + + - + input: + bytes: [ 0xec, 0x80, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lapc $4, 100" + + - + input: + bytes: [ 0xf8, 0x05, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jialc $5, 256" + + - + input: + bytes: [ 0xf8, 0xa0, 0x46, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnezc $5, 72264" + + - + input: + bytes: [ 0xf8, 0x5f, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnezc $2, -16" + + - + input: + bytes: [ 0x04, 0x17, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sigrie 5" diff --git a/tests/MC/Mips/valid-r2-el.txt.yaml b/tests/MC/Mips/valid-r2-el.txt.yaml new file mode 100644 index 000000000..8d15ad124 --- /dev/null +++ b/tests/MC/Mips/valid-r2-el.txt.yaml @@ -0,0 +1,310 @@ +test_cases: + - + input: + bytes: [ 0xc1, 0x0b, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dmt" + + - + input: + bytes: [ 0xc1, 0x0b, 0x65, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dmt $5" + + - + input: + bytes: [ 0xe1, 0x0b, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "emt" + + - + input: + bytes: [ 0xe1, 0x0b, 0x64, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "emt $4" + + - + input: + bytes: [ 0x01, 0x00, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dvpe" + + - + input: + bytes: [ 0x01, 0x00, 0x66, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dvpe $6" + + - + input: + bytes: [ 0x21, 0x00, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "evpe" + + - + input: + bytes: [ 0x21, 0x00, 0x64, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "evpe $4" + + - + input: + bytes: [ 0x08, 0x10, 0x65, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fork $2, $3, $5" + + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "yield $4" + + - + input: + bytes: [ 0x09, 0x20, 0xa0, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "yield $4, $5" + + - + input: + bytes: [ 0x02, 0x20, 0x05, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 0, 2, 0" + + - + input: + bytes: [ 0x20, 0x20, 0x05, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 1, 0, 0" + + - + input: + bytes: [ 0x21, 0x20, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x21, 0x20, 0x0a, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 1, 0" + + - + input: + bytes: [ 0x22, 0x20, 0x0a, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 2, 0" + + - + input: + bytes: [ 0x32, 0x20, 0x0a, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 2, 1" + + - + input: + bytes: [ 0x23, 0x20, 0x1a, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $26, 1, 3, 0" + + - + input: + bytes: [ 0x23, 0x20, 0x1f, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $ra, 1, 3, 0" + + - + input: + bytes: [ 0x24, 0x20, 0x0e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $14, 1, 4, 0" + + - + input: + bytes: [ 0x25, 0x20, 0x0f, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $15, 1, 5, 0" + + - + input: + bytes: [ 0x02, 0x28, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 0, 2, 0" + + - + input: + bytes: [ 0x20, 0x28, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 1, 0, 0" + + - + input: + bytes: [ 0x21, 0x00, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x21, 0x50, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 1, 0" + + - + input: + bytes: [ 0x22, 0x50, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 2, 0" + + - + input: + bytes: [ 0x32, 0x50, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 2, 1" + + - + input: + bytes: [ 0x23, 0xd0, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $26, 1, 3, 0" + + - + input: + bytes: [ 0x23, 0xf8, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $ra, 1, 3, 0" + + - + input: + bytes: [ 0x24, 0x70, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $14, 1, 4, 0" + + - + input: + bytes: [ 0x25, 0x78, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $15, 1, 5, 0" diff --git a/tests/MC/Mips/valid-r2.txt.yaml b/tests/MC/Mips/valid-r2.txt.yaml new file mode 100644 index 000000000..501c37704 --- /dev/null +++ b/tests/MC/Mips/valid-r2.txt.yaml @@ -0,0 +1,310 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x60, 0x0b, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dmt" + + - + input: + bytes: [ 0x41, 0x65, 0x0b, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dmt $5" + + - + input: + bytes: [ 0x41, 0x60, 0x0b, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "emt" + + - + input: + bytes: [ 0x41, 0x64, 0x0b, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "emt $4" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dvpe" + + - + input: + bytes: [ 0x41, 0x66, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dvpe $6" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "evpe" + + - + input: + bytes: [ 0x41, 0x64, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "evpe $4" + + - + input: + bytes: [ 0x7c, 0x65, 0x10, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fork $2, $3, $5" + + - + input: + bytes: [ 0x7c, 0x80, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "yield $4" + + - + input: + bytes: [ 0x7c, 0xa0, 0x20, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "yield $4, $5" + + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 0, 2, 0" + + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 1, 0, 0" + + - + input: + bytes: [ 0x41, 0x00, 0x20, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x20, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x20, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 2, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x20, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 2, 1" + + - + input: + bytes: [ 0x41, 0x1a, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $26, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x1f, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $ra, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x0e, 0x20, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $14, 1, 4, 0" + + - + input: + bytes: [ 0x41, 0x0f, 0x20, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $15, 1, 5, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 0, 2, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 1, 0, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x50, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x50, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 2, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x50, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 2, 1" + + - + input: + bytes: [ 0x41, 0x84, 0xd0, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $26, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x84, 0xf8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $ra, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x70, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $14, 1, 4, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $15, 1, 5, 0" diff --git a/tests/MC/Mips/valid-xfail-mips32.txt.yaml b/tests/MC/Mips/valid-xfail-mips32.txt.yaml new file mode 100644 index 000000000..4fb4de011 --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips32.txt.yaml @@ -0,0 +1,150 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" diff --git a/tests/MC/Mips/valid-xfail-mips32r2.txt.yaml b/tests/MC/Mips/valid-xfail-mips32r2.txt.yaml new file mode 100644 index 000000000..22865f65b --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips32r2.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" + + - + input: + bytes: [ 0x02, 0xa7, 0x68, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $13, $7, $21" diff --git a/tests/MC/Mips/valid-xfail-mips32r3.txt.yaml b/tests/MC/Mips/valid-xfail-mips32r3.txt.yaml new file mode 100644 index 000000000..da59d822f --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips32r3.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" + + - + input: + bytes: [ 0x02, 0xa7, 0x68, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotrv $13, $7, $21" diff --git a/tests/MC/Mips/valid-xfail-mips32r5.txt.yaml b/tests/MC/Mips/valid-xfail-mips32r5.txt.yaml new file mode 100644 index 000000000..e1d9613f2 --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips32r5.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" + + - + input: + bytes: [ 0x02, 0xa7, 0x68, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotrv $13, $7, $21" diff --git a/tests/MC/Mips/valid-xfail-mips32r6.txt.yaml b/tests/MC/Mips/valid-xfail-mips32r6.txt.yaml new file mode 100644 index 000000000..bf719ace0 --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips32r6.txt.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $2, $zero, 12" + + - + input: + bytes: [ 0x20, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $4, $2, 12" + + - + input: + bytes: [ 0x60, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $2, $zero, 12" + + - + input: + bytes: [ 0x60, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $4, $2, 12" + + - + input: + bytes: [ 0x20, 0xc0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $6, $zero, 264" + + - + input: + bytes: [ 0x20, 0xa0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $5, $zero, 264" + + - + input: + bytes: [ 0x20, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqc $5, $6, 264" + + - + input: + bytes: [ 0x60, 0xc0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $6, $zero, 264" + + - + input: + bytes: [ 0x60, 0xa0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $5, $zero, 264" + + - + input: + bytes: [ 0x60, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnec $5, $6, 264" diff --git a/tests/MC/Mips/valid-xfail-mips64r2.txt.yaml b/tests/MC/Mips/valid-xfail-mips64r2.txt.yaml new file mode 100644 index 000000000..55a34c583 --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips64r2.txt.yaml @@ -0,0 +1,390 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x2f, 0x79, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.d $fcc1, $f15, $f15" + + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x35, 0x5c, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.d $fcc4, $f11, $f21" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x21, 0x94, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.d $fcc4, $f18, $f1" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x23, 0x4b, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.d $fcc3, $f9, $f3" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0xad, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.d $fcc5, $f21, $f16" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x27, 0xc4, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $fcc4, $f24, $f7" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x3f, 0x82, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.d $fcc2, $f16, $f31" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x3c, 0x9c, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.d $fcc4, $f19, $f28" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x27, 0xfc, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.d $fcc4, $f31, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x39, 0x6c, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $fcc4, $f13, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x32, 0xcf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.d $fcc7, $f25, $f18" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x31, 0x36, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.d $fcc6, $f6, $f17" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x38, 0xbe, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.d $fcc6, $f23, $f24" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" + + - + input: + bytes: [ 0x46, 0xc0, 0x17, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.pl $f30, $f2" + + - + input: + bytes: [ 0x46, 0xc0, 0xd3, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.pu $f14, $f26" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x46, 0xde, 0x46, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pll.ps $f24, $f8, $f30" + + - + input: + bytes: [ 0x46, 0xdc, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "plu.ps $f0, $f26, $f28" + + - + input: + bytes: [ 0x46, 0xda, 0xf2, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pul.ps $f8, $f30, $f26" + + - + input: + bytes: [ 0x46, 0xc2, 0x46, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "puu.ps $f24, $f8, $f2" + + - + input: + bytes: [ 0x02, 0xa7, 0x68, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotrv $13, $7, $21" diff --git a/tests/MC/Mips/valid-xfail-mips64r3.txt.yaml b/tests/MC/Mips/valid-xfail-mips64r3.txt.yaml new file mode 100644 index 000000000..44b114f12 --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips64r3.txt.yaml @@ -0,0 +1,390 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x2f, 0x79, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.eq.d $fcc1, $f15, $f15" + + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x35, 0x5c, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.f.d $fcc4, $f11, $f21" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x21, 0x94, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.le.d $fcc4, $f18, $f1" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x23, 0x4b, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.lt.d $fcc3, $f9, $f3" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0xad, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.nge.d $fcc5, $f21, $f16" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x27, 0xc4, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $fcc4, $f24, $f7" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x3f, 0x82, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ole.d $fcc2, $f16, $f31" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x3c, 0x9c, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.olt.d $fcc4, $f19, $f28" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x27, 0xfc, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.seq.d $fcc4, $f31, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x39, 0x6c, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $fcc4, $f13, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x32, 0xcf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ule.d $fcc7, $f25, $f18" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x31, 0x36, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ult.d $fcc6, $f6, $f17" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x38, 0xbe, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.un.d $fcc6, $f23, $f24" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" + + - + input: + bytes: [ 0x46, 0xc0, 0x17, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.pl $f30, $f2" + + - + input: + bytes: [ 0x46, 0xc0, 0xd3, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.pu $f14, $f26" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x46, 0xde, 0x46, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "pll.ps $f24, $f8, $f30" + + - + input: + bytes: [ 0x46, 0xdc, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "plu.ps $f0, $f26, $f28" + + - + input: + bytes: [ 0x46, 0xda, 0xf2, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "pul.ps $f8, $f30, $f26" + + - + input: + bytes: [ 0x46, 0xc2, 0x46, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "puu.ps $f24, $f8, $f2" + + - + input: + bytes: [ 0x02, 0xa7, 0x68, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rotrv $13, $7, $21" diff --git a/tests/MC/Mips/valid-xfail-mips64r5.txt.yaml b/tests/MC/Mips/valid-xfail-mips64r5.txt.yaml new file mode 100644 index 000000000..9cde0d73b --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips64r5.txt.yaml @@ -0,0 +1,390 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x2f, 0x79, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.eq.d $fcc1, $f15, $f15" + + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x35, 0x5c, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.f.d $fcc4, $f11, $f21" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x21, 0x94, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.le.d $fcc4, $f18, $f1" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x23, 0x4b, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.lt.d $fcc3, $f9, $f3" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0xad, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.nge.d $fcc5, $f21, $f16" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x27, 0xc4, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $fcc4, $f24, $f7" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x3f, 0x82, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ole.d $fcc2, $f16, $f31" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x3c, 0x9c, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.olt.d $fcc4, $f19, $f28" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x27, 0xfc, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.seq.d $fcc4, $f31, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x39, 0x6c, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $fcc4, $f13, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x32, 0xcf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ule.d $fcc7, $f25, $f18" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x31, 0x36, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ult.d $fcc6, $f6, $f17" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x38, 0xbe, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.un.d $fcc6, $f23, $f24" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" + + - + input: + bytes: [ 0x46, 0xc0, 0x17, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.pl $f30, $f2" + + - + input: + bytes: [ 0x46, 0xc0, 0xd3, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.pu $f14, $f26" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x46, 0xde, 0x46, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "pll.ps $f24, $f8, $f30" + + - + input: + bytes: [ 0x46, 0xdc, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "plu.ps $f0, $f26, $f28" + + - + input: + bytes: [ 0x46, 0xda, 0xf2, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "pul.ps $f8, $f30, $f26" + + - + input: + bytes: [ 0x46, 0xc2, 0x46, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "puu.ps $f24, $f8, $f2" + + - + input: + bytes: [ 0x02, 0xa7, 0x68, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rotrv $13, $7, $21" diff --git a/tests/MC/Mips/valid-xfail-mips64r6.txt.yaml b/tests/MC/Mips/valid-xfail-mips64r6.txt.yaml new file mode 100644 index 000000000..59ef200f3 --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips64r6.txt.yaml @@ -0,0 +1,150 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $2, $zero, 12" + + - + input: + bytes: [ 0x20, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $4, $2, 12" + + - + input: + bytes: [ 0x60, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $2, $zero, 12" + + - + input: + bytes: [ 0x60, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $4, $2, 12" + + - + input: + bytes: [ 0x20, 0xc0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $6, $zero, 264" + + - + input: + bytes: [ 0x20, 0xa0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $5, $zero, 264" + + - + input: + bytes: [ 0x20, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqc $5, $6, 264" + + - + input: + bytes: [ 0x60, 0xc0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $6, $zero, 264" + + - + input: + bytes: [ 0x60, 0xa0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $5, $zero, 264" + + - + input: + bytes: [ 0x60, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnec $5, $6, 264" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x65, 0x6f, 0xec, 0x5f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0x65, 0xce, 0x11, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x04, 0x7e, 0xab, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dati $3, $3, 43981" diff --git a/tests/MC/Mips/valid-xfail.txt.yaml b/tests/MC/Mips/valid-xfail.txt.yaml new file mode 100644 index 000000000..bb87efde5 --- /dev/null +++ b/tests/MC/Mips/valid-xfail.txt.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "b 16" + + - + input: + bytes: [ 0x10, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "b 28" + + - + input: + bytes: [ 0x10, 0x00, 0x28, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "b 41004" + + - + input: + bytes: [ 0x10, 0x04, 0x14, 0xe2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beq $zero, $4, 21388" + + - + input: + bytes: [ 0x11, 0x00, 0x00, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beqz $8, 788" + + - + input: + bytes: [ 0x12, 0x88, 0x00, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beq $20, $8, 96" + + - + input: + bytes: [ 0x15, 0x00, 0x88, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bnez $8, -122796" + + - + input: + bytes: [ 0x15, 0x8a, 0x9f, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bne $12, $10, -98772" + + - + input: + bytes: [ 0x50, 0xc7, 0x07, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beql $6, $7, 8144" + + - + input: + bytes: [ 0x7c, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ext $8, $2, 28, 25" + + - + input: + bytes: [ 0xc2, 0x44, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ll $4, -7321($18)" + + - + input: + bytes: [ 0xe2, 0x64, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sc $4, 18904($19)" diff --git a/tests/MC/Mips/valid.s.yaml b/tests/MC/Mips/valid.s.yaml new file mode 100644 index 000000000..501c37704 --- /dev/null +++ b/tests/MC/Mips/valid.s.yaml @@ -0,0 +1,310 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x60, 0x0b, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dmt" + + - + input: + bytes: [ 0x41, 0x65, 0x0b, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dmt $5" + + - + input: + bytes: [ 0x41, 0x60, 0x0b, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "emt" + + - + input: + bytes: [ 0x41, 0x64, 0x0b, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "emt $4" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dvpe" + + - + input: + bytes: [ 0x41, 0x66, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dvpe $6" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "evpe" + + - + input: + bytes: [ 0x41, 0x64, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "evpe $4" + + - + input: + bytes: [ 0x7c, 0x65, 0x10, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fork $2, $3, $5" + + - + input: + bytes: [ 0x7c, 0x80, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "yield $4" + + - + input: + bytes: [ 0x7c, 0xa0, 0x20, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "yield $4, $5" + + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 0, 2, 0" + + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 1, 0, 0" + + - + input: + bytes: [ 0x41, 0x00, 0x20, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x20, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x20, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 2, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x20, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 2, 1" + + - + input: + bytes: [ 0x41, 0x1a, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $26, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x1f, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $ra, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x0e, 0x20, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $14, 1, 4, 0" + + - + input: + bytes: [ 0x41, 0x0f, 0x20, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $15, 1, 5, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 0, 2, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 1, 0, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x50, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x50, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 2, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x50, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 2, 1" + + - + input: + bytes: [ 0x41, 0x84, 0xd0, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $26, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x84, 0xf8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $ra, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x70, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $14, 1, 4, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $15, 1, 5, 0" diff --git a/tests/MC/Mips/valid.txt.yaml b/tests/MC/Mips/valid.txt.yaml new file mode 100644 index 000000000..933101bc8 --- /dev/null +++ b/tests/MC/Mips/valid.txt.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0xca, 0x76, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit0 $19, 22, 8" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "baddu $9, $6, $7" + + - + input: + bytes: [ 0xd9, 0x0a, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit032 $8, 10, 8" + + - + input: + bytes: [ 0xe8, 0x7f, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit1 $3, 31, 8" + + - + input: + bytes: [ 0xfb, 0x0a, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit132 $24, 10, 8" + + - + input: + bytes: [ 0x71, 0x29, 0xec, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "cins $9, $9, 17, 29" + + - + input: + bytes: [ 0x70, 0x4f, 0x44, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "cins32 $15, $2, 18, 8" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dmul $9, $6, $7" + + - + input: + bytes: [ 0x48, 0x22, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dmfc2 $2, 64" + + - + input: + bytes: [ 0x48, 0xa2, 0x40, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dmtc2 $2, 16455" + + - + input: + bytes: [ 0x70, 0xc0, 0x48, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dpop $9, $6" + + - + input: + bytes: [ 0x71, 0xef, 0x34, 0x7a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "exts $15, $15, 17, 6" + + - + input: + bytes: [ 0x71, 0xa4, 0x42, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "exts32 $4, $13, 10, 8" + + - + input: + bytes: [ 0x71, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtm0 $15" + + - + input: + bytes: [ 0x72, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtm1 $16" + + - + input: + bytes: [ 0x72, 0x20, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtm2 $17" + + - + input: + bytes: [ 0x72, 0x40, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtp0 $18" + + - + input: + bytes: [ 0x72, 0x60, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtp1 $19" + + - + input: + bytes: [ 0x72, 0x80, 0x00, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtp2 $20" + + - + input: + bytes: [ 0x70, 0xc0, 0x48, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "pop $9, $6" + + - + input: + bytes: [ 0x72, 0xf8, 0xc8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "seq $25, $23, $24" + + - + input: + bytes: [ 0x72, 0x10, 0x09, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "seqi $16, $16, 38" + + - + input: + bytes: [ 0x72, 0xf4, 0xb8, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "sne $23, $23, $20" + + - + input: + bytes: [ 0x72, 0x04, 0xb1, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "snei $4, $16, -313" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "sync 6" + + - + input: + bytes: [ 0x71, 0x55, 0xa8, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "v3mulu $21, $10, $21" + + - + input: + bytes: [ 0x72, 0x70, 0x18, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "vmm0 $3, $19, $16" + + - + input: + bytes: [ 0x73, 0x66, 0xd8, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "vmulu $27, $27, $6" diff --git a/tests/MC/Mips/valid_R6-eva.txt.yaml b/tests/MC/Mips/valid_R6-eva.txt.yaml new file mode 100644 index 000000000..70d1389b3 --- /dev/null +++ b/tests/MC/Mips/valid_R6-eva.txt.yaml @@ -0,0 +1,700 @@ +test_cases: + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tlbinvf" + + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tlbinvf" diff --git a/tests/MC/Mips/valid_preR6-eva.txt.yaml b/tests/MC/Mips/valid_preR6-eva.txt.yaml new file mode 100644 index 000000000..3794e9d00 --- /dev/null +++ b/tests/MC/Mips/valid_preR6-eva.txt.yaml @@ -0,0 +1,2820 @@ +test_cases: + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7d, 0xf6, 0x7f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwle $22, 255($15)" + + - + input: + bytes: [ 0x7d, 0x57, 0x80, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwle $23, -256($10)" + + - + input: + bytes: [ 0x7d, 0xb7, 0xa8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwle $23, -176($13)" + + - + input: + bytes: [ 0x7f, 0x80, 0x7f, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwre $zero, 255($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0x80, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwre $zero, -256($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0xa8, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwre $zero, -176($gp)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x7e, 0x29, 0x7f, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swle $9, 255($17)" + + - + input: + bytes: [ 0x7e, 0x6a, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swle $10, -256($19)" + + - + input: + bytes: [ 0x7e, 0xa8, 0x41, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swle $8, 131($21)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x7f, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swre $20, 255($13)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x80, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swre $20, -256($13)" + + - + input: + bytes: [ 0x7d, 0xd2, 0x2b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swre $18, 86($14)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbinvf" + + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7d, 0xf6, 0x7f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwle $22, 255($15)" + + - + input: + bytes: [ 0x7d, 0x57, 0x80, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwle $23, -256($10)" + + - + input: + bytes: [ 0x7d, 0xb7, 0xa8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwle $23, -176($13)" + + - + input: + bytes: [ 0x7f, 0x80, 0x7f, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwre $zero, 255($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0x80, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwre $zero, -256($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0xa8, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwre $zero, -176($gp)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x7e, 0x29, 0x7f, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swle $9, 255($17)" + + - + input: + bytes: [ 0x7e, 0x6a, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swle $10, -256($19)" + + - + input: + bytes: [ 0x7e, 0xa8, 0x41, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swle $8, 131($21)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x7f, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swre $20, 255($13)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x80, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swre $20, -256($13)" + + - + input: + bytes: [ 0x7d, 0xd2, 0x2b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swre $18, 86($14)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbinvf" + + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7d, 0xf6, 0x7f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwle $22, 255($15)" + + - + input: + bytes: [ 0x7d, 0x57, 0x80, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwle $23, -256($10)" + + - + input: + bytes: [ 0x7d, 0xb7, 0xa8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwle $23, -176($13)" + + - + input: + bytes: [ 0x7f, 0x80, 0x7f, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwre $zero, 255($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0x80, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwre $zero, -256($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0xa8, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwre $zero, -176($gp)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x7e, 0x29, 0x7f, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swle $9, 255($17)" + + - + input: + bytes: [ 0x7e, 0x6a, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swle $10, -256($19)" + + - + input: + bytes: [ 0x7e, 0xa8, 0x41, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swle $8, 131($21)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x7f, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swre $20, 255($13)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x80, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swre $20, -256($13)" + + - + input: + bytes: [ 0x7d, 0xd2, 0x2b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swre $18, 86($14)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbinvf" + + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7d, 0xf6, 0x7f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwle $22, 255($15)" + + - + input: + bytes: [ 0x7d, 0x57, 0x80, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwle $23, -256($10)" + + - + input: + bytes: [ 0x7d, 0xb7, 0xa8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwle $23, -176($13)" + + - + input: + bytes: [ 0x7f, 0x80, 0x7f, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwre $zero, 255($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0x80, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwre $zero, -256($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0xa8, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwre $zero, -176($gp)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x7e, 0x29, 0x7f, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swle $9, 255($17)" + + - + input: + bytes: [ 0x7e, 0x6a, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swle $10, -256($19)" + + - + input: + bytes: [ 0x7e, 0xa8, 0x41, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swle $8, 131($21)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x7f, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swre $20, 255($13)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x80, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swre $20, -256($13)" + + - + input: + bytes: [ 0x7d, 0xd2, 0x2b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swre $18, 86($14)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbinvf" + + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7d, 0xf6, 0x7f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwle $22, 255($15)" + + - + input: + bytes: [ 0x7d, 0x57, 0x80, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwle $23, -256($10)" + + - + input: + bytes: [ 0x7d, 0xb7, 0xa8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwle $23, -176($13)" + + - + input: + bytes: [ 0x7f, 0x80, 0x7f, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwre $zero, 255($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0x80, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwre $zero, -256($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0xa8, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwre $zero, -176($gp)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x7e, 0x29, 0x7f, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swle $9, 255($17)" + + - + input: + bytes: [ 0x7e, 0x6a, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swle $10, -256($19)" + + - + input: + bytes: [ 0x7e, 0xa8, 0x41, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swle $8, 131($21)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x7f, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swre $20, 255($13)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x80, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swre $20, -256($13)" + + - + input: + bytes: [ 0x7d, 0xd2, 0x2b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swre $18, 86($14)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlbinvf" + + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7d, 0xf6, 0x7f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwle $22, 255($15)" + + - + input: + bytes: [ 0x7d, 0x57, 0x80, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwle $23, -256($10)" + + - + input: + bytes: [ 0x7d, 0xb7, 0xa8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwle $23, -176($13)" + + - + input: + bytes: [ 0x7f, 0x80, 0x7f, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwre $zero, 255($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0x80, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwre $zero, -256($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0xa8, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwre $zero, -176($gp)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x7e, 0x29, 0x7f, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swle $9, 255($17)" + + - + input: + bytes: [ 0x7e, 0x6a, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swle $10, -256($19)" + + - + input: + bytes: [ 0x7e, 0xa8, 0x41, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swle $8, 131($21)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x7f, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swre $20, 255($13)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x80, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swre $20, -256($13)" + + - + input: + bytes: [ 0x7d, 0xd2, 0x2b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swre $18, 86($14)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlbinvf" diff --git a/tests/details/cs_common_details.yaml b/tests/details/cs_common_details.yaml index 4dd602077..3ed8537eb 100644 --- a/tests/details/cs_common_details.yaml +++ b/tests/details/cs_common_details.yaml @@ -395,7 +395,7 @@ test_cases: input: bytes: [ 0x0c, 0x10, 0x00, 0x97, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x0c, 0x8f, 0xa2, 0x00, 0x00, 0x34, 0x21, 0x34, 0x56, 0x00, 0x80, 0x04, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ CS_OPT_DETAIL, CS_MODE_MIPS32, CS_MODE_BIG_ENDIAN ] + options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R5, CS_MODE_BIG_ENDIAN ] address: 0x1000 expected: insns: @@ -405,36 +405,36 @@ test_cases: op_str: "0x40025c" details: regs_impl_write: [ ra ] - groups: [ stdenc ] + groups: [ call, HasStdEnc, NotInMicroMips, NotNanoMips ] - asm_text: "nop" mnemonic: "nop" details: - groups: [ stdenc, notinmicromips ] + groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ] - asm_text: "addiu $v0, $zero, 0xc" mnemonic: "addiu" op_str: "$v0, $zero, 0xc" details: - groups: [ stdenc, notinmicromips ] + groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ] - - asm_text: "lw $v0, ($sp)" + asm_text: "lw $v0, 0($sp)" mnemonic: "lw" - op_str: "$v0, ($sp)" + op_str: "$v0, 0($sp)" details: - groups: [ stdenc, notinmicromips ] + groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ] - asm_text: "ori $at, $at, 0x3456" mnemonic: "ori" op_str: "$at, $at, 0x3456" details: - groups: [ stdenc ] + groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ] - asm_text: "jr.hb $a0" mnemonic: "jr.hb" op_str: "$a0" details: - groups: [ stdenc, mips32, notmips32r6, notmips64r6, jump ] + groups: [ jump, HasStdEnc, HasMips32r2, NotMips32r6, NotMips64r6 ] - input: bytes: [ 0x56, 0x34, 0x21, 0x34, 0xc2, 0x17, 0x01, 0x00 ] @@ -448,13 +448,13 @@ test_cases: mnemonic: "ori" op_str: "$at, $at, 0x3456" details: - groups: [ stdenc ] + groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ] - asm_text: "srl $v0, $at, 0x1f" mnemonic: "srl" op_str: "$v0, $at, 0x1f" details: - groups: [ stdenc, notinmicromips ] + groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ] - input: bytes: [ 0x00, 0x07, 0x00, 0x07, 0x00, 0x11, 0x93, 0x7c, 0x01, 0x8c, 0x8b, 0x7c, 0x00, 0xc7, 0x48, 0xd0 ] @@ -468,25 +468,25 @@ test_cases: mnemonic: "break" op_str: "7, 0" details: - groups: [ micromips ] + groups: [ InMicroMips, HasMips32r6 ] - asm_text: "wait 0x11" mnemonic: "wait" op_str: "0x11" details: - groups: [ micromips ] + groups: [ InMicroMips, HasMips32r6 ] - asm_text: "syscall 0x18c" mnemonic: "syscall" op_str: "0x18c" details: - groups: [ micromips, int ] + groups: [ InMicroMips ] - asm_text: "rotrv $t1, $a2, $a3" mnemonic: "rotrv" op_str: "$t1, $a2, $a3" details: - groups: [ micromips ] + groups: [ InMicroMips ] - input: bytes: [ 0xec, 0x80, 0x00, 0x19, 0x7c, 0x43, 0x22, 0xa0 ] @@ -496,17 +496,17 @@ test_cases: expected: insns: - - asm_text: "addiupc $a0, 0x64" - mnemonic: "addiupc" + asm_text: "lapc $a0, 0x64" + mnemonic: "lapc" op_str: "$a0, 0x64" details: - groups: [ stdenc, mips32r6 ] + groups: [ HasStdEnc, HasMips32r6 ] - asm_text: "align $a0, $v0, $v1, 2" mnemonic: "align" op_str: "$a0, $v0, $v1, 2" details: - groups: [ stdenc, mips32r6 ] + groups: [ HasStdEnc, HasMips32r6 ] - input: bytes: [ 0x80, 0x20, 0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x10, 0x43, 0x23, 0x0e, 0xd0, 0x44, 0x00, 0x80, 0x4c, 0x43, 0x22, 0x02, 0x2d, 0x03, 0x00, 0x80, 0x7c, 0x43, 0x20, 0x14, 0x7c, 0x43, 0x20, 0x93, 0x4f, 0x20, 0x00, 0x21, 0x4c, 0xc8, 0x00, 0x21, 0x40, 0x82, 0x00, 0x14 ] diff --git a/tests/details/mips.yaml b/tests/details/mips.yaml index 1695728f8..b7fe354dd 100644 --- a/tests/details/mips.yaml +++ b/tests/details/mips.yaml @@ -2,8 +2,8 @@ test_cases: - input: bytes: [ 0x0c, 0x10, 0x00, 0x97, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x0c, 0x8f, 0xa2, 0x00, 0x00, 0x34, 0x21, 0x34, 0x56 ] - arch: "mips" - options: [ CS_OPT_DETAIL, CS_MODE_MIPS32, CS_MODE_BIG_ENDIAN ] + arch: "CS_ARCH_MIPS" + options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R5, CS_MODE_BIG_ENDIAN ] address: 0x0 expected: insns: @@ -32,7 +32,7 @@ test_cases: type: MIPS_OP_IMM imm: 0xc - - asm_text: "lw $v0, ($sp)" + asm_text: "lw $v0, 0($sp)" details: mips: operands: @@ -59,7 +59,7 @@ test_cases: - input: bytes: [ 0x56, 0x34, 0x21, 0x34, 0xc2, 0x17, 0x01, 0x00 ] - arch: "mips" + arch: "CS_ARCH_MIPS" options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN ] address: 0x0 expected: @@ -95,7 +95,7 @@ test_cases: - input: bytes: [ 0x00, 0x07, 0x00, 0x07, 0x00, 0x11, 0x93, 0x7c, 0x01, 0x8c, 0x8b, 0x7c, 0x00, 0xc7, 0x48, 0xd0 ] - arch: "mips" + arch: "CS_ARCH_MIPS" options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_MICRO, CS_MODE_BIG_ENDIAN ] address: 0x0 expected: @@ -144,13 +144,13 @@ test_cases: - input: bytes: [ 0xec, 0x80, 0x00, 0x19, 0x7c, 0x43, 0x22, 0xa0 ] - arch: "mips" + arch: "CS_ARCH_MIPS" options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ] address: 0x0 expected: insns: - - asm_text: "addiupc $a0, 0x64" + asm_text: "lapc $a0, 0x64" details: mips: operands: @@ -180,8 +180,8 @@ test_cases: - input: bytes: [ 0x70, 0x00, 0xb2, 0xff ] - arch: "mips" - options: [ CS_MODE_MIPS64, CS_MODE_MIPS2, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_MIPS2, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ] address: 0x0 expected: insns: @@ -192,7 +192,7 @@ test_cases: operands: - type: MIPS_OP_REG - reg: s2 + reg: "18" - type: MIPS_OP_MEM mem_base: sp @@ -200,7 +200,7 @@ test_cases: - input: bytes: [ 0x70, 0x00, 0xb2, 0xff ] - arch: "mips" + arch: "CS_ARCH_MIPS" options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN] address: 0x0 expected: @@ -218,3 +218,52 @@ test_cases: mem_base: sp mem_disp: 0x70 + - + skip: true + skip_reason: "Capstone python bindings do not handle CS_OPT_DETAIL_REAL." + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ CS_OPT_DETAIL, CS_OPT_DETAIL_REAL, CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "nop" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: zero + - + type: MIPS_OP_REG + reg: zero + - + type: MIPS_OP_IMM + imm: 0 + + - + skip: true + skip_reason: "Capstone python bindings do not handle CS_OPT_DETAIL_REAL." + input: + bytes: [ 0x38,0xf0,0x20,0x46 ] + arch: "CS_ARCH_MIPS" + options: [ CS_OPT_DETAIL, CS_OPT_DETAIL_REAL, CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS1 ] + address: 0x0 + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: fcc0 + - + type: MIPS_OP_REG + reg: f30 + - + type: MIPS_OP_REG + reg: f0 \ No newline at end of file diff --git a/tests/issues/issues.yaml b/tests/issues/issues.yaml index fe7a8c5b1..cc0a17cc6 100644 --- a/tests/issues/issues.yaml +++ b/tests/issues/issues.yaml @@ -4815,3 +4815,145 @@ test_cases: details: sparc: cc: SPARC_CC_ICC_NE + + - + input: + name: "issue 2448" + bytes: [ 0x04, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS32 ] + address: 0x0 + expected: + insns: + - asm_text: "jal 0x10" + + - + input: + name: "issue 1054" + bytes: [ 0x01, 0x20, 0x10, 0x2d, 0x00, 0x80, 0xe8, 0x2d, 0x40, 0xab, 0x50, 0x00, 0x00, 0xa0, 0x40, 0x2d, 0x00, 0x80, 0x50, 0x2d, 0x01, 0xa0, 0x70, 0x2d, 0x40, 0xac, 0x10, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_MIPS3 ] + address: 0x0 + expected: + insns: + - asm_text: "move $v0, $t1" + - asm_text: "move $sp, $a0" + - asm_text: "dmtc0 $t3, $10, 0" + - asm_text: "move $t0, $a1" + - asm_text: "move $t2, $a0" + - asm_text: "move $t6, $t5" + - asm_text: "dmtc0 $t4, $2, 0" + + - + input: + name: "issue 1133" + bytes: [ 0xb5, 0x06, 0xff, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS32R6 ] + address: 0x0 + expected: + insns: + - asm_text: "pref 0x1f, 0xd($t7)" + + - + input: + name: "issue 1267" + bytes: [ 0x00, 0xc0, 0x50, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_MIPS3 ] + address: 0x0 + expected: + insns: + - asm_text: "move $t2, $a2" + + - + input: + name: "issue 1508" + bytes: [ 0x40, 0x02, 0x10, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_MIPS32R6 ] + address: 0x0 + expected: + insns: + - asm_text: "mfc0 $v0, $2, 0" + + - + input: + name: "issue 1634" + bytes: [ 0x46, 0x20, 0x09, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_MIPS3 ] + address: 0x0 + expected: + insns: + - asm_text: "c.ule.d $fcc1, $f1, $f0" + + - + input: + name: "issue 1673" + bytes: [ 0x03, 0x80, 0x0c, 0x40, 0x80, 0x00, 0x8c, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS64 ] + address: 0x0 + expected: + insns: + - asm_text: "mfc0 $t4, $16, 3" + - asm_text: "ori $t4, $t4, 0x80" + + - + input: + name: "issue 1680" + bytes: [ 0x40, 0x00, 0x00, 0x0c, 0x08, 0x00, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS32 ] + address: 0x0 + expected: + insns: + - asm_text: "jal 0x100" + details: + mips: + operands: + - type: MIPS_OP_IMM + imm: 0x100 + + - asm_text: "jr $ra" + details: + mips: + operands: + - type: MIPS_OP_REG + reg: ra + + - + input: + name: "issue 1780" + bytes: [ 0x7c, 0x03, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_MIPS32 ] + address: 0x0 + expected: + insns: + - asm_text: "rdhwr $v1, $29" + + - + input: + name: "issue 1851" + bytes: [ 0x32, 0xC0, 0x38, 0x46, 0x32, 0x02, 0x20, 0x46, 0x32, 0x03, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS64 ] + address: 0x0 + expected: + insns: + - asm_text: "c.eq.d $f24, $f24" + - asm_text: "c.eq.d $fcc2, $f0, $f0" + - asm_text: "c.eq.d $fcc3, $f0, $f0" + + - + input: + name: "issue 1851" + bytes: [ 0x00, 0x00, 0x19, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS32R6 ] + address: 0x0 + expected: + insns: + - asm_text: "jalrc $t9"