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x86: do not print memory offset in negative form. bug reported by Le Dinh Long

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This commit is contained in:
Nguyen Anh Quynh 2014-03-29 17:26:51 +08:00
parent 125f504174
commit 6d3d8005aa
4 changed files with 20 additions and 14 deletions
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11
arch/X86/X86ATTInstPrinter.c
View File

@ -289,10 +289,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
if (MI->csh->detail)
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = imm;
if (imm < 0) {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -imm);
else
SStream_concat(O, "-%"PRIu64, -imm);
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm);
} else {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
@ -376,7 +373,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
else
SStream_concat(O, "%s$%"PRIu64"%s", markup("<imm:"), imm, markup(">"));
} else {
SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), ((1 << 8*MI->x86_imm_size) - 1) & imm, markup(">"));
SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), arch_masks[MI->x86_imm_size] & imm, markup(">"));
}
if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_IMM;
@ -396,7 +393,7 @@ static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O)
// Print X86 immediates as signed values.
int64_t imm = MCOperand_getImm(Op);
if (imm < 0) {
SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), ((1 << 8*MI->x86_imm_size) - 1) & imm, markup(">"));
SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), arch_masks[MI->x86_imm_size] & imm, markup(">"));
} else {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), imm, markup(">"));
@ -435,7 +432,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = DispVal;
if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) {
if (DispVal < 0) {
SStream_concat(O, "0x%"PRIx64, ((1L << (8*MI->csh->mode)) - 1) & DispVal);
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal);
} else {
if (DispVal > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, DispVal);

11
arch/X86/X86IntelInstPrinter.c
View File

@ -293,10 +293,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
if (MI->csh->detail)
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = imm;
if (imm < 0) {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -imm);
else
SStream_concat(O, "-%"PRIu64, -imm);
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm);
} else {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
@ -419,7 +416,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
else
SStream_concat(O, "%"PRIu64, imm);
} else {
SStream_concat(O, "0x%"PRIx64, ((1 << 8*MI->x86_imm_size) - 1) & imm);
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->x86_imm_size] & imm);
}
if (MI->csh->detail) {
@ -439,7 +436,7 @@ static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O)
} else if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
if (imm < 0) {
SStream_concat(O, "0x%"PRIx64, ((1 << 8*MI->x86_imm_size) - 1) & imm);
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->x86_imm_size] & imm);
} else {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
@ -500,7 +497,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
}
if (DispVal < 0) {
SStream_concat(O, "0x%"PRIx64, ((1L << (8*MI->csh->mode)) - 1) & DispVal);
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal);
} else {
if (DispVal > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, DispVal);

10
arch/X86/X86Mapping.c
View File

@ -9,6 +9,16 @@
#include "../../utils.h"
#include "../../include/x86.h"
uint64_t arch_masks[9] = {
0, 0xff,
0xffff,
0,
0xffffffff,
0, 0, 0,
0xffffffffffffffff
};
static x86_reg sib_base_map[] = {
X86_REG_INVALID,
#define ENTRY(x) X86_REG_##x,

2
arch/X86/X86Mapping.h
View File

@ -44,4 +44,6 @@ void X86_insn_combine(cs_struct *h, cs_insn *insn, cs_insn *prev);
// this is to handle instructions embedding accumulate registers into AsmStrs[]
x86_reg X86_insn_reg(unsigned int id);
extern uint64_t arch_masks[9];
#endif