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refactor: Refactor TriCore instruction definitions and mappings
- Add new `multiclass mI_MADDRsh_` to handle `MADDR_H` and `MADDRS_H` in `arch/TriCore/TriCoreInstrInfo.td`
This commit is contained in:
billow
parent
8b56ae652b
commit
6fe3766434
@ -1100,30 +1100,32 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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4200339U, // MADDM_U_rrr2_v110
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806360349U, // MADDM_rcr_v110
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4199709U, // MADDM_rrr2_v110
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4199495U, // MADDRS_H_rrr1_DcEdDaDbUL
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4199495U, // MADDRS_H_rrr1_LL
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4199495U, // MADDRS_H_rrr1_LU
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4199495U, // MADDRS_H_rrr1_UL
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4199495U, // MADDRS_H_rrr1_UL_2
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4199495U, // MADDRS_H_rrr1_UU
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4199495U, // MADDRS_H_rrr1_v110
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4199878U, // MADDRS_Q_rrr1
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2537559494U, // MADDRS_Q_rrr1_L_L
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2554336710U, // MADDRS_Q_rrr1_U_U
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4199347U, // MADDR_H_rrr1_DcEdDaDbUL
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4199347U, // MADDR_H_rrr1_LL
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4199347U, // MADDR_H_rrr1_LU
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4199347U, // MADDR_H_rrr1_UL
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4199347U, // MADDR_H_rrr1_UL_2
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4199347U, // MADDR_H_rrr1_UU
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4199347U, // MADDR_H_rrr1_v110
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4199833U, // MADDR_Q_rrr1
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2537559449U, // MADDR_Q_rrr1_L_L
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2554336665U, // MADDR_Q_rrr1_U_U
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4199461U, // MADDSUMS_H_rrr1_LL
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4199461U, // MADDSUMS_H_rrr1_LU
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4199461U, // MADDSUMS_H_rrr1_UL
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4199461U, // MADDSUMS_H_rrr1_UU
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4199461U, // MADDSUMS_H_rrr1_v110
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4199296U, // MADDSUM_H_rrr1_LL
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4199296U, // MADDSUM_H_rrr1_LU
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4199296U, // MADDSUM_H_rrr1_UL
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4199296U, // MADDSUM_H_rrr1_UU
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4199296U, // MADDSUM_H_rrr1_v110
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4199505U, // MADDSURS_H_rrr1_LL
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4199505U, // MADDSURS_H_rrr1_LU
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4199505U, // MADDSURS_H_rrr1_UL
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@ -1136,12 +1138,10 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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4199525U, // MADDSUS_H_rrr1_LU
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4199525U, // MADDSUS_H_rrr1_UL
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4199525U, // MADDSUS_H_rrr1_UU
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4199525U, // MADDSUS_H_rrr1_v110
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4199565U, // MADDSU_H_rrr1_LL
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4199565U, // MADDSU_H_rrr1_LU
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4199565U, // MADDSU_H_rrr1_UL
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4199565U, // MADDSU_H_rrr1_UU
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4199565U, // MADDSU_H_rrr1_v110
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4199402U, // MADDS_H_rrr1_LL
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4199402U, // MADDS_H_rrr1_LU
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4199402U, // MADDS_H_rrr1_UL
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@ -1268,6 +1268,7 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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4199473U, // MSUBRS_H_rrr1_LU
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4199473U, // MSUBRS_H_rrr1_UL
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4199473U, // MSUBRS_H_rrr1_UU
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4199868U, // MSUBRS_Q_rrr1
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2537559484U, // MSUBRS_Q_rrr1_L_L
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2554336700U, // MSUBRS_Q_rrr1_U_U
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4199327U, // MSUBR_H_rrr1_DcEdDaDbUL
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@ -1275,6 +1276,7 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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4199327U, // MSUBR_H_rrr1_LU
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4199327U, // MSUBR_H_rrr1_UL
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4199327U, // MSUBR_H_rrr1_UU
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4199824U, // MSUBR_Q_rrr1
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2537559440U, // MSUBR_Q_rrr1_L_L
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2554336656U, // MSUBR_Q_rrr1_U_U
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4199382U, // MSUBS_H_rrr1_LL
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@ -2287,30 +2289,32 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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0U, // MADDM_U_rrr2_v110
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17U, // MADDM_rcr_v110
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0U, // MADDM_rrr2_v110
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6U, // MADDRS_H_rrr1_DcEdDaDbUL
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2U, // MADDRS_H_rrr1_LL
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3U, // MADDRS_H_rrr1_LU
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4U, // MADDRS_H_rrr1_UL
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4U, // MADDRS_H_rrr1_UL_2
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5U, // MADDRS_H_rrr1_UU
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65U, // MADDRS_H_rrr1_v110
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65U, // MADDRS_Q_rrr1
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0U, // MADDRS_Q_rrr1_L_L
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0U, // MADDRS_Q_rrr1_U_U
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6U, // MADDR_H_rrr1_DcEdDaDbUL
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2U, // MADDR_H_rrr1_LL
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3U, // MADDR_H_rrr1_LU
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4U, // MADDR_H_rrr1_UL
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4U, // MADDR_H_rrr1_UL_2
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5U, // MADDR_H_rrr1_UU
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65U, // MADDR_H_rrr1_v110
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65U, // MADDR_Q_rrr1
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0U, // MADDR_Q_rrr1_L_L
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0U, // MADDR_Q_rrr1_U_U
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2U, // MADDSUMS_H_rrr1_LL
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3U, // MADDSUMS_H_rrr1_LU
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4U, // MADDSUMS_H_rrr1_UL
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5U, // MADDSUMS_H_rrr1_UU
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65U, // MADDSUMS_H_rrr1_v110
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2U, // MADDSUM_H_rrr1_LL
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3U, // MADDSUM_H_rrr1_LU
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4U, // MADDSUM_H_rrr1_UL
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5U, // MADDSUM_H_rrr1_UU
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65U, // MADDSUM_H_rrr1_v110
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2U, // MADDSURS_H_rrr1_LL
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3U, // MADDSURS_H_rrr1_LU
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4U, // MADDSURS_H_rrr1_UL
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@ -2323,27 +2327,25 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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3U, // MADDSUS_H_rrr1_LU
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4U, // MADDSUS_H_rrr1_UL
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5U, // MADDSUS_H_rrr1_UU
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65U, // MADDSUS_H_rrr1_v110
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2U, // MADDSU_H_rrr1_LL
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3U, // MADDSU_H_rrr1_LU
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4U, // MADDSU_H_rrr1_UL
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5U, // MADDSU_H_rrr1_UU
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65U, // MADDSU_H_rrr1_v110
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2U, // MADDS_H_rrr1_LL
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3U, // MADDS_H_rrr1_LU
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4U, // MADDS_H_rrr1_UL
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5U, // MADDS_H_rrr1_UU
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65U, // MADDS_H_rrr1_v110
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65U, // MADDS_Q_rrr1
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7U, // MADDS_Q_rrr1_L
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6U, // MADDS_Q_rrr1_L
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0U, // MADDS_Q_rrr1_L_L
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65U, // MADDS_Q_rrr1_L_v110
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8U, // MADDS_Q_rrr1_U
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7U, // MADDS_Q_rrr1_U
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0U, // MADDS_Q_rrr1_U_U
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65U, // MADDS_Q_rrr1_e
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7U, // MADDS_Q_rrr1_e_L
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6U, // MADDS_Q_rrr1_e_L
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0U, // MADDS_Q_rrr1_e_L_L
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8U, // MADDS_Q_rrr1_e_U
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7U, // MADDS_Q_rrr1_e_U
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0U, // MADDS_Q_rrr1_e_U_U
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17U, // MADDS_U_rcr
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17U, // MADDS_U_rcr_e
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@ -2360,15 +2362,15 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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5U, // MADD_H_rrr1_UU
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65U, // MADD_H_rrr1_v110
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65U, // MADD_Q_rrr1
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7U, // MADD_Q_rrr1_L
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6U, // MADD_Q_rrr1_L
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0U, // MADD_Q_rrr1_L_L
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65U, // MADD_Q_rrr1_L_v110
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8U, // MADD_Q_rrr1_U
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7U, // MADD_Q_rrr1_U
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0U, // MADD_Q_rrr1_U_U
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65U, // MADD_Q_rrr1_e
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7U, // MADD_Q_rrr1_e_L
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6U, // MADD_Q_rrr1_e_L
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0U, // MADD_Q_rrr1_e_L_L
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8U, // MADD_Q_rrr1_e_U
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7U, // MADD_Q_rrr1_e_U
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0U, // MADD_Q_rrr1_e_U_U
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49U, // MADD_U_rcr
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0U, // MADD_U_rrr2
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@ -2450,18 +2452,20 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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4U, // MSUBM_H_rrr1_UL
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5U, // MSUBM_H_rrr1_UU
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65U, // MSUBM_H_rrr1_v110
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6U, // MSUBRS_H_rrr1_DcEdDaDbUL
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8U, // MSUBRS_H_rrr1_DcEdDaDbUL
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2U, // MSUBRS_H_rrr1_LL
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3U, // MSUBRS_H_rrr1_LU
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4U, // MSUBRS_H_rrr1_UL
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5U, // MSUBRS_H_rrr1_UU
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65U, // MSUBRS_Q_rrr1
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0U, // MSUBRS_Q_rrr1_L_L
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0U, // MSUBRS_Q_rrr1_U_U
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6U, // MSUBR_H_rrr1_DcEdDaDbUL
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8U, // MSUBR_H_rrr1_DcEdDaDbUL
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2U, // MSUBR_H_rrr1_LL
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3U, // MSUBR_H_rrr1_LU
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4U, // MSUBR_H_rrr1_UL
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5U, // MSUBR_H_rrr1_UU
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65U, // MSUBR_Q_rrr1
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0U, // MSUBR_Q_rrr1_L_L
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0U, // MSUBR_Q_rrr1_U_U
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2U, // MSUBS_H_rrr1_LL
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@ -2470,14 +2474,14 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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5U, // MSUBS_H_rrr1_UU
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65U, // MSUBS_H_rrr1_v110
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65U, // MSUBS_Q_rrr1
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7U, // MSUBS_Q_rrr1_L
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6U, // MSUBS_Q_rrr1_L
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0U, // MSUBS_Q_rrr1_L_L
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8U, // MSUBS_Q_rrr1_U
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7U, // MSUBS_Q_rrr1_U
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0U, // MSUBS_Q_rrr1_U_U
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65U, // MSUBS_Q_rrr1_e
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7U, // MSUBS_Q_rrr1_e_L
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6U, // MSUBS_Q_rrr1_e_L
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0U, // MSUBS_Q_rrr1_e_L_L
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8U, // MSUBS_Q_rrr1_e_U
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7U, // MSUBS_Q_rrr1_e_U
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0U, // MSUBS_Q_rrr1_e_U_U
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17U, // MSUBS_U_rcr
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17U, // MSUBS_U_rcr_e
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@ -2494,14 +2498,14 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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5U, // MSUB_H_rrr1_UU
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65U, // MSUB_H_rrr1_v110
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65U, // MSUB_Q_rrr1
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7U, // MSUB_Q_rrr1_L
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6U, // MSUB_Q_rrr1_L
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0U, // MSUB_Q_rrr1_L_L
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8U, // MSUB_Q_rrr1_U
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7U, // MSUB_Q_rrr1_U
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0U, // MSUB_Q_rrr1_U_U
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65U, // MSUB_Q_rrr1_e
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7U, // MSUB_Q_rrr1_e_L
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6U, // MSUB_Q_rrr1_e_L
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0U, // MSUB_Q_rrr1_e_L_L
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8U, // MSUB_Q_rrr1_e_U
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7U, // MSUB_Q_rrr1_e_U
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0U, // MSUB_Q_rrr1_e_U_U
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49U, // MSUB_U_rcr
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0U, // MSUB_U_rrr2
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@ -3168,7 +3172,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
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return;
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break;
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case 4:
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// MADDMS_H_rrr1_UL, MADDM_H_rrr1_UL, MADDRS_H_rrr1_UL, MADDR_H_rrr1_UL, ...
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// MADDMS_H_rrr1_UL, MADDM_H_rrr1_UL, MADDRS_H_rrr1_UL, MADDRS_H_rrr1_UL_...
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SStream_concat0(O, " UL, ");
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printZExtImm_2(MI, 4, O);
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return;
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@ -3180,23 +3184,23 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
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return;
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break;
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case 6:
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// MADDRS_H_rrr1_DcEdDaDbUL, MADDR_H_rrr1_DcEdDaDbUL, MSUBRS_H_rrr1_DcEdD...
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SStream_concat0(O, ", UL, ");
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printZExtImm_2(MI, 4, O);
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return;
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break;
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case 7:
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// MADDS_Q_rrr1_L, MADDS_Q_rrr1_e_L, MADD_Q_rrr1_L, MADD_Q_rrr1_e_L, MSUB...
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SStream_concat0(O, " L, ");
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printZExtImm_2(MI, 4, O);
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return;
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break;
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case 8:
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case 7:
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// MADDS_Q_rrr1_U, MADDS_Q_rrr1_e_U, MADD_Q_rrr1_U, MADD_Q_rrr1_e_U, MSUB...
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SStream_concat0(O, " U, ");
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printZExtImm_2(MI, 4, O);
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return;
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break;
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case 8:
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// MSUBRS_H_rrr1_DcEdDaDbUL, MSUBR_H_rrr1_DcEdDaDbUL
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SStream_concat0(O, ", UL, ");
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printZExtImm_2(MI, 4, O);
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return;
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break;
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case 9:
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// MULM_H_rr1_LL2e, MULR_H_rr1_LL2e, MUL_H_rr1_LL2e
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SStream_concat0(O, "LL, ");
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@ -3259,7 +3263,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
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return;
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break;
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case 4:
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// MADDM_H_rrr1_v110, MADDM_Q_rrr1_v110, MADDSUMS_H_rrr1_v110, MADDSUM_H_...
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// MADDM_H_rrr1_v110, MADDM_Q_rrr1_v110, MADDRS_H_rrr1_v110, MADDRS_Q_rrr...
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printZExtImm_2(MI, 4, O);
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return;
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break;
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -714,48 +714,48 @@
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TriCore_MADDM_U_rrr2_v110 = 703,
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TriCore_MADDM_rcr_v110 = 704,
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TriCore_MADDM_rrr2_v110 = 705,
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TriCore_MADDRS_H_rrr1_DcEdDaDbUL = 706,
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TriCore_MADDRS_H_rrr1_LL = 707,
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TriCore_MADDRS_H_rrr1_LU = 708,
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TriCore_MADDRS_H_rrr1_UL = 709,
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TriCore_MADDRS_H_rrr1_LL = 706,
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TriCore_MADDRS_H_rrr1_LU = 707,
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TriCore_MADDRS_H_rrr1_UL = 708,
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TriCore_MADDRS_H_rrr1_UL_2 = 709,
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TriCore_MADDRS_H_rrr1_UU = 710,
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TriCore_MADDRS_Q_rrr1_L_L = 711,
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TriCore_MADDRS_Q_rrr1_U_U = 712,
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TriCore_MADDR_H_rrr1_DcEdDaDbUL = 713,
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TriCore_MADDR_H_rrr1_LL = 714,
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TriCore_MADDR_H_rrr1_LU = 715,
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TriCore_MADDR_H_rrr1_UL = 716,
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TriCore_MADDR_H_rrr1_UU = 717,
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TriCore_MADDR_Q_rrr1_L_L = 718,
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TriCore_MADDR_Q_rrr1_U_U = 719,
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TriCore_MADDSUMS_H_rrr1_LL = 720,
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TriCore_MADDSUMS_H_rrr1_LU = 721,
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TriCore_MADDSUMS_H_rrr1_UL = 722,
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TriCore_MADDSUMS_H_rrr1_UU = 723,
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TriCore_MADDSUMS_H_rrr1_v110 = 724,
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TriCore_MADDSUM_H_rrr1_LL = 725,
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TriCore_MADDSUM_H_rrr1_LU = 726,
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TriCore_MADDSUM_H_rrr1_UL = 727,
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TriCore_MADDSUM_H_rrr1_UU = 728,
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TriCore_MADDSUM_H_rrr1_v110 = 729,
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TriCore_MADDSURS_H_rrr1_LL = 730,
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TriCore_MADDSURS_H_rrr1_LU = 731,
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TriCore_MADDSURS_H_rrr1_UL = 732,
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TriCore_MADDSURS_H_rrr1_UU = 733,
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TriCore_MADDSUR_H_rrr1_LL = 734,
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TriCore_MADDSUR_H_rrr1_LU = 735,
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TriCore_MADDSUR_H_rrr1_UL = 736,
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TriCore_MADDSUR_H_rrr1_UU = 737,
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TriCore_MADDSUS_H_rrr1_LL = 738,
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TriCore_MADDSUS_H_rrr1_LU = 739,
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TriCore_MADDSUS_H_rrr1_UL = 740,
|
||||
TriCore_MADDSUS_H_rrr1_UU = 741,
|
||||
TriCore_MADDSUS_H_rrr1_v110 = 742,
|
||||
TriCore_MADDSU_H_rrr1_LL = 743,
|
||||
TriCore_MADDSU_H_rrr1_LU = 744,
|
||||
TriCore_MADDSU_H_rrr1_UL = 745,
|
||||
TriCore_MADDSU_H_rrr1_UU = 746,
|
||||
TriCore_MADDSU_H_rrr1_v110 = 747,
|
||||
TriCore_MADDRS_H_rrr1_v110 = 711,
|
||||
TriCore_MADDRS_Q_rrr1 = 712,
|
||||
TriCore_MADDRS_Q_rrr1_L_L = 713,
|
||||
TriCore_MADDRS_Q_rrr1_U_U = 714,
|
||||
TriCore_MADDR_H_rrr1_LL = 715,
|
||||
TriCore_MADDR_H_rrr1_LU = 716,
|
||||
TriCore_MADDR_H_rrr1_UL = 717,
|
||||
TriCore_MADDR_H_rrr1_UL_2 = 718,
|
||||
TriCore_MADDR_H_rrr1_UU = 719,
|
||||
TriCore_MADDR_H_rrr1_v110 = 720,
|
||||
TriCore_MADDR_Q_rrr1 = 721,
|
||||
TriCore_MADDR_Q_rrr1_L_L = 722,
|
||||
TriCore_MADDR_Q_rrr1_U_U = 723,
|
||||
TriCore_MADDSUMS_H_rrr1_LL = 724,
|
||||
TriCore_MADDSUMS_H_rrr1_LU = 725,
|
||||
TriCore_MADDSUMS_H_rrr1_UL = 726,
|
||||
TriCore_MADDSUMS_H_rrr1_UU = 727,
|
||||
TriCore_MADDSUM_H_rrr1_LL = 728,
|
||||
TriCore_MADDSUM_H_rrr1_LU = 729,
|
||||
TriCore_MADDSUM_H_rrr1_UL = 730,
|
||||
TriCore_MADDSUM_H_rrr1_UU = 731,
|
||||
TriCore_MADDSURS_H_rrr1_LL = 732,
|
||||
TriCore_MADDSURS_H_rrr1_LU = 733,
|
||||
TriCore_MADDSURS_H_rrr1_UL = 734,
|
||||
TriCore_MADDSURS_H_rrr1_UU = 735,
|
||||
TriCore_MADDSUR_H_rrr1_LL = 736,
|
||||
TriCore_MADDSUR_H_rrr1_LU = 737,
|
||||
TriCore_MADDSUR_H_rrr1_UL = 738,
|
||||
TriCore_MADDSUR_H_rrr1_UU = 739,
|
||||
TriCore_MADDSUS_H_rrr1_LL = 740,
|
||||
TriCore_MADDSUS_H_rrr1_LU = 741,
|
||||
TriCore_MADDSUS_H_rrr1_UL = 742,
|
||||
TriCore_MADDSUS_H_rrr1_UU = 743,
|
||||
TriCore_MADDSU_H_rrr1_LL = 744,
|
||||
TriCore_MADDSU_H_rrr1_LU = 745,
|
||||
TriCore_MADDSU_H_rrr1_UL = 746,
|
||||
TriCore_MADDSU_H_rrr1_UU = 747,
|
||||
TriCore_MADDS_H_rrr1_LL = 748,
|
||||
TriCore_MADDS_H_rrr1_LU = 749,
|
||||
TriCore_MADDS_H_rrr1_UL = 750,
|
||||
@ -882,317 +882,319 @@
|
||||
TriCore_MSUBRS_H_rrr1_LU = 871,
|
||||
TriCore_MSUBRS_H_rrr1_UL = 872,
|
||||
TriCore_MSUBRS_H_rrr1_UU = 873,
|
||||
TriCore_MSUBRS_Q_rrr1_L_L = 874,
|
||||
TriCore_MSUBRS_Q_rrr1_U_U = 875,
|
||||
TriCore_MSUBR_H_rrr1_DcEdDaDbUL = 876,
|
||||
TriCore_MSUBR_H_rrr1_LL = 877,
|
||||
TriCore_MSUBR_H_rrr1_LU = 878,
|
||||
TriCore_MSUBR_H_rrr1_UL = 879,
|
||||
TriCore_MSUBR_H_rrr1_UU = 880,
|
||||
TriCore_MSUBR_Q_rrr1_L_L = 881,
|
||||
TriCore_MSUBR_Q_rrr1_U_U = 882,
|
||||
TriCore_MSUBS_H_rrr1_LL = 883,
|
||||
TriCore_MSUBS_H_rrr1_LU = 884,
|
||||
TriCore_MSUBS_H_rrr1_UL = 885,
|
||||
TriCore_MSUBS_H_rrr1_UU = 886,
|
||||
TriCore_MSUBS_H_rrr1_v110 = 887,
|
||||
TriCore_MSUBS_Q_rrr1 = 888,
|
||||
TriCore_MSUBS_Q_rrr1_L = 889,
|
||||
TriCore_MSUBS_Q_rrr1_L_L = 890,
|
||||
TriCore_MSUBS_Q_rrr1_U = 891,
|
||||
TriCore_MSUBS_Q_rrr1_U_U = 892,
|
||||
TriCore_MSUBS_Q_rrr1_e = 893,
|
||||
TriCore_MSUBS_Q_rrr1_e_L = 894,
|
||||
TriCore_MSUBS_Q_rrr1_e_L_L = 895,
|
||||
TriCore_MSUBS_Q_rrr1_e_U = 896,
|
||||
TriCore_MSUBS_Q_rrr1_e_U_U = 897,
|
||||
TriCore_MSUBS_U_rcr = 898,
|
||||
TriCore_MSUBS_U_rcr_e = 899,
|
||||
TriCore_MSUBS_U_rrr2 = 900,
|
||||
TriCore_MSUBS_U_rrr2_e = 901,
|
||||
TriCore_MSUBS_rcr = 902,
|
||||
TriCore_MSUBS_rcr_e = 903,
|
||||
TriCore_MSUBS_rrr2 = 904,
|
||||
TriCore_MSUBS_rrr2_e = 905,
|
||||
TriCore_MSUB_F_rrr = 906,
|
||||
TriCore_MSUB_H_rrr1_LL = 907,
|
||||
TriCore_MSUB_H_rrr1_LU = 908,
|
||||
TriCore_MSUB_H_rrr1_UL = 909,
|
||||
TriCore_MSUB_H_rrr1_UU = 910,
|
||||
TriCore_MSUB_H_rrr1_v110 = 911,
|
||||
TriCore_MSUB_Q_rrr1 = 912,
|
||||
TriCore_MSUB_Q_rrr1_L = 913,
|
||||
TriCore_MSUB_Q_rrr1_L_L = 914,
|
||||
TriCore_MSUB_Q_rrr1_U = 915,
|
||||
TriCore_MSUB_Q_rrr1_U_U = 916,
|
||||
TriCore_MSUB_Q_rrr1_e = 917,
|
||||
TriCore_MSUB_Q_rrr1_e_L = 918,
|
||||
TriCore_MSUB_Q_rrr1_e_L_L = 919,
|
||||
TriCore_MSUB_Q_rrr1_e_U = 920,
|
||||
TriCore_MSUB_Q_rrr1_e_U_U = 921,
|
||||
TriCore_MSUB_U_rcr = 922,
|
||||
TriCore_MSUB_U_rrr2 = 923,
|
||||
TriCore_MSUB_rcr = 924,
|
||||
TriCore_MSUB_rcr_e = 925,
|
||||
TriCore_MSUB_rrr2 = 926,
|
||||
TriCore_MSUB_rrr2_e = 927,
|
||||
TriCore_MTCR_rlc = 928,
|
||||
TriCore_MULM_H_rr1_LL2e = 929,
|
||||
TriCore_MULM_H_rr1_LU2e = 930,
|
||||
TriCore_MULM_H_rr1_UL2e = 931,
|
||||
TriCore_MULM_H_rr1_UU2e = 932,
|
||||
TriCore_MULR_H_rr1_LL2e = 933,
|
||||
TriCore_MULR_H_rr1_LU2e = 934,
|
||||
TriCore_MULR_H_rr1_UL2e = 935,
|
||||
TriCore_MULR_H_rr1_UU2e = 936,
|
||||
TriCore_MULR_Q_rr1_2LL = 937,
|
||||
TriCore_MULR_Q_rr1_2UU = 938,
|
||||
TriCore_MULS_U_rc = 939,
|
||||
TriCore_MULS_U_rr2 = 940,
|
||||
TriCore_MULS_rc = 941,
|
||||
TriCore_MULS_rr2 = 942,
|
||||
TriCore_MUL_F_rrr = 943,
|
||||
TriCore_MUL_H_rr1_LL2e = 944,
|
||||
TriCore_MUL_H_rr1_LU2e = 945,
|
||||
TriCore_MUL_H_rr1_UL2e = 946,
|
||||
TriCore_MUL_H_rr1_UU2e = 947,
|
||||
TriCore_MUL_Q_rr1_2LL = 948,
|
||||
TriCore_MUL_Q_rr1_2UU = 949,
|
||||
TriCore_MUL_Q_rr1_2_L = 950,
|
||||
TriCore_MUL_Q_rr1_2_Le = 951,
|
||||
TriCore_MUL_Q_rr1_2_U = 952,
|
||||
TriCore_MUL_Q_rr1_2_Ue = 953,
|
||||
TriCore_MUL_Q_rr1_2__ = 954,
|
||||
TriCore_MUL_Q_rr1_2__e = 955,
|
||||
TriCore_MUL_U_rc = 956,
|
||||
TriCore_MUL_U_rr2 = 957,
|
||||
TriCore_MUL_rc = 958,
|
||||
TriCore_MUL_rc_e = 959,
|
||||
TriCore_MUL_rr2 = 960,
|
||||
TriCore_MUL_rr2_e = 961,
|
||||
TriCore_MUL_srr = 962,
|
||||
TriCore_NAND_T = 963,
|
||||
TriCore_NAND_rc = 964,
|
||||
TriCore_NAND_rr = 965,
|
||||
TriCore_NEZ_A = 966,
|
||||
TriCore_NE_A = 967,
|
||||
TriCore_NE_rc = 968,
|
||||
TriCore_NE_rr = 969,
|
||||
TriCore_NOP_sr = 970,
|
||||
TriCore_NOP_sys = 971,
|
||||
TriCore_NOR_T = 972,
|
||||
TriCore_NOR_rc = 973,
|
||||
TriCore_NOR_rr = 974,
|
||||
TriCore_NOT_sr = 975,
|
||||
TriCore_ORN_T = 976,
|
||||
TriCore_ORN_rc = 977,
|
||||
TriCore_ORN_rr = 978,
|
||||
TriCore_OR_ANDN_T = 979,
|
||||
TriCore_OR_AND_T = 980,
|
||||
TriCore_OR_EQ_rc = 981,
|
||||
TriCore_OR_EQ_rr = 982,
|
||||
TriCore_OR_GE_U_rc = 983,
|
||||
TriCore_OR_GE_U_rr = 984,
|
||||
TriCore_OR_GE_rc = 985,
|
||||
TriCore_OR_GE_rr = 986,
|
||||
TriCore_OR_LT_U_rc = 987,
|
||||
TriCore_OR_LT_U_rr = 988,
|
||||
TriCore_OR_LT_rc = 989,
|
||||
TriCore_OR_LT_rr = 990,
|
||||
TriCore_OR_NE_rc = 991,
|
||||
TriCore_OR_NE_rr = 992,
|
||||
TriCore_OR_NOR_T = 993,
|
||||
TriCore_OR_OR_T = 994,
|
||||
TriCore_OR_T = 995,
|
||||
TriCore_OR_rc = 996,
|
||||
TriCore_OR_rr = 997,
|
||||
TriCore_OR_sc = 998,
|
||||
TriCore_OR_srr = 999,
|
||||
TriCore_PACK_rrr = 1000,
|
||||
TriCore_PARITY_rr = 1001,
|
||||
TriCore_POPCNT_W_rr = 1002,
|
||||
TriCore_Q31TOF_rr = 1003,
|
||||
TriCore_QSEED_F_rr = 1004,
|
||||
TriCore_RESTORE_sys = 1005,
|
||||
TriCore_RET_sr = 1006,
|
||||
TriCore_RET_sys = 1007,
|
||||
TriCore_RFE_sr = 1008,
|
||||
TriCore_RFE_sys = 1009,
|
||||
TriCore_RFM_sys = 1010,
|
||||
TriCore_RSLCX_sys = 1011,
|
||||
TriCore_RSTV_sys = 1012,
|
||||
TriCore_RSUBS_U_rc = 1013,
|
||||
TriCore_RSUBS_rc = 1014,
|
||||
TriCore_RSUB_rc = 1015,
|
||||
TriCore_RSUB_sr = 1016,
|
||||
TriCore_SAT_BU_rr = 1017,
|
||||
TriCore_SAT_BU_sr = 1018,
|
||||
TriCore_SAT_B_rr = 1019,
|
||||
TriCore_SAT_B_sr = 1020,
|
||||
TriCore_SAT_HU_rr = 1021,
|
||||
TriCore_SAT_HU_sr = 1022,
|
||||
TriCore_SAT_H_rr = 1023,
|
||||
TriCore_SAT_H_sr = 1024,
|
||||
TriCore_SELN_rcr = 1025,
|
||||
TriCore_SELN_rrr = 1026,
|
||||
TriCore_SEL_rcr = 1027,
|
||||
TriCore_SEL_rrr = 1028,
|
||||
TriCore_SHAS_rc = 1029,
|
||||
TriCore_SHAS_rr = 1030,
|
||||
TriCore_SHA_H_rc = 1031,
|
||||
TriCore_SHA_H_rr = 1032,
|
||||
TriCore_SHA_rc = 1033,
|
||||
TriCore_SHA_rr = 1034,
|
||||
TriCore_SHA_src = 1035,
|
||||
TriCore_SHUFFLE_rc = 1036,
|
||||
TriCore_SH_ANDN_T = 1037,
|
||||
TriCore_SH_AND_T = 1038,
|
||||
TriCore_SH_EQ_rc = 1039,
|
||||
TriCore_SH_EQ_rr = 1040,
|
||||
TriCore_SH_GE_U_rc = 1041,
|
||||
TriCore_SH_GE_U_rr = 1042,
|
||||
TriCore_SH_GE_rc = 1043,
|
||||
TriCore_SH_GE_rr = 1044,
|
||||
TriCore_SH_H_rc = 1045,
|
||||
TriCore_SH_H_rr = 1046,
|
||||
TriCore_SH_LT_U_rc = 1047,
|
||||
TriCore_SH_LT_U_rr = 1048,
|
||||
TriCore_SH_LT_rc = 1049,
|
||||
TriCore_SH_LT_rr = 1050,
|
||||
TriCore_SH_NAND_T = 1051,
|
||||
TriCore_SH_NE_rc = 1052,
|
||||
TriCore_SH_NE_rr = 1053,
|
||||
TriCore_SH_NOR_T = 1054,
|
||||
TriCore_SH_ORN_T = 1055,
|
||||
TriCore_SH_OR_T = 1056,
|
||||
TriCore_SH_XNOR_T = 1057,
|
||||
TriCore_SH_XOR_T = 1058,
|
||||
TriCore_SH_rc = 1059,
|
||||
TriCore_SH_rr = 1060,
|
||||
TriCore_SH_src = 1061,
|
||||
TriCore_STLCX_abs = 1062,
|
||||
TriCore_STLCX_bo_bso = 1063,
|
||||
TriCore_STUCX_abs = 1064,
|
||||
TriCore_STUCX_bo_bso = 1065,
|
||||
TriCore_ST_A_abs = 1066,
|
||||
TriCore_ST_A_bo_bso = 1067,
|
||||
TriCore_ST_A_bo_c = 1068,
|
||||
TriCore_ST_A_bo_pos = 1069,
|
||||
TriCore_ST_A_bo_pre = 1070,
|
||||
TriCore_ST_A_bo_r = 1071,
|
||||
TriCore_ST_A_bol = 1072,
|
||||
TriCore_ST_A_sc = 1073,
|
||||
TriCore_ST_A_sro = 1074,
|
||||
TriCore_ST_A_ssr = 1075,
|
||||
TriCore_ST_A_ssr_pos = 1076,
|
||||
TriCore_ST_A_ssro = 1077,
|
||||
TriCore_ST_B_abs = 1078,
|
||||
TriCore_ST_B_bo_bso = 1079,
|
||||
TriCore_ST_B_bo_c = 1080,
|
||||
TriCore_ST_B_bo_pos = 1081,
|
||||
TriCore_ST_B_bo_pre = 1082,
|
||||
TriCore_ST_B_bo_r = 1083,
|
||||
TriCore_ST_B_bol = 1084,
|
||||
TriCore_ST_B_sro = 1085,
|
||||
TriCore_ST_B_ssr = 1086,
|
||||
TriCore_ST_B_ssr_pos = 1087,
|
||||
TriCore_ST_B_ssro = 1088,
|
||||
TriCore_ST_DA_abs = 1089,
|
||||
TriCore_ST_DA_bo_bso = 1090,
|
||||
TriCore_ST_DA_bo_c = 1091,
|
||||
TriCore_ST_DA_bo_pos = 1092,
|
||||
TriCore_ST_DA_bo_pre = 1093,
|
||||
TriCore_ST_DA_bo_r = 1094,
|
||||
TriCore_ST_D_abs = 1095,
|
||||
TriCore_ST_D_bo_bso = 1096,
|
||||
TriCore_ST_D_bo_c = 1097,
|
||||
TriCore_ST_D_bo_pos = 1098,
|
||||
TriCore_ST_D_bo_pre = 1099,
|
||||
TriCore_ST_D_bo_r = 1100,
|
||||
TriCore_ST_H_abs = 1101,
|
||||
TriCore_ST_H_bo_bso = 1102,
|
||||
TriCore_ST_H_bo_c = 1103,
|
||||
TriCore_ST_H_bo_pos = 1104,
|
||||
TriCore_ST_H_bo_pre = 1105,
|
||||
TriCore_ST_H_bo_r = 1106,
|
||||
TriCore_ST_H_bol = 1107,
|
||||
TriCore_ST_H_sro = 1108,
|
||||
TriCore_ST_H_ssr = 1109,
|
||||
TriCore_ST_H_ssr_pos = 1110,
|
||||
TriCore_ST_H_ssro = 1111,
|
||||
TriCore_ST_Q_abs = 1112,
|
||||
TriCore_ST_Q_bo_bso = 1113,
|
||||
TriCore_ST_Q_bo_c = 1114,
|
||||
TriCore_ST_Q_bo_pos = 1115,
|
||||
TriCore_ST_Q_bo_pre = 1116,
|
||||
TriCore_ST_Q_bo_r = 1117,
|
||||
TriCore_ST_T = 1118,
|
||||
TriCore_ST_W_abs = 1119,
|
||||
TriCore_ST_W_bo_bso = 1120,
|
||||
TriCore_ST_W_bo_c = 1121,
|
||||
TriCore_ST_W_bo_pos = 1122,
|
||||
TriCore_ST_W_bo_pre = 1123,
|
||||
TriCore_ST_W_bo_r = 1124,
|
||||
TriCore_ST_W_bol = 1125,
|
||||
TriCore_ST_W_sro = 1126,
|
||||
TriCore_ST_W_ssr = 1127,
|
||||
TriCore_ST_W_ssr_pos = 1128,
|
||||
TriCore_ST_W_ssro = 1129,
|
||||
TriCore_SUBC_rr = 1130,
|
||||
TriCore_SUBS_HU_rr = 1131,
|
||||
TriCore_SUBS_H_rr = 1132,
|
||||
TriCore_SUBS_U_rr = 1133,
|
||||
TriCore_SUBS_rr = 1134,
|
||||
TriCore_SUBS_srr = 1135,
|
||||
TriCore_SUBX_rr = 1136,
|
||||
TriCore_SUB_A_rr = 1137,
|
||||
TriCore_SUB_A_sc = 1138,
|
||||
TriCore_SUB_B_rr = 1139,
|
||||
TriCore_SUB_F_rrr = 1140,
|
||||
TriCore_SUB_H_rr = 1141,
|
||||
TriCore_SUB_rr = 1142,
|
||||
TriCore_SUB_srr = 1143,
|
||||
TriCore_SUB_srr_15a = 1144,
|
||||
TriCore_SUB_srr_a15 = 1145,
|
||||
TriCore_SVLCX_sys = 1146,
|
||||
TriCore_SWAPMSK_W_bo_bso = 1147,
|
||||
TriCore_SWAPMSK_W_bo_c = 1148,
|
||||
TriCore_SWAPMSK_W_bo_pos = 1149,
|
||||
TriCore_SWAPMSK_W_bo_pre = 1150,
|
||||
TriCore_SWAPMSK_W_bo_r = 1151,
|
||||
TriCore_SWAP_W_abs = 1152,
|
||||
TriCore_SWAP_W_bo_bso = 1153,
|
||||
TriCore_SWAP_W_bo_c = 1154,
|
||||
TriCore_SWAP_W_bo_pos = 1155,
|
||||
TriCore_SWAP_W_bo_pre = 1156,
|
||||
TriCore_SWAP_W_bo_r = 1157,
|
||||
TriCore_SYSCALL_rc = 1158,
|
||||
TriCore_TRAPSV_sys = 1159,
|
||||
TriCore_TRAPV_sys = 1160,
|
||||
TriCore_UNPACK_rr = 1161,
|
||||
TriCore_UPDFL_rr = 1162,
|
||||
TriCore_UTOF_rr = 1163,
|
||||
TriCore_WAIT_sys = 1164,
|
||||
TriCore_XNOR_T = 1165,
|
||||
TriCore_XNOR_rc = 1166,
|
||||
TriCore_XNOR_rr = 1167,
|
||||
TriCore_XOR_EQ_rc = 1168,
|
||||
TriCore_XOR_EQ_rr = 1169,
|
||||
TriCore_XOR_GE_U_rc = 1170,
|
||||
TriCore_XOR_GE_U_rr = 1171,
|
||||
TriCore_XOR_GE_rc = 1172,
|
||||
TriCore_XOR_GE_rr = 1173,
|
||||
TriCore_XOR_LT_U_rc = 1174,
|
||||
TriCore_XOR_LT_U_rr = 1175,
|
||||
TriCore_XOR_LT_rc = 1176,
|
||||
TriCore_XOR_LT_rr = 1177,
|
||||
TriCore_XOR_NE_rc = 1178,
|
||||
TriCore_XOR_NE_rr = 1179,
|
||||
TriCore_XOR_T = 1180,
|
||||
TriCore_XOR_rc = 1181,
|
||||
TriCore_XOR_rr = 1182,
|
||||
TriCore_XOR_srr = 1183,
|
||||
INSTRUCTION_LIST_END = 1184
|
||||
TriCore_MSUBRS_Q_rrr1 = 874,
|
||||
TriCore_MSUBRS_Q_rrr1_L_L = 875,
|
||||
TriCore_MSUBRS_Q_rrr1_U_U = 876,
|
||||
TriCore_MSUBR_H_rrr1_DcEdDaDbUL = 877,
|
||||
TriCore_MSUBR_H_rrr1_LL = 878,
|
||||
TriCore_MSUBR_H_rrr1_LU = 879,
|
||||
TriCore_MSUBR_H_rrr1_UL = 880,
|
||||
TriCore_MSUBR_H_rrr1_UU = 881,
|
||||
TriCore_MSUBR_Q_rrr1 = 882,
|
||||
TriCore_MSUBR_Q_rrr1_L_L = 883,
|
||||
TriCore_MSUBR_Q_rrr1_U_U = 884,
|
||||
TriCore_MSUBS_H_rrr1_LL = 885,
|
||||
TriCore_MSUBS_H_rrr1_LU = 886,
|
||||
TriCore_MSUBS_H_rrr1_UL = 887,
|
||||
TriCore_MSUBS_H_rrr1_UU = 888,
|
||||
TriCore_MSUBS_H_rrr1_v110 = 889,
|
||||
TriCore_MSUBS_Q_rrr1 = 890,
|
||||
TriCore_MSUBS_Q_rrr1_L = 891,
|
||||
TriCore_MSUBS_Q_rrr1_L_L = 892,
|
||||
TriCore_MSUBS_Q_rrr1_U = 893,
|
||||
TriCore_MSUBS_Q_rrr1_U_U = 894,
|
||||
TriCore_MSUBS_Q_rrr1_e = 895,
|
||||
TriCore_MSUBS_Q_rrr1_e_L = 896,
|
||||
TriCore_MSUBS_Q_rrr1_e_L_L = 897,
|
||||
TriCore_MSUBS_Q_rrr1_e_U = 898,
|
||||
TriCore_MSUBS_Q_rrr1_e_U_U = 899,
|
||||
TriCore_MSUBS_U_rcr = 900,
|
||||
TriCore_MSUBS_U_rcr_e = 901,
|
||||
TriCore_MSUBS_U_rrr2 = 902,
|
||||
TriCore_MSUBS_U_rrr2_e = 903,
|
||||
TriCore_MSUBS_rcr = 904,
|
||||
TriCore_MSUBS_rcr_e = 905,
|
||||
TriCore_MSUBS_rrr2 = 906,
|
||||
TriCore_MSUBS_rrr2_e = 907,
|
||||
TriCore_MSUB_F_rrr = 908,
|
||||
TriCore_MSUB_H_rrr1_LL = 909,
|
||||
TriCore_MSUB_H_rrr1_LU = 910,
|
||||
TriCore_MSUB_H_rrr1_UL = 911,
|
||||
TriCore_MSUB_H_rrr1_UU = 912,
|
||||
TriCore_MSUB_H_rrr1_v110 = 913,
|
||||
TriCore_MSUB_Q_rrr1 = 914,
|
||||
TriCore_MSUB_Q_rrr1_L = 915,
|
||||
TriCore_MSUB_Q_rrr1_L_L = 916,
|
||||
TriCore_MSUB_Q_rrr1_U = 917,
|
||||
TriCore_MSUB_Q_rrr1_U_U = 918,
|
||||
TriCore_MSUB_Q_rrr1_e = 919,
|
||||
TriCore_MSUB_Q_rrr1_e_L = 920,
|
||||
TriCore_MSUB_Q_rrr1_e_L_L = 921,
|
||||
TriCore_MSUB_Q_rrr1_e_U = 922,
|
||||
TriCore_MSUB_Q_rrr1_e_U_U = 923,
|
||||
TriCore_MSUB_U_rcr = 924,
|
||||
TriCore_MSUB_U_rrr2 = 925,
|
||||
TriCore_MSUB_rcr = 926,
|
||||
TriCore_MSUB_rcr_e = 927,
|
||||
TriCore_MSUB_rrr2 = 928,
|
||||
TriCore_MSUB_rrr2_e = 929,
|
||||
TriCore_MTCR_rlc = 930,
|
||||
TriCore_MULM_H_rr1_LL2e = 931,
|
||||
TriCore_MULM_H_rr1_LU2e = 932,
|
||||
TriCore_MULM_H_rr1_UL2e = 933,
|
||||
TriCore_MULM_H_rr1_UU2e = 934,
|
||||
TriCore_MULR_H_rr1_LL2e = 935,
|
||||
TriCore_MULR_H_rr1_LU2e = 936,
|
||||
TriCore_MULR_H_rr1_UL2e = 937,
|
||||
TriCore_MULR_H_rr1_UU2e = 938,
|
||||
TriCore_MULR_Q_rr1_2LL = 939,
|
||||
TriCore_MULR_Q_rr1_2UU = 940,
|
||||
TriCore_MULS_U_rc = 941,
|
||||
TriCore_MULS_U_rr2 = 942,
|
||||
TriCore_MULS_rc = 943,
|
||||
TriCore_MULS_rr2 = 944,
|
||||
TriCore_MUL_F_rrr = 945,
|
||||
TriCore_MUL_H_rr1_LL2e = 946,
|
||||
TriCore_MUL_H_rr1_LU2e = 947,
|
||||
TriCore_MUL_H_rr1_UL2e = 948,
|
||||
TriCore_MUL_H_rr1_UU2e = 949,
|
||||
TriCore_MUL_Q_rr1_2LL = 950,
|
||||
TriCore_MUL_Q_rr1_2UU = 951,
|
||||
TriCore_MUL_Q_rr1_2_L = 952,
|
||||
TriCore_MUL_Q_rr1_2_Le = 953,
|
||||
TriCore_MUL_Q_rr1_2_U = 954,
|
||||
TriCore_MUL_Q_rr1_2_Ue = 955,
|
||||
TriCore_MUL_Q_rr1_2__ = 956,
|
||||
TriCore_MUL_Q_rr1_2__e = 957,
|
||||
TriCore_MUL_U_rc = 958,
|
||||
TriCore_MUL_U_rr2 = 959,
|
||||
TriCore_MUL_rc = 960,
|
||||
TriCore_MUL_rc_e = 961,
|
||||
TriCore_MUL_rr2 = 962,
|
||||
TriCore_MUL_rr2_e = 963,
|
||||
TriCore_MUL_srr = 964,
|
||||
TriCore_NAND_T = 965,
|
||||
TriCore_NAND_rc = 966,
|
||||
TriCore_NAND_rr = 967,
|
||||
TriCore_NEZ_A = 968,
|
||||
TriCore_NE_A = 969,
|
||||
TriCore_NE_rc = 970,
|
||||
TriCore_NE_rr = 971,
|
||||
TriCore_NOP_sr = 972,
|
||||
TriCore_NOP_sys = 973,
|
||||
TriCore_NOR_T = 974,
|
||||
TriCore_NOR_rc = 975,
|
||||
TriCore_NOR_rr = 976,
|
||||
TriCore_NOT_sr = 977,
|
||||
TriCore_ORN_T = 978,
|
||||
TriCore_ORN_rc = 979,
|
||||
TriCore_ORN_rr = 980,
|
||||
TriCore_OR_ANDN_T = 981,
|
||||
TriCore_OR_AND_T = 982,
|
||||
TriCore_OR_EQ_rc = 983,
|
||||
TriCore_OR_EQ_rr = 984,
|
||||
TriCore_OR_GE_U_rc = 985,
|
||||
TriCore_OR_GE_U_rr = 986,
|
||||
TriCore_OR_GE_rc = 987,
|
||||
TriCore_OR_GE_rr = 988,
|
||||
TriCore_OR_LT_U_rc = 989,
|
||||
TriCore_OR_LT_U_rr = 990,
|
||||
TriCore_OR_LT_rc = 991,
|
||||
TriCore_OR_LT_rr = 992,
|
||||
TriCore_OR_NE_rc = 993,
|
||||
TriCore_OR_NE_rr = 994,
|
||||
TriCore_OR_NOR_T = 995,
|
||||
TriCore_OR_OR_T = 996,
|
||||
TriCore_OR_T = 997,
|
||||
TriCore_OR_rc = 998,
|
||||
TriCore_OR_rr = 999,
|
||||
TriCore_OR_sc = 1000,
|
||||
TriCore_OR_srr = 1001,
|
||||
TriCore_PACK_rrr = 1002,
|
||||
TriCore_PARITY_rr = 1003,
|
||||
TriCore_POPCNT_W_rr = 1004,
|
||||
TriCore_Q31TOF_rr = 1005,
|
||||
TriCore_QSEED_F_rr = 1006,
|
||||
TriCore_RESTORE_sys = 1007,
|
||||
TriCore_RET_sr = 1008,
|
||||
TriCore_RET_sys = 1009,
|
||||
TriCore_RFE_sr = 1010,
|
||||
TriCore_RFE_sys = 1011,
|
||||
TriCore_RFM_sys = 1012,
|
||||
TriCore_RSLCX_sys = 1013,
|
||||
TriCore_RSTV_sys = 1014,
|
||||
TriCore_RSUBS_U_rc = 1015,
|
||||
TriCore_RSUBS_rc = 1016,
|
||||
TriCore_RSUB_rc = 1017,
|
||||
TriCore_RSUB_sr = 1018,
|
||||
TriCore_SAT_BU_rr = 1019,
|
||||
TriCore_SAT_BU_sr = 1020,
|
||||
TriCore_SAT_B_rr = 1021,
|
||||
TriCore_SAT_B_sr = 1022,
|
||||
TriCore_SAT_HU_rr = 1023,
|
||||
TriCore_SAT_HU_sr = 1024,
|
||||
TriCore_SAT_H_rr = 1025,
|
||||
TriCore_SAT_H_sr = 1026,
|
||||
TriCore_SELN_rcr = 1027,
|
||||
TriCore_SELN_rrr = 1028,
|
||||
TriCore_SEL_rcr = 1029,
|
||||
TriCore_SEL_rrr = 1030,
|
||||
TriCore_SHAS_rc = 1031,
|
||||
TriCore_SHAS_rr = 1032,
|
||||
TriCore_SHA_H_rc = 1033,
|
||||
TriCore_SHA_H_rr = 1034,
|
||||
TriCore_SHA_rc = 1035,
|
||||
TriCore_SHA_rr = 1036,
|
||||
TriCore_SHA_src = 1037,
|
||||
TriCore_SHUFFLE_rc = 1038,
|
||||
TriCore_SH_ANDN_T = 1039,
|
||||
TriCore_SH_AND_T = 1040,
|
||||
TriCore_SH_EQ_rc = 1041,
|
||||
TriCore_SH_EQ_rr = 1042,
|
||||
TriCore_SH_GE_U_rc = 1043,
|
||||
TriCore_SH_GE_U_rr = 1044,
|
||||
TriCore_SH_GE_rc = 1045,
|
||||
TriCore_SH_GE_rr = 1046,
|
||||
TriCore_SH_H_rc = 1047,
|
||||
TriCore_SH_H_rr = 1048,
|
||||
TriCore_SH_LT_U_rc = 1049,
|
||||
TriCore_SH_LT_U_rr = 1050,
|
||||
TriCore_SH_LT_rc = 1051,
|
||||
TriCore_SH_LT_rr = 1052,
|
||||
TriCore_SH_NAND_T = 1053,
|
||||
TriCore_SH_NE_rc = 1054,
|
||||
TriCore_SH_NE_rr = 1055,
|
||||
TriCore_SH_NOR_T = 1056,
|
||||
TriCore_SH_ORN_T = 1057,
|
||||
TriCore_SH_OR_T = 1058,
|
||||
TriCore_SH_XNOR_T = 1059,
|
||||
TriCore_SH_XOR_T = 1060,
|
||||
TriCore_SH_rc = 1061,
|
||||
TriCore_SH_rr = 1062,
|
||||
TriCore_SH_src = 1063,
|
||||
TriCore_STLCX_abs = 1064,
|
||||
TriCore_STLCX_bo_bso = 1065,
|
||||
TriCore_STUCX_abs = 1066,
|
||||
TriCore_STUCX_bo_bso = 1067,
|
||||
TriCore_ST_A_abs = 1068,
|
||||
TriCore_ST_A_bo_bso = 1069,
|
||||
TriCore_ST_A_bo_c = 1070,
|
||||
TriCore_ST_A_bo_pos = 1071,
|
||||
TriCore_ST_A_bo_pre = 1072,
|
||||
TriCore_ST_A_bo_r = 1073,
|
||||
TriCore_ST_A_bol = 1074,
|
||||
TriCore_ST_A_sc = 1075,
|
||||
TriCore_ST_A_sro = 1076,
|
||||
TriCore_ST_A_ssr = 1077,
|
||||
TriCore_ST_A_ssr_pos = 1078,
|
||||
TriCore_ST_A_ssro = 1079,
|
||||
TriCore_ST_B_abs = 1080,
|
||||
TriCore_ST_B_bo_bso = 1081,
|
||||
TriCore_ST_B_bo_c = 1082,
|
||||
TriCore_ST_B_bo_pos = 1083,
|
||||
TriCore_ST_B_bo_pre = 1084,
|
||||
TriCore_ST_B_bo_r = 1085,
|
||||
TriCore_ST_B_bol = 1086,
|
||||
TriCore_ST_B_sro = 1087,
|
||||
TriCore_ST_B_ssr = 1088,
|
||||
TriCore_ST_B_ssr_pos = 1089,
|
||||
TriCore_ST_B_ssro = 1090,
|
||||
TriCore_ST_DA_abs = 1091,
|
||||
TriCore_ST_DA_bo_bso = 1092,
|
||||
TriCore_ST_DA_bo_c = 1093,
|
||||
TriCore_ST_DA_bo_pos = 1094,
|
||||
TriCore_ST_DA_bo_pre = 1095,
|
||||
TriCore_ST_DA_bo_r = 1096,
|
||||
TriCore_ST_D_abs = 1097,
|
||||
TriCore_ST_D_bo_bso = 1098,
|
||||
TriCore_ST_D_bo_c = 1099,
|
||||
TriCore_ST_D_bo_pos = 1100,
|
||||
TriCore_ST_D_bo_pre = 1101,
|
||||
TriCore_ST_D_bo_r = 1102,
|
||||
TriCore_ST_H_abs = 1103,
|
||||
TriCore_ST_H_bo_bso = 1104,
|
||||
TriCore_ST_H_bo_c = 1105,
|
||||
TriCore_ST_H_bo_pos = 1106,
|
||||
TriCore_ST_H_bo_pre = 1107,
|
||||
TriCore_ST_H_bo_r = 1108,
|
||||
TriCore_ST_H_bol = 1109,
|
||||
TriCore_ST_H_sro = 1110,
|
||||
TriCore_ST_H_ssr = 1111,
|
||||
TriCore_ST_H_ssr_pos = 1112,
|
||||
TriCore_ST_H_ssro = 1113,
|
||||
TriCore_ST_Q_abs = 1114,
|
||||
TriCore_ST_Q_bo_bso = 1115,
|
||||
TriCore_ST_Q_bo_c = 1116,
|
||||
TriCore_ST_Q_bo_pos = 1117,
|
||||
TriCore_ST_Q_bo_pre = 1118,
|
||||
TriCore_ST_Q_bo_r = 1119,
|
||||
TriCore_ST_T = 1120,
|
||||
TriCore_ST_W_abs = 1121,
|
||||
TriCore_ST_W_bo_bso = 1122,
|
||||
TriCore_ST_W_bo_c = 1123,
|
||||
TriCore_ST_W_bo_pos = 1124,
|
||||
TriCore_ST_W_bo_pre = 1125,
|
||||
TriCore_ST_W_bo_r = 1126,
|
||||
TriCore_ST_W_bol = 1127,
|
||||
TriCore_ST_W_sro = 1128,
|
||||
TriCore_ST_W_ssr = 1129,
|
||||
TriCore_ST_W_ssr_pos = 1130,
|
||||
TriCore_ST_W_ssro = 1131,
|
||||
TriCore_SUBC_rr = 1132,
|
||||
TriCore_SUBS_HU_rr = 1133,
|
||||
TriCore_SUBS_H_rr = 1134,
|
||||
TriCore_SUBS_U_rr = 1135,
|
||||
TriCore_SUBS_rr = 1136,
|
||||
TriCore_SUBS_srr = 1137,
|
||||
TriCore_SUBX_rr = 1138,
|
||||
TriCore_SUB_A_rr = 1139,
|
||||
TriCore_SUB_A_sc = 1140,
|
||||
TriCore_SUB_B_rr = 1141,
|
||||
TriCore_SUB_F_rrr = 1142,
|
||||
TriCore_SUB_H_rr = 1143,
|
||||
TriCore_SUB_rr = 1144,
|
||||
TriCore_SUB_srr = 1145,
|
||||
TriCore_SUB_srr_15a = 1146,
|
||||
TriCore_SUB_srr_a15 = 1147,
|
||||
TriCore_SVLCX_sys = 1148,
|
||||
TriCore_SWAPMSK_W_bo_bso = 1149,
|
||||
TriCore_SWAPMSK_W_bo_c = 1150,
|
||||
TriCore_SWAPMSK_W_bo_pos = 1151,
|
||||
TriCore_SWAPMSK_W_bo_pre = 1152,
|
||||
TriCore_SWAPMSK_W_bo_r = 1153,
|
||||
TriCore_SWAP_W_abs = 1154,
|
||||
TriCore_SWAP_W_bo_bso = 1155,
|
||||
TriCore_SWAP_W_bo_c = 1156,
|
||||
TriCore_SWAP_W_bo_pos = 1157,
|
||||
TriCore_SWAP_W_bo_pre = 1158,
|
||||
TriCore_SWAP_W_bo_r = 1159,
|
||||
TriCore_SYSCALL_rc = 1160,
|
||||
TriCore_TRAPSV_sys = 1161,
|
||||
TriCore_TRAPV_sys = 1162,
|
||||
TriCore_UNPACK_rr = 1163,
|
||||
TriCore_UPDFL_rr = 1164,
|
||||
TriCore_UTOF_rr = 1165,
|
||||
TriCore_WAIT_sys = 1166,
|
||||
TriCore_XNOR_T = 1167,
|
||||
TriCore_XNOR_rc = 1168,
|
||||
TriCore_XNOR_rr = 1169,
|
||||
TriCore_XOR_EQ_rc = 1170,
|
||||
TriCore_XOR_EQ_rr = 1171,
|
||||
TriCore_XOR_GE_U_rc = 1172,
|
||||
TriCore_XOR_GE_U_rr = 1173,
|
||||
TriCore_XOR_GE_rc = 1174,
|
||||
TriCore_XOR_GE_rr = 1175,
|
||||
TriCore_XOR_LT_U_rc = 1176,
|
||||
TriCore_XOR_LT_U_rr = 1177,
|
||||
TriCore_XOR_LT_rc = 1178,
|
||||
TriCore_XOR_LT_rr = 1179,
|
||||
TriCore_XOR_NE_rc = 1180,
|
||||
TriCore_XOR_NE_rr = 1181,
|
||||
TriCore_XOR_T = 1182,
|
||||
TriCore_XOR_rc = 1183,
|
||||
TriCore_XOR_rr = 1184,
|
||||
TriCore_XOR_srr = 1185,
|
||||
INSTRUCTION_LIST_END = 1186
|
||||
};
|
||||
|
||||
#endif // GET_INSTRINFO_ENUM
|
||||
@ -1301,8 +1303,8 @@ static const MCOperandInfo OperandInfo98[] = { { TriCore_RPRegClassID, 0, MCOI_O
|
||||
static const MCOperandInfo OperandInfo99[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo100[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo101[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo102[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo103[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo102[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo103[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo104[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo105[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo106[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
@ -2022,19 +2024,23 @@ static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 4, OperandInfo100 },
|
||||
{ 4, OperandInfo101 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
@ -2043,16 +2049,14 @@ static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
@ -2066,14 +2070,12 @@ static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
@ -2093,12 +2095,12 @@ static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
@ -2156,58 +2158,60 @@ static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
@ -2227,11 +2231,11 @@ static const MCInstrDesc TriCoreInsts[] = {
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo103 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo102 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
{ 5, OperandInfo99 },
|
||||
|
||||
@ -1379,18 +1379,27 @@ defm MADD : mIRCR<0x13, 0x01, 0x13, 0x03, "madd">
|
||||
defm MADDS : mIRCR<0x13, 0x05, 0x13, 0x07, "madds">
|
||||
, mIRRR2<0x03, 0x8A, 0x03, 0xEA, "madds">;
|
||||
|
||||
multiclass mIRRR1_LU2<bits<8> prefix, bits<6> ll2, bits<6> lu2,
|
||||
bits<6> ul2, bits<6> uu2,
|
||||
multiclass mIRRR1_LU2<bits<8> prefix, bits<6> ll, bits<6> lu,
|
||||
bits<6> ul, bits<6> uu,
|
||||
string asmstr, RegisterClass rc>{
|
||||
def _rrr1_LL : IRRR1_label<prefix, ll2, asmstr, rc, "LL">;
|
||||
def _rrr1_LU : IRRR1_label<prefix, lu2, asmstr, rc, "LU">;
|
||||
def _rrr1_UL : IRRR1_label<prefix, ul2, asmstr, rc, "UL">;
|
||||
def _rrr1_UU : IRRR1_label<prefix, uu2, asmstr, rc, "UU">;
|
||||
def _rrr1_LL : IRRR1_label<prefix, ll, asmstr, rc, "LL">;
|
||||
def _rrr1_LU : IRRR1_label<prefix, lu, asmstr, rc, "LU">;
|
||||
def _rrr1_UL : IRRR1_label<prefix, ul, asmstr, rc, "UL">;
|
||||
def _rrr1_UU : IRRR1_label<prefix, uu, asmstr, rc, "UU">;
|
||||
}
|
||||
multiclass mIRRR1_E_LU2<bits<8> ll1, bits<6> ll2, bits<6> lu2,
|
||||
bits<6> ul2, bits<6> uu2, string asmstr, bit hasv110=true>{
|
||||
if hasv110 then def _rrr1_v110 : IRRR1<ll1, ul2, asmstr, RE>, NsRequires<[HasV110]>;
|
||||
defm "" : mIRRR1_LU2<ll1, ll2, lu2, ul2, uu2, asmstr, RE>, Requires<[HasV120_UP]>;
|
||||
multiclass mIRRR1_E_LU2<bits<8> pre, bits<6> ll, bits<6> lu,
|
||||
bits<6> ul, bits<6> uu, string asmstr, bit hasv110=true>{
|
||||
if hasv110 then def _rrr1_v110 : IRRR1<pre, ul, asmstr, RE>, NsRequires<[HasV110]>;
|
||||
defm "" : mIRRR1_LU2<pre, ll, lu, ul, uu, asmstr, RE>, Requires<[HasV120_UP]>;
|
||||
}
|
||||
|
||||
multiclass mI_MADDRsh_<bits<8> pre2, bits<6> ul2, bits<8> pre1, bits<6> ll, bits<6> lu,
|
||||
bits<6> ul, bits<6> uu, string asmstr>{
|
||||
def _rrr1_v110: RRR1<pre2, ul2, (outs RD:$d), (ins RD:$s1, RD:$s2, RE:$s3, u2imm:$n),
|
||||
asmstr # " $d, $s3, $s1, $s2, $n", []>, NsRequires<[HasV110]>;
|
||||
def _rrr1_UL_2: RRR1<pre2, ul2, (outs RD:$d), (ins RD:$s1, RD:$s2, RE:$s3, u2imm:$n),
|
||||
asmstr # " $d, $s3, $s1, $s2 UL, $n", []>, Requires<[HasV120_UP]>;
|
||||
defm "" : mIRRR1_LU2<pre1, ll, lu, ul, uu, asmstr, RD>, Requires<[HasV120_UP]>;
|
||||
}
|
||||
|
||||
defm MADD_H : mIRRR1_E_LU2<0x83, 0x1A, 0x19, 0x18, 0x1B, "madd.h">;
|
||||
@ -1420,7 +1429,6 @@ multiclass mI_MADDq_MSUBq_<bits<8> prefix, bits<6> op1, bits<6> op2, bits<6> op3
|
||||
}
|
||||
|
||||
|
||||
|
||||
defm MADD_Q : mI_MADDq_MSUBq_<0x43, 0x02, 0x1B, 0x01, 0x19, 0x00, 0x18, 0x05, 0x1D, 0x04, 0x1C, "madd.q">;
|
||||
defm MADDS_Q : mI_MADDq_MSUBq_<0x43, 0x22, 0x3B, 0x21, 0x39, 0x20, 0x38, 0x25, 0x3D, 0x24, 0x3C, "madds.q">;
|
||||
|
||||
@ -1439,17 +1447,8 @@ defm MADDMS: mIRCR_RRR2<0x13, 0x07, 0x03, 0xEA, "maddms", "_v110">, NsRequires<[
|
||||
defm MADDMS_U: mIRCR_RRR2<0x13, 0x06, 0x03, 0xE8, "maddms.u", "_v110", u9imm>, NsRequires<[HasV110]>;
|
||||
defm MADDMS_H : mIRRR1_E_LU2<0x83, 0x3E, 0x3D, 0x3C, 0x3F, "maddms.h", false>;
|
||||
|
||||
defm MADDR_H : mIRRR1_LU2<0x83, 0x0E, 0x0D, 0x0C, 0x0F, "maddr.h", RD>, Requires<[HasV120_UP]>;
|
||||
defm MADDRS_H : mIRRR1_LU2<0x83, 0x2E, 0x2D, 0x2C, 0x2F, "maddrs.h", RD>, Requires<[HasV120_UP]>;
|
||||
|
||||
// TODO: fixme
|
||||
def MADDR_H_rrr1_v110 : IRRR1<0x43, 0x0E, "maddr.h", RE>, NsRequires<[HasV110]>;
|
||||
def MADDR_H_rrr1_DcEdDaDbUL
|
||||
: RRR1<0x43, 0x1E, (outs RD:$d), (ins RD:$s1, RD:$s2, RE:$s3, u2imm:$n),
|
||||
"maddr.h $d, $s3, $s1, $s2, UL, $n", []>, Requires<[HasV120_UP]>;
|
||||
def MADDRS_H_rrr1_DcEdDaDbUL
|
||||
: RRR1<0x43, 0x3E, (outs RD:$d), (ins RD:$s1, RD:$s2, RE:$s3, u2imm:$n),
|
||||
"maddrs.h $d, $s3, $s1, $s2, UL, $n", []>, Requires<[HasV120_UP]>;
|
||||
defm MADDR_H : mI_MADDRsh_<0x43, 0x1E, 0x83, 0x0E, 0x0D, 0x0C, 0x0F, "maddr.h">;
|
||||
defm MADDRS_H : mI_MADDRsh_<0x43, 0x3E, 0x83, 0x2E, 0x2D, 0x2C, 0x2F, "maddrs.h">;
|
||||
|
||||
multiclass mIRRR1_label2_LL_UU<bits<8> prefix, bits<6> op1, bits<6> op2, string asmstr> {
|
||||
def _rrr1_L_L : IRRR1_label2<prefix, op1, asmstr, RD, "L", "L">, Requires<[HasV120_UP]>;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user