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https://github.com/capstone-engine/capstone.git
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mips: update core
This commit is contained in:
Nguyen Anh Quynh
parent
44cebf2e0b
commit
75ef2426ea
14
Makefile
14
Makefile
@ -39,6 +39,13 @@ LIBNAME = capstone
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LIBOBJ =
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LIBOBJ += cs.o utils.o SStream.o MCInstrDesc.o MCRegisterInfo.o
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ifneq (,$(findstring mips,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_MIPS
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LIBOBJ += arch/Mips/MipsDisassembler.o
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LIBOBJ += arch/Mips/MipsInstPrinter.o
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LIBOBJ += arch/Mips/mapping.o
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LIBOBJ += arch/Mips/module.o
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endif
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ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_POWERPC
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LIBOBJ += arch/PowerPC/PPCDisassembler.o
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@ -61,13 +68,6 @@ ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
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LIBOBJ += arch/X86/X86ATTInstPrinter.o
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LIBOBJ += arch/X86/mapping.o arch/X86/module.o
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endif
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ifneq (,$(findstring mips,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_MIPS
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LIBOBJ += arch/Mips/MipsDisassembler.o
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LIBOBJ += arch/Mips/MipsInstPrinter.o
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LIBOBJ += arch/Mips/mapping.o
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LIBOBJ += arch/Mips/module.o
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endif
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ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_ARM64
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LIBOBJ += arch/AArch64/AArch64BaseInfo.o
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -6,9 +6,10 @@
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|* *|
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\*===----------------------------------------------------------------------===*/
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/* Capstone Disassembler Engine */
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
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#ifdef GET_REGINFO_ENUM
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#undef GET_REGINFO_ENUM
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@ -387,6 +388,7 @@ enum {
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Mips_sub_32_sub_hi_then_sub_32, // 11
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Mips_NUM_TARGET_SUBREGS
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};
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#endif // GET_REGINFO_ENUM
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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@ -397,6 +399,9 @@ enum {
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|* *|
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\*===----------------------------------------------------------------------===*/
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
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#ifdef GET_REGINFO_MC_DESC
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#undef GET_REGINFO_MC_DESC
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@ -821,7 +826,6 @@ static MCRegisterDesc MipsRegDesc[] = { // Descriptors
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{ 747, 148, 1, 0, 2209 },
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};
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// Register classes...
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// CCR Register Class...
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static uint16_t CCR[] = {
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Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31,
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@ -6,11 +6,13 @@
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|* *|
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\*===----------------------------------------------------------------------===*/
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/* Capstone Disassembler Engine */
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
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#ifdef GET_SUBTARGETINFO_ENUM
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#undef GET_SUBTARGETINFO_ENUM
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enum {
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Mips_FeatureBitCount = 1ULL << 0,
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Mips_FeatureCondMov = 1ULL << 1,
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@ -34,6 +36,7 @@ enum {
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Mips_FeatureSingleFloat = 1ULL << 19,
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Mips_FeatureSwap = 1ULL << 20,
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Mips_FeatureVFPU = 1ULL << 21
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};
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#endif // GET_SUBTARGETINFO_ENUM
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@ -28,6 +28,7 @@
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#include "MipsInstPrinter.h"
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static void printUnsignedImm(MCInst *MI, int opNum, SStream *O);
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static bool printAliasInstr(MCInst *MI, SStream *O, void *info);
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static bool printAlias(MCInst *MI, SStream *OS);
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@ -149,6 +150,19 @@ static void printRegName(SStream *OS, unsigned RegNo)
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SStream_concat(OS, "$%s", getRegisterName(RegNo));
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}
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static void printSaveRestore(MCInst *MI, SStream *O)
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{
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unsigned i, e;
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for (i = 0, e = MCInst_getNumOperands(MI); i != e; ++i) {
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if (i != 0)
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SStream_concat(O, ", ");
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if (MCOperand_isReg(MCInst_getOperand(MI, i)))
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printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, i)));
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else
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printUnsignedImm(MI, i, O);
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}
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}
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void Mips_printInst(MCInst *MI, SStream *O, void *info)
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{
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switch (MCInst_getOpcode(MI)) {
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@ -158,6 +172,26 @@ void Mips_printInst(MCInst *MI, SStream *O, void *info)
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SStream_concat(O, ".set\tpush\n");
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SStream_concat(O, ".set\tmips32r2\n");
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break;
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case Mips_Save16:
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SStream_concat(O, "\tsave\t");
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printSaveRestore(MI, O);
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SStream_concat(O, " # 16 bit inst\n");
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return;
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case Mips_SaveX16:
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SStream_concat(O, "\tsave\t");
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printSaveRestore(MI, O);
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SStream_concat(O, "\n");
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return;
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case Mips_Restore16:
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SStream_concat(O, "\trestore\t");
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printSaveRestore(MI, O);
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SStream_concat(O, " # 16 bit inst\n");
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return;
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case Mips_RestoreX16:
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SStream_concat(O, "\trestore\t");
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printSaveRestore(MI, O);
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SStream_concat(O, "\n");
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return;
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}
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// Try to print any aliases first.
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@ -276,7 +276,9 @@ static insn_map insns[] = {
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{ Mips_AndRxRxRy16, MIPS_INS_AND, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
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{ Mips_BALIGN, MIPS_INS_BALIGN, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
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{ Mips_BC1F, MIPS_INS_BC1F, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
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{ Mips_BC1F_MM, MIPS_INS_BC1F, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 },
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{ Mips_BC1T, MIPS_INS_BC1T, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
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{ Mips_BC1T_MM, MIPS_INS_BC1T, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 },
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{ Mips_BCLRI_B, MIPS_INS_BCLRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_BCLRI_D, MIPS_INS_BCLRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_BCLRI_H, MIPS_INS_BCLRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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@ -343,6 +345,7 @@ static insn_map insns[] = {
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{ Mips_BNZ_W, MIPS_INS_BNZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 },
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{ Mips_BPOSGE32, MIPS_INS_BPOSGE32, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 1, 0 },
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{ Mips_BREAK, MIPS_INS_BREAK, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_BREAK_MM, MIPS_INS_BREAK, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_BSELI_B, MIPS_INS_BSELI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_BSEL_V, MIPS_INS_BSEL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_BSETI_B, MIPS_INS_BSETI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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@ -368,7 +371,9 @@ static insn_map insns[] = {
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{ Mips_CEIL_L_S, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CEIL_W_D32, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CEIL_W_D64, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CEIL_W_MM, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_CEIL_W_S, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CEIL_W_S_MM, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_CEQI_B, MIPS_INS_CEQI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_CEQI_D, MIPS_INS_CEQI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_CEQI_H, MIPS_INS_CEQI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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@ -378,6 +383,7 @@ static insn_map insns[] = {
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{ Mips_CEQ_H, MIPS_INS_CEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_CEQ_W, MIPS_INS_CEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_CFC1, MIPS_INS_CFC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CFC1_MM, MIPS_INS_CFC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_CFCMSA, MIPS_INS_CFCMSA, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_CLEI_S_B, MIPS_INS_CLEI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_CLEI_S_D, MIPS_INS_CLEI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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@ -434,21 +440,30 @@ static insn_map insns[] = {
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{ Mips_COPY_U_H, MIPS_INS_COPY_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_COPY_U_W, MIPS_INS_COPY_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_CTC1, MIPS_INS_CTC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CTC1_MM, MIPS_INS_CTC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_CTCMSA, MIPS_INS_CTCMSA, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_CVT_D32_S, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_D32_W, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_D32_W_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_CVT_D64_L, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_D64_S, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_D64_W, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_D_S_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_CVT_L_D64, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_L_D64_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_CVT_L_S, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_L_S_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_CVT_S_D32, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_S_D32_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_CVT_S_D64, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_S_L, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_S_W, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_S_W_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_CVT_W_D32, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_W_D64, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_W_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_CVT_W_S, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_CVT_W_S_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_C_EQ_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_C_EQ_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_C_EQ_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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@ -506,6 +521,7 @@ static insn_map insns[] = {
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{ Mips_DCLO, MIPS_INS_DCLO, { 0 }, { 0 }, { MIPS_GRP_BITCOUNT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_DCLZ, MIPS_INS_DCLZ, { 0 }, { 0 }, { MIPS_GRP_BITCOUNT, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_DERET, MIPS_INS_DERET, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_DERET_MM, MIPS_INS_DERET, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_DEXT, MIPS_INS_DEXT, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_DEXTM, MIPS_INS_DEXTM, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_DEXTU, MIPS_INS_DEXTU, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
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@ -521,6 +537,7 @@ static insn_map insns[] = {
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{ Mips_DIV_U_D, MIPS_INS_DIV_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_DIV_U_H, MIPS_INS_DIV_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_DIV_U_W, MIPS_INS_DIV_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_DI_MM, MIPS_INS_DI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_DMFC0, MIPS_INS_DMFC0, { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 },
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{ Mips_DMFC1, MIPS_INS_DMFC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_DMFC2, MIPS_INS_DMFC2, { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 },
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@ -584,7 +601,9 @@ static insn_map insns[] = {
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{ Mips_DivRxRy16, MIPS_INS_DIV, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
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{ Mips_DivuRxRy16, MIPS_INS_DIVU, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
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{ Mips_EI, MIPS_INS_EI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_EI_MM, MIPS_INS_EI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_ERET, MIPS_INS_ERET, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_ERET_MM, MIPS_INS_ERET, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_EXT, MIPS_INS_EXT, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_EXTP, MIPS_INS_EXTP, { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
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{ Mips_EXTPDP, MIPS_INS_EXTPDP, { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
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@ -601,11 +620,15 @@ static insn_map insns[] = {
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{ Mips_EXT_MM, MIPS_INS_EXT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_FABS_D32, MIPS_INS_ABS, { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_FABS_D64, MIPS_INS_ABS, { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_FABS_MM, MIPS_INS_ABS, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_FABS_S, MIPS_INS_ABS, { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
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{ Mips_FABS_S_MM, MIPS_INS_ABS, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
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{ Mips_FADD_D, MIPS_INS_FADD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
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{ Mips_FADD_D32, MIPS_INS_ADD, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FADD_D64, MIPS_INS_ADD, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FADD_MM, MIPS_INS_ADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FADD_S, MIPS_INS_ADD, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FADD_S_MM, MIPS_INS_ADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FADD_W, MIPS_INS_FADD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FCAF_D, MIPS_INS_FCAF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FCAF_W, MIPS_INS_FCAF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
@ -618,8 +641,10 @@ static insn_map insns[] = {
|
||||
{ Mips_FCLT_D, MIPS_INS_FCLT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FCLT_W, MIPS_INS_FCLT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FCMP_D32, MIPS_INS_C, { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FCMP_D32_MM, MIPS_INS_C, { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FCMP_D64, MIPS_INS_C, { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FCMP_S32, MIPS_INS_C, { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FCMP_S32_MM, MIPS_INS_C, { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FCNE_D, MIPS_INS_FCNE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FCNE_W, MIPS_INS_FCNE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FCOR_D, MIPS_INS_FCOR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
@ -637,7 +662,9 @@ static insn_map insns[] = {
|
||||
{ Mips_FDIV_D, MIPS_INS_FDIV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FDIV_D32, MIPS_INS_DIV, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FDIV_D64, MIPS_INS_DIV, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FDIV_MM, MIPS_INS_DIV, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FDIV_S, MIPS_INS_DIV, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FDIV_S_MM, MIPS_INS_DIV, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FDIV_W, MIPS_INS_FDIV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FEXDO_H, MIPS_INS_FEXDO, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FEXDO_W, MIPS_INS_FEXDO, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
@ -664,7 +691,9 @@ static insn_map insns[] = {
|
||||
{ Mips_FLOOR_L_S, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FLOOR_W_D32, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FLOOR_W_D64, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FLOOR_W_MM, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FLOOR_W_S, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FLOOR_W_S_MM, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FMADD_D, MIPS_INS_FMADD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FMADD_W, MIPS_INS_FMADD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FMAX_A_D, MIPS_INS_FMAX_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
@ -676,18 +705,24 @@ static insn_map insns[] = {
|
||||
{ Mips_FMIN_D, MIPS_INS_FMIN, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FMIN_W, MIPS_INS_FMIN, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FMOV_D32, MIPS_INS_MOV, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FMOV_D32_MM, MIPS_INS_MOV, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FMOV_D64, MIPS_INS_MOV, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FMOV_S, MIPS_INS_MOV, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FMOV_S_MM, MIPS_INS_MOV, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FMSUB_D, MIPS_INS_FMSUB, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FMSUB_W, MIPS_INS_FMSUB, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FMUL_D, MIPS_INS_FMUL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FMUL_D32, MIPS_INS_MUL, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FMUL_D64, MIPS_INS_MUL, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FMUL_MM, MIPS_INS_MUL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FMUL_S, MIPS_INS_MUL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FMUL_S_MM, MIPS_INS_MUL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FMUL_W, MIPS_INS_FMUL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FNEG_D32, MIPS_INS_NEG, { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FNEG_D64, MIPS_INS_NEG, { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FNEG_MM, MIPS_INS_NEG, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FNEG_S, MIPS_INS_NEG, { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FNEG_S_MM, MIPS_INS_NEG, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FRCP_D, MIPS_INS_FRCP, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FRCP_W, MIPS_INS_FRCP, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FRINT_D, MIPS_INS_FRINT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
@ -709,12 +744,16 @@ static insn_map insns[] = {
|
||||
{ Mips_FSQRT_D, MIPS_INS_FSQRT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FSQRT_D32, MIPS_INS_SQRT, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FSQRT_D64, MIPS_INS_SQRT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FSQRT_MM, MIPS_INS_SQRT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FSQRT_S, MIPS_INS_SQRT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FSQRT_S_MM, MIPS_INS_SQRT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FSQRT_W, MIPS_INS_FSQRT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FSUB_D, MIPS_INS_FSUB, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FSUB_D32, MIPS_INS_SUB, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FSUB_D64, MIPS_INS_SUB, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FSUB_MM, MIPS_INS_SUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FSUB_S, MIPS_INS_SUB, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_FSUB_S_MM, MIPS_INS_SUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_FSUB_W, MIPS_INS_FSUB, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FSUEQ_D, MIPS_INS_FSUEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_FSUEQ_W, MIPS_INS_FSUEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
@ -788,7 +827,7 @@ static insn_map insns[] = {
|
||||
{ Mips_JrRa16, MIPS_INS_JR, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 },
|
||||
{ Mips_JrcRa16, MIPS_INS_JRC, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 },
|
||||
{ Mips_JrcRx16, MIPS_INS_JRC, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 },
|
||||
{ Mips_JumpLinkReg16, MIPS_INS_JALRC, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
|
||||
{ Mips_JumpLinkReg16, MIPS_INS_JALRC, { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
|
||||
{ Mips_LB, MIPS_INS_LB, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LB64, MIPS_INS_LB, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LBUX, MIPS_INS_LBUX, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
|
||||
@ -799,6 +838,7 @@ static insn_map insns[] = {
|
||||
{ Mips_LD, MIPS_INS_LD, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LDC1, MIPS_INS_LDC1, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LDC164, MIPS_INS_LDC1, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LDC1_MM, MIPS_INS_LDC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LDC2, MIPS_INS_LDC2, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LDI_B, MIPS_INS_LDI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_LDI_D, MIPS_INS_LDI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
@ -806,7 +846,7 @@ static insn_map insns[] = {
|
||||
{ Mips_LDI_W, MIPS_INS_LDI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_LDL, MIPS_INS_LDL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LDR, MIPS_INS_LDR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LDXC1, MIPS_INS_LDXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LDXC1, MIPS_INS_LDXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LDXC164, MIPS_INS_LDXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LD_B, MIPS_INS_LD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_LD_D, MIPS_INS_LD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
@ -814,6 +854,7 @@ static insn_map insns[] = {
|
||||
{ Mips_LD_W, MIPS_INS_LD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_LEA_ADDiu, MIPS_INS_ADDIU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LEA_ADDiu64, MIPS_INS_DADDIU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LEA_ADDiu_MM, MIPS_INS_ADDIU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LH, MIPS_INS_LH, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LH64, MIPS_INS_LH, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LHX, MIPS_INS_LHX, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
|
||||
@ -821,17 +862,20 @@ static insn_map insns[] = {
|
||||
{ Mips_LHu, MIPS_INS_LHU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LHu64, MIPS_INS_LHU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LHu_MM, MIPS_INS_LHU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LL, MIPS_INS_LL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LL, MIPS_INS_LL, { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LLD, MIPS_INS_LLD, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LL_MM, MIPS_INS_LL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LSA, MIPS_INS_LSA, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_LUXC1, MIPS_INS_LUXC1, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LUXC164, MIPS_INS_LUXC1, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LUXC1_MM, MIPS_INS_LUXC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LUi, MIPS_INS_LUI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LUi64, MIPS_INS_LUI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LUi_MM, MIPS_INS_LUI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LW, MIPS_INS_LW, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LW64, MIPS_INS_LW, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LWC1, MIPS_INS_LWC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LWC1_MM, MIPS_INS_LWC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LWC2, MIPS_INS_LWC2, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LWL, MIPS_INS_LWL, { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LWL64, MIPS_INS_LWL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
@ -841,6 +885,7 @@ static insn_map insns[] = {
|
||||
{ Mips_LWR_MM, MIPS_INS_LWR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LWX, MIPS_INS_LWX, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
|
||||
{ Mips_LWXC1, MIPS_INS_LWXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LWXC1_MM, MIPS_INS_LWXC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LW_MM, MIPS_INS_LW, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_LWu, MIPS_INS_LWU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_LbRxRyOffMemX16, MIPS_INS_LB, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
|
||||
@ -862,12 +907,14 @@ static insn_map insns[] = {
|
||||
{ Mips_MADDV_H, MIPS_INS_MADDV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_MADDV_W, MIPS_INS_MADDV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_MADD_D32, MIPS_INS_MADD, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MADD_D32_MM, MIPS_INS_MADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MADD_D64, MIPS_INS_MADD, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MADD_DSP, MIPS_INS_MADD, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
|
||||
{ Mips_MADD_MM, MIPS_INS_MADD, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MADD_Q_H, MIPS_INS_MADD_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_MADD_Q_W, MIPS_INS_MADD_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_MADD_S, MIPS_INS_MADD, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MADD_S_MM, MIPS_INS_MADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MAQ_SA_W_PHL, MIPS_INS_MAQ_SA, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
|
||||
{ Mips_MAQ_SA_W_PHR, MIPS_INS_MAQ_SA, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
|
||||
{ Mips_MAQ_S_W_PHL, MIPS_INS_MAQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
|
||||
@ -894,8 +941,10 @@ static insn_map insns[] = {
|
||||
{ Mips_MAX_U_W, MIPS_INS_MAX_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_MFC0, MIPS_INS_MFC0, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MFC1, MIPS_INS_MFC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MFC1_MM, MIPS_INS_MFC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MFC2, MIPS_INS_MFC2, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MFHC1, MIPS_INS_MFHC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MFHC1_MM, MIPS_INS_MFHC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MFHI, MIPS_INS_MFHI, { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MFHI64, MIPS_INS_MFHI, { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MFHI_DSP, MIPS_INS_MFHI, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
|
||||
@ -935,37 +984,45 @@ static insn_map insns[] = {
|
||||
{ Mips_MOD_U_W, MIPS_INS_MOD_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_MOVE_V, MIPS_INS_MOVE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_MOVF_D32, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVF_D32_MM, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MOVF_D64, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVF_I, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVF_I64, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_MIPS64, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVF_I_MM, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MOVF_S, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVF_S_MM, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MOVN_I64_D64, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVN_I64_I, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVN_I64_I64, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVN_I64_S, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_MIPS64, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVN_I_D32, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVN_I_D32_MM, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MOVN_I_D64, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVN_I_I, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVN_I_I64, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVN_I_MM, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MOVN_I_S, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVN_I_S_MM, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MOVT_D32, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVT_D32_MM, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MOVT_D64, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVT_I, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVT_I64, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_MIPS64, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVT_I_MM, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MOVT_S, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVT_S_MM, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MOVZ_I64_D64, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVZ_I64_I, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVZ_I64_I64, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVZ_I64_S, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_MIPS64, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVZ_I_D32, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVZ_I_D32_MM, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MOVZ_I_D64, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVZ_I_I, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVZ_I_I64, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVZ_I_MM, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MOVZ_I_S, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MOVZ_I_S_MM, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MSUB, MIPS_INS_MSUB, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MSUBR_Q_H, MIPS_INS_MSUBR_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_MSUBR_Q_W, MIPS_INS_MSUBR_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
@ -977,16 +1034,20 @@ static insn_map insns[] = {
|
||||
{ Mips_MSUBV_H, MIPS_INS_MSUBV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_MSUBV_W, MIPS_INS_MSUBV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_MSUB_D32, MIPS_INS_MSUB, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MSUB_D32_MM, MIPS_INS_MSUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MSUB_D64, MIPS_INS_MSUB, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MSUB_DSP, MIPS_INS_MSUB, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
|
||||
{ Mips_MSUB_MM, MIPS_INS_MSUB, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MSUB_Q_H, MIPS_INS_MSUB_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_MSUB_Q_W, MIPS_INS_MSUB_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_MSUB_S, MIPS_INS_MSUB, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MSUB_S_MM, MIPS_INS_MSUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MTC0, MIPS_INS_MTC0, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MTC1, MIPS_INS_MTC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MTC1_MM, MIPS_INS_MTC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MTC2, MIPS_INS_MTC2, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MTHC1, MIPS_INS_MTHC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MTHC1_MM, MIPS_INS_MTHC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_MTHI, MIPS_INS_MTHI, { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MTHI64, MIPS_INS_MTHI, { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_MTHI_DSP, MIPS_INS_MTHI, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
|
||||
@ -1037,11 +1098,15 @@ static insn_map insns[] = {
|
||||
{ Mips_NLZC_H, MIPS_INS_NLZC, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_NLZC_W, MIPS_INS_NLZC, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_NMADD_D32, MIPS_INS_NMADD, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_NMADD_D32_MM, MIPS_INS_NMADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_NMADD_D64, MIPS_INS_NMADD, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_NMADD_S, MIPS_INS_NMADD, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_NMADD_S_MM, MIPS_INS_NMADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_NMSUB_D32, MIPS_INS_NMSUB, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_NMSUB_D32_MM, MIPS_INS_NMSUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_NMSUB_D64, MIPS_INS_NMSUB, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_NMSUB_S, MIPS_INS_NMSUB, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_NMSUB_S_MM, MIPS_INS_NMSUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_NOR, MIPS_INS_NOR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_NOR64, MIPS_INS_NOR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_NORI_B, MIPS_INS_NORI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
@ -1109,9 +1174,9 @@ static insn_map insns[] = {
|
||||
{ Mips_ROUND_L_S, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_ROUND_W_D32, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_ROUND_W_D64, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_ROUND_W_MM, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_ROUND_W_S, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_RestoreIncSpF16, MIPS_INS_RESTORE, { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
|
||||
{ Mips_RestoreRaF16, MIPS_INS_RESTORE, { MIPS_REG_SP, 0 }, { MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2, MIPS_REG_RA, MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
|
||||
{ Mips_ROUND_W_S_MM, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SAT_S_B, MIPS_INS_SAT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_SAT_S_D, MIPS_INS_SAT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_SAT_S_H, MIPS_INS_SAT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
@ -1123,17 +1188,19 @@ static insn_map insns[] = {
|
||||
{ Mips_SB, MIPS_INS_SB, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SB64, MIPS_INS_SB, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SB_MM, MIPS_INS_SB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SC, MIPS_INS_SC, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SC, MIPS_INS_SC, { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SCD, MIPS_INS_SCD, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SC_MM, MIPS_INS_SC, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SD, MIPS_INS_SD, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SDC1, MIPS_INS_SDC1, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SDC164, MIPS_INS_SDC1, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SDC1_MM, MIPS_INS_SDC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SDC2, MIPS_INS_SDC2, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SDIV, MIPS_INS_DIV, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SDIV_MM, MIPS_INS_DIV, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SDL, MIPS_INS_SDL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SDR, MIPS_INS_SDR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SDXC1, MIPS_INS_SDXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SDXC1, MIPS_INS_SDXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SDXC164, MIPS_INS_SDXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SEB, MIPS_INS_SEB, { 0 }, { 0 }, { MIPS_GRP_SEINREG, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SEB64, MIPS_INS_SEB, { 0 }, { 0 }, { MIPS_GRP_SEINREG, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
@ -1300,9 +1367,11 @@ static insn_map insns[] = {
|
||||
{ Mips_SUBu_MM, MIPS_INS_SUBU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SUXC1, MIPS_INS_SUXC1, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SUXC164, MIPS_INS_SUXC1, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SUXC1_MM, MIPS_INS_SUXC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SW, MIPS_INS_SW, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SW64, MIPS_INS_SW, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SWC1, MIPS_INS_SWC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SWC1_MM, MIPS_INS_SWC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SWC2, MIPS_INS_SWC2, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SWL, MIPS_INS_SWL, { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SWL64, MIPS_INS_SWL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
@ -1311,11 +1380,12 @@ static insn_map insns[] = {
|
||||
{ Mips_SWR64, MIPS_INS_SWR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SWR_MM, MIPS_INS_SWR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SWXC1, MIPS_INS_SWXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SWXC1_MM, MIPS_INS_SWXC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SW_MM, MIPS_INS_SW, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SYNC, MIPS_INS_SYNC, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SYNC_MM, MIPS_INS_SYNC, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SYSCALL, MIPS_INS_SYSCALL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_SaveDecSpF16, MIPS_INS_SAVE, { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
|
||||
{ Mips_SaveRaF16, MIPS_INS_SAVE, { MIPS_REG_RA, MIPS_REG_SP, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
|
||||
{ Mips_SYSCALL_MM, MIPS_INS_SYSCALL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_SbRxRyOffMemX16, MIPS_INS_SB, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
|
||||
{ Mips_SebRx16, MIPS_INS_SEB, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
|
||||
{ Mips_SehRx16, MIPS_INS_SEH, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
|
||||
@ -1360,7 +1430,9 @@ static insn_map insns[] = {
|
||||
{ Mips_TRUNC_L_S, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_TRUNC_W_D32, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_TRUNC_W_D64, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_TRUNC_W_MM, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_TRUNC_W_S, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_TRUNC_W_S_MM, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_TTLTIU, MIPS_INS_TLTIU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_UDIV, MIPS_INS_DIVU, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_UDIV_MM, MIPS_INS_DIVU, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
@ -1369,6 +1441,7 @@ static insn_map insns[] = {
|
||||
{ Mips_VSHF_H, MIPS_INS_VSHF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_VSHF_W, MIPS_INS_VSHF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
|
||||
{ Mips_WAIT, MIPS_INS_WAIT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_WAIT_MM, MIPS_INS_WAIT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
{ Mips_WRDSP, MIPS_INS_WRDSP, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
|
||||
{ Mips_WSBH, MIPS_INS_WSBH, { 0 }, { 0 }, { MIPS_GRP_SWAP, MIPS_GRP_STDENC, 0 }, 0, 0 },
|
||||
{ Mips_WSBH_MM, MIPS_INS_WSBH, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
|
||||
@ -1818,7 +1891,6 @@ static name_map insn_name_maps[] = {
|
||||
{ MIPS_INS_ROTR, "rotr" },
|
||||
{ MIPS_INS_ROTRV, "rotrv" },
|
||||
{ MIPS_INS_ROUND, "round" },
|
||||
{ MIPS_INS_RESTORE, "restore" },
|
||||
{ MIPS_INS_SAT_S, "sat_s" },
|
||||
{ MIPS_INS_SAT_U, "sat_u" },
|
||||
{ MIPS_INS_SB, "sb" },
|
||||
@ -1891,7 +1963,6 @@ static name_map insn_name_maps[] = {
|
||||
{ MIPS_INS_SWXC1, "swxc1" },
|
||||
{ MIPS_INS_SYNC, "sync" },
|
||||
{ MIPS_INS_SYSCALL, "syscall" },
|
||||
{ MIPS_INS_SAVE, "save" },
|
||||
{ MIPS_INS_TEQ, "teq" },
|
||||
{ MIPS_INS_TEQI, "teqi" },
|
||||
{ MIPS_INS_TGE, "tge" },
|
||||
|
||||
@ -593,7 +593,6 @@ typedef enum mips_insn {
|
||||
MIPS_INS_ROTR,
|
||||
MIPS_INS_ROTRV,
|
||||
MIPS_INS_ROUND,
|
||||
MIPS_INS_RESTORE,
|
||||
MIPS_INS_SAT_S,
|
||||
MIPS_INS_SAT_U,
|
||||
MIPS_INS_SB,
|
||||
@ -666,7 +665,6 @@ typedef enum mips_insn {
|
||||
MIPS_INS_SWXC1,
|
||||
MIPS_INS_SYNC,
|
||||
MIPS_INS_SYSCALL,
|
||||
MIPS_INS_SAVE,
|
||||
MIPS_INS_TEQ,
|
||||
MIPS_INS_TEQI,
|
||||
MIPS_INS_TGE,
|
||||
@ -687,7 +685,7 @@ typedef enum mips_insn {
|
||||
MIPS_INS_XOR,
|
||||
MIPS_INS_XORI,
|
||||
|
||||
// some alias instructions
|
||||
//> some alias instructions
|
||||
MIPS_INS_NOP,
|
||||
MIPS_INS_NEGU,
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user