diff --git a/arch/X86/X86GenAsmWriter.inc b/arch/X86/X86GenAsmWriter.inc
index 6d7bd21f8..2b0cf94ff 100644
--- a/arch/X86/X86GenAsmWriter.inc
+++ b/arch/X86/X86GenAsmWriter.inc
@@ -14164,6 +14164,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
 
   // Emit the opcode for the instruction.
   unsigned int opcode = MCInst_getOpcode(MI);
+  //printf("> opcode = %u\n", opcode);
   uint64_t Bits1 = OpInfo[opcode];
   uint64_t Bits2 = OpInfo2[opcode];
   uint64_t Bits = (Bits2 << 32) | Bits1;
diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c
index 99fedc7c9..8f4217647 100644
--- a/arch/X86/X86Mapping.c
+++ b/arch/X86/X86Mapping.c
@@ -47241,6 +47241,7 @@ static struct insn_reg insn_regs_att[] = {
 	{ X86_INSW, X86_REG_DX },
 	{ X86_INSL, X86_REG_DX },
 
+	{ X86_MOV32ao32, X86_REG_EAX },
 	{ X86_MOV64o64a, X86_REG_RAX },
 
 	{ X86_PUSHCS32, X86_REG_CS },
@@ -47356,7 +47357,6 @@ static struct insn_reg insn_regs_intel[] = {
 	{ X86_MOV64o32a, X86_REG_EAX },
 
 	{ X86_MOV16ao16, X86_REG_AX },    // 16-bit A1 1020                  // mov     ax, word ptr [0x2010]
-	{ X86_MOV32ao32, X86_REG_EAX },   // 32-bit A1 10203040              // mov     eax, dword ptr [0x40302010]
 
 	{ X86_MOV64ao32, X86_REG_RAX },   // 64-bit 48 8B04 10203040         // mov     rax, qword ptr [0x40302010]