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feat: Add support for TriCore feature bits and new architectures

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- Add support for new Tricore architectures
- Clean up redundant instructions definitions
- Modify architecture options for the TRICORE mode
- Update disallowed modes for Tricore architecture
This commit is contained in:
billow 2023-04-08 04:04:53 +08:00
parent b9151fb030
commit 7c56b54ebc
No known key found for this signature in database
GPG Key ID: CA735DC44D699DE6
6 changed files with 38 additions and 42 deletions
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27
arch/TriCore/TriCoreDisassembler.c
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@ -169,8 +169,31 @@ static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t A
bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature) {
//TODO: TriCore_getFeatureBits
return true;
switch (mode) {
case CS_MODE_TRICORE_110: {
return feature == TriCore_HasV110Ops;
}
case CS_MODE_TRICORE_120: {
return feature == TriCore_HasV120Ops;
}
case CS_MODE_TRICORE_130: {
return feature == TriCore_HasV130Ops;
}
case CS_MODE_TRICORE_131: {
return feature == TriCore_HasV131Ops;
}
case CS_MODE_TRICORE_160: {
return feature == TriCore_HasV160Ops;
}
case CS_MODE_TRICORE_161: {
return feature == TriCore_HasV161Ops;
}
case CS_MODE_TRICORE_162: {
return feature == TriCore_HasV162Ops;
}
default:
return false;
}
}

35
arch/TriCore/TriCoreDisassembler.h
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@ -12,41 +12,6 @@
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
typedef enum tricore_opcode_arch_val_t
{
TRICORE_GENERIC = 0x00000000,
TRICORE_RIDER_A = 0x00000001,
#define TRICORE_V1_1 TRICORE_RIDER_A
TRICORE_V1_2 = 0x00000002,
TRICORE_V1_3 = 0x00000004,
TRICORE_V1_3_1 = 0x00000100,
TRICORE_V1_6 = 0x00000200,
TRICORE_V1_6_1 = 0x00000400,
TRICORE_V1_6_2 = 0x00000800,
TRICORE_PCP = 0x00000010,
TRICORE_PCP2 = 0x00000020
} TriCoreISA;
/* Some handy definitions for upward/downward compatibility of insns. */
//#define TRICORE_V2_UP TRICORE_V2
#define TRICORE_V1_6_2_UP (TRICORE_V1_6_2)
#define TRICORE_V1_6_1_UP (TRICORE_V1_6_1 | TRICORE_V1_6_2_UP)
#define TRICORE_V1_6_UP (TRICORE_V1_6 | TRICORE_V1_6_1_UP)
#define TRICORE_V1_3_1_UP (TRICORE_V1_3_1 | TRICORE_V1_6_UP)
#define TRICORE_V1_3_UP (TRICORE_V1_3 | TRICORE_V1_3_1_UP)
#define TRICORE_V1_2_UP (TRICORE_V1_2 | TRICORE_V1_3_UP)
#define TRICORE_V1_2_DN TRICORE_V1_2
#define TRICORE_V1_3_DN (TRICORE_V1_3 | TRICORE_V1_2_DN )
#define TRICORE_V1_3_X_DN (TRICORE_V1_3 | TRICORE_V1_2_DN | TRICORE_V1_3_1)
#define TRICORE_V1_3_1_DN (TRICORE_V1_3_1 | TRICORE_V1_3_DN)
#define TRICORE_V1_6_DN (TRICORE_V1_6 | TRICORE_V1_3_1_DN)
#define TRICORE_V1_6_1_DN (TRICORE_V1_6_1 | TRICORE_V1_6_DN)
#define TRICORE_V1_6_2_DN (TRICORE_V1_6_2 | TRICORE_V1_6_1_DN)
void TriCore_init(MCRegisterInfo *MRI);
bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len,

4
cs.c
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@ -248,7 +248,9 @@ static const struct {
{
TRICORE_global_init,
TRICORE_option,
~(CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE),
~(CS_MODE_TRICORE_110 | CS_MODE_TRICORE_120 | CS_MODE_TRICORE_130
| CS_MODE_TRICORE_131 | CS_MODE_TRICORE_160 | CS_MODE_TRICORE_161
| CS_MODE_TRICORE_162 | CS_MODE_BIG_ENDIAN),
},
#else
{ NULL, NULL, 0 },

2
cstool/cstool.c
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@ -105,7 +105,7 @@ static struct {
{ "sh4abe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU },
{ "sh4al-dsp", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU },
{ "sh4al-dspbe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU },
{ "tricore", CS_ARCH_TRICORE, CS_MODE_TRICORE },
{ "tricore", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 },
{ NULL }
};

8
include/capstone/capstone.h
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@ -162,7 +162,13 @@ typedef enum cs_mode {
CS_MODE_SH4A = 1 << 5, ///< SH4A
CS_MODE_SHFPU = 1 << 6, ///< w/ FPU
CS_MODE_SHDSP = 1 << 7, ///< w/ DSP
CS_MODE_TRICORE = 1 << 1, ///< Tricore
CS_MODE_TRICORE_110 = 1 << 1, ///< Tricore 1.1
CS_MODE_TRICORE_120 = 1 << 2, ///< Tricore 1.2
CS_MODE_TRICORE_130 = 1 << 3, ///< Tricore 1.3
CS_MODE_TRICORE_131 = 1 << 4, ///< Tricore 1.3.1
CS_MODE_TRICORE_160 = 1 << 5, ///< Tricore 1.6
CS_MODE_TRICORE_161 = 1 << 6, ///< Tricore 1.6.1
CS_MODE_TRICORE_162 = 1 << 7, ///< Tricore 1.6.2
} cs_mode;
typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size);

4
suite/cstest/src/main.c
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@ -62,7 +62,7 @@ static single_dict arches[] = {
{"CS_MODE_BPF_EXTENDED", CS_MODE_BPF_EXTENDED},
{"CS_MODE_RISCV32", CS_MODE_RISCV32},
{"CS_MODE_RISCV64", CS_MODE_RISCV64},
{"CS_MODE_TRICORE", CS_MODE_TRICORE},
{"CS_MODE_TRICORE", CS_MODE_TRICORE_162},
};
static double_dict options[] = {
@ -109,7 +109,7 @@ static single_dict arches[] = {
{"CS_MODE_M680X_HCS08", CS_OPT_MODE, CS_MODE_M680X_HCS08},
{"CS_MODE_RISCV32", CS_OPT_MODE, CS_MODE_RISCV32},
{"CS_MODE_RISCV64", CS_OPT_MODE, CS_MODE_RISCV64},
{"CS_MODE_TRICORE", CS_OPT_MODE, CS_MODE_TRICORE},
{"CS_MODE_TRICORE", CS_OPT_MODE, CS_MODE_TRICORE_162},
{"CS_OPT_UNSIGNED", CS_OPT_UNSIGNED, CS_OPT_ON},
};