Auto-Sync reproducability + ARM update (#2532)

2024-11-23 05:29:53 +00:00 · 2024-11-21 16:31:27 +00:00 · 2024-11-21 16:31:27 +00:00 · 7d01d7e7a9
commit 7d01d7e7a9
parent 6ad2608dcb
46 changed files with 104237 additions and 233319 deletions
--- a/MCInst.c
+++ b/MCInst.c
@ -244,16 +244,9 @@ void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDescTable, unsign
 	const MCInstrDesc *InstDesc = NULL;
 	const MCOperandInfo *OpInfo = NULL;
 	unsigned short NumOps = 0;
-	if (MI->csh->arch == CS_ARCH_ARM) {
-		// Uses old (pre LLVM 18) indexing method.
-		InstDesc = &InstDescTable[MCInst_getOpcode(MI)];
-		OpInfo = InstDescTable[MCInst_getOpcode(MI)].OpInfo;
-		NumOps = InstDescTable[MCInst_getOpcode(MI)].NumOperands;
-	} else {
 	InstDesc = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size);
-		OpInfo = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size)->OpInfo;
-		NumOps = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size)->NumOperands;
-	}
+	OpInfo = InstDesc->OpInfo;
+	NumOps = InstDesc->NumOperands;

 	for (unsigned i = 0; i < NumOps; ++i) {
 		if (MCOperandInfo_isTiedToOp(&OpInfo[i])) {
--- a/Mapping.h
+++ b/Mapping.h
@ -33,6 +33,7 @@ typedef struct insn_map {
 		loongarch_suppl_info loongarch;
 		aarch64_suppl_info aarch64;
 		systemz_suppl_info systemz;
+		arm_suppl_info arm;
 		xtensa_suppl_info xtensa;
 	} suppl_info; // Supplementary information for each instruction.
 #endif
--- a/arch/ARM/ARMAddressingModes.h
+++ b/arch/ARM/ARMAddressingModes.h
@ -3,8 +3,8 @@
 /*    Rot127 <unisono@quyllur.org> 2022-2023 */
 /* Automatically translated source file from LLVM. */

-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */

 /* Only small edits allowed. */
 /* For multiple similar edits, please create a Patch for the translator. */
@ -27,19 +27,18 @@
 #ifndef CS_ARM_ADDRESSINGMODES_H
 #define CS_ARM_ADDRESSINGMODES_H

-#include <capstone/platform.h>
 #include "../../cs_priv.h"
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
+#include <capstone/platform.h>

-#include "../../MathExtras.h"
 #include <assert.h>
+#include "../../MathExtras.h"

 #define CONCAT(a, b) CONCAT_(a, b)
 #define CONCAT_(a, b) a##_##b

 /// ARM_AM - ARM Addressing Mode Stuff
+// CS namespace begin: ARM_AM
+
 typedef enum ShiftOpc {
 	ARM_AM_no_shift = 0,
 	ARM_AM_asr,
@ -117,24 +116,6 @@ static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_SubMode Mode)
 	}
 }

-/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
-///
-static inline unsigned ARM_AM_rotr32(unsigned Val, unsigned Amt)
-{
-	CS_ASSERT(Amt <= 32);
-	if (Amt == 32) {
-		return Val;
-	}
-	return (Val >> Amt) | (Val << ((32 - Amt) & 31)); // NOLINT(clang-analyzer-core.BitwiseShift)
-}
-
-/// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
-///
-static inline unsigned ARM_AM_rotl32(unsigned Val, unsigned Amt)
-{
-	return (Val << Amt) | (Val >> ((32 - Amt) & 31));
-}
-
 //===--------------------------------------------------------------------===//
 // Addressing Mode #1: shift_operand with registers
 //===--------------------------------------------------------------------===//
@ -148,7 +129,22 @@ static inline unsigned ARM_AM_rotl32(unsigned Val, unsigned Amt)
 // This is stored three operands [rega, regb, opc].  The first is the base
 // reg, the second is the shift amount (or reg0 if not present or imm).  The
 // third operand encodes the shift opcode and the imm if a reg isn't present.
-//
+static inline unsigned ARM_AM_rotr32(unsigned Val, unsigned Amt)
+{
+	CS_ASSERT(Amt <= 32);
+	if (Amt == 32) {
+		return Val;
+	}
+	return (Val >> Amt) |
+	       (Val << ((32 - Amt) &
+			31)); // NOLINT(clang-analyzer-core.BitwiseShift)
+}
+
+static inline unsigned ARM_AM_rotl32(unsigned Val, unsigned Amt)
+{
+	return (Val << Amt) | (Val >> ((32 - Amt) & 31));
+}
+
 static inline unsigned ARM_AM_getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
 {
 	return ShOp | (Imm << 3);
@ -447,6 +443,8 @@ static inline bool ARM_AM_isT2SOImmTwoPartVal(unsigned Imm)

 static inline unsigned ARM_AM_getT2SOImmTwoPartFirst(unsigned Imm)
 {
+	CS_ASSERT(ARM_AM_isT2SOImmTwoPartVal(Imm) &&
+		  "Immedate cannot be encoded as two part immediate!");
 	// Try a shifter operand as one part
 	unsigned V = ARM_AM_rotr32(~255, ARM_AM_getT2SOImmValRotate(Imm)) & Imm;
 	// If the rest is encodable as an immediate, then return it.
@ -458,7 +456,7 @@ static inline unsigned ARM_AM_getT2SOImmTwoPartFirst(unsigned Imm)
 		return Imm & 0xff00ff00U;

 	// The other splat is all that's left as an option.
-
+	CS_ASSERT(ARM_AM_getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
 	return Imm & 0x00ff00ffU;
 }

@ -467,7 +465,8 @@ static inline unsigned ARM_AM_getT2SOImmTwoPartSecond(unsigned Imm)
 	// Mask out the first hunk
 	Imm ^= ARM_AM_getT2SOImmTwoPartFirst(Imm);
 	// Return what's left
-
+	CS_ASSERT(ARM_AM_getT2SOImmVal(Imm) != -1 &&
+		  "Unable to encode second part of T2 two part SO immediate");
 	return Imm;
 }

@ -492,6 +491,7 @@ static inline unsigned ARM_AM_getT2SOImmTwoPartSecond(unsigned Imm)
 static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12,
 					ARM_AM_ShiftOpc SO, unsigned IdxMode)
 {
+	CS_ASSERT(Imm12 < (1 << 12) && "Imm too large!");
 	bool isSub = Opc == ARM_AM_sub;
 	return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16);
 }
@ -715,6 +715,7 @@ static inline uint64_t ARM_AM_decodeVMOVModImm(unsigned ModImm,
 // Generic validation for single-byte immediate (0X00, 00X0, etc).
 static inline bool ARM_AM_isNEONBytesplat(unsigned Value, unsigned Size)
 {
+	CS_ASSERT(Size >= 1 && Size <= 4 && "Invalid size");
 	unsigned count = 0;
 	for (unsigned i = 0; i < Size; ++i) {
 		if (Value & 0xff)
@ -736,6 +737,7 @@ static inline bool ARM_AM_isNEONi16splat(unsigned Value)
 // Encode NEON 16 bits Splat immediate for instructions like VBIC/VORR
 static inline unsigned ARM_AM_encodeNEONi16splat(unsigned Value)
 {
+	CS_ASSERT(ARM_AM_isNEONi16splat(Value) && "Invalid NEON splat value");
 	if (Value >= 0x100)
 		Value = (Value >> 8) | 0xa00;
 	else
@ -753,6 +755,7 @@ static inline bool ARM_AM_isNEONi32splat(unsigned Value)
 /// Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR.
 static inline unsigned ARM_AM_encodeNEONi32splat(unsigned Value)
 {
+	CS_ASSERT(ARM_AM_isNEONi32splat(Value) && "Invalid NEON splat value");
 	if (Value >= 0x100 && Value <= 0xff00)
 		Value = (Value >> 8) | 0x200;
 	else if (Value > 0xffff && Value <= 0xff0000)
--- a/arch/ARM/ARMBaseInfo.c
+++ b/arch/ARM/ARMBaseInfo.c
@ -3,8 +3,8 @@
 /*    Rot127 <unisono@quyllur.org> 2022-2023 */
 /* Automatically translated source file from LLVM. */

-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */

 /* Only small edits allowed. */
 /* For multiple similar edits, please create a Patch for the translator. */
@ -23,17 +23,19 @@
 // This file provides basic encoding and assembly information for ARM.
 //
 //===----------------------------------------------------------------------===//
+
 #include <capstone/platform.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>

 #include "ARMBaseInfo.h"
-#include "ARMMapping.h"
+#include "../../utils.h"

 #define CONCAT(a, b) CONCAT_(a, b)
 #define CONCAT_(a, b) a##_##b

+// CS namespace begin: ARMSysReg
+
+// lookup system register using 12-bit SYSm value.
+// Note: the search is uniqued using M1 mask
 const char *get_pred_mask(ARM_PredBlockMask pred_mask)
 {
 	switch (pred_mask) {
@ -75,8 +77,6 @@ const char *get_pred_mask(ARM_PredBlockMask pred_mask)
 #define GET_MCLASSSYSREG_IMPL
 #include "ARMGenSystemRegister.inc"

-// lookup system register using 12-bit SYSm value.
-// Note: the search is uniqued using M1 mask
 const ARMSysReg_MClassSysReg *
 ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
 {
--- a/arch/ARM/ARMDisassembler.c
+++ b/arch/ARM/ARMDisassembler.c
@ -3,8 +3,8 @@
 /*    Rot127 <unisono@quyllur.org> 2022-2023 */
 /* Automatically translated source file from LLVM. */

-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */

 /* Only small edits allowed. */
 /* For multiple similar edits, please create a Patch for the translator. */
@ -24,6 +24,10 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include <capstone/platform.h>

 #include "../../LEB128.h"
 #include "../../MCDisassembler.h"
@ -34,10 +38,11 @@
 #include "../../MathExtras.h"
 #include "../../cs_priv.h"
 #include "../../utils.h"
-#include "ARMLinkage.h"
 #include "ARMAddressingModes.h"
 #include "ARMBaseInfo.h"
 #include "ARMDisassemblerExtension.h"
+
+#include "ARMLinkage.h"
 #include "ARMMapping.h"

 #define GET_INSTRINFO_MC_DESC
@ -46,27 +51,6 @@
 #define CONCAT(a, b) CONCAT_(a, b)
 #define CONCAT_(a, b) a##_##b

-#define DEBUG_TYPE "arm-disassembler"
-
-// Handles the condition code status of instructions in IT blocks
-;
-
-;
-
-/// ARM disassembler for all ARM platforms.;
-static DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t ByteLen,
-				   MCInst *MI, uint16_t *Size, uint64_t Address,
-				   void *Info);
-DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes, size_t ByteLen,
-			       MCInst *MI, uint16_t *Size, uint64_t Address,
-			       void *Info);
-DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t ByteLen,
-				 MCInst *MI, uint16_t *Size, uint64_t Address,
-				 void *Info);
-DecodeStatus AddThumbPredicate(MCInst *);
-void UpdateThumbVFPPredicate(DecodeStatus, MCInst *);
-;
-
 // end anonymous namespace

 // Forward declare these because the autogenerated code will reference them.
@ -305,11 +289,11 @@ static DecodeStatus DecodeMveAddrModeRQ(MCInst *Inst, unsigned Insn,
 	static DecodeStatus CONCAT(DecodeMveAddrModeQ, shift)( \
 		MCInst * Inst, unsigned Insn, uint64_t Address, \
 		const void *Decoder);
-DECLARE_DecodeMveAddrModeQ(2) DECLARE_DecodeMveAddrModeQ(3)
+DECLARE_DecodeMveAddrModeQ(2);
+DECLARE_DecodeMveAddrModeQ(3);

-	static DecodeStatus
-	DecodeCoprocessor(MCInst *Inst, unsigned Insn, uint64_t Address,
-			  const void *Decoder);
+static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn,
+				      uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn,
 					   uint64_t Address,
 					   const void *Decoder);
@ -420,31 +404,33 @@ static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, uint64_t Address,
 							unsigned Val, \
 							uint64_t Address, \
 							const void *Decoder);
-DECLARE_DecodeT2Imm7(0) DECLARE_DecodeT2Imm7(1) DECLARE_DecodeT2Imm7(2)
+DECLARE_DecodeT2Imm7(0);
+DECLARE_DecodeT2Imm7(1);
+DECLARE_DecodeT2Imm7(2);

-	static DecodeStatus
-	DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, uint64_t Address,
-			     const void *Decoder);
+static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val,
+					 uint64_t Address, const void *Decoder);
 #define DECLARE_DecodeTAddrModeImm7(shift) \
 	static DecodeStatus CONCAT(DecodeTAddrModeImm7, shift)( \
 		MCInst * Inst, unsigned Val, uint64_t Address, \
 		const void *Decoder);
-DECLARE_DecodeTAddrModeImm7(0) DECLARE_DecodeTAddrModeImm7(1)
+DECLARE_DecodeTAddrModeImm7(0);
+DECLARE_DecodeTAddrModeImm7(1);

 #define DECLARE_DecodeT2AddrModeImm7(shift, WriteBack) \
 	static DecodeStatus CONCAT(DecodeT2AddrModeImm7, \
 				   CONCAT(shift, WriteBack))( \
 		MCInst * Inst, unsigned Val, uint64_t Address, \
 		const void *Decoder);
-	DECLARE_DecodeT2AddrModeImm7(0, 0) DECLARE_DecodeT2AddrModeImm7(1, 0)
-		DECLARE_DecodeT2AddrModeImm7(2, 0)
-			DECLARE_DecodeT2AddrModeImm7(0, 1)
-				DECLARE_DecodeT2AddrModeImm7(1, 1)
-					DECLARE_DecodeT2AddrModeImm7(2, 1)
+DECLARE_DecodeT2AddrModeImm7(0, 0);
+DECLARE_DecodeT2AddrModeImm7(1, 0);
+DECLARE_DecodeT2AddrModeImm7(2, 0);
+DECLARE_DecodeT2AddrModeImm7(0, 1);
+DECLARE_DecodeT2AddrModeImm7(1, 1);
+DECLARE_DecodeT2AddrModeImm7(2, 1);

-						static DecodeStatus
-	DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val, uint64_t Address,
-			    const void *Decoder);
+static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val,
+					uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
 					uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn,
@ -501,17 +487,15 @@ static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val,
 		CONCAT(isSigned, CONCAT(isNeg, CONCAT(zeroPermitted, size))))( \
 		MCInst * Inst, unsigned val, uint64_t Address, \
 		const void *Decoder);
-DECLARE_DecodeBFLabelOperand(false, false, false,
-			     4) DECLARE_DecodeBFLabelOperand(true, false, true,
-							     18)
-	DECLARE_DecodeBFLabelOperand(true, false, true, 12)
-		DECLARE_DecodeBFLabelOperand(true, false, true, 16)
-			DECLARE_DecodeBFLabelOperand(false, true, true, 11)
-				DECLARE_DecodeBFLabelOperand(false, false, true,
-							     11)
+DECLARE_DecodeBFLabelOperand(false, false, false, 4);
+DECLARE_DecodeBFLabelOperand(true, false, true, 18);
+DECLARE_DecodeBFLabelOperand(true, false, true, 12);
+DECLARE_DecodeBFLabelOperand(true, false, true, 16);
+DECLARE_DecodeBFLabelOperand(false, true, true, 11);
+DECLARE_DecodeBFLabelOperand(false, false, true, 11);

-					static DecodeStatus
-	DecodeBFAfterTargetOperand(MCInst *Inst, unsigned val, uint64_t Address,
+static DecodeStatus DecodeBFAfterTargetOperand(MCInst *Inst, unsigned val,
+					       uint64_t Address,
 					       const void *Decoder);
 static DecodeStatus DecodePredNoALOperand(MCInst *Inst, unsigned Val,
 					  uint64_t Address,
@ -547,47 +531,47 @@ static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst *Inst,
 	static DecodeStatus CONCAT(DecodeVSTRVLDR_SYSREG, Writeback)( \
 		MCInst * Inst, unsigned Insn, uint64_t Address, \
 		const void *Decoder);
-DECLARE_DecodeVSTRVLDR_SYSREG(false) DECLARE_DecodeVSTRVLDR_SYSREG(true)
+DECLARE_DecodeVSTRVLDR_SYSREG(false);
+DECLARE_DecodeVSTRVLDR_SYSREG(true);

 #define DECLARE_DecodeMVE_MEM_1_pre(shift) \
 	static DecodeStatus CONCAT(DecodeMVE_MEM_1_pre, shift)( \
 		MCInst * Inst, unsigned Val, uint64_t Address, \
 		const void *Decoder);
-	DECLARE_DecodeMVE_MEM_1_pre(0) DECLARE_DecodeMVE_MEM_1_pre(1)
+DECLARE_DecodeMVE_MEM_1_pre(0);
+DECLARE_DecodeMVE_MEM_1_pre(1);

 #define DECLARE_DecodeMVE_MEM_2_pre(shift) \
 	static DecodeStatus CONCAT(DecodeMVE_MEM_2_pre, shift)( \
 		MCInst * Inst, unsigned Val, uint64_t Address, \
 		const void *Decoder);
-		DECLARE_DecodeMVE_MEM_2_pre(0) DECLARE_DecodeMVE_MEM_2_pre(
-			1) DECLARE_DecodeMVE_MEM_2_pre(2)
+DECLARE_DecodeMVE_MEM_2_pre(0);
+DECLARE_DecodeMVE_MEM_2_pre(1);
+DECLARE_DecodeMVE_MEM_2_pre(2);

 #define DECLARE_DecodeMVE_MEM_3_pre(shift) \
 	static DecodeStatus CONCAT(DecodeMVE_MEM_3_pre, shift)( \
 		MCInst * Inst, unsigned Val, uint64_t Address, \
 		const void *Decoder);
-			DECLARE_DecodeMVE_MEM_3_pre(
-				2) DECLARE_DecodeMVE_MEM_3_pre(3)
+DECLARE_DecodeMVE_MEM_3_pre(2);
+DECLARE_DecodeMVE_MEM_3_pre(3);

 #define DECLARE_DecodePowerTwoOperand(MinLog, MaxLog) \
 	static DecodeStatus CONCAT(DecodePowerTwoOperand, \
 				   CONCAT(MinLog, MaxLog))( \
 		MCInst * Inst, unsigned Val, uint64_t Address, \
 		const void *Decoder);
-				DECLARE_DecodePowerTwoOperand(0, 3)
+DECLARE_DecodePowerTwoOperand(0, 3);

 #define DECLARE_DecodeMVEPairVectorIndexOperand(start) \
 	static DecodeStatus CONCAT(DecodeMVEPairVectorIndexOperand, start)( \
 		MCInst * Inst, unsigned Val, uint64_t Address, \
 		const void *Decoder);
-					DECLARE_DecodeMVEPairVectorIndexOperand(
-						2)
-						DECLARE_DecodeMVEPairVectorIndexOperand(
-							0)
+DECLARE_DecodeMVEPairVectorIndexOperand(2);
+DECLARE_DecodeMVEPairVectorIndexOperand(0);

-							static DecodeStatus
-	DecodeMVEVMOVQtoDReg(MCInst *Inst, unsigned Insn, uint64_t Address,
-			     const void *Decoder);
+static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst *Inst, unsigned Insn,
 					 uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMVEVCVTt1fp(MCInst *Inst, unsigned Insn,
@ -599,23 +583,16 @@ typedef DecodeStatus OperandDecoder(MCInst *Inst, unsigned Val,
 				   CONCAT(scalar, predicate_decoder))( \
 		MCInst * Inst, unsigned Insn, uint64_t Address, \
 		const void *Decoder);
-DECLARE_DecodeMVEVCMP(false, DecodeRestrictedIPredicateOperand) DECLARE_DecodeMVEVCMP(
-	false, DecodeRestrictedUPredicateOperand)
-	DECLARE_DecodeMVEVCMP(false, DecodeRestrictedSPredicateOperand)
-		DECLARE_DecodeMVEVCMP(true, DecodeRestrictedIPredicateOperand)
-			DECLARE_DecodeMVEVCMP(true,
-					      DecodeRestrictedUPredicateOperand)
-				DECLARE_DecodeMVEVCMP(
-					true, DecodeRestrictedSPredicateOperand)
-					DECLARE_DecodeMVEVCMP(
-						false,
-						DecodeRestrictedFPPredicateOperand)
-						DECLARE_DecodeMVEVCMP(
-							true,
-							DecodeRestrictedFPPredicateOperand)
+DECLARE_DecodeMVEVCMP(false, DecodeRestrictedIPredicateOperand);
+DECLARE_DecodeMVEVCMP(false, DecodeRestrictedUPredicateOperand);
+DECLARE_DecodeMVEVCMP(false, DecodeRestrictedSPredicateOperand);
+DECLARE_DecodeMVEVCMP(true, DecodeRestrictedIPredicateOperand);
+DECLARE_DecodeMVEVCMP(true, DecodeRestrictedUPredicateOperand);
+DECLARE_DecodeMVEVCMP(true, DecodeRestrictedSPredicateOperand);
+DECLARE_DecodeMVEVCMP(false, DecodeRestrictedFPPredicateOperand);
+DECLARE_DecodeMVEVCMP(true, DecodeRestrictedFPPredicateOperand);

-							static DecodeStatus
-	DecodeMveVCTP(MCInst *Inst, unsigned Insn, uint64_t Address,
+static DecodeStatus DecodeMveVCTP(MCInst *Inst, unsigned Insn, uint64_t Address,
 				  const void *Decoder);
 static DecodeStatus DecodeMVEVPNOT(MCInst *Inst, unsigned Insn,
 				   uint64_t Address, const void *Decoder);
@ -628,6 +605,7 @@ static DecodeStatus DecodeT2AddSubSPImm(MCInst *Inst, unsigned Insn,
 #include "ARMGenDisassemblerTables.inc"

 // Post-decoding checks
+
 static DecodeStatus checkDecodedInstruction(MCInst *MI, uint32_t Insn,
 					    DecodeStatus Result)
 {
@ -659,46 +637,9 @@ static DecodeStatus checkDecodedInstruction(MCInst *MI, uint32_t Insn,
 	}
 }

-static DecodeStatus getInstruction(csh ud, const uint8_t *Bytes,
-				   size_t BytesLen, MCInst *MI, uint16_t *Size,
-				   uint64_t Address, void *Info)
-{
-	DecodeStatus Result = MCDisassembler_Fail;
-	if (MI->csh->mode & CS_MODE_THUMB)
-		Result = getThumbInstruction(ud, Bytes, BytesLen, MI, Size,
-					     Address, Info);
-	else
-		Result = getARMInstruction(ud, Bytes, BytesLen, MI, Size,
-					   Address, Info);
-	MCInst_handleWriteback(MI, ARMInsts, ARR_SIZE(ARMInsts));
-	return Result;
-}
-
-static inline uint32_t endianSensitiveOpcode32(MCInst *MI, const uint8_t *Bytes)
-{
-	uint32_t Insn;
-	if (MODE_IS_BIG_ENDIAN(MI->csh->mode))
-		Insn = (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
-		       ((uint32_t)Bytes[0] << 24);
-	else
-		Insn = ((uint32_t)Bytes[3] << 24) | (Bytes[2] << 16) |
-		       (Bytes[1] << 8) | (Bytes[0] << 0);
-	return Insn;
-}
-
-static inline uint16_t endianSensitiveOpcode16(MCInst *MI, const uint8_t *Bytes)
-{
-	uint16_t Insn;
-	if (MODE_IS_BIG_ENDIAN(MI->csh->mode))
-		Insn = (Bytes[0] << 8) | Bytes[1];
-	else
-		Insn = (Bytes[1] << 8) | Bytes[0];
-
-	return Insn;
-}
-
-DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
-			       MCInst *MI, uint16_t *Size, uint64_t Address,
+static DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes,
+				      size_t BytesLen, MCInst *MI,
+				      uint16_t *Size, uint64_t Address,
 				      void *Info)
 {
 	// We want to read exactly 4 bytes of data.
@ -708,11 +649,11 @@ DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 	}

 	// Encoded as a 32-bit word in the stream.
-	uint32_t Insn = endianSensitiveOpcode32(MI, Bytes);
+	uint32_t Insn = readBytes32(MI, Bytes);

 	// Calling the auto-generated decoder function.
 	DecodeStatus Result =
-		decodeInstruction_4(DecoderTableARM32, MI, Insn, Address);
+		decodeInstruction_4(DecoderTableARM32, MI, Insn, Address, NULL);
 	if (Result != MCDisassembler_Fail) {
 		*Size = 4;
 		return checkDecodedInstruction(MI, Insn, Result);
@ -736,7 +677,7 @@ DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 	for (int i = 0; i < (sizeof(Tables) / sizeof(Tables[0])); ++i) {
 		MCInst_clear(MI);
 		DecodeTable Table = Tables[i];
-		Result = decodeInstruction_4(Table.P, MI, Insn, Address);
+		Result = decodeInstruction_4(Table.P, MI, Insn, Address, NULL);
 		if (Result != MCDisassembler_Fail) {
 			*Size = 4;
 			// Add a fake predicate operand, because we share these instruction
@ -748,7 +689,8 @@ DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 		}
 	}

-	Result = decodeInstruction_4(DecoderTableCoProc32, MI, Insn, Address);
+	Result = decodeInstruction_4(DecoderTableCoProc32, MI, Insn, Address,
+				     NULL);
 	if (Result != MCDisassembler_Fail) {
 		*Size = 4;
 		return checkDecodedInstruction(MI, Insn, Result);
@ -758,8 +700,6 @@ DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 	return MCDisassembler_Fail;
 }

-extern const MCInstrDesc ARMInsts[];
-
 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
 /// immediate Value in the MCInst.  The immediate Value has had any PC
 /// adjustment made by the caller.  If the instruction is a branch instruction
@ -804,8 +744,10 @@ static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
 // that as a post-pass.
 static void AddThumb1SBit(MCInst *MI, bool InITBlock)
 {
-	const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
-	unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
+	const MCInstrDesc *Desc = MCInstrDesc_get(
+		MCInst_getOpcode(MI), ARMDescs.Insts, ARR_SIZE(ARMDescs.Insts));
+	const MCOperandInfo *OpInfo = Desc->OpInfo;
+	unsigned short NumOps = Desc->NumOperands;
 	unsigned i;

 	for (i = 0; i < NumOps; ++i) {
@ -828,8 +770,10 @@ static void AddThumb1SBit(MCInst *MI, bool InITBlock)

 static bool isVectorPredicable(unsigned Opcode)
 {
-	const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
-	unsigned short NumOps = ARMInsts[Opcode].NumOperands;
+	const MCInstrDesc *Desc = MCInstrDesc_get(Opcode, ARMDescs.Insts,
+						  ARR_SIZE(ARMDescs.Insts));
+	const MCOperandInfo *OpInfo = Desc->OpInfo;
+	unsigned short NumOps = Desc->NumOperands;
 	for (unsigned i = 0; i < NumOps; ++i) {
 		if (ARM_isVpred(OpInfo[i].OperandType))
 			return true;
@ -907,9 +851,11 @@ DecodeStatus AddThumbPredicate(MCInst *MI)
 		VCC = VPTBlock_getVPTPred(&(MI->csh->VPTBlock));
 		VPTBlock_advanceVPTState(&(MI->csh->VPTBlock));
 	}
+	const MCInstrDesc *Desc = MCInstrDesc_get(
+		MCInst_getOpcode(MI), ARMDescs.Insts, ARR_SIZE(ARMDescs.Insts));

-	const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
-	unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
+	const MCOperandInfo *OpInfo = Desc->OpInfo;
+	unsigned short NumOps = Desc->NumOperands;

 	unsigned i;
 	for (i = 0; i < NumOps; ++i) {
@ -918,7 +864,7 @@ DecodeStatus AddThumbPredicate(MCInst *MI)
 			break;
 	}

-	if (MCInst_isPredicable(&ARMInsts[MCInst_getOpcode(MI)])) {
+	if (MCInst_isPredicable(Desc)) {
 		MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, (CC)));

 		if (CC == ARMCC_AL)
@ -950,10 +896,11 @@ DecodeStatus AddThumbPredicate(MCInst *MI)
 		MCInst_insert0(MI, VCCPos + 2, MCOperand_CreateReg1(MI, (0)));
 		if (OpInfo[VCCPos].OperandType == ARM_OP_VPRED_R) {
 			int TiedOp = MCOperandInfo_getOperandConstraint(
-				&ARMInsts[MCInst_getOpcode(MI)], VCCPos + 3,
-				MCOI_TIED_TO);
-			CS_ASSERT_RET_VAL(TiedOp >= 0 &&
-			       "Inactive register in vpred_r is not tied to an output!", MCDisassembler_Fail);
+				Desc, VCCPos + 3, MCOI_TIED_TO);
+			CS_ASSERT_RET_VAL(
+				TiedOp >= 0 &&
+					"Inactive register in vpred_r is not tied to an output!",
+				MCDisassembler_Fail);
 			// Copy the operand to ensure it's not invalidated when MI grows.
 			MCOperand Op = *MCInst_getOperand(MI, TiedOp);
 			MCInst_insert0(MI, VCCPos + 3, &Op);
@ -970,7 +917,7 @@ DecodeStatus AddThumbPredicate(MCInst *MI)
 // mode, the auto-generated decoder will give them an (incorrect)
 // predicate operand.  We need to rewrite these operands based on the IT
 // context as a post-pass.
-void UpdateThumbVFPPredicate(DecodeStatus S, MCInst *MI)
+static void UpdateThumbVFPPredicate(DecodeStatus S, MCInst *MI)
 {
 	unsigned CC;
 	CC = ITBlock_getITCC(&(MI->csh->ITBlock));
@ -983,13 +930,13 @@ void UpdateThumbVFPPredicate(DecodeStatus S, MCInst *MI)
 		VPTBlock_advanceVPTState(&(MI->csh->VPTBlock));
 	}

-	const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
-	unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
+	const MCInstrDesc *Desc = MCInstrDesc_get(
+		MCInst_getOpcode(MI), ARMDescs.Insts, ARR_SIZE(ARMDescs.Insts));
+	const MCOperandInfo *OpInfo = Desc->OpInfo;
+	unsigned short NumOps = Desc->NumOperands;
 	for (unsigned i = 0; i < NumOps; ++i) {
 		if (MCOperandInfo_isPredicate(&OpInfo[i])) {
-			if (CC != ARMCC_AL &&
-			    !MCInst_isPredicable(
-				    &ARMInsts[MCInst_getOpcode(MI)]))
+			if (CC != ARMCC_AL && !MCInst_isPredicable(Desc))
 				Check(&S, MCDisassembler_SoftFail);
 			MCOperand_setImm(MCInst_getOperand(MI, i), CC);

@ -1005,8 +952,9 @@ void UpdateThumbVFPPredicate(DecodeStatus S, MCInst *MI)
 	}
 }

-DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
-				 MCInst *MI, uint16_t *Size, uint64_t Address,
+static DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes,
+					size_t BytesLen, MCInst *MI,
+					uint16_t *Size, uint64_t Address,
 					void *Info)
 {
 	// We want to read exactly 2 bytes of data.
@ -1015,9 +963,9 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 		return MCDisassembler_Fail;
 	}

-	uint16_t Insn16 = endianSensitiveOpcode16(MI, Bytes);
-	DecodeStatus Result =
-		decodeInstruction_2(DecoderTableThumb16, MI, Insn16, Address);
+	uint16_t Insn16 = readBytes16(MI, Bytes);
+	DecodeStatus Result = decodeInstruction_2(DecoderTableThumb16, MI,
+						  Insn16, Address, NULL);
 	if (Result != MCDisassembler_Fail) {
 		*Size = 2;
 		Check(&Result, AddThumbPredicate(MI));
@ -1025,7 +973,7 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 	}

 	Result = decodeInstruction_2(DecoderTableThumbSBit16, MI, Insn16,
-				     Address);
+				     Address, NULL);
 	if (Result) {
 		*Size = 2;
 		bool InITBlock = ITBlock_instrInITBlock(&(MI->csh->ITBlock));
@ -1034,7 +982,8 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 		return Result;
 	}

-	Result = decodeInstruction_2(DecoderTableThumb216, MI, Insn16, Address);
+	Result = decodeInstruction_2(DecoderTableThumb216, MI, Insn16, Address,
+				     NULL);
 	if (Result != MCDisassembler_Fail) {
 		*Size = 2;

@ -1070,10 +1019,10 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 		*Size = 0;
 		return MCDisassembler_Fail;
 	}
-	uint32_t Insn32 = (uint32_t)Insn16 << 16 |
-			  endianSensitiveOpcode16(MI, Bytes + 2);
+	uint32_t Insn32 = (uint32_t)Insn16 << 16 | readBytes16(MI, Bytes + 2);

-	Result = decodeInstruction_4(DecoderTableMVE32, MI, Insn32, Address);
+	Result = decodeInstruction_4(DecoderTableMVE32, MI, Insn32, Address,
+				     NULL);
 	if (Result != MCDisassembler_Fail) {
 		*Size = 4;

@ -1094,7 +1043,8 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 		return Result;
 	}

-	Result = decodeInstruction_4(DecoderTableThumb32, MI, Insn32, Address);
+	Result = decodeInstruction_4(DecoderTableThumb32, MI, Insn32, Address,
+				     NULL);
 	if (Result != MCDisassembler_Fail) {
 		*Size = 4;
 		bool InITBlock = ITBlock_instrInITBlock(&(MI->csh->ITBlock));
@ -1103,7 +1053,8 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 		return Result;
 	}

-	Result = decodeInstruction_4(DecoderTableThumb232, MI, Insn32, Address);
+	Result = decodeInstruction_4(DecoderTableThumb232, MI, Insn32, Address,
+				     NULL);
 	if (Result != MCDisassembler_Fail) {
 		*Size = 4;
 		Check(&Result, AddThumbPredicate(MI));
@ -1112,7 +1063,7 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,

 	if (fieldFromInstruction_4(Insn32, 28, 4) == 0xE) {
 		Result = decodeInstruction_4(DecoderTableVFP32, MI, Insn32,
-					     Address);
+					     Address, NULL);
 		if (Result != MCDisassembler_Fail) {
 			*Size = 4;
 			UpdateThumbVFPPredicate(Result, MI);
@ -1120,7 +1071,8 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 		}
 	}

-	Result = decodeInstruction_4(DecoderTableVFPV832, MI, Insn32, Address);
+	Result = decodeInstruction_4(DecoderTableVFPV832, MI, Insn32, Address,
+				     NULL);
 	if (Result != MCDisassembler_Fail) {
 		*Size = 4;
 		return Result;
@ -1128,7 +1080,7 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,

 	if (fieldFromInstruction_4(Insn32, 28, 4) == 0xE) {
 		Result = decodeInstruction_4(DecoderTableNEONDup32, MI, Insn32,
-					     Address);
+					     Address, NULL);
 		if (Result != MCDisassembler_Fail) {
 			*Size = 4;
 			Check(&Result, AddThumbPredicate(MI));
@ -1141,7 +1093,7 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 		NEONLdStInsn &= 0xF0FFFFFF;
 		NEONLdStInsn |= 0x04000000;
 		Result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI,
-					     NEONLdStInsn, Address);
+					     NEONLdStInsn, Address, NULL);
 		if (Result != MCDisassembler_Fail) {
 			*Size = 4;
 			Check(&Result, AddThumbPredicate(MI));
@ -1156,7 +1108,7 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 				4;	    // Move bit 28 to bit 24
 		NEONDataInsn |= 0x12000000; // Set bits 28 and 25
 		Result = decodeInstruction_4(DecoderTableNEONData32, MI,
-					     NEONDataInsn, Address);
+					     NEONDataInsn, Address, NULL);
 		if (Result != MCDisassembler_Fail) {
 			*Size = 4;
 			Check(&Result, AddThumbPredicate(MI));
@ -1169,7 +1121,7 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 				  4;	      // Move bit 28 to bit 24
 		NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
 		Result = decodeInstruction_4(DecoderTablev8Crypto32, MI,
-					     NEONCryptoInsn, Address);
+					     NEONCryptoInsn, Address, NULL);
 		if (Result != MCDisassembler_Fail) {
 			*Size = 4;
 			return Result;
@ -1178,7 +1130,7 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 		uint32_t NEONv8Insn = Insn32;
 		NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
 		Result = decodeInstruction_4(DecoderTablev8NEON32, MI,
-					     NEONv8Insn, Address);
+					     NEONv8Insn, Address, NULL);
 		if (Result != MCDisassembler_Fail) {
 			*Size = 4;
 			return Result;
@ -1189,7 +1141,7 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 	const uint8_t *DecoderTable = ARM_isCDECoproc(Coproc, MI) ?
 					      DecoderTableThumb2CDE32 :
 					      DecoderTableThumb2CoProc32;
-	Result = decodeInstruction_4(DecoderTable, MI, Insn32, Address);
+	Result = decodeInstruction_4(DecoderTable, MI, Insn32, Address, NULL);
 	if (Result != MCDisassembler_Fail) {
 		*Size = 4;
 		Check(&Result, AddThumbPredicate(MI));
@ -1200,6 +1152,21 @@ DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
 	return MCDisassembler_Fail;
 }

+static DecodeStatus getInstruction(csh ud, const uint8_t *Bytes,
+				   size_t BytesLen, MCInst *MI, uint16_t *Size,
+				   uint64_t Address, void *Info)
+{
+	DecodeStatus Result = MCDisassembler_Fail;
+	if (MI->csh->mode & CS_MODE_THUMB)
+		Result = getThumbInstruction(ud, Bytes, BytesLen, MI, Size,
+					     Address, Info);
+	else
+		Result = getARMInstruction(ud, Bytes, BytesLen, MI, Size,
+					   Address, Info);
+	MCInst_handleWriteback(MI, ARMDescs.Insts, ARR_SIZE(ARMDescs.Insts));
+	return Result;
+}
+
 static const uint16_t GPRDecoderTable[] = { ARM_R0,  ARM_R1, ARM_R2,  ARM_R3,
 					    ARM_R4,  ARM_R5, ARM_R6,  ARM_R7,
 					    ARM_R8,  ARM_R9, ARM_R10, ARM_R11,
@ -1561,8 +1528,12 @@ static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
 	// AL predicate is not allowed on Thumb1 branches.
 	if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE)
 		return MCDisassembler_Fail;
-	if (Val != ARMCC_AL &&
-	    !MCInst_isPredicable(&ARMInsts[MCInst_getOpcode(Inst)]))
+
+	const MCInstrDesc *Desc = MCInstrDesc_get(MCInst_getOpcode(Inst),
+						  ARMDescs.Insts,
+						  ARR_SIZE(ARMDescs.Insts));
+
+	if (Val != ARMCC_AL && !MCInst_isPredicable(Desc))
 		Check(&S, MCDisassembler_SoftFail);
 	MCOperand_CreateImm0(Inst, (Val));
 	if (Val == ARMCC_AL) {
@ -1804,8 +1775,6 @@ static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
 {
 	DecodeStatus S = MCDisassembler_Success;

-	unsigned P = fieldFromInstruction_4(Insn, 24, 1);
-	unsigned W = fieldFromInstruction_4(Insn, 21, 1);
 	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
 	unsigned CRd = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned coproc = fieldFromInstruction_4(Insn, 8, 4);
@ -1813,9 +1782,6 @@ static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned U = fieldFromInstruction_4(Insn, 23, 1);

-	// Pre-Indexed implies writeback to Rn
-	bool IsPreIndexed = (P == 1) && (W == 1);
-
 	switch (MCInst_getOpcode(Inst)) {
 	case ARM_LDC_OFFSET:
 	case ARM_LDC_PRE:
@ -1889,10 +1855,6 @@ static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
 	if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && (coproc != 14))
 		return MCDisassembler_Fail;

-	if (IsPreIndexed)
-		// Dummy operand for Rn_wb.
-		MCOperand_CreateImm0(Inst, (0));
-
 	MCOperand_CreateImm0(Inst, (coproc));
 	MCOperand_CreateImm0(Inst, (CRd));
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
@ -4598,11 +4560,12 @@ static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, uint64_t Address,
 \
 		return MCDisassembler_Success; \
 	}
-DEFINE_DecodeT2Imm7(0) DEFINE_DecodeT2Imm7(1) DEFINE_DecodeT2Imm7(2)
+DEFINE_DecodeT2Imm7(0);
+DEFINE_DecodeT2Imm7(1);
+DEFINE_DecodeT2Imm7(2);

-	static DecodeStatus
-	DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, uint64_t Address,
-			     const void *Decoder)
+static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val,
+					 uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;

@ -4667,7 +4630,8 @@ DEFINE_DecodeT2Imm7(0) DEFINE_DecodeT2Imm7(1) DEFINE_DecodeT2Imm7(2)
 \
 		return S; \
 	}
-DEFINE_DecodeTAddrModeImm7(0) DEFINE_DecodeTAddrModeImm7(1)
+DEFINE_DecodeTAddrModeImm7(0);
+DEFINE_DecodeTAddrModeImm7(1);

 #define DEFINE_DecodeT2AddrModeImm7(shift, WriteBack) \
 	static DecodeStatus CONCAT(DecodeT2AddrModeImm7, \
@ -4692,15 +4656,15 @@ DEFINE_DecodeTAddrModeImm7(0) DEFINE_DecodeTAddrModeImm7(1)
 \
 		return S; \
 	}
-	DEFINE_DecodeT2AddrModeImm7(0, 0) DEFINE_DecodeT2AddrModeImm7(1, 0)
-		DEFINE_DecodeT2AddrModeImm7(2, 0)
-			DEFINE_DecodeT2AddrModeImm7(0, 1)
-				DEFINE_DecodeT2AddrModeImm7(1, 1)
-					DEFINE_DecodeT2AddrModeImm7(2, 1)
+DEFINE_DecodeT2AddrModeImm7(0, 0);
+DEFINE_DecodeT2AddrModeImm7(1, 0);
+DEFINE_DecodeT2AddrModeImm7(2, 0);
+DEFINE_DecodeT2AddrModeImm7(0, 1);
+DEFINE_DecodeT2AddrModeImm7(1, 1);
+DEFINE_DecodeT2AddrModeImm7(2, 1);

-						static DecodeStatus
-	DecodeT2LdStPre(MCInst *Inst, unsigned Insn, uint64_t Address,
-			const void *Decoder)
+static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn,
+				    uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;

@ -4897,11 +4861,11 @@ static DecodeStatus DecodeMveAddrModeRQ(MCInst *Inst, unsigned Insn,
 \
 		return S; \
 	}
-DEFINE_DecodeMveAddrModeQ(2) DEFINE_DecodeMveAddrModeQ(3)
+DEFINE_DecodeMveAddrModeQ(2);
+DEFINE_DecodeMveAddrModeQ(3);

-	static DecodeStatus
-	DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, uint64_t Address,
-			     const void *Decoder)
+static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val,
+					 uint64_t Address, const void *Decoder)
 {
 	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
 	// Note only one trailing zero not two.  Also the J1 and J2 values are from
@ -6136,7 +6100,8 @@ static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, uint64_t Address,
 	if (sign1 != sign2)
 		return MCDisassembler_Fail;
 	const unsigned Rd = fieldFromInstruction_4(Insn, 8, 4);
-
+	CS_ASSERT(MCInst_getNumOperands(Inst) == 0 &&
+		  "We should receive an empty Inst");
 	DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);

 	unsigned Val = fieldFromInstruction_4(Insn, 0, 8);
@ -6515,17 +6480,15 @@ static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val,
 					     (isNeg ? -DecVal : DecVal)); \
 		return S; \
 	}
-DEFINE_DecodeBFLabelOperand(false, false, false, 4)
-	DEFINE_DecodeBFLabelOperand(true, false, true,
-				    18) DEFINE_DecodeBFLabelOperand(true, false,
-								    true, 12)
-		DEFINE_DecodeBFLabelOperand(true, false, true, 16)
-			DEFINE_DecodeBFLabelOperand(false, true, true, 11)
-				DEFINE_DecodeBFLabelOperand(false, false, true,
-							    11)
+DEFINE_DecodeBFLabelOperand(false, false, false, 4);
+DEFINE_DecodeBFLabelOperand(true, false, true, 18);
+DEFINE_DecodeBFLabelOperand(true, false, true, 12);
+DEFINE_DecodeBFLabelOperand(true, false, true, 16);
+DEFINE_DecodeBFLabelOperand(false, true, true, 11);
+DEFINE_DecodeBFLabelOperand(false, false, true, 11);

-					static DecodeStatus
-	DecodeBFAfterTargetOperand(MCInst *Inst, unsigned Val, uint64_t Address,
+static DecodeStatus DecodeBFAfterTargetOperand(MCInst *Inst, unsigned Val,
+					       uint64_t Address,
 					       const void *Decoder)
 {
 	uint64_t LocImm = MCOperand_getImm(MCInst_getOperand(Inst, (0)));
@ -6962,12 +6925,14 @@ static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode)
 \
 		return S; \
 	}
-DEFINE_DecodeVSTRVLDR_SYSREG(false) DEFINE_DecodeVSTRVLDR_SYSREG(true)
+DEFINE_DecodeVSTRVLDR_SYSREG(false);
+DEFINE_DecodeVSTRVLDR_SYSREG(true);

-	static inline DecodeStatus
-	DecodeMVE_MEM_pre(MCInst *Inst, unsigned Val, uint64_t Address,
+static inline DecodeStatus DecodeMVE_MEM_pre(MCInst *Inst, unsigned Val,
+					     uint64_t Address,
 					     const void *Decoder, unsigned Rn,
-			  OperandDecoder RnDecoder, OperandDecoder AddrDecoder)
+					     OperandDecoder RnDecoder,
+					     OperandDecoder AddrDecoder)
 {
 	DecodeStatus S = MCDisassembler_Success;

@ -6995,7 +6960,8 @@ DEFINE_DecodeVSTRVLDR_SYSREG(false) DEFINE_DecodeVSTRVLDR_SYSREG(true)
 					 DecodetGPRRegisterClass, \
 					 CONCAT(DecodeTAddrModeImm7, shift)); \
 	}
-DEFINE_DecodeMVE_MEM_1_pre(0) DEFINE_DecodeMVE_MEM_1_pre(1)
+DEFINE_DecodeMVE_MEM_1_pre(0);
+DEFINE_DecodeMVE_MEM_1_pre(1);

 #define DEFINE_DecodeMVE_MEM_2_pre(shift) \
 	static DecodeStatus CONCAT(DecodeMVE_MEM_2_pre, shift)( \
@ -7008,8 +6974,9 @@ DEFINE_DecodeMVE_MEM_1_pre(0) DEFINE_DecodeMVE_MEM_1_pre(1)
 					 CONCAT(DecodeT2AddrModeImm7, \
 						CONCAT(shift, 1))); \
 	}
-	DEFINE_DecodeMVE_MEM_2_pre(0) DEFINE_DecodeMVE_MEM_2_pre(
-		1) DEFINE_DecodeMVE_MEM_2_pre(2)
+DEFINE_DecodeMVE_MEM_2_pre(0);
+DEFINE_DecodeMVE_MEM_2_pre(1);
+DEFINE_DecodeMVE_MEM_2_pre(2);

 #define DEFINE_DecodeMVE_MEM_3_pre(shift) \
 	static DecodeStatus CONCAT(DecodeMVE_MEM_3_pre, shift)( \
@ -7021,7 +6988,8 @@ DEFINE_DecodeMVE_MEM_1_pre(0) DEFINE_DecodeMVE_MEM_1_pre(1)
 					 DecodeMQPRRegisterClass, \
 					 CONCAT(DecodeMveAddrModeQ, shift)); \
 	}
-		DEFINE_DecodeMVE_MEM_3_pre(2) DEFINE_DecodeMVE_MEM_3_pre(3)
+DEFINE_DecodeMVE_MEM_3_pre(2);
+DEFINE_DecodeMVE_MEM_3_pre(3);

 #define DEFINE_DecodePowerTwoOperand(MinLog, MaxLog) \
 	static DecodeStatus CONCAT(DecodePowerTwoOperand, \
@ -7037,7 +7005,7 @@ DEFINE_DecodeMVE_MEM_1_pre(0) DEFINE_DecodeMVE_MEM_1_pre(1)
 		MCOperand_CreateImm0(Inst, (1LL << Val)); \
 		return S; \
 	}
-			DEFINE_DecodePowerTwoOperand(0, 3)
+DEFINE_DecodePowerTwoOperand(0, 3);

 #define DEFINE_DecodeMVEPairVectorIndexOperand(start) \
 	static DecodeStatus CONCAT(DecodeMVEPairVectorIndexOperand, start)( \
@ -7050,12 +7018,11 @@ DEFINE_DecodeMVE_MEM_1_pre(0) DEFINE_DecodeMVE_MEM_1_pre(1)
 \
 		return S; \
 	}
-				DEFINE_DecodeMVEPairVectorIndexOperand(2)
-					DEFINE_DecodeMVEPairVectorIndexOperand(0)
+DEFINE_DecodeMVEPairVectorIndexOperand(2);
+DEFINE_DecodeMVEPairVectorIndexOperand(0);

-						static DecodeStatus
-	DecodeMVEVMOVQtoDReg(MCInst *Inst, unsigned Insn, uint64_t Address,
-			     const void *Decoder)
+static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 	unsigned Rt = fieldFromInstruction_4(Insn, 0, 4);
@ -7261,23 +7228,16 @@ static DecodeStatus DecodeMVEVCVTt1fp(MCInst *Inst, unsigned Insn,
 \
 		return S; \
 	}
-DEFINE_DecodeMVEVCMP(false, DecodeRestrictedIPredicateOperand) DEFINE_DecodeMVEVCMP(
-	false, DecodeRestrictedUPredicateOperand)
-	DEFINE_DecodeMVEVCMP(false, DecodeRestrictedSPredicateOperand)
-		DEFINE_DecodeMVEVCMP(true, DecodeRestrictedIPredicateOperand)
-			DEFINE_DecodeMVEVCMP(true,
-					     DecodeRestrictedUPredicateOperand)
-				DEFINE_DecodeMVEVCMP(
-					true, DecodeRestrictedSPredicateOperand)
-					DEFINE_DecodeMVEVCMP(
-						false,
-						DecodeRestrictedFPPredicateOperand)
-						DEFINE_DecodeMVEVCMP(
-							true,
-							DecodeRestrictedFPPredicateOperand)
+DEFINE_DecodeMVEVCMP(false, DecodeRestrictedIPredicateOperand);
+DEFINE_DecodeMVEVCMP(false, DecodeRestrictedUPredicateOperand);
+DEFINE_DecodeMVEVCMP(false, DecodeRestrictedSPredicateOperand);
+DEFINE_DecodeMVEVCMP(true, DecodeRestrictedIPredicateOperand);
+DEFINE_DecodeMVEVCMP(true, DecodeRestrictedUPredicateOperand);
+DEFINE_DecodeMVEVCMP(true, DecodeRestrictedSPredicateOperand);
+DEFINE_DecodeMVEVCMP(false, DecodeRestrictedFPPredicateOperand);
+DEFINE_DecodeMVEVCMP(true, DecodeRestrictedFPPredicateOperand);

-							static DecodeStatus
-	DecodeMveVCTP(MCInst *Inst, unsigned Insn, uint64_t Address,
+static DecodeStatus DecodeMveVCTP(MCInst *Inst, unsigned Insn, uint64_t Address,
 				  const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
--- a/arch/ARM/ARMDisassemblerExtension.c
+++ b/arch/ARM/ARMDisassemblerExtension.c
@ -109,25 +109,6 @@ void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask)
 	VPTBlock_push_back(VPT, ARMVCC_Then);
 }

-/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
-
-bool Check(DecodeStatus *Out, DecodeStatus In)
-{
-	switch (In) {
-	case MCDisassembler_Success:
-		// Out stays the same.
-		return true;
-	case MCDisassembler_SoftFail:
-		*Out = In;
-		return true;
-	case MCDisassembler_Fail:
-		*Out = In;
-		return false;
-	default: // never reached
-		return false;
-	}
-}
-
 // Imported from ARMBaseInstrInfo.h
 //
 /// isValidCoprocessorNumber - decide whether an explicit coprocessor
--- a/arch/ARM/ARMDisassemblerExtension.h
+++ b/arch/ARM/ARMDisassemblerExtension.h
@ -26,8 +26,6 @@ void ITBlock_advanceITState(ARM_ITBlock *it);

 void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask);

-bool Check(DecodeStatus *Out, DecodeStatus In);
-
 bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num);

 bool ARM_isVpred(arm_op_type op);
--- a/arch/ARM/ARMGenAsmWriter.inc
+++ b/arch/ARM/ARMGenAsmWriter.inc
--- a/arch/ARM/ARMGenCSAliasMnemMap.inc
+++ b/arch/ARM/ARMGenCSAliasMnemMap.inc
@ -1,6 +1,6 @@
 /* Capstone Disassembly Engine, https://www.capstone-engine.org */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
 /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

 /* LLVM-commit: <commit> */
--- a/arch/ARM/ARMGenCSFeatureName.inc
+++ b/arch/ARM/ARMGenCSFeatureName.inc
@ -1,60 +1,80 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
 /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */

 /* Do not edit. */

 /* Capstone's LLVM TableGen Backends: */
 /* https://github.com/capstone-engine/llvm-capstone */

-{ ARM_FEATURE_IsARM, "IsARM" }, { ARM_FEATURE_HasV5T, "HasV5T" },
-	{ ARM_FEATURE_HasV4T, "HasV4T" }, { ARM_FEATURE_HasVFP2, "HasVFP2" },
-	{ ARM_FEATURE_HasV5TE, "HasV5TE" }, { ARM_FEATURE_HasV6T2, "HasV6T2" },
-	{ ARM_FEATURE_HasMVEInt, "HasMVEInt" },
-	{ ARM_FEATURE_HasNEON, "HasNEON" },
-	{ ARM_FEATURE_HasFPRegs64, "HasFPRegs64" },
-	{ ARM_FEATURE_HasFPRegs, "HasFPRegs" },
-	{ ARM_FEATURE_IsThumb2, "IsThumb2" },
-	{ ARM_FEATURE_HasV8_1MMainline, "HasV8_1MMainline" },
-	{ ARM_FEATURE_HasLOB, "HasLOB" }, { ARM_FEATURE_IsThumb, "IsThumb" },
-	{ ARM_FEATURE_HasV8MBaseline, "HasV8MBaseline" },
-	{ ARM_FEATURE_Has8MSecExt, "Has8MSecExt" },
-	{ ARM_FEATURE_HasV8, "HasV8" }, { ARM_FEATURE_HasAES, "HasAES" },
-	{ ARM_FEATURE_HasBF16, "HasBF16" }, { ARM_FEATURE_HasCDE, "HasCDE" },
-	{ ARM_FEATURE_PreV8, "PreV8" }, { ARM_FEATURE_HasV6K, "HasV6K" },
-	{ ARM_FEATURE_HasCRC, "HasCRC" }, { ARM_FEATURE_HasV7, "HasV7" },
-	{ ARM_FEATURE_HasDB, "HasDB" },
-	{ ARM_FEATURE_HasVirtualization, "HasVirtualization" },
-	{ ARM_FEATURE_HasVFP3, "HasVFP3" },
-	{ ARM_FEATURE_HasDPVFP, "HasDPVFP" },
-	{ ARM_FEATURE_HasFullFP16, "HasFullFP16" },
-	{ ARM_FEATURE_HasV6, "HasV6" },
-	{ ARM_FEATURE_HasAcquireRelease, "HasAcquireRelease" },
-	{ ARM_FEATURE_HasV7Clrex, "HasV7Clrex" },
-	{ ARM_FEATURE_HasMVEFloat, "HasMVEFloat" },
-	{ ARM_FEATURE_HasFPRegsV8_1M, "HasFPRegsV8_1M" },
-	{ ARM_FEATURE_HasMP, "HasMP" }, { ARM_FEATURE_HasSB, "HasSB" },
-	{ ARM_FEATURE_HasDivideInARM, "HasDivideInARM" },
-	{ ARM_FEATURE_HasV8_1a, "HasV8_1a" },
-	{ ARM_FEATURE_HasSHA2, "HasSHA2" },
-	{ ARM_FEATURE_HasTrustZone, "HasTrustZone" },
-	{ ARM_FEATURE_UseNaClTrap, "UseNaClTrap" },
-	{ ARM_FEATURE_HasV8_4a, "HasV8_4a" },
-	{ ARM_FEATURE_HasV8_3a, "HasV8_3a" },
-	{ ARM_FEATURE_HasFPARMv8, "HasFPARMv8" },
-	{ ARM_FEATURE_HasFP16, "HasFP16" }, { ARM_FEATURE_HasVFP4, "HasVFP4" },
-	{ ARM_FEATURE_HasFP16FML, "HasFP16FML" },
-	{ ARM_FEATURE_HasFPRegs16, "HasFPRegs16" },
-	{ ARM_FEATURE_HasV8MMainline, "HasV8MMainline" },
-	{ ARM_FEATURE_HasDotProd, "HasDotProd" },
-	{ ARM_FEATURE_HasMatMulInt8, "HasMatMulInt8" },
-	{ ARM_FEATURE_IsMClass, "IsMClass" },
-	{ ARM_FEATURE_HasPACBTI, "HasPACBTI" },
-	{ ARM_FEATURE_IsNotMClass, "IsNotMClass" },
-	{ ARM_FEATURE_HasDSP, "HasDSP" },
-	{ ARM_FEATURE_HasDivideInThumb, "HasDivideInThumb" },
-	{ ARM_FEATURE_HasV6M, "HasV6M" },
+{ ARM_FEATURE_HASV4T, "HasV4T" },
+{ ARM_FEATURE_HASV5T, "HasV5T" },
+{ ARM_FEATURE_HASV5TE, "HasV5TE" },
+{ ARM_FEATURE_HASV6, "HasV6" },
+{ ARM_FEATURE_HASV6M, "HasV6M" },
+{ ARM_FEATURE_HASV8MBASELINE, "HasV8MBaseline" },
+{ ARM_FEATURE_HASV8MMAINLINE, "HasV8MMainline" },
+{ ARM_FEATURE_HASV8_1MMAINLINE, "HasV8_1MMainline" },
+{ ARM_FEATURE_HASMVEINT, "HasMVEInt" },
+{ ARM_FEATURE_HASMVEFLOAT, "HasMVEFloat" },
+{ ARM_FEATURE_HASCDE, "HasCDE" },
+{ ARM_FEATURE_HASFPREGS, "HasFPRegs" },
+{ ARM_FEATURE_HASFPREGS16, "HasFPRegs16" },
+{ ARM_FEATURE_HASNOFPREGS16, "HasNoFPRegs16" },
+{ ARM_FEATURE_HASFPREGS64, "HasFPRegs64" },
+{ ARM_FEATURE_HASFPREGSV8_1M, "HasFPRegsV8_1M" },
+{ ARM_FEATURE_HASV6T2, "HasV6T2" },
+{ ARM_FEATURE_HASV6K, "HasV6K" },
+{ ARM_FEATURE_HASV7, "HasV7" },
+{ ARM_FEATURE_HASV8, "HasV8" },
+{ ARM_FEATURE_PREV8, "PreV8" },
+{ ARM_FEATURE_HASV8_1A, "HasV8_1a" },
+{ ARM_FEATURE_HASV8_2A, "HasV8_2a" },
+{ ARM_FEATURE_HASV8_3A, "HasV8_3a" },
+{ ARM_FEATURE_HASV8_4A, "HasV8_4a" },
+{ ARM_FEATURE_HASV8_5A, "HasV8_5a" },
+{ ARM_FEATURE_HASV8_6A, "HasV8_6a" },
+{ ARM_FEATURE_HASV8_7A, "HasV8_7a" },
+{ ARM_FEATURE_HASVFP2, "HasVFP2" },
+{ ARM_FEATURE_HASVFP3, "HasVFP3" },
+{ ARM_FEATURE_HASVFP4, "HasVFP4" },
+{ ARM_FEATURE_HASDPVFP, "HasDPVFP" },
+{ ARM_FEATURE_HASFPARMV8, "HasFPARMv8" },
+{ ARM_FEATURE_HASNEON, "HasNEON" },
+{ ARM_FEATURE_HASSHA2, "HasSHA2" },
+{ ARM_FEATURE_HASAES, "HasAES" },
+{ ARM_FEATURE_HASCRYPTO, "HasCrypto" },
+{ ARM_FEATURE_HASDOTPROD, "HasDotProd" },
+{ ARM_FEATURE_HASCRC, "HasCRC" },
+{ ARM_FEATURE_HASRAS, "HasRAS" },
+{ ARM_FEATURE_HASLOB, "HasLOB" },
+{ ARM_FEATURE_HASPACBTI, "HasPACBTI" },
+{ ARM_FEATURE_HASFP16, "HasFP16" },
+{ ARM_FEATURE_HASFULLFP16, "HasFullFP16" },
+{ ARM_FEATURE_HASFP16FML, "HasFP16FML" },
+{ ARM_FEATURE_HASBF16, "HasBF16" },
+{ ARM_FEATURE_HASMATMULINT8, "HasMatMulInt8" },
+{ ARM_FEATURE_HASDIVIDEINTHUMB, "HasDivideInThumb" },
+{ ARM_FEATURE_HASDIVIDEINARM, "HasDivideInARM" },
+{ ARM_FEATURE_HASDSP, "HasDSP" },
+{ ARM_FEATURE_HASDB, "HasDB" },
+{ ARM_FEATURE_HASDFB, "HasDFB" },
+{ ARM_FEATURE_HASV7CLREX, "HasV7Clrex" },
+{ ARM_FEATURE_HASACQUIRERELEASE, "HasAcquireRelease" },
+{ ARM_FEATURE_HASMP, "HasMP" },
+{ ARM_FEATURE_HASVIRTUALIZATION, "HasVirtualization" },
+{ ARM_FEATURE_HASTRUSTZONE, "HasTrustZone" },
+{ ARM_FEATURE_HAS8MSECEXT, "Has8MSecExt" },
+{ ARM_FEATURE_ISTHUMB, "IsThumb" },
+{ ARM_FEATURE_ISTHUMB2, "IsThumb2" },
+{ ARM_FEATURE_ISMCLASS, "IsMClass" },
+{ ARM_FEATURE_ISNOTMCLASS, "IsNotMClass" },
+{ ARM_FEATURE_ISARM, "IsARM" },
+{ ARM_FEATURE_USENACLTRAP, "UseNaClTrap" },
+{ ARM_FEATURE_USENEGATIVEIMMEDIATES, "UseNegativeImmediates" },
+{ ARM_FEATURE_HASSB, "HasSB" },
+{ ARM_FEATURE_HASCLRBHB, "HasCLRBHB" },
--- a/arch/ARM/ARMGenCSMappingInsn.inc
+++ b/arch/ARM/ARMGenCSMappingInsn.inc
--- a/arch/ARM/ARMGenCSMappingInsnName.inc
+++ b/arch/ARM/ARMGenCSMappingInsnName.inc
@ -1,10 +1,10 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
 /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */

 /* Do not edit. */

@ -40,6 +40,8 @@
  "ldrsh", // ARM_INS_LDRSH
  "movs", // ARM_INS_MOVS
  "mov", // ARM_INS_MOV
+  "strb", // ARM_INS_STRB
+  "strh", // ARM_INS_STRH
  "str", // ARM_INS_STR
  "adc", // ARM_INS_ADC
  "add", // ARM_INS_ADD
@ -452,13 +454,11 @@
  "stmdb", // ARM_INS_STMDB
  "stm", // ARM_INS_STM
  "stmib", // ARM_INS_STMIB
-	"strb",		// ARM_INS_STRB
  "strd", // ARM_INS_STRD
  "strex", // ARM_INS_STREX
  "strexb", // ARM_INS_STREXB
  "strexd", // ARM_INS_STREXD
  "strexh", // ARM_INS_STREXH
-	"strh",		// ARM_INS_STRH
  "strht", // ARM_INS_STRHT
  "sub", // ARM_INS_SUB
  "svc", // ARM_INS_SVC
@ -577,7 +577,7 @@
  "vrsqrts", // ARM_INS_VRSQRTS
  "vrsra", // ARM_INS_VRSRA
  "vrsubhn", // ARM_INS_VRSUBHN
-	"vscclrm",	// ARM_INS_VSCCLRM
+  "vscclrm_", // ARM_INS_VSCCLRM_
  "vsdot", // ARM_INS_VSDOT
  "vseleq", // ARM_INS_VSELEQ
  "vselge", // ARM_INS_VSELGE
@ -608,6 +608,7 @@
  "vuzp", // ARM_INS_VUZP
  "vzip", // ARM_INS_VZIP
  "addw", // ARM_INS_ADDW
+  "adr_", // ARM_INS_ADR_
  "aut", // ARM_INS_AUT
  "autg", // ARM_INS_AUTG
  "bfl", // ARM_INS_BFL
--- a/arch/ARM/ARMGenCSMappingInsnOp.inc
+++ b/arch/ARM/ARMGenCSMappingInsnOp.inc
--- a/arch/ARM/ARMGenCSOpGroup.inc
+++ b/arch/ARM/ARMGenCSOpGroup.inc
@ -1,28 +1,35 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
 /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */

 /* Do not edit. */

 /* Capstone's LLVM TableGen Backends: */
 /* https://github.com/capstone-engine/llvm-capstone */

-ARM_OP_GROUP_RegImmShift = 0,
-	ARM_OP_GROUP_LdStmModeOperand = 1,
-	ARM_OP_GROUP_MandatoryInvertedPredicateOperand = 2,
-	ARM_OP_GROUP_Operand = 3, ARM_OP_GROUP_ModImmOperand = 4,
-	ARM_OP_GROUP_PredicateOperand = 5, ARM_OP_GROUP_SORegImmOperand = 6,
-	ARM_OP_GROUP_SORegRegOperand = 7, ARM_OP_GROUP_SBitModifierOperand = 8,
+  ARM_OP_GROUP_LdStmModeOperand = 0,
+  ARM_OP_GROUP_MandatoryInvertedPredicateOperand = 1,
+  ARM_OP_GROUP_RegImmShift = 2,
+  ARM_OP_GROUP_Operand = 3,
+  ARM_OP_GROUP_ModImmOperand = 4,
+  ARM_OP_GROUP_PredicateOperand = 5,
+  ARM_OP_GROUP_SORegImmOperand = 6,
+  ARM_OP_GROUP_SORegRegOperand = 7,
+  ARM_OP_GROUP_SBitModifierOperand = 8,
  ARM_OP_GROUP_AddrModeImm12Operand_0 = 9,
-	ARM_OP_GROUP_AddrMode2Operand = 10, ARM_OP_GROUP_CPInstOperand = 11,
+  ARM_OP_GROUP_AddrMode2Operand = 10,
+  ARM_OP_GROUP_CPInstOperand = 11,
  ARM_OP_GROUP_MandatoryPredicateOperand = 12,
-	ARM_OP_GROUP_ThumbITMask = 13, ARM_OP_GROUP_RegisterList = 14,
-	ARM_OP_GROUP_AddrMode7Operand = 15, ARM_OP_GROUP_GPRPairOperand = 16,
-	ARM_OP_GROUP_AddrMode3Operand_0 = 17, ARM_OP_GROUP_PCLabel = 18,
+  ARM_OP_GROUP_ThumbITMask = 13,
+  ARM_OP_GROUP_RegisterList = 14,
+  ARM_OP_GROUP_AddrMode7Operand = 15,
+  ARM_OP_GROUP_GPRPairOperand = 16,
+  ARM_OP_GROUP_AddrMode3Operand_0 = 17,
+  ARM_OP_GROUP_PCLabel = 18,
  ARM_OP_GROUP_AddrModePCOperand = 19,
  ARM_OP_GROUP_AddrMode2OffsetOperand = 20,
  ARM_OP_GROUP_AddrMode3OffsetOperand = 21,
@ -34,53 +41,71 @@ ARM_OP_GROUP_RegImmShift = 0,
  ARM_OP_GROUP_VectorListFourAllLanes = 27,
  ARM_OP_GROUP_VectorListFourSpacedAllLanes = 28,
  ARM_OP_GROUP_VectorListFour = 29,
-	ARM_OP_GROUP_VectorListFourSpaced = 30, ARM_OP_GROUP_T2SOOperand = 31,
-	ARM_OP_GROUP_T2AddrModeImm8OffsetOperand = 32,
-	ARM_OP_GROUP_T2AddrModeImm8Operand_1 = 33,
-	ARM_OP_GROUP_AdrLabelOperand_0 = 34, ARM_OP_GROUP_VectorIndex = 35,
-	ARM_OP_GROUP_BitfieldInvMaskImmOperand = 36,
-	ARM_OP_GROUP_PImmediate = 37, ARM_OP_GROUP_VPTPredicateOperand = 38,
-	ARM_OP_GROUP_CImmediate = 39, ARM_OP_GROUP_CPSIMod = 40,
-	ARM_OP_GROUP_CPSIFlag = 41, ARM_OP_GROUP_MemBOption = 42,
-	ARM_OP_GROUP_FPImmOperand = 43, ARM_OP_GROUP_InstSyncBOption = 44,
-	ARM_OP_GROUP_AddrMode5Operand_0 = 45, ARM_OP_GROUP_CoprocOptionImm = 46,
-	ARM_OP_GROUP_PostIdxImm8s4Operand = 47,
-	ARM_OP_GROUP_AddrMode5Operand_1 = 48,
-	ARM_OP_GROUP_AddrModeImm12Operand_1 = 49,
-	ARM_OP_GROUP_AddrMode3Operand_1 = 50,
-	ARM_OP_GROUP_PostIdxImm8Operand = 51,
-	ARM_OP_GROUP_PostIdxRegOperand = 52, ARM_OP_GROUP_BankedRegOperand = 53,
-	ARM_OP_GROUP_MSRMaskOperand = 54, ARM_OP_GROUP_MveSaturateOp = 55,
-	ARM_OP_GROUP_VMOVModImmOperand = 56,
-	ARM_OP_GROUP_ComplexRotationOp_180_90 = 57,
-	ARM_OP_GROUP_ComplexRotationOp_90_0 = 58,
-	ARM_OP_GROUP_MandatoryRestrictedPredicateOperand = 59,
-	ARM_OP_GROUP_MVEVectorList_2 = 60, ARM_OP_GROUP_MVEVectorList_4 = 61,
-	ARM_OP_GROUP_T2AddrModeImm8Operand_0 = 62,
+  ARM_OP_GROUP_VectorListFourSpaced = 30,
+  ARM_OP_GROUP_T2SOOperand = 31,
+  ARM_OP_GROUP_T2AddrModeImm8Operand_0 = 32,
+  ARM_OP_GROUP_T2AddrModeImm8OffsetOperand = 33,
+  ARM_OP_GROUP_T2AddrModeImm8Operand_1 = 34,
+  ARM_OP_GROUP_AdrLabelOperand_0 = 35,
+  ARM_OP_GROUP_VectorIndex = 36,
+  ARM_OP_GROUP_BitfieldInvMaskImmOperand = 37,
+  ARM_OP_GROUP_PImmediate = 38,
+  ARM_OP_GROUP_VPTPredicateOperand = 39,
+  ARM_OP_GROUP_CImmediate = 40,
+  ARM_OP_GROUP_CPSIMod = 41,
+  ARM_OP_GROUP_CPSIFlag = 42,
+  ARM_OP_GROUP_MemBOption = 43,
+  ARM_OP_GROUP_FPImmOperand = 44,
+  ARM_OP_GROUP_InstSyncBOption = 45,
+  ARM_OP_GROUP_AddrMode5Operand_0 = 46,
+  ARM_OP_GROUP_CoprocOptionImm = 47,
+  ARM_OP_GROUP_PostIdxImm8s4Operand = 48,
+  ARM_OP_GROUP_AddrMode5Operand_1 = 49,
+  ARM_OP_GROUP_AddrModeImm12Operand_1 = 50,
+  ARM_OP_GROUP_AddrMode3Operand_1 = 51,
+  ARM_OP_GROUP_PostIdxImm8Operand = 52,
+  ARM_OP_GROUP_PostIdxRegOperand = 53,
+  ARM_OP_GROUP_BankedRegOperand = 54,
+  ARM_OP_GROUP_MSRMaskOperand = 55,
+  ARM_OP_GROUP_MveSaturateOp = 56,
+  ARM_OP_GROUP_VMOVModImmOperand = 57,
+  ARM_OP_GROUP_ComplexRotationOp_180_90 = 58,
+  ARM_OP_GROUP_ComplexRotationOp_90_0 = 59,
+  ARM_OP_GROUP_MandatoryRestrictedPredicateOperand = 60,
+  ARM_OP_GROUP_MVEVectorList_2 = 61,
+  ARM_OP_GROUP_MVEVectorList_4 = 62,
  ARM_OP_GROUP_MveAddrModeRQOperand_0 = 63,
  ARM_OP_GROUP_MveAddrModeRQOperand_3 = 64,
  ARM_OP_GROUP_MveAddrModeRQOperand_1 = 65,
-	ARM_OP_GROUP_MveAddrModeRQOperand_2 = 66, ARM_OP_GROUP_VPTMask = 67,
-	ARM_OP_GROUP_PKHLSLShiftImm = 68, ARM_OP_GROUP_PKHASRShiftImm = 69,
-	ARM_OP_GROUP_ImmPlusOneOperand = 70, ARM_OP_GROUP_SetendOperand = 71,
-	ARM_OP_GROUP_ShiftImmOperand = 72, ARM_OP_GROUP_RotImmOperand = 73,
+  ARM_OP_GROUP_MveAddrModeRQOperand_2 = 66,
+  ARM_OP_GROUP_VPTMask = 67,
+  ARM_OP_GROUP_PKHLSLShiftImm = 68,
+  ARM_OP_GROUP_PKHASRShiftImm = 69,
+  ARM_OP_GROUP_ImmPlusOneOperand = 70,
+  ARM_OP_GROUP_SetendOperand = 71,
+  ARM_OP_GROUP_ShiftImmOperand = 72,
+  ARM_OP_GROUP_RotImmOperand = 73,
  ARM_OP_GROUP_TraceSyncBOption = 74,
  ARM_OP_GROUP_VectorListOneAllLanes = 75,
  ARM_OP_GROUP_VectorListTwoAllLanes = 76,
  ARM_OP_GROUP_NoHashImmediate = 77,
  ARM_OP_GROUP_AddrMode6OffsetOperand = 78,
-	ARM_OP_GROUP_VectorListOne = 79, ARM_OP_GROUP_VectorListTwo = 80,
+  ARM_OP_GROUP_VectorListOne = 79,
+  ARM_OP_GROUP_VectorListTwo = 80,
  ARM_OP_GROUP_VectorListTwoSpacedAllLanes = 81,
  ARM_OP_GROUP_VectorListTwoSpaced = 82,
  ARM_OP_GROUP_AddrMode5FP16Operand_0 = 83,
  ARM_OP_GROUP_T2AddrModeImm8s4Operand_0 = 84,
  ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand = 85,
-	ARM_OP_GROUP_T2AddrModeImm8s4Operand_1 = 86, ARM_OP_GROUP_FBits16 = 87,
-	ARM_OP_GROUP_FBits32 = 88, ARM_OP_GROUP_ThumbSRImm = 89,
+  ARM_OP_GROUP_T2AddrModeImm8s4Operand_1 = 86,
+  ARM_OP_GROUP_FBits16 = 87,
+  ARM_OP_GROUP_FBits32 = 88,
+  ARM_OP_GROUP_ThumbSRImm = 89,
  ARM_OP_GROUP_ThumbLdrLabelOperand = 90,
  ARM_OP_GROUP_T2AddrModeSoRegOperand = 91,
  ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand = 92,
-	ARM_OP_GROUP_AddrModeTBB = 93, ARM_OP_GROUP_AddrModeTBH = 94,
+  ARM_OP_GROUP_AddrModeTBB = 93,
+  ARM_OP_GROUP_AddrModeTBH = 94,
  ARM_OP_GROUP_ThumbS4ImmOperand = 95,
  ARM_OP_GROUP_AdrLabelOperand_2 = 96,
  ARM_OP_GROUP_ThumbAddrModeImm5S1Operand = 97,
--- a/arch/ARM/ARMGenDisassemblerTables.inc
+++ b/arch/ARM/ARMGenDisassemblerTables.inc
--- a/arch/ARM/ARMGenInstrInfo.inc
+++ b/arch/ARM/ARMGenInstrInfo.inc
--- a/arch/ARM/ARMGenRegisterInfo.inc
+++ b/arch/ARM/ARMGenRegisterInfo.inc
--- a/arch/ARM/ARMGenSubtargetInfo.inc
+++ b/arch/ARM/ARMGenSubtargetInfo.inc
@ -1,10 +1,10 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
 /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */

 /* Do not edit. */

@ -53,189 +53,196 @@ enum {
  ARM_ARMv92a = 35,
  ARM_ARMv93a = 36,
  ARM_ARMv94a = 37,
-	ARM_Feature8MSecExt = 38,
-	ARM_FeatureAAPCSFrameChain = 39,
-	ARM_FeatureAAPCSFrameChainLeaf = 40,
-	ARM_FeatureAClass = 41,
-	ARM_FeatureAES = 42,
-	ARM_FeatureAcquireRelease = 43,
-	ARM_FeatureAtomics32 = 44,
-	ARM_FeatureAvoidMOVsShOp = 45,
-	ARM_FeatureAvoidPartialCPSR = 46,
-	ARM_FeatureBF16 = 47,
-	ARM_FeatureCLRBHB = 48,
-	ARM_FeatureCRC = 49,
-	ARM_FeatureCheapPredicableCPSR = 50,
-	ARM_FeatureCheckVLDnAlign = 51,
-	ARM_FeatureCoprocCDE0 = 52,
-	ARM_FeatureCoprocCDE1 = 53,
-	ARM_FeatureCoprocCDE2 = 54,
-	ARM_FeatureCoprocCDE3 = 55,
-	ARM_FeatureCoprocCDE4 = 56,
-	ARM_FeatureCoprocCDE5 = 57,
-	ARM_FeatureCoprocCDE6 = 58,
-	ARM_FeatureCoprocCDE7 = 59,
-	ARM_FeatureCrypto = 60,
-	ARM_FeatureD32 = 61,
-	ARM_FeatureDB = 62,
-	ARM_FeatureDFB = 63,
-	ARM_FeatureDSP = 64,
-	ARM_FeatureDontWidenVMOVS = 65,
-	ARM_FeatureDotProd = 66,
-	ARM_FeatureExecuteOnly = 67,
-	ARM_FeatureExpandMLx = 68,
-	ARM_FeatureFP16 = 69,
-	ARM_FeatureFP16FML = 70,
-	ARM_FeatureFP64 = 71,
-	ARM_FeatureFPAO = 72,
-	ARM_FeatureFPARMv8 = 73,
-	ARM_FeatureFPARMv8_D16 = 74,
-	ARM_FeatureFPARMv8_D16_SP = 75,
-	ARM_FeatureFPARMv8_SP = 76,
-	ARM_FeatureFPRegs = 77,
-	ARM_FeatureFPRegs16 = 78,
-	ARM_FeatureFPRegs64 = 79,
-	ARM_FeatureFixCMSE_CVE_2021_35465 = 80,
-	ARM_FeatureFixCortexA57AES1742098 = 81,
-	ARM_FeatureFullFP16 = 82,
-	ARM_FeatureFuseAES = 83,
-	ARM_FeatureFuseLiterals = 84,
-	ARM_FeatureHWDivARM = 85,
-	ARM_FeatureHWDivThumb = 86,
-	ARM_FeatureHardenSlsBlr = 87,
-	ARM_FeatureHardenSlsNoComdat = 88,
-	ARM_FeatureHardenSlsRetBr = 89,
-	ARM_FeatureHasNoBranchPredictor = 90,
-	ARM_FeatureHasRetAddrStack = 91,
-	ARM_FeatureHasSlowFPVFMx = 92,
-	ARM_FeatureHasSlowFPVMLx = 93,
-	ARM_FeatureHasVMLxHazards = 94,
-	ARM_FeatureLOB = 95,
-	ARM_FeatureLongCalls = 96,
-	ARM_FeatureMClass = 97,
-	ARM_FeatureMP = 98,
-	ARM_FeatureMVEVectorCostFactor1 = 99,
-	ARM_FeatureMVEVectorCostFactor2 = 100,
-	ARM_FeatureMVEVectorCostFactor4 = 101,
-	ARM_FeatureMatMulInt8 = 102,
-	ARM_FeatureMuxedUnits = 103,
-	ARM_FeatureNEON = 104,
-	ARM_FeatureNEONForFP = 105,
-	ARM_FeatureNEONForFPMovs = 106,
-	ARM_FeatureNaClTrap = 107,
-	ARM_FeatureNoARM = 108,
-	ARM_FeatureNoBTIAtReturnTwice = 109,
-	ARM_FeatureNoMovt = 110,
-	ARM_FeatureNoNegativeImmediates = 111,
-	ARM_FeatureNoPostRASched = 112,
-	ARM_FeatureNonpipelinedVFP = 113,
-	ARM_FeaturePACBTI = 114,
-	ARM_FeaturePerfMon = 115,
-	ARM_FeaturePref32BitThumb = 116,
-	ARM_FeaturePrefISHSTBarrier = 117,
-	ARM_FeaturePrefLoopAlign32 = 118,
-	ARM_FeaturePreferVMOVSR = 119,
-	ARM_FeatureProfUnpredicate = 120,
-	ARM_FeatureRAS = 121,
-	ARM_FeatureRClass = 122,
-	ARM_FeatureReadTp = 123,
-	ARM_FeatureReserveR9 = 124,
-	ARM_FeatureSB = 125,
-	ARM_FeatureSHA2 = 126,
-	ARM_FeatureSlowFPBrcc = 127,
-	ARM_FeatureSlowLoadDSubreg = 128,
-	ARM_FeatureSlowOddRegister = 129,
-	ARM_FeatureSlowVDUP32 = 130,
-	ARM_FeatureSlowVGETLNi32 = 131,
-	ARM_FeatureSplatVFPToNeon = 132,
-	ARM_FeatureStrictAlign = 133,
-	ARM_FeatureThumb2 = 134,
-	ARM_FeatureTrustZone = 135,
-	ARM_FeatureUseMIPipeliner = 136,
-	ARM_FeatureUseMISched = 137,
-	ARM_FeatureUseWideStrideVFP = 138,
-	ARM_FeatureV7Clrex = 139,
-	ARM_FeatureVFP2 = 140,
-	ARM_FeatureVFP2_SP = 141,
-	ARM_FeatureVFP3 = 142,
-	ARM_FeatureVFP3_D16 = 143,
-	ARM_FeatureVFP3_D16_SP = 144,
-	ARM_FeatureVFP3_SP = 145,
-	ARM_FeatureVFP4 = 146,
-	ARM_FeatureVFP4_D16 = 147,
-	ARM_FeatureVFP4_D16_SP = 148,
-	ARM_FeatureVFP4_SP = 149,
-	ARM_FeatureVMLxForwarding = 150,
-	ARM_FeatureVirtualization = 151,
-	ARM_FeatureZCZeroing = 152,
-	ARM_HasCDEOps = 153,
-	ARM_HasMVEFloatOps = 154,
-	ARM_HasMVEIntegerOps = 155,
-	ARM_HasV4TOps = 156,
-	ARM_HasV5TEOps = 157,
-	ARM_HasV5TOps = 158,
-	ARM_HasV6KOps = 159,
-	ARM_HasV6MOps = 160,
-	ARM_HasV6Ops = 161,
-	ARM_HasV6T2Ops = 162,
-	ARM_HasV7Ops = 163,
-	ARM_HasV8MBaselineOps = 164,
-	ARM_HasV8MMainlineOps = 165,
-	ARM_HasV8Ops = 166,
-	ARM_HasV8_1MMainlineOps = 167,
-	ARM_HasV8_1aOps = 168,
-	ARM_HasV8_2aOps = 169,
-	ARM_HasV8_3aOps = 170,
-	ARM_HasV8_4aOps = 171,
-	ARM_HasV8_5aOps = 172,
-	ARM_HasV8_6aOps = 173,
-	ARM_HasV8_7aOps = 174,
-	ARM_HasV8_8aOps = 175,
-	ARM_HasV8_9aOps = 176,
-	ARM_HasV9_0aOps = 177,
-	ARM_HasV9_1aOps = 178,
-	ARM_HasV9_2aOps = 179,
-	ARM_HasV9_3aOps = 180,
-	ARM_HasV9_4aOps = 181,
-	ARM_IWMMXT = 182,
-	ARM_IWMMXT2 = 183,
-	ARM_ModeBigEndianInstructions = 184,
-	ARM_ModeSoftFloat = 185,
-	ARM_ModeThumb = 186,
-	ARM_ProcA5 = 187,
-	ARM_ProcA7 = 188,
-	ARM_ProcA8 = 189,
-	ARM_ProcA9 = 190,
-	ARM_ProcA12 = 191,
-	ARM_ProcA15 = 192,
-	ARM_ProcA17 = 193,
-	ARM_ProcA32 = 194,
-	ARM_ProcA35 = 195,
-	ARM_ProcA53 = 196,
-	ARM_ProcA55 = 197,
-	ARM_ProcA57 = 198,
-	ARM_ProcA72 = 199,
-	ARM_ProcA73 = 200,
-	ARM_ProcA75 = 201,
-	ARM_ProcA76 = 202,
-	ARM_ProcA77 = 203,
-	ARM_ProcA78 = 204,
-	ARM_ProcA78C = 205,
-	ARM_ProcA710 = 206,
-	ARM_ProcExynos = 207,
-	ARM_ProcKrait = 208,
-	ARM_ProcKryo = 209,
-	ARM_ProcM3 = 210,
-	ARM_ProcM7 = 211,
-	ARM_ProcR4 = 212,
-	ARM_ProcR5 = 213,
-	ARM_ProcR7 = 214,
-	ARM_ProcR52 = 215,
-	ARM_ProcSwift = 216,
-	ARM_ProcV1 = 217,
-	ARM_ProcX1 = 218,
-	ARM_ProcX1C = 219,
-	ARM_XScale = 220,
-	ARM_NumSubtargetFeatures = 221
+  ARM_ARMv95a = 38,
+  ARM_Feature8MSecExt = 39,
+  ARM_FeatureAAPCSFrameChain = 40,
+  ARM_FeatureAAPCSFrameChainLeaf = 41,
+  ARM_FeatureAClass = 42,
+  ARM_FeatureAES = 43,
+  ARM_FeatureAcquireRelease = 44,
+  ARM_FeatureAtomics32 = 45,
+  ARM_FeatureAvoidMOVsShOp = 46,
+  ARM_FeatureAvoidPartialCPSR = 47,
+  ARM_FeatureBF16 = 48,
+  ARM_FeatureCLRBHB = 49,
+  ARM_FeatureCRC = 50,
+  ARM_FeatureCheapPredicableCPSR = 51,
+  ARM_FeatureCheckVLDnAlign = 52,
+  ARM_FeatureCoprocCDE0 = 53,
+  ARM_FeatureCoprocCDE1 = 54,
+  ARM_FeatureCoprocCDE2 = 55,
+  ARM_FeatureCoprocCDE3 = 56,
+  ARM_FeatureCoprocCDE4 = 57,
+  ARM_FeatureCoprocCDE5 = 58,
+  ARM_FeatureCoprocCDE6 = 59,
+  ARM_FeatureCoprocCDE7 = 60,
+  ARM_FeatureCrypto = 61,
+  ARM_FeatureD32 = 62,
+  ARM_FeatureDB = 63,
+  ARM_FeatureDFB = 64,
+  ARM_FeatureDSP = 65,
+  ARM_FeatureDontWidenVMOVS = 66,
+  ARM_FeatureDotProd = 67,
+  ARM_FeatureExecuteOnly = 68,
+  ARM_FeatureExpandMLx = 69,
+  ARM_FeatureFP16 = 70,
+  ARM_FeatureFP16FML = 71,
+  ARM_FeatureFP64 = 72,
+  ARM_FeatureFPAO = 73,
+  ARM_FeatureFPARMv8 = 74,
+  ARM_FeatureFPARMv8_D16 = 75,
+  ARM_FeatureFPARMv8_D16_SP = 76,
+  ARM_FeatureFPARMv8_SP = 77,
+  ARM_FeatureFPRegs = 78,
+  ARM_FeatureFPRegs16 = 79,
+  ARM_FeatureFPRegs64 = 80,
+  ARM_FeatureFixCMSE_CVE_2021_35465 = 81,
+  ARM_FeatureFixCortexA57AES1742098 = 82,
+  ARM_FeatureFullFP16 = 83,
+  ARM_FeatureFuseAES = 84,
+  ARM_FeatureFuseLiterals = 85,
+  ARM_FeatureHWDivARM = 86,
+  ARM_FeatureHWDivThumb = 87,
+  ARM_FeatureHardenSlsBlr = 88,
+  ARM_FeatureHardenSlsNoComdat = 89,
+  ARM_FeatureHardenSlsRetBr = 90,
+  ARM_FeatureHasNoBranchPredictor = 91,
+  ARM_FeatureHasRetAddrStack = 92,
+  ARM_FeatureHasSlowFPVFMx = 93,
+  ARM_FeatureHasSlowFPVMLx = 94,
+  ARM_FeatureHasVMLxHazards = 95,
+  ARM_FeatureLOB = 96,
+  ARM_FeatureLongCalls = 97,
+  ARM_FeatureMClass = 98,
+  ARM_FeatureMP = 99,
+  ARM_FeatureMVEVectorCostFactor1 = 100,
+  ARM_FeatureMVEVectorCostFactor2 = 101,
+  ARM_FeatureMVEVectorCostFactor4 = 102,
+  ARM_FeatureMatMulInt8 = 103,
+  ARM_FeatureMuxedUnits = 104,
+  ARM_FeatureNEON = 105,
+  ARM_FeatureNEONForFP = 106,
+  ARM_FeatureNEONForFPMovs = 107,
+  ARM_FeatureNaClTrap = 108,
+  ARM_FeatureNoARM = 109,
+  ARM_FeatureNoBTIAtReturnTwice = 110,
+  ARM_FeatureNoMovt = 111,
+  ARM_FeatureNoNegativeImmediates = 112,
+  ARM_FeatureNoPostRASched = 113,
+  ARM_FeatureNonpipelinedVFP = 114,
+  ARM_FeaturePACBTI = 115,
+  ARM_FeaturePerfMon = 116,
+  ARM_FeaturePref32BitThumb = 117,
+  ARM_FeaturePrefISHSTBarrier = 118,
+  ARM_FeaturePrefLoopAlign32 = 119,
+  ARM_FeaturePreferVMOVSR = 120,
+  ARM_FeatureProfUnpredicate = 121,
+  ARM_FeatureRAS = 122,
+  ARM_FeatureRClass = 123,
+  ARM_FeatureReadTpTPIDRPRW = 124,
+  ARM_FeatureReadTpTPIDRURO = 125,
+  ARM_FeatureReadTpTPIDRURW = 126,
+  ARM_FeatureReserveR9 = 127,
+  ARM_FeatureSB = 128,
+  ARM_FeatureSHA2 = 129,
+  ARM_FeatureSlowFPBrcc = 130,
+  ARM_FeatureSlowLoadDSubreg = 131,
+  ARM_FeatureSlowOddRegister = 132,
+  ARM_FeatureSlowVDUP32 = 133,
+  ARM_FeatureSlowVGETLNi32 = 134,
+  ARM_FeatureSplatVFPToNeon = 135,
+  ARM_FeatureStrictAlign = 136,
+  ARM_FeatureThumb2 = 137,
+  ARM_FeatureTrustZone = 138,
+  ARM_FeatureUseMIPipeliner = 139,
+  ARM_FeatureUseMISched = 140,
+  ARM_FeatureUseWideStrideVFP = 141,
+  ARM_FeatureV7Clrex = 142,
+  ARM_FeatureVFP2 = 143,
+  ARM_FeatureVFP2_SP = 144,
+  ARM_FeatureVFP3 = 145,
+  ARM_FeatureVFP3_D16 = 146,
+  ARM_FeatureVFP3_D16_SP = 147,
+  ARM_FeatureVFP3_SP = 148,
+  ARM_FeatureVFP4 = 149,
+  ARM_FeatureVFP4_D16 = 150,
+  ARM_FeatureVFP4_D16_SP = 151,
+  ARM_FeatureVFP4_SP = 152,
+  ARM_FeatureVMLxForwarding = 153,
+  ARM_FeatureVirtualization = 154,
+  ARM_FeatureZCZeroing = 155,
+  ARM_HasCDEOps = 156,
+  ARM_HasMVEFloatOps = 157,
+  ARM_HasMVEIntegerOps = 158,
+  ARM_HasV4TOps = 159,
+  ARM_HasV5TEOps = 160,
+  ARM_HasV5TOps = 161,
+  ARM_HasV6KOps = 162,
+  ARM_HasV6MOps = 163,
+  ARM_HasV6Ops = 164,
+  ARM_HasV6T2Ops = 165,
+  ARM_HasV7Ops = 166,
+  ARM_HasV8MBaselineOps = 167,
+  ARM_HasV8MMainlineOps = 168,
+  ARM_HasV8Ops = 169,
+  ARM_HasV8_1MMainlineOps = 170,
+  ARM_HasV8_1aOps = 171,
+  ARM_HasV8_2aOps = 172,
+  ARM_HasV8_3aOps = 173,
+  ARM_HasV8_4aOps = 174,
+  ARM_HasV8_5aOps = 175,
+  ARM_HasV8_6aOps = 176,
+  ARM_HasV8_7aOps = 177,
+  ARM_HasV8_8aOps = 178,
+  ARM_HasV8_9aOps = 179,
+  ARM_HasV9_0aOps = 180,
+  ARM_HasV9_1aOps = 181,
+  ARM_HasV9_2aOps = 182,
+  ARM_HasV9_3aOps = 183,
+  ARM_HasV9_4aOps = 184,
+  ARM_HasV9_5aOps = 185,
+  ARM_IWMMXT = 186,
+  ARM_IWMMXT2 = 187,
+  ARM_ModeBigEndianInstructions = 188,
+  ARM_ModeSoftFloat = 189,
+  ARM_ModeThumb = 190,
+  ARM_ProcA5 = 191,
+  ARM_ProcA7 = 192,
+  ARM_ProcA8 = 193,
+  ARM_ProcA9 = 194,
+  ARM_ProcA12 = 195,
+  ARM_ProcA15 = 196,
+  ARM_ProcA17 = 197,
+  ARM_ProcA32 = 198,
+  ARM_ProcA35 = 199,
+  ARM_ProcA53 = 200,
+  ARM_ProcA55 = 201,
+  ARM_ProcA57 = 202,
+  ARM_ProcA72 = 203,
+  ARM_ProcA73 = 204,
+  ARM_ProcA75 = 205,
+  ARM_ProcA76 = 206,
+  ARM_ProcA77 = 207,
+  ARM_ProcA78 = 208,
+  ARM_ProcA78C = 209,
+  ARM_ProcA710 = 210,
+  ARM_ProcExynos = 211,
+  ARM_ProcKrait = 212,
+  ARM_ProcKryo = 213,
+  ARM_ProcM3 = 214,
+  ARM_ProcM7 = 215,
+  ARM_ProcR4 = 216,
+  ARM_ProcR5 = 217,
+  ARM_ProcR7 = 218,
+  ARM_ProcR52 = 219,
+  ARM_ProcSwift = 220,
+  ARM_ProcV1 = 221,
+  ARM_ProcX1 = 222,
+  ARM_ProcX1C = 223,
+  ARM_XScale = 224,
+  ARM_NumSubtargetFeatures = 225
 };
 #endif // GET_SUBTARGETINFO_ENUM
+
+
+
--- a/arch/ARM/ARMGenSystemRegister.inc
+++ b/arch/ARM/ARMGenSystemRegister.inc
@ -1,10 +1,10 @@
 /* Capstone Disassembly Engine, https://www.capstone-engine.org */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
-/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
 /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */

 /* Do not edit. */

@ -18,102 +18,136 @@
 #endif

 #ifdef GET_BANKEDREG_DECL
-const ARMBankedReg_BankedReg *
-ARMBankedReg_lookupBankedRegByName(const char *Name);
-const ARMBankedReg_BankedReg *
-ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding);
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByName(const char * Name);
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding);
 #endif

 #ifdef GET_MCLASSSYSREG_DECL
-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegByName(const char *Name);
-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);
-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8);
-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding);
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByName(const char * Name);
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8);
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding);
 #endif

 #ifdef GET_BANKEDREG_IMPL
 static const ARMBankedReg_BankedReg BankedRegsList[] = {
-	{ "elr_hyp", { .bankedreg = ARM_BANKEDREG_ELR_HYP }, 0x1E },   // 0
-	{ "lr_abt", { .bankedreg = ARM_BANKEDREG_LR_ABT }, 0x14 },     // 1
-	{ "lr_fiq", { .bankedreg = ARM_BANKEDREG_LR_FIQ }, 0xE },      // 2
-	{ "lr_irq", { .bankedreg = ARM_BANKEDREG_LR_IRQ }, 0x10 },     // 3
-	{ "lr_mon", { .bankedreg = ARM_BANKEDREG_LR_MON }, 0x1C },     // 4
-	{ "lr_svc", { .bankedreg = ARM_BANKEDREG_LR_SVC }, 0x12 },     // 5
-	{ "lr_und", { .bankedreg = ARM_BANKEDREG_LR_UND }, 0x16 },     // 6
-	{ "lr_usr", { .bankedreg = ARM_BANKEDREG_LR_USR }, 0x6 },      // 7
-	{ "r10_fiq", { .bankedreg = ARM_BANKEDREG_R10_FIQ }, 0xA },    // 8
-	{ "r10_usr", { .bankedreg = ARM_BANKEDREG_R10_USR }, 0x2 },    // 9
-	{ "r11_fiq", { .bankedreg = ARM_BANKEDREG_R11_FIQ }, 0xB },    // 10
-	{ "r11_usr", { .bankedreg = ARM_BANKEDREG_R11_USR }, 0x3 },    // 11
-	{ "r12_fiq", { .bankedreg = ARM_BANKEDREG_R12_FIQ }, 0xC },    // 12
-	{ "r12_usr", { .bankedreg = ARM_BANKEDREG_R12_USR }, 0x4 },    // 13
-	{ "r8_fiq", { .bankedreg = ARM_BANKEDREG_R8_FIQ }, 0x8 },      // 14
-	{ "r8_usr", { .bankedreg = ARM_BANKEDREG_R8_USR }, 0x0 },      // 15
-	{ "r9_fiq", { .bankedreg = ARM_BANKEDREG_R9_FIQ }, 0x9 },      // 16
-	{ "r9_usr", { .bankedreg = ARM_BANKEDREG_R9_USR }, 0x1 },      // 17
-	{ "spsr_abt", { .bankedreg = ARM_BANKEDREG_SPSR_ABT }, 0x34 }, // 18
-	{ "spsr_fiq", { .bankedreg = ARM_BANKEDREG_SPSR_FIQ }, 0x2E }, // 19
-	{ "spsr_hyp", { .bankedreg = ARM_BANKEDREG_SPSR_HYP }, 0x3E }, // 20
-	{ "spsr_irq", { .bankedreg = ARM_BANKEDREG_SPSR_IRQ }, 0x30 }, // 21
-	{ "spsr_mon", { .bankedreg = ARM_BANKEDREG_SPSR_MON }, 0x3C }, // 22
-	{ "spsr_svc", { .bankedreg = ARM_BANKEDREG_SPSR_SVC }, 0x32 }, // 23
-	{ "spsr_und", { .bankedreg = ARM_BANKEDREG_SPSR_UND }, 0x36 }, // 24
-	{ "sp_abt", { .bankedreg = ARM_BANKEDREG_SP_ABT }, 0x15 },     // 25
-	{ "sp_fiq", { .bankedreg = ARM_BANKEDREG_SP_FIQ }, 0xD },      // 26
-	{ "sp_hyp", { .bankedreg = ARM_BANKEDREG_SP_HYP }, 0x1F },     // 27
-	{ "sp_irq", { .bankedreg = ARM_BANKEDREG_SP_IRQ }, 0x11 },     // 28
-	{ "sp_mon", { .bankedreg = ARM_BANKEDREG_SP_MON }, 0x1D },     // 29
-	{ "sp_svc", { .bankedreg = ARM_BANKEDREG_SP_SVC }, 0x13 },     // 30
-	{ "sp_und", { .bankedreg = ARM_BANKEDREG_SP_UND }, 0x17 },     // 31
-	{ "sp_usr", { .bankedreg = ARM_BANKEDREG_SP_USR }, 0x5 },      // 32
+  { "elr_hyp", { .raw_val = ARM_BANKEDREG_ELR_HYP }, 0x1E }, // 0
+  { "lr_abt", { .raw_val = ARM_BANKEDREG_LR_ABT }, 0x14 }, // 1
+  { "lr_fiq", { .raw_val = ARM_BANKEDREG_LR_FIQ }, 0xE }, // 2
+  { "lr_irq", { .raw_val = ARM_BANKEDREG_LR_IRQ }, 0x10 }, // 3
+  { "lr_mon", { .raw_val = ARM_BANKEDREG_LR_MON }, 0x1C }, // 4
+  { "lr_svc", { .raw_val = ARM_BANKEDREG_LR_SVC }, 0x12 }, // 5
+  { "lr_und", { .raw_val = ARM_BANKEDREG_LR_UND }, 0x16 }, // 6
+  { "lr_usr", { .raw_val = ARM_BANKEDREG_LR_USR }, 0x6 }, // 7
+  { "r10_fiq", { .raw_val = ARM_BANKEDREG_R10_FIQ }, 0xA }, // 8
+  { "r10_usr", { .raw_val = ARM_BANKEDREG_R10_USR }, 0x2 }, // 9
+  { "r11_fiq", { .raw_val = ARM_BANKEDREG_R11_FIQ }, 0xB }, // 10
+  { "r11_usr", { .raw_val = ARM_BANKEDREG_R11_USR }, 0x3 }, // 11
+  { "r12_fiq", { .raw_val = ARM_BANKEDREG_R12_FIQ }, 0xC }, // 12
+  { "r12_usr", { .raw_val = ARM_BANKEDREG_R12_USR }, 0x4 }, // 13
+  { "r8_fiq", { .raw_val = ARM_BANKEDREG_R8_FIQ }, 0x8 }, // 14
+  { "r8_usr", { .raw_val = ARM_BANKEDREG_R8_USR }, 0x0 }, // 15
+  { "r9_fiq", { .raw_val = ARM_BANKEDREG_R9_FIQ }, 0x9 }, // 16
+  { "r9_usr", { .raw_val = ARM_BANKEDREG_R9_USR }, 0x1 }, // 17
+  { "spsr_abt", { .raw_val = ARM_BANKEDREG_SPSR_ABT }, 0x34 }, // 18
+  { "spsr_fiq", { .raw_val = ARM_BANKEDREG_SPSR_FIQ }, 0x2E }, // 19
+  { "spsr_hyp", { .raw_val = ARM_BANKEDREG_SPSR_HYP }, 0x3E }, // 20
+  { "spsr_irq", { .raw_val = ARM_BANKEDREG_SPSR_IRQ }, 0x30 }, // 21
+  { "spsr_mon", { .raw_val = ARM_BANKEDREG_SPSR_MON }, 0x3C }, // 22
+  { "spsr_svc", { .raw_val = ARM_BANKEDREG_SPSR_SVC }, 0x32 }, // 23
+  { "spsr_und", { .raw_val = ARM_BANKEDREG_SPSR_UND }, 0x36 }, // 24
+  { "sp_abt", { .raw_val = ARM_BANKEDREG_SP_ABT }, 0x15 }, // 25
+  { "sp_fiq", { .raw_val = ARM_BANKEDREG_SP_FIQ }, 0xD }, // 26
+  { "sp_hyp", { .raw_val = ARM_BANKEDREG_SP_HYP }, 0x1F }, // 27
+  { "sp_irq", { .raw_val = ARM_BANKEDREG_SP_IRQ }, 0x11 }, // 28
+  { "sp_mon", { .raw_val = ARM_BANKEDREG_SP_MON }, 0x1D }, // 29
+  { "sp_svc", { .raw_val = ARM_BANKEDREG_SP_SVC }, 0x13 }, // 30
+  { "sp_und", { .raw_val = ARM_BANKEDREG_SP_UND }, 0x17 }, // 31
+  { "sp_usr", { .raw_val = ARM_BANKEDREG_SP_USR }, 0x5 }, // 32
  };

-const ARMBankedReg_BankedReg *
-ARMBankedReg_lookupBankedRegByName(const char *Name)
-{
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByName(const char * Name) {
  static const struct IndexTypeStr Index[] = {
-		{ "ELR_HYP", 0 },   { "LR_ABT", 1 },	{ "LR_FIQ", 2 },
-		{ "LR_IRQ", 3 },    { "LR_MON", 4 },	{ "LR_SVC", 5 },
-		{ "LR_UND", 6 },    { "LR_USR", 7 },	{ "R10_FIQ", 8 },
-		{ "R10_USR", 9 },   { "R11_FIQ", 10 },	{ "R11_USR", 11 },
-		{ "R12_FIQ", 12 },  { "R12_USR", 13 },	{ "R8_FIQ", 14 },
-		{ "R8_USR", 15 },   { "R9_FIQ", 16 },	{ "R9_USR", 17 },
-		{ "SPSR_ABT", 18 }, { "SPSR_FIQ", 19 }, { "SPSR_HYP", 20 },
-		{ "SPSR_IRQ", 21 }, { "SPSR_MON", 22 }, { "SPSR_SVC", 23 },
-		{ "SPSR_UND", 24 }, { "SP_ABT", 25 },	{ "SP_FIQ", 26 },
-		{ "SP_HYP", 27 },   { "SP_IRQ", 28 },	{ "SP_MON", 29 },
-		{ "SP_SVC", 30 },   { "SP_UND", 31 },	{ "SP_USR", 32 },
+    { "ELR_HYP", 0 },
+    { "LR_ABT", 1 },
+    { "LR_FIQ", 2 },
+    { "LR_IRQ", 3 },
+    { "LR_MON", 4 },
+    { "LR_SVC", 5 },
+    { "LR_UND", 6 },
+    { "LR_USR", 7 },
+    { "R10_FIQ", 8 },
+    { "R10_USR", 9 },
+    { "R11_FIQ", 10 },
+    { "R11_USR", 11 },
+    { "R12_FIQ", 12 },
+    { "R12_USR", 13 },
+    { "R8_FIQ", 14 },
+    { "R8_USR", 15 },
+    { "R9_FIQ", 16 },
+    { "R9_USR", 17 },
+    { "SPSR_ABT", 18 },
+    { "SPSR_FIQ", 19 },
+    { "SPSR_HYP", 20 },
+    { "SPSR_IRQ", 21 },
+    { "SPSR_MON", 22 },
+    { "SPSR_SVC", 23 },
+    { "SPSR_UND", 24 },
+    { "SP_ABT", 25 },
+    { "SP_FIQ", 26 },
+    { "SP_HYP", 27 },
+    { "SP_IRQ", 28 },
+    { "SP_MON", 29 },
+    { "SP_SVC", 30 },
+    { "SP_UND", 31 },
+    { "SP_USR", 32 },
  };

-	unsigned i =
-		binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
+   unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
   if (i == -1)
      return NULL;
   else
      return &BankedRegsList[Index[i].index];
 }

-const ARMBankedReg_BankedReg *
-ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding)
-{
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding) {
  static const struct IndexType Index[] = {
-		{ 0x0, 15 },  { 0x1, 17 },  { 0x2, 9 },	  { 0x3, 11 },
-		{ 0x4, 13 },  { 0x5, 32 },  { 0x6, 7 },	  { 0x8, 14 },
-		{ 0x9, 16 },  { 0xA, 8 },   { 0xB, 10 },  { 0xC, 12 },
-		{ 0xD, 26 },  { 0xE, 2 },   { 0x10, 3 },  { 0x11, 28 },
-		{ 0x12, 5 },  { 0x13, 30 }, { 0x14, 1 },  { 0x15, 25 },
-		{ 0x16, 6 },  { 0x17, 31 }, { 0x1C, 4 },  { 0x1D, 29 },
-		{ 0x1E, 0 },  { 0x1F, 27 }, { 0x2E, 19 }, { 0x30, 21 },
-		{ 0x32, 23 }, { 0x34, 18 }, { 0x36, 24 }, { 0x3C, 22 },
+    { 0x0, 15 },
+    { 0x1, 17 },
+    { 0x2, 9 },
+    { 0x3, 11 },
+    { 0x4, 13 },
+    { 0x5, 32 },
+    { 0x6, 7 },
+    { 0x8, 14 },
+    { 0x9, 16 },
+    { 0xA, 8 },
+    { 0xB, 10 },
+    { 0xC, 12 },
+    { 0xD, 26 },
+    { 0xE, 2 },
+    { 0x10, 3 },
+    { 0x11, 28 },
+    { 0x12, 5 },
+    { 0x13, 30 },
+    { 0x14, 1 },
+    { 0x15, 25 },
+    { 0x16, 6 },
+    { 0x17, 31 },
+    { 0x1C, 4 },
+    { 0x1D, 29 },
+    { 0x1E, 0 },
+    { 0x1F, 27 },
+    { 0x2E, 19 },
+    { 0x30, 21 },
+    { 0x32, 23 },
+    { 0x34, 18 },
+    { 0x36, 24 },
+    { 0x3C, 22 },
    { 0x3E, 20 },
  };

-	unsigned i =
-		binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
   if (i == -1)
      return NULL;
   else
@ -124,445 +158,311 @@ ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding)

 #ifdef GET_MCLASSSYSREG_IMPL
 static const ARMSysReg_MClassSysReg MClassSysRegsList[] = {
-	{ "apsr",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_APSR },
-	  0x800,
-	  0x100,
-	  0x800,
-	  { 0 } }, // 0
-	{ "apsr_g",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_APSR_G },
-	  0x400,
-	  0x0,
-	  0x400,
-	  { ARM_FeatureDSP } }, // 1
-	{ "apsr_nzcvq",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_APSR_NZCVQ },
-	  0x1800,
-	  0x200,
-	  0x800,
-	  { 0 } }, // 2
-	{ "apsr_nzcvqg",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_APSR_NZCVQG },
-	  0xC00,
-	  0x300,
-	  0xC00,
-	  { ARM_FeatureDSP } }, // 3
-	{ "basepri",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_BASEPRI },
-	  0x811,
-	  0x111,
-	  0x811,
-	  { ARM_HasV7Ops } }, // 4
-	{ "basepri_max",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_BASEPRI_MAX },
-	  0x812,
-	  0x112,
-	  0x812,
-	  { ARM_HasV7Ops } }, // 5
-	{ "basepri_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_BASEPRI_NS },
-	  0x891,
-	  0x191,
-	  0x891,
-	  { ARM_Feature8MSecExt, ARM_HasV7Ops } }, // 6
-	{ "control",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_CONTROL },
-	  0x814,
-	  0x114,
-	  0x814,
-	  { 0 } }, // 7
-	{ "control_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_CONTROL_NS },
-	  0x894,
-	  0x194,
-	  0x894,
-	  { ARM_Feature8MSecExt } }, // 8
-	{ "eapsr",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_EAPSR },
-	  0x802,
-	  0x102,
-	  0x802,
-	  { 0 } }, // 9
-	{ "eapsr_g",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_EAPSR_G },
-	  0x402,
-	  0x2,
-	  0x402,
-	  { ARM_FeatureDSP } }, // 10
-	{ "eapsr_nzcvq",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_EAPSR_NZCVQ },
-	  0x1802,
-	  0x202,
-	  0x802,
-	  { 0 } }, // 11
-	{ "eapsr_nzcvqg",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_EAPSR_NZCVQG },
-	  0xC02,
-	  0x302,
-	  0xC02,
-	  { ARM_FeatureDSP } }, // 12
-	{ "epsr",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_EPSR },
-	  0x806,
-	  0x106,
-	  0x806,
-	  { 0 } }, // 13
-	{ "faultmask",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_FAULTMASK },
-	  0x813,
-	  0x113,
-	  0x813,
-	  { ARM_HasV7Ops } }, // 14
-	{ "faultmask_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_FAULTMASK_NS },
-	  0x893,
-	  0x193,
-	  0x893,
-	  { ARM_Feature8MSecExt, ARM_HasV7Ops } }, // 15
-	{ "iapsr",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_IAPSR },
-	  0x801,
-	  0x101,
-	  0x801,
-	  { 0 } }, // 16
-	{ "iapsr_g",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_IAPSR_G },
-	  0x401,
-	  0x1,
-	  0x401,
-	  { ARM_FeatureDSP } }, // 17
-	{ "iapsr_nzcvq",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_IAPSR_NZCVQ },
-	  0x1801,
-	  0x201,
-	  0x801,
-	  { 0 } }, // 18
-	{ "iapsr_nzcvqg",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_IAPSR_NZCVQG },
-	  0xC01,
-	  0x301,
-	  0xC01,
-	  { ARM_FeatureDSP } }, // 19
-	{ "iepsr",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_IEPSR },
-	  0x807,
-	  0x107,
-	  0x807,
-	  { 0 } }, // 20
-	{ "ipsr",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_IPSR },
-	  0x805,
-	  0x105,
-	  0x805,
-	  { 0 } }, // 21
-	{ "msp",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_MSP },
-	  0x808,
-	  0x108,
-	  0x808,
-	  { 0 } }, // 22
-	{ "msplim",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_MSPLIM },
-	  0x80A,
-	  0x10A,
-	  0x80A,
-	  { ARM_HasV8MBaselineOps } }, // 23
-	{ "msplim_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_MSPLIM_NS },
-	  0x88A,
-	  0x18A,
-	  0x88A,
-	  { ARM_Feature8MSecExt, ARM_HasV8MBaselineOps } }, // 24
-	{ "msp_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_MSP_NS },
-	  0x888,
-	  0x188,
-	  0x888,
-	  { ARM_Feature8MSecExt } }, // 25
-	{ "pac_key_p_0",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_0 },
-	  0x820,
-	  0x120,
-	  0x820,
-	  { ARM_FeaturePACBTI } }, // 26
-	{ "pac_key_p_0_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_0_NS },
-	  0x8A0,
-	  0x1A0,
-	  0x8A0,
-	  { ARM_FeaturePACBTI } }, // 27
-	{ "pac_key_p_1",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_1 },
-	  0x821,
-	  0x121,
-	  0x821,
-	  { ARM_FeaturePACBTI } }, // 28
-	{ "pac_key_p_1_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_1_NS },
-	  0x8A1,
-	  0x1A1,
-	  0x8A1,
-	  { ARM_FeaturePACBTI } }, // 29
-	{ "pac_key_p_2",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_2 },
-	  0x822,
-	  0x122,
-	  0x822,
-	  { ARM_FeaturePACBTI } }, // 30
-	{ "pac_key_p_2_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_2_NS },
-	  0x8A2,
-	  0x1A2,
-	  0x8A2,
-	  { ARM_FeaturePACBTI } }, // 31
-	{ "pac_key_p_3",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_3 },
-	  0x823,
-	  0x123,
-	  0x823,
-	  { ARM_FeaturePACBTI } }, // 32
-	{ "pac_key_p_3_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_3_NS },
-	  0x8A3,
-	  0x1A3,
-	  0x8A3,
-	  { ARM_FeaturePACBTI } }, // 33
-	{ "pac_key_u_0",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_0 },
-	  0x824,
-	  0x124,
-	  0x824,
-	  { ARM_FeaturePACBTI } }, // 34
-	{ "pac_key_u_0_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_0_NS },
-	  0x8A4,
-	  0x1A4,
-	  0x8A4,
-	  { ARM_FeaturePACBTI } }, // 35
-	{ "pac_key_u_1",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_1 },
-	  0x825,
-	  0x125,
-	  0x825,
-	  { ARM_FeaturePACBTI } }, // 36
-	{ "pac_key_u_1_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_1_NS },
-	  0x8A5,
-	  0x1A5,
-	  0x8A5,
-	  { ARM_FeaturePACBTI } }, // 37
-	{ "pac_key_u_2",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_2 },
-	  0x826,
-	  0x126,
-	  0x826,
-	  { ARM_FeaturePACBTI } }, // 38
-	{ "pac_key_u_2_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_2_NS },
-	  0x8A6,
-	  0x1A6,
-	  0x8A6,
-	  { ARM_FeaturePACBTI } }, // 39
-	{ "pac_key_u_3",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_3 },
-	  0x827,
-	  0x127,
-	  0x827,
-	  { ARM_FeaturePACBTI } }, // 40
-	{ "pac_key_u_3_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_3_NS },
-	  0x8A7,
-	  0x1A7,
-	  0x8A7,
-	  { ARM_FeaturePACBTI } }, // 41
-	{ "primask",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PRIMASK },
-	  0x810,
-	  0x110,
-	  0x810,
-	  { 0 } }, // 42
-	{ "primask_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PRIMASK_NS },
-	  0x890,
-	  0x190,
-	  0x890,
-	  { 0 } }, // 43
-	{ "psp",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PSP },
-	  0x809,
-	  0x109,
-	  0x809,
-	  { 0 } }, // 44
-	{ "psplim",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PSPLIM },
-	  0x80B,
-	  0x10B,
-	  0x80B,
-	  { ARM_HasV8MBaselineOps } }, // 45
-	{ "psplim_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PSPLIM_NS },
-	  0x88B,
-	  0x18B,
-	  0x88B,
-	  { ARM_Feature8MSecExt, ARM_HasV8MBaselineOps } }, // 46
-	{ "psp_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_PSP_NS },
-	  0x889,
-	  0x189,
-	  0x889,
-	  { ARM_Feature8MSecExt } }, // 47
-	{ "sp_ns",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_SP_NS },
-	  0x898,
-	  0x198,
-	  0x898,
-	  { ARM_Feature8MSecExt } }, // 48
-	{ "xpsr",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_XPSR },
-	  0x803,
-	  0x103,
-	  0x803,
-	  { 0 } }, // 49
-	{ "xpsr_g",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_XPSR_G },
-	  0x403,
-	  0x3,
-	  0x403,
-	  { ARM_FeatureDSP } }, // 50
-	{ "xpsr_nzcvq",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_XPSR_NZCVQ },
-	  0x1803,
-	  0x203,
-	  0x803,
-	  { 0 } }, // 51
-	{ "xpsr_nzcvqg",
-	  { .mclasssysreg = ARM_MCLASSSYSREG_XPSR_NZCVQG },
-	  0xC03,
-	  0x303,
-	  0xC03,
-	  { ARM_FeatureDSP } }, // 52
+  { "apsr", { .raw_val = ARM_MCLASSSYSREG_APSR }, 0x800, 0x100, 0x800,  {0}  }, // 0
+  { "apsr_g", { .raw_val = ARM_MCLASSSYSREG_APSR_G }, 0x400, 0x0, 0x400,  {ARM_FeatureDSP}  }, // 1
+  { "apsr_nzcvq", { .raw_val = ARM_MCLASSSYSREG_APSR_NZCVQ }, 0x1800, 0x200, 0x800,  {0}  }, // 2
+  { "apsr_nzcvqg", { .raw_val = ARM_MCLASSSYSREG_APSR_NZCVQG }, 0xC00, 0x300, 0xC00,  {ARM_FeatureDSP}  }, // 3
+  { "basepri", { .raw_val = ARM_MCLASSSYSREG_BASEPRI }, 0x811, 0x111, 0x811,  {ARM_HasV7Ops}  }, // 4
+  { "basepri_max", { .raw_val = ARM_MCLASSSYSREG_BASEPRI_MAX }, 0x812, 0x112, 0x812,  {ARM_HasV7Ops}  }, // 5
+  { "basepri_ns", { .raw_val = ARM_MCLASSSYSREG_BASEPRI_NS }, 0x891, 0x191, 0x891,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 6
+  { "control", { .raw_val = ARM_MCLASSSYSREG_CONTROL }, 0x814, 0x114, 0x814,  {0}  }, // 7
+  { "control_ns", { .raw_val = ARM_MCLASSSYSREG_CONTROL_NS }, 0x894, 0x194, 0x894,  {ARM_Feature8MSecExt}  }, // 8
+  { "eapsr", { .raw_val = ARM_MCLASSSYSREG_EAPSR }, 0x802, 0x102, 0x802,  {0}  }, // 9
+  { "eapsr_g", { .raw_val = ARM_MCLASSSYSREG_EAPSR_G }, 0x402, 0x2, 0x402,  {ARM_FeatureDSP}  }, // 10
+  { "eapsr_nzcvq", { .raw_val = ARM_MCLASSSYSREG_EAPSR_NZCVQ }, 0x1802, 0x202, 0x802,  {0}  }, // 11
+  { "eapsr_nzcvqg", { .raw_val = ARM_MCLASSSYSREG_EAPSR_NZCVQG }, 0xC02, 0x302, 0xC02,  {ARM_FeatureDSP}  }, // 12
+  { "epsr", { .raw_val = ARM_MCLASSSYSREG_EPSR }, 0x806, 0x106, 0x806,  {0}  }, // 13
+  { "faultmask", { .raw_val = ARM_MCLASSSYSREG_FAULTMASK }, 0x813, 0x113, 0x813,  {ARM_HasV7Ops}  }, // 14
+  { "faultmask_ns", { .raw_val = ARM_MCLASSSYSREG_FAULTMASK_NS }, 0x893, 0x193, 0x893,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 15
+  { "iapsr", { .raw_val = ARM_MCLASSSYSREG_IAPSR }, 0x801, 0x101, 0x801,  {0}  }, // 16
+  { "iapsr_g", { .raw_val = ARM_MCLASSSYSREG_IAPSR_G }, 0x401, 0x1, 0x401,  {ARM_FeatureDSP}  }, // 17
+  { "iapsr_nzcvq", { .raw_val = ARM_MCLASSSYSREG_IAPSR_NZCVQ }, 0x1801, 0x201, 0x801,  {0}  }, // 18
+  { "iapsr_nzcvqg", { .raw_val = ARM_MCLASSSYSREG_IAPSR_NZCVQG }, 0xC01, 0x301, 0xC01,  {ARM_FeatureDSP}  }, // 19
+  { "iepsr", { .raw_val = ARM_MCLASSSYSREG_IEPSR }, 0x807, 0x107, 0x807,  {0}  }, // 20
+  { "ipsr", { .raw_val = ARM_MCLASSSYSREG_IPSR }, 0x805, 0x105, 0x805,  {0}  }, // 21
+  { "msp", { .raw_val = ARM_MCLASSSYSREG_MSP }, 0x808, 0x108, 0x808,  {0}  }, // 22
+  { "msplim", { .raw_val = ARM_MCLASSSYSREG_MSPLIM }, 0x80A, 0x10A, 0x80A,  {ARM_HasV8MBaselineOps}  }, // 23
+  { "msplim_ns", { .raw_val = ARM_MCLASSSYSREG_MSPLIM_NS }, 0x88A, 0x18A, 0x88A,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 24
+  { "msp_ns", { .raw_val = ARM_MCLASSSYSREG_MSP_NS }, 0x888, 0x188, 0x888,  {ARM_Feature8MSecExt}  }, // 25
+  { "pac_key_p_0", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_0 }, 0x820, 0x120, 0x820,  {ARM_FeaturePACBTI}  }, // 26
+  { "pac_key_p_0_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_0_NS }, 0x8A0, 0x1A0, 0x8A0,  {ARM_FeaturePACBTI}  }, // 27
+  { "pac_key_p_1", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_1 }, 0x821, 0x121, 0x821,  {ARM_FeaturePACBTI}  }, // 28
+  { "pac_key_p_1_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_1_NS }, 0x8A1, 0x1A1, 0x8A1,  {ARM_FeaturePACBTI}  }, // 29
+  { "pac_key_p_2", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_2 }, 0x822, 0x122, 0x822,  {ARM_FeaturePACBTI}  }, // 30
+  { "pac_key_p_2_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_2_NS }, 0x8A2, 0x1A2, 0x8A2,  {ARM_FeaturePACBTI}  }, // 31
+  { "pac_key_p_3", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_3 }, 0x823, 0x123, 0x823,  {ARM_FeaturePACBTI}  }, // 32
+  { "pac_key_p_3_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_3_NS }, 0x8A3, 0x1A3, 0x8A3,  {ARM_FeaturePACBTI}  }, // 33
+  { "pac_key_u_0", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_0 }, 0x824, 0x124, 0x824,  {ARM_FeaturePACBTI}  }, // 34
+  { "pac_key_u_0_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_0_NS }, 0x8A4, 0x1A4, 0x8A4,  {ARM_FeaturePACBTI}  }, // 35
+  { "pac_key_u_1", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_1 }, 0x825, 0x125, 0x825,  {ARM_FeaturePACBTI}  }, // 36
+  { "pac_key_u_1_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_1_NS }, 0x8A5, 0x1A5, 0x8A5,  {ARM_FeaturePACBTI}  }, // 37
+  { "pac_key_u_2", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_2 }, 0x826, 0x126, 0x826,  {ARM_FeaturePACBTI}  }, // 38
+  { "pac_key_u_2_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_2_NS }, 0x8A6, 0x1A6, 0x8A6,  {ARM_FeaturePACBTI}  }, // 39
+  { "pac_key_u_3", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_3 }, 0x827, 0x127, 0x827,  {ARM_FeaturePACBTI}  }, // 40
+  { "pac_key_u_3_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_3_NS }, 0x8A7, 0x1A7, 0x8A7,  {ARM_FeaturePACBTI}  }, // 41
+  { "primask", { .raw_val = ARM_MCLASSSYSREG_PRIMASK }, 0x810, 0x110, 0x810,  {0}  }, // 42
+  { "primask_ns", { .raw_val = ARM_MCLASSSYSREG_PRIMASK_NS }, 0x890, 0x190, 0x890,  {0}  }, // 43
+  { "psp", { .raw_val = ARM_MCLASSSYSREG_PSP }, 0x809, 0x109, 0x809,  {0}  }, // 44
+  { "psplim", { .raw_val = ARM_MCLASSSYSREG_PSPLIM }, 0x80B, 0x10B, 0x80B,  {ARM_HasV8MBaselineOps}  }, // 45
+  { "psplim_ns", { .raw_val = ARM_MCLASSSYSREG_PSPLIM_NS }, 0x88B, 0x18B, 0x88B,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 46
+  { "psp_ns", { .raw_val = ARM_MCLASSSYSREG_PSP_NS }, 0x889, 0x189, 0x889,  {ARM_Feature8MSecExt}  }, // 47
+  { "sp_ns", { .raw_val = ARM_MCLASSSYSREG_SP_NS }, 0x898, 0x198, 0x898,  {ARM_Feature8MSecExt}  }, // 48
+  { "xpsr", { .raw_val = ARM_MCLASSSYSREG_XPSR }, 0x803, 0x103, 0x803,  {0}  }, // 49
+  { "xpsr_g", { .raw_val = ARM_MCLASSSYSREG_XPSR_G }, 0x403, 0x3, 0x403,  {ARM_FeatureDSP}  }, // 50
+  { "xpsr_nzcvq", { .raw_val = ARM_MCLASSSYSREG_XPSR_NZCVQ }, 0x1803, 0x203, 0x803,  {0}  }, // 51
+  { "xpsr_nzcvqg", { .raw_val = ARM_MCLASSSYSREG_XPSR_NZCVQG }, 0xC03, 0x303, 0xC03,  {ARM_FeatureDSP}  }, // 52
  };

-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegByName(const char *Name)
-{
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByName(const char * Name) {
  static const struct IndexTypeStr Index[] = {
-		{ "APSR", 0 },		{ "APSR_G", 1 },
-		{ "APSR_NZCVQ", 2 },	{ "APSR_NZCVQG", 3 },
-		{ "BASEPRI", 4 },	{ "BASEPRI_MAX", 5 },
-		{ "BASEPRI_NS", 6 },	{ "CONTROL", 7 },
-		{ "CONTROL_NS", 8 },	{ "EAPSR", 9 },
-		{ "EAPSR_G", 10 },	{ "EAPSR_NZCVQ", 11 },
-		{ "EAPSR_NZCVQG", 12 }, { "EPSR", 13 },
-		{ "FAULTMASK", 14 },	{ "FAULTMASK_NS", 15 },
-		{ "IAPSR", 16 },	{ "IAPSR_G", 17 },
-		{ "IAPSR_NZCVQ", 18 },	{ "IAPSR_NZCVQG", 19 },
-		{ "IEPSR", 20 },	{ "IPSR", 21 },
-		{ "MSP", 22 },		{ "MSPLIM", 23 },
-		{ "MSPLIM_NS", 24 },	{ "MSP_NS", 25 },
-		{ "PAC_KEY_P_0", 26 },	{ "PAC_KEY_P_0_NS", 27 },
-		{ "PAC_KEY_P_1", 28 },	{ "PAC_KEY_P_1_NS", 29 },
-		{ "PAC_KEY_P_2", 30 },	{ "PAC_KEY_P_2_NS", 31 },
-		{ "PAC_KEY_P_3", 32 },	{ "PAC_KEY_P_3_NS", 33 },
-		{ "PAC_KEY_U_0", 34 },	{ "PAC_KEY_U_0_NS", 35 },
-		{ "PAC_KEY_U_1", 36 },	{ "PAC_KEY_U_1_NS", 37 },
-		{ "PAC_KEY_U_2", 38 },	{ "PAC_KEY_U_2_NS", 39 },
-		{ "PAC_KEY_U_3", 40 },	{ "PAC_KEY_U_3_NS", 41 },
-		{ "PRIMASK", 42 },	{ "PRIMASK_NS", 43 },
-		{ "PSP", 44 },		{ "PSPLIM", 45 },
-		{ "PSPLIM_NS", 46 },	{ "PSP_NS", 47 },
-		{ "SP_NS", 48 },	{ "XPSR", 49 },
-		{ "XPSR_G", 50 },	{ "XPSR_NZCVQ", 51 },
+    { "APSR", 0 },
+    { "APSR_G", 1 },
+    { "APSR_NZCVQ", 2 },
+    { "APSR_NZCVQG", 3 },
+    { "BASEPRI", 4 },
+    { "BASEPRI_MAX", 5 },
+    { "BASEPRI_NS", 6 },
+    { "CONTROL", 7 },
+    { "CONTROL_NS", 8 },
+    { "EAPSR", 9 },
+    { "EAPSR_G", 10 },
+    { "EAPSR_NZCVQ", 11 },
+    { "EAPSR_NZCVQG", 12 },
+    { "EPSR", 13 },
+    { "FAULTMASK", 14 },
+    { "FAULTMASK_NS", 15 },
+    { "IAPSR", 16 },
+    { "IAPSR_G", 17 },
+    { "IAPSR_NZCVQ", 18 },
+    { "IAPSR_NZCVQG", 19 },
+    { "IEPSR", 20 },
+    { "IPSR", 21 },
+    { "MSP", 22 },
+    { "MSPLIM", 23 },
+    { "MSPLIM_NS", 24 },
+    { "MSP_NS", 25 },
+    { "PAC_KEY_P_0", 26 },
+    { "PAC_KEY_P_0_NS", 27 },
+    { "PAC_KEY_P_1", 28 },
+    { "PAC_KEY_P_1_NS", 29 },
+    { "PAC_KEY_P_2", 30 },
+    { "PAC_KEY_P_2_NS", 31 },
+    { "PAC_KEY_P_3", 32 },
+    { "PAC_KEY_P_3_NS", 33 },
+    { "PAC_KEY_U_0", 34 },
+    { "PAC_KEY_U_0_NS", 35 },
+    { "PAC_KEY_U_1", 36 },
+    { "PAC_KEY_U_1_NS", 37 },
+    { "PAC_KEY_U_2", 38 },
+    { "PAC_KEY_U_2_NS", 39 },
+    { "PAC_KEY_U_3", 40 },
+    { "PAC_KEY_U_3_NS", 41 },
+    { "PRIMASK", 42 },
+    { "PRIMASK_NS", 43 },
+    { "PSP", 44 },
+    { "PSPLIM", 45 },
+    { "PSPLIM_NS", 46 },
+    { "PSP_NS", 47 },
+    { "SP_NS", 48 },
+    { "XPSR", 49 },
+    { "XPSR_G", 50 },
+    { "XPSR_NZCVQ", 51 },
    { "XPSR_NZCVQG", 52 },
  };

-	unsigned i =
-		binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
+   unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
   if (i == -1)
      return NULL;
   else
      return &MClassSysRegsList[Index[i].index];
 }

-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12)
-{
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12) {
  static const struct IndexType Index[] = {
-		{ 0x400, 1 },	{ 0x401, 17 }, { 0x402, 10 },  { 0x403, 50 },
-		{ 0x800, 0 },	{ 0x801, 16 }, { 0x802, 9 },   { 0x803, 49 },
-		{ 0x805, 21 },	{ 0x806, 13 }, { 0x807, 20 },  { 0x808, 22 },
-		{ 0x809, 44 },	{ 0x80A, 23 }, { 0x80B, 45 },  { 0x810, 42 },
-		{ 0x811, 4 },	{ 0x812, 5 },  { 0x813, 14 },  { 0x814, 7 },
-		{ 0x820, 26 },	{ 0x821, 28 }, { 0x822, 30 },  { 0x823, 32 },
-		{ 0x824, 34 },	{ 0x825, 36 }, { 0x826, 38 },  { 0x827, 40 },
-		{ 0x888, 25 },	{ 0x889, 47 }, { 0x88A, 24 },  { 0x88B, 46 },
-		{ 0x890, 43 },	{ 0x891, 6 },  { 0x893, 15 },  { 0x894, 8 },
-		{ 0x898, 48 },	{ 0x8A0, 27 }, { 0x8A1, 29 },  { 0x8A2, 31 },
-		{ 0x8A3, 33 },	{ 0x8A4, 35 }, { 0x8A5, 37 },  { 0x8A6, 39 },
-		{ 0x8A7, 41 },	{ 0xC00, 3 },  { 0xC01, 19 },  { 0xC02, 12 },
-		{ 0xC03, 52 },	{ 0x1800, 2 }, { 0x1801, 18 }, { 0x1802, 11 },
+    { 0x400, 1 },
+    { 0x401, 17 },
+    { 0x402, 10 },
+    { 0x403, 50 },
+    { 0x800, 0 },
+    { 0x801, 16 },
+    { 0x802, 9 },
+    { 0x803, 49 },
+    { 0x805, 21 },
+    { 0x806, 13 },
+    { 0x807, 20 },
+    { 0x808, 22 },
+    { 0x809, 44 },
+    { 0x80A, 23 },
+    { 0x80B, 45 },
+    { 0x810, 42 },
+    { 0x811, 4 },
+    { 0x812, 5 },
+    { 0x813, 14 },
+    { 0x814, 7 },
+    { 0x820, 26 },
+    { 0x821, 28 },
+    { 0x822, 30 },
+    { 0x823, 32 },
+    { 0x824, 34 },
+    { 0x825, 36 },
+    { 0x826, 38 },
+    { 0x827, 40 },
+    { 0x888, 25 },
+    { 0x889, 47 },
+    { 0x88A, 24 },
+    { 0x88B, 46 },
+    { 0x890, 43 },
+    { 0x891, 6 },
+    { 0x893, 15 },
+    { 0x894, 8 },
+    { 0x898, 48 },
+    { 0x8A0, 27 },
+    { 0x8A1, 29 },
+    { 0x8A2, 31 },
+    { 0x8A3, 33 },
+    { 0x8A4, 35 },
+    { 0x8A5, 37 },
+    { 0x8A6, 39 },
+    { 0x8A7, 41 },
+    { 0xC00, 3 },
+    { 0xC01, 19 },
+    { 0xC02, 12 },
+    { 0xC03, 52 },
+    { 0x1800, 2 },
+    { 0x1801, 18 },
+    { 0x1802, 11 },
    { 0x1803, 51 },
  };

-	unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index),
-						 M1Encoding12);
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), M1Encoding12);
   if (i == -1)
      return NULL;
   else
      return &MClassSysRegsList[Index[i].index];
 }

-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8)
-{
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8) {
  static const struct IndexType Index[] = {
-		{ 0x0, 1 },    { 0x1, 17 },   { 0x2, 10 },   { 0x3, 50 },
-		{ 0x100, 0 },  { 0x101, 16 }, { 0x102, 9 },  { 0x103, 49 },
-		{ 0x105, 21 }, { 0x106, 13 }, { 0x107, 20 }, { 0x108, 22 },
-		{ 0x109, 44 }, { 0x10A, 23 }, { 0x10B, 45 }, { 0x110, 42 },
-		{ 0x111, 4 },  { 0x112, 5 },  { 0x113, 14 }, { 0x114, 7 },
-		{ 0x120, 26 }, { 0x121, 28 }, { 0x122, 30 }, { 0x123, 32 },
-		{ 0x124, 34 }, { 0x125, 36 }, { 0x126, 38 }, { 0x127, 40 },
-		{ 0x188, 25 }, { 0x189, 47 }, { 0x18A, 24 }, { 0x18B, 46 },
-		{ 0x190, 43 }, { 0x191, 6 },  { 0x193, 15 }, { 0x194, 8 },
-		{ 0x198, 48 }, { 0x1A0, 27 }, { 0x1A1, 29 }, { 0x1A2, 31 },
-		{ 0x1A3, 33 }, { 0x1A4, 35 }, { 0x1A5, 37 }, { 0x1A6, 39 },
-		{ 0x1A7, 41 }, { 0x200, 2 },  { 0x201, 18 }, { 0x202, 11 },
-		{ 0x203, 51 }, { 0x300, 3 },  { 0x301, 19 }, { 0x302, 12 },
+    { 0x0, 1 },
+    { 0x1, 17 },
+    { 0x2, 10 },
+    { 0x3, 50 },
+    { 0x100, 0 },
+    { 0x101, 16 },
+    { 0x102, 9 },
+    { 0x103, 49 },
+    { 0x105, 21 },
+    { 0x106, 13 },
+    { 0x107, 20 },
+    { 0x108, 22 },
+    { 0x109, 44 },
+    { 0x10A, 23 },
+    { 0x10B, 45 },
+    { 0x110, 42 },
+    { 0x111, 4 },
+    { 0x112, 5 },
+    { 0x113, 14 },
+    { 0x114, 7 },
+    { 0x120, 26 },
+    { 0x121, 28 },
+    { 0x122, 30 },
+    { 0x123, 32 },
+    { 0x124, 34 },
+    { 0x125, 36 },
+    { 0x126, 38 },
+    { 0x127, 40 },
+    { 0x188, 25 },
+    { 0x189, 47 },
+    { 0x18A, 24 },
+    { 0x18B, 46 },
+    { 0x190, 43 },
+    { 0x191, 6 },
+    { 0x193, 15 },
+    { 0x194, 8 },
+    { 0x198, 48 },
+    { 0x1A0, 27 },
+    { 0x1A1, 29 },
+    { 0x1A2, 31 },
+    { 0x1A3, 33 },
+    { 0x1A4, 35 },
+    { 0x1A5, 37 },
+    { 0x1A6, 39 },
+    { 0x1A7, 41 },
+    { 0x200, 2 },
+    { 0x201, 18 },
+    { 0x202, 11 },
+    { 0x203, 51 },
+    { 0x300, 3 },
+    { 0x301, 19 },
+    { 0x302, 12 },
    { 0x303, 52 },
  };

-	unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index),
-						 M2M3Encoding8);
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), M2M3Encoding8);
   if (i == -1)
      return NULL;
   else
      return &MClassSysRegsList[Index[i].index];
 }

-const ARMSysReg_MClassSysReg *
-ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding)
-{
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding) {
  static const struct IndexType Index[] = {
-		{ 0x400, 1 },  { 0x401, 17 }, { 0x402, 10 }, { 0x403, 50 },
-		{ 0x800, 0 },  { 0x800, 2 },  { 0x801, 16 }, { 0x801, 18 },
-		{ 0x802, 9 },  { 0x802, 11 }, { 0x803, 49 }, { 0x803, 51 },
-		{ 0x805, 21 }, { 0x806, 13 }, { 0x807, 20 }, { 0x808, 22 },
-		{ 0x809, 44 }, { 0x80A, 23 }, { 0x80B, 45 }, { 0x810, 42 },
-		{ 0x811, 4 },  { 0x812, 5 },  { 0x813, 14 }, { 0x814, 7 },
-		{ 0x820, 26 }, { 0x821, 28 }, { 0x822, 30 }, { 0x823, 32 },
-		{ 0x824, 34 }, { 0x825, 36 }, { 0x826, 38 }, { 0x827, 40 },
-		{ 0x888, 25 }, { 0x889, 47 }, { 0x88A, 24 }, { 0x88B, 46 },
-		{ 0x890, 43 }, { 0x891, 6 },  { 0x893, 15 }, { 0x894, 8 },
-		{ 0x898, 48 }, { 0x8A0, 27 }, { 0x8A1, 29 }, { 0x8A2, 31 },
-		{ 0x8A3, 33 }, { 0x8A4, 35 }, { 0x8A5, 37 }, { 0x8A6, 39 },
-		{ 0x8A7, 41 }, { 0xC00, 3 },  { 0xC01, 19 }, { 0xC02, 12 },
+    { 0x400, 1 },
+    { 0x401, 17 },
+    { 0x402, 10 },
+    { 0x403, 50 },
+    { 0x800, 0 },
+    { 0x800, 2 },
+    { 0x801, 16 },
+    { 0x801, 18 },
+    { 0x802, 9 },
+    { 0x802, 11 },
+    { 0x803, 49 },
+    { 0x803, 51 },
+    { 0x805, 21 },
+    { 0x806, 13 },
+    { 0x807, 20 },
+    { 0x808, 22 },
+    { 0x809, 44 },
+    { 0x80A, 23 },
+    { 0x80B, 45 },
+    { 0x810, 42 },
+    { 0x811, 4 },
+    { 0x812, 5 },
+    { 0x813, 14 },
+    { 0x814, 7 },
+    { 0x820, 26 },
+    { 0x821, 28 },
+    { 0x822, 30 },
+    { 0x823, 32 },
+    { 0x824, 34 },
+    { 0x825, 36 },
+    { 0x826, 38 },
+    { 0x827, 40 },
+    { 0x888, 25 },
+    { 0x889, 47 },
+    { 0x88A, 24 },
+    { 0x88B, 46 },
+    { 0x890, 43 },
+    { 0x891, 6 },
+    { 0x893, 15 },
+    { 0x894, 8 },
+    { 0x898, 48 },
+    { 0x8A0, 27 },
+    { 0x8A1, 29 },
+    { 0x8A2, 31 },
+    { 0x8A3, 33 },
+    { 0x8A4, 35 },
+    { 0x8A5, 37 },
+    { 0x8A6, 39 },
+    { 0x8A7, 41 },
+    { 0xC00, 3 },
+    { 0xC01, 19 },
+    { 0xC02, 12 },
    { 0xC03, 52 },
  };

-	unsigned i =
-		binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
   if (i == -1)
      return NULL;
   else
@ -572,4 +472,6 @@ ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding)
 #endif

 #undef GET_BANKEDREG_DECL
+#undef GET_BANKEDREG_IMPL
 #undef GET_MCLASSSYSREG_DECL
+#undef GET_MCLASSSYSREG_IMPL
--- a/arch/ARM/ARMInstPrinter.c
+++ b/arch/ARM/ARMInstPrinter.c
--- a/arch/ARM/ARMInstPrinter.h
+++ b/arch/ARM/ARMInstPrinter.h
@ -3,8 +3,8 @@
 /*    Rot127 <unisono@quyllur.org> 2022-2023 */
 /* Automatically translated source file from LLVM. */

-/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */

 /* Only small edits allowed. */
 /* For multiple similar edits, please create a Patch for the translator. */
@ -27,177 +27,6 @@
 #ifndef CS_ARM_INSTPRINTER_H
 #define CS_ARM_INSTPRINTER_H

-#include <capstone/platform.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "../../MCInst.h"
-#include "../../MCInstPrinter.h"
-#include "../../MCRegisterInfo.h"
-#include "../../SStream.h"
-#include "../../utils.h"
-#define CONCAT(a, b) CONCAT_(a, b)
-#define CONCAT_(a, b) a##_##b
-
-bool applyTargetSpecificCLOption(const char *Opt);
-// Autogenerated by tblgen.
-void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
-void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O);
-void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O);
-void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O);
-void printAM2PostIndexOp(MCInst *MI, unsigned OpNum, SStream *O);
-void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O);
-void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printAddrMode3Operand(AlwaysPrintImm0) \
-	void CONCAT(printAddrMode3Operand, \
-		    AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
-DECLARE_printAddrMode3Operand(false) DECLARE_printAddrMode3Operand(true)
-
-	void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum,
-					 SStream *O);
-void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
-				bool AlwaysPrintImm0);
-void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O);
-void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O);
-void printLdStmModeOperand(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printAddrMode5Operand(AlwaysPrintImm0) \
-	void CONCAT(printAddrMode5Operand, \
-		    AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
-DECLARE_printAddrMode5Operand(false) DECLARE_printAddrMode5Operand(true)
-
-#define DECLARE_printAddrMode5FP16Operand(AlwaysPrintImm0) \
-	void CONCAT(printAddrMode5FP16Operand, \
-		    AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
-	DECLARE_printAddrMode5FP16Operand(false)
-
-		void printAddrMode6Operand(MCInst *MI, unsigned OpNum,
-					   SStream *O);
-void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O);
-void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O);
-void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
-void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
-void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
-void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printAdrLabelOperand(scale) \
-	void CONCAT(printAdrLabelOperand, scale)(MCInst * MI, unsigned OpNum, \
-						 SStream *O);
-DECLARE_printAdrLabelOperand(0) DECLARE_printAdrLabelOperand(2)
-
-#define DEFINE_printAdrLabelOperandAddr(scale) \
-	static inline void CONCAT(printAdrLabelOperandAddr, scale)( \
-		MCInst * MI, uint64_t Address, unsigned OpNum, SStream *O) \
-	{ \
-		CONCAT(printAdrLabelOperand, scale)(MI, OpNum, O); \
-	}
-	DEFINE_printAdrLabelOperandAddr(0) DEFINE_printAdrLabelOperandAddr(2)
-
-		void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum,
-					    SStream *O);
-void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O);
-void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O);
-void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O,
-				    unsigned Scale);
-void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O);
-void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O);
-void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O);
-void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printAddrModeImm12Operand(AlwaysPrintImm0) \
-	void CONCAT(printAddrModeImm12Operand, \
-		    AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
-DECLARE_printAddrModeImm12Operand(false) DECLARE_printAddrModeImm12Operand(true)
-
-#define DECLARE_printT2AddrModeImm8Operand(AlwaysPrintImm0) \
-	void CONCAT(printT2AddrModeImm8Operand, \
-		    AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
-	DECLARE_printT2AddrModeImm8Operand(true)
-		DECLARE_printT2AddrModeImm8Operand(false)
-
-#define DECLARE_printT2AddrModeImm8s4Operand(AlwaysPrintImm0) \
-	void CONCAT(printT2AddrModeImm8s4Operand, \
-		    AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
-			DECLARE_printT2AddrModeImm8s4Operand(false)
-				DECLARE_printT2AddrModeImm8s4Operand(true)
-
-					void printT2AddrModeImm0_1020s4Operand(
-						MCInst *MI, unsigned OpNum,
-						SStream *O);
-void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O);
-void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O);
-void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printMandatoryRestrictedPredicateOperand(MCInst *MI, unsigned OpNum,
-					      SStream *O);
-void printMandatoryInvertedPredicateOperand(MCInst *MI, unsigned OpNum,
-					    SStream *O);
-void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O);
-void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O);
-void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O);
-void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O);
-void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O);
-void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printVMOVModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printPCLabel(MCInst *MI, unsigned OpNum, SStream *O);
-void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printFBits16(MCInst *MI, unsigned OpNum, SStream *O);
-void printFBits32(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O);
-void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printMVEVectorList(NumRegs) \
-	void CONCAT(printMVEVectorList, NumRegs)(MCInst * MI, unsigned OpNum, \
-						 SStream *O);
-DECLARE_printMVEVectorList(2) DECLARE_printMVEVectorList(4)
-
-#define DECLARE_printComplexRotationOp(Angle, Remainder) \
-	void CONCAT(printComplexRotationOp, CONCAT(Angle, Remainder))( \
-		MCInst * MI, unsigned OpNum, SStream *O);
-	DECLARE_printComplexRotationOp(90, 0)
-		DECLARE_printComplexRotationOp(180, 90)
-
-	// MVE
-	void printVPTPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void printVPTMask(MCInst *MI, unsigned OpNum, SStream *O);
-#define DECLARE_printMveAddrModeRQOperand(shift) \
-	void CONCAT(printMveAddrModeRQOperand, \
-		    shift)(MCInst * MI, unsigned OpNum, SStream *O);
-DECLARE_printMveAddrModeRQOperand(0) DECLARE_printMveAddrModeRQOperand(3)
-	DECLARE_printMveAddrModeRQOperand(1)
-		DECLARE_printMveAddrModeRQOperand(2)
-
-			void printMveSaturateOp(MCInst *MI, unsigned OpNum,
-						SStream *O);
-
 unsigned translateShiftImm(unsigned imm);

 #endif // CS_ARM_INSTPRINTER_H
--- a/arch/ARM/ARMMapping.c
+++ b/arch/ARM/ARMMapping.c
@ -305,8 +305,8 @@ static void ARM_add_not_defined_ops(MCInst *MI)
 	switch (Opcode) {
 	default:
 		return;
-	case ARM_t2MOVsra_flag:
-	case ARM_t2MOVsrl_flag:
+	case ARM_t2MOVsra_glue:
+	case ARM_t2MOVsrl_glue:
 		ARM_insert_detail_op_imm_at(MI, 2, 1, CS_AC_READ);
 		break;
 	case ARM_VCMPEZD:
@ -767,12 +767,32 @@ void ARM_check_updates_flags(MCInst *MI)
 #endif // CAPSTONE_DIET
 }

+void ARM_check_mem_access_validity(MCInst *MI)
+{
+#ifndef CAPSTONE_DIET
+	if (!detail_is_set(MI))
+		return;
+	const arm_suppl_info *suppl = map_get_suppl_info(MI, arm_insns);
+	if (suppl->mem_acc == CS_AC_INVALID) {
+		return;
+	}
+	cs_detail *detail = get_detail(MI);
+	for (int i = 0; i < detail->arm.op_count; ++i) {
+		if (detail->arm.operands[i].type == ARM_OP_MEM && detail->arm.operands[i].access != suppl->mem_acc) {
+			detail->arm.operands[i].access = suppl->mem_acc;
+			return;
+		}
+	}
+#endif // CAPSTONE_DIET
+}
+
 void ARM_set_instr_map_data(MCInst *MI)
 {
 	map_cs_id(MI, arm_insns, ARR_SIZE(arm_insns));
 	map_implicit_reads(MI, arm_insns);
 	map_implicit_writes(MI, arm_insns);
 	ARM_check_updates_flags(MI);
+	ARM_check_mem_access_validity(MI);
 	map_groups(MI, arm_insns);
 }

--- a/bindings/python/capstone/arm.py
+++ b/bindings/python/capstone/arm.py
@ -24,6 +24,7 @@ class ArmSysopReg(ctypes.Union):
    _fields_ = (
        ('mclasssysreg', ctypes.c_uint),
        ('bankedreg', ctypes.c_uint),
+        ('raw_val', ctypes.c_int),
    )

 class ArmOpSysop(ctypes.Structure):
--- a/include/capstone/arm.h
+++ b/include/capstone/arm.h
@ -414,6 +414,7 @@ typedef enum {
 typedef union {
  arm_sysreg mclasssysreg;
  arm_bankedreg bankedreg;
+  int raw_val; ///< Raw value for assignment in generated files.
 } arm_sysop_reg;

 /// Operand type for instruction's operands
@ -893,6 +894,10 @@ typedef struct cs_arm_op {
 	int8_t neon_lane;
 } cs_arm_op;

+typedef struct {
+	cs_ac_type mem_acc; ///< CGI memory access according to mayLoad and mayStore
+} arm_suppl_info;
+
 #define NUM_ARM_OPS 36

 /// Instruction structure
@ -950,6 +955,8 @@ typedef enum arm_insn {
 	ARM_INS_LDRSH,
 	ARM_INS_MOVS,
 	ARM_INS_MOV,
+	ARM_INS_STRB,
+	ARM_INS_STRH,
 	ARM_INS_STR,
 	ARM_INS_ADC,
 	ARM_INS_ADD,
@ -1362,13 +1369,11 @@ typedef enum arm_insn {
 	ARM_INS_STMDB,
 	ARM_INS_STM,
 	ARM_INS_STMIB,
-	ARM_INS_STRB,
 	ARM_INS_STRD,
 	ARM_INS_STREX,
 	ARM_INS_STREXB,
 	ARM_INS_STREXD,
 	ARM_INS_STREXH,
-	ARM_INS_STRH,
 	ARM_INS_STRHT,
 	ARM_INS_SUB,
 	ARM_INS_SVC,
@ -1487,7 +1492,7 @@ typedef enum arm_insn {
 	ARM_INS_VRSQRTS,
 	ARM_INS_VRSRA,
 	ARM_INS_VRSUBHN,
-	ARM_INS_VSCCLRM,
+	ARM_INS_VSCCLRM_,
 	ARM_INS_VSDOT,
 	ARM_INS_VSELEQ,
 	ARM_INS_VSELGE,
@ -1518,6 +1523,7 @@ typedef enum arm_insn {
 	ARM_INS_VUZP,
 	ARM_INS_VZIP,
 	ARM_INS_ADDW,
+	ARM_INS_ADR_,
 	ARM_INS_AUT,
 	ARM_INS_AUTG,
 	ARM_INS_BFL,
@ -1642,63 +1648,73 @@ typedef enum arm_insn_group {
 	// generated content <ARMGenCSFeatureEnum.inc> begin
 	// clang-format off

-	ARM_FEATURE_IsARM = 128,
-	ARM_FEATURE_HasV5T,
-	ARM_FEATURE_HasV4T,
-	ARM_FEATURE_HasVFP2,
-	ARM_FEATURE_HasV5TE,
-	ARM_FEATURE_HasV6T2,
-	ARM_FEATURE_HasMVEInt,
-	ARM_FEATURE_HasNEON,
-	ARM_FEATURE_HasFPRegs64,
-	ARM_FEATURE_HasFPRegs,
-	ARM_FEATURE_IsThumb2,
-	ARM_FEATURE_HasV8_1MMainline,
-	ARM_FEATURE_HasLOB,
-	ARM_FEATURE_IsThumb,
-	ARM_FEATURE_HasV8MBaseline,
-	ARM_FEATURE_Has8MSecExt,
-	ARM_FEATURE_HasV8,
-	ARM_FEATURE_HasAES,
-	ARM_FEATURE_HasBF16,
-	ARM_FEATURE_HasCDE,
-	ARM_FEATURE_PreV8,
-	ARM_FEATURE_HasV6K,
-	ARM_FEATURE_HasCRC,
-	ARM_FEATURE_HasV7,
-	ARM_FEATURE_HasDB,
-	ARM_FEATURE_HasVirtualization,
-	ARM_FEATURE_HasVFP3,
-	ARM_FEATURE_HasDPVFP,
-	ARM_FEATURE_HasFullFP16,
-	ARM_FEATURE_HasV6,
-	ARM_FEATURE_HasAcquireRelease,
-	ARM_FEATURE_HasV7Clrex,
-	ARM_FEATURE_HasMVEFloat,
-	ARM_FEATURE_HasFPRegsV8_1M,
-	ARM_FEATURE_HasMP,
-	ARM_FEATURE_HasSB,
-	ARM_FEATURE_HasDivideInARM,
-	ARM_FEATURE_HasV8_1a,
-	ARM_FEATURE_HasSHA2,
-	ARM_FEATURE_HasTrustZone,
-	ARM_FEATURE_UseNaClTrap,
-	ARM_FEATURE_HasV8_4a,
-	ARM_FEATURE_HasV8_3a,
-	ARM_FEATURE_HasFPARMv8,
-	ARM_FEATURE_HasFP16,
-	ARM_FEATURE_HasVFP4,
-	ARM_FEATURE_HasFP16FML,
-	ARM_FEATURE_HasFPRegs16,
-	ARM_FEATURE_HasV8MMainline,
-	ARM_FEATURE_HasDotProd,
-	ARM_FEATURE_HasMatMulInt8,
-	ARM_FEATURE_IsMClass,
-	ARM_FEATURE_HasPACBTI,
-	ARM_FEATURE_IsNotMClass,
-	ARM_FEATURE_HasDSP,
-	ARM_FEATURE_HasDivideInThumb,
-	ARM_FEATURE_HasV6M,
+	ARM_FEATURE_HASV4T = 128,
+	ARM_FEATURE_HASV5T,
+	ARM_FEATURE_HASV5TE,
+	ARM_FEATURE_HASV6,
+	ARM_FEATURE_HASV6M,
+	ARM_FEATURE_HASV8MBASELINE,
+	ARM_FEATURE_HASV8MMAINLINE,
+	ARM_FEATURE_HASV8_1MMAINLINE,
+	ARM_FEATURE_HASMVEINT,
+	ARM_FEATURE_HASMVEFLOAT,
+	ARM_FEATURE_HASCDE,
+	ARM_FEATURE_HASFPREGS,
+	ARM_FEATURE_HASFPREGS16,
+	ARM_FEATURE_HASNOFPREGS16,
+	ARM_FEATURE_HASFPREGS64,
+	ARM_FEATURE_HASFPREGSV8_1M,
+	ARM_FEATURE_HASV6T2,
+	ARM_FEATURE_HASV6K,
+	ARM_FEATURE_HASV7,
+	ARM_FEATURE_HASV8,
+	ARM_FEATURE_PREV8,
+	ARM_FEATURE_HASV8_1A,
+	ARM_FEATURE_HASV8_2A,
+	ARM_FEATURE_HASV8_3A,
+	ARM_FEATURE_HASV8_4A,
+	ARM_FEATURE_HASV8_5A,
+	ARM_FEATURE_HASV8_6A,
+	ARM_FEATURE_HASV8_7A,
+	ARM_FEATURE_HASVFP2,
+	ARM_FEATURE_HASVFP3,
+	ARM_FEATURE_HASVFP4,
+	ARM_FEATURE_HASDPVFP,
+	ARM_FEATURE_HASFPARMV8,
+	ARM_FEATURE_HASNEON,
+	ARM_FEATURE_HASSHA2,
+	ARM_FEATURE_HASAES,
+	ARM_FEATURE_HASCRYPTO,
+	ARM_FEATURE_HASDOTPROD,
+	ARM_FEATURE_HASCRC,
+	ARM_FEATURE_HASRAS,
+	ARM_FEATURE_HASLOB,
+	ARM_FEATURE_HASPACBTI,
+	ARM_FEATURE_HASFP16,
+	ARM_FEATURE_HASFULLFP16,
+	ARM_FEATURE_HASFP16FML,
+	ARM_FEATURE_HASBF16,
+	ARM_FEATURE_HASMATMULINT8,
+	ARM_FEATURE_HASDIVIDEINTHUMB,
+	ARM_FEATURE_HASDIVIDEINARM,
+	ARM_FEATURE_HASDSP,
+	ARM_FEATURE_HASDB,
+	ARM_FEATURE_HASDFB,
+	ARM_FEATURE_HASV7CLREX,
+	ARM_FEATURE_HASACQUIRERELEASE,
+	ARM_FEATURE_HASMP,
+	ARM_FEATURE_HASVIRTUALIZATION,
+	ARM_FEATURE_HASTRUSTZONE,
+	ARM_FEATURE_HAS8MSECEXT,
+	ARM_FEATURE_ISTHUMB,
+	ARM_FEATURE_ISTHUMB2,
+	ARM_FEATURE_ISMCLASS,
+	ARM_FEATURE_ISNOTMCLASS,
+	ARM_FEATURE_ISARM,
+	ARM_FEATURE_USENACLTRAP,
+	ARM_FEATURE_USENEGATIVEIMMEDIATES,
+	ARM_FEATURE_HASSB,
+	ARM_FEATURE_HASCLRBHB,

 	// clang-format on
 	// generated content <ARMGenCSFeatureEnum.inc> end
--- a/suite/auto-sync/.gitignore
+++ b/suite/auto-sync/.gitignore
@ -10,3 +10,4 @@ src/autosync/lit_config/test_dir_*
 src/autosync/lit_config/.lit_test_times.txt
 src/autosync/Tests/MCUpdaterTests/test_output
 src/autosync/Tests/MCUpdaterTests/**/Output
+src/autosync/cpptranslator/Tests/Differ/output/*.c
--- a/suite/auto-sync/inc_patches/03_Vector_Data_Type.patch
+++ b/suite/auto-sync/inc_patches/03_Vector_Data_Type.patch
@ -1,350 +0,0 @@
-# Set the vector data type for vector instruction.
-# Unfortunately we cannot get this information from the td files.
-# See https://github.com/capstone-engine/capstone/issues/2152
-# for a possible solution.
-
-diff --git a/arch/ARM/ARMGenAsmWriter.inc b/arch/ARM/ARMGenAsmWriter.inc
-index 3a4e61abf..635bfefb0 100644
--- a/arch/ARM/ARMGenAsmWriter.inc
-+++ b/arch/ARM/ARMGenAsmWriter.inc
-@@ -9927,15 +9927,18 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 13:
- 		// FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VFMAD, V...
- 		SStream_concat0(O, ".f64\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F64);
- 		printOperand(MI, 0, O);
- 		break;
- 	case 14:
- 		// FCONSTH, MVE_VABDf16, MVE_VABSf16, MVE_VADD_qr_f16, MVE_VADDf16, MVE_V...
- 		SStream_concat0(O, ".f16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F16);
- 		break;
- 	case 15:
- 		// FCONSTS, MVE_VABDf32, MVE_VABSf32, MVE_VADD_qr_f32, MVE_VADDf32, MVE_V...
- 		SStream_concat0(O, ".f32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F32);
- 		break;
- 	case 16:
- 		// FMSTAT
-@@ -9976,38 +9979,47 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 21:
- 		// MVE_VABAVs16, MVE_VABDs16, MVE_VABSs16, MVE_VADDVs16acc, MVE_VADDVs16n...
- 		SStream_concat0(O, ".s16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_S16);
- 		break;
- 	case 22:
- 		// MVE_VABAVs32, MVE_VABDs32, MVE_VABSs32, MVE_VADDLVs32acc, MVE_VADDLVs3...
- 		SStream_concat0(O, ".s32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_S32);
- 		break;
- 	case 23:
- 		// MVE_VABAVs8, MVE_VABDs8, MVE_VABSs8, MVE_VADDVs8acc, MVE_VADDVs8no_acc...
- 		SStream_concat0(O, ".s8\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_S8);
- 		break;
- 	case 24:
- 		// MVE_VABAVu16, MVE_VABDu16, MVE_VADDVu16acc, MVE_VADDVu16no_acc, MVE_VC...
- 		SStream_concat0(O, ".u16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_U16);
- 		break;
- 	case 25:
- 		// MVE_VABAVu32, MVE_VABDu32, MVE_VADDLVu32acc, MVE_VADDLVu32no_acc, MVE_...
- 		SStream_concat0(O, ".u32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_U32);
- 		break;
- 	case 26:
- 		// MVE_VABAVu8, MVE_VABDu8, MVE_VADDVu8acc, MVE_VADDVu8no_acc, MVE_VCMPu8...
- 		SStream_concat0(O, ".u8\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_U8);
- 		break;
- 	case 27:
- 		// MVE_VADC, MVE_VADCI, MVE_VADD_qr_i32, MVE_VADDi32, MVE_VBICimmi32, MVE...
- 		SStream_concat0(O, ".i32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_I32);
- 		break;
- 	case 28:
- 		// MVE_VADD_qr_i16, MVE_VADDi16, MVE_VBICimmi16, MVE_VCADDi16, MVE_VCLZs1...
- 		SStream_concat0(O, ".i16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_I16);
- 		break;
- 	case 29:
- 		// MVE_VADD_qr_i8, MVE_VADDi8, MVE_VCADDi8, MVE_VCLZs8, MVE_VCMPi8, MVE_V...
- 		SStream_concat0(O, ".i8\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_I8);
- 		break;
- 	case 30:
- 		// MVE_VCTP64, MVE_VSTRD64_qi, MVE_VSTRD64_qi_pre, MVE_VSTRD64_rq, MVE_VS...
-@@ -10016,12 +10028,14 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 31:
- 		// MVE_VCVTf16f32bh, MVE_VCVTf16f32th, VCVTBSH, VCVTTSH, VCVTf2h
- 		SStream_concat0(O, ".f16.f32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F16F32);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		break;
- 	case 32:
- 		// MVE_VCVTf16s16_fix, MVE_VCVTf16s16n, VCVTs2hd, VCVTs2hq, VCVTxs2hd, VC...
- 		SStream_concat0(O, ".f16.s16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F16S16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10029,6 +10043,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 33:
- 		// MVE_VCVTf16u16_fix, MVE_VCVTf16u16n, VCVTu2hd, VCVTu2hq, VCVTxu2hd, VC...
- 		SStream_concat0(O, ".f16.u16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F16U16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10036,6 +10051,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 34:
- 		// MVE_VCVTf32f16bh, MVE_VCVTf32f16th, VCVTBHS, VCVTTHS, VCVTh2f
- 		SStream_concat0(O, ".f32.f16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F32F16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10044,6 +10060,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 35:
- 		// MVE_VCVTf32s32_fix, MVE_VCVTf32s32n, VCVTs2fd, VCVTs2fq, VCVTxs2fd, VC...
- 		SStream_concat0(O, ".f32.s32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F32S32);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10051,6 +10068,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 36:
- 		// MVE_VCVTf32u32_fix, MVE_VCVTf32u32n, VCVTu2fd, VCVTu2fq, VCVTxu2fd, VC...
- 		SStream_concat0(O, ".f32.u32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F32U32);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10058,6 +10076,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 37:
- 		// MVE_VCVTs16f16_fix, MVE_VCVTs16f16a, MVE_VCVTs16f16m, MVE_VCVTs16f16n,...
- 		SStream_concat0(O, ".s16.f16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_S16F16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10065,6 +10084,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 38:
- 		// MVE_VCVTs32f32_fix, MVE_VCVTs32f32a, MVE_VCVTs32f32m, MVE_VCVTs32f32n,...
- 		SStream_concat0(O, ".s32.f32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_S32F32);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10072,6 +10092,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 39:
- 		// MVE_VCVTu16f16_fix, MVE_VCVTu16f16a, MVE_VCVTu16f16m, MVE_VCVTu16f16n,...
- 		SStream_concat0(O, ".u16.f16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_U16F16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10079,6 +10100,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 40:
- 		// MVE_VCVTu32f32_fix, MVE_VCVTu32f32a, MVE_VCVTu32f32m, MVE_VCVTu32f32n,...
- 		SStream_concat0(O, ".u32.f32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_U32F32);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10097,16 +10119,19 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 43:
- 		// MVE_VLDRDU64_qi, MVE_VLDRDU64_qi_pre, MVE_VLDRDU64_rq, MVE_VLDRDU64_rq...
- 		SStream_concat0(O, ".u64\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_U64);
- 		break;
- 	case 44:
- 		// MVE_VMOVimmi64, VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i...
- 		SStream_concat0(O, ".i64\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_I64);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		break;
- 	case 45:
- 		// MVE_VMULLBp16, MVE_VMULLTp16
- 		SStream_concat0(O, ".p16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_P16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10117,6 +10142,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 46:
- 		// MVE_VMULLBp8, MVE_VMULLTp8, VMULLp8, VMULpd, VMULpq
- 		SStream_concat0(O, ".p8\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_P8);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10137,6 +10163,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 49:
- 		// VCVTBDH, VCVTTDH
- 		SStream_concat0(O, ".f16.f64\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F16F64);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 2, O);
-@@ -10145,6 +10172,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 50:
- 		// VCVTBHD, VCVTTHD
- 		SStream_concat0(O, ".f64.f16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F64F16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10153,6 +10181,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 51:
- 		// VCVTDS
- 		SStream_concat0(O, ".f64.f32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F64F32);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10161,6 +10190,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 52:
- 		// VCVTSD
- 		SStream_concat0(O, ".f32.f64\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F32F64);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10169,6 +10199,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 53:
- 		// VJCVT, VTOSIRD, VTOSIZD, VTOSLD
- 		SStream_concat0(O, ".s32.f64\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_S32F64);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10236,12 +10267,14 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 67:
- 		// VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
- 		SStream_concat0(O, ".s64\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_S64);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		break;
- 	case 68:
- 		// VSHTOD
- 		SStream_concat0(O, ".f64.s16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F64S16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10252,6 +10285,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 69:
- 		// VSHTOS
- 		SStream_concat0(O, ".f32.s16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F32S16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10262,6 +10296,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 70:
- 		// VSITOD, VSLTOD
- 		SStream_concat0(O, ".f64.s32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F64S32);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10269,6 +10304,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 71:
- 		// VSITOH, VSLTOH
- 		SStream_concat0(O, ".f16.s32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F16S32);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10276,6 +10312,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 72:
- 		// VTOSHD
- 		SStream_concat0(O, ".s16.f64\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_S16F64);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10286,6 +10323,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 73:
- 		// VTOSHS
- 		SStream_concat0(O, ".s16.f32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_S16F32);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10296,6 +10334,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 74:
- 		// VTOSIRH, VTOSIZH, VTOSLH
- 		SStream_concat0(O, ".s32.f16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_S32F16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10303,6 +10342,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 75:
- 		// VTOUHD
- 		SStream_concat0(O, ".u16.f64\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_U16F64);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10313,6 +10353,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 76:
- 		// VTOUHS
- 		SStream_concat0(O, ".u16.f32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_U16F32);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10323,6 +10364,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 77:
- 		// VTOUIRD, VTOUIZD, VTOULD
- 		SStream_concat0(O, ".u32.f64\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_U32F64);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10330,6 +10372,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 78:
- 		// VTOUIRH, VTOUIZH, VTOULH
- 		SStream_concat0(O, ".u32.f16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_U32F16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10337,6 +10380,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 79:
- 		// VUHTOD
- 		SStream_concat0(O, ".f64.u16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F64U16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10347,6 +10391,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 80:
- 		// VUHTOS
- 		SStream_concat0(O, ".f32.u16\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F32U16);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10357,6 +10402,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 81:
- 		// VUITOD, VULTOD
- 		SStream_concat0(O, ".f64.u32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F64U32);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
-@@ -10364,6 +10410,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 82:
- 		// VUITOH, VULTOH
- 		SStream_concat0(O, ".f16.u32\t");
-+		ARM_add_vector_data(MI, ARM_VECTORDATA_F16U32);
- 		printOperand(MI, 0, O);
- 		SStream_concat0(O, ", ");
- 		printOperand(MI, 1, O);
--- a/suite/auto-sync/inc_patches/04_Vector_size.patch
+++ b/suite/auto-sync/inc_patches/04_Vector_size.patch
@ -1,48 +0,0 @@
-diff --git a/arch/ARM/ARMGenAsmWriter.inc b/arch/ARM/ARMGenAsmWriter.inc
-index 635bfefb0..35f2fe3c8 100644
--- a/arch/ARM/ARMGenAsmWriter.inc
-+++ b/arch/ARM/ARMGenAsmWriter.inc
-@@ -9870,14 +9870,17 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 1:
- 		// VLD1LNdAsm_16, VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_register_Asm_16, VLD2...
- 		SStream_concat0(O, ".16\t");
-+		ARM_add_vector_size(MI, 16);
- 		break;
- 	case 2:
- 		// VLD1LNdAsm_32, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_register_Asm_32, VLD2...
- 		SStream_concat0(O, ".32\t");
-+		ARM_add_vector_size(MI, 32);
- 		break;
- 	case 3:
- 		// VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_8, VLD1LNdWB_register_Asm_8, VLD2LNd...
- 		SStream_concat0(O, ".8\t");
-+		ARM_add_vector_size(MI, 8);
- 		break;
- 	case 4:
- 		// t2LDR_POST_imm, t2LDR_PRE_imm, t2STR_POST_imm, t2STR_PRE_imm
-@@ -10024,6 +10027,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 30:
- 		// MVE_VCTP64, MVE_VSTRD64_qi, MVE_VSTRD64_qi_pre, MVE_VSTRD64_rq, MVE_VS...
- 		SStream_concat0(O, ".64\t");
-+		ARM_add_vector_size(MI, 64);
- 		break;
- 	case 31:
- 		// MVE_VCVTf16f32bh, MVE_VCVTf16f32th, VCVTBSH, VCVTTSH, VCVTf2h
-@@ -10207,14 +10211,17 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
- 	case 54:
- 		// VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq...
- 		SStream_concat0(O, ".16\t{");
-+		ARM_add_vector_size(MI, 16);
- 		break;
- 	case 55:
- 		// VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq...
- 		SStream_concat0(O, ".32\t{");
-+		ARM_add_vector_size(MI, 32);
- 		break;
- 	case 56:
- 		// VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U...
- 		SStream_concat0(O, ".8\t{");
-+		ARM_add_vector_size(MI, 8);
- 		break;
- 	case 57:
- 		// VLDR_FPCXTNS_off, VLDR_FPCXTNS_post, VLDR_FPCXTNS_pre, VMSR_FPCXTNS, V...
--- a/suite/auto-sync/inc_patches/ARM/01_LDM_reg_lists_write_attribute.patch
+++ b/suite/auto-sync/inc_patches/ARM/01_LDM_reg_lists_write_attribute.patch
@ -0,0 +1,378 @@
+# The reglist operands are immediates. These immediates are technically read.
+# But for Capstone we want every register in the least to be written (for load instructions).
+# Hence, we patch it here.
+diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc
+index cc10dad8..8a1ede35 100644
+--- a/arch/ARM/ARMGenCSMappingInsnOp.inc
+++ b/arch/ARM/ARMGenCSMappingInsnOp.inc
+@@ -4925,32 +4925,32 @@
+ { /* ARM_FLDMXDB_UPD (851) - ARM_INS_FLDMDBX - fldmdbx${p}	$Rn!, $regs */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_FLDMXIA (852) - ARM_INS_FLDMIAX - fldmiax${p}	$Rn, $regs */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_FLDMXIA_UPD (853) - ARM_INS_FLDMIAX - fldmiax${p}	$Rn!, $regs */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_FMSTAT (854) - ARM_INS_VMRS - vmrs${p}	APSR_nzcv, fpscr */
+ {
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+@@ -5210,80 +5210,80 @@
+ }},
+ { /* ARM_LDMDA (885) - ARM_INS_LDMDA - ldmda${p}	$Rn, $regs */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_LDMDA_UPD (886) - ARM_INS_LDMDA - ldmda${p}	$Rn!, $regs */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_LDMDB (887) - ARM_INS_LDMDB - ldmdb${p}	$Rn, $regs */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_LDMDB_UPD (888) - ARM_INS_LDMDB - ldmdb${p}	$Rn!, $regs */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_LDMIA (889) - ARM_INS_LDM - ldm${p}	$Rn, $regs */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_LDMIA_UPD (890) - ARM_INS_LDM - ldm${p}	$Rn!, $regs */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_LDMIB (891) - ARM_INS_LDMIB - ldmib${p}	$Rn, $regs */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_LDMIB_UPD (892) - ARM_INS_LDMIB - ldmib${p}	$Rn!, $regs */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_LDRBT_POST_IMM (893) - ARM_INS_LDRBT - ldrbt${p}	$Rt, $addr, $offset */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+@@ -23132,64 +23132,64 @@
+ { /* ARM_VLDMDDB_UPD (2838) - ARM_INS_VLDMDB - vldmdb${p}	$Rn!, $regs */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_VLDMDIA (2839) - ARM_INS_VLDMIA - vldmia${p}	$Rn, $regs */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_VLDMDIA_UPD (2840) - ARM_INS_VLDMIA - vldmia${p}	$Rn!, $regs */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ {{{ /* ARM_VLDMQIA (2841) - ARM_INS_INVALID -  */
+  0
+ }}},
+ { /* ARM_VLDMSDB_UPD (2842) - ARM_INS_VLDMDB - vldmdb${p}	$Rn!, $regs */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_VLDMSIA (2843) - ARM_INS_VLDMIA - vldmia${p}	$Rn, $regs */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_VLDMSIA_UPD (2844) - ARM_INS_VLDMIA - vldmia${p}	$Rn!, $regs */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_VLDRD (2845) - ARM_INS_VLDR - vldr${p}	$Dd, $addr */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+@@ -28522,21 +28522,21 @@
+   { 0 }
+ }},
+ { /* ARM_VSCCLRMD (3449) - ARM_INS_VSCCLRM_ - vscclrm{$p}	$regs */
+ {
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_VSCCLRMS (3450) - ARM_INS_VSCCLRM_ - vscclrm{$p}	$regs */
+ {
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_VSDOTD (3451) - ARM_INS_VSDOT - vsdot.s8	$Vd, $Vn, $Vm */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+@@ -32683,80 +32683,80 @@
+ }},
+ { /* ARM_sysLDMDA (3964) - ARM_INS_LDMDA - ldmda${p}	$Rn, $regs ^ */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_sysLDMDA_UPD (3965) - ARM_INS_LDMDA - ldmda${p}	$Rn!, $regs ^ */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_sysLDMDB (3966) - ARM_INS_LDMDB - ldmdb${p}	$Rn, $regs ^ */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_sysLDMDB_UPD (3967) - ARM_INS_LDMDB - ldmdb${p}	$Rn!, $regs ^ */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_sysLDMIA (3968) - ARM_INS_LDM - ldm${p}	$Rn, $regs ^ */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_sysLDMIA_UPD (3969) - ARM_INS_LDM - ldm${p}	$Rn!, $regs ^ */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_sysLDMIB (3970) - ARM_INS_LDMIB - ldmib${p}	$Rn, $regs ^ */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_sysLDMIB_UPD (3971) - ARM_INS_LDMIB - ldmib${p}	$Rn!, $regs ^ */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_sysSTMDA (3972) - ARM_INS_STMDA - stmda${p}	$Rn, $regs ^ */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+@@ -33633,42 +33633,42 @@
+ }},
+ { /* ARM_t2LDMDB (4075) - ARM_INS_LDMDB - ldmdb${p}	$Rn, $regs */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_t2LDMDB_UPD (4076) - ARM_INS_LDMDB - ldmdb${p}	$Rn!, $regs */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_t2LDMIA (4077) - ARM_INS_LDM - ldm${p}.w	$Rn, $regs */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_t2LDMIA_UPD (4078) - ARM_INS_LDM - ldm${p}.w	$Rn!, $regs */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_t2LDRBT (4079) - ARM_INS_LDRBT - ldrbt${p}	$Rt, $addr */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+@@ -36683,13 +36683,13 @@
+ }}},
+ { /* ARM_tLDMIA (4413) - ARM_INS_LDM - ldm${p}	$Rn, $regs */
+ {
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_tLDRBi (4414) - ARM_INS_LDRB - ldrb${p}	$Rt, $addr */
+ {
+   { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
--- a/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch
+++ b/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch
@ -1,250 +0,0 @@
-# Sets the correct access attributes for register lists of LDM instructions.
-# See issue: https://github.com/llvm/llvm-project/issues/62455
-
-diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc
-index fe71aa54f..a3b04d915 100644
--- a/arch/ARM/ARMGenCSMappingInsnOp.inc
-+++ b/arch/ARM/ARMGenCSMappingInsnOp.inc
-@@ -9073,7 +9073,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -9092,7 +9092,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -9108,7 +9108,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -9127,7 +9127,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -9143,7 +9143,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -9162,7 +9162,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -9178,7 +9178,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -9197,7 +9197,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -55518,7 +55518,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -55534,7 +55534,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -55553,7 +55553,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -55574,7 +55574,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -55590,7 +55590,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -55609,7 +55609,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -80998,7 +80998,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -81017,7 +81017,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -81033,7 +81033,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -81052,7 +81052,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -81068,7 +81068,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -81087,7 +81087,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -81103,7 +81103,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -81122,7 +81122,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -82831,7 +82831,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -82850,7 +82850,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -82866,7 +82866,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -82885,7 +82885,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -88945,7 +88945,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
--- a/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch
+++ b/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch
@ -1,25 +0,0 @@
-# Sets the correct access attributes for register lists of VSCCLRM instructions.
-# See issue: https://github.com/llvm/llvm-project/issues/62455
-
-diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc
-index a3b04d915..12c9a1f9c 100644
--- a/arch/ARM/ARMGenCSMappingInsnOp.inc
-+++ b/arch/ARM/ARMGenCSMappingInsnOp.inc
-@@ -70562,7 +70562,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
-@@ -70575,7 +70575,7 @@
- 	      CS_AC_READ,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- 	    { CS_OP_IMM,
-	      CS_AC_READ,
-+	      CS_AC_WRITE,
- 	      { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
- 	    { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
- 	    { 0 } }
--- a/suite/auto-sync/inc_patches/ARM/02_vector_data_types.patch
+++ b/suite/auto-sync/inc_patches/ARM/02_vector_data_types.patch
@ -0,0 +1,345 @@
+diff --git a/arch/ARM/ARMGenAsmWriter.inc b/arch/ARM/ARMGenAsmWriter.inc
+index b8b7182d..59d4e510 100644
+--- a/arch/ARM/ARMGenAsmWriter.inc
+++ b/arch/ARM/ARMGenAsmWriter.inc
+@@ -10011,18 +10011,15 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 14:
+     // FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VFMAD, V...
+     SStream_concat0(O, ".f64\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F64);
+     printOperand(MI, 0, O);
+     break;
+   case 15:
+     // FCONSTH, MVE_VABDf16, MVE_VABSf16, MVE_VADD_qr_f16, MVE_VADDf16, MVE_V...
+     SStream_concat0(O, ".f16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F16);
+     break;
+   case 16:
+     // FCONSTS, MVE_VABDf32, MVE_VABSf32, MVE_VADD_qr_f32, MVE_VADDf32, MVE_V...
+     SStream_concat0(O, ".f32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F32);
+     break;
+   case 17:
+     // FMSTAT
+@@ -10047,47 +10044,38 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 21:
+     // MVE_VABAVs16, MVE_VABDs16, MVE_VABSs16, MVE_VADDVs16acc, MVE_VADDVs16n...
+     SStream_concat0(O, ".s16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_S16);
+     break;
+   case 22:
+     // MVE_VABAVs32, MVE_VABDs32, MVE_VABSs32, MVE_VADDLVs32acc, MVE_VADDLVs3...
+     SStream_concat0(O, ".s32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_S32);
+     break;
+   case 23:
+     // MVE_VABAVs8, MVE_VABDs8, MVE_VABSs8, MVE_VADDVs8acc, MVE_VADDVs8no_acc...
+     SStream_concat0(O, ".s8\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_S8);
+     break;
+   case 24:
+     // MVE_VABAVu16, MVE_VABDu16, MVE_VADDVu16acc, MVE_VADDVu16no_acc, MVE_VC...
+     SStream_concat0(O, ".u16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_U16);
+     break;
+   case 25:
+     // MVE_VABAVu32, MVE_VABDu32, MVE_VADDLVu32acc, MVE_VADDLVu32no_acc, MVE_...
+     SStream_concat0(O, ".u32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_U32);
+     break;
+   case 26:
+     // MVE_VABAVu8, MVE_VABDu8, MVE_VADDVu8acc, MVE_VADDVu8no_acc, MVE_VCMPu8...
+     SStream_concat0(O, ".u8\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_U8);
+     break;
+   case 27:
+     // MVE_VADC, MVE_VADCI, MVE_VADD_qr_i32, MVE_VADDi32, MVE_VBICimmi32, MVE...
+     SStream_concat0(O, ".i32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_I32);
+     break;
+   case 28:
+     // MVE_VADD_qr_i16, MVE_VADDi16, MVE_VBICimmi16, MVE_VCADDi16, MVE_VCLZs1...
+     SStream_concat0(O, ".i16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_I16);
+     break;
+   case 29:
+     // MVE_VADD_qr_i8, MVE_VADDi8, MVE_VCADDi8, MVE_VCLZs8, MVE_VCMPi8, MVE_V...
+     SStream_concat0(O, ".i8\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_I8);
+     break;
+   case 30:
+     // MVE_VCTP64, MVE_VSTRD64_qi, MVE_VSTRD64_qi_pre, MVE_VSTRD64_rq, MVE_VS...
+@@ -10097,14 +10085,12 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 31:
+     // MVE_VCVTf16f32bh, MVE_VCVTf16f32th, VCVTBSH, VCVTTSH, VCVTf2h
+     SStream_concat0(O, ".f16.f32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F16F32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     break;
+   case 32:
+     // MVE_VCVTf16s16_fix, MVE_VCVTf16s16n, VCVTs2hd, VCVTs2hq, VCVTxs2hd, VC...
+     SStream_concat0(O, ".f16.s16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F16S16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10112,7 +10098,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 33:
+     // MVE_VCVTf16u16_fix, MVE_VCVTf16u16n, VCVTu2hd, VCVTu2hq, VCVTxu2hd, VC...
+     SStream_concat0(O, ".f16.u16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F16U16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10120,7 +10105,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 34:
+     // MVE_VCVTf32f16bh, MVE_VCVTf32f16th, VCVTBHS, VCVTTHS, VCVTh2f
+     SStream_concat0(O, ".f32.f16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F32F16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10129,7 +10113,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 35:
+     // MVE_VCVTf32s32_fix, MVE_VCVTf32s32n, VCVTs2fd, VCVTs2fq, VCVTxs2fd, VC...
+     SStream_concat0(O, ".f32.s32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F32S32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10137,7 +10120,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 36:
+     // MVE_VCVTf32u32_fix, MVE_VCVTf32u32n, VCVTu2fd, VCVTu2fq, VCVTxu2fd, VC...
+     SStream_concat0(O, ".f32.u32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F32U32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10145,7 +10127,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 37:
+     // MVE_VCVTs16f16_fix, MVE_VCVTs16f16a, MVE_VCVTs16f16m, MVE_VCVTs16f16n,...
+     SStream_concat0(O, ".s16.f16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_S16F16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10153,7 +10134,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 38:
+     // MVE_VCVTs32f32_fix, MVE_VCVTs32f32a, MVE_VCVTs32f32m, MVE_VCVTs32f32n,...
+     SStream_concat0(O, ".s32.f32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_S32F32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10161,7 +10141,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 39:
+     // MVE_VCVTu16f16_fix, MVE_VCVTu16f16a, MVE_VCVTu16f16m, MVE_VCVTu16f16n,...
+     SStream_concat0(O, ".u16.f16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_U16F16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10169,7 +10148,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 40:
+     // MVE_VCVTu32f32_fix, MVE_VCVTu32f32a, MVE_VCVTu32f32m, MVE_VCVTu32f32n,...
+     SStream_concat0(O, ".u32.f32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_U32F32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10188,19 +10166,16 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 43:
+     // MVE_VLDRDU64_qi, MVE_VLDRDU64_qi_pre, MVE_VLDRDU64_rq, MVE_VLDRDU64_rq...
+     SStream_concat0(O, ".u64\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_U64);
+     break;
+   case 44:
+     // MVE_VMOVimmi64, VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i...
+     SStream_concat0(O, ".i64\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_I64);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     break;
+   case 45:
+     // MVE_VMULLBp16, MVE_VMULLTp16
+     SStream_concat0(O, ".p16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_P16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10211,7 +10186,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 46:
+     // MVE_VMULLBp8, MVE_VMULLTp8, VMULLp8, VMULpd, VMULpq
+     SStream_concat0(O, ".p8\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_P8);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10232,7 +10206,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 49:
+     // VCVTBDH, VCVTTDH
+     SStream_concat0(O, ".f16.f64\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F16F64);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 2, O);
+@@ -10241,7 +10214,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 50:
+     // VCVTBHD, VCVTTHD
+     SStream_concat0(O, ".f64.f16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F64F16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10250,7 +10222,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 51:
+     // VCVTDS
+     SStream_concat0(O, ".f64.f32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F64F32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10259,7 +10230,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 52:
+     // VCVTSD
+     SStream_concat0(O, ".f32.f64\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F32F64);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10268,7 +10238,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 53:
+     // VJCVT, VTOSIRD, VTOSIZD, VTOSLD
+     SStream_concat0(O, ".s32.f64\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_S32F64);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10339,14 +10308,12 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 67:
+     // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
+     SStream_concat0(O, ".s64\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_S64);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     break;
+   case 68:
+     // VSHTOD
+     SStream_concat0(O, ".f64.s16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F64S16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10357,7 +10324,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 69:
+     // VSHTOS
+     SStream_concat0(O, ".f32.s16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F32S16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10368,7 +10334,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 70:
+     // VSITOD, VSLTOD
+     SStream_concat0(O, ".f64.s32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F64S32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10376,7 +10341,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 71:
+     // VSITOH, VSLTOH
+     SStream_concat0(O, ".f16.s32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F16S32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10384,7 +10348,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 72:
+     // VTOSHD
+     SStream_concat0(O, ".s16.f64\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_S16F64);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10395,7 +10358,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 73:
+     // VTOSHS
+     SStream_concat0(O, ".s16.f32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_S16F32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10406,7 +10368,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 74:
+     // VTOSIRH, VTOSIZH, VTOSLH
+     SStream_concat0(O, ".s32.f16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_S32F16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10414,7 +10375,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 75:
+     // VTOUHD
+     SStream_concat0(O, ".u16.f64\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_U16F64);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10425,7 +10385,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 76:
+     // VTOUHS
+     SStream_concat0(O, ".u16.f32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_U16F32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10436,7 +10395,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 77:
+     // VTOUIRD, VTOUIZD, VTOULD
+     SStream_concat0(O, ".u32.f64\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_U32F64);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10444,7 +10402,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 78:
+     // VTOUIRH, VTOUIZH, VTOULH
+     SStream_concat0(O, ".u32.f16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_U32F16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10452,7 +10409,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 79:
+     // VUHTOD
+     SStream_concat0(O, ".f64.u16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F64U16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10463,7 +10419,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 80:
+     // VUHTOS
+     SStream_concat0(O, ".f32.u16\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F32U16);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10474,7 +10429,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 81:
+     // VUITOD, VULTOD
+     SStream_concat0(O, ".f64.u32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F64U32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+@@ -10482,7 +10436,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   case 82:
+     // VUITOH, VULTOH
+     SStream_concat0(O, ".f16.u32\t");
+    ARM_add_vector_data(MI, ARM_VECTORDATA_F16U32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
--- a/suite/auto-sync/inc_patches/ARM/03_vector_size.patch
+++ b/suite/auto-sync/inc_patches/ARM/03_vector_size.patch
@ -0,0 +1,90 @@
+diff --git a/arch/ARM/ARMGenAsmWriter.inc b/arch/ARM/ARMGenAsmWriter.inc
+index 33fa7815..b8b7182d 100644
+--- a/arch/ARM/ARMGenAsmWriter.inc
+++ b/arch/ARM/ARMGenAsmWriter.inc
+@@ -9939,28 +9939,31 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+   // Fragment 1 encoded into 7 bits for 89 unique commands.
+   switch ((Bits >> 19) & 127) {
+   default: CS_ASSERT_RET(0 && "Invalid command number.");
+   case 0:
+     // ASRi, ASRr, ITasm, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHT...
+     SStream_concat1(O, ' ');
+     break;
+   case 1:
+     // VLD1LNdAsm_16, VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_register_Asm_16, VLD2...
+     SStream_concat0(O, ".16\t");
+    ARM_add_vector_size(MI, 16);
+     break;
+   case 2:
+     // VLD1LNdAsm_32, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_register_Asm_32, VLD2...
+     SStream_concat0(O, ".32\t");
+    ARM_add_vector_size(MI, 32);
+     break;
+   case 3:
+     // VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_8, VLD1LNdWB_register_Asm_8, VLD2LNd...
+     SStream_concat0(O, ".8\t");
+    ARM_add_vector_size(MI, 8);
+     break;
+   case 4:
+     // t2LDRB_OFFSET_imm, t2LDRB_POST_imm, t2LDRB_PRE_imm, t2LDRH_OFFSET_imm,...
+     SStream_concat0(O, ".w ");
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     break;
+   case 5:
+     // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,...
+     SStream_concat0(O, "\t");
+@@ -10082,20 +10085,21 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+     ARM_add_vector_data(MI, ARM_VECTORDATA_I16);
+     break;
+   case 29:
+     // MVE_VADD_qr_i8, MVE_VADDi8, MVE_VCADDi8, MVE_VCLZs8, MVE_VCMPi8, MVE_V...
+     SStream_concat0(O, ".i8\t");
+     ARM_add_vector_data(MI, ARM_VECTORDATA_I8);
+     break;
+   case 30:
+     // MVE_VCTP64, MVE_VSTRD64_qi, MVE_VSTRD64_qi_pre, MVE_VSTRD64_rq, MVE_VS...
+     SStream_concat0(O, ".64\t");
+    ARM_add_vector_size(MI, 64);
+     break;
+   case 31:
+     // MVE_VCVTf16f32bh, MVE_VCVTf16f32th, VCVTBSH, VCVTTSH, VCVTf2h
+     SStream_concat0(O, ".f16.f32\t");
+     ARM_add_vector_data(MI, ARM_VECTORDATA_F16F32);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     break;
+   case 32:
+     // MVE_VCVTf16s16_fix, MVE_VCVTf16s16n, VCVTs2hd, VCVTs2hq, VCVTxs2hd, VC...
+@@ -10265,28 +10269,31 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+     // VJCVT, VTOSIRD, VTOSIZD, VTOSLD
+     SStream_concat0(O, ".s32.f64\t");
+     ARM_add_vector_data(MI, ARM_VECTORDATA_S32F64);
+     printOperand(MI, 0, O);
+     SStream_concat0(O, ", ");
+     printOperand(MI, 1, O);
+     break;
+   case 54:
+     // VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq...
+     SStream_concat0(O, ".16\t{");
+    ARM_add_vector_size(MI, 16);
+     break;
+   case 55:
+     // VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq...
+     SStream_concat0(O, ".32\t{");
+    ARM_add_vector_size(MI, 32);
+     break;
+   case 56:
+     // VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U...
+     SStream_concat0(O, ".8\t{");
+    ARM_add_vector_size(MI, 8);
+     break;
+   case 57:
+     // VLDR_FPCXTNS_off, VLDR_FPCXTNS_post, VLDR_FPCXTNS_pre, VMSR_FPCXTNS, V...
+     SStream_concat0(O, "\tfpcxtns, ");
+     break;
+   case 58:
+     // VLDR_FPCXTS_off, VLDR_FPCXTS_post, VLDR_FPCXTS_pre, VMSR_FPCXTS, VSTR_...
+     SStream_concat0(O, "\tfpcxts, ");
+     break;
+   case 59:
--- a/suite/auto-sync/src/autosync/ASUpdater.py
+++ b/suite/auto-sync/src/autosync/ASUpdater.py
@ -182,6 +182,10 @@ class ASUpdater:
        if USteps.MC in self.steps:
            self.mc_updater.gen_all()
        if not self.write:
+            if self.inc_generator.has_inc_patches():
+                log.warning(
+                    f"Patches to inc files are only applied with the -w flag. This wasn't done. Find them in {get_path('{INC_PATCH_DIR}')}"
+                )
            # Done
            exit(0)

@ -194,6 +198,7 @@ class ASUpdater:
                continue
            self.copy_files(file, self.arch_dir)
            i += 1
+        self.inc_generator.apply_patches()
        log.info(f"Copied {i} files")

        i = 0
--- a/suite/auto-sync/src/autosync/IncGenerator.py
+++ b/suite/auto-sync/src/autosync/IncGenerator.py
@ -127,9 +127,13 @@ class IncGenerator:
                    log.fatal("Generation failed")
                    raise e

+    def has_inc_patches(self) -> bool:
+        patch_dir = self.patches_dir_path.joinpath(self.arch)
+        return patch_dir.exists()
+
    def apply_patches(self) -> None:
        """
-        Applies a all patches of inc files.
+        Applies all patches of inc files.
        Files must be moved to their arch/<ARCH> directory before.
        """
        patch_dir = self.patches_dir_path.joinpath(self.arch)
@ -139,10 +143,9 @@ class IncGenerator:
        for patch in patch_dir.iterdir():
            try:
                subprocess.run(
-                    ["git", "apply", str(patch)],
+                    ["git", "apply", "-C4", "--recount", str(patch)],
                    check=True,
                )
+                log.info(f"Applied inc patch {patch.name}")
            except subprocess.CalledProcessError as e:
-                log.warning(f"Patch {patch.name} did not apply correctly!")
-                log.warning(f"git apply returned: {e}")
-                return
+                log.warning(f".inc patch {patch.name} did not apply correctly!")
--- a/suite/auto-sync/src/autosync/cpptranslator/Differ.py
+++ b/suite/auto-sync/src/autosync/cpptranslator/Differ.py
@ -12,9 +12,9 @@ import sys
 import tempfile
 from enum import StrEnum
 from pathlib import Path
-from shutil import copy2
+from shutil import copyfile

-from tree_sitter import Language, Node, Parser, Tree
+from tree_sitter import Language, Node, Parser, Tree, Point

 from autosync.Targets import ARCH_LLVM_NAMING
 from autosync.cpptranslator.Configurator import Configurator
@ -38,31 +38,24 @@ class PatchCoord:

    start_byte: int
    end_byte: int
-    start_point: tuple[int, int]
-    end_point: tuple[int, int]
+    start_point: Point
+    end_point: Point

    def __init__(
        self,
        start_byte: int,
        end_byte: int,
-        start_point: tuple[int, int],
-        end_point: tuple[int, int],
+        start_point: Point,
+        end_point: Point,
+        inserted: bool = False,
    ):
        self.start_byte = start_byte
        self.end_byte = end_byte
        self.start_point = start_point
        self.end_point = end_point
+        self.inserted = inserted  # True, if the PatchCoordinates point to a position not occupied by a node.

    def __lt__(self, other):
-        if not (
-            (self.start_byte <= other.start_byte and self.end_byte <= other.end_byte)
-            or (self.start_byte >= other.start_byte and self.end_byte >= other.end_byte)
-        ):
-            raise IndexError(
-                f"Coordinates overlap. No comparison possible.\n"
-                f"a.start_byte = {self.start_byte} a.end_byte = {self.end_byte}\n"
-                f"b.start_byte = {other.start_byte} b.end_byte = {other.end_byte}\n"
-            )
        return self.end_byte < other.start_byte

    def __str__(self) -> str:
@ -129,18 +122,6 @@ class Patch:
        backup[self.node_id]["edit"] = self.edit.decode("utf8") if self.edit else ""
        return backup

-    def merge(self, other) -> None:
-        """
-        Merge two patches to one. Necessary if two old nodes are not present in the new file.
-        And therefore share PatchCoordinates.
-        """
-        if other.new:
-            raise ValueError("This patch should not have a .new set.")
-        if not other.old:
-            raise ValueError("No data in .old")
-        self.old = other.old + self.old
-        self.old_hash = get_sha256(self.old)
-
    def __lt__(self, other):
        try:
            return self.coord < other.coord
@ -161,20 +142,19 @@ class Differ:
    Then, we extract all nodes of a specific type out of this AST.
    Which nodes specifically is defined in "arch_config.json::General::nodes_to_diff".

-    These nodes (old and new separately) are than sorted descending by their coordinates.
-    Meaning, nodes at the end in the file come first.
+    These nodes (old and new separately) are then sorted descending by their coordinates.
+    Meaning, nodes at the end of the files come first.
    The identifiers of those nodes are saved in a single list.
-    Now we iterate over this list of identifiers. Now we make decisions:
+    Now we iterate over this list of identifiers and make decisions:

-    The node id is present as:
-        old node & new node     => Text matches?
+    The node id is present in:
+        old and new file        => Text matches?
                                    yes => Continue
-                                    no  => Add new node as Patch (see below)
-        only old node           => We save all consecutive old nodes, which have _no_ equivalent new node
-                                    and add them as single patch
-        only new node           => Add patch
+                                    no  => Patch node (see below)
+        only in one file        => Insert node at a suitable point (documented below in code).
+    A node is never removed from a file. This is the responsibility of the user when doing clean up.

-    Now we have the patch. We have a persistence file which saved previous decisions, on which patch to choose.
+    Now we have the patch. We have a persistence file which previous decisions, on which patch to choose.
    We take the node text of the old and new node (or only from a single one) and compare them to our previous decision.
    If the text of the nodes didn't change since the last run, we auto-apply the patch.
    Otherwise, the user decides:
@ -182,31 +162,29 @@ class Differ:
        - Choose the new node text
        - Open the editor to edit the patch and apply it.
        - Use the stored previous decision.
-        - Select always the old nodes.
-        - Go back and decide on node before.
+        - Select always the old nodes from now on.
+        - Go back and decide on the node before.

    Each decision is saved to the persistence file for later.
-
-    Last (optional) step is to write the patches to the new file.
-    Please note that we always write to the new file in the current version.
    """

    ts_cpp_lang: Language = None
    parser: Parser = None
    translated_files: [Path]
-    diff_dest_files: [Path] = list()
+    patched_file_paths: dict[str:Path] = dict()
    old_files: [Path]
    conf_arch: dict
    conf_general: dict
    tree: Tree = None
    persistence_filepath: Path
-    saved_patches: dict = None
+    saved_patches: dict = (
+        None  # Saved patches, indexed by old file names and node identifiers.
+    )
    patches: list[Patch]

-    current_patch: Patch
    cur_old_node: Node | None = None
    cur_new_node: Node | None = None
-    cur_nid: str = None
+    cur_nid: str = ""

    def __init__(
        self,
@ -214,6 +192,7 @@ class Differ:
        no_auto_apply: bool,
        testing: bool = False,
        check_saved: bool = False,
+        edit_old_file: bool = True,
    ):
        self.configurator = configurator
        self.no_auto_apply = no_auto_apply
@ -225,9 +204,13 @@ class Differ:
        self.differ = dl.Differ()
        self.testing = testing
        self.check_saved = check_saved
+        self.edit_old_file = (
+            edit_old_file  # If true, the changes are written to the old file.
+        )
+        self.user_choices = list()

-        self.diff_out_dir = get_path("{CPP_TRANSLATOR_DIFF_OUT_DIR}")
        if self.testing:
+            self.diff_out_dir = get_path("{DIFFER_TEST_OUTPUT_DIR}")
            t_out_dir: Path = get_path("{DIFFER_TEST_NEW_SRC_DIR}")
            self.translated_files = [
                t_out_dir.joinpath(sp["out"])
@ -239,6 +222,7 @@ class Differ:
            ]
            self.load_persistence_file()
        else:
+            self.diff_out_dir = get_path("{CPP_TRANSLATOR_DIFF_OUT_DIR}")
            t_out_dir: Path = get_path("{CPP_TRANSLATOR_TRANSLATION_OUT_DIR}")
            self.translated_files = [
                t_out_dir.joinpath(sp["out"])
@ -278,6 +262,9 @@ class Differ:
                exit(1)

    def save_to_persistence_file(self) -> None:
+        if self.testing:
+            print("Testing: Skip saving to persistent file...")
+            return
        print("\nSave choices...\n")
        with open(self.persistence_filepath, "w") as f:
            json.dump(self.saved_patches, f, indent=2)
@ -298,10 +285,11 @@ class Differ:
        """
        log.info("Copy files for editing")
        diff_dir: Path = self.diff_out_dir
-        for f in self.translated_files:
+        to_copy = self.old_files if self.edit_old_file else self.translated_files
+        for f in to_copy:
            dest = diff_dir.joinpath(f.name)
-            copy2(f, dest)
-            self.diff_dest_files.append(dest)
+            copyfile(f, dest)
+            self.patched_file_paths[f.name] = dest

    def get_diff_intro_msg(
        self,
@ -313,12 +301,17 @@ class Differ:
    ) -> str:
        color_new = self.conf_general["diff_color_new"]
        color_old = self.conf_general["diff_color_old"]
+        written_to = (
+            bold("OLD FILE", color_old)
+            if self.edit_old_file
+            else bold("NEW FILE", color_new)
+        )
        return (
            f"{bold(f'Diffing files - {current}/{total}')} \n\n"
            + f"{bold('NEW FILE: ', color_new)} {str(new_filename)}\n"
            + f"{bold('OLD FILE: ', color_old)} {str(old_filename)}\n\n"
            + f"{bold('Diffs to process: ')} {num_diffs}\n\n"
-            + f"{bold('Changes get written to: ')} {bold('NEW FILE', color_new)}\n"
+            + f"{bold('Changes are written to: ')} {written_to}\n"
        )

    def get_diff_node_id(self, node: Node) -> bytes:
@ -471,6 +464,9 @@ class Differ:
        self, saved_diff_present: bool, saved_choice: ApplyType
    ) -> ApplyType:
        while True:
+            if len(self.user_choices) > 0:
+                choice = self.user_choices.pop(0)
+            else:
                choice = self.print_prompt(saved_diff_present, saved_choice)
            if choice not in ["O", "o", "n", "e", "E", "s", "p", "q", "?", "help"]:
                print(f"{bold(choice)} is not valid.")
@ -531,37 +527,29 @@ class Differ:
    def add_patch(
        self,
        apply_type: ApplyType,
-        consec_old: int,
        old_filepath: Path,
        patch_coord: PatchCoord,
        saved_patch: dict | None = None,
        edited_text: bytes | None = None,
    ) -> None:
-        self.current_patch = self.create_patch(
-            patch_coord, apply_type, saved_patch, edited_text
-        )
-        self.persist_patch(old_filepath, self.current_patch)
-        if consec_old > 1:
-            # Two or more old nodes are not present in the new file.
-            # Merge them to one patch.
-            self.patches[-1].merge(self.current_patch)
-        else:
-            self.patches.append(self.current_patch)
+        patch = self.create_patch(patch_coord, apply_type, saved_patch, edited_text)
+        self.persist_patch(old_filepath, patch)
+        self.patches.append(patch)

    def diff_nodes(
        self,
        old_filepath: Path,
-        new_nodes: dict[bytes, Node],
-        old_nodes: dict[bytes, Node],
+        new_nodes: dict[str, Node],
+        old_nodes: dict[str, Node],
    ) -> list[Patch]:
        """
        Asks the user for each different node, which version should be written.
-        It writes the choice to a file, so the previous choice can be applied again if nothing changed.
+        It saves the choice to a file, so the previous choice can be applied again if nothing changed.
        """
        # Sort list of nodes descending.
        # This is necessary because
        #   a) we need to apply the patches backwards (starting from the end of the file,
-        #      so the coordinates in the file don't change, when replace text).
+        #      so the coordinates in the file don't change when replacing text).
        #   b) If there is an old node, which is not present in the new file, we search for
        #      a node which is adjacent (random node order wouldn't allow this).
        new_nodes = {
@ -579,24 +567,16 @@ class Differ:

        # Collect all node ids of this file
        node_ids = set()
-        for new_node_id, old_node_id in zip(new_nodes.keys(), old_nodes.keys()):
-            node_ids.add(new_node_id)
-            node_ids.add(old_node_id)
-
-        # The initial patch coordinates point after the last node in the file.
-        n0 = new_nodes[list(new_nodes.keys())[0]]
-        PatchCoord(n0.end_byte, n0.end_byte, n0.end_point, n0.end_point)
+        for n in list(new_nodes.keys()) + list(old_nodes.keys()):
+            node_ids.add(n)

        node_ids = sorted(node_ids)
        self.patches = list()
        matching_nodes_count = 0
-        # Counts the number of _consecutive_ old nodes which have no equivalent new node.
-        # They will be merged to a single patch later
-        consec_old = 0
        choice: ApplyType | None = None
        idx = 0
        while idx < len(node_ids):
-            self.cur_nid = node_ids[idx]
+            self.cur_nid: str = node_ids[idx]
            self.cur_new_node = (
                None if self.cur_nid not in new_nodes else new_nodes[self.cur_nid]
            )
@ -604,18 +584,18 @@ class Differ:
                None if self.cur_nid not in old_nodes else old_nodes[self.cur_nid]
            )

-            n = (
+            new_node_text = (
                self.cur_new_node.text.decode("utf8").splitlines()
                if self.cur_new_node
                else [""]
            )
-            o = (
+            old_node_text = (
                self.cur_old_node.text.decode("utf8").splitlines()
                if self.cur_old_node
                else [""]
            )

-            diff_lines = list(self.differ.compare(o, n))
+            diff_lines = list(self.differ.compare(old_node_text, new_node_text))
            if self.no_difference(diff_lines):
                log.info(
                    f"{bold('Patch:')} {idx + 1}/{len(node_ids)} - Nodes {bold(self.cur_nid)} match."
@ -624,35 +604,7 @@ class Differ:
                idx += 1
                continue

-            if self.cur_new_node:
-                consec_old = 0
-                # We always write to the new file. So we always take he coordinates form it.
-                patch_coord = PatchCoord.get_coordinates_from_node(self.cur_new_node)
-            else:
-                consec_old += 1
-                # If the old node has no equivalent new node,
-                # we search for the next adjacent old node which exist also in new nodes.
-                # The single old node is insert before the found new one.
-                old_node_ids = list(old_nodes.keys())
-                j = old_node_ids.index(self.cur_nid)
-                while j >= 0 and (old_node_ids[j] not in new_nodes.keys()):
-                    j -= 1
-                if j < 0 or old_node_ids[j] not in new_nodes.keys():
-                    # No new node exists before the old node.
-                    # So just put it to the very beginning.
-                    ref_end_byte = 1
-                    ref_start_point = (1, 0)
-                else:
-                    ref_new: Node = new_nodes[old_node_ids[j]]
-                    ref_end_byte = ref_new.start_byte
-                    ref_start_point = ref_new.start_point
-                # We always write to the new file. So we always take he coordinates form it.
-                patch_coord = PatchCoord(
-                    ref_end_byte - 1,
-                    ref_end_byte - 1,
-                    ref_start_point,
-                    ref_start_point,
-                )
+            patch_coord = self.determine_patch_coordinates(new_nodes, old_nodes)

            save_exists = False
            saved: dict | None = None
@ -664,7 +616,7 @@ class Differ:
                save_exists = True
                if self.saved_patch_matches(saved) and not self.no_auto_apply:
                    apply_type = ApplyType(saved["apply_type"])
-                    self.add_patch(apply_type, consec_old, old_filepath, patch_coord)
+                    self.add_patch(apply_type, old_filepath, patch_coord)
                    log.info(
                        f"{bold('Patch:')} {idx + 1}/{len(node_ids)} - Auto apply patch for {bold(self.cur_nid)}"
                    )
@ -672,7 +624,7 @@ class Differ:
                    continue

            if choice == ApplyType.OLD_ALL:
-                self.add_patch(ApplyType.OLD, consec_old, old_filepath, patch_coord)
+                self.add_patch(ApplyType.OLD, old_filepath, patch_coord)
                idx += 1
                continue

@ -685,17 +637,19 @@ class Differ:
                    # No data in old node. Skip
                    idx += 1
                    continue
-                self.add_patch(ApplyType.OLD, consec_old, old_filepath, patch_coord)
+                self.add_patch(ApplyType.OLD, old_filepath, patch_coord)
            elif choice == ApplyType.NEW:
-                # Already in file. Only save patch.
-                self.persist_patch(old_filepath, self.create_patch(patch_coord, choice))
+                if not self.cur_new_node:
+                    # No data in old node. Skip
+                    idx += 1
+                    continue
+                self.add_patch(ApplyType.NEW, old_filepath, patch_coord)
            elif choice == ApplyType.SAVED:
                if not save_exists:
                    print(bold("Save does not exist."))
                    continue
                self.add_patch(
                    saved["apply_type"],
-                    consec_old,
                    old_filepath,
                    patch_coord,
                    saved_patch=saved,
@ -713,14 +667,16 @@ class Differ:
                input("Press enter to continue...\n")
                continue
            elif choice == ApplyType.OLD_ALL:
-                self.add_patch(ApplyType.OLD, consec_old, old_filepath, patch_coord)
+                self.add_patch(ApplyType.OLD, old_filepath, patch_coord)
            elif choice == ApplyType.EDIT:
                edited_text = self.edit_patch(diff_lines)
                if not edited_text:
                    continue
-                self.persist_patch(
+                self.add_patch(
+                    ApplyType.EDIT,
                    old_filepath,
-                    self.create_patch(patch_coord, choice, edited_text=edited_text),
+                    patch_coord,
+                    edited_text=edited_text,
                )
            elif choice == ApplyType.PREVIOUS:
                if idx == 0:
@ -733,18 +689,80 @@ class Differ:
        log.info(f"Number of matching nodes = {matching_nodes_count}")
        return self.patches

-    def diff(self) -> None:
+    def determine_patch_coordinates(
+        self, new_nodes: dict[str, Node], old_nodes: dict[str, Node]
+    ):
+        # The node to be replaced is Node-PATCHED and part of File-PATCHED
+        # The other node is called Node-SRC and is part of File-SRC
+
+        if self.edit_old_file and self.cur_old_node:
+            # File-PATCHED = old file. Because we patch the old file.
+            patch_coord = PatchCoord.get_coordinates_from_node(self.cur_old_node)
+            return patch_coord
+        elif not self.edit_old_file and self.cur_new_node:
+            # File-PATCHED = new file. Because we patch the new file.
+            patch_coord = PatchCoord.get_coordinates_from_node(self.cur_new_node)
+            return patch_coord
+
+        # In this case there is no Node-PATCHED. So we don't know the PatchCoordinates.
+        # We have to insert Node-SRC at another point in the File-PATCHED.
+        # If the Node-SRC has no equivalent node in the FILE-PATCHED,
+        # we search for another Node-SRC also existing in File-PATCHED.
+        # The Node-SRC is insert before the equivalent node in File-PATCHED.
+        #
+        # Example:
+        #
+        # File-PATCHED       | File-SRC
+        # -------------------|-----------------
+        # ...                | ...
+        # <none>             | Node-SRC
+        # Node-PATCHED-fcn() | Node-SRC-fcn()
+        # ...                | ...
+        #
+        # Node-SRC is inserted before Node-PATCHED-fcn(). Because these
+        # are the nodes both files share.
+
+        patch_nodes = old_nodes if self.edit_old_file else new_nodes
+        src_nodes = new_nodes if self.edit_old_file else old_nodes
+
+        src_node_ids = list(src_nodes.keys())
+        j = src_node_ids.index(self.cur_nid)
+        while j >= 0 and (src_node_ids[j] not in patch_nodes.keys()):
+            j -= 1
+
+        if j < 0 or src_node_ids[j] not in patch_nodes.keys():
+            # No shared node before Node-SRC as reference.
+            # So put it to the very beginning of the file.
+            # The user should move it.
+            ref_end_byte = 1
+            ref_start_point = (1, 0)
+        else:
+            ref_new: Node = patch_nodes[src_node_ids[j]]
+            ref_end_byte = ref_new.start_byte
+            ref_start_point = ref_new.start_point
+        patch_coord = PatchCoord(
+            ref_end_byte - 1,
+            ref_end_byte - 1,
+            ref_start_point,
+            ref_start_point,
+            inserted=True,
+        )
+        return patch_coord
+
+    def diff(self, user_choices: list[str] | None = None) -> None:
        """
        Diffs certain nodes from the newly translated and old source files to each other.
        The user then selects which diff should be written to the new file.
        """

+        if user_choices:
+            self.user_choices = user_choices
        # We do not write to the translated files directly.
        self.copy_files()
        new_file = dict()
        old_file = dict()
        i = 0
-        for old_filepath, new_filepath in zip(self.old_files, self.diff_dest_files):
+        for old_filepath, new_filepath in zip(self.old_files, self.translated_files):
            new_file[i] = dict()
            new_file[i]["filepath"] = new_filepath
            new_file[i]["nodes"] = self.parse_file(new_filepath)
@ -763,11 +781,15 @@ class Differ:
            print_prominent_info(
                self.get_diff_intro_msg(
                    old_filepath, new_filepath, k + 1, i, diffs_to_process
-                )
+                ),
+                wait_for_user=(not self.testing),
            )
            if diffs_to_process == 0:
                continue
-            patches[new_filepath] = self.diff_nodes(
+            patch_file_path = (
+                old_filepath.name if self.edit_old_file else new_filepath.name
+            )
+            patches[self.patched_file_paths[patch_file_path]] = self.diff_nodes(
                old_filepath, new_file[k]["nodes"], old_file[k]["nodes"]
            )
        self.patch_files(patches)
@ -793,9 +815,17 @@ class Differ:
                else:
                    print_prominent_warning(f"No data for {patch.apply} defined.")
                    return
-                src = src[:start_byte] + data + src[end_byte:]
+                if patch.coord.inserted:
+                    # The patch doesn't replace a previous node.
+                    # So we wrap it in new lines to make it easier to fix later.
+                    data = b"\n" + data + b"\n"
+                prefix = src[:start_byte] if src[:start_byte] else b""
+                middle = data if data else b""
+                postfix = src[end_byte:] if src[end_byte:] else b""
+                src = prefix + middle + postfix
            with open(filepath, "wb") as f:
                f.write(src)
+        if not self.testing:
            run_clang_format(list(file_patches.keys()))
        return

@ -817,7 +847,6 @@ class Differ:
                if self.get_separator_line() in line:
                    break
                edited_text += line
-        tmp_file.close()
        return edited_text

    @staticmethod
@ -950,9 +979,6 @@ def parse_args() -> argparse.Namespace:


 if __name__ == "__main__":
-    if not sys.hexversion >= 0x030B00F0:
-        log.fatal("Python >= v3.11 required.")
-        exit(1)
    args = parse_args()
    log.basicConfig(
        level=convert_loglevel(args.verbosity),
--- a/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/expected/diff_test_file_patching_new.c
+++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/expected/diff_test_file_patching_new.c
@ -0,0 +1,30 @@
+
+void patch_beginning_of_file() {
+	return;
+}
+// SPDX-FileCopyrightText: 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+void function_a(int x) {
+	return;
+}
+
+int patch_new_into_old_II() {
+	// Should be at the same position between patch_new_into_old_I and function_a
+	// in the old file.
+	// The order of these two new functions are switched because they are
+	// applied backwards
+	return 0xffffffff;
+}
+
+int patch_new_into_old_I() {
+	// Should be at the same position between function_b and patch_new_into_old_II
+	// in the old file.
+	// The order of these two new functions are switched because they are
+	// applied backwards
+	return 0xffffffff;
+}
+
+void function_b(int x) {
+	return;
+}
--- a/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/expected/diff_test_file_patching_replace.c
+++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/expected/diff_test_file_patching_replace.c
@ -0,0 +1,24 @@
+// SPDX-FileCopyrightText: 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+void function_a(int x) {
+	return;
+}
+
+int patch_same_into_old_smaller() {
+	// Should replace the same function in the old file.
+	// At the same position between function_a and function_b.
+	// Function has more line than the function in the old file.
+	return 0xffffffff;
+}
+
+void function_b(int x) {
+	return;
+}
+
+void patch_same_into_old_bigger() {
+	// Should replace the same function in the old file.
+	// At the same position after function_b.
+	// Function has less lines than the function in the old file.
+	return 1;
+}
--- a/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/new_src/diff_test_file_patching_new.c
+++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/new_src/diff_test_file_patching_new.c
@ -0,0 +1,30 @@
+// SPDX-FileCopyrightText: 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+void function_a(int x) {
+	return;
+}
+
+int patch_new_into_old_I() {
+	// Should be at the same position between function_b and patch_new_into_old_II
+	// in the old file.
+	// The order of these two new functions are switched because they are
+	// applied backwards
+	return 0xffffffff;
+}
+
+int patch_new_into_old_II() {
+	// Should be at the same position between patch_new_into_old_I and function_a
+	// in the old file.
+	// The order of these two new functions are switched because they are
+	// applied backwards
+	return 0xffffffff;
+}
+
+void function_b(int x) {
+	return;
+}
+
+void patch_beginning_of_file() {
+	return;
+}
--- a/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/new_src/diff_test_file_patching_replace.c
+++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/new_src/diff_test_file_patching_replace.c
@ -0,0 +1,24 @@
+// SPDX-FileCopyrightText: 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+void function_a(int x) {
+	return;
+}
+
+int patch_same_into_old_smaller() {
+	// Should replace the same function in the old file.
+	// At the same position between function_a and function_b.
+	// Function has more line than the function in the old file.
+	return 0xffffffff;
+}
+
+void function_b(int x) {
+	return;
+}
+
+void patch_same_into_old_bigger() {
+	// Should replace the same function in the old file.
+	// At the same position after function_b.
+	// Function has less lines than the function in the old file.
+	return 1;
+}
--- a/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/old_src/diff_test_file_patching_new.c
+++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/old_src/diff_test_file_patching_new.c
@ -0,0 +1,10 @@
+// SPDX-FileCopyrightText: 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+void function_a(int x) {
+	return;
+}
+
+void function_b(int x) {
+	return;
+}
--- a/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/old_src/diff_test_file_patching_replace.c
+++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/old_src/diff_test_file_patching_replace.c
@ -0,0 +1,26 @@
+// SPDX-FileCopyrightText: 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+void function_a(int x) {
+	return;
+}
+
+int patch_same_into_old_smaller() {
+	// Function has less lines than the function in the new file.
+	return 0;
+}
+
+void function_b(int x) {
+	return;
+}
+
+int patch_same_into_old_bigger() {
+	// Function has more lines than the function in the new file.
+	int o = 0;
+	o += 1;
+	o += 1;
+	o += 1;
+	o += 1;
+	o += 1;
+	return 0;
+}
--- a/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/output/README.md
+++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/output/README.md
@ -0,0 +1,6 @@
+<!--
+Copyright © 2024 Rot127 <unisono@quyllur.org>
+SPDX-License-Identifier: BSD-3
+-->
+
+Output directory for patched files.
--- a/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/test_arch_config.json
+++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/test_arch_config.json
@ -26,6 +26,14 @@
      {
        "in": "{DIFFER_TEST_OLD_SRC_DIR}/diff_test_file.c",
        "out": "diff_test_file.c"
+      },
+      {
+        "in": "{DIFFER_TEST_OLD_SRC_DIR}/diff_test_file_patching_new.c",
+        "out": "diff_test_file_patching_new.c"
+      },
+      {
+        "in": "{DIFFER_TEST_OLD_SRC_DIR}/diff_test_file_patching_replace.c",
+        "out": "diff_test_file_patching_replace.c"
      }
    ],
    "files_for_template_search": [],
--- a/suite/auto-sync/src/autosync/cpptranslator/Tests/test_differ.py
+++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_differ.py
@ -22,6 +22,7 @@ class TestHeaderPatcher(unittest.TestCase):
            configurator.get_parser(), configurator.get_cpp_lang(), [], []
        )
        cls.differ = Differ(configurator, testing=True, no_auto_apply=True)
+        cls.maxDiff = 10000

    def check_persistence(self, nid, expected, apply_type, edited_text):
        new_node: Node = self.new_nodes[nid] if nid in self.new_nodes else None
@ -104,3 +105,13 @@ class TestHeaderPatcher(unittest.TestCase):
        }
        edited_text: bytes = b"aaaaaaa\n\n\n\n\n91928"
        self.check_persistence(nid, expected, ApplyType.EDIT, edited_text)
+
+    def test_patching(self):
+        self.differ.diff(user_choices=list("nnnnnnnnnnnnnnnnnnnnnnnnn"))
+        for efile in get_path("{DIFFER_TEST_EXPECTED_DIR}").iterdir():
+            with open(efile) as f:
+                expected = f.read()
+            with open(get_path("{DIFFER_TEST_OUTPUT_DIR}").joinpath(efile.name)) as f:
+                actual = f.read()
+            print(f"Compare {efile}")
+            self.assertEqual(expected, actual)
--- a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json
+++ b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json
--- a/suite/auto-sync/src/autosync/path_vars.json
+++ b/suite/auto-sync/src/autosync/path_vars.json
@ -35,6 +35,8 @@
    "{DIFFER_TEST_CONFIG_FILE}": "{DIFFER_TEST_DIR}/test_arch_config.json",
    "{DIFFER_TEST_OLD_SRC_DIR}": "{DIFFER_TEST_DIR}/old_src/",
    "{DIFFER_TEST_NEW_SRC_DIR}": "{DIFFER_TEST_DIR}/new_src/",
+    "{DIFFER_TEST_OUTPUT_DIR}": "{DIFFER_TEST_DIR}/output/",
+    "{DIFFER_TEST_EXPECTED_DIR}": "{DIFFER_TEST_DIR}/expected/",
    "{DIFFER_TEST_PERSISTENCE_FILE}": "{DIFFER_TEST_DIR}/test_saved_patches.json",
    "{AUTO_SYNC_TEST_DIR}": "{AUTO_SYNC_SRC}/Tests/",
    "{MCUPDATER_CONFIG_FILE}": "{AUTO_SYNC_SRC}/mcupdater.json",