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Add SYS ops test to cstest

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This commit is contained in:
Adam Seitz 2022-03-22 08:46:57 -04:00
parent 50535d9477
commit 82c6e17068
2 changed files with 20 additions and 37 deletions
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20
suite/cstest/issues.cs
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@ -1,3 +1,23 @@
!# issue 1856 AArch64 SYS instruction operands: tlbi 1 op
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0x1f,0x83,0x08,0xd5 == tlbi vmalle1is ; op_count: 1 ; operands[0].type: SYS = 0x3
!# issue 1856 AArch64 SYS instruction operands: tlbi 2 op
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0x22,0x87,0x08,0xd5 == tlbi vae1, x2 ; op_count: 2 ; operands[0].type: SYS = 0x16
!# issue 1856 AArch64 SYS instruction operands: at
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0xc0,0x78,0x0c,0xd5 == at s12e0r, x0 ; op_count: 2 ; operands[0].type: SYS = 0x59
!# issue 1856 AArch64 SYS instruction operands: dc
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0x22,0x7b,0x0b,0xd5 == dc cvau, x2 ; op_count: 2 ; operands[0].type: SYS = 0x62
!# issue 1856 AArch64 SYS instruction operands: ic
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0x20,0x75,0x0b,0xd5 == ic ivau, x0 ; op_count: 2 ; operands[0].type: SYS = 0x68
!# issue 1839 AArch64 Incorrect detailed disassembly of ldr
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0x41,0x00,0x40,0xf9 == ldr x1, [x2] ; operands[0].access: WRITE ; operands[1].access: READ

37
suite/regress/test_arm64_sys_op.py
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@ -1,37 +0,0 @@
import unittest
from capstone import *
from capstone.arm64 import *
class AArch64SysOpTest(unittest.TestCase):
PATTERNS = [
("22 7b 0b d5", ARM64_DC_CVAU, ARM64_REG_X2), # dc cvau, x2
("20 75 0b d5", ARM64_IC_IVAU, ARM64_REG_X0), # ic ivau, x0
("c0 78 0c d5", ARM64_AT_S12E0R, ARM64_REG_X0), # at s12e0r, x0
("22 87 08 d5", ARM64_TLBI_VAE1, ARM64_REG_X2), # tlbi vae1, x2
("1f 83 08 d5", ARM64_TLBI_VMALLE1IS, None), # tlbi vmalle1is
]
def test_operands(self):
cs = Cs(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN)
cs.detail = True
for pattern, sys, reg in self.PATTERNS:
l = list(cs.disasm(bytes.fromhex(pattern), 0))
self.assertEqual(len(l), 1)
insn = l[0]
if reg is None:
op_count = 1
else:
op_count = 2
self.assertEqual(len(insn.operands), op_count)
self.assertEqual(insn.operands[0].type, ARM64_OP_SYS)
self.assertEqual(insn.operands[0].value.sys, sys)
if reg:
self.assertEqual(insn.operands[1].type, ARM64_OP_REG)
self.assertEqual(insn.operands[1].value.reg, reg)
if __name__ == '__main__':
unittest.main()