mirror of
https://github.com/capstone-engine/capstone.git
synced 2024-11-23 13:39:46 +00:00
Remove all compiler warnings
This commit is contained in:
Sidney Pontes Filho
billow
parent
c1c16347b3
commit
82fcf25a5c
@ -1,7 +0,0 @@
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TODO
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TriCoreInstPrinter.c
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- Implement all related functions
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TriCoreGenAsmWriter.inc
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- Fix according to TriCoreInstPrinter.c
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@ -69,126 +69,48 @@ static DecodeStatus DecodeAddrRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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static DecodeStatus DecodeExtRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodePSRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSBInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSBRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeBInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRCPWInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRCLInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder);
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#include "TriCoreGenDisassemblerTables.inc"
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#define GET_REGINFO_ENUM
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@ -237,20 +159,6 @@ static DecodeStatus DecodeExtRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodePSRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder)
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{
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unsigned Reg;
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if (RegNo < 40 || RegNo > 43)
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return MCDisassembler_Fail;
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Reg = getReg(Decoder, TriCore_PSRegsRegClassID, RegNo);
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeOperandRegister(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder)
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{
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@ -275,36 +183,6 @@ static DecodeStatus DecodeOperandRegister(MCInst *Inst, unsigned RegNo,
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#define GET_INSTRINFO_ENUM
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#include "TriCoreGenInstrInfo.inc"
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static DecodeStatus DecodeSBInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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unsigned disp8 = fieldFromInstruction_4(Insn, 8, 8);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if(is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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// Decode disp8.
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MCOperand_CreateImm0(Inst, disp8);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if(is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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// Decode const4.
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MCOperand_CreateImm0(Inst, const4);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSBRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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@ -323,25 +201,6 @@ static DecodeStatus DecodeSBRInstruction(MCInst *Inst, unsigned Insn,
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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unsigned n = fieldFromInstruction_4(Insn, 12, 4);
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unsigned const4 = fieldFromInstruction_4(Insn, 8, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if(is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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// Decode n.
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MCOperand_CreateImm0(Inst, n);
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// Decode const4.
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MCOperand_CreateImm0(Inst, const4);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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@ -357,52 +216,6 @@ static DecodeStatus DecodeSCInstruction(MCInst *Inst, unsigned Insn,
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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DecodeStatus status;
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unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
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unsigned d = fieldFromInstruction_4(Insn, 8, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if(is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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// Decode s2.
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status = DecodeOperandRegister(Inst, s2, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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// Decode d.
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status = DecodeOperandRegister(Inst, d, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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DecodeStatus status;
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unsigned off4 = fieldFromInstruction_4(Insn, 12, 4);
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unsigned d = fieldFromInstruction_4(Insn, 8, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if(is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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// Decode off4.
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MCOperand_CreateImm0(Inst, off4);
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// Decode d.
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status = DecodeOperandRegister(Inst, d, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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@ -443,28 +256,6 @@ static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn,
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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DecodeStatus status;
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unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
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unsigned off4 = fieldFromInstruction_4(Insn, 8, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if(is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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// Decode s2.
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status = DecodeOperandRegister(Inst, s2, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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// Decode off4.
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MCOperand_CreateImm0(Inst, off4);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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@ -489,137 +280,6 @@ static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn,
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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DecodeStatus status;
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unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
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unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
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unsigned n = fieldFromInstruction_4(Insn, 6, 2);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if(is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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// Decode s2.
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status = DecodeOperandRegister(Inst, s2, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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// Decode s1/d.
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status = DecodeOperandRegister(Inst, s1_d, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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// Decode n.
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MCOperand_CreateImm0(Inst, n);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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DecodeStatus status;
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unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
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unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if(is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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// Decode s2.
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status = DecodeOperandRegister(Inst, s2, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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// Decode s1.
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status = DecodeOperandRegister(Inst, s1, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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DecodeStatus status;
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unsigned off4 = fieldFromInstruction_4(Insn, 12, 4);
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unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if(is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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// Decode off4.
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MCOperand_CreateImm0(Inst, off4);
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// Decode s1.
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status = DecodeOperandRegister(Inst, s1, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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DecodeStatus status;
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unsigned off18_0 = fieldFromInstruction_4(Insn, 16, 6);
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unsigned off18_1 = fieldFromInstruction_4(Insn, 28, 4);
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unsigned off18_2 = fieldFromInstruction_4(Insn, 22, 4);
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unsigned off18_3 = fieldFromInstruction_4(Insn, 12, 4);
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unsigned off18 = (off18_0 << 0) | (off18_1 << 6) |
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(off18_2 << 10) | (off18_3 << 14);
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unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if(!is32Bit) // This instruction is 32-bit
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return MCDisassembler_Fail;
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// Decode off18.
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MCOperand_CreateImm0(Inst, off18);
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// Decode s1/d.
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status = DecodeOperandRegister(Inst, s1_d, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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unsigned off18_0 = fieldFromInstruction_4(Insn, 16, 6);
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unsigned off18_1 = fieldFromInstruction_4(Insn, 28, 4);
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unsigned off18_2 = fieldFromInstruction_4(Insn, 22, 4);
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unsigned off18_3 = fieldFromInstruction_4(Insn, 12, 4);
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unsigned off18 = (off18_0 << 0) | (off18_1 << 6) |
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(off18_2 << 10) | (off18_3 << 14);
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unsigned b = fieldFromInstruction_4(Insn, 11, 1);
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unsigned bpos3 = fieldFromInstruction_4(Insn, 8, 3);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if(!is32Bit) // This instruction is 32-bit
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return MCDisassembler_Fail;
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// Decode off18.
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MCOperand_CreateImm0(Inst, off18);
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// Decode b.
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MCOperand_CreateImm0(Inst, b);
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// Decode bpos3.
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MCOperand_CreateImm0(Inst, bpos3);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeBInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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@ -638,45 +298,6 @@ static DecodeStatus DecodeBInstruction(MCInst *Inst, unsigned Insn,
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, void *Decoder)
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{
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DecodeStatus status;
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unsigned d = fieldFromInstruction_4(Insn, 28, 4);
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unsigned pos2 = fieldFromInstruction_4(Insn, 23, 5);
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unsigned pos1 = fieldFromInstruction_4(Insn, 16, 5);
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unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
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unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode d.
|
||||
status = DecodeOperandRegister(Inst, d, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode pos2.
|
||||
MCOperand_CreateImm0(Inst, pos2);
|
||||
|
||||
// Decode pos1.
|
||||
MCOperand_CreateImm0(Inst, pos1);
|
||||
|
||||
// Decode s2.
|
||||
status = DecodeOperandRegister(Inst, s2, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
@ -742,91 +363,6 @@ static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned disp15 = fieldFromInstruction_4(Insn, 16, 15);
|
||||
unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode disp15.
|
||||
MCOperand_CreateImm0(Inst, disp15);
|
||||
|
||||
// Decode const4.
|
||||
MCOperand_CreateImm0(Inst, const4);
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned disp15 = fieldFromInstruction_4(Insn, 16, 15);
|
||||
unsigned n_0 = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned n_1 = fieldFromInstruction_4(Insn, 7, 1);
|
||||
unsigned n = (n_0 << 0) | (n_1 << 4);
|
||||
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode disp15.
|
||||
MCOperand_CreateImm0(Inst, disp15);
|
||||
|
||||
// Decode n.
|
||||
MCOperand_CreateImm0(Inst, n);
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned disp15 = fieldFromInstruction_4(Insn, 16, 15);
|
||||
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode disp15.
|
||||
MCOperand_CreateImm0(Inst, disp15);
|
||||
|
||||
// Decode s2.
|
||||
status = DecodeOperandRegister(Inst, s2, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
@ -893,115 +429,6 @@ static DecodeStatus DecodeRCPWInstruction(MCInst *Inst, unsigned Insn,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
||||
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
||||
unsigned const9 = fieldFromInstruction_4(Insn, 12, 9);
|
||||
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode d.
|
||||
status = DecodeOperandRegister(Inst, d, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s3.
|
||||
status = DecodeOperandRegister(Inst, s3, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode const9.
|
||||
MCOperand_CreateImm0(Inst, const9);
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
||||
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
||||
unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode d.
|
||||
status = DecodeOperandRegister(Inst, d, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s3.
|
||||
status = DecodeOperandRegister(Inst, s3, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode const4.
|
||||
MCOperand_CreateImm0(Inst, const4);
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
||||
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
||||
unsigned width = fieldFromInstruction_4(Insn, 16, 5);
|
||||
unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode d.
|
||||
status = DecodeOperandRegister(Inst, d, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s3.
|
||||
status = DecodeOperandRegister(Inst, s3, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode width.
|
||||
MCOperand_CreateImm0(Inst, width);
|
||||
|
||||
// Decode const4.
|
||||
MCOperand_CreateImm0(Inst, const4);
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRCLInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
@ -1066,41 +493,6 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
||||
unsigned n = fieldFromInstruction_4(Insn, 16, 2);
|
||||
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode d.
|
||||
status = DecodeOperandRegister(Inst, d, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode n.
|
||||
MCOperand_CreateImm0(Inst, n);
|
||||
|
||||
// Decode s2.
|
||||
status = DecodeOperandRegister(Inst, s2, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
@ -1171,222 +563,6 @@ static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
||||
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
||||
unsigned n = fieldFromInstruction_4(Insn, 16, 2);
|
||||
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode d.
|
||||
status = DecodeOperandRegister(Inst, d, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s3.
|
||||
status = DecodeOperandRegister(Inst, s3, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode n.
|
||||
MCOperand_CreateImm0(Inst, n);
|
||||
|
||||
// Decode s2.
|
||||
status = DecodeOperandRegister(Inst, s2, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
||||
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
||||
unsigned n = fieldFromInstruction_4(Insn, 16, 2);
|
||||
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode d.
|
||||
status = DecodeOperandRegister(Inst, d, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s3.
|
||||
status = DecodeOperandRegister(Inst, s3, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode n.
|
||||
MCOperand_CreateImm0(Inst, n);
|
||||
|
||||
// Decode s2.
|
||||
status = DecodeOperandRegister(Inst, s2, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
||||
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
||||
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode d.
|
||||
status = DecodeOperandRegister(Inst, d, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s3.
|
||||
status = DecodeOperandRegister(Inst, s3, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s2.
|
||||
status = DecodeOperandRegister(Inst, s2, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
||||
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
||||
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode d.
|
||||
status = DecodeOperandRegister(Inst, d, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s3.
|
||||
status = DecodeOperandRegister(Inst, s3, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s2.
|
||||
status = DecodeOperandRegister(Inst, s2, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
||||
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
||||
unsigned width = fieldFromInstruction_4(Insn, 16, 5);
|
||||
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode d.
|
||||
status = DecodeOperandRegister(Inst, d, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s3.
|
||||
status = DecodeOperandRegister(Inst, s3, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode width.
|
||||
MCOperand_CreateImm0(Inst, width);
|
||||
|
||||
// Decode s2.
|
||||
status = DecodeOperandRegister(Inst, s2, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
// Decode s1.
|
||||
status = DecodeOperandRegister(Inst, s1, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder)
|
||||
{
|
||||
DecodeStatus status;
|
||||
unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
|
||||
|
||||
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
||||
|
||||
if(!is32Bit) // This instruction is 32-bit
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// Decode s1/d.
|
||||
status = DecodeOperandRegister(Inst, s1_d, Address, Decoder);
|
||||
if (status != MCDisassembler_Success)
|
||||
return status;
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
#define GET_SUBTARGETINFO_ENUM
|
||||
#include "TriCoreGenInstrInfo.inc"
|
||||
bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
|
||||
|
||||
@ -205,26 +205,6 @@ static void printAddrModeMemSrc(MCInst *MI, int OpNum, SStream *O) {
|
||||
set_mem_access(MI, false);
|
||||
}
|
||||
|
||||
static void printCCOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
MCOperand *MO = MCInst_getOperand(MI, OpNum);
|
||||
unsigned CC = MCOperand_getImm(MO);
|
||||
switch (CC) {
|
||||
default: // unreachable
|
||||
case 0:
|
||||
SStream_concat0(O, "eq");
|
||||
break;
|
||||
case 1:
|
||||
SStream_concat0(O, "ne");
|
||||
break;
|
||||
case 3:
|
||||
SStream_concat0(O, "lt");
|
||||
break;
|
||||
case 2:
|
||||
SStream_concat0(O, "ge");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#define PRINT_ALIAS_INSTR
|
||||
#include "TriCoreGenAsmWriter.inc"
|
||||
|
||||
@ -359,7 +359,7 @@ typedef struct cs_detail {
|
||||
cs_bpf bpf; ///< Berkeley Packet Filter architecture (including eBPF)
|
||||
cs_riscv riscv; ///< RISCV architecture
|
||||
cs_sh sh; ///< SH architecture
|
||||
cs_tricore tricore; // XCore architecture
|
||||
cs_tricore tricore; ///< TriCore architecture
|
||||
};
|
||||
} cs_detail;
|
||||
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/* Capstone Disassembler Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
// TODO: This is just a copy of XCore. Implement for TriCore.
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include <platform.h>
|
||||
@ -74,7 +72,7 @@ static void print_insn_detail(cs_insn *ins)
|
||||
|
||||
static void test()
|
||||
{
|
||||
#define TRICORE_CODE "\x16\x01"
|
||||
#define TRICORE_CODE "\x16\x01\x20\x01"
|
||||
|
||||
struct platform platforms[] = {
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user