Add Alpha architecture (#2071)

CMakeLists.txt

@@ -57,8 +57,8 @@ option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by defau
 option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF)
 option(CAPSTONE_INSTALL "Generate install target" ${PROJECT_IS_TOP_LEVEL})
 
-set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE)
-set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore)
+set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA)
+set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha)
 
 list(LENGTH SUPPORTED_ARCHITECTURES count)
 math(EXPR count "${count}-1")
@@ -157,6 +157,7 @@ set(HEADERS_COMMON
     include/capstone/tricore.h
     include/capstone/platform.h
     include/capstone/sh.h
+    include/capstone/alpha.h
 )
 
 set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c)
@@ -581,6 +582,30 @@ if (CAPSTONE_TRICORE_SUPPORT)
     set(TEST_SOURCES ${TEST_SOURCES} test_tricore.c)
 endif ()
 
+if (CAPSTONE_ALPHA_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_ALPHA)
+    set(SOURCES_ALPHA
+            arch/Alpha/AlphaDisassembler.c
+            arch/Alpha/AlphaInstPrinter.c
+            arch/Alpha/AlphaMapping.c
+            arch/Alpha/AlphaModule.c
+            )
+    set(HEADERS_ALPHA
+            arch/Alpha/AlphaDisassembler.h
+            arch/Alpha/AlphaGenAsmWriter.inc
+            arch/Alpha/AlphaGenDisassemblerTables.inc
+            arch/Alpha/AlphaGenInstrInfo.inc
+            arch/Alpha/AlphaGenRegisterInfo.inc
+            arch/Alpha/AlphaLinkage.h
+            arch/Alpha/AlphaMapping.h
+            arch/Alpha/AlphaModule.h
+            arch/Alpha/AlphaGenCSMappingInsnOp.inc
+            arch/Alpha/AlphaGenCSMappingInsn.inc
+            arch/Alpha/AlphaGenCSMappingInsnName.inc
+            )
+    set(TEST_SOURCES ${TEST_SOURCES} test_alpha.c)
+endif ()
+
 if (CAPSTONE_OSXKERNEL_SUPPORT)
     add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
 endif()
@@ -605,6 +630,7 @@ set(ALL_SOURCES
     ${SOURCES_RISCV}
     ${SOURCES_SH}
     ${SOURCES_TRICORE}
+    ${SOURCES_ALPHA}
 )
 
 set(ALL_HEADERS
@@ -628,6 +654,7 @@ set(ALL_HEADERS
     ${HEADERS_RISCV}
     ${HEADERS_SH}
     ${HEADERS_TRICORE}
+    ${HEADERS_ALPHA}
 )
 
 ## properties
@@ -691,6 +718,7 @@ source_group("Source\\BPF" FILES ${SOURCES_BPF})
 source_group("Source\\RISCV" FILES ${SOURCES_RISCV})
 source_group("Source\\SH" FILES ${SOURCES_SH})
 source_group("Source\\TriCore" FILES ${SOURCES_TRICORE})
+source_group("Source\\Alpha" FILES ${SOURCES_ALPHA})
 
 source_group("Include\\Common" FILES ${HEADERS_COMMON})
 source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
@@ -712,6 +740,7 @@ source_group("Include\\BPF" FILES ${HEADERS_BPF})
 source_group("Include\\RISCV" FILES ${HEADERS_RISCV})
 source_group("Include\\SH" FILES ${HEADERS_SH})
 source_group("Include\\TriCore" FILES ${HEADERS_TRICORE})
+source_group("Include\\Alpha" FILES ${HEADERS_ALPHA})
 
 ## installation
 if(CAPSTONE_INSTALL)

COMPILE.TXT

@@ -85,6 +85,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 
 	/usr/include/capstone/arm.h
 	/usr/include/capstone/arm64.h
+	/usr/include/capstone/alpha.h
 	/usr/include/capstone/bpf.h
 	/usr/include/capstone/capstone.h
 	/usr/include/capstone/evm.h

COMPILE_CMAKE.TXT

@@ -21,6 +21,7 @@ Get CMake for free from http://www.cmake.org.
 
   - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM.
   - CAPSTONE_AARCH64_SUPPORT: support AARCH64. Run cmake with -DCAPSTONE_AARCH64_SUPPORT=0 to remove AARCH64.
+  - CAPSTONE_ALPHA_SUPPORT: support Alpha. Run cmake with -DCAPSTONE_ALPHA_SUPPORT=0 to remove Alpha.
   - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.
   - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K.
   - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips.
@@ -113,7 +114,7 @@ Get CMake for free from http://www.cmake.org.
 
   Will just target the x86 architecture. The list of available architectures is: ARM,
   AARCH64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX,
-  WASM, BPF, RISCV.
+  WASM, BPF, RISCV, Alpha.
   
 (4) You can also create an installation image with cmake, by using the 'install' target.
   Use:

COMPILE_MSVC.TXT

@@ -32,6 +32,7 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.
 
   - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support.
   - CAPSTONE_HAS_AARCH64: support AARCH64. Delete this to remove AARCH64 support.
+  - CAPSTONE_HAS_ALPHA: support Alpha. Delete this to remove Alpha support.
   - CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support.
   - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support.
   - CAPSTONE_HAS_POWERPC: support PPC. Delete this to remove PPC support.
@@ -41,7 +42,7 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.
   - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support.
   - CAPSTONE_HAS_TRICORE: support TriCore. Delete this to remove TriCore support.
 
-  By default, all 9 architectures are compiled in.
+  By default, all 11 architectures are compiled in.
 
 
   Besides, Capstone also allows some more customization via following macros.

CREDITS.TXT

@@ -88,3 +88,4 @@ fanfuqiang & citypw & porto703 : RISCV architecture.
 Josh "blacktop" Maine: Arm64 architecture improvements.
 Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support)
 Billow & Sidneyp : TriCore architecture.
+Dmitry Sibirtsev: Alpha architecture.

HACK.TXT

@@ -6,6 +6,7 @@ Capstone source is organized as followings.
 .                   <- core engine + README + COMPILE.TXT etc
 ├── arch            <- code handling disasm engine for each arch
 │   ├── AArch64     <- AArch64 engine
+│   ├── Alpha       <- Alpha engine
 │   ├── ARM         <- ARM engine
 │   ├── BPF         <- Berkeley Packet Filter engine
 │   ├── EVM         <- Ethereum engine

Makefile

@@ -325,12 +325,21 @@ ifneq (,$(findstring tricore,$(CAPSTONE_ARCHS)))
 	LIBOBJ_TRICORE += $(LIBSRC_TRICORE:%.c=$(OBJDIR)/%.o)
 endif
 
+DEP_ALPHA =
+DEP_ALPHA +=$(wildcard arch/Alpha/Alpha*.inc)
+
+LIBOBJ_ALPHA =
+ifneq (,$(findstring alpha,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_ALPHA
+	LIBSRC_ALPHA += $(wildcard arch/Alpha/Alpha*.c)
+	LIBOBJ_ALPHA += $(LIBSRC_ALPHA:%.c=$(OBJDIR)/%.o)
+endif
 
 LIBOBJ =
 LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o
 LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_AARCH64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
 LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
-LIBOBJ += $(LIBOBJ_TRICORE)
+LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA)
 
 
 ifeq ($(PKG_EXTRA),)
@@ -466,6 +475,7 @@ $(LIBOBJ_WASM): $(DEP_WASM)
 $(LIBOBJ_MOS65XX): $(DEP_MOS65XX)
 $(LIBOBJ_BPF): $(DEP_BPF)
 $(LIBOBJ_TRICORE): $(DEP_TRICORE)
+$(LIBOBJ_ALPHA): $(DEP_ALPHA)
 
 ifeq ($(CAPSTONE_STATIC),yes)
 $(ARCHIVE): $(LIBOBJ)
@@ -552,12 +562,12 @@ dist:
 	git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
 
 TESTS  = test_basic test_detail test_arm test_aarch64 test_m68k test_mips test_ppc test_sparc test_tricore
-TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf
+TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf test_alpha
 TESTS += test_basic.static test_detail.static test_arm.static test_aarch64.static
 TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static
 TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static
 TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static test_riscv.static
-TESTS += test_mos65xx.static test_wasm.static test_bpf.static
+TESTS += test_mos65xx.static test_wasm.static test_bpf.static test_alpha.static
 
 check: $(TESTS)
 

Mapping.c

@@ -314,6 +314,7 @@ DEFINE_get_detail_op(arm, ARM);
 DEFINE_get_detail_op(ppc, PPC);
 DEFINE_get_detail_op(tricore, TriCore);
 DEFINE_get_detail_op(aarch64, AArch64);
+DEFINE_get_detail_op(alpha, Alpha);
 
 /// Returns true if for this architecture the
 /// alias operands should be filled.

Mapping.h

@@ -121,6 +121,7 @@ DECL_get_detail_op(arm, ARM);
 DECL_get_detail_op(ppc, PPC);
 DECL_get_detail_op(tricore, TriCore);
 DECL_get_detail_op(aarch64, AArch64);
+DECL_get_detail_op(alpha, Alpha);
 
 /// Increments the detail->arch.op_count by one.
 #define DEFINE_inc_detail_op_count(arch, ARCH) \
@@ -144,6 +145,8 @@ DEFINE_inc_detail_op_count(tricore, TriCore);
 DEFINE_dec_detail_op_count(tricore, TriCore);
 DEFINE_inc_detail_op_count(aarch64, AArch64);
 DEFINE_dec_detail_op_count(aarch64, AArch64);
+DEFINE_inc_detail_op_count(alpha, Alpha);
+DEFINE_dec_detail_op_count(alpha, Alpha);
 
 /// Returns true if a memory operand is currently edited.
 static inline bool doing_mem(const MCInst *MI)
@@ -169,6 +172,7 @@ DEFINE_get_arch_detail(arm, ARM);
 DEFINE_get_arch_detail(ppc, PPC);
 DEFINE_get_arch_detail(tricore, TriCore);
 DEFINE_get_arch_detail(aarch64, AArch64);
+DEFINE_get_arch_detail(alpha, Alpha);
 
 static inline bool detail_is_set(const MCInst *MI)
 {

arch/Alpha/AlphaDisassembler.c

@@ -0,0 +1,113 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev  <sibirtsevdl@gmail.com>, 2023 */
+
+#ifdef CAPSTONE_HAS_ALPHA
+
+#include <stdio.h> // DEBUG
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../utils.h"
+
+#include "../../MCFixedLenDisassembler.h"
+#include "../../Mapping.h"
+
+#include "AlphaDisassembler.h"
+#include "AlphaLinkage.h"
+
+static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder);
+
+static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder);
+
+static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder);
+
+#include "AlphaGenDisassemblerTables.inc"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+
+#include "AlphaGenRegisterInfo.inc"
+
+static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	unsigned Register = GPRC[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	unsigned Register = F4RC[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	unsigned Register = F8RC[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
+
+#define GET_SUBTARGETINFO_ENUM
+
+#include "AlphaGenInstrInfo.inc"
+
+DecodeStatus Alpha_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+									   size_t ByteLen, MCInst *MI,
+									   uint16_t *Size, uint64_t Address,
+									   void *Info)
+{
+	if (!handle) {
+		return MCDisassembler_Fail;
+	}
+
+	if (ByteLen < 4) {
+		*Size = 0;
+		return MCDisassembler_Fail;
+	}
+
+	uint32_t Insn = readBytes32(MI, Bytes);
+	// Calling the auto-generated decoder function.
+	DecodeStatus Result =
+		decodeInstruction_4(DecoderTable32, MI, Insn, Address, NULL);
+
+	if (Result != MCDisassembler_Fail) {
+		*Size = 4;
+		return Result;
+	}
+
+	*Size = 4;
+	return MCDisassembler_Fail;
+}
+
+void Alpha_init(MCRegisterInfo *MRI)
+{
+	MCRegisterInfo_InitMCRegisterInfo(
+		MRI, AlphaRegDesc, ARR_SIZE(AlphaRegDesc), 0, 0, AlphaMCRegisterClasses,
+		ARR_SIZE(AlphaMCRegisterClasses), 0, 0, AlphaRegDiffLists, 0,
+		AlphaSubRegIdxLists, 1, 0);
+}
+
+#endif

arch/Alpha/AlphaDisassembler.h

@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifndef CS_ALPHADISASSEMBLER_H
+#define CS_ALPHADISASSEMBLER_H
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include <capstone/capstone.h>
+
+void Alpha_init(MCRegisterInfo *MRI);
+
+#endif // CS_ALPHADISASSEMBLER_H

arch/Alpha/AlphaGenCSMappingInsnName.inc

@@ -0,0 +1,164 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
+/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  "invalid", // Alpha_INS_INVALID
+  "addl", // Alpha_INS_ADDL
+  "addq", // Alpha_INS_ADDQ
+  "adds/su", // Alpha_INS_ADDSsSU
+  "addt/su", // Alpha_INS_ADDTsSU
+  "and", // Alpha_INS_AND
+  "beq", // Alpha_INS_BEQ
+  "bge", // Alpha_INS_BGE
+  "bgt", // Alpha_INS_BGT
+  "bic", // Alpha_INS_BIC
+  "bis", // Alpha_INS_BIS
+  "blbc", // Alpha_INS_BLBC
+  "blbs", // Alpha_INS_BLBS
+  "ble", // Alpha_INS_BLE
+  "blt", // Alpha_INS_BLT
+  "bne", // Alpha_INS_BNE
+  "br", // Alpha_INS_BR
+  "bsr", // Alpha_INS_BSR
+  "cmoveq", // Alpha_INS_CMOVEQ
+  "cmovge", // Alpha_INS_CMOVGE
+  "cmovgt", // Alpha_INS_CMOVGT
+  "cmovlbc", // Alpha_INS_CMOVLBC
+  "cmovlbs", // Alpha_INS_CMOVLBS
+  "cmovle", // Alpha_INS_CMOVLE
+  "cmovlt", // Alpha_INS_CMOVLT
+  "cmovne", // Alpha_INS_CMOVNE
+  "cmpbge", // Alpha_INS_CMPBGE
+  "cmpeq", // Alpha_INS_CMPEQ
+  "cmple", // Alpha_INS_CMPLE
+  "cmplt", // Alpha_INS_CMPLT
+  "cmpteq/su", // Alpha_INS_CMPTEQsSU
+  "cmptle/su", // Alpha_INS_CMPTLEsSU
+  "cmptlt/su", // Alpha_INS_CMPTLTsSU
+  "cmptun/su", // Alpha_INS_CMPTUNsSU
+  "cmpule", // Alpha_INS_CMPULE
+  "cmpult", // Alpha_INS_CMPULT
+  "COND_BRANCH", // Alpha_INS_COND_BRANCH
+  "cpyse", // Alpha_INS_CPYSE
+  "cpysn", // Alpha_INS_CPYSN
+  "cpys", // Alpha_INS_CPYS
+  "ctlz", // Alpha_INS_CTLZ
+  "ctpop", // Alpha_INS_CTPOP
+  "cttz", // Alpha_INS_CTTZ
+  "cvtqs/sui", // Alpha_INS_CVTQSsSUI
+  "cvtqt/sui", // Alpha_INS_CVTQTsSUI
+  "cvtst/s", // Alpha_INS_CVTSTsS
+  "cvttq/svc", // Alpha_INS_CVTTQsSVC
+  "cvtts/sui", // Alpha_INS_CVTTSsSUI
+  "divs/su", // Alpha_INS_DIVSsSU
+  "divt/su", // Alpha_INS_DIVTsSU
+  "ecb", // Alpha_INS_ECB
+  "eqv", // Alpha_INS_EQV
+  "excb", // Alpha_INS_EXCB
+  "extbl", // Alpha_INS_EXTBL
+  "extlh", // Alpha_INS_EXTLH
+  "extll", // Alpha_INS_EXTLL
+  "extqh", // Alpha_INS_EXTQH
+  "extql", // Alpha_INS_EXTQL
+  "extwh", // Alpha_INS_EXTWH
+  "extwl", // Alpha_INS_EXTWL
+  "fbeq", // Alpha_INS_FBEQ
+  "fbge", // Alpha_INS_FBGE
+  "fbgt", // Alpha_INS_FBGT
+  "fble", // Alpha_INS_FBLE
+  "fblt", // Alpha_INS_FBLT
+  "fbne", // Alpha_INS_FBNE
+  "fcmoveq", // Alpha_INS_FCMOVEQ
+  "fcmovge", // Alpha_INS_FCMOVGE
+  "fcmovgt", // Alpha_INS_FCMOVGT
+  "fcmovle", // Alpha_INS_FCMOVLE
+  "fcmovlt", // Alpha_INS_FCMOVLT
+  "fcmovne", // Alpha_INS_FCMOVNE
+  "fetch", // Alpha_INS_FETCH
+  "fetch_m", // Alpha_INS_FETCH_M
+  "ftois", // Alpha_INS_FTOIS
+  "ftoit", // Alpha_INS_FTOIT
+  "insbl", // Alpha_INS_INSBL
+  "inslh", // Alpha_INS_INSLH
+  "insll", // Alpha_INS_INSLL
+  "insqh", // Alpha_INS_INSQH
+  "insql", // Alpha_INS_INSQL
+  "inswh", // Alpha_INS_INSWH
+  "inswl", // Alpha_INS_INSWL
+  "itofs", // Alpha_INS_ITOFS
+  "itoft", // Alpha_INS_ITOFT
+  "jmp", // Alpha_INS_JMP
+  "jsr", // Alpha_INS_JSR
+  "jsr_coroutine", // Alpha_INS_JSR_COROUTINE
+  "lda", // Alpha_INS_LDA
+  "ldah", // Alpha_INS_LDAH
+  "ldbu", // Alpha_INS_LDBU
+  "ldl", // Alpha_INS_LDL
+  "ldl_l", // Alpha_INS_LDL_L
+  "ldq", // Alpha_INS_LDQ
+  "ldq_l", // Alpha_INS_LDQ_L
+  "ldq_u", // Alpha_INS_LDQ_U
+  "lds", // Alpha_INS_LDS
+  "ldt", // Alpha_INS_LDT
+  "ldwu", // Alpha_INS_LDWU
+  "mb", // Alpha_INS_MB
+  "mskbl", // Alpha_INS_MSKBL
+  "msklh", // Alpha_INS_MSKLH
+  "mskll", // Alpha_INS_MSKLL
+  "mskqh", // Alpha_INS_MSKQH
+  "mskql", // Alpha_INS_MSKQL
+  "mskwh", // Alpha_INS_MSKWH
+  "mskwl", // Alpha_INS_MSKWL
+  "mull", // Alpha_INS_MULL
+  "mulq", // Alpha_INS_MULQ
+  "muls/su", // Alpha_INS_MULSsSU
+  "mult/su", // Alpha_INS_MULTsSU
+  "ornot", // Alpha_INS_ORNOT
+  "rc", // Alpha_INS_RC
+  "ret", // Alpha_INS_RET
+  "rpcc", // Alpha_INS_RPCC
+  "rs", // Alpha_INS_RS
+  "s4addl", // Alpha_INS_S4ADDL
+  "s4addq", // Alpha_INS_S4ADDQ
+  "s4subl", // Alpha_INS_S4SUBL
+  "s4subq", // Alpha_INS_S4SUBQ
+  "s8addl", // Alpha_INS_S8ADDL
+  "s8addq", // Alpha_INS_S8ADDQ
+  "s8subl", // Alpha_INS_S8SUBL
+  "s8subq", // Alpha_INS_S8SUBQ
+  "sextb", // Alpha_INS_SEXTB
+  "sextw", // Alpha_INS_SEXTW
+  "sll", // Alpha_INS_SLL
+  "sqrts/su", // Alpha_INS_SQRTSsSU
+  "sqrtt/su", // Alpha_INS_SQRTTsSU
+  "sra", // Alpha_INS_SRA
+  "srl", // Alpha_INS_SRL
+  "stb", // Alpha_INS_STB
+  "stl", // Alpha_INS_STL
+  "stl_c", // Alpha_INS_STL_C
+  "stq", // Alpha_INS_STQ
+  "stq_c", // Alpha_INS_STQ_C
+  "stq_u", // Alpha_INS_STQ_U
+  "sts", // Alpha_INS_STS
+  "stt", // Alpha_INS_STT
+  "stw", // Alpha_INS_STW
+  "subl", // Alpha_INS_SUBL
+  "subq", // Alpha_INS_SUBQ
+  "subs/su", // Alpha_INS_SUBSsSU
+  "subt/su", // Alpha_INS_SUBTsSU
+  "trapb", // Alpha_INS_TRAPB
+  "umulh", // Alpha_INS_UMULH
+  "wh64", // Alpha_INS_WH64
+  "wh64en", // Alpha_INS_WH64EN
+  "wmb", // Alpha_INS_WMB
+  "xor", // Alpha_INS_XOR
+  "zapnot", // Alpha_INS_ZAPNOT

arch/Alpha/AlphaGenCSOpGroup.inc

@@ -0,0 +1,14 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
+/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  Alpha_OP_GROUP_Operand = 0,

arch/Alpha/AlphaGenRegisterInfo.inc

@@ -0,0 +1,281 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
+/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  Alpha_NoRegister,
+  Alpha_F0 = 1,
+  Alpha_F1 = 2,
+  Alpha_F2 = 3,
+  Alpha_F3 = 4,
+  Alpha_F4 = 5,
+  Alpha_F5 = 6,
+  Alpha_F6 = 7,
+  Alpha_F7 = 8,
+  Alpha_F8 = 9,
+  Alpha_F9 = 10,
+  Alpha_F10 = 11,
+  Alpha_F11 = 12,
+  Alpha_F12 = 13,
+  Alpha_F13 = 14,
+  Alpha_F14 = 15,
+  Alpha_F15 = 16,
+  Alpha_F16 = 17,
+  Alpha_F17 = 18,
+  Alpha_F18 = 19,
+  Alpha_F19 = 20,
+  Alpha_F20 = 21,
+  Alpha_F21 = 22,
+  Alpha_F22 = 23,
+  Alpha_F23 = 24,
+  Alpha_F24 = 25,
+  Alpha_F25 = 26,
+  Alpha_F26 = 27,
+  Alpha_F27 = 28,
+  Alpha_F28 = 29,
+  Alpha_F29 = 30,
+  Alpha_F30 = 31,
+  Alpha_F31 = 32,
+  Alpha_R0 = 33,
+  Alpha_R1 = 34,
+  Alpha_R2 = 35,
+  Alpha_R3 = 36,
+  Alpha_R4 = 37,
+  Alpha_R5 = 38,
+  Alpha_R6 = 39,
+  Alpha_R7 = 40,
+  Alpha_R8 = 41,
+  Alpha_R9 = 42,
+  Alpha_R10 = 43,
+  Alpha_R11 = 44,
+  Alpha_R12 = 45,
+  Alpha_R13 = 46,
+  Alpha_R14 = 47,
+  Alpha_R15 = 48,
+  Alpha_R16 = 49,
+  Alpha_R17 = 50,
+  Alpha_R18 = 51,
+  Alpha_R19 = 52,
+  Alpha_R20 = 53,
+  Alpha_R21 = 54,
+  Alpha_R22 = 55,
+  Alpha_R23 = 56,
+  Alpha_R24 = 57,
+  Alpha_R25 = 58,
+  Alpha_R26 = 59,
+  Alpha_R27 = 60,
+  Alpha_R28 = 61,
+  Alpha_R29 = 62,
+  Alpha_R30 = 63,
+  Alpha_R31 = 64,
+  NUM_TARGET_REGS // 65
+};
+
+// Register classes
+
+enum {
+  Alpha_F4RCRegClassID = 0,
+  Alpha_F8RCRegClassID = 1,
+  Alpha_GPRCRegClassID = 2,
+
+};
+#endif // GET_REGINFO_ENUM
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg AlphaRegDiffLists[] = {
+  /* 0 */ 65535, 0,
+};
+
+static const uint16_t AlphaSubRegIdxLists[] = {
+  /* 0 */ 0,
+};
+
+static const MCRegisterDesc AlphaRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0, 0 },
+  { 24, 1, 1, 0, 1, 0 },
+  { 54, 1, 1, 0, 1, 0 },
+  { 76, 1, 1, 0, 1, 0 },
+  { 98, 1, 1, 0, 1, 0 },
+  { 120, 1, 1, 0, 1, 0 },
+  { 142, 1, 1, 0, 1, 0 },
+  { 164, 1, 1, 0, 1, 0 },
+  { 186, 1, 1, 0, 1, 0 },
+  { 208, 1, 1, 0, 1, 0 },
+  { 230, 1, 1, 0, 1, 0 },
+  { 0, 1, 1, 0, 1, 0 },
+  { 30, 1, 1, 0, 1, 0 },
+  { 60, 1, 1, 0, 1, 0 },
+  { 82, 1, 1, 0, 1, 0 },
+  { 104, 1, 1, 0, 1, 0 },
+  { 126, 1, 1, 0, 1, 0 },
+  { 148, 1, 1, 0, 1, 0 },
+  { 170, 1, 1, 0, 1, 0 },
+  { 192, 1, 1, 0, 1, 0 },
+  { 214, 1, 1, 0, 1, 0 },
+  { 8, 1, 1, 0, 1, 0 },
+  { 38, 1, 1, 0, 1, 0 },
+  { 68, 1, 1, 0, 1, 0 },
+  { 90, 1, 1, 0, 1, 0 },
+  { 112, 1, 1, 0, 1, 0 },
+  { 134, 1, 1, 0, 1, 0 },
+  { 156, 1, 1, 0, 1, 0 },
+  { 178, 1, 1, 0, 1, 0 },
+  { 200, 1, 1, 0, 1, 0 },
+  { 222, 1, 1, 0, 1, 0 },
+  { 16, 1, 1, 0, 1, 0 },
+  { 46, 1, 1, 0, 1, 0 },
+  { 27, 1, 1, 0, 1, 0 },
+  { 57, 1, 1, 0, 1, 0 },
+  { 79, 1, 1, 0, 1, 0 },
+  { 101, 1, 1, 0, 1, 0 },
+  { 123, 1, 1, 0, 1, 0 },
+  { 145, 1, 1, 0, 1, 0 },
+  { 167, 1, 1, 0, 1, 0 },
+  { 189, 1, 1, 0, 1, 0 },
+  { 211, 1, 1, 0, 1, 0 },
+  { 233, 1, 1, 0, 1, 0 },
+  { 4, 1, 1, 0, 1, 0 },
+  { 34, 1, 1, 0, 1, 0 },
+  { 64, 1, 1, 0, 1, 0 },
+  { 86, 1, 1, 0, 1, 0 },
+  { 108, 1, 1, 0, 1, 0 },
+  { 130, 1, 1, 0, 1, 0 },
+  { 152, 1, 1, 0, 1, 0 },
+  { 174, 1, 1, 0, 1, 0 },
+  { 196, 1, 1, 0, 1, 0 },
+  { 218, 1, 1, 0, 1, 0 },
+  { 12, 1, 1, 0, 1, 0 },
+  { 42, 1, 1, 0, 1, 0 },
+  { 72, 1, 1, 0, 1, 0 },
+  { 94, 1, 1, 0, 1, 0 },
+  { 116, 1, 1, 0, 1, 0 },
+  { 138, 1, 1, 0, 1, 0 },
+  { 160, 1, 1, 0, 1, 0 },
+  { 182, 1, 1, 0, 1, 0 },
+  { 204, 1, 1, 0, 1, 0 },
+  { 226, 1, 1, 0, 1, 0 },
+  { 20, 1, 1, 0, 1, 0 },
+  { 50, 1, 1, 0, 1, 0 },
+};
+
+  // F4RC Register Class...
+  static const MCPhysReg F4RC[] = {
+    Alpha_F0, Alpha_F1, Alpha_F10, Alpha_F11, Alpha_F12, Alpha_F13, Alpha_F14, Alpha_F15, Alpha_F16, Alpha_F17, Alpha_F18, Alpha_F19, Alpha_F20, Alpha_F21, Alpha_F22, Alpha_F23, Alpha_F24, Alpha_F25, Alpha_F26, Alpha_F27, Alpha_F28, Alpha_F29, Alpha_F30, Alpha_F2, Alpha_F3, Alpha_F4, Alpha_F5, Alpha_F6, Alpha_F7, Alpha_F8, Alpha_F9, Alpha_F31, 
+  };
+
+  // F4RC Bit set.
+  static const uint8_t F4RCBits[] = {
+    0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // F8RC Register Class...
+  static const MCPhysReg F8RC[] = {
+    Alpha_F0, Alpha_F1, Alpha_F10, Alpha_F11, Alpha_F12, Alpha_F13, Alpha_F14, Alpha_F15, Alpha_F16, Alpha_F17, Alpha_F18, Alpha_F19, Alpha_F20, Alpha_F21, Alpha_F22, Alpha_F23, Alpha_F24, Alpha_F25, Alpha_F26, Alpha_F27, Alpha_F28, Alpha_F29, Alpha_F30, Alpha_F2, Alpha_F3, Alpha_F4, Alpha_F5, Alpha_F6, Alpha_F7, Alpha_F8, Alpha_F9, Alpha_F31, 
+  };
+
+  // F8RC Bit set.
+  static const uint8_t F8RCBits[] = {
+    0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // GPRC Register Class...
+  static const MCPhysReg GPRC[] = {
+    Alpha_R0, Alpha_R1, Alpha_R2, Alpha_R3, Alpha_R4, Alpha_R5, Alpha_R6, Alpha_R7, Alpha_R8, Alpha_R16, Alpha_R17, Alpha_R18, Alpha_R19, Alpha_R20, Alpha_R21, Alpha_R22, Alpha_R23, Alpha_R24, Alpha_R25, Alpha_R28, Alpha_R27, Alpha_R26, Alpha_R29, Alpha_R9, Alpha_R10, Alpha_R11, Alpha_R12, Alpha_R13, Alpha_R14, Alpha_R15, Alpha_R30, Alpha_R31, 
+  };
+
+  // GPRC Bit set.
+  static const uint8_t GPRCBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+static const MCRegisterClass AlphaMCRegisterClasses[] = {
+  { F4RC, F4RCBits, sizeof(F4RCBits) },
+  { F8RC, F8RCBits, sizeof(F8RCBits) },
+  { GPRC, GPRCBits, sizeof(GPRCBits) },
+};
+
+static const uint16_t AlphaRegEncodingTable[] = {
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+};
+#endif // GET_REGINFO_MC_DESC
+
+
+

arch/Alpha/AlphaGenSubtargetInfo.inc

@@ -0,0 +1,24 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
+/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  Alpha_FeatureCIX = 0,
+  Alpha_NumSubtargetFeatures = 1
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+

arch/Alpha/AlphaInstPrinter.c

@@ -0,0 +1,90 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifdef CAPSTONE_HAS_ALPHA
+
+#include <platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../utils.h"
+#include "../../Mapping.h"
+#include "../../MCInstPrinter.h"
+
+#include "AlphaLinkage.h"
+#include "AlphaMapping.h"
+
+static const char *getRegisterName(unsigned RegNo);
+
+static void printInstruction(MCInst *, uint64_t, SStream *);
+static void printOperand(MCInst *MI, int OpNum, SStream *O);
+static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
+
+#define GET_INSTRINFO_ENUM
+
+#include "AlphaGenInstrInfo.inc"
+
+#define GET_REGINFO_ENUM
+
+#include "AlphaGenRegisterInfo.inc"
+
+static void printOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	if (OpNum >= MI->size)
+		return;
+
+	Alpha_add_cs_detail(MI, OpNum);
+	
+	MCOperand *Op;
+	Op = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isReg(Op)) {
+		unsigned reg = MCOperand_getReg(Op);
+		SStream_concat(O, "%s", getRegisterName(reg));
+	} else if (MCOperand_isImm(Op)) {
+		int64_t Imm = MCOperand_getImm(Op);
+		if (Imm >= 0) {
+			if (Imm > HEX_THRESHOLD)
+				SStream_concat(O, "0x%" PRIx64, Imm);
+			else
+				SStream_concat(O, "%" PRIu64, Imm);
+		} else {
+			if (Imm < -HEX_THRESHOLD)
+				SStream_concat(O, "-0x%" PRIx64, -Imm);
+			else
+				SStream_concat(O, "-%" PRIu64, -Imm);
+		}
+	}
+}
+
+static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) 
+{
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+
+	uint64_t Imm = MCOperand_getImm(Op);
+	uint64_t Target = Address + 4 + (int16_t) (Imm << 2);
+
+	Alpha_set_detail_op_imm(MI, OpNum, ALPHA_OP_IMM, Target);
+	printUInt64(O, Target);
+}
+
+#define PRINT_ALIAS_INSTR
+
+#include "AlphaGenAsmWriter.inc"
+
+const char *Alpha_LLVM_getRegisterName(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return getRegisterName(id);
+#else
+	return NULL;
+#endif
+}
+
+void Alpha_LLVM_printInstruction(MCInst *MI, SStream *O, void *Info)
+{
+	printAliasInstr(MI, MI->address, O);
+	printInstruction(MI, MI->address, O);
+}
+
+#endif

arch/Alpha/AlphaLinkage.h

@@ -0,0 +1,21 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifndef CS_ALPHA_LINKAGE_H
+#define CS_ALPHA_LINKAGE_H
+
+// Function defintions to call static LLVM functions.
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "AlphaMapping.h"
+
+const char *Alpha_LLVM_getRegisterName(csh handle, unsigned int id);
+void Alpha_LLVM_printInstruction(MCInst *MI, SStream *O, void *Info);
+DecodeStatus Alpha_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+									   size_t ByteLen, MCInst *MI,
+									   uint16_t *Size, uint64_t Address,
+									   void *Info);
+
+#endif // CS_ALPHA_LINKAGE_H

arch/Alpha/AlphaMapping.c

@@ -0,0 +1,182 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifdef CAPSTONE_HAS_ALPHA
+
+#include <stdio.h> // debug
+#include <string.h>
+
+#include "../../Mapping.h"
+#include "../../cs_priv.h"
+#include "../../cs_simple_types.h"
+#include "../../utils.h"
+
+#include "AlphaLinkage.h"
+#include "AlphaMapping.h"
+#include "./AlphaDisassembler.h"
+
+#define GET_INSTRINFO_ENUM
+
+#include "AlphaGenInstrInfo.inc"
+
+static insn_map insns[] = {
+#include "AlphaGenCSMappingInsn.inc"
+};
+
+const map_insn_ops insn_operands[] = {
+#include "AlphaGenCSMappingInsnOp.inc"
+};
+
+void Alpha_init_cs_detail(MCInst *MI)
+{
+	if (detail_is_set(MI)) {
+		memset(get_detail(MI), 0,
+			   offsetof(cs_detail, alpha) + sizeof(cs_alpha));
+	}
+}
+
+void Alpha_add_cs_detail(MCInst *MI, unsigned OpNum)
+{
+	if (!detail_is_set(MI))
+		return;
+
+	cs_op_type op_type = map_get_op_type(MI, OpNum);
+	if (op_type == CS_OP_IMM)
+		Alpha_set_detail_op_imm(MI, OpNum, ALPHA_OP_IMM,
+								MCInst_getOpVal(MI, OpNum));
+	else if (op_type == CS_OP_REG)
+		Alpha_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum));
+	else
+		assert(0 && "Op type not handled.");
+}
+
+void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType,
+							 int64_t Imm)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
+	assert(map_get_op_type(MI, OpNum) == CS_OP_IMM);
+	assert(ImmType == ALPHA_OP_IMM);
+
+	Alpha_get_detail_op(MI, 0)->type = ImmType;
+	Alpha_get_detail_op(MI, 0)->imm = Imm;
+	Alpha_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	Alpha_inc_op_count(MI);
+}
+
+void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
+	assert(map_get_op_type(MI, OpNum) == CS_OP_REG);
+
+	Alpha_get_detail_op(MI, 0)->type = ALPHA_OP_REG;
+	Alpha_get_detail_op(MI, 0)->reg = Reg;
+	Alpha_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	Alpha_inc_op_count(MI);
+}
+
+// given internal insn id, return public instruction info
+void Alpha_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	unsigned short i;
+
+	i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
+	if (i == 0) { return; }
+	insn->id = insns[i].mapid;
+
+	if (insn->detail) {
+#ifndef CAPSTONE_DIET
+		memcpy(insn->detail->regs_read, insns[i].regs_use,
+				sizeof(insns[i].regs_use));
+		insn->detail->regs_read_count =
+			(uint8_t)count_positive(insns[i].regs_use);
+
+		memcpy(insn->detail->regs_write, insns[i].regs_mod,
+				sizeof(insns[i].regs_mod));
+		insn->detail->regs_write_count =
+			(uint8_t)count_positive(insns[i].regs_mod);
+
+		memcpy(insn->detail->groups, insns[i].groups,
+				sizeof(insns[i].groups));
+		insn->detail->groups_count =
+			(uint8_t)count_positive8(insns[i].groups);
+#endif
+	}
+}
+
+#ifndef CAPSTONE_DIET
+
+static const char *insn_names[] = {
+#include "AlphaGenCSMappingInsnName.inc"
+};
+
+// special alias insn
+// static name_map alias_insn_names[] = {{0, NULL}};
+#endif
+
+const char *Alpha_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= ALPHA_INS_ENDING)
+		return NULL;
+
+	if (id < ARR_SIZE(insn_names))
+		return insn_names[id];
+
+	return NULL;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+	{Alpha_GRP_INVALID, NULL},
+	{Alpha_GRP_CALL, "call"},
+	{Alpha_GRP_JUMP, "jump"},
+	{Alpha_GRP_BRANCH_RELATIVE, "branch_relative"},
+};
+#endif
+
+const char *Alpha_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+const char *Alpha_getRegisterName(csh handle, unsigned int id)
+{
+	return Alpha_LLVM_getRegisterName(handle, id);
+}
+
+void Alpha_printInst(MCInst *MI, SStream *O, void *Info)
+{
+	return Alpha_LLVM_printInstruction(MI, O, Info);
+}
+
+void Alpha_set_instr_map_data(MCInst *MI) 
+{
+	map_cs_id(MI, insns, ARR_SIZE(insns));
+	map_implicit_reads(MI, insns);
+	map_implicit_writes(MI, insns);
+	map_groups(MI, insns);
+}
+
+bool Alpha_getInstruction(csh handle, const uint8_t *code,
+								  size_t code_len, MCInst *instr,
+								  uint16_t *size, uint64_t address, void *info)
+{
+	Alpha_init_cs_detail(instr);
+	bool Result = Alpha_LLVM_getInstruction(handle, code, code_len, instr, size,
+									 address, info);
+	Alpha_set_instr_map_data(instr);
+	return Result;
+}
+
+#endif

arch/Alpha/AlphaMapping.h

@@ -0,0 +1,35 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifndef CS_ALPHA_MAP_H
+#define CS_ALPHA_MAP_H
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../SStream.h"
+#include <capstone/capstone.h>
+
+// unsigned int Alpha_map_insn_id(cs_struct *h, unsigned int id);
+
+// given internal insn id, return public instruction info
+void Alpha_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *Alpha_insn_name(csh handle, unsigned int id);
+
+const char *Alpha_group_name(csh handle, unsigned int id);
+
+void Alpha_printInst(MCInst *MI, SStream *O, void *Info);
+
+const char *Alpha_getRegisterName(csh handle, unsigned int id);
+bool Alpha_getInstruction(csh handle, const uint8_t *code,
+								  size_t code_len, MCInst *instr,
+								  uint16_t *size, uint64_t address, void *info);
+void Alpha_init_cs_detail(MCInst *MI);
+void Alpha_add_cs_detail(MCInst *MI, unsigned OpNum);
+
+void Alpha_set_instr_map_data(MCInst *MI);
+void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType,
+							 int64_t Imm);
+void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg);
+
+#endif

arch/Alpha/AlphaModule.c

@@ -0,0 +1,41 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifdef CAPSTONE_HAS_ALPHA
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "AlphaDisassembler.h"
+#include "AlphaMapping.h"
+#include "AlphaModule.h"
+
+cs_err ALPHA_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	Alpha_init(mri);
+	ud->printer = Alpha_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = Alpha_getInstruction;
+	ud->post_printer = NULL;
+
+	ud->reg_name = Alpha_getRegisterName;
+	ud->insn_id = Alpha_get_insn_id;
+	ud->insn_name = Alpha_insn_name;
+	ud->group_name = Alpha_group_name;
+
+	return CS_ERR_OK;
+}
+
+cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_SYNTAX)
+		handle->syntax = (int)value;
+
+	return CS_ERR_OK;
+}
+
+#endif

arch/Alpha/AlphaModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifndef CAPSTONE_ALPHAMODULE_H
+#define CAPSTONE_ALPHAMODULE_H
+
+#include "../../utils.h"
+
+cs_err ALPHA_global_init(cs_struct *ud);
+cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif // CAPSTONE_ALPHAMODULE_H

bindings/Makefile

@@ -23,6 +23,7 @@ TEST_M680X = $(TMPDIR)/test_m680x
 TEST_TRICORE = $(TMPDIR)/test_tricore
 TEST_SH = $(TMPDIR)/test_sh
 TEST_TMS320C64X = $(TMPDIR)/test_tms320c64x
+TEST_ALPHA = $(TMPDIR)/test_alpha
 
 PYTHON3 ?= python3
 
@@ -64,6 +65,7 @@ expected:
 	../tests/test_sh > $(TEST_SH)_e
 	../tests/test_tricore > $(TEST_TRICORE)_e
 	../tests/test_tms320c64x > $(TEST_TMS320C64X)_e
+	../tests/test_alpha > $(TEST_ALPHA)_e
 
 python: FORCE
 	cd python && $(MAKE)
@@ -88,6 +90,7 @@ python: FORCE
 	$(PYTHON3) python/test_sh.py > $(TEST_SH)_o
 	$(PYTHON3) python/test_tricore.py > $(TEST_TRICORE)_o
 	$(PYTHON3) python/test_tms320c64x.py > $(TEST_TMS320C64X)_o
+	$(PYTHON3) python/test_alpha.py > $(TEST_ALPHA)_o
 	$(MAKE) test_diff
 
 java: FORCE
@@ -127,6 +130,7 @@ test_diff: FORCE
 	$(DIFF) $(TEST_SH)_e $(TEST_SH)_o
 	$(DIFF) $(TEST_TRICORE)_e $(TEST_TRICORE)_o
 	$(DIFF) $(TEST_TMS320C64X)_e $(TEST_TMS320C64X)_o
+	$(DIFF) $(TEST_ALPHA)_e $(TEST_ALPHA)_o
 
 clean:
 	rm -rf $(TMPDIR)

bindings/const_generator.py

@@ -5,7 +5,7 @@ import sys, re
 
 INCL_DIR = '../include/capstone/'
 
-include = [ 'arm.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h' ]
+include = [ 'arm.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h', 'alpha.h' ]
 
 template = {
     'java': {
@@ -53,6 +53,7 @@ template = {
             'riscv.h': 'riscv',
             'sh.h': 'sh',
             'tricore.h': ['TRICORE', 'TriCore'],
+            'alpha.h': ['ALPHA', 'Alpha'],
             'comment_open': '#',
             'comment_close': '',
         },

bindings/python/Makefile

@@ -72,7 +72,7 @@ TESTS = test_basic.py test_detail.py test_arm.py test_aarch64.py test_m68k.py te
 TESTS += test_ppc.py test_sparc.py test_systemz.py test_x86.py test_xcore.py test_tms320c64x.py
 TESTS += test_m680x.py test_skipdata.py test_mos65xx.py test_bpf.py test_riscv.py
 TESTS += test_evm.py test_tricore.py test_wasm.py test_sh.py
-TESTS += test_lite.py test_iter.py test_customized_mnem.py
+TESTS += test_lite.py test_iter.py test_customized_mnem.py test_alpha.py
 
 check:
 	@for t in $(TESTS); do \

bindings/python/capstone/__init__.py

@@ -41,6 +41,7 @@ __all__ = [
     'CS_ARCH_RISCV',
     'CS_ARCH_SH',
     'CS_ARCH_TRICORE',
+    'CS_ARCH_ALPHA',
     'CS_ARCH_ALL',
 
     'CS_MODE_LITTLE_ENDIAN',
@@ -217,7 +218,8 @@ CS_ARCH_BPF = 14
 CS_ARCH_RISCV = 15
 CS_ARCH_SH = 16
 CS_ARCH_TRICORE = 17
-CS_ARCH_MAX = 18
+CS_ARCH_ALPHA = 18
+CS_ARCH_MAX = 19
 CS_ARCH_ALL = 0xFFFF
 
 # disasm mode
@@ -441,7 +443,7 @@ def copy_ctypes_list(src):
     return [copy_ctypes(n) for n in src]
 
 # Weird import placement because these modules are needed by the below code but need the above functions
-from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore
+from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore, alpha
 
 class _cs_arch(ctypes.Union):
     _fields_ = (
@@ -463,13 +465,14 @@ class _cs_arch(ctypes.Union):
         ('riscv', riscv.CsRISCV),
         ('sh', sh.CsSH),
         ('tricore', tricore.CsTriCore),
+        ('alpha', alpha.CsAlpha),
     )
 
 class _cs_detail(ctypes.Structure):
     _fields_ = (
         ('regs_read', ctypes.c_uint16 * 20),
         ('regs_read_count', ctypes.c_ubyte),
-        ('regs_write', ctypes.c_uint16 * 20),
+        ('regs_write', ctypes.c_uint16 * 47),
         ('regs_write_count', ctypes.c_ubyte),
         ('groups', ctypes.c_ubyte * 8),
         ('groups_count', ctypes.c_ubyte),
@@ -812,6 +815,8 @@ class CsInsn(object):
             (self.sh_insn, self.sh_size, self.operands) = sh.get_arch_info(self._raw.detail.contents.arch.sh)
         elif arch == CS_ARCH_TRICORE:
             (self.update_flags, self.operands) = tricore.get_arch_info(self._raw.detail.contents.arch.tricore)
+        elif arch == CS_ARCH_ALPHA:
+            (self.operands) = alpha.get_arch_info(self._raw.detail.contents.arch.alpha)
 
 
     def __getattr__(self, name):
@@ -1304,7 +1309,7 @@ def debug():
         "sysz": CS_ARCH_SYSZ, 'xcore': CS_ARCH_XCORE, "tms320c64x": CS_ARCH_TMS320C64X,
         "m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,
         'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE,
-        'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH,
+        'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA,
     }
 
     all_archs = ""

bindings/python/capstone/alpha.py

@@ -0,0 +1,43 @@
+import ctypes
+from . import copy_ctypes_list
+from .alpha_const import *
+
+class AlphaOpMem(ctypes.Structure):
+    _fields_ = (
+        ('base', ctypes.c_uint8),
+        ('disp', ctypes.c_int32),
+    )
+
+
+class AlphaOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int32),
+    )
+
+
+class AlphaOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', AlphaOpValue),
+        ('access', ctypes.c_uint8)
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+
+# Instruction structure
+class CsAlpha(ctypes.Structure):
+    _fields_ = (
+        ('op_count', ctypes.c_uint8),
+        ('operands', AlphaOp * 3)
+    )
+
+def get_arch_info(a):
+    return (copy_ctypes_list(a.operands[:a.op_count]))

bindings/python/capstone/alpha_const.py

@@ -0,0 +1,239 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [alpha_const.py]
+
+# Operand type for instruction's operands
+ALPHA_OP_INVALID = CS_OP_INVALID
+ALPHA_OP_REG = CS_OP_REG
+ALPHA_OP_IMM = CS_OP_IMM
+
+# Alpha registers
+
+Alpha_REG_INVALID = 0
+Alpha_REG_F0 = 1
+Alpha_REG_F1 = 2
+Alpha_REG_F2 = 3
+Alpha_REG_F3 = 4
+Alpha_REG_F4 = 5
+Alpha_REG_F5 = 6
+Alpha_REG_F6 = 7
+Alpha_REG_F7 = 8
+Alpha_REG_F8 = 9
+Alpha_REG_F9 = 10
+Alpha_REG_F10 = 11
+Alpha_REG_F11 = 12
+Alpha_REG_F12 = 13
+Alpha_REG_F13 = 14
+Alpha_REG_F14 = 15
+Alpha_REG_F15 = 16
+Alpha_REG_F16 = 17
+Alpha_REG_F17 = 18
+Alpha_REG_F18 = 19
+Alpha_REG_F19 = 20
+Alpha_REG_F20 = 21
+Alpha_REG_F21 = 22
+Alpha_REG_F22 = 23
+Alpha_REG_F23 = 24
+Alpha_REG_F24 = 25
+Alpha_REG_F25 = 26
+Alpha_REG_F26 = 27
+Alpha_REG_F27 = 28
+Alpha_REG_F28 = 29
+Alpha_REG_F29 = 30
+Alpha_REG_F30 = 31
+Alpha_REG_F31 = 32
+Alpha_REG_R0 = 33
+Alpha_REG_R1 = 34
+Alpha_REG_R2 = 35
+Alpha_REG_R3 = 36
+Alpha_REG_R4 = 37
+Alpha_REG_R5 = 38
+Alpha_REG_R6 = 39
+Alpha_REG_R7 = 40
+Alpha_REG_R8 = 41
+Alpha_REG_R9 = 42
+Alpha_REG_R10 = 43
+Alpha_REG_R11 = 44
+Alpha_REG_R12 = 45
+Alpha_REG_R13 = 46
+Alpha_REG_R14 = 47
+Alpha_REG_R15 = 48
+Alpha_REG_R16 = 49
+Alpha_REG_R17 = 50
+Alpha_REG_R18 = 51
+Alpha_REG_R19 = 52
+Alpha_REG_R20 = 53
+Alpha_REG_R21 = 54
+Alpha_REG_R22 = 55
+Alpha_REG_R23 = 56
+Alpha_REG_R24 = 57
+Alpha_REG_R25 = 58
+Alpha_REG_R26 = 59
+Alpha_REG_R27 = 60
+Alpha_REG_R28 = 61
+Alpha_REG_R29 = 62
+Alpha_REG_R30 = 63
+Alpha_REG_R31 = 64
+Alpha_REG_ENDING = 65
+
+# Alpha instruction
+Alpha_INS_INVALID = 66
+Alpha_INS_ADDL = 67
+Alpha_INS_ADDQ = 68
+Alpha_INS_ADDSsSU = 69
+Alpha_INS_ADDTsSU = 70
+Alpha_INS_AND = 71
+Alpha_INS_BEQ = 72
+Alpha_INS_BGE = 73
+Alpha_INS_BGT = 74
+Alpha_INS_BIC = 75
+Alpha_INS_BIS = 76
+Alpha_INS_BLBC = 77
+Alpha_INS_BLBS = 78
+Alpha_INS_BLE = 79
+Alpha_INS_BLT = 80
+Alpha_INS_BNE = 81
+Alpha_INS_BR = 82
+Alpha_INS_BSR = 83
+Alpha_INS_CMOVEQ = 84
+Alpha_INS_CMOVGE = 85
+Alpha_INS_CMOVGT = 86
+Alpha_INS_CMOVLBC = 87
+Alpha_INS_CMOVLBS = 88
+Alpha_INS_CMOVLE = 89
+Alpha_INS_CMOVLT = 90
+Alpha_INS_CMOVNE = 91
+Alpha_INS_CMPBGE = 92
+Alpha_INS_CMPEQ = 93
+Alpha_INS_CMPLE = 94
+Alpha_INS_CMPLT = 95
+Alpha_INS_CMPTEQsSU = 96
+Alpha_INS_CMPTLEsSU = 97
+Alpha_INS_CMPTLTsSU = 98
+Alpha_INS_CMPTUNsSU = 99
+Alpha_INS_CMPULE = 100
+Alpha_INS_CMPULT = 101
+Alpha_INS_COND_BRANCH = 102
+Alpha_INS_CPYSE = 103
+Alpha_INS_CPYSN = 104
+Alpha_INS_CPYS = 105
+Alpha_INS_CTLZ = 106
+Alpha_INS_CTPOP = 107
+Alpha_INS_CTTZ = 108
+Alpha_INS_CVTQSsSUI = 109
+Alpha_INS_CVTQTsSUI = 110
+Alpha_INS_CVTSTsS = 111
+Alpha_INS_CVTTQsSVC = 112
+Alpha_INS_CVTTSsSUI = 113
+Alpha_INS_DIVSsSU = 114
+Alpha_INS_DIVTsSU = 115
+Alpha_INS_ECB = 116
+Alpha_INS_EQV = 117
+Alpha_INS_EXCB = 118
+Alpha_INS_EXTBL = 119
+Alpha_INS_EXTLH = 120
+Alpha_INS_EXTLL = 121
+Alpha_INS_EXTQH = 122
+Alpha_INS_EXTQL = 123
+Alpha_INS_EXTWH = 124
+Alpha_INS_EXTWL = 125
+Alpha_INS_FBEQ = 126
+Alpha_INS_FBGE = 127
+Alpha_INS_FBGT = 128
+Alpha_INS_FBLE = 129
+Alpha_INS_FBLT = 130
+Alpha_INS_FBNE = 131
+Alpha_INS_FCMOVEQ = 132
+Alpha_INS_FCMOVGE = 133
+Alpha_INS_FCMOVGT = 134
+Alpha_INS_FCMOVLE = 135
+Alpha_INS_FCMOVLT = 136
+Alpha_INS_FCMOVNE = 137
+Alpha_INS_FETCH = 138
+Alpha_INS_FETCH_M = 139
+Alpha_INS_FTOIS = 140
+Alpha_INS_FTOIT = 141
+Alpha_INS_INSBL = 142
+Alpha_INS_INSLH = 143
+Alpha_INS_INSLL = 144
+Alpha_INS_INSQH = 145
+Alpha_INS_INSQL = 146
+Alpha_INS_INSWH = 147
+Alpha_INS_INSWL = 148
+Alpha_INS_ITOFS = 149
+Alpha_INS_ITOFT = 150
+Alpha_INS_JMP = 151
+Alpha_INS_JSR = 152
+Alpha_INS_JSR_COROUTINE = 153
+Alpha_INS_LDA = 154
+Alpha_INS_LDAH = 155
+Alpha_INS_LDBU = 156
+Alpha_INS_LDL = 157
+Alpha_INS_LDL_L = 158
+Alpha_INS_LDQ = 159
+Alpha_INS_LDQ_L = 160
+Alpha_INS_LDQ_U = 161
+Alpha_INS_LDS = 162
+Alpha_INS_LDT = 163
+Alpha_INS_LDWU = 164
+Alpha_INS_MB = 165
+Alpha_INS_MSKBL = 166
+Alpha_INS_MSKLH = 167
+Alpha_INS_MSKLL = 168
+Alpha_INS_MSKQH = 169
+Alpha_INS_MSKQL = 170
+Alpha_INS_MSKWH = 171
+Alpha_INS_MSKWL = 172
+Alpha_INS_MULL = 173
+Alpha_INS_MULQ = 174
+Alpha_INS_MULSsSU = 175
+Alpha_INS_MULTsSU = 176
+Alpha_INS_ORNOT = 177
+Alpha_INS_RC = 178
+Alpha_INS_RET = 179
+Alpha_INS_RPCC = 180
+Alpha_INS_RS = 181
+Alpha_INS_S4ADDL = 182
+Alpha_INS_S4ADDQ = 183
+Alpha_INS_S4SUBL = 184
+Alpha_INS_S4SUBQ = 185
+Alpha_INS_S8ADDL = 186
+Alpha_INS_S8ADDQ = 187
+Alpha_INS_S8SUBL = 188
+Alpha_INS_S8SUBQ = 189
+Alpha_INS_SEXTB = 190
+Alpha_INS_SEXTW = 191
+Alpha_INS_SLL = 192
+Alpha_INS_SQRTSsSU = 193
+Alpha_INS_SQRTTsSU = 194
+Alpha_INS_SRA = 195
+Alpha_INS_SRL = 196
+Alpha_INS_STB = 197
+Alpha_INS_STL = 198
+Alpha_INS_STL_C = 199
+Alpha_INS_STQ = 200
+Alpha_INS_STQ_C = 201
+Alpha_INS_STQ_U = 202
+Alpha_INS_STS = 203
+Alpha_INS_STT = 204
+Alpha_INS_STW = 205
+Alpha_INS_SUBL = 206
+Alpha_INS_SUBQ = 207
+Alpha_INS_SUBSsSU = 208
+Alpha_INS_SUBTsSU = 209
+Alpha_INS_TRAPB = 210
+Alpha_INS_UMULH = 211
+Alpha_INS_WH64 = 212
+Alpha_INS_WH64EN = 213
+Alpha_INS_WMB = 214
+Alpha_INS_XOR = 215
+Alpha_INS_ZAPNOT = 216
+ALPHA_INS_ENDING = 217
+
+# Group of Alpha instructions
+Alpha_GRP_INVALID = 218
+
+# Generic groups
+Alpha_GRP_CALL = 219
+Alpha_GRP_JUMP = 220
+Alpha_GRP_BRANCH_RELATIVE = 221
+Alpha_GRP_ENDING = 222

bindings/python/setup_cython.py

@@ -69,7 +69,7 @@ else:
 compile_args = ['-O3', '-fomit-frame-pointer', '-I' + HEADERS_DIR]
 link_args = ['-L' + LIBS_DIR]
 
-ext_module_names = ['arm', 'arm_const', 'aarch64', 'aarch64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const', 'mos65xx', 'mos65xx_const', 'wasm', 'wasm_const', 'bpf', 'bpf_const', 'riscv', 'riscv_const', 'sh', 'sh_const', 'tricore', 'tricore_const' ]
+ext_module_names = ['arm', 'arm_const', 'aarch64', 'aarch64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const', 'mos65xx', 'mos65xx_const', 'wasm', 'wasm_const', 'bpf', 'bpf_const', 'riscv', 'riscv_const', 'sh', 'sh_const', 'tricore', 'tricore_const', 'alpha', 'alpha_const' ]
 
 ext_modules = [Extension("capstone.ccapstone",
                          ["pyx/ccapstone.pyx"],

bindings/python/test_all.py

@@ -2,7 +2,7 @@
 
 import test_basic, test_arm, test_aarch64, test_detail, test_lite, test_m68k, test_mips, \
     test_ppc, test_x86, test_skipdata, test_sparc, test_systemz, test_tms320c64x, test_customized_mnem, \
-    test_m680x, test_mos65xx, test_xcore, test_riscv
+    test_m680x, test_mos65xx, test_xcore, test_riscv, test_alpha
 
 test_basic.test_class()
 test_arm.test_class()
@@ -22,3 +22,4 @@ test_skipdata.test_class()
 test_customized_mnem.test()
 test_xcore.test_class()
 test_riscv.test_class()
+test_alpha.test_class()

bindings/python/test_alpha.py

@@ -0,0 +1,56 @@
+#!/usr/bin/env python3
+
+# Capstone Python bindings, by Dmitry Sibirtsev <sibirtsev_dl@gmail.com>
+
+from __future__ import print_function
+from capstone import *
+from capstone.alpha import *
+from xprint import to_x, to_hex
+
+ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7'
+
+all_tests = (
+    (CS_ARCH_ALPHA, 0, ALPHA_CODE, "Alpha"),
+)
+
+
+def print_insn_detail(insn):
+    # print address, mnemonic and operands
+    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
+
+    # "data" instruction generated by SKIPDATA option has no detail
+    if insn.id == 0:
+        return
+
+    if len(insn.operands) > 0:
+        print("\top_count: %u" % len(insn.operands))
+        c = 0
+        for i in insn.operands:
+            if i.type == ALPHA_OP_REG:
+                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
+            if i.type == ALPHA_OP_IMM:
+                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
+            c += 1
+
+
+# ## Test class Cs
+def test_class():
+    for (arch, mode, code, comment) in all_tests:
+        print("*" * 16)
+        print("Platform: %s" % comment)
+        print("Code: %s" % to_hex(code))
+        print("Disasm:")
+
+        try:
+            md = Cs(arch, mode)
+            md.detail = True
+            for insn in md.disasm(code, 0x1000):
+                print_insn_detail(insn)
+                print()
+            print("0x%x:\n" % (insn.address + insn.size))
+        except CsError as e:
+            print("ERROR: %s" % e)
+
+
+if __name__ == '__main__':
+    test_class()

bindings/python/test_basic.py

@@ -40,6 +40,7 @@ MOS65XX_CODE = b"\x0d\x34\x12\x00\x81\x65\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x4
 EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00"
 RISCV_CODE32 = b"\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00"
 RISCV_CODE64 = b"\x13\x04\xa8\x7a"
+ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7'
 
 
 all_tests = (
@@ -75,6 +76,7 @@ all_tests = (
         (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF", None),
         (CS_ARCH_RISCV, CS_MODE_RISCV32, RISCV_CODE32, "RISCV32", None),
         (CS_ARCH_RISCV, CS_MODE_RISCV64, RISCV_CODE64, "RISCV64", None),
+        (CS_ARCH_ALPHA, 0, ALPHA_CODE, "Alpha", None),
 )
 
 # ## Test cs_disasm_quick()

bindings/python/test_detail.py

@@ -30,6 +30,7 @@ M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x
 M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
 MOS65XX_CODE = b"\x0A\x00\xFE\x34\x12\xD0\xFF\xEA\x19\x56\x34\x46\x80"
 EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00"
+ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7'
 
 all_tests = (
         (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
@@ -57,6 +58,7 @@ all_tests = (
         (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
         (CS_ARCH_MOS65XX, 0, MOS65XX_CODE, "MOS65XX", None),
         (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF", None),
+        (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha", None),
 )
 
 

bindings/python/test_iter.py

@@ -28,6 +28,8 @@ SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x
 XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
 M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
 M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
+ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7'
+
 
 all_tests = (
         (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
@@ -55,6 +57,7 @@ all_tests = (
         (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
         (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None),
         (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
+        (CS_ARCH_ALPHA, 0, ALPHA_CODE, "Alpha", None),
         )
 
 # ## Test class Cs

config.mk

@@ -4,7 +4,7 @@
 ################################################################################
 # Specify which archs you want to compile in. By default, we build all archs.
 
-CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore
+CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore alpha
 
 
 ################################################################################

cs.c

@@ -70,6 +70,7 @@
 #include "arch/BPF/BPFModule.h"
 #include "arch/SH/SHModule.h"
 #include "arch/TriCore/TriCoreModule.h"
+#include "arch/Alpha/AlphaModule.h"
 
 static const struct {
 	// constructor initialization
@@ -255,6 +256,15 @@ static const struct {
 #else
 	{ NULL, NULL, 0 },
 #endif
+#ifdef CAPSTONE_HAS_ALPHA
+	{
+		ALPHA_global_init,
+		ALPHA_option,
+		0,
+	},
+#else
+	{ NULL, NULL, 0 },
+#endif
 };
 
 // bitmask of enabled architectures
@@ -313,6 +323,9 @@ static const uint32_t all_arch = 0
 #ifdef CAPSTONE_HAS_TRICORE
 	| (1 << CS_ARCH_TRICORE)
 #endif
+#ifdef CAPSTONE_HAS_ALPHA
+	| (1 << CS_ARCH_ALPHA)
+#endif
 ;
 
 
@@ -387,7 +400,8 @@ bool CAPSTONE_API cs_support(int query)
 				    (1 << CS_ARCH_M680X) | (1 << CS_ARCH_EVM)        |
 				    (1 << CS_ARCH_RISCV) | (1 << CS_ARCH_MOS65XX)    |
 				    (1 << CS_ARCH_WASM)  | (1 << CS_ARCH_BPF)        |
-				    (1 << CS_ARCH_SH)    | (1 << CS_ARCH_TRICORE));
+				    (1 << CS_ARCH_SH)    | (1 << CS_ARCH_TRICORE)    |
+					(1 << CS_ARCH_ALPHA));
 
 	if ((unsigned int)query < CS_ARCH_MAX)
 		return all_arch & (1 << query);
@@ -718,6 +732,9 @@ static uint8_t skipdata_size(cs_struct *handle)
 			// TriCore instruction's length can be 2 or 4 bytes,
 			// so we just skip 2 bytes
 			return 2;
+		case CS_ARCH_ALPHA:
+			// Alpha alignment is 4.
+			return 4;
 	}
 }
 
@@ -1454,6 +1471,11 @@ int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type)
 				if (insn->detail->tricore.operands[i].type == (tricore_op_type)op_type)
 					count++;
 			break;
+		case CS_ARCH_ALPHA:
+			for (i = 0; i < insn->detail->alpha.op_count; i++)
+				if (insn->detail->alpha.operands[i].type == (alpha_op_type)op_type)
+					count++;
+			break;
 	}
 
 	return count;
@@ -1637,6 +1659,14 @@ int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type,
 					return i;
 			}
 			break;
+		case CS_ARCH_ALPHA:
+			for (i = 0; i < insn->detail->alpha.op_count; i++) {
+				if (insn->detail->alpha.operands[i].type == (alpha_op_type)op_type)
+					count++;
+				if (count == post)
+					return i;
+			}
+			break;
 	}
 
 	return -1;

cstool/cstool.c

@@ -114,6 +114,7 @@ static struct {
 	{ "tc160", CS_ARCH_TRICORE, CS_MODE_TRICORE_160 },
 	{ "tc161", CS_ARCH_TRICORE, CS_MODE_TRICORE_161 },
 	{ "tc162", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 },
+	{ "alpha", CS_ARCH_ALPHA, 0 },
 	{ NULL }
 };
 
@@ -208,6 +209,10 @@ static void usage(char *prog)
 		printf("        aarch64be     aarch64 + big endian\n");
 	}
 
+	if (cs_support(CS_ARCH_ALPHA)) {
+		printf("        alpha       alpha\n");
+	}
+
 	if (cs_support(CS_ARCH_MIPS)) {
 		printf("        mips        mips32 + little endian\n");
 		printf("        mipsbe      mips32 + big endian\n");
@@ -392,6 +397,9 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
 		case CS_ARCH_TRICORE:
 			print_insn_detail_tricore(handle, ins);
 			break;
+		case CS_ARCH_ALPHA:
+			print_insn_detail_alpha(handle, ins);
+			break;
 		default: break;
 	}
 
@@ -528,6 +536,10 @@ int main(int argc, char **argv)
 					printf("tricore=1 ");
 				}
 
+				if (cs_support(CS_ARCH_ALPHA)) {
+					printf("alpha=1 ");
+				}
+
 				printf("\n");
 				return 0;
 			case 'h':

cstool/cstool.h

@@ -19,5 +19,6 @@ void print_insn_detail_mos65xx(csh handle, cs_insn *ins);
 void print_insn_detail_bpf(csh handle, cs_insn *ins);
 void print_insn_detail_sh(csh handle, cs_insn *ins);
 void print_insn_detail_tricore(csh handle, cs_insn *ins);
+void print_insn_detail_alpha(csh handle, cs_insn *ins);
 
 #endif //CAPSTONE_CSTOOL_CSTOOL_H_

cstool/cstool_alpha.c

@@ -0,0 +1,63 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <capstone/capstone.h>
+#include "cstool.h"
+
+void print_insn_detail_alpha(csh handle, cs_insn *ins)
+{
+	cs_alpha *alpha;
+	int i;
+	cs_regs regs_read, regs_write;
+	uint8_t regs_read_count, regs_write_count;
+
+	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
+	if (ins->detail == NULL)
+		return;
+
+	alpha = &(ins->detail->alpha);
+
+	if (alpha->op_count)
+		printf("\top_count: %u\n", alpha->op_count);
+
+	for (i = 0; i < alpha->op_count; i++) {
+		cs_alpha_op *op = &(alpha->operands[i]);
+		switch ((int)op->type) {
+		default:
+			break;
+		case ALPHA_OP_REG:
+			printf("\t\toperands[%u].type: REG = %s\n", i,
+			       cs_reg_name(handle, op->reg));
+			break;
+		case ALPHA_OP_IMM:
+			printf("\t\toperands[%u].type: IMM = 0x%x\n", i,
+			       op->imm);
+			break;
+		}
+
+		// Print out all registers accessed by this instruction (either implicit or
+		// explicit)
+		if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
+				    regs_write, &regs_write_count)) {
+			if (regs_read_count) {
+				printf("\tRegisters read:");
+				for (i = 0; i < regs_read_count; i++) {
+					printf(" %s",
+					       cs_reg_name(handle,
+							   regs_read[i]));
+				}
+				printf("\n");
+			}
+
+			if (regs_write_count) {
+				printf("\tRegisters modified:");
+				for (i = 0; i < regs_write_count; i++) {
+					printf(" %s",
+					       cs_reg_name(handle,
+							   regs_write[i]));
+				}
+				printf("\n");
+			}
+		}
+	}
+}

include/capstone/alpha.h

@@ -0,0 +1,302 @@
+#ifndef CAPSTONE_ALPHA_H
+#define CAPSTONE_ALPHA_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+#include "cs_operand.h"
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable : 4201)
+#endif
+
+#define MAX_ALPHA_OPS 3
+
+//> Operand type for instruction's operands
+typedef enum alpha_op_type {
+	ALPHA_OP_INVALID = CS_OP_INVALID, ///< CS_OP_INVALID (Uninitialized).
+	ALPHA_OP_REG = CS_OP_REG,	    ///< CS_OP_REG (Register operand).
+	ALPHA_OP_IMM = CS_OP_IMM,	    ///< CS_OP_IMM (Immediate operand).
+} alpha_op_type;
+
+// Instruction operand
+typedef struct cs_alpha_op {
+	alpha_op_type type; // operand type
+	union {
+		unsigned int reg; // register value for REG operand
+		int32_t imm; // immediate value for IMM operand
+	};
+	enum cs_ac_type access;
+} cs_alpha_op;
+
+// Instruction structure
+typedef struct cs_alpha {
+	// Number of operands of this instruction,
+	// or 0 when instruction has no operand.
+	uint8_t op_count;
+	cs_alpha_op operands[MAX_ALPHA_OPS]; // operands for this instruction.
+} cs_alpha;
+
+
+//> Alpha registers
+typedef enum alpha_reg {
+	// generated content <AlphaGenCSRegEnum.inc> begin
+	// clang-format off
+
+	Alpha_REG_INVALID = 0,
+	Alpha_REG_F0 = 1,
+	Alpha_REG_F1 = 2,
+	Alpha_REG_F2 = 3,
+	Alpha_REG_F3 = 4,
+	Alpha_REG_F4 = 5,
+	Alpha_REG_F5 = 6,
+	Alpha_REG_F6 = 7,
+	Alpha_REG_F7 = 8,
+	Alpha_REG_F8 = 9,
+	Alpha_REG_F9 = 10,
+	Alpha_REG_F10 = 11,
+	Alpha_REG_F11 = 12,
+	Alpha_REG_F12 = 13,
+	Alpha_REG_F13 = 14,
+	Alpha_REG_F14 = 15,
+	Alpha_REG_F15 = 16,
+	Alpha_REG_F16 = 17,
+	Alpha_REG_F17 = 18,
+	Alpha_REG_F18 = 19,
+	Alpha_REG_F19 = 20,
+	Alpha_REG_F20 = 21,
+	Alpha_REG_F21 = 22,
+	Alpha_REG_F22 = 23,
+	Alpha_REG_F23 = 24,
+	Alpha_REG_F24 = 25,
+	Alpha_REG_F25 = 26,
+	Alpha_REG_F26 = 27,
+	Alpha_REG_F27 = 28,
+	Alpha_REG_F28 = 29,
+	Alpha_REG_F29 = 30,
+	Alpha_REG_F30 = 31,
+	Alpha_REG_F31 = 32,
+	Alpha_REG_R0 = 33,
+	Alpha_REG_R1 = 34,
+	Alpha_REG_R2 = 35,
+	Alpha_REG_R3 = 36,
+	Alpha_REG_R4 = 37,
+	Alpha_REG_R5 = 38,
+	Alpha_REG_R6 = 39,
+	Alpha_REG_R7 = 40,
+	Alpha_REG_R8 = 41,
+	Alpha_REG_R9 = 42,
+	Alpha_REG_R10 = 43,
+	Alpha_REG_R11 = 44,
+	Alpha_REG_R12 = 45,
+	Alpha_REG_R13 = 46,
+	Alpha_REG_R14 = 47,
+	Alpha_REG_R15 = 48,
+	Alpha_REG_R16 = 49,
+	Alpha_REG_R17 = 50,
+	Alpha_REG_R18 = 51,
+	Alpha_REG_R19 = 52,
+	Alpha_REG_R20 = 53,
+	Alpha_REG_R21 = 54,
+	Alpha_REG_R22 = 55,
+	Alpha_REG_R23 = 56,
+	Alpha_REG_R24 = 57,
+	Alpha_REG_R25 = 58,
+	Alpha_REG_R26 = 59,
+	Alpha_REG_R27 = 60,
+	Alpha_REG_R28 = 61,
+	Alpha_REG_R29 = 62,
+	Alpha_REG_R30 = 63,
+	Alpha_REG_R31 = 64,
+	Alpha_REG_ENDING, // 65
+
+	// clang-format on
+	// generated content <AlphaGenCSRegEnum.inc> end
+} alpha_reg;
+
+//> Alpha instruction
+typedef enum alpha_insn {
+	// generated content <AlphaGenCSInsnEnum.inc:GET_INSTR_ENUM> begin
+	// clang-format off
+
+	Alpha_INS_INVALID,
+	Alpha_INS_ADDL,
+	Alpha_INS_ADDQ,
+	Alpha_INS_ADDSsSU,
+	Alpha_INS_ADDTsSU,
+	Alpha_INS_AND,
+	Alpha_INS_BEQ,
+	Alpha_INS_BGE,
+	Alpha_INS_BGT,
+	Alpha_INS_BIC,
+	Alpha_INS_BIS,
+	Alpha_INS_BLBC,
+	Alpha_INS_BLBS,
+	Alpha_INS_BLE,
+	Alpha_INS_BLT,
+	Alpha_INS_BNE,
+	Alpha_INS_BR,
+	Alpha_INS_BSR,
+	Alpha_INS_CMOVEQ,
+	Alpha_INS_CMOVGE,
+	Alpha_INS_CMOVGT,
+	Alpha_INS_CMOVLBC,
+	Alpha_INS_CMOVLBS,
+	Alpha_INS_CMOVLE,
+	Alpha_INS_CMOVLT,
+	Alpha_INS_CMOVNE,
+	Alpha_INS_CMPBGE,
+	Alpha_INS_CMPEQ,
+	Alpha_INS_CMPLE,
+	Alpha_INS_CMPLT,
+	Alpha_INS_CMPTEQsSU,
+	Alpha_INS_CMPTLEsSU,
+	Alpha_INS_CMPTLTsSU,
+	Alpha_INS_CMPTUNsSU,
+	Alpha_INS_CMPULE,
+	Alpha_INS_CMPULT,
+	Alpha_INS_COND_BRANCH,
+	Alpha_INS_CPYSE,
+	Alpha_INS_CPYSN,
+	Alpha_INS_CPYS,
+	Alpha_INS_CTLZ,
+	Alpha_INS_CTPOP,
+	Alpha_INS_CTTZ,
+	Alpha_INS_CVTQSsSUI,
+	Alpha_INS_CVTQTsSUI,
+	Alpha_INS_CVTSTsS,
+	Alpha_INS_CVTTQsSVC,
+	Alpha_INS_CVTTSsSUI,
+	Alpha_INS_DIVSsSU,
+	Alpha_INS_DIVTsSU,
+	Alpha_INS_ECB,
+	Alpha_INS_EQV,
+	Alpha_INS_EXCB,
+	Alpha_INS_EXTBL,
+	Alpha_INS_EXTLH,
+	Alpha_INS_EXTLL,
+	Alpha_INS_EXTQH,
+	Alpha_INS_EXTQL,
+	Alpha_INS_EXTWH,
+	Alpha_INS_EXTWL,
+	Alpha_INS_FBEQ,
+	Alpha_INS_FBGE,
+	Alpha_INS_FBGT,
+	Alpha_INS_FBLE,
+	Alpha_INS_FBLT,
+	Alpha_INS_FBNE,
+	Alpha_INS_FCMOVEQ,
+	Alpha_INS_FCMOVGE,
+	Alpha_INS_FCMOVGT,
+	Alpha_INS_FCMOVLE,
+	Alpha_INS_FCMOVLT,
+	Alpha_INS_FCMOVNE,
+	Alpha_INS_FETCH,
+	Alpha_INS_FETCH_M,
+	Alpha_INS_FTOIS,
+	Alpha_INS_FTOIT,
+	Alpha_INS_INSBL,
+	Alpha_INS_INSLH,
+	Alpha_INS_INSLL,
+	Alpha_INS_INSQH,
+	Alpha_INS_INSQL,
+	Alpha_INS_INSWH,
+	Alpha_INS_INSWL,
+	Alpha_INS_ITOFS,
+	Alpha_INS_ITOFT,
+	Alpha_INS_JMP,
+	Alpha_INS_JSR,
+	Alpha_INS_JSR_COROUTINE,
+	Alpha_INS_LDA,
+	Alpha_INS_LDAH,
+	Alpha_INS_LDBU,
+	Alpha_INS_LDL,
+	Alpha_INS_LDL_L,
+	Alpha_INS_LDQ,
+	Alpha_INS_LDQ_L,
+	Alpha_INS_LDQ_U,
+	Alpha_INS_LDS,
+	Alpha_INS_LDT,
+	Alpha_INS_LDWU,
+	Alpha_INS_MB,
+	Alpha_INS_MSKBL,
+	Alpha_INS_MSKLH,
+	Alpha_INS_MSKLL,
+	Alpha_INS_MSKQH,
+	Alpha_INS_MSKQL,
+	Alpha_INS_MSKWH,
+	Alpha_INS_MSKWL,
+	Alpha_INS_MULL,
+	Alpha_INS_MULQ,
+	Alpha_INS_MULSsSU,
+	Alpha_INS_MULTsSU,
+	Alpha_INS_ORNOT,
+	Alpha_INS_RC,
+	Alpha_INS_RET,
+	Alpha_INS_RPCC,
+	Alpha_INS_RS,
+	Alpha_INS_S4ADDL,
+	Alpha_INS_S4ADDQ,
+	Alpha_INS_S4SUBL,
+	Alpha_INS_S4SUBQ,
+	Alpha_INS_S8ADDL,
+	Alpha_INS_S8ADDQ,
+	Alpha_INS_S8SUBL,
+	Alpha_INS_S8SUBQ,
+	Alpha_INS_SEXTB,
+	Alpha_INS_SEXTW,
+	Alpha_INS_SLL,
+	Alpha_INS_SQRTSsSU,
+	Alpha_INS_SQRTTsSU,
+	Alpha_INS_SRA,
+	Alpha_INS_SRL,
+	Alpha_INS_STB,
+	Alpha_INS_STL,
+	Alpha_INS_STL_C,
+	Alpha_INS_STQ,
+	Alpha_INS_STQ_C,
+	Alpha_INS_STQ_U,
+	Alpha_INS_STS,
+	Alpha_INS_STT,
+	Alpha_INS_STW,
+	Alpha_INS_SUBL,
+	Alpha_INS_SUBQ,
+	Alpha_INS_SUBSsSU,
+	Alpha_INS_SUBTsSU,
+	Alpha_INS_TRAPB,
+	Alpha_INS_UMULH,
+	Alpha_INS_WH64,
+	Alpha_INS_WH64EN,
+	Alpha_INS_WMB,
+	Alpha_INS_XOR,
+	Alpha_INS_ZAPNOT,
+
+	// clang-format on
+	// generated content <AlphaGenCSInsnEnum.inc:GET_INSTR_ENUM> end
+    ALPHA_INS_ENDING, // <-- mark the end of the list of instructions
+} alpha_insn;
+
+//> Group of Alpha instructions
+typedef enum alpha_insn_group {
+	Alpha_GRP_INVALID, ///< = CS_GRP_INVALID
+	//> Generic groups
+	Alpha_GRP_CALL, ///< = CS_GRP_CALL
+	Alpha_GRP_JUMP, ///< = CS_GRP_JUMP
+	Alpha_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
+	Alpha_GRP_ENDING, ///< = mark the end of the list of groups
+} alpha_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

include/capstone/capstone.h

@@ -150,6 +150,7 @@ typedef enum cs_arch {
 	CS_ARCH_RISCV,          ///< RISCV architecture
 	CS_ARCH_SH,             ///< SH architecture
 	CS_ARCH_TRICORE,	///< TriCore architecture
+	CS_ARCH_ALPHA, 		///< Alpha architecture
 	CS_ARCH_MAX,
 	CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
 } cs_arch;
@@ -370,8 +371,9 @@ typedef struct cs_opt_skipdata {
 #include "bpf.h"
 #include "sh.h"
 #include "tricore.h"
+#include "alpha.h"
 
-#define MAX_IMPL_W_REGS 20
+#define MAX_IMPL_W_REGS 47
 #define MAX_IMPL_R_REGS 20
 #define MAX_NUM_GROUPS 8
 
@@ -414,6 +416,7 @@ typedef struct cs_detail {
 		cs_riscv riscv; ///< RISCV architecture
 		cs_sh sh;        ///< SH architecture
 		cs_tricore tricore; ///< TriCore architecture
+		cs_alpha alpha; ///< Alpha architecture
 	};
 } cs_detail;
 

nmake.bat

@@ -22,6 +22,7 @@ if "%1"=="MOS65XX" set %arch%=MOS65XX
 if "%1"=="WASM" set %arch%=WASM
 if "%1"=="BPF" set %arch%=BPF
 if "%1"=="RISCV" set %arch%=RISCV
+if "%1"=="ALPHA" set %arch%=ALPHA
 
 if not "%arch%"=="" set flags=%flags% and " -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF -DCAPSTONE_%arch%_SUPPORT=ON"
 

suite/MC/Alpha/insn-alpha.s.cs

@@ -0,0 +1,199 @@
+# CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, None
+0x03,0x00,0x22,0x40 = addl   $1,$2,$3
+0x03,0xd0,0x3b,0x40 = addl   $1,0xde,$3
+0x03,0x04,0x22,0x40 = addq   $1,$2,$3
+0x03,0xd4,0x3b,0x40 = addq   $1,0xde,$3
+0x03,0xb0,0x22,0x58 = adds/su        $f1,$f10,$f11
+0x03,0xb4,0x22,0x58 = addt/su        $f1,$f10,$f11
+0x03,0x00,0x22,0x44 = and    $1,$2,$3
+0x03,0xd0,0x3b,0x44 = and    $1,0xde,$3
+0xfc,0x3f,0x20,0xe4 = beq    $1,0xfffffffffffffff4
+0xfc,0x3f,0x20,0xf8 = bge    $1,0xfffffffffffffff4
+0xfc,0x3f,0x20,0xfc = bgt    $1,0xfffffffffffffff4
+0x03,0x01,0x22,0x44 = bic    $1,$2,$3
+0x03,0xd1,0x3b,0x44 = bic    $1,0xde,$3
+0x03,0x04,0x22,0x44 = bis    $1,$2,$3
+0x03,0xd4,0x3b,0x44 = bis    $1,0xde,$3
+0xfc,0x3f,0x20,0xe0 = blbc   $1,0xfffffffffffffff4
+0xfc,0x3f,0x20,0xf0 = blbs   $1,0xfffffffffffffff4
+0xfc,0x3f,0x20,0xec = ble    $1,0xfffffffffffffff4
+0xfc,0x3f,0x20,0xe8 = blt    $1,0xfffffffffffffff4
+0xfc,0x3f,0x20,0xf4 = bne    $1,0xfffffffffffffff4
+0xfc,0x3f,0xe0,0xc3 = br     $31,0xfffffffffffffff4
+0xfc,0x3f,0x40,0xd3 = bsr    $26,$0xfffffffffffffff4 ..ng
+0x83,0x04,0x22,0x44 = cmoveq $1,$2,$3
+0xc3,0x08,0x22,0x44 = cmovge $1,$2,$3
+0xc3,0x0c,0x22,0x44 = cmovgt $1,$2,$3
+0xc3,0x02,0x22,0x44 = cmovlbc        $1,$2,$3
+0x83,0x02,0x22,0x44 = cmovlbs        $1,$2,$3
+0x83,0x0c,0x22,0x44 = cmovle $1,$2,$3
+0x83,0x08,0x22,0x44 = cmovlt $1,$2,$3
+0xc3,0x04,0x22,0x44 = cmovne $1,$2,$3
+0xe3,0x01,0x22,0x40 = cmpbge $1,$2,$3
+0xe3,0xd1,0x3b,0x40 = cmpbge $1,0xde,$3
+0xa3,0x05,0x22,0x40 = cmpeq  $1,$2,$3
+0xa3,0xd5,0x3b,0x40 = cmpeq  $1,0xde,$3
+0xa3,0x0d,0x22,0x40 = cmple  $1,$2,$3
+0xa3,0xdd,0x3b,0x40 = cmple  $1,0xde,$3
+0xa3,0x09,0x22,0x40 = cmplt  $1,$2,$3
+0xa3,0xd9,0x3b,0x40 = cmplt  $1,0xde,$3
+0xa3,0xb4,0x22,0x58 = cmpteq/su      $f1,$f10,$f11
+0xe3,0xb4,0x22,0x58 = cmptle/su      $f1,$f10,$f11
+0xc3,0xb4,0x22,0x58 = cmptlt/su      $f1,$f10,$f11
+0x83,0xb4,0x22,0x58 = cmptun/su      $f1,$f10,$f11
+0xa3,0x07,0x22,0x40 = cmpule $1,$2,$3
+0xa3,0xd7,0x3b,0x40 = cmpule $1,0xde,$3
+0xa3,0x03,0x22,0x40 = cmpult $1,$2,$3
+0xa3,0xd3,0x3b,0x40 = cmpult $1,0xde,$3
+0x43,0x04,0x22,0x5c = cpyse  $f1,$f10,$f11
+0x23,0x04,0x22,0x5c = cpysn  $f1,$f10,$f11
+0x03,0x04,0x22,0x5c = cpys   $f1,$f10,$f11
+0x42,0x06,0xe1,0x73 = ctlz   $1,$2
+0x02,0x06,0xe1,0x73 = ctpop  $1,$2
+0x62,0x06,0xe1,0x73 = cttz   $1,$2
+0x82,0xf7,0xe1,0x5b = cvtqs/sui      $f1,$f10
+0xc2,0xf7,0xe1,0x5b = cvtqt/sui      $f1,$f10
+0x82,0xd5,0xe1,0x5b = cvtst/s        $f1,$f10
+0xe2,0xa5,0xe1,0x5b = cvttq/svc      $f1,$f10
+0x82,0xf5,0xe1,0x5b = cvtts/sui      $f1,$f10
+0x63,0xb0,0x22,0x58 = divs/su        $f1,$f10,$f11
+0x63,0xb4,0x22,0x58 = divt/su        $f1,$f10,$f11
+0x00,0xe8,0xe1,0x63 = ecb    ($1)
+0x03,0x09,0x22,0x44 = eqv    $1,$2,$3
+0x03,0xd9,0x3b,0x44 = eqv    $1,0xde,$3
+0x00,0x04,0x00,0x60 = excb
+0xc3,0x00,0x22,0x48 = extbl  $1,$2,$3
+0xc3,0xd0,0x3b,0x48 = extbl $1,0xde,$3
+0x43,0x0d,0x22,0x48 = extlh $1,$2,$3
+0x43,0xdd,0x3b,0x48 = extlh $1,0xde,$3
+0xc3,0x04,0x22,0x48 = extll $1,$2,$3
+0xc3,0xd4,0x3b,0x48 = extll $1,0xde,$3
+0x43,0x0f,0x22,0x48 = extqh $1,$2,$3
+0x43,0xdf,0x3b,0x48 = extqh $1,0xde,$3
+0xc3,0x06,0x22,0x48 = extql $1,$2,$3
+0xc3,0xd6,0x3b,0x48 = extql $1,0xde,$3
+0x43,0x0b,0x22,0x48 = extwh $1,$2,$3
+0x43,0xdb,0x3b,0x48 = extwh $1,0xde,$3
+0xc3,0x02,0x22,0x48 = extwl $1,$2,$3
+0xc3,0xd2,0x3b,0x48 = extwl $1,0xde,$3
+0xfc,0x3f,0x20,0xc4 = fbeq  $f1,0xfffffffffffffff4
+0xfc,0x3f,0x20,0xd8 = fbge  $f1,0xfffffffffffffff4
+0xfc,0x3f,0x20,0xdc = fbgt  $f1,0xfffffffffffffff4
+0xfc,0x3f,0x20,0xcc = fble  $f1,0xfffffffffffffff4
+0xfc,0x3f,0x20,0xc8 = fblt  $f1,0xfffffffffffffff4
+0xfc,0x3f,0x20,0xd4 = fbne  $f1,0xfffffffffffffff4
+0x43,0x05,0x22,0x5c = fcmoveq       ,$f10,$f11
+0xa3,0x05,0x22,0x5c = fcmovge       ,$f10,$f11
+0xe3,0x05,0x22,0x5c = fcmovgt       ,$f10,$f11
+0xc3,0x05,0x22,0x5c = fcmovle       ,$f10,$f11
+0x83,0x05,0x22,0x5c = fcmovlt       ,$f10,$f11
+0x63,0x05,0x22,0x5c = fcmovne       ,$f10,$f11
+0x00,0x80,0xe1,0x63 = fetch ($1)
+0x00,0xa0,0xe1,0x63 = fetch_m       ($1)
+0x01,0x0f,0x3f,0x70 = ftois $f1,$1
+0x01,0x0e,0x3f,0x70 = ftoit $f1,$1
+0x63,0x01,0x22,0x48 = insbl $1,$2,$3
+0x63,0xd1,0x3b,0x48 = insbl $1,0xde,$3
+0xe3,0x0c,0x22,0x48 = inslh $1,$2,$3
+0xe3,0xdc,0x3b,0x48 = inslh $1,0xde,$3
+0x63,0x05,0x22,0x48 = insll $1,$2,$3
+0x63,0xd5,0x3b,0x48 = insll $1,0xde,$3
+0xe3,0x0e,0x22,0x48 = insqh $1,$2,$3
+0xe3,0xde,0x3b,0x48 = insqh $1,0xde,$3
+0x63,0x07,0x22,0x48 = insql $1,$2,$3
+0x63,0xd7,0x3b,0x48 = insql $1,0xde,$3
+0xe3,0x0a,0x22,0x48 = inswh $1,$2,$3
+0xe3,0xda,0x3b,0x48 = inswh $1,0xde,$3
+0x63,0x03,0x22,0x48 = inswl $1,$2,$3
+0x63,0xd3,0x3b,0x48 = inswl $1,0xde,$3
+0x81,0x00,0x3f,0x50 = itofs $1,$f1
+0x81,0x04,0x3f,0x50 = itoft $1,$f1
+0x00,0x00,0xfa,0x6b = jmp   $31,$12,0
+0x00,0x40,0x5b,0x6b = jsr    $26,($27),0
+0xff,0xcf,0x22,0x68 = jsr_coroutine $1,($2),0xfff
+0x10,0x00,0x22,0x20 = lda   $1,0x10($2)
+0x10,0x00,0x22,0x24 = ldah  $1,0x10($2)
+0x10,0x00,0x22,0x28 = ldbu  $1,0x10($2)
+0x10,0x00,0x22,0xa0 = ldl   $1,0x10($2)
+0x10,0x00,0x22,0xa8 = ldl_l $1,0x10($2)
+0x10,0x00,0x22,0xa4 = ldq   $1,0x10($2)
+0x10,0x00,0x22,0xac = ldq_l $1,0x10($2)
+0x10,0x00,0x22,0x2c = ldq_u $1,0x10($2)
+0x10,0x00,0x22,0x88 = lds   $f1,0x10($2)
+0x10,0x00,0x22,0x8c = ldt   $f1,0x10($2)
+0x10,0x00,0x22,0x30 = ldwu  $1,0x10($2)
+0x00,0x40,0x00,0x60 = mb
+0x43,0x00,0x22,0x48 = mskbl $1,$2,$3
+0x43,0xd0,0x3b,0x48 = mskbl $1,0xde,$3
+0x43,0x0c,0x22,0x48 = msklh $1,$2,$3
+0x43,0xdc,0x3b,0x48 = msklh $1,0xde,$3
+0x43,0x04,0x22,0x48 = mskll $1,$2,$3
+0x43,0xd4,0x3b,0x48 = mskll $1,0xde,$3
+0x43,0x0e,0x22,0x48 = mskqh $1,$2,$3
+0x43,0xde,0x3b,0x48 = mskqh $1,0xde,$3
+0x43,0x06,0x22,0x48 = mskql $1,$2,$3
+0x43,0xd6,0x3b,0x48 = mskql $1,0xde,$3
+0x43,0x0a,0x22,0x48 = mskwh $1,$2,$3
+0x43,0xda,0x3b,0x48 = mskwh $1,0xde,$3
+0x43,0x02,0x22,0x48 = mskwl $1,$2,$3
+0x43,0xd2,0x3b,0x48 = mskwl $1,0xde,$3
+0x03,0x00,0x22,0x4c = mull  $1,$2,$3
+0x03,0xd0,0x3b,0x4c = mull  $1,0xde,$3
+0x03,0x04,0x22,0x4c = mulq  $1,$2,$3
+0x03,0xd4,0x3b,0x4c = mulq  $1,0xde,$3
+0x43,0xb0,0x22,0x58 = muls/su       $f1,$f10,$f11
+0x43,0xb4,0x22,0x58 = mult/su       $f1,$f10,$f11
+0x03,0x05,0x22,0x44 = ornot $1,$2,$3
+0x03,0xd5,0x3b,0x44 = ornot $1,0xde,$3
+0x00,0xe0,0x20,0x60 = rc    $1
+0x01,0x80,0xfa,0x6b = ret   $31,($26),1
+0x00,0xc0,0x1f,0x60 = rpcc  $0
+0x00,0xf0,0x20,0x60 = rs    $1
+0x43,0x00,0x22,0x40 = s4addl        $1,$2,$3
+0x43,0xd0,0x3b,0x40 = s4addl        $1,0xde,$3
+0x63,0x01,0x22,0x40 = s4subl        $1,$2,$3
+0x63,0xd1,0x3b,0x40 = s4subl        $1,0xde,$3
+0x63,0x05,0x22,0x40 = s4subq        $1,$2,$3
+0x63,0xd5,0x3b,0x40 = s4subq        $1,0xde,$3
+0x43,0x02,0x22,0x40 = s8addl        $1,$2,$3
+0x43,0xd2,0x3b,0x40 = s8addl        $1,0xde,$3
+0x43,0x06,0x22,0x40 = s8addq        $1,$2,$3
+0x43,0xd6,0x3b,0x40 = s8addq        $1,0xde,$3
+0x63,0x03,0x22,0x40 = s8subl        $1,$2,$3
+0x63,0xd3,0x3b,0x40 = s8subl        $1,0xde,$3
+0x63,0x07,0x22,0x40 = s8subq        $1,$2,$3
+0x63,0xd7,0x3b,0x40 = s8subq        $1,0xde,$3
+0x02,0x00,0xe1,0x73 = sextb $1,$2
+0x22,0x00,0xe1,0x73 = sextw $1,$2
+0x23,0x07,0x22,0x48 = sll   $1,$2,$3
+0x23,0xd7,0x3b,0x48 = sll   $1,0xde,$3
+0x62,0xb1,0xe1,0x53 = sqrts/su      $f1,$f10
+0x62,0xb5,0xe1,0x53 = sqrtt/su      $f1,$f10
+0x83,0x07,0x22,0x48 = sra   $1,$2,$3
+0x83,0xd7,0x3b,0x48 = sra   $1,0xde,$3
+0x83,0x06,0x22,0x48 = srl   $1,$2,$3
+0x83,0xd6,0x3b,0x48 = srl   $1,0xde,$3
+0x10,0x00,0x22,0x38 = stb   $1, 0x10($2)
+0x10,0x00,0x22,0xb0 = stl   $1,0x10($2)
+0x10,0x00,0x22,0xb8 = stl_c $1,0x10($2)
+0x10,0x00,0x22,0xb4 = stq   $1,0x10($2)
+0x10,0x00,0x22,0xbc = stq_c $1,0x10($2)
+0x10,0x00,0x22,0x3c = stq_u $1, 0x10($2)
+0x10,0x00,0x22,0x98 = sts   $f1,0x10($2)
+0x10,0x00,0x22,0x9c = stt   $f1,0x10($2)
+0x10,0x00,0x22,0x34 = stw   $1,0x10($2)
+0x23,0x01,0x22,0x40 = subl  $1,$2,$3
+0x23,0xd1,0x3b,0x40 = subl  $1,0xde,$3
+0x23,0x05,0x22,0x40 = subq  $1,$2,$3
+0x23,0xd5,0x3b,0x40 = subq  $1,0xde,$3
+0x23,0xb0,0x22,0x58 = subs/su       $f1,$f10,$f11
+0x23,0xb4,0x22,0x58 = subt/su       $f1,$f10,$f11
+0x00,0x00,0x00,0x60 = trapb
+0x03,0x06,0x22,0x4c = umulh $1,$2,$3
+0x03,0xd6,0x3b,0x4c = umulh $1,0xde,$3
+0x00,0xf8,0xe1,0x63 = wh64  ($1)
+0x00,0xfc,0xe1,0x63 = wh64en        ($1)
+0x00,0x44,0x00,0x60 = wmb
+0x03,0x08,0x22,0x44 = xor   $1,$2,$3
+0x03,0xd8,0x3b,0x44 = xor   $1,0xde,$3
+0x23,0xd6,0x3b,0x48 = zapnot        $1,0xde,$3

suite/auto-sync/Updater/ASUpdater.py

@@ -151,7 +151,7 @@ def parse_args() -> argparse.Namespace:
         description="Capstones architecture module updater.",
     )
     parser.add_argument(
-        "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC", "AArch64"], required=True
+        "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC", "AArch64", "Alpha"], required=True
     )
     parser.add_argument("-d", dest="no_clean", help="Don't clean build dir before updating.", action="store_true")
     parser.add_argument(

suite/auto-sync/Updater/CppTranslator/CppTranslator.py

@@ -452,7 +452,7 @@ def parse_args() -> argparse.Namespace:
         description="Capstones C++ to C translator for LLVM source files",
     )
     parser.add_argument(
-        "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC", "AArch64"], required=True
+        "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC", "AArch64", "Alpha"], required=True
     )
     parser.add_argument(
         "-v",

suite/auto-sync/Updater/CppTranslator/Differ.py

@@ -11,7 +11,7 @@ import difflib as dl
 import logging as log
 import sys
 
-from Configurator import Configurator
+from CppTranslator.Configurator import Configurator
 from Helper import (
     convert_loglevel,
     find_id_by_type,
@@ -603,7 +603,7 @@ def parse_args() -> argparse.Namespace:
         action="store_true",
     )
     parser.add_argument(
-        "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC, AArch64"], required=True
+        "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC, AArch64", "Alpha"], required=True
     )
     parser.add_argument(
         "-v",

suite/auto-sync/Updater/CppTranslator/arch_config.json

@@ -119,5 +119,14 @@
       "isSVEAddSubImm"
     ],
     "manually_edited_files": []
+  },
+  "Alpha": {
+    "files_to_translate": [],
+    "files_for_template_search": [
+      "{CPP_INC_OUT_DIR}/AlphaGenDisassemblerTables.inc",
+      "{CPP_INC_OUT_DIR}/AlphaGenAsmWriter.inc"
+    ],
+    "templates_with_arg_deduction": [],
+    "manually_edited_files": []
   }
 }

suite/auto-sync/Updater/Update-Arch.sh

@@ -53,7 +53,7 @@ setup_build_dir() {
 # Main
 #
 
-supported="ARM, PPC, AArch64"
+supported="ARM, PPC, AArch64, Alpha"
 
 if [ $# -ne 3 ] || [ "$1" = "-h" ] || [ "$1" = "--help" ]; then
   echo "$0 <arch> <path-llvm-project> <llvm-release-commit>"

suite/capstone_get_setup.c

@@ -73,6 +73,9 @@ int main()
 	if (cs_support(CS_ARCH_TRICORE)) {
 		printf("tricore=1 ");
 	}
+	if (cs_support(CS_ARCH_ALPHA)) {
+		printf("alpha=1 ");
+	}
 	printf("\n");
 
 	return 0;

suite/cstest/include/factory.h

@@ -24,5 +24,6 @@ char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins);
 char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins);
 char *get_detail_bpf(csh *handle, cs_mode mode, cs_insn *ins);
 char *get_detail_tricore(csh *handle, cs_mode mode, cs_insn *ins);
+char *get_detail_alpha(csh *handle, cs_mode mode, cs_insn *ins);
 
 #endif /* FACTORY_H */

suite/cstest/src/alpha_detail.c

@@ -0,0 +1,69 @@
+/* Capstone testing regression */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#include "factory.h"
+
+char *get_detail_alpha(csh *p_handle, cs_mode mode, cs_insn *ins)
+{
+	cs_alpha *alpha;
+	int i;
+	cs_regs regs_read, regs_write;
+	uint8_t regs_read_count, regs_write_count;
+
+	char *result;
+	result = (char *)malloc(sizeof(char));
+	result[0] = '\0';
+
+	if (ins->detail == NULL)
+		return result;
+
+	csh handle = *p_handle;
+
+	alpha = &(ins->detail->alpha);
+
+	if (alpha->op_count)
+		add_str(&result, "\top_count: %u\n", alpha->op_count);
+
+	for (i = 0; i < alpha->op_count; i++) {
+		cs_alpha_op *op = &(alpha->operands[i]);
+		switch ((int)op->type) {
+		default:
+			break;
+		case ALPHA_OP_REG:
+			add_str(&result, "\t\toperands[%u].type: REG = %s\n", i,
+				cs_reg_name(handle, op->reg));
+			break;
+		case ALPHA_OP_IMM:
+			add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n",
+				i, op->imm);
+			break;
+		}
+
+		// Print out all registers accessed by this instruction (either implicit or
+		// explicit)
+		if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
+				    regs_write, &regs_write_count)) {
+			if (regs_read_count) {
+				add_str(&result, "\tRegisters read:");
+				for (i = 0; i < regs_read_count; i++) {
+					add_str(&result, " %s",
+						cs_reg_name(handle,
+							    regs_read[i]));
+				}
+				add_str(&result, "\n");
+			}
+
+			if (regs_write_count) {
+				add_str(&result, "\tRegisters modified:");
+				for (i = 0; i < regs_write_count; i++) {
+					add_str(&result, " %s",
+						cs_reg_name(handle,
+							    regs_write[i]));
+				}
+				add_str(&result, "\n");
+			}
+		}
+	}
+
+	return result;
+}

suite/cstest/src/capstone_test.c

@@ -195,6 +195,9 @@ int set_function(int arch)
 		case CS_ARCH_TRICORE:
 			function = get_detail_tricore;
 			break;
+		case CS_ARCH_ALPHA:
+			function = get_detail_alpha;
+			break;
 		default:
 			return -1;
 	}

suite/cstest/src/main.c

@@ -21,6 +21,7 @@ static single_dict arches[] = {
 	{"CS_ARCH_BPF", CS_ARCH_BPF},
 	{"CS_ARCH_RISCV", CS_ARCH_RISCV},
 	{"CS_ARCH_TRICORE", CS_ARCH_TRICORE},
+	{"CS_ARCH_ALPHA", CS_ARCH_ALPHA},
 };
 
  static single_dict modes[] = {

suite/test_c.sh

@@ -23,4 +23,5 @@
 ../tests/test_wasm > /tmp/$1
 ../tests/test_winkernel > /tmp/$1
 ../tests/test_x86 > /tmp/$1
-../tests/test_xcore > /tmp/$1
+../tests/test_xcore > /tmp/$1
+../tests/test_alpha > /tmp/$1

suite/test_corpus.py

@@ -33,6 +33,7 @@ def test_file(fname):
         "CS_ARCH_XCORE": CS_ARCH_XCORE,
         "CS_ARCH_RISCV": CS_ARCH_RISCV,
         "CS_ARCH_TRICORE": CS_ARCH_TRICORE,
+        "CS_ARCH_ALPHA": CS_ARCH_ALPHA,
     }
     
     modes = {
@@ -115,6 +116,7 @@ def test_file(fname):
         ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_161"): 52,
         ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_162"): 53,
         ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN+CS_MODE_QPX"): 54,
+        ("CS_ARCH_ALPHA", "CS_MODE_LITTLE_ENDIAN"): 55,
     }
 
     #if not option in ('', 'None'):

suite/test_corpus3.py

@@ -43,6 +43,7 @@ def test_file(fname):
         "CS_ARCH_XCORE": CS_ARCH_XCORE,
         "CS_ARCH_RISCV": CS_ARCH_RISCV,
         "CS_ARCH_TRICORE": CS_ARCH_TRICORE,
+        "CS_ARCH_ALPHA": CS_ARCH_ALPHA,
     }
 
     modes = {
@@ -125,6 +126,7 @@ def test_file(fname):
         ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_161"): 52,
         ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_162"): 53,
         ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN+CS_MODE_QPX"): 54,
+        ("CS_ARCH_ALPHA", "CS_MODE_LITTLE_ENDIAN"): 55,
     }
 
     # if not option in ('', 'None'):

suite/test_python.sh

@@ -11,3 +11,4 @@
 ../bindings/python/test_ppc.py >> /tmp/$1
 ../bindings/python/test_sparc.py >> /tmp/$1
 ../bindings/python/test_x86.py >> /tmp/$1
+../bindings/python/test_alpha.py >> /tmp/$1

tests/Makefile

@@ -137,6 +137,11 @@ ifneq (,$(findstring sh,$(CAPSTONE_ARCHS)))
 CFLAGS += -DCAPSTONE_HAS_SH
 SOURCES += test_sh.c
 endif
+ifneq (,$(findstring alpha,$(CAPSTONE_ARCHS)))
+CFLAGS += -DCAPSTONE_HAS_ALPHA
+SOURCES += test_alpha.c
+endif
+
 
 OBJS = $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o))
 BINARY = $(addprefix $(TESTDIR)/,$(SOURCES:.c=$(BIN_EXT)))

tests/test_all.sh

@@ -18,4 +18,5 @@
 ./test_wasm
 ./test_winkernel
 ./test_x86
-./test_xcore
+./test_xcore
+./test_alpha

tests/test_alpha.c

@@ -0,0 +1,135 @@
+/* Capstone Disassembler Engine */
+/* By Dmitry Sibirtsev <aquynh@gmail.com>, 2013-2019 */
+
+#include <stdio.h>
+
+#include <capstone/platform.h>
+#include <capstone/capstone.h>
+
+struct platform {
+	cs_arch arch;
+	cs_mode mode;
+	unsigned char *code;
+	size_t size;
+	char *comment;
+};
+
+static csh handle;
+
+static void print_string_hex(char *comment, unsigned char *str, size_t len)
+{
+	unsigned char *c;
+
+	printf("%s", comment);
+	for (c = str; c < str + len; c++) {
+		printf("0x%02x ", *c & 0xff);
+	}
+
+	printf("\n");
+}
+
+static void print_insn_detail(cs_insn *ins)
+{
+	cs_alpha *alpha;
+	int i;
+
+	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
+	if (ins->detail == NULL)
+		return;
+
+	alpha = &(ins->detail->alpha);
+	if (alpha->op_count)
+		printf("\top_count: %u\n", alpha->op_count);
+
+	for (i = 0; i < alpha->op_count; i++) {
+		cs_alpha_op *op = &(alpha->operands[i]);
+		switch ((int)op->type) {
+		default:
+			break;
+		case ALPHA_OP_REG:
+			printf("\t\toperands[%u].type: REG = %s\n", i,
+			       cs_reg_name(handle, op->reg));
+			break;
+		case ALPHA_OP_IMM:
+			printf("\t\toperands[%u].type: IMM = 0x%x\n", i,
+			       op->imm);
+			break;
+		}
+	}
+
+	printf("\n");
+}
+
+static void test()
+{
+#define ALPHA_CODE \
+	"\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7"
+
+	struct platform platforms[] = {
+		{
+			CS_ARCH_ALPHA,
+			0,
+			(unsigned char *)ALPHA_CODE,
+			sizeof(ALPHA_CODE) - 1,
+			"Alpha",
+		},
+	};
+
+	uint64_t address = 0x1000;
+	cs_insn *insn;
+	int i;
+	size_t count;
+
+	for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) {
+		cs_err err =
+			cs_open(platforms[i].arch, platforms[i].mode, &handle);
+		if (err) {
+			printf("Failed on cs_open() with error returned: %u\n",
+			       err);
+			continue;
+		}
+
+		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
+
+		count = cs_disasm(handle, platforms[i].code, platforms[i].size,
+				  address, 0, &insn);
+		if (count) {
+			size_t j;
+
+			printf("****************\n");
+			printf("Platform: %s\n", platforms[i].comment);
+			print_string_hex("Code: ", platforms[i].code,
+					 platforms[i].size);
+			printf("Disasm:\n");
+
+			for (j = 0; j < count; j++) {
+				printf("0x%" PRIx64 ":\t%s\t%s\n",
+				       insn[j].address, insn[j].mnemonic,
+				       insn[j].op_str);
+				print_insn_detail(&insn[j]);
+			}
+			printf("0x%" PRIx64 ":\n",
+			       insn[j - 1].address + insn[j - 1].size);
+
+			// free memory allocated by cs_disasm()
+			cs_free(insn, count);
+		} else {
+			printf("****************\n");
+			printf("Platform: %s\n", platforms[i].comment);
+			print_string_hex("Code:", platforms[i].code,
+					 platforms[i].size);
+			printf("ERROR: Failed to disasm given code!\n");
+		}
+
+		printf("\n");
+
+		cs_close(&handle);
+	}
+}
+
+int main()
+{
+	test();
+
+	return 0;
+}

tests/test_basic.c

@@ -90,6 +90,9 @@ static void test()
 #ifdef CAPSTONE_HAS_RISCV
 #define RISCV_CODE32 "\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00"
 #define RISCV_CODE64 "\x13\x04\xa8\x7a"  // aaa80413
+#endif
+#ifdef CAPSTONE_HAS_ALPHA
+#define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7"
 #endif
 
 	struct platform {
@@ -363,6 +366,15 @@ static void test()
 			sizeof(RISCV_CODE64) - 1,
 			"RISCV64"
 		},
+#endif
+#ifdef CAPSTONE_HAS_ALPHA
+		{
+			CS_ARCH_ALPHA,
+			CS_MODE_LITTLE_ENDIAN,
+			(unsigned char*)ALPHA_CODE,
+			sizeof(ALPHA_CODE) - 1,
+			"Alpha"
+		},
 #endif
 	};
 

tests/test_detail.c

@@ -77,6 +77,9 @@ static void test()
 #endif
 #ifdef CAPSTONE_HAS_BPF
 #define EBPF_CODE "\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00"
+#endif
+#ifdef CAPSTONE_HAS_ALPHA
+#define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7"
 #endif
 
 	struct platform platforms[] = {
@@ -280,6 +283,15 @@ static void test()
 			sizeof(EBPF_CODE) - 1,
 			"eBPF"
 		},
+#endif
+#ifdef CAPSTONE_HAS_ALPHA
+		{
+			CS_ARCH_ALPHA,
+			CS_MODE_LITTLE_ENDIAN,
+			(unsigned char*)ALPHA_CODE,
+			sizeof(ALPHA_CODE) - 1,
+			"Alpha"
+		},
 #endif
 	};
 

tests/test_iter.c

@@ -79,6 +79,10 @@ static void test()
 #define TRICORE_CODE "\x16\x01\x20\x01\x1d\x00\x02\x00\x8f\x70\x00\x11\x40\xae\x89\xee\x04\x09\x42\xf2\xe2\xf2\xc2\x11\x19\xff\xc0\x70\x19\xff\x20\x10"
 #endif
 
+#ifdef CAPSTONE_HAS_ALPHA
+#define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7"
+#endif
+
 struct platform platforms[] = {
 #ifdef CAPSTONE_HAS_X86
 		{
@@ -261,6 +265,15 @@ struct platform platforms[] = {
 		sizeof(TRICORE_CODE) - 1,
 		"TriCore"
 	    },
+#endif
+#ifdef CAPSTONE_HAS_ALPHA
+	    {
+		CS_ARCH_ALPHA,
+		0,
+		(unsigned char*)ALPHA_CODE,
+		sizeof(ALPHA_CODE) - 1,
+		"Alpha"
+	    },
 #endif
 	};