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https://github.com/capstone-engine/capstone.git
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Update Cython bindings
This commit is contained in:
Peace-Maker
parent
c43083ad65
commit
90ef5aad5f
@ -1,4 +1,4 @@
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PYTHON2 ?= python
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PYTHON2 ?= python2
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PYTHON3 ?= python3
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.PHONY: gen_const install install3 install_cython sdist sdist3 bdist bdist3 clean check
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@ -885,7 +885,7 @@ class Cs(object):
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raise CsError(status)
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try:
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import ccapstone
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from . import ccapstone
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# rewire disasm to use the faster version
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self.disasm = ccapstone.Cs(self).disasm
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except:
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@ -2,7 +2,7 @@
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cimport pyx.ccapstone as cc
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import capstone, ctypes
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from . import arm, x86, mips, ppc, arm64, sparc, systemz, xcore, tms320c64x, CsError
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from . import arm, x86, mips, ppc, arm64, sparc, systemz, xcore, tms320c64x, m68k, m680x, evm, mos65xx, bpf, riscv, tricore, CsError
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_diet = cc.cs_support(capstone.CS_SUPPORT_DIET)
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@ -20,6 +20,7 @@ class CsDetail(object):
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self.regs_write_count = detail.regs_write_count
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self.groups = detail.groups
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self.groups_count = detail.groups_count
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self.writeback = detail.writeback
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if arch == capstone.CS_ARCH_ARM:
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(self.usermode, self.vector_size, self.vector_data, self.cps_mode, self.cps_flag, \
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@ -33,9 +34,12 @@ class CsDetail(object):
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self.modrm, self.sib, self.disp, \
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self.sib_index, self.sib_scale, self.sib_base, \
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self.xop_cc, self.sse_cc, self.avx_cc, self.avx_sae, self.avx_rm, \
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self.eflags, self.operands) = x86.get_arch_info(detail.arch.x86)
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self.eflags, self.encoding, self.modrm_offset, self.disp_offset, \
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self.disp_size, self.imm_offset, self.imm_size, self.operands) = x86.get_arch_info(detail.arch.x86)
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elif arch == capstone.CS_ARCH_M68K:
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(self.operands, self.op_size) = m68k.get_arch_info(detail.arch.m68k)
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elif arch == capstone.CS_ARCH_MIPS:
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self.operands = mips.get_arch_info(detail.arch.mips)
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self.operands = mips.get_arch_info(detail.arch.mips)
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elif arch == capstone.CS_ARCH_PPC:
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(self.bc, self.bh, self.update_cr0, self.operands) = \
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ppc.get_arch_info(detail.arch.ppc)
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@ -44,9 +48,21 @@ class CsDetail(object):
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elif arch == capstone.CS_ARCH_SYSZ:
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(self.cc, self.operands) = systemz.get_arch_info(detail.arch.sysz)
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elif arch == capstone.CS_ARCH_XCORE:
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self.operands = xcore.get_arch_info(detail.arch.xcore)
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self.operands = xcore.get_arch_info(detail.arch.xcore)
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elif arch == capstone.CS_ARCH_TMS320C64X:
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(self.condition, self.funit, self.parallel, self.operands) = tms320c64x.get_arch_info(self._detail.arch.tms320c64x)
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(self.condition, self.funit, self.parallel, self.operands) = tms320c64x.get_arch_info(self._detail.arch.tms320c64x)
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elif arch == capstone.CS_ARCH_M680X:
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(self.flags, self.operands) = m680x.get_arch_info(detail.arch.m680x)
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elif arch == capstone.CS_ARCH_EVM:
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(self.pop, self.push, self.fee) = evm.get_arch_info(detail.arch.evm)
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elif arch == capstone.CS_ARCH_MOS65XX:
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(self.am, self.modifies_flags, self.operands) = mos65xx.get_arch_info(detail.arch.mos65xx)
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elif arch == capstone.CS_ARCH_BPF:
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(self.operands) = bpf.get_arch_info(detail.arch.bpf)
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elif arch == capstone.CS_ARCH_RISCV:
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(self.need_effective_addr, self.operands) = riscv.get_arch_info(detail.arch.riscv)
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elif arch == capstone.CS_ARCH_TRICORE:
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(self.update_flags, self.operands) = tricore.get_arch_info(detail.arch.tricore)
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cdef class CsInsn(object):
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@ -249,7 +265,8 @@ cdef class CsInsn(object):
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if self._raw.id == 0:
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raise CsError(capstone.CS_ERR_SKIPDATA)
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cdef cc.uint16_t regs_read[64], regs_write[64]
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cdef cc.uint16_t regs_read[64]
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cdef cc.uint16_t regs_write[64]
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cdef cc.uint8_t read_count, write_count
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status = cc.cs_regs_access(self._cs.csh, &self._raw, regs_read, &read_count, regs_write, &write_count)
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@ -339,12 +356,16 @@ def debug():
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diet = "standard"
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archs = { "arm": capstone.CS_ARCH_ARM, "arm64": capstone.CS_ARCH_ARM64, \
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"mips": capstone.CS_ARCH_MIPS, "ppc": capstone.CS_ARCH_PPC, \
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"sparc": capstone.CS_ARCH_SPARC, "sysz": capstone.CS_ARCH_SYSZ, \
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"xcore": capstone.CS_ARCH_XCORE, "tms320c64x": capstone.CS_ARCH_TMS320C64X }
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"m68k": capstone.CS_ARCH_M68K, "mips": capstone.CS_ARCH_MIPS, \
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"ppc": capstone.CS_ARCH_PPC, "sparc": capstone.CS_ARCH_SPARC, \
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"sysz": capstone.CS_ARCH_SYSZ, "xcore": capstone.CS_ARCH_XCORE, \
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"tms320c64x": capstone.CS_ARCH_TMS320C64X, "m680x": capstone.CS_ARCH_M680X, \
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"evm": capstone.CS_ARCH_EVM, "mos65xx": capstone.CS_ARCH_MOS65XX, \
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"bpf": capstone.CS_ARCH_BPF, "riscv": capstone.CS_ARCH_RISCV, \
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"tricore": capstone.CS_ARCH_TRICORE }
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all_archs = ""
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keys = archs.keys()
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keys = list(archs.keys())
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keys.sort()
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for k in keys:
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if cc.cs_support(archs[k]):
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@ -41,7 +41,7 @@ else:
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compile_args = ['-O3', '-fomit-frame-pointer', '-I' + HEADERS_DIR]
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link_args = ['-L' + LIBS_DIR]
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ext_module_names = ['arm', 'arm_const', 'arm64', 'arm64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const' ]
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ext_module_names = ['arm', 'arm_const', 'arm64', 'arm64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const', 'mos65xx', 'mos65xx_const', 'bpf', 'bpf_const', 'riscv', 'riscv_const', 'tricore', 'tricore_const' ]
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ext_modules = [Extension("capstone.ccapstone",
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["pyx/ccapstone.pyx"],
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@ -54,6 +54,10 @@ ext_modules += [Extension("capstone.%s" % name,
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extra_link_args=link_args)
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for name in ext_module_names]
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for e in ext_modules:
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e.cython_directives = {"language_level": str(sys.version_info[0])}
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def clean_bins():
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shutil.rmtree(LIBS_DIR, ignore_errors=True)
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shutil.rmtree(HEADERS_DIR, ignore_errors=True)
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@ -137,6 +141,8 @@ setup(
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classifiers = [
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'License :: OSI Approved :: BSD License',
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'Programming Language :: Python :: 2',
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'Programming Language :: Python :: 2.7',
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'Programming Language :: Python :: 3',
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],
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include_package_data=True,
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package_data={
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