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Architecture updater (auto-sync) - Updating PPC (#2013)

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This commit is contained in:
Rot127 2023-09-05 04:24:59 +00:00 committed by GitHub
parent 198e0ab391
commit 926cfebd6b
128 changed files with 79246 additions and 42521 deletions
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16
CMakeLists.txt
View File

@ -253,19 +253,23 @@ if(CAPSTONE_PPC_SUPPORT)
arch/PowerPC/PPCModule.c
)
set(HEADERS_PPC
arch/PowerPC/PPCDisassembler.h
arch/PowerPC/PPCGenAsmWriter.inc
arch/PowerPC/PPCInstrInfo.h
arch/PowerPC/PPCInstPrinter.h
arch/PowerPC/PPCLinkage.h
arch/PowerPC/PPCMapping.h
arch/PowerPC/PPCMCTargetDesc.h
arch/PowerPC/PPCPredicates.h
arch/PowerPC/PPCRegisterInfo.h
arch/PowerPC/PPCGenAsmWriter.inc
arch/PowerPC/PPCGenRegisterName.inc
arch/PowerPC/PPCGenCSFeatureName.inc
arch/PowerPC/PPCGenCSMappingInsn.inc
arch/PowerPC/PPCGenCSMappingInsnOp.inc
arch/PowerPC/PPCGenCSMappingInsnName.inc
arch/PowerPC/PPCGenCSOpGroup.inc
arch/PowerPC/PPCGenDisassemblerTables.inc
arch/PowerPC/PPCMappingInsn.inc
arch/PowerPC/PPCMappingInsnName.inc
arch/PowerPC/PPCGenInstrInfo.inc
arch/PowerPC/PPCGenSubtargetInfo.inc
arch/PowerPC/PPCGenRegisterInfo.inc
arch/PowerPC/PPCGenInstrInfo.inc
)
set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c)
endif()

8
MCInst.c
View File

@ -34,6 +34,8 @@ void MCInst_Init(MCInst *inst)
inst->xAcquireRelease = 0;
for (int i = 0; i < MAX_MC_OPS; ++i)
inst->tied_op_idx[i] = -1;
inst->isAliasInstr = false;
inst->fillDetailOps = false;
}
void MCInst_clear(MCInst *inst)
@ -280,3 +282,9 @@ uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum)
else
assert(0 && "Operand type not handled in this getter.");
}
void MCInst_setIsAlias(MCInst *MI, bool Flag) {
assert(MI);
MI->isAliasInstr = Flag;
MI->flat_insn->is_alias = Flag;
}

8
MCInst.h
View File

@ -129,6 +129,8 @@ struct MCInst {
cs_wasm_op wasm_data; // for WASM operand
MCRegisterInfo *MRI;
uint8_t xAcquireRelease; // X86 xacquire/xrelease
bool isAliasInstr; // Flag if this MCInst is an alias.
bool fillDetailOps; // If set, detail->operands gets filled.
};
void MCInst_Init(MCInst *inst);
@ -163,4 +165,10 @@ bool MCInst_opIsTying(const MCInst *MI, unsigned OpNum);
uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum);
void MCInst_setIsAlias(MCInst *MI, bool Flag);
static inline bool MCInst_isAlias(const MCInst *MI) {
return MI->isAliasInstr;
}
#endif

3
MCInstPrinter.c
View File

@ -6,6 +6,7 @@
#include <capstone/platform.h>
extern bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool PPC_getFeatureBits(unsigned int mode, unsigned int feature);
static bool testFeatureBits(const MCInst *MI, uint32_t Value)
{
@ -15,6 +16,8 @@ static bool testFeatureBits(const MCInst *MI, uint32_t Value)
assert(0 && "Not implemented for current arch.");
case CS_ARCH_ARM:
return ARM_getFeatureBits(MI->csh->mode, Value);
case CS_ARCH_PPC:
return PPC_getFeatureBits(MI->csh->mode, Value);
}
}

58
Mapping.c
View File

@ -3,6 +3,7 @@
/* Rot127 <unisono@quyllur.org>, 2022-2023 */
#include "Mapping.h"
#include "capstone/capstone.h"
// create a cache for fast id lookup
static unsigned short *make_id2insn(const insn_map *insns, unsigned int size)
@ -311,3 +312,60 @@ const cs_ac_type mapping_get_op_access(MCInst *MI, unsigned OpNum,
DEFINE_get_detail_op(arm, ARM);
DEFINE_get_detail_op(ppc, PPC);
DEFINE_get_detail_op(tricore, TriCore);
/// Returns true if for this architecture the
/// alias operands should be filled.
/// TODO: Replace this with a proper option.
/// So it can be toggled between disas() calls.
bool map_use_alias_details(const MCInst *MI) {
assert(MI);
return !(MI->csh->detail_opt & CS_OPT_DETAIL_REAL);
}
/// Sets the setDetailOps flag to @p Val.
/// If detail == NULLit refuses to set the flag to true.
void map_set_fill_detail_ops(MCInst *MI, bool Val) {
assert(MI);
if (!detail_is_set(MI)) {
MI->fillDetailOps = false;
return;
}
MI->fillDetailOps = Val;
}
/// Sets the instruction alias flags and the given alias id.
void map_set_is_alias_insn(MCInst *MI, bool Val, uint64_t Alias) {
assert(MI);
MI->isAliasInstr = Val;
MI->flat_insn->is_alias = Val;
MI->flat_insn->alias_id = Alias;
}
/// Sets an alternative id for some instruction.
/// Or -1 if it fails.
/// You must add (<ARCH>_INS_ALIAS_BEGIN + 1) to the id to get the real id.
void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_id_map, int map_size) {
if (!MCInst_isAlias(MI))
return;
char alias_mnem[16] = { 0 };
int i = 0, j = 0;
const char *asm_str_buf = O->buffer;
// Skip spaces and tabs
while (asm_str_buf[i] == ' ' || asm_str_buf[i] == '\t') {
if (!asm_str_buf[i]) {
MI->flat_insn->alias_id = -1;
return;
}
++i;
}
for (; j < sizeof(alias_mnem) - 1; ++j, ++i) {
if (!asm_str_buf[i] || asm_str_buf[i] == ' ' || asm_str_buf[i] == '\t')
break;
alias_mnem[j] = O->buffer[i];
}
MI->flat_insn->alias_id = name2id(alias_mnem_id_map, map_size, alias_mnem);
}

31
Mapping.h
View File

@ -28,6 +28,9 @@ typedef struct insn_map {
[MAX_NUM_GROUPS]; ///< list of group this instruction belong to
bool branch; // branch instruction?
bool indirect_branch; // indirect branch instruction?
union {
ppc_suppl_info ppc;
} suppl_info; // Supplementary information for each instruction.
#endif
} insn_map;
@ -166,7 +169,7 @@ DEFINE_get_arch_detail(tricore, TriCore);
static inline bool detail_is_set(const MCInst *MI)
{
assert(MI && MI->flat_insn);
return MI->flat_insn->detail != NULL;
return MI->flat_insn->detail != NULL && MI->csh->detail_opt & CS_OPT_ON;
}
static inline cs_detail *get_detail(const MCInst *MI)
@ -175,4 +178,30 @@ static inline cs_detail *get_detail(const MCInst *MI)
return MI->flat_insn->detail;
}
static inline bool set_detail_ops(const MCInst *MI)
{
assert(MI && MI->flat_insn);
return MI->fillDetailOps;
}
/// Returns if the given instruction is an alias instruction.
#define RETURN_IF_INSN_IS_ALIAS(MI) \
do { \
if (MI->isAliasInstr) \
return; \
} while(0)
void map_set_fill_detail_ops(MCInst *MI, bool Val);
static inline bool map_fill_detail_ops(MCInst *MI) {
assert(MI);
return MI->fillDetailOps;
}
void map_set_is_alias_insn(MCInst *MI, bool Val, uint64_t Alias);
bool map_use_alias_details(const MCInst *MI);
void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_id_map, int map_size);
#endif // CS_MAPPING_H

32
SStream.c
View File

@ -24,8 +24,26 @@
void SStream_Init(SStream *ss)
{
assert(ss);
ss->index = 0;
ss->buffer[0] = '\0';
ss->is_closed = false;
}
/**
* Open the output stream. Every write attempt is accepted again.
*/
void SStream_Open(SStream *ss) {
assert(ss);
ss->is_closed = false;
}
/**
* Closes the output stream. Every write attempt is ignored.
*/
void SStream_Close(SStream *ss) {
assert(ss);
ss->is_closed = true;
}
/**
@ -34,6 +52,7 @@ void SStream_Init(SStream *ss)
void SStream_concat0(SStream *ss, const char *s)
{
#ifndef CAPSTONE_DIET
SSTREAM_RETURN_IF_CLOSED(ss);
if (s[0] == '\0')
return;
unsigned int len = (unsigned int) strlen(s);
@ -50,6 +69,7 @@ void SStream_concat0(SStream *ss, const char *s)
void SStream_concat1(SStream *ss, const char c)
{
#ifndef CAPSTONE_DIET
SSTREAM_RETURN_IF_CLOSED(ss);
if (c == '\0')
return;
ss->buffer[ss->index] = c;
@ -64,6 +84,7 @@ void SStream_concat1(SStream *ss, const char c)
void SStream_concat(SStream *ss, const char *fmt, ...)
{
#ifndef CAPSTONE_DIET
SSTREAM_RETURN_IF_CLOSED(ss);
va_list ap;
int ret;
@ -77,6 +98,7 @@ void SStream_concat(SStream *ss, const char *fmt, ...)
// print number with prefix #
void printInt64Bang(SStream *O, int64_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%"PRIx64, val);
@ -95,6 +117,7 @@ void printInt64Bang(SStream *O, int64_t val)
void printUInt64Bang(SStream *O, uint64_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%"PRIx64, val);
else
@ -104,6 +127,7 @@ void printUInt64Bang(SStream *O, uint64_t val)
// print number
void printInt64(SStream *O, int64_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, val);
@ -122,6 +146,7 @@ void printInt64(SStream *O, int64_t val)
void printUInt64(SStream *O, uint64_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, val);
else
@ -131,6 +156,7 @@ void printUInt64(SStream *O, uint64_t val)
// print number in decimal mode
void printInt32BangDec(SStream *O, int32_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val >= 0)
SStream_concat(O, "#%u", val);
else {
@ -143,6 +169,7 @@ void printInt32BangDec(SStream *O, int32_t val)
void printInt32Bang(SStream *O, int32_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", val);
@ -161,6 +188,7 @@ void printInt32Bang(SStream *O, int32_t val)
void printInt32(SStream *O, int32_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%x", val);
@ -179,6 +207,7 @@ void printInt32(SStream *O, int32_t val)
void printUInt32Bang(SStream *O, uint32_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", val);
else
@ -187,6 +216,7 @@ void printUInt32Bang(SStream *O, uint32_t val)
void printUInt32(SStream *O, uint32_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%x", val);
else
@ -195,10 +225,12 @@ void printUInt32(SStream *O, uint32_t val)
void printFloat(SStream *O, float val)
{
SSTREAM_RETURN_IF_CLOSED(O);
SStream_concat(O, "%e", val);
}
void printFloatBang(SStream *O, float val)
{
SSTREAM_RETURN_IF_CLOSED(O);
SStream_concat(O, "#%e", val);
}

11
SStream.h
View File

@ -9,10 +9,21 @@
typedef struct SStream {
char buffer[512];
int index;
bool is_closed;
} SStream;
#define SSTREAM_RETURN_IF_CLOSED(OS) \
do { \
if (OS->is_closed) \
return; \
} while(0)
void SStream_Init(SStream *ss);
void SStream_Open(SStream *ss);
void SStream_Close(SStream *ss);
void SStream_concat(SStream *ss, const char *fmt, ...);
void SStream_concat0(SStream *ss, const char *s);

182
arch/AArch64/AArch64InstPrinter.c
View File

@ -67,7 +67,7 @@ static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int inde
static void op_addImm(MCInst *MI, int v)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = v;
MI->flat_insn->detail->arm64.op_count++;
@ -79,7 +79,7 @@ static void set_sme_index(MCInst *MI, bool status)
// Doing SME Index operand
MI->csh->doing_SME_Index = status;
if (MI->csh->detail != CS_OPT_ON)
if (MI->csh->detail_opt != CS_OPT_ON)
return;
if (status) {
@ -105,7 +105,7 @@ static void set_mem_access(MCInst *MI, bool status)
MI->csh->doing_mem = status;
if (MI->csh->detail != CS_OPT_ON)
if (MI->csh->detail_opt != CS_OPT_ON)
return;
if (status) {
@ -181,7 +181,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
getRegisterName(getWRegFromXReg(MCOperand_getReg(Op1)), AArch64_NoRegAltName));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -246,7 +246,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -292,7 +292,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz"));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -342,7 +342,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfx" : "ubfx"));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -402,7 +402,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
printInt32Bang(O, Width);
MCInst_setOpcodePub(MI, AArch64_map_insn("bfc"));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -448,7 +448,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
MCInst_setOpcodePub(MI, AArch64_map_insn("bfi"));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -500,7 +500,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil"));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -556,7 +556,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
printInt64Bang(O, SignExtend64(Value, RegWidth));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -592,7 +592,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
printInt64Bang(O, SignExtend64(Value, RegWidth));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -625,7 +625,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
printInt64Bang(O, SignExtend64(Value, RegWidth));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -730,7 +730,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
case AArch64_CPY_ZPmV_B:
case AArch64_CPY_ZPmR_B:
case AArch64_DUP_ZR_B:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
}
break;
@ -743,7 +743,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
case AArch64_DUP_ZR_H:
case AArch64_FCPY_ZPmI_H:
case AArch64_FDUP_ZI_H:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
}
break;
@ -756,7 +756,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
case AArch64_DUP_ZR_S:
case AArch64_FCPY_ZPmI_S:
case AArch64_FDUP_ZI_S:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
}
break;
@ -769,47 +769,47 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
case AArch64_DUP_ZR_D:
case AArch64_FCPY_ZPmI_D:
case AArch64_FDUP_ZI_D:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
}
break;
case AArch64_INSvi8lane:
case AArch64_ORR_PPzPP:
case AArch64_ORRS_PPzPP:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1B;
}
break;
case AArch64_INSvi16lane:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1H;
}
break;
case AArch64_INSvi32lane:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1S;
}
break;
case AArch64_INSvi64lane:
case AArch64_ORR_ZZZ:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1D;
}
break;
case AArch64_ORRv16i8:
case AArch64_NOTv16i8:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_16B;
MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_16B;
}
break;
case AArch64_ORRv8i8:
case AArch64_NOTv8i8:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_8B;
MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_8B;
}
@ -820,31 +820,31 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
case AArch64_EORS_PPzPP:
case AArch64_SEL_PPPP:
case AArch64_SEL_ZPZZ_B:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1B;
}
break;
case AArch64_SEL_ZPZZ_D:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1D;
}
break;
case AArch64_SEL_ZPZZ_H:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1H;
}
break;
case AArch64_SEL_ZPZZ_S:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1S;
}
break;
case AArch64_DUP_ZZI_B:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
if (MI->flat_insn->detail->arm64.op_count == 1) {
arm64_op_addReg(MI, ARM64_REG_B0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
@ -854,7 +854,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
}
break;
case AArch64_DUP_ZZI_D:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
if (MI->flat_insn->detail->arm64.op_count == 1) {
arm64_op_addReg(MI, ARM64_REG_D0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
@ -864,7 +864,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
}
break;
case AArch64_DUP_ZZI_H:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
if (MI->flat_insn->detail->arm64.op_count == 1) {
arm64_op_addReg(MI, ARM64_REG_H0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
@ -874,7 +874,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
}
break;
case AArch64_DUP_ZZI_Q:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1Q;
if (MI->flat_insn->detail->arm64.op_count == 1) {
arm64_op_addReg(MI, ARM64_REG_Q0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
@ -884,7 +884,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
}
break;
case AArch64_DUP_ZZI_S:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
if (MI->flat_insn->detail->arm64.op_count == 1) {
arm64_op_addReg(MI, ARM64_REG_S0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
@ -895,7 +895,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
break;
// Hacky detail filling of SMSTART and SMSTOP alias'
case AArch64_MSRpstatesvcrImm1:{
if(MI->csh->detail){
if(MI->csh->detail_opt){
MI->flat_insn->detail->arm64.op_count = 2;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -1006,7 +1006,7 @@ static bool printSysAlias(MCInst *MI, SStream *O)
MCInst_setOpcodePub(MI, AArch64_map_insn(Ins));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#if 0
#ifndef CAPSTONE_DIET
uint8_t access;
@ -1038,7 +1038,7 @@ static void printOperand(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64_REG_INVALID) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = Reg;
@ -1079,7 +1079,7 @@ static void printOperand(MCInst *MI, unsigned OpNum, SStream *O)
printUInt64Bang(O, imm);
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm;
} else if (MI->csh->doing_SME_Index) {
@ -1105,7 +1105,7 @@ static void printImm(MCInst *MI, unsigned OpNum, SStream *O)
MCOperand *Op = MCInst_getOperand(MI, OpNum);
printUInt64Bang(O, MCOperand_getImm(Op));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -1123,7 +1123,7 @@ static void printImmHex(MCInst *MI, unsigned OpNum, SStream *O)
MCOperand *Op = MCInst_getOperand(MI, OpNum);
printUInt64Bang(O, MCOperand_getImm(Op));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -1145,7 +1145,7 @@ static void printSImm(MCInst *MI, unsigned OpNo, SStream *O, int Size) {
else
printInt64Bang(O, MCOperand_getImm(Op));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -1168,7 +1168,7 @@ static void printPostIncOperand(MCInst *MI, unsigned OpNum, SStream *O,
if (Reg == AArch64_XZR) {
printInt32Bang(O, Imm);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -1183,7 +1183,7 @@ static void printPostIncOperand(MCInst *MI, unsigned OpNum, SStream *O,
} else {
SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -1208,7 +1208,7 @@ static void printVRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat0(O, getRegisterName(Reg, AArch64_vreg));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -1227,7 +1227,7 @@ static void printSysCROperand(MCInst *MI, unsigned OpNum, SStream *O)
//assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
SStream_concat(O, "c%u", MCOperand_getImm(Op));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -1251,7 +1251,7 @@ static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O)
printInt32Bang(O, Val);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -1276,7 +1276,7 @@ static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O)
Val = AArch64_AM_decodeLogicalImmediate(Val, 32);
printUInt32Bang(O, (int)Val);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -1312,7 +1312,7 @@ static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O)
break;
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -1338,7 +1338,7 @@ static void printShifter(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, ", %s ", AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val)));
printInt32BangDec(O, AArch64_AM_getShiftValue(Val));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
arm64_shifter shifter = ARM64_SFT_INVALID;
switch(AArch64_AM_getShiftType(Val)) {
@ -1373,7 +1373,7 @@ static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O)
{
SStream_concat0(O, getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -1409,7 +1409,7 @@ static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat0(O, ", lsl ");
printInt32Bang(O, ShiftVal);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal;
}
@ -1421,7 +1421,7 @@ static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
arm64_extender ext = ARM64_EXT_INVALID;
switch(ExtType) {
default: // never reach
@ -1466,7 +1466,7 @@ static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat0(O, " ");
printInt32Bang(O, ShiftVal);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal;
}
@ -1479,7 +1479,7 @@ static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -1502,13 +1502,13 @@ static void printMemExtendImpl(MCInst *MI, bool SignExtend, bool DoShift, unsign
if (IsLSL) {
SStream_concat0(O, "lsl");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL;
}
} else {
SStream_concat(O, "%cxt%c", (SignExtend ? 's' : 'u'), SrcRegKind);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (!SignExtend) {
switch(SrcRegKind) {
default: break;
@ -1545,7 +1545,7 @@ static void printMemExtendImpl(MCInst *MI, bool SignExtend, bool DoShift, unsign
if (DoShift || IsLSL) {
SStream_concat(O, " #%u", Log2_32(Width / 8));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = Log2_32(Width / 8);
}
@ -1583,7 +1583,7 @@ static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O)
AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
SStream_concat0(O, getCondCodeName(CC));
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->arm64.cc = (arm64_cc)(CC + 1);
}
@ -1592,7 +1592,7 @@ static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O)
AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
SStream_concat0(O, getCondCodeName(getInvertedCondCode(CC)));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.cc = (arm64_cc)(getInvertedCondCode(CC) + 1);
}
}
@ -1603,7 +1603,7 @@ static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale)
printInt64Bang(O, val);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
} else {
@ -1629,7 +1629,7 @@ static void printUImm12Offset(MCInst *MI, unsigned OpNum, SStream *O, unsigned S
int64_t val = Scale * MCOperand_getImm(MO);
printInt64Bang(O, val);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
} else {
@ -1691,7 +1691,7 @@ static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O, bool IsSVEPr
printInt32Bang(O, prfop);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -1739,7 +1739,7 @@ static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "#%.8f", FPImm);
#endif
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -1783,7 +1783,7 @@ static void printGPRSeqPairsClassOperand(MCInst *MI, unsigned OpNum, SStream *O,
SStream_concat(O, "%s, %s", getRegisterName(Even, AArch64_NoRegAltName),
getRegisterName(Odd, AArch64_NoRegAltName));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -1848,7 +1848,7 @@ static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
else
SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -1980,7 +1980,7 @@ static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
printInt32(O, (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
SStream_concat0(O, "]");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vector_index = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
}
}
@ -1995,7 +1995,7 @@ static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O)
uint64_t imm = (MCOperand_getImm(Op) * 4) + MI->address;
printUInt64Bang(O, imm);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2020,7 +2020,7 @@ static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O)
uint64_t imm = (MCOperand_getImm(Op) * 0x1000) + (MI->address & ~0xfff);
printUInt64Bang(O, imm);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2055,7 +2055,7 @@ static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O)
if (Name) {
SStream_concat0(O, Name);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2070,7 +2070,7 @@ static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O)
} else {
printUInt32Bang(O, Val);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2096,7 +2096,7 @@ static void printBarriernXSOption(MCInst *MI, unsigned OpNo, SStream *O) {
if (Name) {
SStream_concat0(O, Name);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2112,7 +2112,7 @@ static void printBarriernXSOption(MCInst *MI, unsigned OpNo, SStream *O) {
else {
printUInt32Bang(O, Val);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2138,7 +2138,7 @@ static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
if (Val == ARM64_SYSREG_DBGDTRRX_EL0) {
SStream_concat0(O, "dbgdtrrx_el0");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2160,7 +2160,7 @@ static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
if( Val == ARM64_SYSREG_VSCTLR_EL2){
SStream_concat0(O, "ttbr0_el2");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2181,7 +2181,7 @@ static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
if (Reg && Reg->Readable) {
SStream_concat0(O, Reg->Name);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2200,7 +2200,7 @@ static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
AArch64SysReg_genericRegisterString(Val, result);
SStream_concat0(O, result);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -2225,7 +2225,7 @@ static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
if (Val == ARM64_SYSREG_DBGDTRTX_EL0) {
SStream_concat0(O, "dbgdtrtx_el0");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2247,7 +2247,7 @@ static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
if( Val == ARM64_SYSREG_VSCTLR_EL2){
SStream_concat0(O, "ttbr0_el2");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2268,7 +2268,7 @@ static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
if (Reg && Reg->Writeable) {
SStream_concat0(O, Reg->Name);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2287,7 +2287,7 @@ static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
AArch64SysReg_genericRegisterString(Val, result);
SStream_concat0(O, result);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -2310,7 +2310,7 @@ static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O)
if (PState) {
SStream_concat0(O, PState->Name);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@ -2324,7 +2324,7 @@ static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O)
} else {
printUInt32Bang(O, Val);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
unsigned char access;
@ -2347,7 +2347,7 @@ static void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "#%#016llx", Val);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
unsigned char access;
@ -2377,7 +2377,7 @@ static void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O)
// assert(svcr && "Unexpected SVCR operand!");
SStream_concat0(O, svcr->Name);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2426,7 +2426,7 @@ static void printMatrix(MCInst *MI, unsigned OpNum, SStream *O, int EltSize)
}
SStream_concat0(O, sizeStr);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2446,7 +2446,7 @@ static void printMatrixIndex(MCInst *MI, unsigned OpNum, SStream *O)
int64_t imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
printInt64(O, imm);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_SME_Index) {
// Access op_count-1 as We want to add info to previous operand, not create a new one
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.disp = imm;
@ -2461,7 +2461,7 @@ static void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O)
unsigned Reg = MCOperand_getReg(RegOp);
SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2502,7 +2502,7 @@ static void printMatrixTileVector(MCInst *MI, unsigned OpNum, SStream *O, bool I
SStream_concat0(O, RegNameNew);
#endif
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2542,7 +2542,7 @@ static void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O){
continue;
SStream_concat0(O, getRegisterName(MatrixZADRegisterTable[J], AArch64_NoRegAltName));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2595,7 +2595,7 @@ static void printSVERegOp(MCInst *MI, unsigned OpNum, SStream *O, char suffix)
Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2715,7 +2715,7 @@ static void printZPRasFPR(MCInst *MI, unsigned OpNum, SStream *O, int Width)
SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access;
@ -2758,10 +2758,10 @@ static void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O)
void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst *mci)
{
if (((cs_struct *)handle)->detail != CS_OPT_ON)
if (((cs_struct *)handle)->detail_opt != CS_OPT_ON)
return;
if (mci->csh->detail) {
if (mci->csh->detail_opt) {
unsigned opcode = MCInst_getOpcode(mci);
switch (opcode) {

12
arch/AArch64/AArch64Mapping.c
View File

@ -410,10 +410,10 @@ void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
if (i != 0) {
insn->id = insns[i].mapid;
if (h->detail) {
if (h->detail_opt) {
#ifndef CAPSTONE_DIET
cs_struct handle;
handle.detail = h->detail;
handle.detail_opt = h->detail_opt;
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
@ -768,7 +768,7 @@ arm64_sys_op AArch64_map_sys_op(const char *name)
void arm64_op_addReg(MCInst *MI, int reg)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = reg;
MI->flat_insn->detail->arm64.op_count++;
@ -777,14 +777,14 @@ void arm64_op_addReg(MCInst *MI, int reg)
void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vas = sp;
}
}
void arm64_op_addFP(MCInst *MI, float fp)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = fp;
MI->flat_insn->detail->arm64.op_count++;
@ -793,7 +793,7 @@ void arm64_op_addFP(MCInst *MI, float fp)
void arm64_op_addImm(MCInst *MI, int64_t imm)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)imm;
MI->flat_insn->detail->arm64.op_count++;

4
arch/ARM/ARMMapping.c
View File

@ -826,7 +826,7 @@ static void add_cs_detail_RegImmShift(MCInst *MI, ARM_AM_ShiftOpc ShOpc,
if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm))
return;
if (!MI->csh->detail)
if (!detail_is_set(MI))
return;
if (doing_mem(MI))
@ -850,7 +850,7 @@ static void add_cs_detail_RegImmShift(MCInst *MI, ARM_AM_ShiftOpc ShOpc,
static void add_cs_detail_general(MCInst *MI, arm_op_group op_group,
unsigned OpNum)
{
if (!MI->csh->detail)
if (!detail_is_set(MI))
return;
cs_op_type op_type = map_get_op_type(MI, OpNum);

2
arch/EVM/EVMMapping.c
View File

@ -37,7 +37,7 @@ void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
insn->id = id;
#ifndef CAPSTONE_DIET
if (evm_insn_find(insns, ARR_SIZE(insns), id) > 0) {
if (h->detail) {
if (h->detail_opt) {
memcpy(&insn->detail->evm, &insns[id], sizeof(insns[id]));
}
}

14
arch/Mips/MipsInstPrinter.c
View File

@ -89,7 +89,7 @@ static void set_mem_access(MCInst *MI, bool status)
{
MI->csh->doing_mem = status;
if (MI->csh->detail != CS_OPT_ON)
if (MI->csh->detail_opt != CS_OPT_ON)
return;
if (status) {
@ -193,7 +193,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
reg = Mips_map_register(reg);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg;
} else {
@ -208,12 +208,12 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
if (imm) { // only print Imm offset if it is not 0
printInt64(O, imm);
}
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
} else {
printInt64(O, imm);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
MI->flat_insn->detail->mips.op_count++;
@ -229,7 +229,7 @@ static void printUnsignedImm(MCInst *MI, int opNum, SStream *O)
int64_t imm = MCOperand_getImm(MO);
printInt64(O, imm);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm;
MI->flat_insn->detail->mips.op_count++;
@ -247,7 +247,7 @@ static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O)
SStream_concat(O, "0x%x", imm);
else
SStream_concat(O, "%u", imm);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
MI->flat_insn->detail->mips.op_count++;
@ -410,7 +410,7 @@ static void printRegisterList(MCInst *MI, int opNum, SStream *O)
SStream_concat0(O, ", ");
reg = MCOperand_getReg(MCInst_getOperand(MI, i));
printRegName(O, reg);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
MI->flat_insn->detail->mips.op_count++;

2
arch/Mips/MipsMapping.c
View File

@ -232,7 +232,7 @@ void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
if (i != 0) {
insn->id = insns[i].mapid;
if (h->detail) {
if (h->detail_opt) {
#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);

771
arch/PowerPC/PPCDisassembler.c
View File

@ -1,367 +1,305 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifdef CAPSTONE_HAS_POWERPC
#include <stdio.h> // DEBUG
#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "../../cs_priv.h"
#include "../../utils.h"
#include "PPCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../MCRegisterInfo.h"
#include "../../LEB128.h"
#include "../../MCDisassembler.h"
#include "../../MathExtras.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../MCInst.h"
#include "../../MCInstPrinter.h"
#include "../../MCInstrDesc.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "../../utils.h"
#include "PPCLinkage.h"
#include "PPCMapping.h"
#include "PPCMCTargetDesc.h"
#include "PPCPredicates.h"
#define GET_REGINFO_ENUM
#include "PPCGenRegisterInfo.inc"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
DEFINE_PPC_REGCLASSES
#define DEBUG_TYPE "ppc-disassembler"
DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
MCInst *MI, uint16_t *Size, uint64_t Address,
void *Info)
;
// end anonymous namespace
static DecodeStatus decodeCondBrTarget(MCInst *Inst, unsigned Imm,
uint64_t Address,
const void *Decoder)
{
MCOperand_CreateImm0(Inst, (SignExtend32((Imm), 14)));
return MCDisassembler_Success;
}
static DecodeStatus decodeDirectBrTarget(MCInst *Inst, unsigned Imm,
uint64_t Address,
const void *Decoder)
{
int32_t Offset = SignExtend32((Imm), 24);
MCOperand_CreateImm0(Inst, (Offset));
return MCDisassembler_Success;
}
// FIXME: These can be generated by TableGen from the existing register
// encoding values!
static const unsigned CRRegs[] = {
PPC_CR0, PPC_CR1, PPC_CR2, PPC_CR3,
PPC_CR4, PPC_CR5, PPC_CR6, PPC_CR7
};
static const unsigned CRBITRegs[] = {
PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN,
PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN,
PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN,
PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN,
PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN,
PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN,
PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN,
PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN
};
static const unsigned FRegs[] = {
PPC_F0, PPC_F1, PPC_F2, PPC_F3,
PPC_F4, PPC_F5, PPC_F6, PPC_F7,
PPC_F8, PPC_F9, PPC_F10, PPC_F11,
PPC_F12, PPC_F13, PPC_F14, PPC_F15,
PPC_F16, PPC_F17, PPC_F18, PPC_F19,
PPC_F20, PPC_F21, PPC_F22, PPC_F23,
PPC_F24, PPC_F25, PPC_F26, PPC_F27,
PPC_F28, PPC_F29, PPC_F30, PPC_F31
};
static const unsigned VFRegs[] = {
PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3,
PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7,
PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11,
PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15,
PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19,
PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23,
PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27,
PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31
};
static const unsigned VRegs[] = {
PPC_V0, PPC_V1, PPC_V2, PPC_V3,
PPC_V4, PPC_V5, PPC_V6, PPC_V7,
PPC_V8, PPC_V9, PPC_V10, PPC_V11,
PPC_V12, PPC_V13, PPC_V14, PPC_V15,
PPC_V16, PPC_V17, PPC_V18, PPC_V19,
PPC_V20, PPC_V21, PPC_V22, PPC_V23,
PPC_V24, PPC_V25, PPC_V26, PPC_V27,
PPC_V28, PPC_V29, PPC_V30, PPC_V31
};
static const unsigned VSRegs[] = {
PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3,
PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7,
PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11,
PPC_VSL12, PPC_VSL13, PPC_VSL14, PPC_VSL15,
PPC_VSL16, PPC_VSL17, PPC_VSL18, PPC_VSL19,
PPC_VSL20, PPC_VSL21, PPC_VSL22, PPC_VSL23,
PPC_VSL24, PPC_VSL25, PPC_VSL26, PPC_VSL27,
PPC_VSL28, PPC_VSL29, PPC_VSL30, PPC_VSL31,
PPC_V0, PPC_V1, PPC_V2, PPC_V3,
PPC_V4, PPC_V5, PPC_V6, PPC_V7,
PPC_V8, PPC_V9, PPC_V10, PPC_V11,
PPC_V12, PPC_V13, PPC_V14, PPC_V15,
PPC_V16, PPC_V17, PPC_V18, PPC_V19,
PPC_V20, PPC_V21, PPC_V22, PPC_V23,
PPC_V24, PPC_V25, PPC_V26, PPC_V27,
PPC_V28, PPC_V29, PPC_V30, PPC_V31
};
static const unsigned VSFRegs[] = {
PPC_F0, PPC_F1, PPC_F2, PPC_F3,
PPC_F4, PPC_F5, PPC_F6, PPC_F7,
PPC_F8, PPC_F9, PPC_F10, PPC_F11,
PPC_F12, PPC_F13, PPC_F14, PPC_F15,
PPC_F16, PPC_F17, PPC_F18, PPC_F19,
PPC_F20, PPC_F21, PPC_F22, PPC_F23,
PPC_F24, PPC_F25, PPC_F26, PPC_F27,
PPC_F28, PPC_F29, PPC_F30, PPC_F31,
PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3,
PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7,
PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11,
PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15,
PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19,
PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23,
PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27,
PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31
};
static const unsigned VSSRegs[] = {
PPC_F0, PPC_F1, PPC_F2, PPC_F3,
PPC_F4, PPC_F5, PPC_F6, PPC_F7,
PPC_F8, PPC_F9, PPC_F10, PPC_F11,
PPC_F12, PPC_F13, PPC_F14, PPC_F15,
PPC_F16, PPC_F17, PPC_F18, PPC_F19,
PPC_F20, PPC_F21, PPC_F22, PPC_F23,
PPC_F24, PPC_F25, PPC_F26, PPC_F27,
PPC_F28, PPC_F29, PPC_F30, PPC_F31,
PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3,
PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7,
PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11,
PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15,
PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19,
PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23,
PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27,
PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31
};
static const unsigned GPRegs[] = {
PPC_R0, PPC_R1, PPC_R2, PPC_R3,
PPC_R4, PPC_R5, PPC_R6, PPC_R7,
PPC_R8, PPC_R9, PPC_R10, PPC_R11,
PPC_R12, PPC_R13, PPC_R14, PPC_R15,
PPC_R16, PPC_R17, PPC_R18, PPC_R19,
PPC_R20, PPC_R21, PPC_R22, PPC_R23,
PPC_R24, PPC_R25, PPC_R26, PPC_R27,
PPC_R28, PPC_R29, PPC_R30, PPC_R31
};
static const unsigned GP0Regs[] = {
PPC_ZERO, PPC_R1, PPC_R2, PPC_R3,
PPC_R4, PPC_R5, PPC_R6, PPC_R7,
PPC_R8, PPC_R9, PPC_R10, PPC_R11,
PPC_R12, PPC_R13, PPC_R14, PPC_R15,
PPC_R16, PPC_R17, PPC_R18, PPC_R19,
PPC_R20, PPC_R21, PPC_R22, PPC_R23,
PPC_R24, PPC_R25, PPC_R26, PPC_R27,
PPC_R28, PPC_R29, PPC_R30, PPC_R31
};
static const unsigned G8Regs[] = {
PPC_X0, PPC_X1, PPC_X2, PPC_X3,
PPC_X4, PPC_X5, PPC_X6, PPC_X7,
PPC_X8, PPC_X9, PPC_X10, PPC_X11,
PPC_X12, PPC_X13, PPC_X14, PPC_X15,
PPC_X16, PPC_X17, PPC_X18, PPC_X19,
PPC_X20, PPC_X21, PPC_X22, PPC_X23,
PPC_X24, PPC_X25, PPC_X26, PPC_X27,
PPC_X28, PPC_X29, PPC_X30, PPC_X31
};
static const unsigned G80Regs[] = {
PPC_ZERO8, PPC_X1, PPC_X2, PPC_X3,
PPC_X4, PPC_X5, PPC_X6, PPC_X7,
PPC_X8, PPC_X9, PPC_X10, PPC_X11,
PPC_X12, PPC_X13, PPC_X14, PPC_X15,
PPC_X16, PPC_X17, PPC_X18, PPC_X19,
PPC_X20, PPC_X21, PPC_X22, PPC_X23,
PPC_X24, PPC_X25, PPC_X26, PPC_X27,
PPC_X28, PPC_X29, PPC_X30, PPC_X31
};
static const unsigned QFRegs[] = {
PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3,
PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7,
PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11,
PPC_QF12, PPC_QF13, PPC_QF14, PPC_QF15,
PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19,
PPC_QF20, PPC_QF21, PPC_QF22, PPC_QF23,
PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27,
PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31
};
static const unsigned SPERegs[] = {
PPC_S0, PPC_S1, PPC_S2, PPC_S3,
PPC_S4, PPC_S5, PPC_S6, PPC_S7,
PPC_S8, PPC_S9, PPC_S10, PPC_S11,
PPC_S12, PPC_S13, PPC_S14, PPC_S15,
PPC_S16, PPC_S17, PPC_S18, PPC_S19,
PPC_S20, PPC_S21, PPC_S22, PPC_S23,
PPC_S24, PPC_S25, PPC_S26, PPC_S27,
PPC_S28, PPC_S29, PPC_S30, PPC_S31
};
#if 0
static uint64_t getFeatureBits(int feature)
{
// enable all features
return (uint64_t)-1;
}
#endif
static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo,
const unsigned *Regs, size_t RegsLen)
const MCPhysReg *Regs)
{
if (RegNo >= RegsLen / sizeof(unsigned)) {
return MCDisassembler_Fail;
}
MCOperand_CreateReg0(Inst, Regs[RegNo]);
MCOperand_CreateReg0(Inst, (Regs[RegNo]));
return MCDisassembler_Success;
}
static DecodeStatus DecodeCRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, CRRegs, sizeof(CRRegs));
return decodeRegisterClass(Inst, RegNo, CRRegs);
}
#if 0
static DecodeStatus DecodeCRRC0RegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, CRRegs, sizeof(CRRegs));
}
#endif
static DecodeStatus DecodeCRBITRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, CRBITRegs, sizeof(CRBITRegs));
return decodeRegisterClass(Inst, RegNo, CRBITRegs);
}
static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, FRegs, sizeof(FRegs));
return decodeRegisterClass(Inst, RegNo, FRegs);
}
static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, FRegs, sizeof(FRegs));
return decodeRegisterClass(Inst, RegNo, FRegs);
}
static DecodeStatus DecodeVFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, VFRegs, sizeof(VFRegs));
return decodeRegisterClass(Inst, RegNo, VFRegs);
}
static DecodeStatus DecodeVRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, VRegs, sizeof(VRegs));
return decodeRegisterClass(Inst, RegNo, VRegs);
}
static DecodeStatus DecodeVSRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, VSRegs, sizeof(VSRegs));
return decodeRegisterClass(Inst, RegNo, VSRegs);
}
static DecodeStatus DecodeVSFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, VSFRegs, sizeof(VSFRegs));
return decodeRegisterClass(Inst, RegNo, VSFRegs);
}
static DecodeStatus DecodeVSSRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, VSSRegs, sizeof(VSSRegs));
return decodeRegisterClass(Inst, RegNo, VSSRegs);
}
static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, GPRegs, sizeof(GPRegs));
return decodeRegisterClass(Inst, RegNo, RRegs);
}
static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, GP0Regs, sizeof(GP0Regs));
return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
}
static DecodeStatus DecodeG8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, G8Regs, sizeof(G8Regs));
return decodeRegisterClass(Inst, RegNo, XRegs);
}
static DecodeStatus DecodeG8pRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, XRegs);
}
static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, G80Regs, sizeof(G80Regs));
return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
}
#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
static DecodeStatus DecodeQFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, QFRegs, sizeof(QFRegs));
}
static DecodeStatus DecodeSPE4RCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, GPRegs, sizeof(GPRegs));
}
static DecodeStatus DecodeSPERCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, SPERegs, sizeof(SPERegs));
return decodeRegisterClass(Inst, RegNo, SPERegs);
}
static DecodeStatus DecodeACCRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, ACCRegs);
}
static DecodeStatus DecodeWACCRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, WACCRegs);
}
static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, WACC_HIRegs);
}
// TODO: Make this function static when the register class is used by a new
// instruction.
DecodeStatus DecodeDMRROWRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, DMRROWRegs);
}
static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, DMRROWpRegs);
}
static DecodeStatus DecodeDMRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, DMRRegs);
}
// TODO: Make this function static when the register class is used by a new
// instruction.
DecodeStatus DecodeDMRpRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, DMRpRegs);
}
static DecodeStatus DecodeVSRpRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
return decodeRegisterClass(Inst, RegNo, VSRpRegs);
}
#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder, unsigned N)
static DecodeStatus DecodeQFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
{
//assert(isUInt<N>(Imm) && "Invalid immediate");
MCOperand_CreateImm0(Inst, Imm);
return decodeRegisterClass(Inst, RegNo, QFRegs);
}
#define DEFINE_decodeUImmOperand(N) \
static DecodeStatus CONCAT(decodeUImmOperand, N)( \
MCInst * Inst, uint64_t Imm, int64_t Address, const void *Decoder) \
{ \
\
MCOperand_CreateImm0(Inst, (Imm)); \
return MCDisassembler_Success; \
}
DEFINE_decodeUImmOperand(5) DEFINE_decodeUImmOperand(16)
DEFINE_decodeUImmOperand(6) DEFINE_decodeUImmOperand(10)
DEFINE_decodeUImmOperand(8) DEFINE_decodeUImmOperand(7)
DEFINE_decodeUImmOperand(12)
#define DEFINE_decodeSImmOperand(N) \
static DecodeStatus CONCAT(decodeSImmOperand, N)( \
MCInst * Inst, uint64_t Imm, int64_t Address, const void *Decoder) \
{ \
\
MCOperand_CreateImm0(Inst, (SignExtend64(Imm, N))); \
return MCDisassembler_Success; \
}
DEFINE_decodeSImmOperand(16) DEFINE_decodeSImmOperand(5)
DEFINE_decodeSImmOperand(34)
static DecodeStatus
decodeImmZeroOperand(MCInst *Inst, uint64_t Imm, int64_t Address,
const void *Decoder)
{
if (Imm != 0)
return MCDisassembler_Fail;
MCOperand_CreateImm0(Inst, (Imm));
return MCDisassembler_Success;
}
static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder, unsigned N)
static DecodeStatus decodeVSRpEvenOperands(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
// assert(isUInt<N>(Imm) && "Invalid immediate");
MCOperand_CreateImm0(Inst, SignExtend64(Imm, N));
if (RegNo & 1)
return MCDisassembler_Fail;
MCOperand_CreateReg0(Inst, (VSRpRegs[RegNo >> 1]));
return MCDisassembler_Success;
}
#define GET_INSTRINFO_ENUM
#include "PPCGenInstrInfo.inc"
static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
int64_t Address, const void *Decoder)
{
// Decode the memri field (imm, reg), which has the low 16-bits as the
// displacement and the next 5 bits as the register #.
@ -369,38 +307,34 @@ static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm,
uint64_t Base = Imm >> 16;
uint64_t Disp = Imm & 0xFFFF;
// assert(Base < 32 && "Invalid base register");
if (Base >= 32)
return MCDisassembler_Fail;
switch (MCInst_getOpcode(Inst)) {
default: break;
case PPC_LBZU:
case PPC_LHAU:
case PPC_LHZU:
case PPC_LWZU:
case PPC_LFSU:
case PPC_LFDU:
// Add the tied output operand.
MCOperand_CreateReg0(Inst, GP0Regs[Base]);
break;
case PPC_STBU:
case PPC_STHU:
case PPC_STWU:
case PPC_STFSU:
case PPC_STFDU:
MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base]));
break;
default:
break;
case PPC_LBZU:
case PPC_LHAU:
case PPC_LHZU:
case PPC_LWZU:
case PPC_LFSU:
case PPC_LFDU:
// Add the tied output operand.
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
break;
case PPC_STBU:
case PPC_STHU:
case PPC_STWU:
case PPC_STFSU:
case PPC_STFDU:
MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, RRegsNoR0[Base]));
break;
}
MCOperand_CreateImm0(Inst, SignExtend64(Disp, 16));
MCOperand_CreateReg0(Inst, GP0Regs[Base]);
MCOperand_CreateImm0(Inst, (SignExtend64(Disp, 16)));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
int64_t Address, const void *Decoder)
{
// Decode the memrix field (imm, reg), which has the low 14-bits as the
// displacement and the next 5 bits as the register #.
@ -408,24 +342,35 @@ static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm,
uint64_t Base = Imm >> 14;
uint64_t Disp = Imm & 0x3FFF;
// assert(Base < 32 && "Invalid base register");
if (Base >= 32)
return MCDisassembler_Fail;
if (MCInst_getOpcode(Inst) == PPC_LDU)
// Add the tied output operand.
MCOperand_CreateReg0(Inst, GP0Regs[Base]);
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
else if (MCInst_getOpcode(Inst) == PPC_STDU)
MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base]));
MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, RRegsNoR0[Base]));
MCOperand_CreateImm0(Inst, SignExtend64(Disp << 2, 16));
MCOperand_CreateReg0(Inst, GP0Regs[Base]);
MCOperand_CreateImm0(Inst, (SignExtend64(Disp << 2, 16)));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRIHashOperands(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
// Decode the memrix field for a hash store or hash check operation.
// The field is composed of a register and an immediate value that is 6 bits
// and covers the range -8 to -512. The immediate is always negative and 2s
// complement which is why we sign extend a 7 bit value.
const uint64_t Base = Imm >> 6;
const int64_t Disp = SignExtend64((Imm & 0x3F) + 64, 7) * 8;
MCOperand_CreateImm0(Inst, (Disp));
MCOperand_CreateReg0(Inst, (RRegs[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRIX16Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
int64_t Address, const void *Decoder)
{
// Decode the memrix16 field (imm, reg), which has the low 12-bits as the
// displacement with 16-byte aligned, and the next 5 bits as the register #.
@ -433,18 +378,39 @@ static DecodeStatus decodeMemRIX16Operands(MCInst *Inst, uint64_t Imm,
uint64_t Base = Imm >> 12;
uint64_t Disp = Imm & 0xFFF;
// assert(Base < 32 && "Invalid base register");
if (Base >= 32)
return MCDisassembler_Fail;
MCOperand_CreateImm0(Inst, (SignExtend64(Disp << 4, 16)));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
MCOperand_CreateImm0(Inst, SignExtend64(Disp << 4, 16));
MCOperand_CreateReg0(Inst, GP0Regs[Base]);
static DecodeStatus decodeMemRI34PCRelOperands(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
// Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as
// the displacement, and the next 5 bits as an immediate 0.
uint64_t Base = Imm >> 34;
uint64_t Disp = Imm & 0x3FFFFFFFFUL;
MCOperand_CreateImm0(Inst, (SignExtend64(Disp, 34)));
return decodeImmZeroOperand(Inst, Base, Address, Decoder);
}
static DecodeStatus decodeMemRI34Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the memri34 field (imm, reg), which has the low 34-bits as the
// displacement, and the next 5 bits as the register #.
uint64_t Base = Imm >> 34;
uint64_t Disp = Imm & 0x3FFFFFFFFUL;
MCOperand_CreateImm0(Inst, (SignExtend64(Disp, 34)));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeSPE8Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
int64_t Address, const void *Decoder)
{
// Decode the spe8disp field (imm, reg), which has the low 5-bits as the
// displacement with 8-byte aligned, and the next 5 bits as the register #.
@ -452,18 +418,13 @@ static DecodeStatus decodeSPE8Operands(MCInst *Inst, uint64_t Imm,
uint64_t Base = Imm >> 5;
uint64_t Disp = Imm & 0x1F;
// assert(Base < 32 && "Invalid base register");
if (Base >= 32)
return MCDisassembler_Fail;
MCOperand_CreateImm0(Inst, Disp << 3);
MCOperand_CreateReg0(Inst, GP0Regs[Base]);
MCOperand_CreateImm0(Inst, (Disp << 3));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeSPE4Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
int64_t Address, const void *Decoder)
{
// Decode the spe4disp field (imm, reg), which has the low 5-bits as the
// displacement with 4-byte aligned, and the next 5 bits as the register #.
@ -471,18 +432,13 @@ static DecodeStatus decodeSPE4Operands(MCInst *Inst, uint64_t Imm,
uint64_t Base = Imm >> 5;
uint64_t Disp = Imm & 0x1F;
// assert(Base < 32 && "Invalid base register");
if (Base >= 32)
return MCDisassembler_Fail;
MCOperand_CreateImm0(Inst, Disp << 2);
MCOperand_CreateReg0(Inst, GP0Regs[Base]);
MCOperand_CreateImm0(Inst, (Disp << 2));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeSPE2Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
int64_t Address, const void *Decoder)
{
// Decode the spe2disp field (imm, reg), which has the low 5-bits as the
// displacement with 2-byte aligned, and the next 5 bits as the register #.
@ -490,138 +446,83 @@ static DecodeStatus decodeSPE2Operands(MCInst *Inst, uint64_t Imm,
uint64_t Base = Imm >> 5;
uint64_t Disp = Imm & 0x1F;
// assert(Base < 32 && "Invalid base register");
if (Base >= 32)
return MCDisassembler_Fail;
MCOperand_CreateImm0(Inst, Disp << 1);
MCOperand_CreateReg0(Inst, GP0Regs[Base]);
MCOperand_CreateImm0(Inst, (Disp << 1));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeCRBitMOperand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
int64_t Address, const void *Decoder)
{
// The cr bit encoding is 0x80 >> cr_reg_num.
unsigned Zeros = CountTrailingZeros_64(Imm);
// assert(Zeros < 8 && "Invalid CR bit value");
unsigned Zeros = CountTrailingZeros_32(Imm);
if (Zeros >= 8)
return MCDisassembler_Fail;
MCOperand_CreateReg0(Inst, CRRegs[7 - Zeros]);
MCOperand_CreateReg0(Inst, (CRRegs[7 - Zeros]));
return MCDisassembler_Success;
}
#include "PPCGenDisassemblerTables.inc"
static DecodeStatus getInstruction(MCInst *MI,
const uint8_t *code, size_t code_len,
uint16_t *Size,
uint64_t Address, MCRegisterInfo *MRI)
DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
MCInst *MI, uint16_t *Size, uint64_t Address,
void *Info)
{
uint32_t insn;
DecodeStatus result;
// If this is an 8-byte prefixed instruction, handle it here.
// Note: prefixed instructions aren't technically 8-byte entities - the
// prefix
// appears in memory at an address 4 bytes prior to that of the base
// instruction regardless of endianness. So we read the two pieces and
// rebuild the 8-byte instruction.
// TODO: In this function we call decodeInstruction several times with
// different decoder tables. It may be possible to only call once by
// looking at the top 6 bits of the instruction.
if (PPC_getFeatureBits(MI->csh->mode, PPC_FeaturePrefixInstrs) &&
BytesLen >= 8) {
uint32_t Prefix = readBytes32(MI, Bytes);
uint32_t BaseInst = readBytes32(MI, Bytes + 4);
uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
DecodeStatus result =
decodeInstruction_4(DecoderTable64, MI, Inst, Address);
if (result != MCDisassembler_Fail) {
*Size = 8;
return result;
}
}
// Get the four bytes of the instruction.
if (code_len < 4) {
// not enough data
*Size = 4;
if (BytesLen < 4) {
*Size = 0;
return MCDisassembler_Fail;
}
// The instruction is big-endian encoded.
if (MODE_IS_BIG_ENDIAN(MI->csh->mode))
insn = ((uint32_t) code[0] << 24) | (code[1] << 16) |
(code[2] << 8) | (code[3] << 0);
else // little endian
insn = ((uint32_t) code[3] << 24) | (code[2] << 16) |
(code[1] << 8) | (code[0] << 0);
// Read the instruction in the proper endianness.
uint64_t Inst = readBytes32(MI, Bytes);
if (MI->flat_insn->detail) {
memset(MI->flat_insn->detail, 0, offsetof(cs_detail, ppc) + sizeof(cs_ppc));
if (PPC_getFeatureBits(MI->csh->mode, PPC_FeatureQPX)) {
DecodeStatus result =
decodeInstruction_4(DecoderTableQPX32, MI, Inst, Address);
if (result != MCDisassembler_Fail)
return result;
} else if (PPC_getFeatureBits(MI->csh->mode, PPC_FeatureSPE)) {
DecodeStatus result =
decodeInstruction_4(DecoderTableSPE32, MI, Inst, Address);
if (result != MCDisassembler_Fail)
return result;
} else if (PPC_getFeatureBits(MI->csh->mode, PPC_FeaturePS)) {
DecodeStatus result = decodeInstruction_4(DecoderTablePS32, MI, Inst, Address);
if (result != MCDisassembler_Fail)
return result;
}
if (MI->csh->mode & CS_MODE_QPX) {
result = decodeInstruction_4(DecoderTableQPX32, MI, insn, Address);
if (result != MCDisassembler_Fail) {
*Size = 4;
return result;
}
// failed to decode
MCInst_clear(MI);
} else if (MI->csh->mode & CS_MODE_SPE) {
result = decodeInstruction_4(DecoderTableSPE32, MI, insn, Address);
if (result != MCDisassembler_Fail) {
*Size = 4;
return result;
}
// failed to decode
MCInst_clear(MI);
} else if (MI->csh->mode & CS_MODE_PS) {
result = decodeInstruction_4(DecoderTablePS32, MI, insn, Address);
if (result != MCDisassembler_Fail) {
*Size = 4;
return result;
}
// failed to decode
MCInst_clear(MI);
}
result = decodeInstruction_4(DecoderTable32, MI, insn, Address);
if (result != MCDisassembler_Fail) {
*Size = 4;
return result;
}
// cannot decode, report error
MCInst_clear(MI);
*Size = 0;
return MCDisassembler_Fail;
return decodeInstruction_4(DecoderTable32, MI, Inst, Address);
}
bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info)
{
DecodeStatus status = getInstruction(instr,
code, code_len,
size,
address, (MCRegisterInfo *)info);
return status == MCDisassembler_Success;
DecodeStatus PPC_LLVM_getInstruction(csh handle, const uint8_t *Bytes, size_t BytesLen,
MCInst *MI, uint16_t *Size, uint64_t Address,
void *Info) {
return getInstruction(handle, Bytes, BytesLen, MI, Size, Address, Info);
}
#define GET_REGINFO_MC_DESC
#include "PPCGenRegisterInfo.inc"
void PPC_init(MCRegisterInfo *MRI)
{
/*
InitMCRegisterInfo(PPCRegDesc, 344,
RA, PC,
PPCMCRegisterClasses, 36,
PPCRegUnitRoots, 171, PPCRegDiffLists, PPCLaneMaskLists, PPCRegStrings, PPCRegClassStrings,
PPCSubRegIdxLists, 7,
PPCSubRegIdxRanges, PPCRegEncodingTable);
*/
MCRegisterInfo_InitMCRegisterInfo(MRI, PPCRegDesc, 344,
0, 0,
PPCMCRegisterClasses, 36,
0, 0,
PPCRegDiffLists,
0,
PPCSubRegIdxLists, 7,
0);
}
#endif

17
arch/PowerPC/PPCDisassembler.h
View File

@ -1,17 +0,0 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifndef CS_PPCDISASSEMBLER_H
#define CS_PPCDISASSEMBLER_H
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
void PPC_init(MCRegisterInfo *MRI);
bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info);
#endif

23774
arch/PowerPC/PPCGenAsmWriter.inc
View File

File diff suppressed because it is too large Load Diff

687
arch/PowerPC/PPCGenCSAliasMnemMap.inc Normal file
View File

@ -0,0 +1,687 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ PPC_INS_ALIAS_RFEBB, "rfebb" },
{ PPC_INS_ALIAS_LI, "li" },
{ PPC_INS_ALIAS_LIS, "lis" },
{ PPC_INS_ALIAS_MR, "mr" },
{ PPC_INS_ALIAS_MR_, "mr." },
{ PPC_INS_ALIAS_NOT, "not" },
{ PPC_INS_ALIAS_NOT_, "not." },
{ PPC_INS_ALIAS_NOP, "nop" },
{ PPC_INS_ALIAS_MTUDSCR, "mtudscr" },
{ PPC_INS_ALIAS_MFUDSCR, "mfudscr" },
{ PPC_INS_ALIAS_MTVRSAVE, "mtvrsave" },
{ PPC_INS_ALIAS_MFVRSAVE, "mfvrsave" },
{ PPC_INS_ALIAS_MTCR, "mtcr" },
{ PPC_INS_ALIAS_SUB, "sub" },
{ PPC_INS_ALIAS_SUB_, "sub." },
{ PPC_INS_ALIAS_SUBC, "subc" },
{ PPC_INS_ALIAS_SUBC_, "subc." },
{ PPC_INS_ALIAS_VMR, "vmr" },
{ PPC_INS_ALIAS_VNOT, "vnot" },
{ PPC_INS_ALIAS_ROTLWI, "rotlwi" },
{ PPC_INS_ALIAS_ROTLWI_, "rotlwi." },
{ PPC_INS_ALIAS_ROTLW, "rotlw" },
{ PPC_INS_ALIAS_ROTLW_, "rotlw." },
{ PPC_INS_ALIAS_CLRLWI, "clrlwi" },
{ PPC_INS_ALIAS_CLRLWI_, "clrlwi." },
{ PPC_INS_ALIAS_ISELLT, "isellt" },
{ PPC_INS_ALIAS_ISELGT, "iselgt" },
{ PPC_INS_ALIAS_ISELEQ, "iseleq" },
{ PPC_INS_ALIAS_XNOP, "xnop" },
{ PPC_INS_ALIAS_CNTLZW, "cntlzw" },
{ PPC_INS_ALIAS_CNTLZW_, "cntlzw." },
{ PPC_INS_ALIAS_MTXER, "mtxer" },
{ PPC_INS_ALIAS_MFXER, "mfxer" },
{ PPC_INS_ALIAS_MFRTCU, "mfrtcu" },
{ PPC_INS_ALIAS_MFRTCL, "mfrtcl" },
{ PPC_INS_ALIAS_MTLR, "mtlr" },
{ PPC_INS_ALIAS_MFLR, "mflr" },
{ PPC_INS_ALIAS_MTCTR, "mtctr" },
{ PPC_INS_ALIAS_MFCTR, "mfctr" },
{ PPC_INS_ALIAS_MTUAMR, "mtuamr" },
{ PPC_INS_ALIAS_MFUAMR, "mfuamr" },
{ PPC_INS_ALIAS_MTDSCR, "mtdscr" },
{ PPC_INS_ALIAS_MFDSCR, "mfdscr" },
{ PPC_INS_ALIAS_MTDSISR, "mtdsisr" },
{ PPC_INS_ALIAS_MFDSISR, "mfdsisr" },
{ PPC_INS_ALIAS_MTDAR, "mtdar" },
{ PPC_INS_ALIAS_MFDAR, "mfdar" },
{ PPC_INS_ALIAS_MTDEC, "mtdec" },
{ PPC_INS_ALIAS_MFDEC, "mfdec" },
{ PPC_INS_ALIAS_MTSDR1, "mtsdr1" },
{ PPC_INS_ALIAS_MFSDR1, "mfsdr1" },
{ PPC_INS_ALIAS_MTSRR0, "mtsrr0" },
{ PPC_INS_ALIAS_MFSRR0, "mfsrr0" },
{ PPC_INS_ALIAS_MTSRR1, "mtsrr1" },
{ PPC_INS_ALIAS_MFSRR1, "mfsrr1" },
{ PPC_INS_ALIAS_MTCFAR, "mtcfar" },
{ PPC_INS_ALIAS_MFCFAR, "mfcfar" },
{ PPC_INS_ALIAS_MTAMR, "mtamr" },
{ PPC_INS_ALIAS_MFAMR, "mfamr" },
{ PPC_INS_ALIAS_MFSPRG, "mfsprg" },
{ PPC_INS_ALIAS_MFSPRG0, "mfsprg0" },
{ PPC_INS_ALIAS_MTSPRG, "mtsprg" },
{ PPC_INS_ALIAS_MTSPRG0, "mtsprg0" },
{ PPC_INS_ALIAS_MFSPRG1, "mfsprg1" },
{ PPC_INS_ALIAS_MTSPRG1, "mtsprg1" },
{ PPC_INS_ALIAS_MFSPRG2, "mfsprg2" },
{ PPC_INS_ALIAS_MTSPRG2, "mtsprg2" },
{ PPC_INS_ALIAS_MFSPRG3, "mfsprg3" },
{ PPC_INS_ALIAS_MTSPRG3, "mtsprg3" },
{ PPC_INS_ALIAS_MFASR, "mfasr" },
{ PPC_INS_ALIAS_MTASR, "mtasr" },
{ PPC_INS_ALIAS_MTTBL, "mttbl" },
{ PPC_INS_ALIAS_MTTBU, "mttbu" },
{ PPC_INS_ALIAS_MFPVR, "mfpvr" },
{ PPC_INS_ALIAS_MFSPEFSCR, "mfspefscr" },
{ PPC_INS_ALIAS_MTSPEFSCR, "mtspefscr" },
{ PPC_INS_ALIAS_XVMOVDP, "xvmovdp" },
{ PPC_INS_ALIAS_XVMOVSP, "xvmovsp" },
{ PPC_INS_ALIAS_XXSPLTD, "xxspltd" },
{ PPC_INS_ALIAS_XXMRGHD, "xxmrghd" },
{ PPC_INS_ALIAS_XXMRGLD, "xxmrgld" },
{ PPC_INS_ALIAS_XXSWAPD, "xxswapd" },
{ PPC_INS_ALIAS_MFFPRD, "mffprd" },
{ PPC_INS_ALIAS_MTFPRD, "mtfprd" },
{ PPC_INS_ALIAS_MFFPRWZ, "mffprwz" },
{ PPC_INS_ALIAS_MTFPRWA, "mtfprwa" },
{ PPC_INS_ALIAS_MTFPRWZ, "mtfprwz" },
{ PPC_INS_ALIAS_TEND_, "tend." },
{ PPC_INS_ALIAS_TENDALL_, "tendall." },
{ PPC_INS_ALIAS_TSUSPEND_, "tsuspend." },
{ PPC_INS_ALIAS_TRESUME_, "tresume." },
{ PPC_INS_ALIAS_DCI, "dci" },
{ PPC_INS_ALIAS_DCCCI, "dccci" },
{ PPC_INS_ALIAS_ICI, "ici" },
{ PPC_INS_ALIAS_ICCCI, "iccci" },
{ PPC_INS_ALIAS_MTFSFI, "mtfsfi" },
{ PPC_INS_ALIAS_MTFSFI_, "mtfsfi." },
{ PPC_INS_ALIAS_MTFSF, "mtfsf" },
{ PPC_INS_ALIAS_MTFSF_, "mtfsf." },
{ PPC_INS_ALIAS_SC, "sc" },
{ PPC_INS_ALIAS_SYNC, "sync" },
{ PPC_INS_ALIAS_LWSYNC, "lwsync" },
{ PPC_INS_ALIAS_PTESYNC, "ptesync" },
{ PPC_INS_ALIAS_WAIT, "wait" },
{ PPC_INS_ALIAS_WAITRSV, "waitrsv" },
{ PPC_INS_ALIAS_WAITIMPL, "waitimpl" },
{ PPC_INS_ALIAS_MBAR, "mbar" },
{ PPC_INS_ALIAS_CRSET, "crset" },
{ PPC_INS_ALIAS_CRCLR, "crclr" },
{ PPC_INS_ALIAS_CRMOVE, "crmove" },
{ PPC_INS_ALIAS_CRNOT, "crnot" },
{ PPC_INS_ALIAS_MFTB, "mftb" },
{ PPC_INS_ALIAS_MFTBL, "mftbl" },
{ PPC_INS_ALIAS_MFTBU, "mftbu" },
{ PPC_INS_ALIAS_MFBR0, "mfbr0" },
{ PPC_INS_ALIAS_MTBR0, "mtbr0" },
{ PPC_INS_ALIAS_MFBR1, "mfbr1" },
{ PPC_INS_ALIAS_MTBR1, "mtbr1" },
{ PPC_INS_ALIAS_MFBR2, "mfbr2" },
{ PPC_INS_ALIAS_MTBR2, "mtbr2" },
{ PPC_INS_ALIAS_MFBR3, "mfbr3" },
{ PPC_INS_ALIAS_MTBR3, "mtbr3" },
{ PPC_INS_ALIAS_MFBR4, "mfbr4" },
{ PPC_INS_ALIAS_MTBR4, "mtbr4" },
{ PPC_INS_ALIAS_MFBR5, "mfbr5" },
{ PPC_INS_ALIAS_MTBR5, "mtbr5" },
{ PPC_INS_ALIAS_MFBR6, "mfbr6" },
{ PPC_INS_ALIAS_MTBR6, "mtbr6" },
{ PPC_INS_ALIAS_MFBR7, "mfbr7" },
{ PPC_INS_ALIAS_MTBR7, "mtbr7" },
{ PPC_INS_ALIAS_MTMSRD, "mtmsrd" },
{ PPC_INS_ALIAS_MTMSR, "mtmsr" },
{ PPC_INS_ALIAS_MTPID, "mtpid" },
{ PPC_INS_ALIAS_MFPID, "mfpid" },
{ PPC_INS_ALIAS_MFSPRG4, "mfsprg4" },
{ PPC_INS_ALIAS_MTSPRG4, "mtsprg4" },
{ PPC_INS_ALIAS_MFSPRG5, "mfsprg5" },
{ PPC_INS_ALIAS_MTSPRG5, "mtsprg5" },
{ PPC_INS_ALIAS_MFSPRG6, "mfsprg6" },
{ PPC_INS_ALIAS_MTSPRG6, "mtsprg6" },
{ PPC_INS_ALIAS_MFSPRG7, "mfsprg7" },
{ PPC_INS_ALIAS_MTSPRG7, "mtsprg7" },
{ PPC_INS_ALIAS_MTDBATU, "mtdbatu" },
{ PPC_INS_ALIAS_MFDBATU, "mfdbatu" },
{ PPC_INS_ALIAS_MTDBATL, "mtdbatl" },
{ PPC_INS_ALIAS_MFDBATL, "mfdbatl" },
{ PPC_INS_ALIAS_MTIBATU, "mtibatu" },
{ PPC_INS_ALIAS_MFIBATU, "mfibatu" },
{ PPC_INS_ALIAS_MTIBATL, "mtibatl" },
{ PPC_INS_ALIAS_MFIBATL, "mfibatl" },
{ PPC_INS_ALIAS_MTPPR, "mtppr" },
{ PPC_INS_ALIAS_MFPPR, "mfppr" },
{ PPC_INS_ALIAS_MTESR, "mtesr" },
{ PPC_INS_ALIAS_MFESR, "mfesr" },
{ PPC_INS_ALIAS_MTDEAR, "mtdear" },
{ PPC_INS_ALIAS_MFDEAR, "mfdear" },
{ PPC_INS_ALIAS_MTTCR, "mttcr" },
{ PPC_INS_ALIAS_MFTCR, "mftcr" },
{ PPC_INS_ALIAS_MFTBHI, "mftbhi" },
{ PPC_INS_ALIAS_MTTBHI, "mttbhi" },
{ PPC_INS_ALIAS_MFTBLO, "mftblo" },
{ PPC_INS_ALIAS_MTTBLO, "mttblo" },
{ PPC_INS_ALIAS_MTSRR2, "mtsrr2" },
{ PPC_INS_ALIAS_MFSRR2, "mfsrr2" },
{ PPC_INS_ALIAS_MTSRR3, "mtsrr3" },
{ PPC_INS_ALIAS_MFSRR3, "mfsrr3" },
{ PPC_INS_ALIAS_MTDCCR, "mtdccr" },
{ PPC_INS_ALIAS_MFDCCR, "mfdccr" },
{ PPC_INS_ALIAS_MTICCR, "mticcr" },
{ PPC_INS_ALIAS_MFICCR, "mficcr" },
{ PPC_INS_ALIAS_TLBIE, "tlbie" },
{ PPC_INS_ALIAS_TLBREHI, "tlbrehi" },
{ PPC_INS_ALIAS_TLBRELO, "tlbrelo" },
{ PPC_INS_ALIAS_TLBWEHI, "tlbwehi" },
{ PPC_INS_ALIAS_TLBWELO, "tlbwelo" },
{ PPC_INS_ALIAS_ROTLDI, "rotldi" },
{ PPC_INS_ALIAS_ROTLDI_, "rotldi." },
{ PPC_INS_ALIAS_ROTLD, "rotld" },
{ PPC_INS_ALIAS_ROTLD_, "rotld." },
{ PPC_INS_ALIAS_CLRLDI, "clrldi" },
{ PPC_INS_ALIAS_CLRLDI_, "clrldi." },
{ PPC_INS_ALIAS_LNIA, "lnia" },
{ PPC_INS_ALIAS_BCp, "bc+" },
{ PPC_INS_ALIAS_BCAp, "bca+" },
{ PPC_INS_ALIAS_BCLp, "bcl+" },
{ PPC_INS_ALIAS_BCLAp, "bcla+" },
{ PPC_INS_ALIAS_BCm, "bc-" },
{ PPC_INS_ALIAS_BCAm, "bca-" },
{ PPC_INS_ALIAS_BCLm, "bcl-" },
{ PPC_INS_ALIAS_BCLAm, "bcla-" },
{ PPC_INS_ALIAS_BT, "bt" },
{ PPC_INS_ALIAS_BTA, "bta" },
{ PPC_INS_ALIAS_BTLR, "btlr" },
{ PPC_INS_ALIAS_BTL, "btl" },
{ PPC_INS_ALIAS_BTLA, "btla" },
{ PPC_INS_ALIAS_BTLRL, "btlrl" },
{ PPC_INS_ALIAS_BTCTR, "btctr" },
{ PPC_INS_ALIAS_BTCTRL, "btctrl" },
{ PPC_INS_ALIAS_BDZLR, "bdzlr" },
{ PPC_INS_ALIAS_BDZLRL, "bdzlrl" },
{ PPC_INS_ALIAS_BDZL, "bdzl" },
{ PPC_INS_ALIAS_BDZLA, "bdzla" },
{ PPC_INS_ALIAS_BDZ, "bdz" },
{ PPC_INS_ALIAS_BDNZL, "bdnzl" },
{ PPC_INS_ALIAS_BDNZLA, "bdnzla" },
{ PPC_INS_ALIAS_BDNZ, "bdnz" },
{ PPC_INS_ALIAS_BDZLp, "bdzl+" },
{ PPC_INS_ALIAS_BDZLAp, "bdzla+" },
{ PPC_INS_ALIAS_BDZp, "bdz+" },
{ PPC_INS_ALIAS_BDNZLp, "bdnzl+" },
{ PPC_INS_ALIAS_BDNZLAp, "bdnzla+" },
{ PPC_INS_ALIAS_BDNZp, "bdnz+" },
{ PPC_INS_ALIAS_BDZLm, "bdzl-" },
{ PPC_INS_ALIAS_BDZLAm, "bdzla-" },
{ PPC_INS_ALIAS_BDZm, "bdz-" },
{ PPC_INS_ALIAS_BDNZLm, "bdnzl-" },
{ PPC_INS_ALIAS_BDNZLAm, "bdnzla-" },
{ PPC_INS_ALIAS_BDNZm, "bdnz-" },
{ PPC_INS_ALIAS_BDNZLR, "bdnzlr" },
{ PPC_INS_ALIAS_BDNZLRL, "bdnzlrl" },
{ PPC_INS_ALIAS_BDZLRp, "bdzlr+" },
{ PPC_INS_ALIAS_BDZLRLp, "bdzlrl+" },
{ PPC_INS_ALIAS_BDNZLRp, "bdnzlr+" },
{ PPC_INS_ALIAS_BDNZLRLp, "bdnzlrl+" },
{ PPC_INS_ALIAS_BDZLRm, "bdzlr-" },
{ PPC_INS_ALIAS_BDZLRLm, "bdzlrl-" },
{ PPC_INS_ALIAS_BDNZLRm, "bdnzlr-" },
{ PPC_INS_ALIAS_BDNZLRLm, "bdnzlrl-" },
{ PPC_INS_ALIAS_BF, "bf" },
{ PPC_INS_ALIAS_BFA, "bfa" },
{ PPC_INS_ALIAS_BFLR, "bflr" },
{ PPC_INS_ALIAS_BFL, "bfl" },
{ PPC_INS_ALIAS_BFLA, "bfla" },
{ PPC_INS_ALIAS_BFLRL, "bflrl" },
{ PPC_INS_ALIAS_BFCTR, "bfctr" },
{ PPC_INS_ALIAS_BFCTRL, "bfctrl" },
{ PPC_INS_ALIAS_BTm, "bt-" },
{ PPC_INS_ALIAS_BTAm, "bta-" },
{ PPC_INS_ALIAS_BTLRm, "btlr-" },
{ PPC_INS_ALIAS_BTLm, "btl-" },
{ PPC_INS_ALIAS_BTLAm, "btla-" },
{ PPC_INS_ALIAS_BTLRLm, "btlrl-" },
{ PPC_INS_ALIAS_BTCTRm, "btctr-" },
{ PPC_INS_ALIAS_BTCTRLm, "btctrl-" },
{ PPC_INS_ALIAS_BFm, "bf-" },
{ PPC_INS_ALIAS_BFAm, "bfa-" },
{ PPC_INS_ALIAS_BFLRm, "bflr-" },
{ PPC_INS_ALIAS_BFLm, "bfl-" },
{ PPC_INS_ALIAS_BFLAm, "bfla-" },
{ PPC_INS_ALIAS_BFLRLm, "bflrl-" },
{ PPC_INS_ALIAS_BFCTRm, "bfctr-" },
{ PPC_INS_ALIAS_BFCTRLm, "bfctrl-" },
{ PPC_INS_ALIAS_BTp, "bt+" },
{ PPC_INS_ALIAS_BTAp, "bta+" },
{ PPC_INS_ALIAS_BTLRp, "btlr+" },
{ PPC_INS_ALIAS_BTLp, "btl+" },
{ PPC_INS_ALIAS_BTLAp, "btla+" },
{ PPC_INS_ALIAS_BTLRLp, "btlrl+" },
{ PPC_INS_ALIAS_BTCTRp, "btctr+" },
{ PPC_INS_ALIAS_BTCTRLp, "btctrl+" },
{ PPC_INS_ALIAS_BFp, "bf+" },
{ PPC_INS_ALIAS_BFAp, "bfa+" },
{ PPC_INS_ALIAS_BFLRp, "bflr+" },
{ PPC_INS_ALIAS_BFLp, "bfl+" },
{ PPC_INS_ALIAS_BFLAp, "bfla+" },
{ PPC_INS_ALIAS_BFLRLp, "bflrl+" },
{ PPC_INS_ALIAS_BFCTRp, "bfctr+" },
{ PPC_INS_ALIAS_BFCTRLp, "bfctrl+" },
{ PPC_INS_ALIAS_BDNZT, "bdnzt" },
{ PPC_INS_ALIAS_BDNZTA, "bdnzta" },
{ PPC_INS_ALIAS_BDNZTLR, "bdnztlr" },
{ PPC_INS_ALIAS_BDNZTL, "bdnztl" },
{ PPC_INS_ALIAS_BDNZTLA, "bdnztla" },
{ PPC_INS_ALIAS_BDNZTLRL, "bdnztlrl" },
{ PPC_INS_ALIAS_BDNZF, "bdnzf" },
{ PPC_INS_ALIAS_BDNZFA, "bdnzfa" },
{ PPC_INS_ALIAS_BDNZFLR, "bdnzflr" },
{ PPC_INS_ALIAS_BDNZFL, "bdnzfl" },
{ PPC_INS_ALIAS_BDNZFLA, "bdnzfla" },
{ PPC_INS_ALIAS_BDNZFLRL, "bdnzflrl" },
{ PPC_INS_ALIAS_BDZT, "bdzt" },
{ PPC_INS_ALIAS_BDZTA, "bdzta" },
{ PPC_INS_ALIAS_BDZTLR, "bdztlr" },
{ PPC_INS_ALIAS_BDZTL, "bdztl" },
{ PPC_INS_ALIAS_BDZTLA, "bdztla" },
{ PPC_INS_ALIAS_BDZTLRL, "bdztlrl" },
{ PPC_INS_ALIAS_BDZF, "bdzf" },
{ PPC_INS_ALIAS_BDZFA, "bdzfa" },
{ PPC_INS_ALIAS_BDZFLR, "bdzflr" },
{ PPC_INS_ALIAS_BDZFL, "bdzfl" },
{ PPC_INS_ALIAS_BDZFLA, "bdzfla" },
{ PPC_INS_ALIAS_BDZFLRL, "bdzflrl" },
{ PPC_INS_ALIAS_B, "b" },
{ PPC_INS_ALIAS_BA, "ba" },
{ PPC_INS_ALIAS_BL, "bl" },
{ PPC_INS_ALIAS_BLA, "bla" },
{ PPC_INS_ALIAS_BLR, "blr" },
{ PPC_INS_ALIAS_BLRL, "blrl" },
{ PPC_INS_ALIAS_BCTR, "bctr" },
{ PPC_INS_ALIAS_BCTRL, "bctrl" },
{ PPC_INS_ALIAS_BLT, "blt" },
{ PPC_INS_ALIAS_BLTA, "blta" },
{ PPC_INS_ALIAS_BLTLR, "bltlr" },
{ PPC_INS_ALIAS_BLTCTR, "bltctr" },
{ PPC_INS_ALIAS_BLTL, "bltl" },
{ PPC_INS_ALIAS_BLTLA, "bltla" },
{ PPC_INS_ALIAS_BLTLRL, "bltlrl" },
{ PPC_INS_ALIAS_BLTCTRL, "bltctrl" },
{ PPC_INS_ALIAS_BLTm, "blt-" },
{ PPC_INS_ALIAS_BLTAm, "blta-" },
{ PPC_INS_ALIAS_BLTLRm, "bltlr-" },
{ PPC_INS_ALIAS_BLTCTRm, "bltctr-" },
{ PPC_INS_ALIAS_BLTLm, "bltl-" },
{ PPC_INS_ALIAS_BLTLAm, "bltla-" },
{ PPC_INS_ALIAS_BLTLRLm, "bltlrl-" },
{ PPC_INS_ALIAS_BLTCTRLm, "bltctrl-" },
{ PPC_INS_ALIAS_BLTp, "blt+" },
{ PPC_INS_ALIAS_BLTAp, "blta+" },
{ PPC_INS_ALIAS_BLTLRp, "bltlr+" },
{ PPC_INS_ALIAS_BLTCTRp, "bltctr+" },
{ PPC_INS_ALIAS_BLTLp, "bltl+" },
{ PPC_INS_ALIAS_BLTLAp, "bltla+" },
{ PPC_INS_ALIAS_BLTLRLp, "bltlrl+" },
{ PPC_INS_ALIAS_BLTCTRLp, "bltctrl+" },
{ PPC_INS_ALIAS_BGT, "bgt" },
{ PPC_INS_ALIAS_BGTA, "bgta" },
{ PPC_INS_ALIAS_BGTLR, "bgtlr" },
{ PPC_INS_ALIAS_BGTCTR, "bgtctr" },
{ PPC_INS_ALIAS_BGTL, "bgtl" },
{ PPC_INS_ALIAS_BGTLA, "bgtla" },
{ PPC_INS_ALIAS_BGTLRL, "bgtlrl" },
{ PPC_INS_ALIAS_BGTCTRL, "bgtctrl" },
{ PPC_INS_ALIAS_BGTm, "bgt-" },
{ PPC_INS_ALIAS_BGTAm, "bgta-" },
{ PPC_INS_ALIAS_BGTLRm, "bgtlr-" },
{ PPC_INS_ALIAS_BGTCTRm, "bgtctr-" },
{ PPC_INS_ALIAS_BGTLm, "bgtl-" },
{ PPC_INS_ALIAS_BGTLAm, "bgtla-" },
{ PPC_INS_ALIAS_BGTLRLm, "bgtlrl-" },
{ PPC_INS_ALIAS_BGTCTRLm, "bgtctrl-" },
{ PPC_INS_ALIAS_BGTp, "bgt+" },
{ PPC_INS_ALIAS_BGTAp, "bgta+" },
{ PPC_INS_ALIAS_BGTLRp, "bgtlr+" },
{ PPC_INS_ALIAS_BGTCTRp, "bgtctr+" },
{ PPC_INS_ALIAS_BGTLp, "bgtl+" },
{ PPC_INS_ALIAS_BGTLAp, "bgtla+" },
{ PPC_INS_ALIAS_BGTLRLp, "bgtlrl+" },
{ PPC_INS_ALIAS_BGTCTRLp, "bgtctrl+" },
{ PPC_INS_ALIAS_BEQ, "beq" },
{ PPC_INS_ALIAS_BEQA, "beqa" },
{ PPC_INS_ALIAS_BEQLR, "beqlr" },
{ PPC_INS_ALIAS_BEQCTR, "beqctr" },
{ PPC_INS_ALIAS_BEQL, "beql" },
{ PPC_INS_ALIAS_BEQLA, "beqla" },
{ PPC_INS_ALIAS_BEQLRL, "beqlrl" },
{ PPC_INS_ALIAS_BEQCTRL, "beqctrl" },
{ PPC_INS_ALIAS_BEQm, "beq-" },
{ PPC_INS_ALIAS_BEQAm, "beqa-" },
{ PPC_INS_ALIAS_BEQLRm, "beqlr-" },
{ PPC_INS_ALIAS_BEQCTRm, "beqctr-" },
{ PPC_INS_ALIAS_BEQLm, "beql-" },
{ PPC_INS_ALIAS_BEQLAm, "beqla-" },
{ PPC_INS_ALIAS_BEQLRLm, "beqlrl-" },
{ PPC_INS_ALIAS_BEQCTRLm, "beqctrl-" },
{ PPC_INS_ALIAS_BEQp, "beq+" },
{ PPC_INS_ALIAS_BEQAp, "beqa+" },
{ PPC_INS_ALIAS_BEQLRp, "beqlr+" },
{ PPC_INS_ALIAS_BEQCTRp, "beqctr+" },
{ PPC_INS_ALIAS_BEQLp, "beql+" },
{ PPC_INS_ALIAS_BEQLAp, "beqla+" },
{ PPC_INS_ALIAS_BEQLRLp, "beqlrl+" },
{ PPC_INS_ALIAS_BEQCTRLp, "beqctrl+" },
{ PPC_INS_ALIAS_BUN, "bun" },
{ PPC_INS_ALIAS_BUNA, "buna" },
{ PPC_INS_ALIAS_BUNLR, "bunlr" },
{ PPC_INS_ALIAS_BUNCTR, "bunctr" },
{ PPC_INS_ALIAS_BUNL, "bunl" },
{ PPC_INS_ALIAS_BUNLA, "bunla" },
{ PPC_INS_ALIAS_BUNLRL, "bunlrl" },
{ PPC_INS_ALIAS_BUNCTRL, "bunctrl" },
{ PPC_INS_ALIAS_BUNm, "bun-" },
{ PPC_INS_ALIAS_BUNAm, "buna-" },
{ PPC_INS_ALIAS_BUNLRm, "bunlr-" },
{ PPC_INS_ALIAS_BUNCTRm, "bunctr-" },
{ PPC_INS_ALIAS_BUNLm, "bunl-" },
{ PPC_INS_ALIAS_BUNLAm, "bunla-" },
{ PPC_INS_ALIAS_BUNLRLm, "bunlrl-" },
{ PPC_INS_ALIAS_BUNCTRLm, "bunctrl-" },
{ PPC_INS_ALIAS_BUNp, "bun+" },
{ PPC_INS_ALIAS_BUNAp, "buna+" },
{ PPC_INS_ALIAS_BUNLRp, "bunlr+" },
{ PPC_INS_ALIAS_BUNCTRp, "bunctr+" },
{ PPC_INS_ALIAS_BUNLp, "bunl+" },
{ PPC_INS_ALIAS_BUNLAp, "bunla+" },
{ PPC_INS_ALIAS_BUNLRLp, "bunlrl+" },
{ PPC_INS_ALIAS_BUNCTRLp, "bunctrl+" },
{ PPC_INS_ALIAS_BSO, "bso" },
{ PPC_INS_ALIAS_BSOA, "bsoa" },
{ PPC_INS_ALIAS_BSOLR, "bsolr" },
{ PPC_INS_ALIAS_BSOCTR, "bsoctr" },
{ PPC_INS_ALIAS_BSOL, "bsol" },
{ PPC_INS_ALIAS_BSOLA, "bsola" },
{ PPC_INS_ALIAS_BSOLRL, "bsolrl" },
{ PPC_INS_ALIAS_BSOCTRL, "bsoctrl" },
{ PPC_INS_ALIAS_BSOm, "bso-" },
{ PPC_INS_ALIAS_BSOAm, "bsoa-" },
{ PPC_INS_ALIAS_BSOLRm, "bsolr-" },
{ PPC_INS_ALIAS_BSOCTRm, "bsoctr-" },
{ PPC_INS_ALIAS_BSOLm, "bsol-" },
{ PPC_INS_ALIAS_BSOLAm, "bsola-" },
{ PPC_INS_ALIAS_BSOLRLm, "bsolrl-" },
{ PPC_INS_ALIAS_BSOCTRLm, "bsoctrl-" },
{ PPC_INS_ALIAS_BSOp, "bso+" },
{ PPC_INS_ALIAS_BSOAp, "bsoa+" },
{ PPC_INS_ALIAS_BSOLRp, "bsolr+" },
{ PPC_INS_ALIAS_BSOCTRp, "bsoctr+" },
{ PPC_INS_ALIAS_BSOLp, "bsol+" },
{ PPC_INS_ALIAS_BSOLAp, "bsola+" },
{ PPC_INS_ALIAS_BSOLRLp, "bsolrl+" },
{ PPC_INS_ALIAS_BSOCTRLp, "bsoctrl+" },
{ PPC_INS_ALIAS_BGE, "bge" },
{ PPC_INS_ALIAS_BGEA, "bgea" },
{ PPC_INS_ALIAS_BGELR, "bgelr" },
{ PPC_INS_ALIAS_BGECTR, "bgectr" },
{ PPC_INS_ALIAS_BGEL, "bgel" },
{ PPC_INS_ALIAS_BGELA, "bgela" },
{ PPC_INS_ALIAS_BGELRL, "bgelrl" },
{ PPC_INS_ALIAS_BGECTRL, "bgectrl" },
{ PPC_INS_ALIAS_BGEm, "bge-" },
{ PPC_INS_ALIAS_BGEAm, "bgea-" },
{ PPC_INS_ALIAS_BGELRm, "bgelr-" },
{ PPC_INS_ALIAS_BGECTRm, "bgectr-" },
{ PPC_INS_ALIAS_BGELm, "bgel-" },
{ PPC_INS_ALIAS_BGELAm, "bgela-" },
{ PPC_INS_ALIAS_BGELRLm, "bgelrl-" },
{ PPC_INS_ALIAS_BGECTRLm, "bgectrl-" },
{ PPC_INS_ALIAS_BGEp, "bge+" },
{ PPC_INS_ALIAS_BGEAp, "bgea+" },
{ PPC_INS_ALIAS_BGELRp, "bgelr+" },
{ PPC_INS_ALIAS_BGECTRp, "bgectr+" },
{ PPC_INS_ALIAS_BGELp, "bgel+" },
{ PPC_INS_ALIAS_BGELAp, "bgela+" },
{ PPC_INS_ALIAS_BGELRLp, "bgelrl+" },
{ PPC_INS_ALIAS_BGECTRLp, "bgectrl+" },
{ PPC_INS_ALIAS_BNL, "bnl" },
{ PPC_INS_ALIAS_BNLA, "bnla" },
{ PPC_INS_ALIAS_BNLLR, "bnllr" },
{ PPC_INS_ALIAS_BNLCTR, "bnlctr" },
{ PPC_INS_ALIAS_BNLL, "bnll" },
{ PPC_INS_ALIAS_BNLLA, "bnlla" },
{ PPC_INS_ALIAS_BNLLRL, "bnllrl" },
{ PPC_INS_ALIAS_BNLCTRL, "bnlctrl" },
{ PPC_INS_ALIAS_BNLm, "bnl-" },
{ PPC_INS_ALIAS_BNLAm, "bnla-" },
{ PPC_INS_ALIAS_BNLLRm, "bnllr-" },
{ PPC_INS_ALIAS_BNLCTRm, "bnlctr-" },
{ PPC_INS_ALIAS_BNLLm, "bnll-" },
{ PPC_INS_ALIAS_BNLLAm, "bnlla-" },
{ PPC_INS_ALIAS_BNLLRLm, "bnllrl-" },
{ PPC_INS_ALIAS_BNLCTRLm, "bnlctrl-" },
{ PPC_INS_ALIAS_BNLp, "bnl+" },
{ PPC_INS_ALIAS_BNLAp, "bnla+" },
{ PPC_INS_ALIAS_BNLLRp, "bnllr+" },
{ PPC_INS_ALIAS_BNLCTRp, "bnlctr+" },
{ PPC_INS_ALIAS_BNLLp, "bnll+" },
{ PPC_INS_ALIAS_BNLLAp, "bnlla+" },
{ PPC_INS_ALIAS_BNLLRLp, "bnllrl+" },
{ PPC_INS_ALIAS_BNLCTRLp, "bnlctrl+" },
{ PPC_INS_ALIAS_BLE, "ble" },
{ PPC_INS_ALIAS_BLEA, "blea" },
{ PPC_INS_ALIAS_BLELR, "blelr" },
{ PPC_INS_ALIAS_BLECTR, "blectr" },
{ PPC_INS_ALIAS_BLEL, "blel" },
{ PPC_INS_ALIAS_BLELA, "blela" },
{ PPC_INS_ALIAS_BLELRL, "blelrl" },
{ PPC_INS_ALIAS_BLECTRL, "blectrl" },
{ PPC_INS_ALIAS_BLEm, "ble-" },
{ PPC_INS_ALIAS_BLEAm, "blea-" },
{ PPC_INS_ALIAS_BLELRm, "blelr-" },
{ PPC_INS_ALIAS_BLECTRm, "blectr-" },
{ PPC_INS_ALIAS_BLELm, "blel-" },
{ PPC_INS_ALIAS_BLELAm, "blela-" },
{ PPC_INS_ALIAS_BLELRLm, "blelrl-" },
{ PPC_INS_ALIAS_BLECTRLm, "blectrl-" },
{ PPC_INS_ALIAS_BLEp, "ble+" },
{ PPC_INS_ALIAS_BLEAp, "blea+" },
{ PPC_INS_ALIAS_BLELRp, "blelr+" },
{ PPC_INS_ALIAS_BLECTRp, "blectr+" },
{ PPC_INS_ALIAS_BLELp, "blel+" },
{ PPC_INS_ALIAS_BLELAp, "blela+" },
{ PPC_INS_ALIAS_BLELRLp, "blelrl+" },
{ PPC_INS_ALIAS_BLECTRLp, "blectrl+" },
{ PPC_INS_ALIAS_BNG, "bng" },
{ PPC_INS_ALIAS_BNGA, "bnga" },
{ PPC_INS_ALIAS_BNGLR, "bnglr" },
{ PPC_INS_ALIAS_BNGCTR, "bngctr" },
{ PPC_INS_ALIAS_BNGL, "bngl" },
{ PPC_INS_ALIAS_BNGLA, "bngla" },
{ PPC_INS_ALIAS_BNGLRL, "bnglrl" },
{ PPC_INS_ALIAS_BNGCTRL, "bngctrl" },
{ PPC_INS_ALIAS_BNGm, "bng-" },
{ PPC_INS_ALIAS_BNGAm, "bnga-" },
{ PPC_INS_ALIAS_BNGLRm, "bnglr-" },
{ PPC_INS_ALIAS_BNGCTRm, "bngctr-" },
{ PPC_INS_ALIAS_BNGLm, "bngl-" },
{ PPC_INS_ALIAS_BNGLAm, "bngla-" },
{ PPC_INS_ALIAS_BNGLRLm, "bnglrl-" },
{ PPC_INS_ALIAS_BNGCTRLm, "bngctrl-" },
{ PPC_INS_ALIAS_BNGp, "bng+" },
{ PPC_INS_ALIAS_BNGAp, "bnga+" },
{ PPC_INS_ALIAS_BNGLRp, "bnglr+" },
{ PPC_INS_ALIAS_BNGCTRp, "bngctr+" },
{ PPC_INS_ALIAS_BNGLp, "bngl+" },
{ PPC_INS_ALIAS_BNGLAp, "bngla+" },
{ PPC_INS_ALIAS_BNGLRLp, "bnglrl+" },
{ PPC_INS_ALIAS_BNGCTRLp, "bngctrl+" },
{ PPC_INS_ALIAS_BNE, "bne" },
{ PPC_INS_ALIAS_BNEA, "bnea" },
{ PPC_INS_ALIAS_BNELR, "bnelr" },
{ PPC_INS_ALIAS_BNECTR, "bnectr" },
{ PPC_INS_ALIAS_BNEL, "bnel" },
{ PPC_INS_ALIAS_BNELA, "bnela" },
{ PPC_INS_ALIAS_BNELRL, "bnelrl" },
{ PPC_INS_ALIAS_BNECTRL, "bnectrl" },
{ PPC_INS_ALIAS_BNEm, "bne-" },
{ PPC_INS_ALIAS_BNEAm, "bnea-" },
{ PPC_INS_ALIAS_BNELRm, "bnelr-" },
{ PPC_INS_ALIAS_BNECTRm, "bnectr-" },
{ PPC_INS_ALIAS_BNELm, "bnel-" },
{ PPC_INS_ALIAS_BNELAm, "bnela-" },
{ PPC_INS_ALIAS_BNELRLm, "bnelrl-" },
{ PPC_INS_ALIAS_BNECTRLm, "bnectrl-" },
{ PPC_INS_ALIAS_BNEp, "bne+" },
{ PPC_INS_ALIAS_BNEAp, "bnea+" },
{ PPC_INS_ALIAS_BNELRp, "bnelr+" },
{ PPC_INS_ALIAS_BNECTRp, "bnectr+" },
{ PPC_INS_ALIAS_BNELp, "bnel+" },
{ PPC_INS_ALIAS_BNELAp, "bnela+" },
{ PPC_INS_ALIAS_BNELRLp, "bnelrl+" },
{ PPC_INS_ALIAS_BNECTRLp, "bnectrl+" },
{ PPC_INS_ALIAS_BNU, "bnu" },
{ PPC_INS_ALIAS_BNUA, "bnua" },
{ PPC_INS_ALIAS_BNULR, "bnulr" },
{ PPC_INS_ALIAS_BNUCTR, "bnuctr" },
{ PPC_INS_ALIAS_BNUL, "bnul" },
{ PPC_INS_ALIAS_BNULA, "bnula" },
{ PPC_INS_ALIAS_BNULRL, "bnulrl" },
{ PPC_INS_ALIAS_BNUCTRL, "bnuctrl" },
{ PPC_INS_ALIAS_BNUm, "bnu-" },
{ PPC_INS_ALIAS_BNUAm, "bnua-" },
{ PPC_INS_ALIAS_BNULRm, "bnulr-" },
{ PPC_INS_ALIAS_BNUCTRm, "bnuctr-" },
{ PPC_INS_ALIAS_BNULm, "bnul-" },
{ PPC_INS_ALIAS_BNULAm, "bnula-" },
{ PPC_INS_ALIAS_BNULRLm, "bnulrl-" },
{ PPC_INS_ALIAS_BNUCTRLm, "bnuctrl-" },
{ PPC_INS_ALIAS_BNUp, "bnu+" },
{ PPC_INS_ALIAS_BNUAp, "bnua+" },
{ PPC_INS_ALIAS_BNULRp, "bnulr+" },
{ PPC_INS_ALIAS_BNUCTRp, "bnuctr+" },
{ PPC_INS_ALIAS_BNULp, "bnul+" },
{ PPC_INS_ALIAS_BNULAp, "bnula+" },
{ PPC_INS_ALIAS_BNULRLp, "bnulrl+" },
{ PPC_INS_ALIAS_BNUCTRLp, "bnuctrl+" },
{ PPC_INS_ALIAS_BNS, "bns" },
{ PPC_INS_ALIAS_BNSA, "bnsa" },
{ PPC_INS_ALIAS_BNSLR, "bnslr" },
{ PPC_INS_ALIAS_BNSCTR, "bnsctr" },
{ PPC_INS_ALIAS_BNSL, "bnsl" },
{ PPC_INS_ALIAS_BNSLA, "bnsla" },
{ PPC_INS_ALIAS_BNSLRL, "bnslrl" },
{ PPC_INS_ALIAS_BNSCTRL, "bnsctrl" },
{ PPC_INS_ALIAS_BNSm, "bns-" },
{ PPC_INS_ALIAS_BNSAm, "bnsa-" },
{ PPC_INS_ALIAS_BNSLRm, "bnslr-" },
{ PPC_INS_ALIAS_BNSCTRm, "bnsctr-" },
{ PPC_INS_ALIAS_BNSLm, "bnsl-" },
{ PPC_INS_ALIAS_BNSLAm, "bnsla-" },
{ PPC_INS_ALIAS_BNSLRLm, "bnslrl-" },
{ PPC_INS_ALIAS_BNSCTRLm, "bnsctrl-" },
{ PPC_INS_ALIAS_BNSp, "bns+" },
{ PPC_INS_ALIAS_BNSAp, "bnsa+" },
{ PPC_INS_ALIAS_BNSLRp, "bnslr+" },
{ PPC_INS_ALIAS_BNSCTRp, "bnsctr+" },
{ PPC_INS_ALIAS_BNSLp, "bnsl+" },
{ PPC_INS_ALIAS_BNSLAp, "bnsla+" },
{ PPC_INS_ALIAS_BNSLRLp, "bnslrl+" },
{ PPC_INS_ALIAS_BNSCTRLp, "bnsctrl+" },
{ PPC_INS_ALIAS_CMPWI, "cmpwi" },
{ PPC_INS_ALIAS_CMPW, "cmpw" },
{ PPC_INS_ALIAS_CMPLWI, "cmplwi" },
{ PPC_INS_ALIAS_CMPLW, "cmplw" },
{ PPC_INS_ALIAS_CMPDI, "cmpdi" },
{ PPC_INS_ALIAS_CMPD, "cmpd" },
{ PPC_INS_ALIAS_CMPLDI, "cmpldi" },
{ PPC_INS_ALIAS_CMPLD, "cmpld" },
{ PPC_INS_ALIAS_CMPI, "cmpi" },
{ PPC_INS_ALIAS_CMP, "cmp" },
{ PPC_INS_ALIAS_CMPLI, "cmpli" },
{ PPC_INS_ALIAS_CMPL, "cmpl" },
{ PPC_INS_ALIAS_TRAP, "trap" },
{ PPC_INS_ALIAS_TDLTI, "tdlti" },
{ PPC_INS_ALIAS_TDLT, "tdlt" },
{ PPC_INS_ALIAS_TWLTI, "twlti" },
{ PPC_INS_ALIAS_TWLT, "twlt" },
{ PPC_INS_ALIAS_TDLEI, "tdlei" },
{ PPC_INS_ALIAS_TDLE, "tdle" },
{ PPC_INS_ALIAS_TWLEI, "twlei" },
{ PPC_INS_ALIAS_TWLE, "twle" },
{ PPC_INS_ALIAS_TDEQI, "tdeqi" },
{ PPC_INS_ALIAS_TDEQ, "tdeq" },
{ PPC_INS_ALIAS_TWEQI, "tweqi" },
{ PPC_INS_ALIAS_TWEQ, "tweq" },
{ PPC_INS_ALIAS_TDGEI, "tdgei" },
{ PPC_INS_ALIAS_TDGE, "tdge" },
{ PPC_INS_ALIAS_TWGEI, "twgei" },
{ PPC_INS_ALIAS_TWGE, "twge" },
{ PPC_INS_ALIAS_TDGTI, "tdgti" },
{ PPC_INS_ALIAS_TDGT, "tdgt" },
{ PPC_INS_ALIAS_TWGTI, "twgti" },
{ PPC_INS_ALIAS_TWGT, "twgt" },
{ PPC_INS_ALIAS_TDNLI, "tdnli" },
{ PPC_INS_ALIAS_TDNL, "tdnl" },
{ PPC_INS_ALIAS_TWNLI, "twnli" },
{ PPC_INS_ALIAS_TWNL, "twnl" },
{ PPC_INS_ALIAS_TDNEI, "tdnei" },
{ PPC_INS_ALIAS_TDNE, "tdne" },
{ PPC_INS_ALIAS_TWNEI, "twnei" },
{ PPC_INS_ALIAS_TWNE, "twne" },
{ PPC_INS_ALIAS_TDNGI, "tdngi" },
{ PPC_INS_ALIAS_TDNG, "tdng" },
{ PPC_INS_ALIAS_TWNGI, "twngi" },
{ PPC_INS_ALIAS_TWNG, "twng" },
{ PPC_INS_ALIAS_TDLLTI, "tdllti" },
{ PPC_INS_ALIAS_TDLLT, "tdllt" },
{ PPC_INS_ALIAS_TWLLTI, "twllti" },
{ PPC_INS_ALIAS_TWLLT, "twllt" },
{ PPC_INS_ALIAS_TDLLEI, "tdllei" },
{ PPC_INS_ALIAS_TDLLE, "tdlle" },
{ PPC_INS_ALIAS_TWLLEI, "twllei" },
{ PPC_INS_ALIAS_TWLLE, "twlle" },
{ PPC_INS_ALIAS_TDLGEI, "tdlgei" },
{ PPC_INS_ALIAS_TDLGE, "tdlge" },
{ PPC_INS_ALIAS_TWLGEI, "twlgei" },
{ PPC_INS_ALIAS_TWLGE, "twlge" },
{ PPC_INS_ALIAS_TDLGTI, "tdlgti" },
{ PPC_INS_ALIAS_TDLGT, "tdlgt" },
{ PPC_INS_ALIAS_TWLGTI, "twlgti" },
{ PPC_INS_ALIAS_TWLGT, "twlgt" },
{ PPC_INS_ALIAS_TDLNLI, "tdlnli" },
{ PPC_INS_ALIAS_TDLNL, "tdlnl" },
{ PPC_INS_ALIAS_TWLNLI, "twlnli" },
{ PPC_INS_ALIAS_TWLNL, "twlnl" },
{ PPC_INS_ALIAS_TDLNGI, "tdlngi" },
{ PPC_INS_ALIAS_TDLNG, "tdlng" },
{ PPC_INS_ALIAS_TWLNGI, "twlngi" },
{ PPC_INS_ALIAS_TWLNG, "twlng" },
{ PPC_INS_ALIAS_TDUI, "tdui" },
{ PPC_INS_ALIAS_TDU, "tdu" },
{ PPC_INS_ALIAS_TWUI, "twui" },
{ PPC_INS_ALIAS_TWU, "twu" },
{ PPC_INS_ALIAS_PASTE_, "paste." },
{ PPC_INS_ALIAS_QVFCLR, "qvfclr" },
{ PPC_INS_ALIAS_QVFAND, "qvfand" },
{ PPC_INS_ALIAS_QVFANDC, "qvfandc" },
{ PPC_INS_ALIAS_QVFCTFB, "qvfctfb" },
{ PPC_INS_ALIAS_QVFXOR, "qvfxor" },
{ PPC_INS_ALIAS_QVFOR, "qvfor" },
{ PPC_INS_ALIAS_QVFNOR, "qvfnor" },
{ PPC_INS_ALIAS_QVFEQU, "qvfequ" },
{ PPC_INS_ALIAS_QVFNOT, "qvfnot" },
{ PPC_INS_ALIAS_QVFORC, "qvforc" },
{ PPC_INS_ALIAS_QVFNAND, "qvfnand" },
{ PPC_INS_ALIAS_QVFSET, "qvfset" },

32
arch/PowerPC/PPCGenCSFeatureName.inc Normal file
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ PPC_FEATURE_IsNotISAFuture, "IsNotISAFuture" },
{ PPC_FEATURE_IsISA3_0, "IsISA3_0" },
{ PPC_FEATURE_In64BitMode, "In64BitMode" },
{ PPC_FEATURE_In32BitMode, "In32BitMode" },
{ PPC_FEATURE_PCRelativeMemops, "PCRelativeMemops" },
{ PPC_FEATURE_HasBPERMD, "HasBPERMD" },
{ PPC_FEATURE_HasSPE, "HasSPE" },
{ PPC_FEATURE_IsE500, "IsE500" },
{ PPC_FEATURE_IsPPC4xx, "IsPPC4xx" },
{ PPC_FEATURE_HasExtDiv, "HasExtDiv" },
{ PPC_FEATURE_IsISAFuture, "IsISAFuture" },
{ PPC_FEATURE_HasFPU, "HasFPU" },
{ PPC_FEATURE_HasICBT, "HasICBT" },
{ PPC_FEATURE_HasPartwordAtomics, "HasPartwordAtomics" },
{ PPC_FEATURE_IsISA2_06, "IsISA2_06" },
{ PPC_FEATURE_IsBookE, "IsBookE" },
{ PPC_FEATURE_HasPS, "HasPS" },
{ PPC_FEATURE_HasQPX, "HasQPX" },
{ PPC_FEATURE_IsPPC6xx, "IsPPC6xx" },

19827
arch/PowerPC/PPCGenCSMappingInsn.inc Normal file
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1664
arch/PowerPC/PPCGenCSMappingInsnName.inc Normal file
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15990
arch/PowerPC/PPCGenCSMappingInsnOp.inc Normal file
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42
arch/PowerPC/PPCGenCSOpGroup.inc Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
PPC_OP_GROUP_S12ImmOperand = 0,
PPC_OP_GROUP_Operand = 1,
PPC_OP_GROUP_MemRegReg = 2,
PPC_OP_GROUP_U6ImmOperand = 3,
PPC_OP_GROUP_U5ImmOperand = 4,
PPC_OP_GROUP_MemRegImm = 5,
PPC_OP_GROUP_S16ImmOperand = 6,
PPC_OP_GROUP_U2ImmOperand = 7,
PPC_OP_GROUP_U16ImmOperand = 8,
PPC_OP_GROUP_BranchOperand = 9,
PPC_OP_GROUP_AbsBranchOperand = 10,
PPC_OP_GROUP_PredicateOperand = 11,
PPC_OP_GROUP_U1ImmOperand = 12,
PPC_OP_GROUP_TLSCall = 13,
PPC_OP_GROUP_U3ImmOperand = 14,
PPC_OP_GROUP_S5ImmOperand = 15,
PPC_OP_GROUP_MemRegImmHash = 16,
PPC_OP_GROUP_U4ImmOperand = 17,
PPC_OP_GROUP_U10ImmOperand = 18,
PPC_OP_GROUP_crbitm = 19,
PPC_OP_GROUP_S34ImmOperand = 20,
PPC_OP_GROUP_ImmZeroOperand = 21,
PPC_OP_GROUP_MemRegImm34 = 22,
PPC_OP_GROUP_MemRegImm34PCRel = 23,
PPC_OP_GROUP_U8ImmOperand = 24,
PPC_OP_GROUP_MemRegImmPS = 25,
PPC_OP_GROUP_U12ImmOperand = 26,
PPC_OP_GROUP_U7ImmOperand = 27,
PPC_OP_GROUP_ATBitsAsHint = 28,

14554
arch/PowerPC/PPCGenDisassemblerTables.inc
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arch/PowerPC/PPCGenInstrInfo.inc
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arch/PowerPC/PPCGenRegisterInfo.inc
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arch/PowerPC/PPCGenRegisterName.inc
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
static const char *getRegisterName(unsigned RegNo)
{
#ifndef CAPSTONE_DIET
static const char AsmStrs[] = {
/* 0 */ '*', '*', 'R', 'O', 'U', 'N', 'D', 'I', 'N', 'G', 32, 'M', 'O', 'D', 'E', '*', '*', 0,
/* 18 */ '*', '*', 'F', 'R', 'A', 'M', 'E', 32, 'P', 'O', 'I', 'N', 'T', 'E', 'R', '*', '*', 0,
/* 36 */ '*', '*', 'B', 'A', 'S', 'E', 32, 'P', 'O', 'I', 'N', 'T', 'E', 'R', '*', '*', 0,
/* 53 */ 'f', '1', '0', 0,
/* 57 */ 'q', '1', '0', 0,
/* 61 */ 'r', '1', '0', 0,
/* 65 */ 'v', 's', '1', '0', 0,
/* 70 */ 'v', '1', '0', 0,
/* 74 */ 'f', '2', '0', 0,
/* 78 */ 'q', '2', '0', 0,
/* 82 */ 'r', '2', '0', 0,
/* 86 */ 'v', 's', '2', '0', 0,
/* 91 */ 'v', '2', '0', 0,
/* 95 */ 'f', '3', '0', 0,
/* 99 */ 'q', '3', '0', 0,
/* 103 */ 'r', '3', '0', 0,
/* 107 */ 'v', 's', '3', '0', 0,
/* 112 */ 'v', '3', '0', 0,
/* 116 */ 'v', 's', '4', '0', 0,
/* 121 */ 'v', 's', '5', '0', 0,
/* 126 */ 'v', 's', '6', '0', 0,
/* 131 */ 'f', '0', 0,
/* 134 */ 'q', '0', 0,
/* 137 */ 'c', 'r', '0', 0,
/* 141 */ 'v', 's', '0', 0,
/* 145 */ 'v', '0', 0,
/* 148 */ 'f', '1', '1', 0,
/* 152 */ 'q', '1', '1', 0,
/* 156 */ 'r', '1', '1', 0,
/* 160 */ 'v', 's', '1', '1', 0,
/* 165 */ 'v', '1', '1', 0,
/* 169 */ 'f', '2', '1', 0,
/* 173 */ 'q', '2', '1', 0,
/* 177 */ 'r', '2', '1', 0,
/* 181 */ 'v', 's', '2', '1', 0,
/* 186 */ 'v', '2', '1', 0,
/* 190 */ 'f', '3', '1', 0,
/* 194 */ 'q', '3', '1', 0,
/* 198 */ 'r', '3', '1', 0,
/* 202 */ 'v', 's', '3', '1', 0,
/* 207 */ 'v', '3', '1', 0,
/* 211 */ 'v', 's', '4', '1', 0,
/* 216 */ 'v', 's', '5', '1', 0,
/* 221 */ 'v', 's', '6', '1', 0,
/* 226 */ 'f', '1', 0,
/* 229 */ 'q', '1', 0,
/* 232 */ 'c', 'r', '1', 0,
/* 236 */ 'v', 's', '1', 0,
/* 240 */ 'v', '1', 0,
/* 243 */ 'f', '1', '2', 0,
/* 247 */ 'q', '1', '2', 0,
/* 251 */ 'r', '1', '2', 0,
/* 255 */ 'v', 's', '1', '2', 0,
/* 260 */ 'v', '1', '2', 0,
/* 264 */ 'f', '2', '2', 0,
/* 268 */ 'q', '2', '2', 0,
/* 272 */ 'r', '2', '2', 0,
/* 276 */ 'v', 's', '2', '2', 0,
/* 281 */ 'v', '2', '2', 0,
/* 285 */ 'v', 's', '3', '2', 0,
/* 290 */ 'v', 's', '4', '2', 0,
/* 295 */ 'v', 's', '5', '2', 0,
/* 300 */ 'v', 's', '6', '2', 0,
/* 305 */ 'f', '2', 0,
/* 308 */ 'q', '2', 0,
/* 311 */ 'c', 'r', '2', 0,
/* 315 */ 'v', 's', '2', 0,
/* 319 */ 'v', '2', 0,
/* 322 */ 'f', '1', '3', 0,
/* 326 */ 'q', '1', '3', 0,
/* 330 */ 'r', '1', '3', 0,
/* 334 */ 'v', 's', '1', '3', 0,
/* 339 */ 'v', '1', '3', 0,
/* 343 */ 'f', '2', '3', 0,
/* 347 */ 'q', '2', '3', 0,
/* 351 */ 'r', '2', '3', 0,
/* 355 */ 'v', 's', '2', '3', 0,
/* 360 */ 'v', '2', '3', 0,
/* 364 */ 'v', 's', '3', '3', 0,
/* 369 */ 'v', 's', '4', '3', 0,
/* 374 */ 'v', 's', '5', '3', 0,
/* 379 */ 'v', 's', '6', '3', 0,
/* 384 */ 'f', '3', 0,
/* 387 */ 'q', '3', 0,
/* 390 */ 'c', 'r', '3', 0,
/* 394 */ 'v', 's', '3', 0,
/* 398 */ 'v', '3', 0,
/* 401 */ 'f', '1', '4', 0,
/* 405 */ 'q', '1', '4', 0,
/* 409 */ 'r', '1', '4', 0,
/* 413 */ 'v', 's', '1', '4', 0,
/* 418 */ 'v', '1', '4', 0,
/* 422 */ 'f', '2', '4', 0,
/* 426 */ 'q', '2', '4', 0,
/* 430 */ 'r', '2', '4', 0,
/* 434 */ 'v', 's', '2', '4', 0,
/* 439 */ 'v', '2', '4', 0,
/* 443 */ 'v', 's', '3', '4', 0,
/* 448 */ 'v', 's', '4', '4', 0,
/* 453 */ 'v', 's', '5', '4', 0,
/* 458 */ 'f', '4', 0,
/* 461 */ 'q', '4', 0,
/* 464 */ 'c', 'r', '4', 0,
/* 468 */ 'v', 's', '4', 0,
/* 472 */ 'v', '4', 0,
/* 475 */ 'f', '1', '5', 0,
/* 479 */ 'q', '1', '5', 0,
/* 483 */ 'r', '1', '5', 0,
/* 487 */ 'v', 's', '1', '5', 0,
/* 492 */ 'v', '1', '5', 0,
/* 496 */ 'f', '2', '5', 0,
/* 500 */ 'q', '2', '5', 0,
/* 504 */ 'r', '2', '5', 0,
/* 508 */ 'v', 's', '2', '5', 0,
/* 513 */ 'v', '2', '5', 0,
/* 517 */ 'v', 's', '3', '5', 0,
/* 522 */ 'v', 's', '4', '5', 0,
/* 527 */ 'v', 's', '5', '5', 0,
/* 532 */ 'f', '5', 0,
/* 535 */ 'q', '5', 0,
/* 538 */ 'c', 'r', '5', 0,
/* 542 */ 'v', 's', '5', 0,
/* 546 */ 'v', '5', 0,
/* 549 */ 'f', '1', '6', 0,
/* 553 */ 'q', '1', '6', 0,
/* 557 */ 'r', '1', '6', 0,
/* 561 */ 'v', 's', '1', '6', 0,
/* 566 */ 'v', '1', '6', 0,
/* 570 */ 'f', '2', '6', 0,
/* 574 */ 'q', '2', '6', 0,
/* 578 */ 'r', '2', '6', 0,
/* 582 */ 'v', 's', '2', '6', 0,
/* 587 */ 'v', '2', '6', 0,
/* 591 */ 'v', 's', '3', '6', 0,
/* 596 */ 'v', 's', '4', '6', 0,
/* 601 */ 'v', 's', '5', '6', 0,
/* 606 */ 'f', '6', 0,
/* 609 */ 'q', '6', 0,
/* 612 */ 'c', 'r', '6', 0,
/* 616 */ 'v', 's', '6', 0,
/* 620 */ 'v', '6', 0,
/* 623 */ 'f', '1', '7', 0,
/* 627 */ 'q', '1', '7', 0,
/* 631 */ 'r', '1', '7', 0,
/* 635 */ 'v', 's', '1', '7', 0,
/* 640 */ 'v', '1', '7', 0,
/* 644 */ 'f', '2', '7', 0,
/* 648 */ 'q', '2', '7', 0,
/* 652 */ 'r', '2', '7', 0,
/* 656 */ 'v', 's', '2', '7', 0,
/* 661 */ 'v', '2', '7', 0,
/* 665 */ 'v', 's', '3', '7', 0,
/* 670 */ 'v', 's', '4', '7', 0,
/* 675 */ 'v', 's', '5', '7', 0,
/* 680 */ 'f', '7', 0,
/* 683 */ 'q', '7', 0,
/* 686 */ 'c', 'r', '7', 0,
/* 690 */ 'v', 's', '7', 0,
/* 694 */ 'v', '7', 0,
/* 697 */ 'f', '1', '8', 0,
/* 701 */ 'q', '1', '8', 0,
/* 705 */ 'r', '1', '8', 0,
/* 709 */ 'v', 's', '1', '8', 0,
/* 714 */ 'v', '1', '8', 0,
/* 718 */ 'f', '2', '8', 0,
/* 722 */ 'q', '2', '8', 0,
/* 726 */ 'r', '2', '8', 0,
/* 730 */ 'v', 's', '2', '8', 0,
/* 735 */ 'v', '2', '8', 0,
/* 739 */ 'v', 's', '3', '8', 0,
/* 744 */ 'v', 's', '4', '8', 0,
/* 749 */ 'v', 's', '5', '8', 0,
/* 754 */ 'f', '8', 0,
/* 757 */ 'q', '8', 0,
/* 760 */ 'r', '8', 0,
/* 763 */ 'v', 's', '8', 0,
/* 767 */ 'v', '8', 0,
/* 770 */ 'f', '1', '9', 0,
/* 774 */ 'q', '1', '9', 0,
/* 778 */ 'r', '1', '9', 0,
/* 782 */ 'v', 's', '1', '9', 0,
/* 787 */ 'v', '1', '9', 0,
/* 791 */ 'f', '2', '9', 0,
/* 795 */ 'q', '2', '9', 0,
/* 799 */ 'r', '2', '9', 0,
/* 803 */ 'v', 's', '2', '9', 0,
/* 808 */ 'v', '2', '9', 0,
/* 812 */ 'v', 's', '3', '9', 0,
/* 817 */ 'v', 's', '4', '9', 0,
/* 822 */ 'v', 's', '5', '9', 0,
/* 827 */ 'f', '9', 0,
/* 830 */ 'q', '9', 0,
/* 833 */ 'r', '9', 0,
/* 836 */ 'v', 's', '9', 0,
/* 840 */ 'v', '9', 0,
/* 843 */ 'v', 'r', 's', 'a', 'v', 'e', 0,
/* 850 */ 'c', 'r', '0', 'u', 'n', 0,
/* 856 */ 'c', 'r', '1', 'u', 'n', 0,
/* 862 */ 'c', 'r', '2', 'u', 'n', 0,
/* 868 */ 'c', 'r', '3', 'u', 'n', 0,
/* 874 */ 'c', 'r', '4', 'u', 'n', 0,
/* 880 */ 'c', 'r', '5', 'u', 'n', 0,
/* 886 */ 'c', 'r', '6', 'u', 'n', 0,
/* 892 */ 'c', 'r', '7', 'u', 'n', 0,
/* 898 */ 'c', 'r', '0', 'e', 'q', 0,
/* 904 */ 'c', 'r', '1', 'e', 'q', 0,
/* 910 */ 'c', 'r', '2', 'e', 'q', 0,
/* 916 */ 'c', 'r', '3', 'e', 'q', 0,
/* 922 */ 'c', 'r', '4', 'e', 'q', 0,
/* 928 */ 'c', 'r', '5', 'e', 'q', 0,
/* 934 */ 'c', 'r', '6', 'e', 'q', 0,
/* 940 */ 'c', 'r', '7', 'e', 'q', 0,
/* 946 */ 's', 'p', 'e', 'f', 's', 'c', 'r', 0,
/* 954 */ 'x', 'e', 'r', 0,
/* 958 */ 'l', 'r', 0,
/* 961 */ 'c', 't', 'r', 0,
/* 965 */ 'c', 'r', '0', 'g', 't', 0,
/* 971 */ 'c', 'r', '1', 'g', 't', 0,
/* 977 */ 'c', 'r', '2', 'g', 't', 0,
/* 983 */ 'c', 'r', '3', 'g', 't', 0,
/* 989 */ 'c', 'r', '4', 'g', 't', 0,
/* 995 */ 'c', 'r', '5', 'g', 't', 0,
/* 1001 */ 'c', 'r', '6', 'g', 't', 0,
/* 1007 */ 'c', 'r', '7', 'g', 't', 0,
/* 1013 */ 'c', 'r', '0', 'l', 't', 0,
/* 1019 */ 'c', 'r', '1', 'l', 't', 0,
/* 1025 */ 'c', 'r', '2', 'l', 't', 0,
/* 1031 */ 'c', 'r', '3', 'l', 't', 0,
/* 1037 */ 'c', 'r', '4', 'l', 't', 0,
/* 1043 */ 'c', 'r', '5', 'l', 't', 0,
/* 1049 */ 'c', 'r', '6', 'l', 't', 0,
/* 1055 */ 'c', 'r', '7', 'l', 't', 0,
};
static const uint16_t RegAsmOffset[] = {
36, 954, 961, 18, 958, 0, 946, 843, 954, 55, 36, 137, 232, 311,
390, 464, 538, 612, 686, 961, 131, 226, 305, 384, 458, 532, 606, 680,
754, 827, 53, 148, 243, 322, 401, 475, 549, 623, 697, 770, 74, 169,
264, 343, 422, 496, 570, 644, 718, 791, 95, 190, 18, 958, 134, 229,
308, 387, 461, 535, 609, 683, 757, 830, 57, 152, 247, 326, 405, 479,
553, 627, 701, 774, 78, 173, 268, 347, 426, 500, 574, 648, 722, 795,
99, 194, 138, 233, 312, 391, 465, 539, 613, 687, 760, 833, 61, 156,
251, 330, 409, 483, 557, 631, 705, 778, 82, 177, 272, 351, 430, 504,
578, 652, 726, 799, 103, 198, 138, 233, 312, 391, 465, 539, 613, 687,
760, 833, 61, 156, 251, 330, 409, 483, 557, 631, 705, 778, 82, 177,
272, 351, 430, 504, 578, 652, 726, 799, 103, 198, 145, 240, 319, 398,
472, 546, 620, 694, 767, 840, 70, 165, 260, 339, 418, 492, 566, 640,
714, 787, 91, 186, 281, 360, 439, 513, 587, 661, 735, 808, 112, 207,
145, 240, 319, 398, 472, 546, 620, 694, 767, 840, 70, 165, 260, 339,
418, 492, 566, 640, 714, 787, 91, 186, 281, 360, 439, 513, 587, 661,
735, 808, 112, 207, 141, 236, 315, 394, 468, 542, 616, 690, 763, 836,
65, 160, 255, 334, 413, 487, 561, 635, 709, 782, 86, 181, 276, 355,
434, 508, 582, 656, 730, 803, 107, 202, 285, 364, 443, 517, 591, 665,
739, 812, 116, 211, 290, 369, 448, 522, 596, 670, 744, 817, 121, 216,
295, 374, 453, 527, 601, 675, 749, 822, 126, 221, 300, 379, 138, 233,
312, 391, 465, 539, 613, 687, 760, 833, 61, 156, 251, 330, 409, 483,
557, 631, 705, 778, 82, 177, 272, 351, 430, 504, 578, 652, 726, 799,
103, 198, 55, 898, 904, 910, 916, 922, 928, 934, 940, 965, 971, 977,
983, 989, 995, 1001, 1007, 1013, 1019, 1025, 1031, 1037, 1043, 1049, 1055, 850,
856, 862, 868, 874, 880, 886, 892,
};
return AsmStrs+RegAsmOffset[RegNo-1];
#else
return NULL;
#endif
}

210
arch/PowerPC/PPCGenSubtargetInfo.inc
View File

@ -1,90 +1,134 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *|
|* Subtarget Enumeration Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
PPC_DeprecatedDST = 0,
PPC_Directive32 = 1,
PPC_Directive64 = 2,
PPC_Directive440 = 3,
PPC_Directive601 = 4,
PPC_Directive602 = 5,
PPC_Directive603 = 6,
PPC_Directive604 = 7,
PPC_Directive620 = 8,
PPC_Directive750 = 9,
PPC_Directive970 = 10,
PPC_Directive7400 = 11,
PPC_DirectiveA2 = 12,
PPC_DirectiveE500 = 13,
PPC_DirectiveE500mc = 14,
PPC_DirectiveE5500 = 15,
PPC_DirectivePwr3 = 16,
PPC_DirectivePwr4 = 17,
PPC_DirectivePwr5 = 18,
PPC_DirectivePwr5x = 19,
PPC_DirectivePwr6 = 20,
PPC_DirectivePwr6x = 21,
PPC_DirectivePwr7 = 22,
PPC_DirectivePwr8 = 23,
PPC_DirectivePwr9 = 24,
PPC_Feature64Bit = 25,
PPC_Feature64BitRegs = 26,
PPC_FeatureAltivec = 27,
PPC_FeatureBPERMD = 28,
PPC_FeatureBookE = 29,
PPC_FeatureCMPB = 30,
PPC_FeatureCRBits = 31,
PPC_FeatureDirectMove = 32,
PPC_FeatureE500 = 33,
PPC_FeatureExtDiv = 34,
PPC_FeatureFCPSGN = 35,
PPC_FeatureFPCVT = 36,
PPC_FeatureFPRND = 37,
PPC_FeatureFPU = 38,
PPC_FeatureFRE = 39,
PPC_FeatureFRES = 40,
PPC_FeatureFRSQRTE = 41,
PPC_FeatureFRSQRTES = 42,
PPC_FeatureFSqrt = 43,
PPC_FeatureFloat128 = 44,
PPC_FeatureFusion = 45,
PPC_FeatureHTM = 46,
PPC_FeatureHardFloat = 47,
PPC_FeatureICBT = 48,
PPC_FeatureISA3_0 = 49,
PPC_FeatureISEL = 50,
PPC_FeatureInvariantFunctionDescriptors = 51,
PPC_FeatureLDBRX = 52,
PPC_FeatureLFIWAX = 53,
PPC_FeatureLongCall = 54,
PPC_FeatureMFOCRF = 55,
PPC_FeatureMFTB = 56,
PPC_FeatureMSYNC = 57,
PPC_FeatureP8Altivec = 58,
PPC_FeatureP8Crypto = 59,
PPC_FeatureP8Vector = 60,
PPC_FeatureP9Altivec = 61,
PPC_FeatureP9Vector = 62,
PPC_FeaturePOPCNTD = 63,
PPC_FeaturePPC4xx = 64,
PPC_FeaturePPC6xx = 65,
PPC_FeaturePS = 66,
PPC_FeaturePartwordAtomic = 67,
PPC_FeatureQPX = 68,
PPC_FeatureRecipPrec = 69,
PPC_FeatureSPE = 70,
PPC_FeatureSTFIWX = 71,
PPC_FeatureSecurePlt = 72,
PPC_FeatureSlowPOPCNTD = 73,
PPC_FeatureVSX = 74,
PPC_AIXOS = 0,
PPC_DeprecatedDST = 1,
PPC_Directive32 = 2,
PPC_Directive64 = 3,
PPC_Directive440 = 4,
PPC_Directive601 = 5,
PPC_Directive602 = 6,
PPC_Directive603 = 7,
PPC_Directive604 = 8,
PPC_Directive620 = 9,
PPC_Directive750 = 10,
PPC_Directive970 = 11,
PPC_Directive7400 = 12,
PPC_DirectiveA2 = 13,
PPC_DirectiveE500 = 14,
PPC_DirectiveE500mc = 15,
PPC_DirectiveE5500 = 16,
PPC_DirectivePwr3 = 17,
PPC_DirectivePwr4 = 18,
PPC_DirectivePwr5 = 19,
PPC_DirectivePwr5x = 20,
PPC_DirectivePwr6 = 21,
PPC_DirectivePwr6x = 22,
PPC_DirectivePwr7 = 23,
PPC_DirectivePwr8 = 24,
PPC_DirectivePwr9 = 25,
PPC_DirectivePwr10 = 26,
PPC_DirectivePwrFuture = 27,
PPC_Feature64Bit = 28,
PPC_Feature64BitRegs = 29,
PPC_FeatureAddLogicalFusion = 30,
PPC_FeatureAddiLoadFusion = 31,
PPC_FeatureAddisLoadFusion = 32,
PPC_FeatureAltivec = 33,
PPC_FeatureArithAddFusion = 34,
PPC_FeatureBPERMD = 35,
PPC_FeatureBack2BackFusion = 36,
PPC_FeatureBookE = 37,
PPC_FeatureCMPB = 38,
PPC_FeatureCRBits = 39,
PPC_FeatureCompareFusion = 40,
PPC_FeatureDirectMove = 41,
PPC_FeatureE500 = 42,
PPC_FeatureEFPU2 = 43,
PPC_FeatureExtDiv = 44,
PPC_FeatureFCPSGN = 45,
PPC_FeatureFPCVT = 46,
PPC_FeatureFPRND = 47,
PPC_FeatureFPU = 48,
PPC_FeatureFRE = 49,
PPC_FeatureFRES = 50,
PPC_FeatureFRSQRTE = 51,
PPC_FeatureFRSQRTES = 52,
PPC_FeatureFSqrt = 53,
PPC_FeatureFastMFLR = 54,
PPC_FeatureFloat128 = 55,
PPC_FeatureFusion = 56,
PPC_FeatureHTM = 57,
PPC_FeatureHardFloat = 58,
PPC_FeatureICBT = 59,
PPC_FeatureISA2_06 = 60,
PPC_FeatureISA2_07 = 61,
PPC_FeatureISA3_0 = 62,
PPC_FeatureISA3_1 = 63,
PPC_FeatureISAFuture = 64,
PPC_FeatureISEL = 65,
PPC_FeatureInvariantFunctionDescriptors = 66,
PPC_FeatureLDBRX = 67,
PPC_FeatureLFIWAX = 68,
PPC_FeatureLogicalAddFusion = 69,
PPC_FeatureLogicalFusion = 70,
PPC_FeatureLongCall = 71,
PPC_FeatureMFOCRF = 72,
PPC_FeatureMFTB = 73,
PPC_FeatureMMA = 74,
PPC_FeatureMSYNC = 75,
PPC_FeatureModernAIXAs = 76,
PPC_FeatureP8Altivec = 77,
PPC_FeatureP8Crypto = 78,
PPC_FeatureP8Vector = 79,
PPC_FeatureP9Altivec = 80,
PPC_FeatureP9Vector = 81,
PPC_FeatureP10Vector = 82,
PPC_FeaturePCRelativeMemops = 83,
PPC_FeaturePOPCNTD = 84,
PPC_FeaturePPC4xx = 85,
PPC_FeaturePPC6xx = 86,
PPC_FeaturePPCPostRASched = 87,
PPC_FeaturePPCPreRASched = 88,
PPC_FeaturePS = 89,
PPC_FeaturePairedVectorMemops = 90,
PPC_FeaturePartwordAtomic = 91,
PPC_FeaturePredictableSelectIsExpensive = 92,
PPC_FeaturePrefixInstrs = 93,
PPC_FeaturePrivileged = 94,
PPC_FeatureQPX = 95,
PPC_FeatureQuadwordAtomic = 96,
PPC_FeatureROPProtect = 97,
PPC_FeatureRecipPrec = 98,
PPC_FeatureSPE = 99,
PPC_FeatureSTFIWX = 100,
PPC_FeatureSecurePlt = 101,
PPC_FeatureSha3Fusion = 102,
PPC_FeatureSlowPOPCNTD = 103,
PPC_FeatureStoreFusion = 104,
PPC_FeatureTwoConstNR = 105,
PPC_FeatureUnalignedFloats = 106,
PPC_FeatureVSX = 107,
PPC_FeatureVectorsUseTwoUnits = 108,
PPC_FeatureWideImmFusion = 109,
PPC_FeatureZeroMoveFusion = 110,
PPC_NumSubtargetFeatures = 111
};
#endif // GET_SUBTARGETINFO_ENUM

1578
arch/PowerPC/PPCInstPrinter.c
View File

File diff suppressed because it is too large Load Diff

80
arch/PowerPC/PPCInstPrinter.h
View File

@ -1,15 +1,79 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
#ifndef CS_PPCINSTPRINTER_H
#define CS_PPCINSTPRINTER_H
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax -*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an PPC MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifndef CS_PPC_INSTPRINTER_H
#define CS_PPC_INSTPRINTER_H
#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "../../LEB128.h"
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "PPCMCTargetDesc.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
void PPC_printInst(MCInst *MI, SStream *O, void *Info);
bool showRegistersWithPercentPrefix(const MCInst *MI, const char *RegName);
bool showRegistersWithPrefix(const MCInst *MI);
// Autogenerated by tblgen.
void printATBitsAsHint(MCInst *MI, unsigned OpNo, SStream *O);
void printU1ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU3ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU7ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU8ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU10ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printS12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printS34ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printImmZeroOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo,
SStream *O);
void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O);
void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O);
void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O);
void printMemRegImmPS(MCInst *MI, unsigned OpNo, SStream *O);
void printMemRegImmHash(MCInst *MI, unsigned OpNo, SStream *O);
void printMemRegImm34PCRel(MCInst *MI, unsigned OpNo, SStream *O);
void printMemRegImm34(MCInst *MI, unsigned OpNo, SStream *O);
void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O);
;
// end namespace llvm
void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci);
#endif
#endif // CS_PPC_INSTPRINTER_H

50
arch/PowerPC/PPCInstrInfo.h Normal file
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@ -0,0 +1,50 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Rot127 <unisono@quyllur.org> 2022-2023 */
#ifndef CS_PPC_INSTRINFO_H
#define CS_PPC_INSTRINFO_H
#include "PPCMCTargetDesc.h"
extern const MCInstrDesc PPCInsts[];
static bool isVFRegister(unsigned Reg) {
return Reg >= PPC_VF0 && Reg <= PPC_VF31;
}
static bool isVRRegister(unsigned Reg) {
return Reg >= PPC_V0 && Reg <= PPC_V31;
}
/// getRegNumForOperand - some operands use different numbering schemes
/// for the same registers. For example, a VSX instruction may have any of
/// vs0-vs63 allocated whereas an Altivec instruction could only have
/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
/// register number needed for the opcode/operand number combination.
/// The operand number argument will be useful when we need to extend this
/// to instructions that use both Altivec and VSX numbering (for different
/// operands).
static unsigned PPCInstrInfo_getRegNumForOperand(const MCInstrDesc *Desc, unsigned Reg,
unsigned OpNo) {
int16_t regClass = Desc->OpInfo[OpNo].RegClass;
switch (regClass) {
// We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
// VSX32-VSX63 during encoding/disassembling
case PPC_VSSRCRegClassID:
case PPC_VSFRCRegClassID:
if (isVFRegister(Reg))
return PPC_VSX32 + (Reg - PPC_VF0);
break;
// We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
// VSX32-VSX63 during encoding/disassembling
case PPC_VSRCRegClassID:
if (isVRRegister(Reg))
return PPC_VSX32 + (Reg - PPC_V0);
break;
// Other RegClass doesn't need mapping
default:
break;
}
return Reg;
}
#endif // CS_PPC_INSTRINFO_H

21
arch/PowerPC/PPCLinkage.h Normal file
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@ -0,0 +1,21 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_PPC_LINKAGE_H
#define CS_PPC_LINKAGE_H
// Function defintions to call static LLVM functions.
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "capstone/capstone.h"
DecodeStatus PPC_LLVM_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
MCInst *MI, uint16_t *Size, uint64_t Address,
void *Info);
const char *PPC_LLVM_getRegisterName(unsigned RegNo);
void PPC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
#endif // CS_PPC_LINKAGE_H

220
arch/PowerPC/PPCMCTargetDesc.h Normal file
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@ -0,0 +1,220 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file provides PowerPC specific target descriptions.
//
//===----------------------------------------------------------------------===//
#ifndef CS_PPC_MCTARGETDESC_H
#define CS_PPC_MCTARGETDESC_H
// GCC #defines PPC on Linux but we use it as our namespace name
#undef PPC
#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "../../LEB128.h"
#include "../../MathExtras.h"
#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCRegisterInfo.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
/// Returns true iff Val consists of one contiguous run of 1s with any number of
/// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so
/// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not,
/// since all 1s are not contiguous.
static inline bool isRunOfOnes(unsigned Val, unsigned *MB, unsigned *ME)
{
if (!Val)
return false;
if (isShiftedMask_32(Val)) {
// look for the first non-zero bit
*MB = countLeadingZeros(Val);
// look for the first zero bit after the run of ones
*ME = countLeadingZeros((Val - 1) ^ Val);
return true;
} else {
Val = ~Val; // invert mask
if (isShiftedMask_32(Val)) {
// effectively look for the first zero bit
*ME = countLeadingZeros(Val) - 1;
// effectively look for the first one bit after the run of zeros
*MB = countLeadingZeros((Val - 1) ^ Val) + 1;
return true;
}
}
// no run present
return false;
}
static inline bool isRunOfOnes64(uint64_t Val, unsigned *MB, unsigned *ME)
{
if (!Val)
return false;
if (isShiftedMask_64(Val)) {
// look for the first non-zero bit
*MB = countLeadingZeros(Val);
// look for the first zero bit after the run of ones
*ME = countLeadingZeros((Val - 1) ^ Val);
return true;
} else {
Val = ~Val; // invert mask
if (isShiftedMask_64(Val)) {
// effectively look for the first zero bit
*ME = countLeadingZeros(Val) - 1;
// effectively look for the first one bit after the run of zeros
*MB = countLeadingZeros((Val - 1) ^ Val) + 1;
return true;
}
}
// no run present
return false;
}
// end namespace llvm
// Generated files will use "namespace PPC". To avoid symbol clash,
// undefine PPC here. PPC may be predefined on some hosts.
#undef PPC
// Defines symbolic names for PowerPC registers. This defines a mapping from
// register name to register number.
//
#define GET_REGINFO_ENUM
#include "PPCGenRegisterInfo.inc"
// Defines symbolic names for the PowerPC instructions.
//
#define GET_INSTRINFO_ENUM
#define GET_INSTRINFO_SCHED_ENUM
#define GET_INSTRINFO_MC_HELPER_DECLS
#define GET_INSTRINFO_MC_DESC
#include "PPCGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "PPCGenSubtargetInfo.inc"
#define PPC_REGS0_7(X) \
{ \
X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
}
#define PPC_REGS0_31(X) \
{ \
X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, \
X##11, X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, \
X##20, X##21, X##22, X##23, X##24, X##25, X##26, X##27, X##28, \
X##29, X##30, X##31 \
}
#define PPC_REGS0_63(X) \
{ \
X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, \
X##11, X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, \
X##20, X##21, X##22, X##23, X##24, X##25, X##26, X##27, X##28, \
X##29, X##30, X##31, X##32, X##33, X##34, X##35, X##36, X##37, \
X##38, X##39, X##40, X##41, X##42, X##43, X##44, X##45, X##46, \
X##47, X##48, X##49, X##50, X##51, X##52, X##53, X##54, X##55, \
X##56, X##57, X##58, X##59, X##60, X##61, X##62, X##63 \
}
#define PPC_REGS_NO0_31(Z, X) \
{ \
Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, \
X##21, X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, \
X##30, X##31 \
}
#define PPC_REGS_LO_HI(LO, HI) \
{ \
LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \
LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \
LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \
LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, \
HI##2, HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, \
HI##11, HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, \
HI##19, HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, \
HI##27, HI##28, HI##29, HI##30, HI##31 \
}
#define PPC_REGS0_7(X) \
{ \
X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
}
#define PPC_REGS0_3(X) \
{ \
X##0, X##1, X##2, X##3 \
}
#define DEFINE_PPC_REGCLASSES \
static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC_R); \
static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC_X); \
static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC_F); \
static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC_VSRp); \
static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC_S); \
static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC_VF); \
static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC_V); \
static const MCPhysReg RRegsNoR0[32] = PPC_REGS_NO0_31(PPC_ZERO, PPC_R); \
static const MCPhysReg XRegsNoX0[32] = \
PPC_REGS_NO0_31(PPC_ZERO8, PPC_X); \
static const MCPhysReg VSRegs[64] = PPC_REGS_LO_HI(PPC_VSL, PPC_V); \
static const MCPhysReg VSFRegs[64] = PPC_REGS_LO_HI(PPC_F, PPC_VF); \
static const MCPhysReg VSSRegs[64] = PPC_REGS_LO_HI(PPC_F, PPC_VF); \
static const MCPhysReg CRBITRegs[32] = \
{ \
PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, PPC_CR1LT, \
PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR2LT, PPC_CR2GT, \
PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, \
PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, \
PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, \
PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, \
PPC_CR7EQ, PPC_CR7UN}; \
static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC_CR); \
static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC_ACC); \
static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC_WACC); \
static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC_WACC_HI); \
static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC_DMRROWp); \
static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC_DMRROW); \
static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC_DMR); \
static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC_DMRp);
static const MCPhysReg QFRegs[] = {
PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3,
PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7,
PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11,
PPC_QF12, PPC_QF13, PPC_QF14, PPC_QF15,
PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19,
PPC_QF20, PPC_QF21, PPC_QF22, PPC_QF23,
PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27,
PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31
};
#endif // CS_PPC_MCTARGETDESC_H

1071
arch/PowerPC/PPCMapping.c
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File diff suppressed because it is too large Load Diff

59
arch/PowerPC/PPCMapping.h
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@ -4,13 +4,25 @@
#ifndef CS_PPC_MAP_H
#define CS_PPC_MAP_H
#include "../../cs_priv.h"
#include "../../MCDisassembler.h"
#include "capstone/capstone.h"
typedef enum {
#include "PPCGenCSOpGroup.inc"
} ppc_op_group;
void PPC_init_mri(MCRegisterInfo *MRI);
void PPC_init_cs_detail(MCInst *MI);
// return name of regiser in friendly string
const char *PPC_reg_name(csh handle, unsigned int reg);
// return register id, given register name
ppc_reg PPC_name_reg(const char *name);
void PPC_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */info);
bool PPC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
// given internal insn id, return public instruction info
void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
@ -18,23 +30,46 @@ void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *PPC_insn_name(csh handle, unsigned int id);
const char *PPC_group_name(csh handle, unsigned int id);
struct ppc_alias {
typedef struct {
unsigned int id; // instruction id
int cc; // code condition
const char *mnem;
};
} ppc_alias_id;
// map instruction name to public instruction ID
ppc_insn PPC_map_insn(const char *name);
// check if this insn is relative branch
bool PPC_abs_branch(cs_struct *h, unsigned int id);
void PPC_set_mem_access(MCInst *MI, bool status);
static inline void set_mem_access(MCInst *MI, bool status)
{
PPC_set_mem_access(MI, status);
}
// map internal raw register to 'public' register
ppc_reg PPC_map_register(unsigned int r);
// given alias mnemonic, return instruction ID & CC
bool PPC_alias_insn(const char *name, struct ppc_alias *alias);
bool PPC_getFeatureBits(unsigned int mode, unsigned int feature);
void PPC_add_cs_detail(MCInst *MI, ppc_op_group op_group, va_list args);
static inline void add_cs_detail(MCInst *MI, ppc_op_group op_group, ...)
{
if (!MI->flat_insn->detail)
return;
va_list args;
va_start(args, op_group);
PPC_add_cs_detail(MI, op_group, args);
va_end(args);
}
void PPC_set_detail_op_reg(MCInst *MI, unsigned OpNum, ppc_reg Reg);
void PPC_set_detail_op_imm(MCInst *MI, unsigned OpNum, int64_t Imm);
void PPC_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val, bool is_off_reg);
void PPC_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Val,
cs_ac_type access);
void PPC_setup_op(cs_ppc_op *op);
ppc_pred PPC_get_no_hint_pred(unsigned Code);
void PPC_check_updates_cr0(MCInst *MI);
void PPC_set_instr_map_data(MCInst *MI, const uint8_t *Bytes, size_t BytesLen);
#endif

13220
arch/PowerPC/PPCMappingInsn.inc
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1731
arch/PowerPC/PPCMappingInsnName.inc
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File diff suppressed because it is too large Load Diff

9
arch/PowerPC/PPCModule.c
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@ -5,7 +5,6 @@
#include "../../utils.h"
#include "../../MCRegisterInfo.h"
#include "PPCDisassembler.h"
#include "PPCInstPrinter.h"
#include "PPCMapping.h"
#include "PPCModule.h"
@ -15,12 +14,12 @@ cs_err PPC_global_init(cs_struct *ud)
MCRegisterInfo *mri;
mri = (MCRegisterInfo *) cs_mem_malloc(sizeof(*mri));
PPC_init(mri);
ud->printer = PPC_printInst;
PPC_init_mri(mri);
ud->printer = PPC_printer;
ud->printer_info = mri;
ud->getinsn_info = mri;
ud->disasm = PPC_getInstruction;
ud->post_printer = PPC_post_printer;
ud->post_printer = NULL;
ud->reg_name = PPC_reg_name;
ud->insn_id = PPC_get_insn_id;
@ -36,7 +35,7 @@ cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value)
handle->syntax = (int) value;
if (type == CS_OPT_MODE) {
handle->mode = (cs_mode)value;
handle->mode |= (cs_mode)value;
}
return CS_ERR_OK;

90
arch/PowerPC/PPCPredicates.h
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@ -1,9 +1,22 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@ -11,52 +24,41 @@
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifndef CS_POWERPC_PPCPREDICATES_H
#define CS_POWERPC_PPCPREDICATES_H
#ifndef CS_PPC_PREDICATES_H
#define CS_PPC_PREDICATES_H
// GCC #defines PPC on Linux but we use it as our namespace name
#include "capstone/ppc.h"
#undef PPC
// NOTE: duplicate of ppc_bc in ppc.h to maitain code compatibility with LLVM
typedef enum ppc_predicate {
PPC_PRED_LT = (0 << 5) | 12,
PPC_PRED_LE = (1 << 5) | 4,
PPC_PRED_EQ = (2 << 5) | 12,
PPC_PRED_GE = (0 << 5) | 4,
PPC_PRED_GT = (1 << 5) | 12,
PPC_PRED_NE = (2 << 5) | 4,
PPC_PRED_UN = (3 << 5) | 12,
PPC_PRED_NU = (3 << 5) | 4,
PPC_PRED_LT_MINUS = (0 << 5) | 14,
PPC_PRED_LE_MINUS = (1 << 5) | 6,
PPC_PRED_EQ_MINUS = (2 << 5) | 14,
PPC_PRED_GE_MINUS = (0 << 5) | 6,
PPC_PRED_GT_MINUS = (1 << 5) | 14,
PPC_PRED_NE_MINUS = (2 << 5) | 6,
PPC_PRED_UN_MINUS = (3 << 5) | 14,
PPC_PRED_NU_MINUS = (3 << 5) | 6,
PPC_PRED_LT_PLUS = (0 << 5) | 15,
PPC_PRED_LE_PLUS = (1 << 5) | 7,
PPC_PRED_EQ_PLUS = (2 << 5) | 15,
PPC_PRED_GE_PLUS = (0 << 5) | 7,
PPC_PRED_GT_PLUS = (1 << 5) | 15,
PPC_PRED_NE_PLUS = (2 << 5) | 7,
PPC_PRED_UN_PLUS = (3 << 5) | 15,
PPC_PRED_NU_PLUS = (3 << 5) | 7,
// Generated files will use "namespace PPC". To avoid symbol clash,
// undefine PPC here. PPC may be predefined on some hosts.
#undef PPC
// When dealing with individual condition-register bits, we have simple set
// and unset predicates.
PPC_PRED_BIT_SET = 1024,
PPC_PRED_BIT_UNSET = 1025
} ppc_predicate;
// Predicates moved to ppc.h
typedef ppc_pred PPC_Predicate;
/// Invert the specified predicate. != -> ==, < -> >=.
ppc_predicate InvertPredicate(ppc_predicate Opcode);
PPC_Predicate InvertPredicate(PPC_Predicate Opcode);
/// Assume the condition register is set by MI(a,b), return the predicate if
/// we modify the instructions such that condition register is set by MI(b,a).
ppc_predicate getSwappedPredicate(ppc_predicate Opcode);
PPC_Predicate getSwappedPredicate(PPC_Predicate Opcode);
/// Return the condition without hint bits.
static inline unsigned PPC_getPredicateCondition(PPC_Predicate Opcode)
{
return (unsigned)(Opcode & ~PPC_BR_HINT_MASK);
}
#endif
/// Return the hint bits of the predicate.
static inline unsigned PPC_getPredicateHint(PPC_Predicate Opcode)
{
return (unsigned)(Opcode & PPC_BR_HINT_MASK);
}
/// Return predicate consisting of specified condition and hint bits.
static inline PPC_Predicate PPC_getPredicate(unsigned Condition, unsigned Hint)
{
return (PPC_Predicate)((Condition & ~PPC_BR_HINT_MASK) | (Hint & PPC_BR_HINT_MASK));
}
#endif // CS_PPC_PREDICATES_H

58
arch/PowerPC/PPCRegisterInfo.h Normal file
View File

@ -0,0 +1,58 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Rot127 <unisono@quyllur.org> 2022-2023 */
#ifndef CS_PPC_REGISTERINFO_H
#define CS_PPC_REGISTERINFO_H
#include "PPCMCTargetDesc.h"
/// stripRegisterPrefix - This method strips the character prefix from a
/// register name so that only the number is left. Used by for linux asm.
static const char *PPCRegisterInfo_stripRegisterPrefix(const char *RegName) {
switch (RegName[0]) {
case 'a':
if (RegName[1] == 'c' && RegName[2] == 'c')
return RegName + 3;
break;
case 'r':
case 'f':
case 'v':
if (RegName[1] == 's') {
if (RegName[2] == 'p')
return RegName + 3;
return RegName + 2;
}
return RegName + 1;
case 'c':
if (RegName[1] == 'r')
return RegName + 2;
break;
case 'w':
// For wacc and wacc_hi
if (RegName[1] == 'a' && RegName[2] == 'c' && RegName[3] == 'c') {
if (RegName[4] == '_')
return RegName + 7;
else
return RegName + 4;
}
break;
case 'd':
// For dmr, dmrp, dmrrow, dmrrowp
if (RegName[1] == 'm' && RegName[2] == 'r') {
if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w' &&
RegName[6] == 'p')
return RegName + 7;
else if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w')
return RegName + 6;
else if (RegName[3] == 'p')
return RegName + 4;
else
return RegName + 3;
}
break;
}
return RegName;
}
#endif // CS_PPC_REGISTERINFO_H

2
arch/RISCV/RISCVDisassembler.c
View File

@ -355,7 +355,7 @@ static DecodeStatus RISCVDisassembler_getInstruction(int mode, MCInst *MI,
Inst = code[0] | (code[1] << 8) | (code[2] << 16) | ((uint32_t)code[3] << 24);
init_MI_insn_detail(MI);
// Now we need mark what instruction need fix effective address output.
if (MI->csh->detail)
if (MI->csh->detail_opt)
markLSInsn(MI, Inst);
Result = decodeInstruction(DecoderTable32, MI, Inst, Address, MRI, mode);
} else {

6
arch/RISCV/RISCVInstPrinter.c
View File

@ -97,7 +97,7 @@ void RISCV_printInst(MCInst *MI, SStream *O, void *info)
printInstruction(MI, O, MRI);
//printAnnotation(O, Annot);
// fix load/store type insttuction
if (MI->csh->detail &&
if (MI->csh->detail_opt &&
MI->flat_insn->detail->riscv.need_effective_addr)
fixDetailOfEffectiveAddr(MI);
@ -123,7 +123,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
if (MCOperand_isReg(MO)) {
reg = MCOperand_getReg(MO);
printRegName(O, reg);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].type = RISCV_OP_REG;
MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].reg = reg;
MI->flat_insn->detail->riscv.op_count++;
@ -143,7 +143,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
SStream_concat(O, "-%" PRIu64, -Imm);
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].type = RISCV_OP_IMM;
MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].imm = Imm;
MI->flat_insn->detail->riscv.op_count++;

2
arch/RISCV/RISCVMapping.c
View File

@ -149,7 +149,7 @@ void RISCV_get_insn_id(cs_struct * h, cs_insn * insn, unsigned int id)
if (i != 0) {
insn->id = insns[i].mapid;
if (h->detail) {
if (h->detail_opt) {
#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read,
insns[i].regs_use, sizeof(insns[i].regs_use));

28
arch/Sparc/SparcInstPrinter.c
View File

@ -42,14 +42,14 @@ static void printOperand(MCInst *MI, int opNum, SStream *O);
static void Sparc_add_hint(MCInst *MI, unsigned int hint)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sparc.hint = hint;
}
}
static void Sparc_add_reg(MCInst *MI, unsigned int reg)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
MI->flat_insn->detail->sparc.op_count++;
@ -58,7 +58,7 @@ static void Sparc_add_reg(MCInst *MI, unsigned int reg)
static void set_mem_access(MCInst *MI, bool status)
{
if (MI->csh->detail != CS_OPT_ON)
if (MI->csh->detail_opt != CS_OPT_ON)
return;
MI->csh->doing_mem = status;
@ -75,7 +75,7 @@ static void set_mem_access(MCInst *MI, bool status)
void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
{
if (((cs_struct *)ud)->detail != CS_OPT_ON)
if (((cs_struct *)ud)->detail_opt != CS_OPT_ON)
return;
// fix up some instructions
@ -170,7 +170,7 @@ static void printOperand(MCInst *MI, int opNum, SStream *O)
printRegName(O, reg);
reg = Sparc_map_register(reg);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg;
@ -261,7 +261,7 @@ static void printOperand(MCInst *MI, int opNum, SStream *O)
printInt64(O, Imm);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = Imm;
} else {
@ -332,7 +332,7 @@ static void printCCOperand(MCInst *MI, int opNum, SStream *O)
SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC));
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->sparc.cc = (sparc_cc)CC;
}
@ -371,7 +371,7 @@ void Sparc_printInst(MCInst *MI, SStream *O, void *Info)
case SP_BPXCCNT:
case SP_TXCCri:
case SP_TXCCrr:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
// skip 'b', 't'
MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 1);
MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
@ -379,7 +379,7 @@ void Sparc_printInst(MCInst *MI, SStream *O, void *Info)
break;
case SP_BPFCCANT:
case SP_BPFCCNT:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
// skip 'fb'
MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 2);
MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
@ -391,7 +391,7 @@ void Sparc_printInst(MCInst *MI, SStream *O, void *Info)
case SP_FMOVQ_XCC:
case SP_FMOVS_ICC:
case SP_FMOVS_XCC:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
// skip 'fmovd', 'fmovq', 'fmovs'
MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 5);
MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
@ -401,7 +401,7 @@ void Sparc_printInst(MCInst *MI, SStream *O, void *Info)
case SP_MOVICCrr:
case SP_MOVXCCri:
case SP_MOVXCCrr:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
// skip 'mov'
MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 3);
MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
@ -410,7 +410,7 @@ void Sparc_printInst(MCInst *MI, SStream *O, void *Info)
case SP_V9FMOVD_FCC:
case SP_V9FMOVQ_FCC:
case SP_V9FMOVS_FCC:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
// skip 'fmovd', 'fmovq', 'fmovs'
MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 5);
MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
@ -418,7 +418,7 @@ void Sparc_printInst(MCInst *MI, SStream *O, void *Info)
break;
case SP_V9MOVFCCri:
case SP_V9MOVFCCrr:
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
// skip 'mov'
MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 3);
MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
@ -436,7 +436,7 @@ void Sparc_printInst(MCInst *MI, SStream *O, void *Info)
void Sparc_addReg(MCInst *MI, int reg)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
MI->flat_insn->detail->sparc.op_count++;

2
arch/Sparc/SparcMapping.c
View File

@ -167,7 +167,7 @@ void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
if (i != 0) {
insn->id = insns[i].mapid;
if (h->detail) {
if (h->detail_opt) {
#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);

44
arch/SystemZ/SystemZInstPrinter.c
View File

@ -49,7 +49,7 @@ static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index
SStream_concat(O, "%%%s, ", getRegisterName(Index));
SStream_concat(O, "%%%s)", getRegisterName(Base));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index);
@ -57,14 +57,14 @@ static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index
MI->flat_insn->detail->sysz.op_count++;
}
} else if (!Index) {
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp;
MI->flat_insn->detail->sysz.op_count++;
}
} else {
SStream_concat(O, "(%%%s)", getRegisterName(Index));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index);
@ -83,7 +83,7 @@ static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
SStream_concat(O, "%%%s", getRegisterName(reg));
reg = SystemZ_map_register(reg);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_REG;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].reg = reg;
MI->flat_insn->detail->sysz.op_count++;
@ -93,7 +93,7 @@ static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
printInt64(O, Imm);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Imm;
MI->flat_insn->detail->sysz.op_count++;
@ -107,7 +107,7 @@ static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O)
// assert(isUInt<1>(Value) && "Invalid u1imm argument");
printInt64(O, Value);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
MI->flat_insn->detail->sysz.op_count++;
@ -120,7 +120,7 @@ static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O)
// assert(isUInt<2>(Value) && "Invalid u2imm argument");
printInt64(O, Value);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
MI->flat_insn->detail->sysz.op_count++;
@ -133,7 +133,7 @@ static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O)
// assert(isUInt<3>(Value) && "Invalid u4imm argument");
printInt64(O, Value);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
MI->flat_insn->detail->sysz.op_count++;
@ -146,7 +146,7 @@ static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O)
// assert(isUInt<4>(Value) && "Invalid u4imm argument");
printInt64(O, Value);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
MI->flat_insn->detail->sysz.op_count++;
@ -160,7 +160,7 @@ static void printU6ImmOperand(MCInst *MI, int OpNum, SStream *O)
printUInt32(O, Value);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
MI->flat_insn->detail->sysz.op_count++;
@ -184,7 +184,7 @@ static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O)
SStream_concat(O, "-%u", -Value);
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
MI->flat_insn->detail->sysz.op_count++;
@ -201,7 +201,7 @@ static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O)
else
SStream_concat(O, "%u", Value);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
MI->flat_insn->detail->sysz.op_count++;
@ -214,7 +214,7 @@ static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O)
// assert(isUInt<12>(Value) && "Invalid u12imm argument");
printInt64(O, Value);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
MI->flat_insn->detail->sysz.op_count++;
@ -238,7 +238,7 @@ static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O)
SStream_concat(O, "-%u", -Value);
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
MI->flat_insn->detail->sysz.op_count++;
@ -255,7 +255,7 @@ static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O)
else
SStream_concat(O, "%u", Value);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
MI->flat_insn->detail->sysz.op_count++;
@ -269,7 +269,7 @@ static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O)
printInt32(O, Value);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
MI->flat_insn->detail->sysz.op_count++;
@ -283,7 +283,7 @@ static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O)
printUInt32(O, Value);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
MI->flat_insn->detail->sysz.op_count++;
@ -296,7 +296,7 @@ static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O)
// assert(isUInt<48>(Value) && "Invalid u48imm argument");
printInt64(O, Value);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
MI->flat_insn->detail->sysz.op_count++;
@ -312,7 +312,7 @@ static void printPCRelOperand(MCInst *MI, int OpNum, SStream *O)
printInt64(O, imm);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = imm;
MI->flat_insn->detail->sysz.op_count++;
@ -364,7 +364,7 @@ static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O)
SStream_concat(O, ", %%%s", getRegisterName(Base));
SStream_concat0(O, ")");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = Length;
@ -391,7 +391,7 @@ static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O)
SStream_concat(O, ", %%%s", getRegisterName(Base));
SStream_concat0(O, ")");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = (uint8_t)SystemZ_map_register(Length);
@ -418,7 +418,7 @@ static void printCond4Operand(MCInst *MI, int OpNum, SStream *O)
// assert(Imm > 0 && Imm < 15 && "Invalid condition");
SStream_concat0(O, CondNames[Imm - 1]);
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->sysz.cc = (sysz_cc)Imm;
}

2
arch/SystemZ/SystemZMapping.c
View File

@ -170,7 +170,7 @@ void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
if (i != 0) {
insn->id = insns[i].mapid;
if (h->detail) {
if (h->detail_opt) {
#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);

12
arch/TMS320C64x/TMS320C64xInstPrinter.c
View File

@ -41,7 +41,7 @@ void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
int i;
cs_tms320c64x *tms320c64x;
if (mci->csh->detail) {
if (mci->csh->detail_opt) {
tms320c64x = &mci->flat_insn->detail->tms320c64x;
for (i = 0; i < insn->detail->groups_count; i++) {
@ -147,7 +147,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
SStream_concat0(O, getRegisterName(reg));
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_REG;
MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].reg = reg;
MI->flat_insn->detail->tms320c64x.op_count++;
@ -167,7 +167,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
SStream_concat(O, "-%"PRIu64, -Imm);
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_IMM;
MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].imm = Imm;
MI->flat_insn->detail->tms320c64x.op_count++;
@ -236,7 +236,7 @@ static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
break;
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
tms320c64x = &MI->flat_insn->detail->tms320c64x;
tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
@ -322,7 +322,7 @@ static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
offset = (Val >> 7) & 0x7fff;
SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
tms320c64x = &MI->flat_insn->detail->tms320c64x;
tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
@ -344,7 +344,7 @@ static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
SStream_concat(O, "%s:%s", getRegisterName(reg + 1), getRegisterName(reg));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
tms320c64x = &MI->flat_insn->detail->tms320c64x;
tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_REGPAIR;

2
arch/TMS320C64x/TMS320C64xMapping.c
View File

@ -1698,7 +1698,7 @@ void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
if (i != 0) {
insn->id = insns[i].mapid;
if (h->detail) {
if (h->detail_opt) {
#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);

2
arch/TriCore/TriCoreMapping.c
View File

@ -145,7 +145,7 @@ static const insn_ops insn_operands[] = {
void TriCore_set_access(MCInst *MI)
{
#ifndef CAPSTONE_DIET
if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail))
if (!(MI->csh->detail_opt == CS_OPT_ON && MI->flat_insn->detail))
return;
assert(MI->Opcode < ARR_SIZE(insn_operands));

38
arch/X86/X86ATTInstPrinter.c
View File

@ -62,7 +62,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void set_mem_access(MCInst *MI, bool status)
{
if (MI->csh->detail != CS_OPT_ON)
if (MI->csh->detail_opt != CS_OPT_ON)
return;
MI->csh->doing_mem = status;
@ -312,7 +312,7 @@ static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
MCOperand *SegReg;
int reg;
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
uint8_t access[6];
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
@ -334,7 +334,7 @@ static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
_printOperand(MI, Op + 1, O);
SStream_concat0(O, ":");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg);
}
}
@ -350,7 +350,7 @@ static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
uint8_t access[6];
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
@ -368,7 +368,7 @@ static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
// DI accesses are always ES-based on non-64bit mode
if (MI->csh->mode != CS_MODE_64) {
SStream_concat0(O, "%es:(");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES;
}
} else
@ -436,7 +436,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
MCOperand *SegReg = MCInst_getOperand(MI, Op+1);
int reg;
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
uint8_t access[6];
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
@ -457,14 +457,14 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
_printOperand(MI, Op + 1, O);
SStream_concat0(O, ":");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg);
}
}
if (MCOperand_isImm(DispSpec)) {
int64_t imm = MCOperand_getImm(DispSpec);
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
if (imm < 0) {
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm);
@ -476,7 +476,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
}
}
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->x86.op_count++;
}
@ -489,7 +489,7 @@ static void printU8Imm(MCInst *MI, unsigned Op, SStream *O)
else
SStream_concat(O, "$%u", val);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = val;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = 1;
@ -544,7 +544,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
else
SStream_concat(O, "%"PRIu64, imm);
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
MI->has_imm = true;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
@ -559,7 +559,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
if (MCOperand_isReg(Op)) {
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(reg);
} else {
@ -678,7 +678,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
break;
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
@ -711,7 +711,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
int segreg;
int64_t DispVal = 1;
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
uint8_t access[6];
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
@ -734,14 +734,14 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
_printOperand(MI, Op + X86_AddrSegmentReg, O);
SStream_concat0(O, ":");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(segreg);
}
}
if (MCOperand_isImm(DispSpec)) {
DispVal = MCOperand_getImm(DispSpec);
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal;
if (DispVal) {
if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) {
@ -770,7 +770,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
SStream_concat0(O, ", ");
_printOperand(MI, Op + X86_AddrIndexReg, O);
ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op + X86_AddrScaleAmt));
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal;
if (ScaleVal != 1) {
SStream_concat(O, ", %u", ScaleVal);
@ -783,7 +783,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
SStream_concat0(O, "0");
}
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->x86.op_count++;
}
@ -874,7 +874,7 @@ void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info)
MI->flat_insn->detail->x86.operands[0].size = MI->imm_size;
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
uint8_t access[6] = {0};
// some instructions need to supply immediate 1 in the first op

2
arch/X86/X86Disassembler.c
View File

@ -1002,7 +1002,7 @@ bool X86_getInstruction(csh ud, const uint8_t *code, size_t code_len,
instr->x86_prefix[3] = insn.prefix3;
instr->xAcquireRelease = insn.xAcquireRelease;
if (handle->detail) {
if (handle->detail_opt) {
update_pub_insn(instr->flat_insn, &insn);
}

36
arch/X86/X86IntelInstPrinter.c
View File

@ -63,7 +63,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void set_mem_access(MCInst *MI, bool status)
{
if (MI->csh->detail != CS_OPT_ON)
if (MI->csh->detail_opt != CS_OPT_ON)
return;
MI->csh->doing_mem = status;
@ -454,7 +454,7 @@ static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
MCOperand *SegReg;
int reg;
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
@ -479,7 +479,7 @@ static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
// If this has a segment register, print it.
if (reg) {
_printOperand(MI, Op + 1, O);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg);
}
SStream_concat0(O, ":");
@ -494,7 +494,7 @@ static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
@ -516,7 +516,7 @@ static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
// DI accesses are always ES-based on non-64bit mode
if (MI->csh->mode != CS_MODE_64) {
SStream_concat0(O, "es:[");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES;
}
} else
@ -590,7 +590,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
MCOperand *SegReg = MCInst_getOperand(MI, Op + 1);
int reg;
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
@ -614,7 +614,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
if (reg) {
_printOperand(MI, Op + 1, O);
SStream_concat0(O, ":");
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg);
}
}
@ -623,7 +623,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
if (MCOperand_isImm(DispSpec)) {
int64_t imm = MCOperand_getImm(DispSpec);
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
if (imm < 0)
@ -634,7 +634,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
SStream_concat0(O, "]");
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->x86.op_count++;
if (MI->op1_size == 0)
@ -647,7 +647,7 @@ static void printU8Imm(MCInst *MI, unsigned Op, SStream *O)
printImm(MI, O, val, true);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
@ -712,7 +712,7 @@ void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info)
printInstruction(MI, O);
reg = X86_insn_reg_intel(MCInst_getOpcode(MI), &access1);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access[6] = {0};
#endif
@ -769,7 +769,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
printImm(MI, O, imm, true);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
@ -805,7 +805,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(reg);
} else {
@ -892,7 +892,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
break;
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
} else {
@ -935,7 +935,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg);
int reg;
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
@ -960,7 +960,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
reg = MCOperand_getReg(SegReg);
if (reg) {
_printOperand(MI, Op + X86_AddrSegmentReg, O);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg);
}
SStream_concat0(O, ":");
@ -983,7 +983,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
if (MCOperand_isImm(DispSpec)) {
int64_t DispVal = MCOperand_getImm(DispSpec);
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal;
if (DispVal) {
if (NeedPlus) {
@ -1014,7 +1014,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
SStream_concat0(O, "]");
if (MI->csh->detail)
if (MI->csh->detail_opt)
MI->flat_insn->detail->x86.op_count++;
if (MI->op1_size == 0)

24
arch/X86/X86Mapping.c
View File

@ -1018,7 +1018,7 @@ void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
if (i != -1) {
insn->id = insns[i].mapid;
if (h->detail) {
if (h->detail_opt) {
#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
@ -1864,7 +1864,7 @@ static bool valid_notrack(cs_struct *h, unsigned int opcode)
// add *CX register to regs_read[] & regs_write[]
static void add_cx(MCInst *MI)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
x86_reg cx;
if (MI->csh->mode & CS_MODE_16)
@ -2002,7 +2002,7 @@ bool X86_lockrep(MCInst *MI, SStream *O)
}
// copy normalized prefix[] back to x86.prefix[]
if (MI->csh->detail)
if (MI->csh->detail_opt)
memcpy(MI->flat_insn->detail->x86.prefix, MI->x86_prefix, ARR_SIZE(MI->x86_prefix));
return res;
@ -2010,7 +2010,7 @@ bool X86_lockrep(MCInst *MI, SStream *O)
void op_addReg(MCInst *MI, int reg)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg];
@ -2023,7 +2023,7 @@ void op_addReg(MCInst *MI, int reg)
void op_addImm(MCInst *MI, int v)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = v;
// if op_count > 0, then this operand's size is taken from the destination op
@ -2043,28 +2043,28 @@ void op_addImm(MCInst *MI, int v)
void op_addXopCC(MCInst *MI, int v)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.xop_cc = v;
}
}
void op_addSseCC(MCInst *MI, int v)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.sse_cc = v;
}
}
void op_addAvxCC(MCInst *MI, int v)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.avx_cc = v;
}
}
void op_addAvxRoundingMode(MCInst *MI, int v)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.avx_rm = v;
}
}
@ -2072,7 +2072,7 @@ void op_addAvxRoundingMode(MCInst *MI, int v)
// below functions supply details to X86GenAsmWriter*.inc
void op_addAvxZeroOpmask(MCInst *MI)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
// link with the previous operand
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].avx_zero_opmask = true;
}
@ -2080,14 +2080,14 @@ void op_addAvxZeroOpmask(MCInst *MI)
void op_addAvxSae(MCInst *MI)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->x86.avx_sae = true;
}
}
void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v)
{
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
// link with the previous operand
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].avx_bcast = v;
}

20
arch/XCore/XCoreInstPrinter.c
View File

@ -64,7 +64,7 @@ void XCore_insn_extract(MCInst *MI, const char *code)
id = XCore_reg_id(p);
if (id) {
// register
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
MI->flat_insn->detail->xcore.op_count++;
@ -86,7 +86,7 @@ void XCore_insn_extract(MCInst *MI, const char *code)
id = XCore_reg_id(p2);
if (id) {
// base register
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)id;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
@ -105,18 +105,18 @@ void XCore_insn_extract(MCInst *MI, const char *code)
id = XCore_reg_id(p2);
if (id) {
// index register
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)id;
}
} else {
// a number means disp
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = atoi(p2);
}
}
}
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->xcore.op_count++;
}
}
@ -125,7 +125,7 @@ void XCore_insn_extract(MCInst *MI, const char *code)
id = XCore_reg_id(p2);
if (id) {
// register
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
MI->flat_insn->detail->xcore.op_count++;
@ -137,7 +137,7 @@ void XCore_insn_extract(MCInst *MI, const char *code)
id = XCore_reg_id(p);
if (id) {
// register
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
MI->flat_insn->detail->xcore.op_count++;
@ -149,7 +149,7 @@ void XCore_insn_extract(MCInst *MI, const char *code)
static void set_mem_access(MCInst *MI, bool status, int reg)
{
if (MI->csh->detail != CS_OPT_ON)
if (MI->csh->detail_opt != CS_OPT_ON)
return;
MI->csh->doing_mem = status;
@ -193,7 +193,7 @@ static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
reg = MCOperand_getReg(MO);
SStream_concat0(O, getRegisterName(reg));
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
if (MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base == ARM_REG_INVALID)
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg;
@ -210,7 +210,7 @@ static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
printInt32(O, Imm);
if (MI->csh->detail) {
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = Imm;
} else {

2
arch/XCore/XCoreMapping.c
View File

@ -93,7 +93,7 @@ void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
if (i != 0) {
insn->id = insns[i].mapid;
if (h->detail) {
if (h->detail_opt) {
#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);

6
bindings/python/capstone/__init__.py
View File

@ -334,6 +334,7 @@ CS_GRP_BRANCH_RELATIVE = 7 # all relative branching instructions
CS_AC_INVALID = 0 # Invalid/unitialized access type.
CS_AC_READ = (1 << 0) # Operand that is read from.
CS_AC_WRITE = (1 << 1) # Operand that is written to.
CS_AC_READ_WRITE = (2)
# Capstone syntax value
CS_OPT_SYNTAX_DEFAULT = 1 << 1 # Default assembly syntax of all platforms (CS_OPT_SYNTAX)
@ -479,11 +480,14 @@ class _cs_detail(ctypes.Structure):
class _cs_insn(ctypes.Structure):
_fields_ = (
('id', ctypes.c_uint),
('alias_id', ctypes.c_uint64),
('address', ctypes.c_uint64),
('size', ctypes.c_uint16),
('bytes', ctypes.c_ubyte * 24),
('mnemonic', ctypes.c_char * 32),
('op_str', ctypes.c_char * 160),
('is_alias', ctypes.c_bool),
('usesAliasDetails', ctypes.c_bool),
('detail', ctypes.POINTER(_cs_detail)),
)
@ -784,7 +788,7 @@ class CsInsn(object):
elif arch == CS_ARCH_MIPS:
self.operands = mips.get_arch_info(self._raw.detail.contents.arch.mips)
elif arch == CS_ARCH_PPC:
(self.bc, self.bh, self.update_cr0, self.operands) = \
(self.bc, self.update_cr0, self.operands) = \
ppc.get_arch_info(self._raw.detail.contents.arch.ppc)
elif arch == CS_ARCH_SPARC:
(self.cc, self.hint, self.operands) = sparc.get_arch_info(self._raw.detail.contents.arch.sparc)

32
bindings/python/capstone/ppc.py
View File

@ -9,13 +9,7 @@ class PpcOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('disp', ctypes.c_int32),
)
class PpcOpCrx(ctypes.Structure):
_fields_ = (
('scale', ctypes.c_uint),
('reg', ctypes.c_uint),
('cond', ctypes.c_uint),
('offset', ctypes.c_uint),
)
class PpcOpValue(ctypes.Union):
@ -23,13 +17,25 @@ class PpcOpValue(ctypes.Union):
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', PpcOpMem),
('crx', PpcOpCrx),
)
class PpcOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', PpcOpValue),
('access', ctypes.c_uint),
)
class PpcBC(ctypes.Structure):
_fields_ = (
('bo', ctypes.c_uint8),
('bi', ctypes.c_uint8),
('crX_bit', ctypes.c_uint),
('crX', ctypes.c_uint),
('hint', ctypes.c_uint),
('pred_cr', ctypes.c_uint),
('pred_ctr', ctypes.c_uint),
('bh', ctypes.c_uint),
)
@property
@ -44,20 +50,14 @@ class PpcOp(ctypes.Structure):
def mem(self):
return self.value.mem
@property
def crx(self):
return self.value.crx
class CsPpc(ctypes.Structure):
_fields_ = (
('bc', ctypes.c_uint),
('bh', ctypes.c_uint),
('bc', PpcBC),
('update_cr0', ctypes.c_bool),
('op_count', ctypes.c_uint8),
('operands', PpcOp * 8),
)
def get_arch_info(a):
return (a.bc, a.bh, a.update_cr0, copy_ctypes_list(a.operands[:a.op_count]))
return (a.bc, a.update_cr0, copy_ctypes_list(a.operands[:a.op_count]))

5067
bindings/python/capstone/ppc_const.py
View File

File diff suppressed because it is too large Load Diff

3
bindings/python/pyx/ccapstone.pxd
View File

@ -18,11 +18,14 @@ cdef extern from "<capstone/capstone.h>":
ctypedef struct cs_insn:
unsigned int id
uint64_t alias_id;
uint64_t address
uint16_t size
uint8_t bytes[24]
char mnemonic[32]
char op_str[160]
bool is_alias;
bool usesAliasDetails;
cs_detail *detail
ctypedef enum cs_err:

49
bindings/python/test_ppc.py
View File

@ -30,33 +30,42 @@ def print_insn_detail(insn):
c = 0
for i in insn.operands:
if i.type == PPC_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.value.reg)))
if i.type == PPC_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.value.imm)))
if i.type == PPC_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
if i.value.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.disp != 0:
% (c, insn.reg_name(i.value.mem.base)))
if i.value.mem.offset != 0:
print("\t\t\toperands[%u].mem.offset: REG = %s\n" \
% (c, insn.reg_name(i.value.mem.offset)))
if i.value.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x_32(i.mem.disp)))
if i.type == PPC_OP_CRX:
print("\t\toperands[%u].type: CRX" % c)
print("\t\t\toperands[%u].crx.scale: = %u" \
% (c, i.crx.scale))
if i.crx.reg != 0:
print("\t\t\toperands[%u].crx.reg: REG = %s" \
% (c, insn.reg_name(i.crx.reg)))
if i.crx.cond != 0:
print("\t\t\toperands[%u].crx.cond: 0x%x" \
% (c, i.crx.cond))
% (c, to_x_32(i.value.mem.disp)))
if i.access == CS_AC_READ:
print("\t\toperands[%u].access: READ\n" % (c))
elif i.access == CS_AC_WRITE:
print("\t\toperands[%u].access: WRITE\n" % (c))
elif i.access == CS_AC_READ | CS_AC_WRITE:
print("\t\toperands[%u].access: READ | WRITE\n" % (c))
c += 1
if insn.bc.pred_cr != PPC_PRED_INVALID or \
insn.bc.pred_ctr != PPC_PRED_INVALID:
print("\tBranch:\n")
print("\t\tbi: %u\n" % insn.bc.bi)
print("\t\tbo: %u\n" % insn.bc.bo)
if insn.bc.bh != PPC_BH_INVALID:
print("\t\tbh: %u\n" %insn.bc.bh)
if insn.bc.pred_cr != PPC_PRED_INVALID:
print("\t\tcrX: %s\n" % insn.reg_name(insn.bc.crX))
print("\t\tpred CR-bit: %u\n" % insn.bc.pred_cr)
if insn.bc.pred_ctr != PPC_PRED_INVALID:
print("\t\tpred CTR: %u\n" % insn.bc.pred_ctr)
if insn.bc.hint != PPC_BH_INVALID:
print("\t\thint: %u\n" % insn.bc.hint)
if insn.bc:
print("\tBranch code: %u" % insn.bc)
if insn.bh:
print("\tBranch hint: %u" % insn.bh)
if insn.update_cr0:
print("\tUpdate-CR0: True")

28
cs.c
View File

@ -123,7 +123,7 @@ static const struct {
PPC_global_init,
PPC_option,
~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_BIG_ENDIAN
| CS_MODE_QPX | CS_MODE_PS),
| CS_MODE_QPX | CS_MODE_PS | CS_MODE_BOOKE),
},
#else
{ NULL, NULL, 0 },
@ -489,7 +489,7 @@ cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle)
ud->arch = arch;
ud->mode = mode;
// by default, do not break instruction into details
ud->detail = CS_OPT_OFF;
ud->detail_opt = CS_OPT_OFF;
// default skipdata setup
ud->skipdata_setup.mnemonic = SKIPDATA_MNEM;
@ -731,7 +731,7 @@ cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
return CS_ERR_OK;
case CS_OPT_DETAIL:
handle->detail = (cs_opt_value)value;
handle->detail_opt |= (cs_opt_value)value;
return CS_ERR_OK;
case CS_OPT_SKIPDATA:
@ -914,7 +914,7 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64
// relative branches need to know the address & size of current insn
mci.address = offset;
if (handle->detail) {
if (handle->detail_opt) {
// allocate memory for @detail pointer
insn_cache->detail = cs_mem_malloc(sizeof(cs_detail));
} else {
@ -953,7 +953,7 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64
// encounter a broken instruction
// free memory of @detail pointer
if (handle->detail) {
if (handle->detail_opt) {
cs_mem_free(insn_cache->detail);
}
@ -1008,7 +1008,7 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64
total_size += (sizeof(cs_insn) * cache_size);
tmp = cs_mem_realloc(total, total_size);
if (tmp == NULL) { // insufficient memory
if (handle->detail) {
if (handle->detail_opt) {
insn_cache = (cs_insn *)total;
for (i = 0; i < c; i++, insn_cache++)
cs_mem_free(insn_cache->detail);
@ -1043,7 +1043,7 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64
tmp = cs_mem_realloc(total, total_size - (cache_size - f) * sizeof(*insn_cache));
if (tmp == NULL) { // insufficient memory
// free all detail pointers
if (handle->detail) {
if (handle->detail_opt) {
insn_cache = (cs_insn *)total;
for (i = 0; i < c; i++, insn_cache++)
cs_mem_free(insn_cache->detail);
@ -1089,7 +1089,7 @@ cs_insn * CAPSTONE_API cs_malloc(csh ud)
handle->errnum = CS_ERR_MEM;
return NULL;
} else {
if (handle->detail) {
if (handle->detail_opt) {
// allocate memory for @detail pointer
insn->detail = cs_mem_malloc(sizeof(cs_detail));
if (insn->detail == NULL) { // insufficient memory
@ -1246,7 +1246,7 @@ bool CAPSTONE_API cs_insn_group(csh ud, const cs_insn *insn, unsigned int group_
handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
if (!handle->detail_opt) {
handle->errnum = CS_ERR_DETAIL;
return false;
}
@ -1273,7 +1273,7 @@ bool CAPSTONE_API cs_reg_read(csh ud, const cs_insn *insn, unsigned int reg_id)
handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
if (!handle->detail_opt) {
handle->errnum = CS_ERR_DETAIL;
return false;
}
@ -1300,7 +1300,7 @@ bool CAPSTONE_API cs_reg_write(csh ud, const cs_insn *insn, unsigned int reg_id)
handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
if (!handle->detail_opt) {
handle->errnum = CS_ERR_DETAIL;
return false;
}
@ -1328,7 +1328,7 @@ int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type)
handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
if (!handle->detail_opt) {
handle->errnum = CS_ERR_DETAIL;
return -1;
}
@ -1447,7 +1447,7 @@ int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type,
handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
if (!handle->detail_opt) {
handle->errnum = CS_ERR_DETAIL;
return -1;
}
@ -1636,7 +1636,7 @@ cs_err CAPSTONE_API cs_regs_access(csh ud, const cs_insn *insn,
handle->errnum = CS_ERR_DIET;
return CS_ERR_DIET;
#else
if (!handle->detail) {
if (!handle->detail_opt) {
handle->errnum = CS_ERR_DETAIL;
return CS_ERR_DETAIL;
}

10
cs_priv.h
View File

@ -69,7 +69,8 @@ struct cs_struct {
ARM_ITBlock ITBlock; // for Arm only
ARM_VPTBlock VPTBlock; // for ARM only
bool PrintBranchImmNotAsAddress;
cs_opt_value detail, imm_unsigned;
bool ShowVSRNumsAsVR;
cs_opt_value detail_opt, imm_unsigned;
int syntax; // asm syntax for simple printer such as ARM, Mips & PPC
bool doing_mem; // handling memory operand in InstPrinter code
bool doing_SME_Index; // handling a SME instruction that has index
@ -87,6 +88,13 @@ struct cs_struct {
// Returns a bool (0 or 1) whether big endian is enabled for a mode
#define MODE_IS_BIG_ENDIAN(mode) (((mode) & CS_MODE_BIG_ENDIAN) != 0)
/// Returns true of the 16bit flag is set.
#define IS_16BIT(mode) ((mode & CS_MODE_16) != 0)
/// Returns true of the 32bit flag is set.
#define IS_32BIT(mode) ((mode & CS_MODE_32) != 0)
/// Returns true of the 64bit flag is set.
#define IS_64BIT(mode) ((mode & CS_MODE_64) != 0)
extern cs_malloc_t cs_mem_malloc;
extern cs_calloc_t cs_mem_calloc;
extern cs_realloc_t cs_mem_realloc;

18
cstool/cstool.c
View File

@ -178,7 +178,7 @@ static uint8_t *preprocess(char *code, size_t *size)
static void usage(char *prog)
{
printf("Cstool for Capstone Disassembler Engine v%u.%u.%u\n\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA);
printf("Syntax: %s [-d|-s|-u|-v] <arch+mode> <assembly-hexstring> [start-address-in-hex-format]\n", prog);
printf("Syntax: %s [-d|-a|-r|-s|-u|-v] <arch+mode> <assembly-hexstring> [start-address-in-hex-format]\n", prog);
printf("\nThe following <arch+mode> options are supported:\n");
if (cs_support(CS_ARCH_X86)) {
@ -322,6 +322,8 @@ static void usage(char *prog)
printf("\nExtra options:\n");
printf(" -d show detailed information of the instructions\n");
printf(" -r show detailed information of the real instructions (even for alias)\n");
printf(" -a Print Capstone register alias (if any). Otherwise LLVM register names are emitted.\n");
printf(" -s decode in SKIPDATA mode\n");
printf(" -u show immediates as unsigned\n");
printf(" -v show version & Capstone core build info\n\n");
@ -330,6 +332,10 @@ static void usage(char *prog)
static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
{
printf("\tID: %u (%s)\n", ins->id, cs_insn_name(handle, ins->id));
if (ins->is_alias) {
printf("\tIs alias: %" PRIu64 " (%s) ", ins->alias_id, cs_insn_name(handle, ins->alias_id));
printf("with %s operand set\n", ins->usesAliasDetails ? "ALIAS" : "REAL");
}
switch(arch) {
case CS_ARCH_X86:
@ -418,13 +424,17 @@ int main(int argc, char **argv)
bool unsigned_flag = false;
bool skipdata = false;
bool custom_reg_alias = false;
bool set_real_detail = false;
int args_left;
while ((c = getopt (argc, argv, "asudhv")) != -1) {
while ((c = getopt (argc, argv, "rasudhv")) != -1) {
switch (c) {
case 'a':
custom_reg_alias = true;
break;
case 'r':
set_real_detail = true;
break;
case 's':
skipdata = true;
break;
@ -593,6 +603,10 @@ int main(int argc, char **argv)
cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_CS_REG_ALIAS);
}
if (set_real_detail) {
cs_option(handle, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL);
}
count = cs_disasm(handle, assembly, size, address, 0, &insn);
if (count > 0) {
size_t i;

121
cstool/cstool_powerpc.c
View File

@ -4,34 +4,58 @@
#include <stdio.h>
#include <capstone/capstone.h>
#include "capstone/ppc.h"
#include "cstool.h"
static const char* get_bc_name(int bc)
static const char* get_pred_name(ppc_pred pred)
{
switch(bc) {
switch(pred) {
default:
case PPC_BC_INVALID:
return ("invalid");
case PPC_BC_LT:
case PPC_PRED_LT:
case PPC_PRED_LT_MINUS:
case PPC_PRED_LT_PLUS:
return ("lt");
case PPC_BC_LE:
case PPC_PRED_LE:
case PPC_PRED_LE_MINUS:
case PPC_PRED_LE_PLUS:
return ("le");
case PPC_BC_EQ:
case PPC_PRED_EQ:
case PPC_PRED_EQ_MINUS:
case PPC_PRED_EQ_PLUS:
return ("eq");
case PPC_BC_GE:
case PPC_PRED_GE:
case PPC_PRED_GE_MINUS:
case PPC_PRED_GE_PLUS:
return ("ge");
case PPC_BC_GT:
case PPC_PRED_GT:
case PPC_PRED_GT_MINUS:
case PPC_PRED_GT_PLUS:
return ("gt");
case PPC_BC_NE:
case PPC_PRED_NE:
case PPC_PRED_NE_MINUS:
case PPC_PRED_NE_PLUS:
return ("ne");
case PPC_BC_UN:
return ("un");
case PPC_BC_NU:
return ("nu");
case PPC_BC_SO:
return ("so");
case PPC_BC_NS:
return ("ns");
case PPC_PRED_UN: // PPC_PRED_SO
case PPC_PRED_UN_MINUS:
case PPC_PRED_UN_PLUS:
return ("so/un");
case PPC_PRED_NU: // PPC_PRED_NS
case PPC_PRED_NU_MINUS:
case PPC_PRED_NU_PLUS:
return ("ns/nu");
case PPC_PRED_NZ:
case PPC_PRED_NZ_MINUS:
case PPC_PRED_NZ_PLUS:
return ("nz");
case PPC_PRED_Z:
case PPC_PRED_Z_MINUS:
case PPC_PRED_Z_PLUS:
return ("z");
case PPC_PRED_BIT_SET:
return "bit-set";
case PPC_PRED_BIT_UNSET:
return "bit-unset";
}
}
@ -64,25 +88,70 @@ void print_insn_detail_ppc(csh handle, cs_insn *ins)
if (op->mem.base != PPC_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n",
i, cs_reg_name(handle, op->mem.base));
if (op->mem.offset != PPC_REG_INVALID)
printf("\t\t\toperands[%u].mem.offset: REG = %s\n", i,
cs_reg_name(handle, op->mem.offset));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
break;
case PPC_OP_CRX:
printf("\t\toperands[%u].type: CRX\n", i);
printf("\t\t\toperands[%u].crx.scale: %d\n", i, op->crx.scale);
printf("\t\t\toperands[%u].crx.reg: %s\n", i, cs_reg_name(handle, op->crx.reg));
printf("\t\t\toperands[%u].crx.cond: %s\n", i, get_bc_name(op->crx.cond));
}
switch(op->access) {
default:
break;
case CS_AC_READ:
printf("\t\toperands[%u].access: READ\n", i);
break;
case CS_AC_WRITE:
printf("\t\toperands[%u].access: WRITE\n", i);
break;
case CS_AC_READ_WRTE:
printf("\t\toperands[%u].access: READ | WRITE\n", i);
break;
}
}
if (ppc->bc != 0)
printf("\tBranch code: %u\n", ppc->bc);
if (ppc->bc.pred_cr != PPC_PRED_INVALID ||
ppc->bc.pred_ctr != PPC_PRED_INVALID) {
printf("\tBranch:\n");
printf("\t\tbi: %u\n", ppc->bc.bi);
printf("\t\tbo: %u\n", ppc->bc.bo);
if (ppc->bc.bh != PPC_BH_INVALID)
printf("\t\tbh: %u\n", ppc->bc.bh);
if (ppc->bc.pred_cr != PPC_PRED_INVALID) {
printf("\t\tcrX: %s\n", cs_reg_name(handle, ppc->bc.crX));
printf("\t\tpred CR-bit: %s\n", get_pred_name(ppc->bc.pred_cr));
}
if (ppc->bc.pred_ctr != PPC_PRED_INVALID)
printf("\t\tpred CTR: %s\n", get_pred_name(ppc->bc.pred_ctr));
if (ppc->bc.hint != PPC_BH_INVALID)
printf("\t\thint: %u\n", ppc->bc.hint);
}
if (ppc->bh != 0)
printf("\tBranch hint: %u\n", ppc->bh);
if (ppc->bc.hint != PPC_BR_NOT_GIVEN)
printf("\tBranch hint: %u\n", ppc->bc.hint);
if (ppc->update_cr0)
printf("\tUpdate-CR0: True\n");
uint16_t *regs_read = ins->detail->regs_read;
uint16_t *regs_write = ins->detail->regs_write;
uint8_t regs_read_count = ins->detail->regs_read_count;
uint8_t regs_write_count = ins->detail->regs_write_count;
// Print out all registers accessed by this instruction (either implicit or explicit)
if (regs_read_count) {
printf("\tImplicit registers read:");
for(i = 0; i < regs_read_count; i++) {
printf(" %s", cs_reg_name(handle, regs_read[i]));
}
printf("\n");
}
if (regs_write_count) {
printf("\tImplicit registers modified:");
for(i = 0; i < regs_write_count; i++) {
printf(" %s", cs_reg_name(handle, regs_write[i]));
}
printf("\n");
}
}

72
docs/ARCHITECTURE.md
View File

@ -56,22 +56,22 @@ Here is a boiled down explanation about these steps.
**Step 1**
```
Forward to
getInstr(bytes) ┌───┐LLVM code ┌─────────┐ ┌──────────┐
┌──────────────────►│ A ├────────────► │ ├───────────►│ ├────┐
│ │ R │ │ LLVM │ │ LLVM │ │ Decode
│ │ C │ │ │ │ │ │ Instr.
│ │ H │ │ │decode(Op0) │ │◄───┘
┌────────┐ disasm(bytes) ┌──────────┴──┐ │ │ │ Disass- │ ◄──────────┤ Decoder │
│CS Core ├──────────────►│ ARCH Module │ │ │ │ embler ├──────────► │ State │
└────────┘ └─────────────┘ │ M │ │ │ │ Machine │
▲ │ A │ │ │decode(Op1) │ │
│ │ P │ │ │ ◄──────────┤ │
│ │ P │ │ ├──────────► │ │
│ │ I │ │ │ │ │
│ │ N │ │ │ │ │
└───────────────────┤ G │◄─────────────┤ │◄───────────┤ │
└───┘ └─────────┘ └──────────┘
ARCH_LLVM_getInstr(
ARCH_getInstr(bytes) ┌───┐ bytes) ┌─────────┐ ┌──────────┐
┌──────────────────────►│ A ├──────────────────► │ ├───────────►│ ├────┐
│ │ R │ │ LLVM │ │ LLVM │ │ Decode
│ │ C │ │ │ │ │ │ Instr.
│ │ H │ │ │decode(Op0) │ │◄───┘
┌────────┐ disasm(bytes) ┌──────────┴──┐ │ │ │ Disass- │ ◄──────────┤ Decoder │
│CS Core ├──────────────►│ ARCH Module │ │ │ │ embler ├──────────► │ State │
└────────┘ └─────────────┘ │ M │ │ │ │ Machine │
▲ │ A │ │ │decode(Op1) │ │
│ │ P │ │ │ ◄──────────┤ │
│ │ P │ │ ├──────────► │ │
│ │ I │ │ │ │ │
│ │ N │ │ │ │ │
└───────────────────────┤ G │◄───────────────────┤ │◄───────────┤ │
└───┘ └─────────┘ └──────────┘
```
In the first decoding step the instruction bytes get forwarded to the
@ -85,25 +85,25 @@ The disassembler and the state machine are equivalent to what `llvm-objdump` use
**Step 2**
```
printInst(
MCInst,
┌───┐ asm_buf) ┌────────┐ ┌──────────┐
┌───────────►│ A ├──────────────► │ ├───────────►│ ├──────┐
│ │ R │ │ LLVM │ │ LLVM │ │ Decode
│ │ C │ add_cs_detail │ │ │ │ │ Mnemonic
│ │ H │ (Op0) │ │ print(Op0) │ │◄─────┘
│ │ │ ◄──────────────┤ │ ◄──────────┤ │
printer(MCInst, │ │ ├──────────────► │ ├──────────► │ Asm- │
┌────────┐ asm_buf)┌──────────┴──┐ │ │ │ Inst │ │ Writer │
│CS Core ├────────────────►│ ARCH Module │ │ │ │ Printer│ │ State │
└────────┘ └─────────────┘ │ M │ add_cs_detail │ │ │ Machine │
▲ │ A │ (Op1) │ │ print(Op1) │ │
│ │ P │ ◄──────────────┤ │ ◄──────────┤ │
│ │ P ├──────────────► │ ├──────────► │ │
│ │ I │ │ │ │ │
│ │ N │ │ │ │ │
└────────────┤ G │◄───────────────┤ │◄───────────┤ │
└───┘ └────────┘ └──────────┘
ARCH_printInst( ARCH_LLVM_printInst(
MCInst, MCInst,
asm_buf) ┌───┐ asm_buf) ┌────────┐ ┌──────────┐
┌───────────────►│ A ├───────────────────► │ ├───────────►│ ├──────┐
│ │ R │ │ LLVM │ │ LLVM │ │ Decode
│ │ C │ │ │ │ │ │ Mnemonic
│ │ H │ add_cs_detail(Op0) │ │ print(Op0) │ │◄─────┘
│ │ │ ◄───────────────────┤ │ ◄──────────┤ │
printer(MCInst, │ │ ├───────────────────► │ ├──────────► │ Asm- │
┌────────┐ asm_buf)┌──────────┴──┐ │ │ │ Inst │ │ Writer │
│CS Core ├────────────────►│ ARCH Module │ │ │ │ Printer│ │ State │
└────────┘ └─────────────┘ │ M │ │ │ │ Machine │
▲ │ A │ add_cs_detail(Op1) │ │ print(Op1) │ │
│ │ P │ ◄───────────────────┤ │ ◄──────────┤ │
│ │ P ├───────────────────► │ ├──────────► │ │
│ │ I │ │ │ │ │
│ │ N │ │ │ │ │
└────────────────┤ G │◄────────────────────┤ │◄───────────┤ │
└───┘ └────────┘ └──────────┘
```
The second decoding step passes the `MCInst` and a buffer to the printer.
@ -115,4 +115,4 @@ Each time an operand is printed, the mapping component is called
to populate the `cs_insn` with the operand information and details.
Again the `InstPrinter` and `AsmWriter` are translated code from LLVM,
and with that mirror the behavior of `llvm-objdump`.
so they mirror the behavior of `llvm-objdump`.

17
include/capstone/capstone.h
View File

@ -225,6 +225,8 @@ typedef enum cs_opt_value {
CS_OPT_SYNTAX_MASM = 1 << 5, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_MOTOROLA = 1 << 6, ///< MOS65XX use $ as hex prefix
CS_OPT_SYNTAX_CS_REG_ALIAS = 1 << 7, ///< Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
CS_OPT_SYNTAX_PERCENT = 1 << 8, ///< Prints the % in front of PPC registers.
CS_OPT_DETAIL_REAL = 1 << 1, ///< If enabled, always sets the real instruction detail. Even if the instruction is an alias.
} cs_opt_value;
/// Common instruction groups - to be consistent across all architectures.
@ -366,6 +368,12 @@ typedef struct cs_insn {
/// NOTE: in Skipdata mode, "data" instruction has 0 for this id field.
unsigned int id;
/// If this instruction is an alias instruction, this member is set with
/// the alias ID.
/// Otherwise to <ARCH>_INS_INVALID.
/// -- Only supported by auto-sync archs --
uint64_t alias_id;
/// Address (EIP) of this instruction
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
uint64_t address;
@ -386,6 +394,15 @@ typedef struct cs_insn {
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
char op_str[160];
/// True: This instruction is an alias.
/// False: Otherwise.
/// -- Only supported by auto-sync archs --
bool is_alias;
/// True: The operands are the ones of the alias instructions.
/// False: The detail operands are from the real instruction.
bool usesAliasDetails;
/// Pointer to cs_detail.
/// NOTE: detail pointer is only valid when both requirements below are met:
/// (1) CS_OP_DETAIL = CS_OPT_ON

24
include/capstone/cs_operand.h
View File

@ -7,11 +7,11 @@
/// Common instruction operand types - to be consistent across all architectures.
typedef enum cs_op_type {
CS_OP_INVALID = 0, ///< uninitialized/invalid operand.
CS_OP_REG = 1, ///< Register operand.
CS_OP_IMM = 2, ///< Immediate operand.
CS_OP_FP = 3, ///< Floating-Point operand.
CS_OP_PRED = 4, ///< Predicate operand.
CS_OP_INVALID = 0, ///< uninitialized/invalid operand.
CS_OP_REG = 1, ///< Register operand.
CS_OP_IMM = 2, ///< Immediate operand.
CS_OP_FP = 3, ///< Floating-Point operand.
CS_OP_PRED = 4, ///< Predicate operand.
CS_OP_RESERVED_5 = 5,
CS_OP_RESERVED_6 = 6,
CS_OP_RESERVED_7 = 7,
@ -24,15 +24,19 @@ typedef enum cs_op_type {
CS_OP_RESERVED_14 = 14,
CS_OP_RESERVED_15 = 15,
CS_OP_SPECIAL = 0x10, ///< Special operands from archs
CS_OP_MEM = 0x80, ///< Memory operand. Can be ORed with another operand type.
CS_OP_MEM =
0x80, ///< Memory operand. Can be ORed with another operand type.
} cs_op_type;
/// Common instruction operand access types - to be consistent across all architectures.
/// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE
typedef enum cs_ac_type {
CS_AC_INVALID = 0, ///< Uninitialized/invalid access type.
CS_AC_READ = 1 << 0, ///< Operand read from memory or register.
CS_AC_WRITE = 1 << 1, ///< Operand write to memory or register.
CS_AC_INVALID = 0, ///< Uninitialized/invalid access type.
CS_AC_READ = 1 << 0, ///< Operand read from memory or register.
CS_AC_WRITE = 1 << 1, ///< Operand write to memory or register.
CS_AC_READ_WRTE =
CS_AC_READ |
CS_AC_WRITE, ///< Operand reads and writes from/to memory or register.
} cs_ac_type;
#endif // CS_OPERAND_H
#endif // CS_OPERAND_H

2743
include/capstone/ppc.h
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File diff suppressed because it is too large Load Diff

11
suite/MC/PowerPC/ppc64-encoding-bookII.s.cs
View File

@ -7,18 +7,13 @@
0x4c,0x00,0x01,0x2c = isync
0x7c,0x43,0x21,0x2d = stwcx. 2, 3, 4
0x7c,0x43,0x21,0xad = stdcx. 2, 3, 4
// 0x7c,0x40,0x04,0xac = sync 2
0x7c,0x00,0x06,0xac = eieio
// 0x7c,0x40,0x00,0x7c = wait 2
0x7c,0x02,0x18,0xac = dcbf 2, 3
0x7c,0x43,0x20,0x28 = lwarx 2, 3, 4
0x7c,0x43,0x20,0xa8 = ldarx 2, 3, 4
0x7c,0x00,0x04,0xac = sync
// 0x7c,0x20,0x04,0xac = sync 1
// 0x7c,0x40,0x04,0xac = sync 2
// 0x7c,0x00,0x00,0x7c = wait 0
// 0x7c,0x20,0x00,0x7c = wait 1
// 0x7c,0x40,0x00,0x7c = wait 2
0x7c,0x20,0x04,0xac = lwsync
0x7c,0x40,0x04,0xac = ptesync
0x7c,0x5b,0x1a,0xe6 = mftb 2, 123
0x7c,0x4c,0x42,0xe6 = mftb 2, 268
// 0x7c,0x4d,0x42,0xe6 = mftb 2, 269
0x7c,0x4d,0x42,0xe6 = mftbu 2

70
suite/MC/PowerPC/ppc64-encoding-bookIII.s.cs
View File

@ -1,35 +1,57 @@
# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME
// 0x7c,0x80,0x01,0x24 = mtmsr 4, 0
# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME+CS_MODE_BOOKE+
0x4c,0x00,0x02,0x24 = hrfid
0x4c,0x00,0x03,0x64 = nap
0x7c,0x80,0x01,0x24 = mtmsr 4
0x7c,0x81,0x01,0x24 = mtmsr 4, 1
0x7c,0x80,0x00,0xa6 = mfmsr 4
// 0x7c,0x80,0x01,0x64 = mtmsrd 4, 0
0x7c,0x80,0x01,0x64 = mtmsrd 4
0x7c,0x81,0x01,0x64 = mtmsrd 4, 1
0x7c,0x90,0x42,0xa6 = mfspr 4, 272
0x7c,0x91,0x42,0xa6 = mfspr 4, 273
0x7c,0x92,0x42,0xa6 = mfspr 4, 274
0x7c,0x93,0x42,0xa6 = mfspr 4, 275
0x7c,0x84,0x42,0xa6 = mfspr 4, 260
0x7c,0x85,0x42,0xa6 = mfspr 4, 261
0x7c,0x86,0x42,0xa6 = mfspr 4, 262
0x7c,0x87,0x42,0xa6 = mfspr 4, 263
0x7c,0x44,0x42,0xa6 = mfspr 2, 260
0x7c,0x45,0x42,0xa6 = mfspr 2, 261
0x7c,0x46,0x42,0xa6 = mfspr 2, 262
0x7c,0x47,0x42,0xa6 = mfspr 2, 263
0x7c,0x90,0x43,0xa6 = mtspr 272, 4
0x7c,0x91,0x43,0xa6 = mtspr 273, 4
0x7c,0x92,0x43,0xa6 = mtspr 274, 4
0x7c,0x93,0x43,0xa6 = mtspr 275, 4
0x7c,0x90,0x43,0xa6 = mtspr 272, 4
0x7c,0x91,0x43,0xa6 = mtspr 273, 4
0x7c,0x92,0x43,0xa6 = mtspr 274, 4
0x7c,0x93,0x43,0xa6 = mtspr 275, 4
0x7c,0x98,0x43,0xa6 = mtspr 280, 4
0x7c,0x96,0x02,0xa6 = mfspr 4, 22
0x7c,0x96,0x03,0xa6 = mtspr 22, 4
// 0x7c,0x9f,0x42,0xa6 = mfspr 4, 287
0x7c,0x99,0x02,0xa6 = mfspr 4, 25
0x7c,0x99,0x03,0xa6 = mtspr 25, 4
0x7c,0x9a,0x02,0xa6 = mfspr 4, 26
0x7c,0x9a,0x03,0xa6 = mtspr 26, 4
0x7c,0x9b,0x02,0xa6 = mfspr 4, 27
0x7c,0x9b,0x03,0xa6 = mtspr 27, 4
0x7c,0x84,0x43,0xa6 = mtspr 260, 4
0x7c,0x85,0x43,0xa6 = mtspr 261, 4
0x7c,0x86,0x43,0xa6 = mtspr 262, 4
0x7c,0x87,0x43,0xa6 = mtspr 263, 4
0x7c,0x98,0x43,0xa6 = mtasr 4
0x7c,0x96,0x02,0xa6 = mfdec 4
0x7c,0x96,0x03,0xa6 = mtdec 4
0x7c,0x9f,0x42,0xa6 = mfpvr 4
0x7c,0x99,0x02,0xa6 = mfsdr1 4
0x7c,0x99,0x03,0xa6 = mtsdr1 4
0x7c,0x9a,0x02,0xa6 = mfsrr0 4
0x7c,0x9a,0x03,0xa6 = mtsrr0 4
0x7c,0x9b,0x02,0xa6 = mfsrr1 4
0x7c,0x9b,0x03,0xa6 = mtsrr1 4
0x7c,0x00,0x23,0x64 = slbie 4
0x7c,0x80,0x2b,0x24 = slbmte 4, 5
0x7c,0x80,0x2f,0x26 = slbmfee 4, 5
0x7c,0x00,0x03,0xe4 = slbia
0x7c,0x00,0x04,0x6c = tlbsync
0x7c,0x40,0x1e,0xa6 = slbmfev 2, 3
0x7c,0x00,0x03,0xe4 = slbia
0x7c,0x80,0x2f,0xa7 = slbfee. 4, 5
0x7c,0x00,0x04,0x6c = tlbsync
0x7c,0x00,0x22,0x24 = tlbiel 4
// 0x7c,0x00,0x22,0x64 = tlbie 4,0
0x7c,0x00,0x22,0x64 = tlbie 4
0x7c,0x00,0x22,0x64 = tlbie 4
0x4c,0x00,0x00,0x64 = rfi
0x4c,0x00,0x00,0x66 = rfci
0x7d,0x80,0x01,0x06 = wrtee 12
0x7c,0x00,0x01,0x46 = wrteei 0
0x7c,0x00,0x81,0x46 = wrteei 1
0x7c,0x00,0x07,0x64 = tlbre
0x7c,0x00,0x07,0xa4 = tlbwe
0x7c,0x0b,0x66,0x24 = tlbivax 11, 12
0x7c,0x0b,0x67,0x24 = tlbsx 11, 12
0x7c,0xb0,0x62,0x9c = mfpmr 5, 400
0x7c,0xd0,0x63,0x9c = mtpmr 400, 6
0x7c,0x00,0x41,0xcc = icblc 0, 0, 8
0x7c,0x00,0x4b,0xcc = icbtls 0, 0, 9

975
suite/MC/PowerPC/ppc64-encoding-ext.s.cs
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File diff suppressed because it is too large Load Diff

57
suite/MC/PowerPC/ppc64-encoding.s.cs
View File

@ -1,23 +1,23 @@
# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, None
// 0x4c,0x8a,0x18,0x20 = bclr 4, 10, 3
// 0x4c,0x8a,0x00,0x20 = bclr 4, 10, 0
// 0x4c,0x8a,0x18,0x21 = bclrl 4, 10, 3
// 0x4c,0x8a,0x00,0x21 = bclrl 4, 10, 0
// 0x4c,0x8a,0x1c,0x20 = bcctr 4, 10, 3
// 0x4c,0x8a,0x04,0x20 = bcctr 4, 10, 0
// 0x4c,0x8a,0x1c,0x21 = bcctrl 4, 10, 3
// 0x4c,0x8a,0x04,0x21 = bcctrl 4, 10, 0
0x4c,0x43,0x22,0x02 = crand cr0eq, cr0un, cr1lt
0x4c,0x43,0x21,0xc2 = crnand cr0eq, cr0un, cr1lt
0x4c,0x43,0x23,0x82 = cror cr0eq, cr0un, cr1lt
0x4c,0x43,0x21,0x82 = crxor cr0eq, cr0un, cr1lt
0x4c,0x43,0x20,0x42 = crnor cr0eq, cr0un, cr1lt
0x4c,0x43,0x22,0x42 = creqv cr0eq, cr0un, cr1lt
0x4c,0x43,0x21,0x02 = crandc cr0eq, cr0un, cr1lt
0x4c,0x43,0x23,0x42 = crorc cr0eq, cr0un, cr1lt
# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME
0x4c,0x8a,0x18,0x20 = bclr 4, 10, 3
0x4c,0x8a,0x00,0x20 = bflr 10
0x4c,0x8a,0x18,0x21 = bclrl 4, 10, 3
0x4c,0x8a,0x00,0x21 = bflrl 10
0x4c,0x8a,0x1c,0x20 = bcctr 4, 10, 3
0x4c,0x8a,0x04,0x20 = bfctr 10
0x4c,0x8a,0x1c,0x21 = bcctrl 4, 10, 3
0x4c,0x8a,0x04,0x21 = bfctrl 10
0x4c,0x43,0x22,0x02 = crand 2, 3, 4
0x4c,0x43,0x21,0xc2 = crnand 2, 3, 4
0x4c,0x43,0x23,0x82 = cror 2, 3, 4
0x4c,0x43,0x21,0x82 = crxor 2, 3, 4
0x4c,0x43,0x20,0x42 = crnor 2, 3, 4
0x4c,0x43,0x22,0x42 = creqv 2, 3, 4
0x4c,0x43,0x21,0x02 = crandc 2, 3, 4
0x4c,0x43,0x23,0x42 = crorc 2, 3, 4
0x4d,0x0c,0x00,0x00 = mcrf 2, 3
0x44,0x00,0x00,0x22 = sc 1
// 0x44,0x00,0x00,0x02 = sc 0
0x44,0x00,0x00,0x02 = sc
0x88,0x44,0x00,0x80 = lbz 2, 128(4)
0x7c,0x43,0x20,0xae = lbzx 2, 3, 4
0x8c,0x44,0x00,0x80 = lbzu 2, 128(4)
@ -69,15 +69,14 @@
0x3c,0x43,0x00,0x80 = addis 2, 3, 128
0x7c,0x43,0x22,0x14 = add 2, 3, 4
0x7c,0x43,0x22,0x15 = add. 2, 3, 4
0x7c,0x43,0x20,0x50 = subf 2, 3, 4
0x7c,0x43,0x20,0x51 = subf. 2, 3, 4
0x7c,0x43,0x20,0x50 = sub 2, 4, 3
0x7c,0x43,0x20,0x51 = sub. 2, 4, 3
0x30,0x43,0x00,0x80 = addic 2, 3, 128
0x34,0x43,0x00,0x80 = addic. 2, 3, 128
0x20,0x43,0x00,0x04 = subfic 2, 3, 4
0x7c,0x43,0x20,0x14 = addc 2, 3, 4
0x7c,0x43,0x20,0x15 = addc. 2, 3, 4
0x7c,0x43,0x20,0x10 = subfc 2, 3, 4
0x7c,0x43,0x20,0x10 = subfc 2, 3, 4
0x7c,0x43,0x20,0x10 = subc 2, 4, 3
0x7c,0x43,0x21,0x14 = adde 2, 3, 4
0x7c,0x43,0x21,0x15 = adde. 2, 3, 4
0x7c,0x43,0x21,0x10 = subfe 2, 3, 4
@ -121,11 +120,11 @@
0x7d,0x03,0x20,0x00 = cmpw 2, 3, 4
0x29,0x03,0x00,0x80 = cmplwi 2, 3, 128
0x7d,0x03,0x20,0x40 = cmplw 2, 3, 4
// 0x0c,0x43,0x00,0x04 = twi 2, 3, 4
// 0x7c,0x43,0x20,0x08 = tw 2, 3, 4
// 0x08,0x43,0x00,0x04 = tdi 2, 3, 4
// 0x7c,0x43,0x20,0x88 = td 2, 3, 4
0x7c,0x43,0x21,0x5e = isel r2, r3, r4, cr1gt
0x0c,0x43,0x00,0x04 = twllti 3, 4
0x7c,0x43,0x20,0x08 = twllt 3, 4
0x08,0x43,0x00,0x04 = tdllti 3, 4
0x7c,0x43,0x20,0x88 = tdllt 3, 4
0x7c,0x43,0x21,0x5e = isel 2, 3, 4, 5
0x70,0x62,0x00,0x80 = andi. 2, 3, 128
0x74,0x62,0x00,0x80 = andis. 2, 3, 128
0x60,0x62,0x00,0x80 = ori 2, 3, 128
@ -152,8 +151,8 @@
0x7c,0x62,0x07,0x75 = extsb. 2, 3
0x7c,0x62,0x07,0x34 = extsh 2, 3
0x7c,0x62,0x07,0x35 = extsh. 2, 3
// 0x7c,0x62,0x00,0x34 = cntlzw 2, 3
// 0x7c,0x62,0x00,0x35 = cntlzw. 2, 3
0x7c,0x62,0x00,0x34 = cntlzw 2, 3
0x7c,0x62,0x00,0x35 = cntlzw. 2, 3
0x7c,0x62,0x02,0xf4 = popcntw 2, 3
0x7c,0x62,0x07,0xb4 = extsw 2, 3
0x7c,0x62,0x07,0xb5 = extsw. 2, 3

6
suite/MC/PowerPC/ppc64-operands.s.cs
View File

@ -25,7 +25,7 @@
0xe8,0x22,0x7f,0xfc = ld 1, 32764(2)
0xe8,0x22,0x00,0x04 = ld 1, 4(2)
0xe8,0x22,0xff,0xfc = ld 1, -4(2)
// 0x48,0x00,0x04,0x00 = b .+1024
0x48,0x00,0x04,0x00 = b .+1024
0x48,0x00,0x04,0x02 = ba 1024
// 0x41,0x82,0x04,0x00 = beq 0, .+1024
// 0x41,0x82,0x04,0x02 = beqa 0, 1024
0x41,0x82,0x04,0x00 = bt 2, .+1024
0x41,0x82,0x04,0x02 = bta 2, 1024

34
suite/auto-sync/CppTranslator/CppTranslator.py
View File

@ -1,5 +1,4 @@
#!/usr/bin/env python3
import subprocess
from pathlib import Path
import termcolor
@ -11,7 +10,7 @@ import sys
from tree_sitter.binding import Query
from Configurator import Configurator
from Helper import convert_loglevel, print_prominent_warning, get_header, run_clang_format
from Helper import convert_loglevel, print_prominent_warning, get_header, run_clang_format, get_path
from Patches.AddCSDetail import AddCSDetail
from Patches.AddOperand import AddOperand
from Patches.Assert import Assert
@ -37,6 +36,7 @@ from Patches.GetOperand import GetOperand
from Patches.GetSubReg import GetSubReg
from Patches.Includes import Includes
from Patches.InlineToStaticInline import InlineToStaticInline
from Patches.IsRegImm import IsOperandRegImm
from Patches.IsOptionalDef import IsOptionalDef
from Patches.IsPredicate import IsPredicate
from Patches.LLVMFallThrough import LLVMFallThrough
@ -57,7 +57,7 @@ from Patches.STIArgument import STIArgument
from Patches.STIFeatureBits import STIFeatureBits
from Patches.STParameter import SubtargetInfoParam
from Patches.SetOpcode import SetOpcode
from Patches.SignExtend32 import SignExtend32
from Patches.SignExtend import SignExtend
from Patches.SizeAssignments import SizeAssignment
from Patches.StreamOperation import StreamOperations
from Patches.TemplateDeclaration import TemplateDeclaration
@ -115,7 +115,8 @@ class Translator:
SetOpcode.__name__: 0,
GetOperand.__name__: 0,
GetOperandRegImm.__name__: 0,
SignExtend32.__name__: 0,
IsOperandRegImm.__name__: 0,
SignExtend.__name__: 0,
DecoderParameter.__name__: 0,
UsingDeclaration.__name__: 0,
DecoderCast.__name__: 0,
@ -159,9 +160,9 @@ class Translator:
self.ts_cpp_lang = self.configurator.get_cpp_lang()
self.parser = self.configurator.get_parser()
self.src_paths: [Path] = [Path(sp["in"]) for sp in self.conf["files_to_translate"]]
t_out_dir = self.conf_general["translation_out_dir"]
self.out_paths: [Path] = [Path(t_out_dir + sp["out"]) for sp in self.conf["files_to_translate"]]
self.src_paths: [Path] = [get_path(sp["in"]) for sp in self.conf["files_to_translate"]]
t_out_dir: Path = get_path(self.conf_general["translation_out_dir"])
self.out_paths: [Path] = [t_out_dir.joinpath(sp["out"]) for sp in self.conf["files_to_translate"]]
self.collect_template_instances()
self.init_patches()
@ -207,8 +208,8 @@ class Translator:
patch = SetOpcode(p)
elif ptype == GetOperand.__name__:
patch = GetOperand(p)
elif ptype == SignExtend32.__name__:
patch = SignExtend32(p)
elif ptype == SignExtend.__name__:
patch = SignExtend(p)
elif ptype == TemplateDeclaration.__name__:
patch = TemplateDeclaration(p, self.template_collector)
elif ptype == TemplateDefinition.__name__:
@ -285,6 +286,8 @@ class Translator:
patch = AddCSDetail(p, self.arch)
elif ptype == PrintRegImmShift.__name__:
patch = PrintRegImmShift(p)
elif ptype == IsOperandRegImm.__name__:
patch = IsOperandRegImm(p)
else:
log.fatal(f"Patch type {ptype} not in Patch init routine.")
exit(1)
@ -387,11 +390,12 @@ class Translator:
with open(self.current_src_path_out, "w") as f:
f.write(get_header())
f.write(self.src.decode("utf8"))
run_clang_format(self.out_paths, Path(self.conf_general["clang_format_file"]))
run_clang_format(self.out_paths, get_path(self.conf_general["clang_format_file"]))
def collect_template_instances(self):
search_paths = [Path(p) for p in self.conf["files_for_template_search"]]
self.template_collector = TemplateCollector(self.parser, self.ts_cpp_lang, search_paths)
search_paths = [get_path(p) for p in self.conf["files_for_template_search"]]
temp_arg_deduction = [p.encode("utf8") for p in self.conf["templates_with_arg_deduction"]]
self.template_collector = TemplateCollector(self.parser, self.ts_cpp_lang, search_paths, temp_arg_deduction)
self.template_collector.collect()
def get_patch_kwargs(self, patch):
@ -409,8 +413,10 @@ class Translator:
)
+ "\n"
)
else:
return
for f in manual_edited:
msg += f
msg += get_path(f).name + "\n"
print_prominent_warning(msg)
@ -419,7 +425,7 @@ def parse_args() -> argparse.Namespace:
prog="CppTranslator",
description="Capstones C++ to C translator for LLVM source files",
)
parser.add_argument("-a", dest="arch", help="Name of target architecture.", choices=["ARM"], required=True)
parser.add_argument("-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC"], required=True)
parser.add_argument(
"-v",
dest="verbosity",

22
suite/auto-sync/CppTranslator/Differ.py
View File

@ -23,6 +23,7 @@ from Helper import (
print_prominent_warning,
get_sha256,
run_clang_format,
get_path,
)
@ -162,16 +163,17 @@ class Differ:
self.parser = self.configurator.get_parser()
self.differ = dl.Differ()
t_out_dir = self.conf_general["translation_out_dir"]
self.translated_files = [Path(t_out_dir + sp["out"]) for sp in self.conf_arch["files_to_translate"]]
cs_arch_src = self.conf_general["cs_arch_src"]
t_out_dir: Path = get_path(self.conf_general["translation_out_dir"])
self.translated_files = [t_out_dir.joinpath(sp["out"]) for sp in self.conf_arch["files_to_translate"]]
cs_arch_src: Path = get_path(self.conf_general["cs_arch_src"])
cs_arch_src = cs_arch_src.joinpath(self.arch if self.arch != "PPC" else "PowerPC")
self.old_files = [
Path(cs_arch_src + f"/{self.arch}/" + sp["out"]) for sp in self.conf_arch["files_to_translate"]
cs_arch_src.joinpath(f"{cs_arch_src}/" + sp["out"]) for sp in self.conf_arch["files_to_translate"]
]
self.load_persistence_file()
def load_persistence_file(self) -> None:
self.persistence_filepath = Path(self.conf_general["patch_persistence_file"])
self.persistence_filepath = get_path(self.conf_general["patch_persistence_file"])
if not self.persistence_filepath.exists():
self.saved_patches = dict()
return
@ -200,9 +202,9 @@ class Differ:
Copy translated files to diff directory for editing.
"""
log.info("Copy files for editing")
diff_dir = self.conf_general["diff_out_dir"]
diff_dir: Path = get_path(self.conf_general["diff_out_dir"])
for f in self.translated_files:
dest = Path(diff_dir + f.name)
dest = diff_dir.joinpath(f.name)
copy2(f, dest)
self.diff_dest_files.append(dest)
@ -515,7 +517,7 @@ class Differ:
continue
self.add_patch(saved["apply_type"], consec_old, old_filepath, patch_coord)
elif choice == ApplyType.OLD_ALL:
continue
self.add_patch(ApplyType.OLD, consec_old, old_filepath, patch_coord)
elif choice == ApplyType.EDIT:
print(f"{bold('Editing not yet implemented.', 'light_red')}")
continue
@ -586,7 +588,7 @@ class Differ:
src = src[:start_byte] + data + src[end_byte:]
with open(filepath, "wb") as f:
f.write(src)
run_clang_format(list(file_patches.keys()), Path(self.conf_general["clang_format_file"]))
run_clang_format(list(file_patches.keys()), get_path(self.conf_general["clang_format_file"]))
return
@ -601,7 +603,7 @@ def parse_args() -> argparse.Namespace:
help="Do not apply saved diff resolutions. Ask for every diff again.",
action="store_true",
)
parser.add_argument("-a", dest="arch", help="Name of target architecture.", choices=["ARM"], required=True)
parser.add_argument("-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC"], required=True)
parser.add_argument(
"-v",
dest="verbosity",

33
suite/auto-sync/CppTranslator/Helper.py
View File

@ -1,5 +1,6 @@
import hashlib
import logging as log
import re
import shutil
import subprocess
from pathlib import Path
@ -129,7 +130,7 @@ def get_header() -> str:
"/* LLVM-commit: <commit> */\n"
"/* LLVM-tag: <tag> */\n\n"
"/* Only small edits allowed. */\n"
"/* For multiple similiar edits, please create a Patch for the translator. */\n\n"
"/* For multiple similar edits, please create a Patch for the translator. */\n\n"
"/* Capstone's C++ file translator: */\n"
"/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */\n\n"
)
@ -138,4 +139,32 @@ def get_header() -> str:
def run_clang_format(out_paths: list[Path], clang_format_file: Path):
for out_file in out_paths:
log.info(f"Format {out_file}")
subprocess.run(["clang-format-16", f"-style=file:{clang_format_file.absolute().name}", "-i", out_file])
subprocess.run(["clang-format-16", f"-style=file:{clang_format_file}", "-i", out_file])
def get_path(config_path: str) -> Path:
try:
res = subprocess.run(["git", "rev-parse", "--show-toplevel"], check=True, stdout=subprocess.PIPE)
except subprocess.CalledProcessError:
log.fatal("Could not get repository top level directory.")
exit(1)
repo_root = res.stdout.decode("utf8").strip("\n")
if not Path(repo_root).exists():
log.fatal(f'The repository root directory is not not a valid path "{repo_root}"')
exit(1)
if "{CS_ROOT}" in config_path:
p = Path(re.sub(r"\{CS_ROOT}", repo_root, config_path))
elif "{AUTO_SYNC_ROOT}" in config_path:
auto_sync_root = Path(repo_root).joinpath(Path("suite/auto-sync/"))
config_path = re.sub(r"\{AUTO_SYNC_ROOT}", ".", config_path)
p = auto_sync_root.joinpath(Path(config_path))
elif "{CPP_TRANSLATOR_ROOT}" in config_path:
cppt_root = Path(repo_root).joinpath(Path("suite/auto-sync/CppTranslator/"))
config_path = re.sub(r"\{CPP_TRANSLATOR_ROOT}", ".", config_path)
p = cppt_root.joinpath(Path(config_path))
else:
p = Path(config_path)
if not p.exists():
log.fatal(f'Path "{p.absolute().name}" in config does not exist.')
exit(1)
return p

10
suite/auto-sync/CppTranslator/Patches/AddCSDetail.py
View File

@ -19,17 +19,19 @@ class AddCSDetail(Patch):
"""
# Parameter lists of printOperand() functions we need to add `add_cs_detail()` to.
# SPaces are removed, so we only need to check the letters.
# Spaces are removed, so we only need to check the letters.
valid_param_lists = [
b"(MCInst*MI,unsignedOpNum,SStream*O)", # Default printOperand parameters.
b"(MCInst*MI,unsignedOpNo,SStream*O)", # ARM - printComplexRotationOp
b"(MCInst*MI,unsignedOpNo,SStream*O)", # ARM - printComplexRotationOp / PPC default
b"(SStream*O,ARM_AM::ShiftOpcShOpc,unsignedShImm,boolgetUseMarkup())", # ARM - printRegImmShift
b"(MCInst*MI,unsignedOpNo,SStream*O,constchar*Modifier)", # PPC - printPredicateOperand
b"(MCInst*MI,uint64_tAddress,unsignedOpNo,SStream*O)", # PPC - printBranchOperand
]
def __init__(self, priority: int, arch: str):
super().__init__(priority)
self.arch = arch
self.apply_only_to = {"files": ["ARMInstPrinter.cpp"], "archs": list()}
self.apply_only_to = {"files": ["ARMInstPrinter.cpp", "PPCInstPrinter.cpp"], "archs": list()}
def get_search_pattern(self) -> str:
return (
@ -50,7 +52,7 @@ class AddCSDetail(Patch):
fcn_def: Node = captures[0][0]
params = captures[2][0]
params = get_text(src, params.start_byte, params.end_byte)
if re.sub(b" ", b"", params) not in self.valid_param_lists:
if re.sub(b"[\n \t]", b"", params) not in self.valid_param_lists:
return get_text(src, fcn_def.start_byte, fcn_def.end_byte)
fcn_id = captures[1][0]

5
suite/auto-sync/CppTranslator/Patches/Assert.py
View File

@ -1,9 +1,4 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text
from Patches.Patch import Patch

3
suite/auto-sync/CppTranslator/Patches/ClassesDef.py
View File

@ -23,6 +23,9 @@ class ClassesDef(Patch):
return "class_specifier"
def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
if len(captures) < 2:
# Forward class definition. Ignore it.
return b""
field_decl_list = captures[1][0]
functions = list()
for field_decl in field_decl_list.named_children:

1
suite/auto-sync/CppTranslator/Patches/CreateOperand0.py
View File

@ -1,4 +1,3 @@
import logging as log
import re
from tree_sitter import Node

1
suite/auto-sync/CppTranslator/Patches/CreateOperand1.py
View File

@ -1,4 +1,3 @@
import logging as log
import re
from tree_sitter import Node

3
suite/auto-sync/CppTranslator/Patches/DeclarationInConditionClause.py
View File

@ -1,6 +1,3 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text

2
suite/auto-sync/CppTranslator/Patches/DecodeInstruction.py
View File

@ -1,5 +1,3 @@
import logging as log
from tree_sitter import Node
from Patches.HelperMethods import get_text

4
suite/auto-sync/CppTranslator/Patches/DecoderCast.py
View File

@ -1,9 +1,5 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text
from Patches.Patch import Patch

4
suite/auto-sync/CppTranslator/Patches/DecoderParameter.py
View File

@ -1,9 +1,5 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text
from Patches.Patch import Patch

6
suite/auto-sync/CppTranslator/Patches/FeatureBits.py
View File

@ -1,9 +1,5 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text, get_function_params_of_node, get_MCInst_var_name
from Patches.HelperMethods import get_text, get_MCInst_var_name
from Patches.Patch import Patch

4
suite/auto-sync/CppTranslator/Patches/FeatureBitsDecl.py
View File

@ -1,9 +1,5 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text
from Patches.Patch import Patch

3
suite/auto-sync/CppTranslator/Patches/GetNumOperands.py
View File

@ -1,6 +1,3 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text

3
suite/auto-sync/CppTranslator/Patches/GetOpcode.py
View File

@ -1,6 +1,3 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text

3
suite/auto-sync/CppTranslator/Patches/GetOperand.py
View File

@ -1,6 +1,3 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text

7
suite/auto-sync/CppTranslator/Patches/GetOperandRegImm.py
View File

@ -1,6 +1,3 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text
@ -11,6 +8,8 @@ class GetOperandRegImm(Patch):
"""
Patch OPERAND.getReg()
to MCOperand_getReg(OPERAND)
Same for isImm()
"""
def __init__(self, priority: int):
@ -21,7 +20,7 @@ class GetOperandRegImm(Patch):
"(call_expression"
" (field_expression"
" ((_) @operand)"
' ((field_identifier) @field_id (#match? @field_id "get[RI][em][gm]"))'
' ((field_identifier) @field_id (#match? @field_id "get(Reg|Imm)"))'
" )"
" (argument_list)"
") @get_operand"

3
suite/auto-sync/CppTranslator/Patches/GetSubReg.py
View File

@ -1,6 +1,3 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text, get_MCInst_var_name

3
suite/auto-sync/CppTranslator/Patches/HelperMethods.py
View File

@ -76,6 +76,7 @@ def namespace_enum(src: bytes, ns_id: bytes, enum: Node) -> bytes:
for c in enum.named_children:
if c.type == "enumerator_list":
enumerator_list = c
break
if not enumerator_list:
log.fatal("Could not find enumerator_list.")
@ -85,7 +86,7 @@ def namespace_enum(src: bytes, ns_id: bytes, enum: Node) -> bytes:
for e in enumerator_list.named_children:
if e.type == "enumerator":
enum_entry_text = get_text(src, e.start_byte, e.end_byte)
res = re.sub(enum_entry_text, ns_id + b"_" + enum_entry_text, res)
res = res.replace(enum_entry_text, ns_id + b"_" + enum_entry_text)
return res

57
suite/auto-sync/CppTranslator/Patches/Includes.py
View File

@ -1,5 +1,4 @@
import logging as log
import re
from tree_sitter import Node
@ -47,6 +46,8 @@ class Includes(Patch):
res = get_general_inc()
if self.arch == "ARM":
return res + get_ARM_includes(filename) + get_general_macros()
elif self.arch == "PPC":
return res + get_PPC_includes(filename) + get_general_macros()
else:
log.fatal(f"Includes of {self.arch} not handled.")
exit(1)
@ -61,6 +62,60 @@ def get_general_inc() -> bytes:
)
def get_PPC_includes(filename: str) -> bytes:
if filename == "PPCDisassembler.cpp":
return (
b'#include "../../LEB128.h"\n'
+ b'#include "../../MCDisassembler.h"\n'
+ b'#include "../../MCFixedLenDisassembler.h"\n'
+ b'#include "../../MCInst.h"\n'
+ b'#include "../../MCInstrDesc.h"\n'
+ b'#include "../../MCInstPrinter.h"\n'
+ b'#include "../../MCRegisterInfo.h"\n'
+ b'#include "../../SStream.h"\n'
+ b'#include "../../utils.h"\n'
+ b'#include "PPCLinkage.h"\n'
+ b'#include "PPCMapping.h"\n'
+ b'#include "PPCMCTargetDesc.h"\n'
+ b'#include "PPCPredicates.h"\n\n'
)
elif filename == "PPCInstPrinter.cpp":
return (
b'#include "../../LEB128.h"\n'
+ b'#include "../../MCInst.h"\n'
+ b'#include "../../MCInstrDesc.h"\n'
+ b'#include "../../MCInstPrinter.h"\n'
+ b'#include "../../MCRegisterInfo.h"\n'
+ b'#include "PPCInstrInfo.h"\n'
+ b'#include "PPCInstPrinter.h"\n'
+ b'#include "PPCLinkage.h"\n'
+ b'#include "PPCMCTargetDesc.h"\n'
+ b'#include "PPCMapping.h"\n'
+ b'#include "PPCPredicates.h"\n\n'
+ b'#include "PPCRegisterInfo.h"\n\n'
)
elif filename == "PPCInstPrinter.h":
return (
b'#include "../../LEB128.h"\n'
+ b'#include "../../MCDisassembler.h"\n'
+ b'#include "../../MCInst.h"\n'
+ b'#include "../../MCInstrDesc.h"\n'
+ b'#include "../../MCRegisterInfo.h"\n'
+ b'#include "../../SStream.h"\n'
+ b'#include "PPCMCTargetDesc.h"\n\n'
)
elif filename == "PPCMCTargetDesc.h":
return (
b'#include "../../LEB128.h"\n'
+ b'#include "../../MathExtras.h"\n'
+ b'#include "../../MCInst.h"\n'
+ b'#include "../../MCInstrDesc.h"\n'
+ b'#include "../../MCRegisterInfo.h"\n'
)
log.fatal(f"No includes given for PPC source file: {filename}")
exit(1)
def get_ARM_includes(filename: str) -> bytes:
if filename == "ARMDisassembler.cpp":
return (

7
suite/auto-sync/CppTranslator/Patches/IsOptionalDef.py
View File

@ -1,6 +1,3 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text
@ -9,8 +6,8 @@ from Patches.Patch import Patch
class IsOptionalDef(Patch):
"""
Patch OpInfo[i].isPredicate()
to MCOperandInfo_isPredicate(&OpInfo[i])
Patch OpInfo[i].isOptionalDef()
to MCOperandInfo_isOptionalDef(&OpInfo[i])
"""
def __init__(self, priority: int):

3
suite/auto-sync/CppTranslator/Patches/IsPredicate.py
View File

@ -1,6 +1,3 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text

41
suite/auto-sync/CppTranslator/Patches/IsRegImm.py Normal file
View File

@ -0,0 +1,41 @@
from tree_sitter import Node
from Patches.HelperMethods import get_text
from Patches.Patch import Patch
class IsOperandRegImm(Patch):
"""
Patch OPERAND.isReg()
to MCOperand_isReg(OPERAND)
Same for isImm()
"""
def __init__(self, priority: int):
super().__init__(priority)
def get_search_pattern(self) -> str:
q = (
"(call_expression"
" (field_expression"
" ((_) @operand)"
' ((field_identifier) @field_id (#match? @field_id "is(Reg|Imm)"))'
" )"
" (argument_list)"
") @is_operand"
)
return q
def get_main_capture_name(self) -> str:
return "is_operand"
def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
# The operand
operand: Node = captures[1][0]
# 'isReg()/isImm()'
get_reg_imm = captures[2][0]
fcn = get_text(src, get_reg_imm.start_byte, get_reg_imm.end_byte)
op = get_text(src, operand.start_byte, operand.end_byte)
return b"MCOperand_" + fcn + b"(" + op + b")"

4
suite/auto-sync/CppTranslator/Patches/LLVMFallThrough.py
View File

@ -1,9 +1,5 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text
from Patches.Patch import Patch

3
suite/auto-sync/CppTranslator/Patches/MethodToFunctions.py
View File

@ -1,6 +1,3 @@
import logging as log
import re
from tree_sitter import Node
from Patches.HelperMethods import get_text

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