Initial auto-sync LoongArch support (#2349)

* Initial auto-sync LoongArch support - Accompanied llvm changes: https://github.com/capstone-engine/llvm-capstone/pull/45 - MC Tests are generated from llvm - Instruction groups are implemented - Register accesses are implemented - Memory operands are handled for memory instructions - Code are formatted using clang-format of LLVM 17 - Import tests from LLVM MC - Collect operand type and access - Collect registers read/modified --------- Co-authored-by: CoA <1109673069@qq.com> * Ensure same indent for all patched lines. * Emit upper case OP_GROUP enum * Spell all enum values in capital letters. * Capticalize enums in loongarch_detail.c * Add test which contains now a tab. * Run clang-format on test_loongarch.c --------- Co-authored-by: CoA <1109673069@qq.com> Co-authored-by: Rot127 <unisono@quyllur.org>
2024-11-23 05:29:53 +00:00 · 2024-06-26 14:47:44 +08:00 · 2024-06-26 14:47:44 +08:00 · 95966a1393
commit 95966a1393
parent a3fd6ac3a4
229 changed files with 60694 additions and 57 deletions
--- a/.github/labeler.yml
+++ b/.github/labeler.yml
@ -64,6 +64,13 @@ HPPA:
  - suite/MC/HPPA/*
  - tests/test_hppa.c

+LoongArch:
+  - arch/LoongArch/*
+  - cstool/cstool_loongarch.c
+  - include/capstone/loongarch.h
+  - suite/MC/LoongArch/*
+  - tests/test_loongarch.c
+
 M680X:
  - arch/M680X/*
  - cstool/cstool_m680x.c
--- a/.github/workflows/auto-sync.yml
+++ b/.github/workflows/auto-sync.yml
@ -46,6 +46,7 @@ jobs:
          ./src/autosync/ASUpdater.py -d -a Alpha -s IncGen
          ./src/autosync/ASUpdater.py -d -a ARM -s IncGen
          ./src/autosync/ASUpdater.py -d -a PPC -s IncGen
+          ./src/autosync/ASUpdater.py -d -a LoongArch -s IncGen

      - name: CppTranslator - Patch tests
        run: |
@ -60,6 +61,7 @@ jobs:
          ./src/autosync/ASUpdater.py --ci -d -a AArch64 -s Translate
          ./src/autosync/ASUpdater.py --ci -d -a ARM -s Translate
          ./src/autosync/ASUpdater.py --ci -d -a PPC -s Translate
+          ./src/autosync/ASUpdater.py --ci -d -a LoongArch -s Translate

      - name: Test Header patcher
        run: |
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@ -81,8 +81,8 @@ if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN)
    set(CMAKE_OSX_ARCHITECTURES "x86_64;arm64")
 endif()

-set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA)
-set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha HPPA)
+set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA LOONGARCH)
+set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha HPPA LoongArch)

 list(LENGTH SUPPORTED_ARCHITECTURES count)
 math(EXPR count "${count}-1")
@ -188,6 +188,7 @@ set(HEADERS_COMMON
    include/capstone/sh.h
    include/capstone/alpha.h
    include/capstone/hppa.h
+    include/capstone/loongarch.h
 )

 set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c)
@ -654,6 +655,24 @@ if(CAPSTONE_HPPA_SUPPORT)
    set(TEST_SOURCES ${TEST_SOURCES} test_hppa.c)
 endif()

+if (CAPSTONE_LOONGARCH_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_LOONGARCH)
+    set(SOURCES_LOONGARCH
+            arch/LoongArch/LoongArchDisassembler.c
+            arch/LoongArch/LoongArchDisassemblerExtension.c
+            arch/LoongArch/LoongArchInstPrinter.c
+            arch/LoongArch/LoongArchMapping.c
+            arch/LoongArch/LoongArchModule.c
+            )
+    set(HEADERS_LOONGARCH
+            arch/LoongArch/LoongArchInstPrinter.h
+            arch/LoongArch/LoongArchMapping.h
+            arch/LoongArch/LoongArchModule.h
+            arch/LoongArch/LoongArchLinkage.h
+            )
+    set(TEST_SOURCES ${TEST_SOURCES} test_loongarch.c)
+endif ()
+
 if (CAPSTONE_OSXKERNEL_SUPPORT)
    add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
 endif()
@ -680,6 +699,7 @@ set(ALL_SOURCES
    ${SOURCES_TRICORE}
    ${SOURCES_ALPHA}
    ${SOURCES_HPPA}
+    ${SOURCES_LOONGARCH}
 )

 set(ALL_HEADERS
@ -705,6 +725,7 @@ set(ALL_HEADERS
    ${HEADERS_TRICORE}
    ${HEADERS_ALPHA}
    ${HEADERS_HPPA}
+    ${HEADERS_LOONGARCH}
 )

 ## properties
@ -770,6 +791,7 @@ source_group("Source\\SH" FILES ${SOURCES_SH})
 source_group("Source\\TriCore" FILES ${SOURCES_TRICORE})
 source_group("Source\\Alpha" FILES ${SOURCES_ALPHA})
 source_group("Source\\HPPA" FILES ${SOURCES_HPPA})
+source_group("Source\\LoongArch" FILES ${SOURCES_LOONGARCH})

 source_group("Include\\Common" FILES ${HEADERS_COMMON})
 source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
@ -793,6 +815,7 @@ source_group("Include\\SH" FILES ${HEADERS_SH})
 source_group("Include\\TriCore" FILES ${HEADERS_TRICORE})
 source_group("Include\\Alpha" FILES ${HEADERS_ALPHA})
 source_group("Include\\HPPA" FILES ${HEADERS_HPPA})
+source_group("Include\\LoongArch" FILES ${HEADERS_LOONGARCH})

 ## installation
 if(CAPSTONE_INSTALL)
--- a/COMPILE.TXT
+++ b/COMPILE.TXT
@ -90,6 +90,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 	/usr/include/capstone/capstone.h
 	/usr/include/capstone/evm.h
 	/usr/include/capstone/hppa.h
+	/usr/include/capstone/loongarch.h
 	/usr/include/capstone/m680x.h
 	/usr/include/capstone/m68k.h
 	/usr/include/capstone/mips.h
--- a/COMPILE_CMAKE.TXT
+++ b/COMPILE_CMAKE.TXT
@ -23,6 +23,7 @@ Get CMake for free from http://www.cmake.org.
  - CAPSTONE_AARCH64_SUPPORT: support AARCH64. Run cmake with -DCAPSTONE_AARCH64_SUPPORT=0 to remove AARCH64.
  - CAPSTONE_ALPHA_SUPPORT: support Alpha. Run cmake with -DCAPSTONE_ALPHA_SUPPORT=0 to remove Alpha.
  - CAPSTONE_HPPA_SUPPORT: support HPPA. Run cmake with -DCAPSTONE_HPPA_SUPPORT=0 to remove HPPA.
+  - CAPSTONE_LOONGARCH_SUPPORT: support LoongArch. Run cmake with -DCAPSTONE_LOONGARCH_SUPPORT=0 to remove LoongArch.
  - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.
  - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K.
  - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips.
@ -120,7 +121,7 @@ Get CMake for free from http://www.cmake.org.

  Will just target the x86 architecture. The list of available architectures is: ARM,
  AARCH64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX,
-  WASM, BPF, RISCV, Alpha, HPPA.
+  WASM, BPF, RISCV, Alpha, HPPA, LoongArch.
  
 (4) You can also create an installation image with cmake, by using the 'install' target.
  Use:
--- a/CREDITS.TXT
+++ b/CREDITS.TXT
@ -88,4 +88,5 @@ fanfuqiang & citypw & porto703 : RISCV architecture.
 Josh "blacktop" Maine: Arm64 architecture improvements.
 Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support)
 Billow & Sidneyp : TriCore architecture.
-Dmitry Sibirtsev: Alpha & HPPA architecture.
+Dmitry Sibirtsev: Alpha & HPPA architecture.
+Jiajie Chen & Yanglin Xun: LoongArch architecture.
--- a/MCInst.h
+++ b/MCInst.h
@ -26,6 +26,7 @@
 typedef struct MCInst MCInst;
 typedef struct cs_struct cs_struct;
 typedef struct MCOperand MCOperand;
+typedef unsigned MCRegister;

 /// MCOperand - Instances of this class represent operands of the MCInst class.
 /// This is a simple discriminated union.
--- a/14
+++ b/14
@ -345,12 +345,21 @@ ifneq (,$(findstring hppa,$(CAPSTONE_ARCHS)))
 	LIBOBJ_HPPA += $(LIBSRC_HPPA:%.c=$(OBJDIR)/%.o)
 endif

+DEP_LOONGARCH =
+DEP_LOONGARCH += $(wildcard arch/LoongArch/LoongArch*.inc)
+
+LIBOBJ_LOONGARCH =
+ifneq (,$(findstring loongarch,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_LOONGARCH
+	LIBSRC_LOONGARCH += $(wildcard arch/LoongArch/LoongArch*.c)
+	LIBOBJ_LOONGARCH += $(LIBSRC_LOONGARCH:%.c=$(OBJDIR)/%.o)
+endif

 LIBOBJ =
 LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o
 LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_AARCH64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
 LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
-LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) $(LIBOBJ_HPPA)
+LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) $(LIBOBJ_HPPA) $(LIBOBJ_LOONGARCH)


 ifeq ($(PKG_EXTRA),)
@ -488,6 +497,7 @@ $(LIBOBJ_BPF): $(DEP_BPF)
 $(LIBOBJ_TRICORE): $(DEP_TRICORE)
 $(LIBOBJ_ALPHA): $(DEP_ALPHA)
 $(LIBOBJ_HPPA): $(DEP_HPPA)
+$(LIBOBJ_LOONGARCH): $(DEP_LOONGARCH)

 ifeq ($(CAPSTONE_STATIC),yes)
 $(ARCHIVE): $(LIBOBJ)
@ -575,11 +585,13 @@ dist:

 TESTS  = test_basic test_detail test_arm test_aarch64 test_m68k test_mips test_ppc test_sparc test_tricore test_hppa
 TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf test_alpha
+TESTS += test_loongarch
 TESTS += test_basic.static test_detail.static test_arm.static test_aarch64.static
 TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static
 TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static
 TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static test_riscv.static
 TESTS += test_mos65xx.static test_wasm.static test_bpf.static test_alpha.static test_hppa.static
+TESTS += test_loongarch.static

 check: $(TESTS)

--- a/Mapping.c
+++ b/Mapping.c
@ -337,6 +337,7 @@ DEFINE_get_detail_op(tricore, TriCore);
 DEFINE_get_detail_op(aarch64, AArch64);
 DEFINE_get_detail_op(alpha, Alpha);
 DEFINE_get_detail_op(hppa, HPPA);
+DEFINE_get_detail_op(loongarch, LoongArch);

 /// Returns true if for this architecture the
 /// alias operands should be filled.
--- a/Mapping.h
+++ b/Mapping.h
@ -30,6 +30,7 @@ typedef struct insn_map {
 	bool indirect_branch;	  // indirect branch instruction?
 	union {
 		ppc_suppl_info ppc;
+		loongarch_suppl_info loongarch;
 	} suppl_info; // Supplementary information for each instruction.
 #endif
 } insn_map;
@ -135,6 +136,7 @@ DECL_get_detail_op(tricore, TriCore);
 DECL_get_detail_op(aarch64, AArch64);
 DECL_get_detail_op(alpha, Alpha);
 DECL_get_detail_op(hppa, HPPA);
+DECL_get_detail_op(loongarch, LoongArch);

 /// Increments the detail->arch.op_count by one.
 #define DEFINE_inc_detail_op_count(arch, ARCH) \
@ -162,6 +164,8 @@ DEFINE_inc_detail_op_count(alpha, Alpha);
 DEFINE_dec_detail_op_count(alpha, Alpha);
 DEFINE_inc_detail_op_count(hppa, HPPA);
 DEFINE_dec_detail_op_count(hppa, HPPA);
+DEFINE_inc_detail_op_count(loongarch, LoongArch);
+DEFINE_dec_detail_op_count(loongarch, LoongArch);

 /// Returns true if a memory operand is currently edited.
 static inline bool doing_mem(const MCInst *MI)
@ -189,6 +193,7 @@ DEFINE_get_arch_detail(tricore, TriCore);
 DEFINE_get_arch_detail(aarch64, AArch64);
 DEFINE_get_arch_detail(alpha, Alpha);
 DEFINE_get_arch_detail(hppa, HPPA);
+DEFINE_get_arch_detail(loongarch, LoongArch);

 static inline bool detail_is_set(const MCInst *MI)
 {
--- a/README.md
+++ b/README.md
@ -16,8 +16,8 @@ Created by Nguyen Anh Quynh, then developed and maintained by a small community,
 Capstone offers some unparalleled features:

 - Support multiple hardware architectures: ARM, AArch64, Alpha, BPF, Ethereum VM,
-  HP PA-RISC (HPPA), M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc,
-  SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86 (16, 32, 64).
+  LoongArch, HP PA-RISC (HPPA), M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH,
+  Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86 (16, 32, 64).

 - Having clean/simple/lightweight/intuitive architecture-neutral API.

--- a/arch/LoongArch/LoongArchDisassembler.c
+++ b/arch/LoongArch/LoongArchDisassembler.c
@ -0,0 +1,199 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- LoongArchDisassembler.cpp - Disassembler for LoongArch ------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the LoongArchDisassembler class.
+//
+//===----------------------------------------------------------------------===//
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../MCInst.h"
+#include "../../MathExtras.h"
+#include "../../MCInstPrinter.h"
+#include "../../MCDisassembler.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../cs_priv.h"
+#include "../../utils.h"
+#include "LoongArchDisassemblerExtension.h"
+#define GET_SUBTARGETINFO_ENUM
+#include "LoongArchGenSubtargetInfo.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "LoongArchGenInstrInfo.inc"
+
+#define GET_REGINFO_ENUM
+#include "LoongArchGenRegisterInfo.inc"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define DEBUG_TYPE "loongarch-disassembler"
+
+static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					   uint64_t Address,
+					   const void *Decoder)
+{
+	if (RegNo >= 32)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_R0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, uint64_t RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	if (RegNo >= 32)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_F0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, uint64_t RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	if (RegNo >= 32)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_F0_64 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCFRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					   uint64_t Address,
+					   const void *Decoder)
+{
+	if (RegNo >= 8)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_FCC0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFCSRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	if (RegNo >= 4)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_FCSR0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLSX128RegisterClass(MCInst *Inst, uint64_t RegNo,
+					      uint64_t Address,
+					      const void *Decoder)
+{
+	if (RegNo >= 32)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_VR0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLASX256RegisterClass(MCInst *Inst, uint64_t RegNo,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	if (RegNo >= 32)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_XR0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSCRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					   uint64_t Address,
+					   const void *Decoder)
+{
+	if (RegNo >= 4)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_SCR0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+#define DEFINE_decodeUImmOperand(N, P) \
+	static DecodeStatus CONCAT(decodeUImmOperand, CONCAT(N, P))( \
+		MCInst * Inst, uint64_t Imm, int64_t Address, \
+		const void *Decoder) \
+	{ \
+		MCOperand_CreateImm0(Inst, (Imm + P)); \
+		return MCDisassembler_Success; \
+	}
+DEFINE_decodeUImmOperand(2, 1);
+DEFINE_decodeUImmOperand(12, 0);
+
+#define DEFINE_decodeSImmOperand(N, S) \
+	static DecodeStatus CONCAT(decodeSImmOperand, CONCAT(N, S))( \
+		MCInst * Inst, uint64_t Imm, int64_t Address, \
+		const void *Decoder) \
+	{ \
+		MCOperand_CreateImm0(Inst, (SignExtend64((Imm << S), N + S))); \
+		return MCDisassembler_Success; \
+	}
+DEFINE_decodeSImmOperand(5, 0);
+DEFINE_decodeSImmOperand(12, 0);
+DEFINE_decodeSImmOperand(16, 0);
+DEFINE_decodeSImmOperand(20, 0);
+DEFINE_decodeSImmOperand(14, 2);
+DEFINE_decodeSImmOperand(9, 3);
+DEFINE_decodeSImmOperand(10, 2);
+DEFINE_decodeSImmOperand(11, 1);
+DEFINE_decodeSImmOperand(8, 3);
+DEFINE_decodeSImmOperand(8, 2);
+DEFINE_decodeSImmOperand(8, 1);
+DEFINE_decodeSImmOperand(8, 0);
+DEFINE_decodeSImmOperand(21, 2);
+DEFINE_decodeSImmOperand(16, 2);
+DEFINE_decodeSImmOperand(26, 2);
+DEFINE_decodeSImmOperand(13, 0);
+
+#include "LoongArchGenDisassemblerTables.inc"
+
+static DecodeStatus getInstruction(MCInst *MI, uint64_t *Size,
+				   const uint8_t *Bytes, size_t BytesLen,
+				   uint64_t Address, SStream *CS)
+{
+	uint32_t Insn;
+	DecodeStatus Result;
+
+	// We want to read exactly 4 bytes of data because all LoongArch instructions
+	// are fixed 32 bits.
+	if (BytesLen < 4) {
+		*Size = 0;
+		return MCDisassembler_Fail;
+	}
+
+	Insn = readBytes32(MI, Bytes);
+	// Calling the auto-generated decoder function.
+	Result = decodeInstruction_4(DecoderTable32, MI, Insn, Address, NULL);
+	*Size = 4;
+
+	return Result;
+}
+
+DecodeStatus LoongArch_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
+					   const uint8_t *Bytes,
+					   size_t BytesLen, uint64_t Address,
+					   SStream *CS)
+{
+	return getInstruction(MI, Size, Bytes, BytesLen, Address, CS);
+}
--- a/arch/LoongArch/LoongArchDisassemblerExtension.c
+++ b/arch/LoongArch/LoongArchDisassemblerExtension.c
@ -0,0 +1,25 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+/*    Jiajie Chen <c@jia.je>, 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#include <capstone/loongarch.h>
+
+#include "LoongArchDisassemblerExtension.h"
+
+#define GET_SUBTARGETINFO_ENUM
+#include "LoongArchGenSubtargetInfo.inc"
+
+bool LoongArch_getFeatureBits(unsigned int mode, unsigned int feature)
+{
+	// handle loongarch32/64
+	if (feature == LoongArch_Feature64Bit) {
+		if (mode & CS_MODE_LOONGARCH64)
+			return true;
+		return false;
+	}
+
+	// otherwise we support everything
+	return true;
+}
--- a/arch/LoongArch/LoongArchDisassemblerExtension.h
+++ b/arch/LoongArch/LoongArchDisassemblerExtension.h
@ -0,0 +1,14 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+/*    Jiajie Chen <c@jia.je>, 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#ifndef CS_LOONGARCH_DISASSEMBLER_EXTENSION_H
+#define CS_LOONGARCH_DISASSEMBLER_EXTENSION_H
+
+#include "capstone/capstone.h"
+
+bool LoongArch_getFeatureBits(unsigned int mode, unsigned int feature);
+
+#endif // CS_LOONGARCH_DISASSEMBLER_EXTENSION_H
--- a/arch/LoongArch/LoongArchGenAsmWriter.inc
+++ b/arch/LoongArch/LoongArchGenAsmWriter.inc
--- a/arch/LoongArch/LoongArchGenCSAliasEnum.inc
+++ b/arch/LoongArch/LoongArchGenCSAliasEnum.inc
@ -0,0 +1,20 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+	LOONGARCH_INS_ALIAS_LA, // Real instr.: LOONGARCH_PseudoLA_GOT
+	LOONGARCH_INS_ALIAS_LA_GLOBAL, // Real instr.: LOONGARCH_PseudoLA_GOT
+	LOONGARCH_INS_ALIAS_LA_LOCAL, // Real instr.: LOONGARCH_PseudoLA_PCREL
+	LOONGARCH_INS_ALIAS_NOP, // Real instr.: LOONGARCH_ANDI
+	LOONGARCH_INS_ALIAS_MOVE, // Real instr.: LOONGARCH_OR
+	LOONGARCH_INS_ALIAS_RET, // Real instr.: LOONGARCH_JIRL
+	LOONGARCH_INS_ALIAS_JR, // Real instr.: LOONGARCH_JIRL
--- a/arch/LoongArch/LoongArchGenCSAliasMnemMap.inc
+++ b/arch/LoongArch/LoongArchGenCSAliasMnemMap.inc
@ -0,0 +1,20 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+	{ LOONGARCH_INS_ALIAS_LA, "la" },
+	{ LOONGARCH_INS_ALIAS_LA_GLOBAL, "la_global" },
+	{ LOONGARCH_INS_ALIAS_LA_LOCAL, "la_local" },
+	{ LOONGARCH_INS_ALIAS_NOP, "nop" },
+	{ LOONGARCH_INS_ALIAS_MOVE, "move" },
+	{ LOONGARCH_INS_ALIAS_RET, "ret" },
+	{ LOONGARCH_INS_ALIAS_JR, "jr" },
--- a/arch/LoongArch/LoongArchGenCSFeatureName.inc
+++ b/arch/LoongArch/LoongArchGenCSFeatureName.inc
@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{ LOONGARCH_FEATURE_ISLA64, "IsLA64" },
+{ LOONGARCH_FEATURE_ISLA32, "IsLA32" },
+{ LOONGARCH_FEATURE_HASLAGLOBALWITHPCREL, "HasLaGlobalWithPcrel" },
+{ LOONGARCH_FEATURE_HASLAGLOBALWITHABS, "HasLaGlobalWithAbs" },
+{ LOONGARCH_FEATURE_HASLALOCALWITHABS, "HasLaLocalWithAbs" },
--- a/arch/LoongArch/LoongArchGenCSMappingInsn.inc
+++ b/arch/LoongArch/LoongArchGenCSMappingInsn.inc
--- a/arch/LoongArch/LoongArchGenCSMappingInsnName.inc
+++ b/arch/LoongArch/LoongArchGenCSMappingInsnName.inc
--- a/arch/LoongArch/LoongArchGenCSMappingInsnOp.inc
+++ b/arch/LoongArch/LoongArchGenCSMappingInsnOp.inc
--- a/arch/LoongArch/LoongArchGenCSOpGroup.inc
+++ b/arch/LoongArch/LoongArchGenCSOpGroup.inc
@ -0,0 +1,15 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  LOONGARCH_OP_GROUP_OPERAND = 0,
+  LOONGARCH_OP_GROUP_ATOMICMEMOP = 1,
--- a/arch/LoongArch/LoongArchGenDisassemblerTables.inc
+++ b/arch/LoongArch/LoongArchGenDisassemblerTables.inc
--- a/arch/LoongArch/LoongArchGenInstrInfo.inc
+++ b/arch/LoongArch/LoongArchGenInstrInfo.inc
--- a/arch/LoongArch/LoongArchGenRegisterInfo.inc
+++ b/arch/LoongArch/LoongArchGenRegisterInfo.inc
@ -0,0 +1,708 @@
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  LoongArch_NoRegister,
+  LoongArch_F0 = 1,
+  LoongArch_F1 = 2,
+  LoongArch_F2 = 3,
+  LoongArch_F3 = 4,
+  LoongArch_F4 = 5,
+  LoongArch_F5 = 6,
+  LoongArch_F6 = 7,
+  LoongArch_F7 = 8,
+  LoongArch_F8 = 9,
+  LoongArch_F9 = 10,
+  LoongArch_F10 = 11,
+  LoongArch_F11 = 12,
+  LoongArch_F12 = 13,
+  LoongArch_F13 = 14,
+  LoongArch_F14 = 15,
+  LoongArch_F15 = 16,
+  LoongArch_F16 = 17,
+  LoongArch_F17 = 18,
+  LoongArch_F18 = 19,
+  LoongArch_F19 = 20,
+  LoongArch_F20 = 21,
+  LoongArch_F21 = 22,
+  LoongArch_F22 = 23,
+  LoongArch_F23 = 24,
+  LoongArch_F24 = 25,
+  LoongArch_F25 = 26,
+  LoongArch_F26 = 27,
+  LoongArch_F27 = 28,
+  LoongArch_F28 = 29,
+  LoongArch_F29 = 30,
+  LoongArch_F30 = 31,
+  LoongArch_F31 = 32,
+  LoongArch_FCC0 = 33,
+  LoongArch_FCC1 = 34,
+  LoongArch_FCC2 = 35,
+  LoongArch_FCC3 = 36,
+  LoongArch_FCC4 = 37,
+  LoongArch_FCC5 = 38,
+  LoongArch_FCC6 = 39,
+  LoongArch_FCC7 = 40,
+  LoongArch_FCSR0 = 41,
+  LoongArch_FCSR1 = 42,
+  LoongArch_FCSR2 = 43,
+  LoongArch_FCSR3 = 44,
+  LoongArch_R0 = 45,
+  LoongArch_R1 = 46,
+  LoongArch_R2 = 47,
+  LoongArch_R3 = 48,
+  LoongArch_R4 = 49,
+  LoongArch_R5 = 50,
+  LoongArch_R6 = 51,
+  LoongArch_R7 = 52,
+  LoongArch_R8 = 53,
+  LoongArch_R9 = 54,
+  LoongArch_R10 = 55,
+  LoongArch_R11 = 56,
+  LoongArch_R12 = 57,
+  LoongArch_R13 = 58,
+  LoongArch_R14 = 59,
+  LoongArch_R15 = 60,
+  LoongArch_R16 = 61,
+  LoongArch_R17 = 62,
+  LoongArch_R18 = 63,
+  LoongArch_R19 = 64,
+  LoongArch_R20 = 65,
+  LoongArch_R21 = 66,
+  LoongArch_R22 = 67,
+  LoongArch_R23 = 68,
+  LoongArch_R24 = 69,
+  LoongArch_R25 = 70,
+  LoongArch_R26 = 71,
+  LoongArch_R27 = 72,
+  LoongArch_R28 = 73,
+  LoongArch_R29 = 74,
+  LoongArch_R30 = 75,
+  LoongArch_R31 = 76,
+  LoongArch_SCR0 = 77,
+  LoongArch_SCR1 = 78,
+  LoongArch_SCR2 = 79,
+  LoongArch_SCR3 = 80,
+  LoongArch_VR0 = 81,
+  LoongArch_VR1 = 82,
+  LoongArch_VR2 = 83,
+  LoongArch_VR3 = 84,
+  LoongArch_VR4 = 85,
+  LoongArch_VR5 = 86,
+  LoongArch_VR6 = 87,
+  LoongArch_VR7 = 88,
+  LoongArch_VR8 = 89,
+  LoongArch_VR9 = 90,
+  LoongArch_VR10 = 91,
+  LoongArch_VR11 = 92,
+  LoongArch_VR12 = 93,
+  LoongArch_VR13 = 94,
+  LoongArch_VR14 = 95,
+  LoongArch_VR15 = 96,
+  LoongArch_VR16 = 97,
+  LoongArch_VR17 = 98,
+  LoongArch_VR18 = 99,
+  LoongArch_VR19 = 100,
+  LoongArch_VR20 = 101,
+  LoongArch_VR21 = 102,
+  LoongArch_VR22 = 103,
+  LoongArch_VR23 = 104,
+  LoongArch_VR24 = 105,
+  LoongArch_VR25 = 106,
+  LoongArch_VR26 = 107,
+  LoongArch_VR27 = 108,
+  LoongArch_VR28 = 109,
+  LoongArch_VR29 = 110,
+  LoongArch_VR30 = 111,
+  LoongArch_VR31 = 112,
+  LoongArch_XR0 = 113,
+  LoongArch_XR1 = 114,
+  LoongArch_XR2 = 115,
+  LoongArch_XR3 = 116,
+  LoongArch_XR4 = 117,
+  LoongArch_XR5 = 118,
+  LoongArch_XR6 = 119,
+  LoongArch_XR7 = 120,
+  LoongArch_XR8 = 121,
+  LoongArch_XR9 = 122,
+  LoongArch_XR10 = 123,
+  LoongArch_XR11 = 124,
+  LoongArch_XR12 = 125,
+  LoongArch_XR13 = 126,
+  LoongArch_XR14 = 127,
+  LoongArch_XR15 = 128,
+  LoongArch_XR16 = 129,
+  LoongArch_XR17 = 130,
+  LoongArch_XR18 = 131,
+  LoongArch_XR19 = 132,
+  LoongArch_XR20 = 133,
+  LoongArch_XR21 = 134,
+  LoongArch_XR22 = 135,
+  LoongArch_XR23 = 136,
+  LoongArch_XR24 = 137,
+  LoongArch_XR25 = 138,
+  LoongArch_XR26 = 139,
+  LoongArch_XR27 = 140,
+  LoongArch_XR28 = 141,
+  LoongArch_XR29 = 142,
+  LoongArch_XR30 = 143,
+  LoongArch_XR31 = 144,
+  LoongArch_F0_64 = 145,
+  LoongArch_F1_64 = 146,
+  LoongArch_F2_64 = 147,
+  LoongArch_F3_64 = 148,
+  LoongArch_F4_64 = 149,
+  LoongArch_F5_64 = 150,
+  LoongArch_F6_64 = 151,
+  LoongArch_F7_64 = 152,
+  LoongArch_F8_64 = 153,
+  LoongArch_F9_64 = 154,
+  LoongArch_F10_64 = 155,
+  LoongArch_F11_64 = 156,
+  LoongArch_F12_64 = 157,
+  LoongArch_F13_64 = 158,
+  LoongArch_F14_64 = 159,
+  LoongArch_F15_64 = 160,
+  LoongArch_F16_64 = 161,
+  LoongArch_F17_64 = 162,
+  LoongArch_F18_64 = 163,
+  LoongArch_F19_64 = 164,
+  LoongArch_F20_64 = 165,
+  LoongArch_F21_64 = 166,
+  LoongArch_F22_64 = 167,
+  LoongArch_F23_64 = 168,
+  LoongArch_F24_64 = 169,
+  LoongArch_F25_64 = 170,
+  LoongArch_F26_64 = 171,
+  LoongArch_F27_64 = 172,
+  LoongArch_F28_64 = 173,
+  LoongArch_F29_64 = 174,
+  LoongArch_F30_64 = 175,
+  LoongArch_F31_64 = 176,
+  NUM_TARGET_REGS // 177
+};
+
+// Register classes
+
+enum {
+  LoongArch_FPR32RegClassID = 0,
+  LoongArch_GPRRegClassID = 1,
+  LoongArch_GPRTRegClassID = 2,
+  LoongArch_CFRRegClassID = 3,
+  LoongArch_FCSRRegClassID = 4,
+  LoongArch_SCRRegClassID = 5,
+  LoongArch_FPR64RegClassID = 6,
+  LoongArch_LSX128RegClassID = 7,
+  LoongArch_LASX256RegClassID = 8,
+
+};
+
+// Register alternate name indices
+
+enum {
+  LoongArch_NoRegAltName,	// 0
+  LoongArch_RegAliasName,	// 1
+  NUM_TARGET_REG_ALT_NAMES = 2
+};
+
+// Subregister indices
+
+enum {
+  LoongArch_NoSubRegister,
+  LoongArch_sub_32,	// 1
+  LoongArch_sub_64,	// 2
+  LoongArch_sub_128,	// 3
+  LoongArch_NUM_TARGET_SUBREGS
+};
+#endif // GET_REGINFO_ENUM
+
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg LoongArchRegDiffLists[] = {
+  /* 0 */ -32, 64, -144, 0,
+  /* 4 */ 144, -64, 32, 0,
+};
+
+static const uint16_t LoongArchSubRegIdxLists[] = {
+  /* 0 */ 3, 2, 1, 0,
+};
+
+static const MCRegisterDesc LoongArchRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0, 0 },
+  { 47, 3, 4, 3, 12288, 2 },
+  { 116, 3, 4, 3, 12289, 2 },
+  { 171, 3, 4, 3, 12290, 2 },
+  { 226, 3, 4, 3, 12291, 2 },
+  { 495, 3, 4, 3, 12292, 2 },
+  { 539, 3, 4, 3, 12293, 2 },
+  { 583, 3, 4, 3, 12294, 2 },
+  { 627, 3, 4, 3, 12295, 2 },
+  { 666, 3, 4, 3, 12296, 2 },
+  { 705, 3, 4, 3, 12297, 2 },
+  { 0, 3, 4, 3, 12298, 2 },
+  { 69, 3, 4, 3, 12299, 2 },
+  { 138, 3, 4, 3, 12300, 2 },
+  { 193, 3, 4, 3, 12301, 2 },
+  { 248, 3, 4, 3, 12302, 2 },
+  { 506, 3, 4, 3, 12303, 2 },
+  { 550, 3, 4, 3, 12304, 2 },
+  { 594, 3, 4, 3, 12305, 2 },
+  { 638, 3, 4, 3, 12306, 2 },
+  { 677, 3, 4, 3, 12307, 2 },
+  { 14, 3, 4, 3, 12308, 2 },
+  { 83, 3, 4, 3, 12309, 2 },
+  { 152, 3, 4, 3, 12310, 2 },
+  { 207, 3, 4, 3, 12311, 2 },
+  { 262, 3, 4, 3, 12312, 2 },
+  { 520, 3, 4, 3, 12313, 2 },
+  { 564, 3, 4, 3, 12314, 2 },
+  { 608, 3, 4, 3, 12315, 2 },
+  { 652, 3, 4, 3, 12316, 2 },
+  { 691, 3, 4, 3, 12317, 2 },
+  { 28, 3, 4, 3, 12318, 2 },
+  { 97, 3, 4, 3, 12319, 2 },
+  { 42, 3, 3, 3, 12320, 2 },
+  { 111, 3, 3, 3, 12321, 2 },
+  { 166, 3, 3, 3, 12322, 2 },
+  { 221, 3, 3, 3, 12323, 2 },
+  { 490, 3, 3, 3, 12324, 2 },
+  { 534, 3, 3, 3, 12325, 2 },
+  { 578, 3, 3, 3, 12326, 2 },
+  { 622, 3, 3, 3, 12327, 2 },
+  { 55, 3, 3, 3, 12328, 2 },
+  { 124, 3, 3, 3, 12329, 2 },
+  { 179, 3, 3, 3, 12330, 2 },
+  { 234, 3, 3, 3, 12331, 2 },
+  { 52, 3, 3, 3, 12332, 2 },
+  { 121, 3, 3, 3, 12333, 2 },
+  { 176, 3, 3, 3, 12334, 2 },
+  { 231, 3, 3, 3, 12335, 2 },
+  { 499, 3, 3, 3, 12336, 2 },
+  { 543, 3, 3, 3, 12337, 2 },
+  { 587, 3, 3, 3, 12338, 2 },
+  { 631, 3, 3, 3, 12339, 2 },
+  { 670, 3, 3, 3, 12340, 2 },
+  { 709, 3, 3, 3, 12341, 2 },
+  { 5, 3, 3, 3, 12342, 2 },
+  { 74, 3, 3, 3, 12343, 2 },
+  { 143, 3, 3, 3, 12344, 2 },
+  { 198, 3, 3, 3, 12345, 2 },
+  { 253, 3, 3, 3, 12346, 2 },
+  { 511, 3, 3, 3, 12347, 2 },
+  { 555, 3, 3, 3, 12348, 2 },
+  { 599, 3, 3, 3, 12349, 2 },
+  { 643, 3, 3, 3, 12350, 2 },
+  { 682, 3, 3, 3, 12351, 2 },
+  { 19, 3, 3, 3, 12352, 2 },
+  { 88, 3, 3, 3, 12353, 2 },
+  { 157, 3, 3, 3, 12354, 2 },
+  { 212, 3, 3, 3, 12355, 2 },
+  { 267, 3, 3, 3, 12356, 2 },
+  { 525, 3, 3, 3, 12357, 2 },
+  { 569, 3, 3, 3, 12358, 2 },
+  { 613, 3, 3, 3, 12359, 2 },
+  { 657, 3, 3, 3, 12360, 2 },
+  { 696, 3, 3, 3, 12361, 2 },
+  { 33, 3, 3, 3, 12362, 2 },
+  { 102, 3, 3, 3, 12363, 2 },
+  { 50, 3, 3, 3, 12364, 2 },
+  { 119, 3, 3, 3, 12365, 2 },
+  { 174, 3, 3, 3, 12366, 2 },
+  { 229, 3, 3, 3, 12367, 2 },
+  { 61, 1, 6, 1, 12288, 0 },
+  { 130, 1, 6, 1, 12289, 0 },
+  { 185, 1, 6, 1, 12290, 0 },
+  { 240, 1, 6, 1, 12291, 0 },
+  { 498, 1, 6, 1, 12292, 0 },
+  { 542, 1, 6, 1, 12293, 0 },
+  { 586, 1, 6, 1, 12294, 0 },
+  { 630, 1, 6, 1, 12295, 0 },
+  { 669, 1, 6, 1, 12296, 0 },
+  { 708, 1, 6, 1, 12297, 0 },
+  { 4, 1, 6, 1, 12298, 0 },
+  { 73, 1, 6, 1, 12299, 0 },
+  { 142, 1, 6, 1, 12300, 0 },
+  { 197, 1, 6, 1, 12301, 0 },
+  { 252, 1, 6, 1, 12302, 0 },
+  { 510, 1, 6, 1, 12303, 0 },
+  { 554, 1, 6, 1, 12304, 0 },
+  { 598, 1, 6, 1, 12305, 0 },
+  { 642, 1, 6, 1, 12306, 0 },
+  { 681, 1, 6, 1, 12307, 0 },
+  { 18, 1, 6, 1, 12308, 0 },
+  { 87, 1, 6, 1, 12309, 0 },
+  { 156, 1, 6, 1, 12310, 0 },
+  { 211, 1, 6, 1, 12311, 0 },
+  { 266, 1, 6, 1, 12312, 0 },
+  { 524, 1, 6, 1, 12313, 0 },
+  { 568, 1, 6, 1, 12314, 0 },
+  { 612, 1, 6, 1, 12315, 0 },
+  { 656, 1, 6, 1, 12316, 0 },
+  { 695, 1, 6, 1, 12317, 0 },
+  { 32, 1, 6, 1, 12318, 0 },
+  { 101, 1, 6, 1, 12319, 0 },
+  { 65, 0, 3, 0, 12288, 0 },
+  { 134, 0, 3, 0, 12289, 0 },
+  { 189, 0, 3, 0, 12290, 0 },
+  { 244, 0, 3, 0, 12291, 0 },
+  { 502, 0, 3, 0, 12292, 0 },
+  { 546, 0, 3, 0, 12293, 0 },
+  { 590, 0, 3, 0, 12294, 0 },
+  { 634, 0, 3, 0, 12295, 0 },
+  { 673, 0, 3, 0, 12296, 0 },
+  { 712, 0, 3, 0, 12297, 0 },
+  { 9, 0, 3, 0, 12298, 0 },
+  { 78, 0, 3, 0, 12299, 0 },
+  { 147, 0, 3, 0, 12300, 0 },
+  { 202, 0, 3, 0, 12301, 0 },
+  { 257, 0, 3, 0, 12302, 0 },
+  { 515, 0, 3, 0, 12303, 0 },
+  { 559, 0, 3, 0, 12304, 0 },
+  { 603, 0, 3, 0, 12305, 0 },
+  { 647, 0, 3, 0, 12306, 0 },
+  { 686, 0, 3, 0, 12307, 0 },
+  { 23, 0, 3, 0, 12308, 0 },
+  { 92, 0, 3, 0, 12309, 0 },
+  { 161, 0, 3, 0, 12310, 0 },
+  { 216, 0, 3, 0, 12311, 0 },
+  { 271, 0, 3, 0, 12312, 0 },
+  { 529, 0, 3, 0, 12313, 0 },
+  { 573, 0, 3, 0, 12314, 0 },
+  { 617, 0, 3, 0, 12315, 0 },
+  { 661, 0, 3, 0, 12316, 0 },
+  { 700, 0, 3, 0, 12317, 0 },
+  { 37, 0, 3, 0, 12318, 0 },
+  { 106, 0, 3, 0, 12319, 0 },
+  { 297, 2, 5, 2, 12288, 0 },
+  { 324, 2, 5, 2, 12289, 0 },
+  { 344, 2, 5, 2, 12290, 0 },
+  { 364, 2, 5, 2, 12291, 0 },
+  { 384, 2, 5, 2, 12292, 0 },
+  { 404, 2, 5, 2, 12293, 0 },
+  { 424, 2, 5, 2, 12294, 0 },
+  { 444, 2, 5, 2, 12295, 0 },
+  { 464, 2, 5, 2, 12296, 0 },
+  { 484, 2, 5, 2, 12297, 0 },
+  { 276, 2, 5, 2, 12298, 0 },
+  { 303, 2, 5, 2, 12299, 0 },
+  { 330, 2, 5, 2, 12300, 0 },
+  { 350, 2, 5, 2, 12301, 0 },
+  { 370, 2, 5, 2, 12302, 0 },
+  { 390, 2, 5, 2, 12303, 0 },
+  { 410, 2, 5, 2, 12304, 0 },
+  { 430, 2, 5, 2, 12305, 0 },
+  { 450, 2, 5, 2, 12306, 0 },
+  { 470, 2, 5, 2, 12307, 0 },
+  { 283, 2, 5, 2, 12308, 0 },
+  { 310, 2, 5, 2, 12309, 0 },
+  { 337, 2, 5, 2, 12310, 0 },
+  { 357, 2, 5, 2, 12311, 0 },
+  { 377, 2, 5, 2, 12312, 0 },
+  { 397, 2, 5, 2, 12313, 0 },
+  { 417, 2, 5, 2, 12314, 0 },
+  { 437, 2, 5, 2, 12315, 0 },
+  { 457, 2, 5, 2, 12316, 0 },
+  { 477, 2, 5, 2, 12317, 0 },
+  { 290, 2, 5, 2, 12318, 0 },
+  { 317, 2, 5, 2, 12319, 0 },
+};
+
+  // FPR32 Register Class...
+  static const MCPhysReg FPR32[] = {
+    LoongArch_F0, LoongArch_F1, LoongArch_F2, LoongArch_F3, LoongArch_F4, LoongArch_F5, LoongArch_F6, LoongArch_F7, LoongArch_F8, LoongArch_F9, LoongArch_F10, LoongArch_F11, LoongArch_F12, LoongArch_F13, LoongArch_F14, LoongArch_F15, LoongArch_F16, LoongArch_F17, LoongArch_F18, LoongArch_F19, LoongArch_F20, LoongArch_F21, LoongArch_F22, LoongArch_F23, LoongArch_F24, LoongArch_F25, LoongArch_F26, LoongArch_F27, LoongArch_F28, LoongArch_F29, LoongArch_F30, LoongArch_F31, 
+  };
+
+  // FPR32 Bit set.
+  static const uint8_t FPR32Bits[] = {
+    0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // GPR Register Class...
+  static const MCPhysReg GPR[] = {
+    LoongArch_R4, LoongArch_R5, LoongArch_R6, LoongArch_R7, LoongArch_R8, LoongArch_R9, LoongArch_R10, LoongArch_R11, LoongArch_R12, LoongArch_R13, LoongArch_R14, LoongArch_R15, LoongArch_R16, LoongArch_R17, LoongArch_R18, LoongArch_R19, LoongArch_R20, LoongArch_R22, LoongArch_R23, LoongArch_R24, LoongArch_R25, LoongArch_R26, LoongArch_R27, LoongArch_R28, LoongArch_R29, LoongArch_R30, LoongArch_R31, LoongArch_R0, LoongArch_R1, LoongArch_R2, LoongArch_R3, LoongArch_R21, 
+  };
+
+  // GPR Bit set.
+  static const uint8_t GPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
+  };
+
+  // GPRT Register Class...
+  static const MCPhysReg GPRT[] = {
+    LoongArch_R4, LoongArch_R5, LoongArch_R6, LoongArch_R7, LoongArch_R8, LoongArch_R9, LoongArch_R10, LoongArch_R11, LoongArch_R12, LoongArch_R13, LoongArch_R14, LoongArch_R15, LoongArch_R16, LoongArch_R17, LoongArch_R18, LoongArch_R19, LoongArch_R20, 
+  };
+
+  // GPRT Bit set.
+  static const uint8_t GPRTBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x03, 
+  };
+
+  // CFR Register Class...
+  static const MCPhysReg CFR[] = {
+    LoongArch_FCC0, LoongArch_FCC1, LoongArch_FCC2, LoongArch_FCC3, LoongArch_FCC4, LoongArch_FCC5, LoongArch_FCC6, LoongArch_FCC7, 
+  };
+
+  // CFR Bit set.
+  static const uint8_t CFRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
+  };
+
+  // FCSR Register Class...
+  static const MCPhysReg FCSR[] = {
+    LoongArch_FCSR0, LoongArch_FCSR1, LoongArch_FCSR2, LoongArch_FCSR3, 
+  };
+
+  // FCSR Bit set.
+  static const uint8_t FCSRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
+  };
+
+  // SCR Register Class...
+  static const MCPhysReg SCR[] = {
+    LoongArch_SCR0, LoongArch_SCR1, LoongArch_SCR2, LoongArch_SCR3, 
+  };
+
+  // SCR Bit set.
+  static const uint8_t SCRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
+  };
+
+  // FPR64 Register Class...
+  static const MCPhysReg FPR64[] = {
+    LoongArch_F0_64, LoongArch_F1_64, LoongArch_F2_64, LoongArch_F3_64, LoongArch_F4_64, LoongArch_F5_64, LoongArch_F6_64, LoongArch_F7_64, LoongArch_F8_64, LoongArch_F9_64, LoongArch_F10_64, LoongArch_F11_64, LoongArch_F12_64, LoongArch_F13_64, LoongArch_F14_64, LoongArch_F15_64, LoongArch_F16_64, LoongArch_F17_64, LoongArch_F18_64, LoongArch_F19_64, LoongArch_F20_64, LoongArch_F21_64, LoongArch_F22_64, LoongArch_F23_64, LoongArch_F24_64, LoongArch_F25_64, LoongArch_F26_64, LoongArch_F27_64, LoongArch_F28_64, LoongArch_F29_64, LoongArch_F30_64, LoongArch_F31_64, 
+  };
+
+  // FPR64 Bit set.
+  static const uint8_t FPR64Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // LSX128 Register Class...
+  static const MCPhysReg LSX128[] = {
+    LoongArch_VR0, LoongArch_VR1, LoongArch_VR2, LoongArch_VR3, LoongArch_VR4, LoongArch_VR5, LoongArch_VR6, LoongArch_VR7, LoongArch_VR8, LoongArch_VR9, LoongArch_VR10, LoongArch_VR11, LoongArch_VR12, LoongArch_VR13, LoongArch_VR14, LoongArch_VR15, LoongArch_VR16, LoongArch_VR17, LoongArch_VR18, LoongArch_VR19, LoongArch_VR20, LoongArch_VR21, LoongArch_VR22, LoongArch_VR23, LoongArch_VR24, LoongArch_VR25, LoongArch_VR26, LoongArch_VR27, LoongArch_VR28, LoongArch_VR29, LoongArch_VR30, LoongArch_VR31, 
+  };
+
+  // LSX128 Bit set.
+  static const uint8_t LSX128Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // LASX256 Register Class...
+  static const MCPhysReg LASX256[] = {
+    LoongArch_XR0, LoongArch_XR1, LoongArch_XR2, LoongArch_XR3, LoongArch_XR4, LoongArch_XR5, LoongArch_XR6, LoongArch_XR7, LoongArch_XR8, LoongArch_XR9, LoongArch_XR10, LoongArch_XR11, LoongArch_XR12, LoongArch_XR13, LoongArch_XR14, LoongArch_XR15, LoongArch_XR16, LoongArch_XR17, LoongArch_XR18, LoongArch_XR19, LoongArch_XR20, LoongArch_XR21, LoongArch_XR22, LoongArch_XR23, LoongArch_XR24, LoongArch_XR25, LoongArch_XR26, LoongArch_XR27, LoongArch_XR28, LoongArch_XR29, LoongArch_XR30, LoongArch_XR31, 
+  };
+
+  // LASX256 Bit set.
+  static const uint8_t LASX256Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+static const MCRegisterClass LoongArchMCRegisterClasses[] = {
+  { FPR32, FPR32Bits, sizeof(FPR32Bits) },
+  { GPR, GPRBits, sizeof(GPRBits) },
+  { GPRT, GPRTBits, sizeof(GPRTBits) },
+  { CFR, CFRBits, sizeof(CFRBits) },
+  { FCSR, FCSRBits, sizeof(FCSRBits) },
+  { SCR, SCRBits, sizeof(SCRBits) },
+  { FPR64, FPR64Bits, sizeof(FPR64Bits) },
+  { LSX128, LSX128Bits, sizeof(LSX128Bits) },
+  { LASX256, LASX256Bits, sizeof(LASX256Bits) },
+};
+
+static const uint16_t LoongArchRegEncodingTable[] = {
+  0,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  24,
+  25,
+  26,
+  27,
+  28,
+  29,
+  30,
+  31,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  0,
+  1,
+  2,
+  3,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  24,
+  25,
+  26,
+  27,
+  28,
+  29,
+  30,
+  31,
+  0,
+  1,
+  2,
+  3,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  24,
+  25,
+  26,
+  27,
+  28,
+  29,
+  30,
+  31,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  24,
+  25,
+  26,
+  27,
+  28,
+  29,
+  30,
+  31,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  24,
+  25,
+  26,
+  27,
+  28,
+  29,
+  30,
+  31,
+};
+#endif // GET_REGINFO_MC_DESC
+
+
+
--- a/arch/LoongArch/LoongArchGenSubtargetInfo.inc
+++ b/arch/LoongArch/LoongArchGenSubtargetInfo.inc
@ -0,0 +1,38 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  LoongArch_Feature32Bit = 0,
+  LoongArch_Feature64Bit = 1,
+  LoongArch_FeatureAutoVec = 2,
+  LoongArch_FeatureBasicD = 3,
+  LoongArch_FeatureBasicF = 4,
+  LoongArch_FeatureExtLASX = 5,
+  LoongArch_FeatureExtLBT = 6,
+  LoongArch_FeatureExtLSX = 7,
+  LoongArch_FeatureExtLVZ = 8,
+  LoongArch_FeatureFrecipe = 9,
+  LoongArch_FeatureRelax = 10,
+  LoongArch_FeatureUAL = 11,
+  LoongArch_LaGlobalWithAbs = 12,
+  LoongArch_LaGlobalWithPcrel = 13,
+  LoongArch_LaLocalWithAbs = 14,
+  LoongArch_NumSubtargetFeatures = 15
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+
--- a/arch/LoongArch/LoongArchInstPrinter.c
+++ b/arch/LoongArch/LoongArchInstPrinter.c
@ -0,0 +1,102 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- LoongArchInstPrinter.cpp - Convert LoongArch MCInst to asm syntax --===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an LoongArch MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "LoongArchMapping.h"
+#include "LoongArchInstPrinter.h"
+
+#define GET_SUBTARGETINFO_ENUM
+#include "LoongArchGenSubtargetInfo.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "LoongArchGenInstrInfo.inc"
+
+#define GET_REGINFO_ENUM
+#include "LoongArchGenRegisterInfo.inc"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define DEBUG_TYPE "loongarch-asm-printer"
+
+// Include the auto-generated portion of the assembly writer.
+#define PRINT_ALIAS_INSTR
+#include "LoongArchGenAsmWriter.inc"
+
+static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
+		      SStream *O)
+{
+	if (!printAliasInstr(MI, Address, O))
+		printInstruction(MI, Address, O);
+	;
+}
+
+void LoongArch_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
+			      SStream *O)
+{
+	printInst(MI, Address, Annot, O);
+}
+
+const char *LoongArch_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx)
+{
+	return getRegisterName(RegNo, AltIdx);
+}
+
+static void printRegName(SStream *O, MCRegister Reg)
+{
+	SStream_concat1(O, '$');
+	SStream_concat0(O, getRegisterName(Reg, LoongArch_RegAliasName));
+}
+
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, LOONGARCH_OP_GROUP_OPERAND, OpNo);
+	MCOperand *MO = MCInst_getOperand(MI, (OpNo));
+
+	if (MCOperand_isReg(MO)) {
+		printRegName(O, MCOperand_getReg(MO));
+		return;
+	}
+
+	if (MCOperand_isImm(MO)) {
+		printInt64(O, MCOperand_getImm(MO));
+		return;
+	}
+
+	assert(0 && "Expressions are not supported.");
+}
+
+static void printAtomicMemOp(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, LOONGARCH_OP_GROUP_ATOMICMEMOP, OpNo);
+	MCOperand *MO = MCInst_getOperand(MI, (OpNo));
+
+	printRegName(O, MCOperand_getReg(MO));
+}
--- a/arch/LoongArch/LoongArchInstPrinter.h
+++ b/arch/LoongArch/LoongArchInstPrinter.h
@ -0,0 +1,54 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- LoongArchInstPrinter.h - Convert LoongArch MCInst to asm syntax ---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints a LoongArch MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHINSTPRINTER_H
+#define LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHINSTPRINTER_H
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../MCInstPrinter.h"
+#include "../../cs_priv.h"
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
+		      SStream *O);
+static void printRegName(SStream *O, MCRegister Reg);
+static void printAtomicMemOp(MCInst *MI, unsigned OpNo, SStream *O);
+// Autogenerated by tblgen.
+static void printInstruction(MCInst *MI, uint64_t Address, SStream *O);
+static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *O);
+static void printCustomAliasOperand(MCInst *MI, uint64_t Address,
+				    unsigned OpIdx, unsigned PrintMethodIdx,
+				    SStream *O);
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
+;
+// end namespace llvm
+
+#endif // LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHINSTPRINTER_H
--- a/arch/LoongArch/LoongArchLinkage.h
+++ b/arch/LoongArch/LoongArchLinkage.h
@ -0,0 +1,24 @@
+/* Capstone Disassembly Engine */
+/* By Jiajie Chen <c@jia.je>, 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#ifndef CS_LOONGARCH_LINKAGE_H
+#define CS_LOONGARCH_LINKAGE_H
+
+// Function definitions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "capstone/capstone.h"
+
+const char *LoongArch_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
+void LoongArch_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
+			      SStream *O);
+DecodeStatus LoongArch_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
+					   const uint8_t *Bytes,
+					   size_t BytesLen, uint64_t Address,
+					   SStream *CS);
+
+#endif // CS_LOONGARCH_LINKAGE_H
--- a/arch/LoongArch/LoongArchMapping.c
+++ b/arch/LoongArch/LoongArchMapping.c
@ -0,0 +1,499 @@
+/* Capstone Disassembly Engine */
+/* By Jiajie Chen <c@jia.je>, 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#ifdef CAPSTONE_HAS_LOONGARCH
+
+#include <stdio.h>
+#include <string.h>
+
+#include <capstone/capstone.h>
+#include <capstone/loongarch.h>
+
+#include "../../Mapping.h"
+#include "../../MCDisassembler.h"
+#include "../../cs_priv.h"
+#include "../../cs_simple_types.h"
+
+#include "LoongArchMapping.h"
+#include "LoongArchLinkage.h"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "LoongArchGenRegisterInfo.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "LoongArchGenInstrInfo.inc"
+
+void LoongArch_init_mri(MCRegisterInfo *MRI)
+{
+	MCRegisterInfo_InitMCRegisterInfo(MRI, LoongArchRegDesc,
+					  sizeof(LoongArchRegDesc), 0, 0,
+					  LoongArchMCRegisterClasses,
+					  ARR_SIZE(LoongArchMCRegisterClasses),
+					  0, 0, LoongArchRegDiffLists, 0,
+					  LoongArchSubRegIdxLists,
+					  ARR_SIZE(LoongArchSubRegIdxLists), 0);
+}
+
+const char *LoongArch_reg_name(csh handle, unsigned int reg)
+{
+	int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;
+
+	if (syntax_opt & CS_OPT_SYNTAX_NOREGNAME) {
+		return LoongArch_LLVM_getRegisterName(reg,
+						      LoongArch_NoRegAltName);
+	}
+	return LoongArch_LLVM_getRegisterName(reg, LoongArch_RegAliasName);
+}
+
+void LoongArch_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	// Not used by LoongArch. Information is set after disassembly.
+}
+
+static const char *const insn_name_maps[] = {
+#include "LoongArchGenCSMappingInsnName.inc"
+};
+
+const char *LoongArch_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id < ARR_SIZE(insn_name_maps))
+		return insn_name_maps[id];
+	// not found
+	return NULL;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	{ LOONGARCH_GRP_INVALID, NULL },
+
+	{ LOONGARCH_GRP_JUMP, "jump" },
+	{ LOONGARCH_GRP_CALL, "call" },
+	{ LOONGARCH_GRP_RET, "return" },
+	{ LOONGARCH_GRP_INT, "int" },
+	{ LOONGARCH_GRP_IRET, "iret" },
+	{ LOONGARCH_GRP_PRIVILEGE, "privilege" },
+	{ LOONGARCH_GRP_BRANCH_RELATIVE, "branch_relative" },
+
+// architecture-specific groups
+#include "LoongArchGenCSFeatureName.inc"
+};
+#endif
+
+const char *LoongArch_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+void LoongArch_reg_access(const cs_insn *insn, cs_regs regs_read,
+			  uint8_t *regs_read_count, cs_regs regs_write,
+			  uint8_t *regs_write_count)
+{
+	uint8_t i;
+	uint8_t read_count, write_count;
+	cs_loongarch *loongarch = &(insn->detail->loongarch);
+
+	read_count = insn->detail->regs_read_count;
+	write_count = insn->detail->regs_write_count;
+
+	// implicit registers
+	memcpy(regs_read, insn->detail->regs_read,
+	       read_count * sizeof(insn->detail->regs_read[0]));
+	memcpy(regs_write, insn->detail->regs_write,
+	       write_count * sizeof(insn->detail->regs_write[0]));
+
+	// explicit registers
+	for (i = 0; i < loongarch->op_count; i++) {
+		cs_loongarch_op *op = &(loongarch->operands[i]);
+		switch ((int)op->type) {
+		case LOONGARCH_OP_REG:
+			if ((op->access & CS_AC_READ) &&
+			    !arr_exist(regs_read, read_count, op->reg)) {
+				regs_read[read_count] = (uint16_t)op->reg;
+				read_count++;
+			}
+			if ((op->access & CS_AC_WRITE) &&
+			    !arr_exist(regs_write, write_count, op->reg)) {
+				regs_write[write_count] = (uint16_t)op->reg;
+				write_count++;
+			}
+			break;
+		case LOONGARCH_OP_MEM:
+			// registers appeared in memory references always being read
+			if ((op->mem.base != LOONGARCH_REG_INVALID) &&
+			    !arr_exist(regs_read, read_count, op->mem.base)) {
+				regs_read[read_count] = (uint16_t)op->mem.base;
+				read_count++;
+			}
+			if ((insn->detail->writeback) &&
+			    (op->mem.base != LOONGARCH_REG_INVALID) &&
+			    !arr_exist(regs_write, write_count, op->mem.base)) {
+				regs_write[write_count] =
+					(uint16_t)op->mem.base;
+				write_count++;
+			}
+		default:
+			break;
+		}
+	}
+
+	*regs_read_count = read_count;
+	*regs_write_count = write_count;
+}
+
+const insn_map loongarch_insns[] = {
+#include "LoongArchGenCSMappingInsn.inc"
+};
+
+void LoongArch_rewrite_memory_operand(MCInst *MI)
+{
+	// rewrite base + disp operands to memory operands in memory instructions
+	// convert e.g.
+	// ld.d   $t3, $t2, 0x410
+	// op_count: 3
+	//         operands[0].type: REG = t3
+	//         operands[0].access: WRITE
+	//         operands[1].type: REG = t2
+	//         operands[1].access: READ
+	//         operands[2].type: IMM = 0x410
+	//         operands[2].access: READ
+	// to:
+	// op_count: 3
+	//         operands[0].type: REG = t3
+	//         operands[0].access: WRITE
+	//         operands[1].type: MEM
+	//                 operands[1].mem.base: REG = t2
+	//                 operands[1].mem.disp: 0x410
+	//        operands[1].access: READ
+
+	if (!detail_is_set(MI))
+		return;
+
+	const loongarch_suppl_info *suppl_info =
+		map_get_suppl_info(MI, loongarch_insns);
+	if (suppl_info->memory_access == CS_AC_INVALID) {
+		// not memory instruction
+		return;
+	}
+
+	// handle special cases
+	unsigned int base;
+	switch (MI->flat_insn->id) {
+	case LOONGARCH_INS_SC_Q:
+	case LOONGARCH_INS_LLACQ_W:
+	case LOONGARCH_INS_LLACQ_D:
+	case LOONGARCH_INS_SCREL_W:
+	case LOONGARCH_INS_SCREL_D:
+		// last register rj is memory operand
+		LoongArch_get_detail_op(MI, -1)->type = LOONGARCH_OP_MEM;
+		base = LoongArch_get_detail_op(MI, -1)->reg;
+		LoongArch_get_detail_op(MI, -1)->mem.base = base;
+		LoongArch_get_detail_op(MI, -1)->access =
+			suppl_info->memory_access;
+		return;
+
+	case LOONGARCH_INS_LDGT_B:
+	case LOONGARCH_INS_LDGT_H:
+	case LOONGARCH_INS_LDGT_W:
+	case LOONGARCH_INS_LDGT_D:
+	case LOONGARCH_INS_LDLE_B:
+	case LOONGARCH_INS_LDLE_H:
+	case LOONGARCH_INS_LDLE_W:
+	case LOONGARCH_INS_LDLE_D:
+	case LOONGARCH_INS_STGT_B:
+	case LOONGARCH_INS_STGT_H:
+	case LOONGARCH_INS_STGT_W:
+	case LOONGARCH_INS_STGT_D:
+	case LOONGARCH_INS_STLE_B:
+	case LOONGARCH_INS_STLE_H:
+	case LOONGARCH_INS_STLE_W:
+	case LOONGARCH_INS_STLE_D:
+	case LOONGARCH_INS_FLDLE_S:
+	case LOONGARCH_INS_FLDLE_D:
+	case LOONGARCH_INS_FLDGT_S:
+	case LOONGARCH_INS_FLDGT_D:
+	case LOONGARCH_INS_FSTLE_S:
+	case LOONGARCH_INS_FSTLE_D:
+	case LOONGARCH_INS_FSTGT_S:
+	case LOONGARCH_INS_FSTGT_D:
+		// second register rj is memory operand
+		LoongArch_get_detail_op(MI, -2)->type = LOONGARCH_OP_MEM;
+		base = LoongArch_get_detail_op(MI, -2)->reg;
+		LoongArch_get_detail_op(MI, -2)->mem.base = base;
+		LoongArch_get_detail_op(MI, -2)->access =
+			suppl_info->memory_access;
+		return;
+	default:
+		break;
+	}
+
+	switch (suppl_info->form) {
+	case LOONGARCH_INSN_FORM_FMT2RI12:	 // ld, ldl, ldr, st, stl, str
+	case LOONGARCH_INSN_FORM_FMT2RI14:	 // ll, sc, ldptr, stptr
+	case LOONGARCH_INSN_FORM_FMT2RI9_VRI:	 // vldrepl.d
+	case LOONGARCH_INSN_FORM_FMT2RI10_VRI:	 // vldrepl.w
+	case LOONGARCH_INSN_FORM_FMT2RI11_VRI:	 // vldrepl.h
+	case LOONGARCH_INSN_FORM_FMT2RI12_VRI:	 // vld, vldrepl, vst
+	case LOONGARCH_INSN_FORM_FMT2RI8I1_VRII: // vstelm.d
+	case LOONGARCH_INSN_FORM_FMT2RI8I2_VRII: // vstelm.w
+	case LOONGARCH_INSN_FORM_FMT2RI8I3_VRII: // vstelm.h
+	case LOONGARCH_INSN_FORM_FMT2RI8I4_VRII: // vstelm.b
+	case LOONGARCH_INSN_FORM_FMT2RI9_XRI:	 // xvldrepl.d
+	case LOONGARCH_INSN_FORM_FMT2RI10_XRI:	 // xvldrepl.w
+	case LOONGARCH_INSN_FORM_FMT2RI11_XRI:	 // xvldrepl.h
+	case LOONGARCH_INSN_FORM_FMT2RI12_XRI:	 // xvld, xvldrepl, xvst
+	case LOONGARCH_INSN_FORM_FMT2RI8I2_XRII: // xvstelm.d
+	case LOONGARCH_INSN_FORM_FMT2RI8I3_XRII: // xvstelm.w
+	case LOONGARCH_INSN_FORM_FMT2RI8I4_XRII: // xvstelm.h
+	case LOONGARCH_INSN_FORM_FMT2RI8I5_XRII: // xvstelm.b
+	case LOONGARCH_INSN_FORM_FMTPRELD:	 // preld
+	case LOONGARCH_INSN_FORM_FPFMT2RI12:	 // fld, fst
+		// immediate offset
+		LoongArch_get_detail_op(MI, -2)->type = LOONGARCH_OP_MEM;
+		base = LoongArch_get_detail_op(MI, -2)->reg;
+		LoongArch_get_detail_op(MI, -2)->mem.base = base;
+		LoongArch_get_detail_op(MI, -2)->mem.disp =
+			LoongArch_get_detail_op(MI, -1)->imm;
+		LoongArch_get_detail_op(MI, -2)->access =
+			suppl_info->memory_access;
+		LoongArch_dec_op_count(MI);
+		break;
+
+	case LOONGARCH_INSN_FORM_FMT3R: // ldx, stx, amo
+		if (suppl_info->memory_access == CS_AC_READ_WRITE) {
+			// amo: read + write
+			// last register rj is memory operand
+			LoongArch_get_detail_op(MI, -1)->type =
+				LOONGARCH_OP_MEM;
+			base = LoongArch_get_detail_op(MI, -1)->reg;
+			LoongArch_get_detail_op(MI, -1)->mem.base = base;
+			LoongArch_get_detail_op(MI, -1)->access =
+				suppl_info->memory_access;
+			break;
+		}
+		// fallthrough
+
+	case LOONGARCH_INSN_FORM_FPFMTMEM:  // fldx, fstx
+	case LOONGARCH_INSN_FORM_FMT3R_VRR: // vldx, vstx
+	case LOONGARCH_INSN_FORM_FMT3R_XRR: // xvldx, xvstx
+	case LOONGARCH_INSN_FORM_FMTPRELDX: // preldx
+		// register offset
+		LoongArch_get_detail_op(MI, -2)->type = LOONGARCH_OP_MEM;
+		base = LoongArch_get_detail_op(MI, -2)->reg;
+		LoongArch_get_detail_op(MI, -2)->mem.base = base;
+		LoongArch_get_detail_op(MI, -2)->mem.index =
+			LoongArch_get_detail_op(MI, -1)->reg;
+		LoongArch_get_detail_op(MI, -2)->access =
+			suppl_info->memory_access;
+		LoongArch_dec_op_count(MI);
+		break;
+
+	default:
+		assert(0 && "Unknown LoongArch memory instruction");
+		break;
+	}
+}
+
+void LoongArch_set_instr_map_data(MCInst *MI)
+{
+	map_cs_id(MI, loongarch_insns, ARR_SIZE(loongarch_insns));
+	map_implicit_reads(MI, loongarch_insns);
+	map_implicit_writes(MI, loongarch_insns);
+	map_groups(MI, loongarch_insns);
+	const loongarch_suppl_info *suppl_info =
+		map_get_suppl_info(MI, loongarch_insns);
+	if (suppl_info) {
+		LoongArch_get_detail(MI)->format = suppl_info->form;
+	}
+}
+
+bool LoongArch_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			      MCInst *instr, uint16_t *size, uint64_t address,
+			      void *info)
+{
+	uint64_t temp_size;
+	LoongArch_init_cs_detail(instr);
+	bool Result = LoongArch_LLVM_getInstruction(instr, &temp_size, code,
+						    code_len, address, info) !=
+		      MCDisassembler_Fail;
+	LoongArch_set_instr_map_data(instr);
+	*size = temp_size;
+	return Result;
+}
+
+/// Adds group to the instruction which are not defined in LLVM.
+static void LoongArch_add_cs_groups(MCInst *MI)
+{
+	if (!MI->flat_insn->detail)
+		return;
+	unsigned Opcode = MI->flat_insn->id;
+	cs_loongarch *loongarch = &(MI->flat_insn->detail->loongarch);
+	switch (Opcode) {
+	default:
+		return;
+	case LOONGARCH_INS_BL:
+		add_group(MI, LOONGARCH_GRP_CALL);
+		break;
+	case LOONGARCH_INS_JIRL:
+		if (loongarch->op_count == 3 &&
+		    loongarch->operands[0].reg == LOONGARCH_REG_RA) {
+			// call: jirl ra, rj, offs16
+			add_group(MI, LOONGARCH_GRP_CALL);
+		} else if (loongarch->op_count == 0) {
+			// ret
+			add_group(MI, LOONGARCH_GRP_RET);
+		} else if (loongarch->op_count == 1) {
+			// jr rj
+			add_group(MI, LOONGARCH_GRP_JUMP);
+		}
+		break;
+	case LOONGARCH_INS_B:
+	case LOONGARCH_INS_BCEQZ:
+	case LOONGARCH_INS_BEQ:
+	case LOONGARCH_INS_BEQZ:
+	case LOONGARCH_INS_BGE:
+	case LOONGARCH_INS_BGEU:
+	case LOONGARCH_INS_BLT:
+	case LOONGARCH_INS_BLTU:
+	case LOONGARCH_INS_BNE:
+	case LOONGARCH_INS_BNEZ:
+		add_group(MI, LOONGARCH_GRP_JUMP);
+		add_group(MI, LOONGARCH_GRP_BRANCH_RELATIVE);
+		break;
+	case LOONGARCH_INS_SYSCALL:
+		add_group(MI, LOONGARCH_GRP_INT);
+		break;
+	case LOONGARCH_INS_ERTN:
+		add_group(MI, LOONGARCH_GRP_IRET);
+		add_group(MI, LOONGARCH_GRP_PRIVILEGE);
+		break;
+	case LOONGARCH_INS_CSRXCHG:
+	case LOONGARCH_INS_CACOP:
+	case LOONGARCH_INS_LDDIR:
+	case LOONGARCH_INS_LDPTE:
+	case LOONGARCH_INS_IOCSRRD_B:
+	case LOONGARCH_INS_IOCSRRD_H:
+	case LOONGARCH_INS_IOCSRRD_W:
+	case LOONGARCH_INS_IOCSRRD_D:
+	case LOONGARCH_INS_IOCSRWR_B:
+	case LOONGARCH_INS_IOCSRWR_H:
+	case LOONGARCH_INS_IOCSRWR_W:
+	case LOONGARCH_INS_IOCSRWR_D:
+	case LOONGARCH_INS_TLBCLR:
+	case LOONGARCH_INS_TLBFLUSH:
+	case LOONGARCH_INS_TLBSRCH:
+	case LOONGARCH_INS_TLBRD:
+	case LOONGARCH_INS_TLBWR:
+	case LOONGARCH_INS_INVTLB:
+		add_group(MI, LOONGARCH_GRP_PRIVILEGE);
+		break;
+	}
+}
+
+void LoongArch_printer(MCInst *MI, SStream *O,
+		       void * /* MCRegisterInfo* */ info)
+{
+	MCRegisterInfo *MRI = (MCRegisterInfo *)info;
+	MI->MRI = MRI;
+
+	LoongArch_LLVM_printInst(MI, MI->address, "", O);
+
+	LoongArch_rewrite_memory_operand(MI);
+	LoongArch_add_cs_groups(MI);
+}
+
+void LoongArch_setup_op(cs_loongarch_op *op)
+{
+	memset(op, 0, sizeof(cs_loongarch_op));
+	op->type = LOONGARCH_OP_INVALID;
+}
+
+void LoongArch_init_cs_detail(MCInst *MI)
+{
+	if (detail_is_set(MI)) {
+		unsigned int i;
+
+		memset(get_detail(MI), 0,
+		       offsetof(cs_detail, loongarch) + sizeof(cs_loongarch));
+
+		for (i = 0; i < ARR_SIZE(LoongArch_get_detail(MI)->operands);
+		     i++)
+			LoongArch_setup_op(
+				&LoongArch_get_detail(MI)->operands[i]);
+	}
+}
+
+static const map_insn_ops insn_operands[] = {
+#include "LoongArchGenCSMappingInsnOp.inc"
+};
+
+void LoongArch_set_detail_op_imm(MCInst *MI, unsigned OpNum,
+				 loongarch_op_type ImmType, int64_t Imm)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM);
+	assert(ImmType == LOONGARCH_OP_IMM);
+
+	LoongArch_get_detail_op(MI, 0)->type = ImmType;
+	LoongArch_get_detail_op(MI, 0)->imm = Imm;
+	LoongArch_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	LoongArch_inc_op_count(MI);
+}
+
+void LoongArch_set_detail_op_reg(MCInst *MI, unsigned OpNum, loongarch_reg Reg)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
+
+	LoongArch_get_detail_op(MI, 0)->type = LOONGARCH_OP_REG;
+	LoongArch_get_detail_op(MI, 0)->reg = Reg;
+	LoongArch_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	LoongArch_inc_op_count(MI);
+}
+
+void LoongArch_add_cs_detail(MCInst *MI, int /* loongarch_op_group */ op_group,
+			     va_list args)
+{
+	if (!detail_is_set(MI))
+		return;
+
+	unsigned OpNum = va_arg(args, unsigned);
+	// Handle memory operands later
+	cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
+
+	// Fill cs_detail
+	switch (op_group) {
+	default:
+		printf("ERROR: Operand group %d not handled!\n", op_group);
+		assert(0);
+	case LOONGARCH_OP_GROUP_OPERAND:
+		if (op_type == CS_OP_IMM) {
+			LoongArch_set_detail_op_imm(MI, OpNum, LOONGARCH_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum));
+		} else if (op_type == CS_OP_REG) {
+			LoongArch_set_detail_op_reg(MI, OpNum,
+						    MCInst_getOpVal(MI, OpNum));
+		} else
+			assert(0 && "Op type not handled.");
+		break;
+	case LOONGARCH_OP_GROUP_ATOMICMEMOP:
+		assert(op_type == CS_OP_REG);
+		// converted to MEM operand later in LoongArch_rewrite_memory_operand
+		LoongArch_set_detail_op_reg(MI, OpNum,
+					    MCInst_getOpVal(MI, OpNum));
+		break;
+	}
+}
+
+#endif
--- a/arch/LoongArch/LoongArchMapping.h
+++ b/arch/LoongArch/LoongArchMapping.h
@ -0,0 +1,53 @@
+/* Capstone Disassembly Engine */
+/* By Jiajie Chen <c@jia.je>, 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#ifndef CS_LOONGARCH_MAPPING_H
+#define CS_LOONGARCH_MAPPING_H
+
+#include "../../include/capstone/capstone.h"
+#include "../../utils.h"
+
+typedef enum {
+#include "LoongArchGenCSOpGroup.inc"
+} loongarch_op_group;
+
+void LoongArch_init_mri(MCRegisterInfo *MRI);
+
+// return name of register in friendly string
+const char *LoongArch_reg_name(csh handle, unsigned int reg);
+
+void LoongArch_printer(MCInst *MI, SStream *O,
+		       void * /* MCRegisterInfo* */ info);
+
+// given internal insn id, return public instruction ID
+void LoongArch_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *LoongArch_insn_name(csh handle, unsigned int id);
+
+const char *LoongArch_group_name(csh handle, unsigned int id);
+
+void LoongArch_reg_access(const cs_insn *insn, cs_regs regs_read,
+			  uint8_t *regs_read_count, cs_regs regs_write,
+			  uint8_t *regs_write_count);
+
+bool LoongArch_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			      MCInst *instr, uint16_t *size, uint64_t address,
+			      void *info);
+
+// cs_detail related functions
+void LoongArch_init_cs_detail(MCInst *MI);
+void LoongArch_add_cs_detail(MCInst *MI, int /* loongarch_op_group */ op_group,
+			     va_list args);
+static inline void add_cs_detail(MCInst *MI,
+				 int /* loongarch_op_group */ op_group, ...)
+{
+	if (!MI->flat_insn->detail)
+		return;
+	va_list args;
+	va_start(args, op_group);
+	LoongArch_add_cs_detail(MI, op_group, args);
+	va_end(args);
+}
+
+#endif // CS_LOONGARCH_MAPPING_H
--- a/arch/LoongArch/LoongArchModule.c
+++ b/arch/LoongArch/LoongArchModule.c
@ -0,0 +1,53 @@
+/* Capstone Disassembly Engine */
+/* By Jiajie Chen <c@jia.je> 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#ifdef CAPSTONE_HAS_LOONGARCH
+
+#include <capstone/capstone.h>
+
+#include "LoongArchModule.h"
+#include "../../MCRegisterInfo.h"
+#include "../../cs_priv.h"
+#include "LoongArchMapping.h"
+
+cs_err LoongArch_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	LoongArch_init_mri(mri);
+
+	ud->printer = LoongArch_printer;
+	ud->printer_info = mri;
+	ud->reg_name = LoongArch_reg_name;
+	ud->insn_id = LoongArch_get_insn_id;
+	ud->insn_name = LoongArch_insn_name;
+	ud->group_name = LoongArch_group_name;
+	ud->post_printer = NULL;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = LoongArch_reg_access;
+#endif
+
+	ud->disasm = LoongArch_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+cs_err LoongArch_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	switch (type) {
+	case CS_OPT_MODE:
+		handle->mode = (cs_mode)value;
+		break;
+	case CS_OPT_SYNTAX:
+		handle->syntax |= (int)value;
+		break;
+	default:
+		break;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif
--- a/arch/LoongArch/LoongArchModule.h
+++ b/arch/LoongArch/LoongArchModule.h
@ -0,0 +1,13 @@
+/* Capstone Disassembly Engine */
+/* By Jiajie Chen <c@jia.je>, 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#ifndef CS_LoongArch_MODULE_H
+#define CS_LoongArch_MODULE_H
+
+#include "../../utils.h"
+
+cs_err LoongArch_global_init(cs_struct *ud);
+cs_err LoongArch_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif
--- a/cmake.sh
+++ b/cmake.sh
@ -63,6 +63,9 @@ case $1 in
  HPPA)
    ARCH=HPPA
    ;;
+  LOONGARCH)
+    ARCH=LOONGARCH
+    ;;
  *)
    ;;
 esac
--- a/config.mk
+++ b/config.mk
@ -4,7 +4,7 @@
 ################################################################################
 # Specify which archs you want to compile in. By default, we build all archs.

-CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore alpha hppa
+CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore alpha hppa loongarch


 ################################################################################
--- a/cs.c
+++ b/cs.c
@ -72,6 +72,7 @@
 #include "arch/TriCore/TriCoreModule.h"
 #include "arch/Alpha/AlphaModule.h"
 #include "arch/HPPA/HPPAModule.h"
+#include "arch/LoongArch/LoongArchModule.h"

 typedef struct cs_arch_config {
 	// constructor initialization
@ -209,6 +210,12 @@ typedef struct cs_arch_config {
 		ALPHA_option, \
 		~(CS_MODE_LITTLE_ENDIAN | CS_MODE_BIG_ENDIAN), \
 	}
+#define CS_ARCH_CONFIG_LOONGARCH \
+	{ \
+		LoongArch_global_init, \
+		LoongArch_option, \
+		~(CS_MODE_LITTLE_ENDIAN | CS_MODE_LOONGARCH32 | CS_MODE_LOONGARCH64), \
+	}

 #ifdef CAPSTONE_USE_ARCH_REGISTRATION
 static cs_arch_config arch_configs[MAX_ARCH];
@ -320,6 +327,11 @@ static const cs_arch_config arch_configs[MAX_ARCH] = {
 #else
 	{ NULL, NULL, 0 },
 #endif
+#ifdef CAPSTONE_HAS_LOONGARCH
+	CS_ARCH_CONFIG_LOONGARCH,
+#else
+	{ NULL, NULL, 0 },
+#endif
 };

 // bitmask of enabled architectures
@ -384,6 +396,9 @@ static const uint32_t all_arch = 0
 #ifdef CAPSTONE_HAS_HPPA
 	| (1 << CS_ARCH_HPPA)
 #endif
+#ifdef CAPSTONE_HAS_LOONGARCH
+	| (1 << CS_ARCH_LOONGARCH)
+#endif
 ;
 #endif

@ -603,6 +618,14 @@ void CAPSTONE_API cs_arch_register_alpha(void)
 #endif
 }

+CAPSTONE_EXPORT
+void CAPSTONE_API cs_arch_register_loongarch(void)
+{
+#if defined(CAPSTONE_USE_ARCH_REGISTRATION) && defined(CAPSTONE_HAS_LOONGARCH)
+	CS_ARCH_REGISTER(LOONGARCH);
+#endif
+}
+
 CAPSTONE_EXPORT
 bool CAPSTONE_API cs_support(int query)
 {
@ -617,7 +640,8 @@ bool CAPSTONE_API cs_support(int query)
 				    (1 << CS_ARCH_RISCV) | (1 << CS_ARCH_MOS65XX)    |
 				    (1 << CS_ARCH_WASM)  | (1 << CS_ARCH_BPF)        |
 				    (1 << CS_ARCH_SH)    | (1 << CS_ARCH_TRICORE)    |
-					(1 << CS_ARCH_ALPHA) | (1 << CS_ARCH_HPPA));
+				    (1 << CS_ARCH_ALPHA) | (1 << CS_ARCH_HPPA)       |
+				    (1 << CS_ARCH_LOONGARCH));

 	if ((unsigned int)query < CS_ARCH_MAX)
 		return all_arch & (1 << query);
@ -962,6 +986,9 @@ static uint8_t skipdata_size(cs_struct *handle)
 		case CS_ARCH_HPPA:
 			// Hppa alignment is 4.
 			return 4;
+		case CS_ARCH_LOONGARCH:
+			// LoongArch alignment is 4.
+			return 4;
 	}
 }

@ -1711,6 +1738,11 @@ int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type)
 				if (insn->detail->hppa.operands[i].type == (hppa_op_type)op_type)
 					count++;
 			break;
+		case CS_ARCH_LOONGARCH:
+			for (i = 0; i < insn->detail->loongarch.op_count; i++)
+				if (insn->detail->loongarch.operands[i].type == (loongarch_op_type)op_type)
+					count++;
+			break;
 	}

 	return count;
@ -1910,6 +1942,14 @@ int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type,
 					return i;
 			}
 			break;
+		case CS_ARCH_LOONGARCH:
+			for (i = 0; i < insn->detail->loongarch.op_count; i++) {
+				if (insn->detail->loongarch.operands[i].type == (loongarch_op_type)op_type)
+					count++;
+				if (count == post)
+					return i;
+			}
+			break;
 	}

 	return -1;
--- a/cstool/cstool.c
+++ b/cstool/cstool.c
@ -122,6 +122,8 @@ static struct {
 	{ "hppa20be", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_BIG_ENDIAN },
 	{ "hppa20w", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_LITTLE_ENDIAN },
 	{ "hppa20wbe", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_BIG_ENDIAN },
+	{ "loongarch32", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32 },
+	{ "loongarch64", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64 },
 	{ NULL }
 };

@ -342,6 +344,11 @@ static void usage(char *prog)
 		printf("        tc162       tricore V1.6.2\n");
 	}

+	if (cs_support(CS_ARCH_LOONGARCH)) {
+		printf("        loongarch32 LoongArch32\n");
+		printf("        loongarch64 LoongArch64\n");
+	}
+
 	printf("\nExtra options:\n");
 	printf("        -d show detailed information of the instructions\n");
 	printf("        -r show detailed information of the real instructions (even for alias)\n");
@ -420,6 +427,9 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
 		case CS_ARCH_HPPA:
 			print_insn_detail_hppa(handle, ins);
 			break;
+		case CS_ARCH_LOONGARCH:
+			print_insn_detail_loongarch(handle, ins);
+			break;
 		default: break;
 	}

@ -564,6 +574,10 @@ int main(int argc, char **argv)
 					printf("hppa=1 ");
 				}

+				if (cs_support(CS_ARCH_LOONGARCH)) {
+					printf("loongarch=1 ");
+				}
+
 				printf("\n");
 				return 0;
 			case 'h':
--- a/cstool/cstool.h
+++ b/cstool/cstool.h
@ -21,5 +21,6 @@ void print_insn_detail_sh(csh handle, cs_insn *ins);
 void print_insn_detail_tricore(csh handle, cs_insn *ins);
 void print_insn_detail_alpha(csh handle, cs_insn *ins);
 void print_insn_detail_hppa(csh handle, cs_insn *ins);
+void print_insn_detail_loongarch(csh handle, cs_insn *ins);

 #endif //CAPSTONE_CSTOOL_CSTOOL_H_
--- a/cstool/cstool_loongarch.c
+++ b/cstool/cstool_loongarch.c
@ -0,0 +1,91 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/*    Jiajie Chen <c@jia.je>, 2013-2024 */
+
+#include <stdio.h>
+#include <capstone/capstone.h>
+#include "cstool.h"
+
+void print_insn_detail_loongarch(csh handle, cs_insn *ins)
+{
+	cs_loongarch *loongarch;
+	int i;
+	cs_regs regs_read, regs_write;
+	uint8_t regs_read_count, regs_write_count;
+	uint8_t access;
+
+	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
+	if (ins->detail == NULL)
+		return;
+
+	loongarch = &(ins->detail->loongarch);
+	if (loongarch->op_count)
+		printf("\top_count: %u\n", loongarch->op_count);
+
+	for (i = 0; i < loongarch->op_count; i++) {
+		cs_loongarch_op *op = &(loongarch->operands[i]);
+		switch ((int)op->type) {
+		default:
+			break;
+		case LOONGARCH_OP_REG:
+			printf("\t\toperands[%u].type: REG = %s\n", i,
+			       cs_reg_name(handle, op->reg));
+			break;
+		case LOONGARCH_OP_IMM:
+			printf("\t\toperands[%u].type: IMM = 0x%lx\n", i,
+			       (long)op->imm);
+			break;
+		case LOONGARCH_OP_MEM:
+			printf("\t\toperands[%u].type: MEM\n", i);
+			if (op->mem.base != LOONGARCH_REG_INVALID)
+				printf("\t\t\toperands[%u].mem.base: REG = %s\n",
+				       i, cs_reg_name(handle, op->mem.base));
+			if (op->mem.index != LOONGARCH_REG_INVALID)
+				printf("\t\t\toperands[%u].mem.index: REG = %s\n",
+				       i, cs_reg_name(handle, op->mem.index));
+			if (op->mem.disp != 0)
+				printf("\t\t\toperands[%u].mem.disp: 0x%lx\n",
+				       i, (long)op->mem.disp);
+
+			break;
+		}
+
+		access = op->access;
+		switch (access) {
+		default:
+			break;
+		case CS_AC_READ:
+			printf("\t\toperands[%u].access: READ\n", i);
+			break;
+		case CS_AC_WRITE:
+			printf("\t\toperands[%u].access: WRITE\n", i);
+			break;
+		case CS_AC_READ | CS_AC_WRITE:
+			printf("\t\toperands[%u].access: READ | WRITE\n", i);
+			break;
+		}
+	}
+
+	if (ins->detail->writeback)
+		printf("\tWrite-back: True\n");
+
+	/* print all registers that are involved in this instruction */
+	if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
+			    regs_write, &regs_write_count)) {
+		if (regs_read_count) {
+			printf("\tRegisters read:");
+			for (i = 0; i < regs_read_count; i++)
+				printf(" %s",
+				       cs_reg_name(handle, regs_read[i]));
+			printf("\n");
+		}
+
+		if (regs_write_count) {
+			printf("\tRegisters modified:");
+			for (i = 0; i < regs_write_count; i++)
+				printf(" %s",
+				       cs_reg_name(handle, regs_write[i]));
+			printf("\n");
+		}
+	}
+}
--- a/include/capstone/capstone.h
+++ b/include/capstone/capstone.h
@ -158,6 +158,7 @@ typedef enum cs_arch {
 	CS_ARCH_TRICORE,	///< TriCore architecture
 	CS_ARCH_ALPHA, 		///< Alpha architecture
 	CS_ARCH_HPPA, 		///< HPPA architecture
+	CS_ARCH_LOONGARCH, 	///< LoongArch architecture
 	CS_ARCH_MAX,
 	CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
 } cs_arch;
@ -240,6 +241,8 @@ typedef enum cs_mode {
 	CS_MODE_HPPA_11 = 1 << 1, ///< HPPA 1.1
 	CS_MODE_HPPA_20 = 1 << 2, ///< HPPA 2.0
 	CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3), ///< HPPA 2.0 wide
+	CS_MODE_LOONGARCH32  = 1 << 0,        ///< LoongArch32
+	CS_MODE_LOONGARCH64  = 1 << 1,        ///< LoongArch64
 } cs_mode;

 typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size);
@ -341,21 +344,22 @@ typedef struct cs_opt_skipdata {
 	/// immediately from cs_disasm()
 	/// NOTE: if this callback pointer is NULL, Capstone would skip a number
 	/// of bytes depending on architectures, as following:
-	/// Arm:     2 bytes (Thumb mode) or 4 bytes.
-	/// AArch64: 4 bytes.
-	/// Mips:    4 bytes.
-	/// M680x:   1 byte.
-	/// PowerPC: 4 bytes.
-	/// Sparc:   4 bytes.
-	/// SystemZ: 2 bytes.
-	/// X86:     1 bytes.
-	/// XCore:   2 bytes.
-	/// EVM:     1 bytes.
-	/// RISCV:   4 bytes.
-	/// WASM:    1 bytes.
-	/// MOS65XX: 1 bytes.
-	/// BPF:     8 bytes.
-	/// TriCore: 2 bytes.
+	/// Arm:       2 bytes (Thumb mode) or 4 bytes.
+	/// AArch64:   4 bytes.
+	/// Mips:      4 bytes.
+	/// M680x:     1 byte.
+	/// PowerPC:   4 bytes.
+	/// Sparc:     4 bytes.
+	/// SystemZ:   2 bytes.
+	/// X86:       1 bytes.
+	/// XCore:     2 bytes.
+	/// EVM:       1 bytes.
+	/// RISCV:     4 bytes.
+	/// WASM:      1 bytes.
+	/// MOS65XX:   1 bytes.
+	/// BPF:       8 bytes.
+	/// TriCore:   2 bytes.
+	/// LoongArch: 4 bytes.
 	cs_skipdata_cb_t callback; 	// default value is NULL

 	/// User-defined data to be passed to @callback function pointer.
@ -387,6 +391,7 @@ typedef struct cs_opt_skipdata {
 #include "tricore.h"
 #include "alpha.h"
 #include "hppa.h"
+#include "loongarch.h"

 #define MAX_IMPL_W_REGS 47
 #define MAX_IMPL_R_REGS 20
@ -437,6 +442,7 @@ typedef struct cs_detail {
 		cs_tricore tricore; ///< TriCore architecture
 		cs_alpha alpha; ///< Alpha architecture
 		cs_hppa hppa; ///< HPPA architecture
+		cs_loongarch loongarch; ///< LoongArch architecture
 	};
 } cs_detail;

@ -583,6 +589,8 @@ CAPSTONE_EXPORT
 void CAPSTONE_API cs_arch_register_tricore(void);
 CAPSTONE_EXPORT
 void CAPSTONE_API cs_arch_register_alpha(void);
+CAPSTONE_EXPORT
+void CAPSTONE_API cs_arch_register_loongarch(void);

 /**
 This API can be used to either ask for archs supported by this library,
--- a/include/capstone/loongarch.h
+++ b/include/capstone/loongarch.h
--- a/nmake.bat
+++ b/nmake.bat
@ -24,6 +24,7 @@ if "%1"=="BPF" set %arch%=BPF
 if "%1"=="RISCV" set %arch%=RISCV
 if "%1"=="ALPHA" set %arch%=ALPHA
 if "%1"=="HPPA" set %arch%=HPPA
+if "%1"=="LOONGARCH" set %arch%=LOONGARCH

 if not "%arch%"=="" set flags=%flags% and " -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF -DCAPSTONE_%arch%_SUPPORT=ON"

--- a/suite/MC/LoongArch/absd.s.cs
+++ b/suite/MC/LoongArch/absd.s.cs
@ -0,0 +1,9 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x36,0x44,0x60,0x74 = xvabsd.b $xr22, $xr1, $xr17
+0x11,0xa7,0x60,0x74 = xvabsd.h $xr17, $xr24, $xr9
+0x3c,0x75,0x61,0x74 = xvabsd.w $xr28, $xr9, $xr29
+0xfe,0xce,0x61,0x74 = xvabsd.d $xr30, $xr23, $xr19
+0x90,0x3c,0x62,0x74 = xvabsd.bu $xr16, $xr4, $xr15
+0xed,0xee,0x62,0x74 = xvabsd.hu $xr13, $xr23, $xr27
+0x5f,0x3e,0x63,0x74 = xvabsd.wu $xr31, $xr18, $xr15
+0x5a,0x91,0x63,0x74 = xvabsd.du $xr26, $xr10, $xr4
--- a/suite/MC/LoongArch/add.s.cs
+++ b/suite/MC/LoongArch/add.s.cs
@ -0,0 +1,6 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x74,0x16,0x0a,0x74 = xvadd.b $xr20, $xr19, $xr5
+0xf8,0xb8,0x0a,0x74 = xvadd.h $xr24, $xr7, $xr14
+0x33,0x54,0x0b,0x74 = xvadd.w $xr19, $xr1, $xr21
+0xd3,0xb4,0x0b,0x74 = xvadd.d $xr19, $xr6, $xr13
+0x84,0x1b,0x2d,0x75 = xvadd.q $xr4, $xr28, $xr6
--- a/suite/MC/LoongArch/adda.s.cs
+++ b/suite/MC/LoongArch/adda.s.cs
@ -0,0 +1,5 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x0a,0x6f,0x5c,0x74 = xvadda.b $xr10, $xr24, $xr27
+0x80,0xf7,0x5c,0x74 = xvadda.h $xr0, $xr28, $xr29
+0x3f,0x25,0x5d,0x74 = xvadda.w $xr31, $xr9, $xr9
+0x2a,0xe4,0x5d,0x74 = xvadda.d $xr10, $xr1, $xr25
--- a/suite/MC/LoongArch/addi.s.cs
+++ b/suite/MC/LoongArch/addi.s.cs
@ -0,0 +1,5 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xc1,0x0a,0x8a,0x76 = xvaddi.bu $xr1, $xr22, 2
+0x43,0xf5,0x8a,0x76 = xvaddi.hu $xr3, $xr10, 0x1d
+0x65,0x0d,0x8b,0x76 = xvaddi.wu $xr5, $xr11, 3
+0x06,0x9c,0x8b,0x76 = xvaddi.du $xr6, $xr0, 7
--- a/suite/MC/LoongArch/addw.s.cs
+++ b/suite/MC/LoongArch/addw.s.cs
@ -0,0 +1,25 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xd7,0x13,0x1e,0x74 = xvaddwev.h.b $xr23, $xr30, $xr4
+0x74,0xfe,0x1e,0x74 = xvaddwev.w.h $xr20, $xr19, $xr31
+0x28,0x65,0x1f,0x74 = xvaddwev.d.w $xr8, $xr9, $xr25
+0xdd,0xf6,0x1f,0x74 = xvaddwev.q.d $xr29, $xr22, $xr29
+0xbe,0x69,0x2e,0x74 = xvaddwev.h.bu $xr30, $xr13, $xr26
+0xef,0xc3,0x2e,0x74 = xvaddwev.w.hu $xr15, $xr31, $xr16
+0x10,0x52,0x2f,0x74 = xvaddwev.d.wu $xr16, $xr16, $xr20
+0x4a,0xca,0x2f,0x74 = xvaddwev.q.du $xr10, $xr18, $xr18
+0xe3,0x24,0x3e,0x74 = xvaddwev.h.bu.b $xr3, $xr7, $xr9
+0x1a,0xee,0x3e,0x74 = xvaddwev.w.hu.h $xr26, $xr16, $xr27
+0xa0,0x21,0x3f,0x74 = xvaddwev.d.wu.w $xr0, $xr13, $xr8
+0x53,0x8d,0x3f,0x74 = xvaddwev.q.du.d $xr19, $xr10, $xr3
+0xae,0x62,0x22,0x74 = xvaddwod.h.b $xr14, $xr21, $xr24
+0x53,0xdf,0x22,0x74 = xvaddwod.w.h $xr19, $xr26, $xr23
+0x2c,0x51,0x23,0x74 = xvaddwod.d.w $xr12, $xr9, $xr20
+0x4b,0xa0,0x23,0x74 = xvaddwod.q.d $xr11, $xr2, $xr8
+0xc6,0x24,0x32,0x74 = xvaddwod.h.bu $xr6, $xr6, $xr9
+0x61,0xe7,0x32,0x74 = xvaddwod.w.hu $xr1, $xr27, $xr25
+0x7a,0x2e,0x33,0x74 = xvaddwod.d.wu $xr26, $xr19, $xr11
+0xd5,0xa2,0x33,0x74 = xvaddwod.q.du $xr21, $xr22, $xr8
+0x55,0x63,0x40,0x74 = xvaddwod.h.bu.b $xr21, $xr26, $xr24
+0xdf,0xc0,0x40,0x74 = xvaddwod.w.hu.h $xr31, $xr6, $xr16
+0x8c,0x7f,0x41,0x74 = xvaddwod.d.wu.w $xr12, $xr28, $xr31
+0x9d,0xb0,0x41,0x74 = xvaddwod.q.du.d $xr29, $xr4, $xr12
--- a/suite/MC/LoongArch/and.s.cs
+++ b/suite/MC/LoongArch/and.s.cs
@ -0,0 +1,2 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xee,0x4e,0x26,0x75 = xvand.v $xr14, $xr23, $xr19
--- a/suite/MC/LoongArch/andi.s.cs
+++ b/suite/MC/LoongArch/andi.s.cs
@ -0,0 +1,2 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xeb,0x08,0xd1,0x77 = xvandi.b $xr11, $xr7, 0x42
--- a/suite/MC/LoongArch/andn.s.cs
+++ b/suite/MC/LoongArch/andn.s.cs
@ -0,0 +1,2 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xe3,0x0d,0x28,0x75 = xvandn.v $xr3, $xr15, $xr3
--- a/suite/MC/LoongArch/arith.s.cs
+++ b/suite/MC/LoongArch/arith.s.cs
@ -0,0 +1,30 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x29,0x7c,0x10,0x00 = add.w $a5, $ra, $s8
+0x35,0x4f,0x11,0x00 = sub.w $r21, $s2, $t7
+0xe5,0xd8,0x83,0x02 = addi.w $a1, $a3, 0xf6
+0x22,0x8a,0x05,0x00 = alsl.w $tp, $t5, $tp, 4
+0x30,0x06,0x00,0x14 = lu12i.w $t4, 0x31
+0xe4,0xff,0xff,0x15 = lu12i.w $a0, -1
+0x5d,0x0b,0x12,0x00 = slt $s6, $s3, $tp
+0xab,0xf6,0x12,0x00 = sltu $a7, $r21, $s6
+0x3b,0xac,0x03,0x02 = slti $s4, $ra, 0xeb
+0x00,0x89,0x42,0x02 = sltui $zero, $a4, 0xa2
+0x69,0x17,0x00,0x18 = pcaddi $a5, 0xbb
+0xa0,0x04,0x00,0x1c = pcaddu12i $zero, 0x25
+0x2a,0x0b,0x00,0x1a = pcalau12i $a6, 0x59
+0xf3,0x87,0x14,0x00 = and $t7, $s8, $ra
+0x11,0x7a,0x15,0x00 = or $t5, $t4, $s7
+0x45,0x16,0x14,0x00 = nor $a1, $t6, $a1
+0x6f,0xa2,0x15,0x00 = xor $t3, $t7, $a4
+0x3c,0x97,0x16,0x00 = andn $s5, $s2, $a1
+0x62,0x64,0x16,0x00 = orn $tp, $sp, $s2
+0x19,0xa8,0x41,0x03 = andi $s2, $zero, 0x6a
+0xb1,0xbc,0x80,0x03 = ori $t5, $a1, 0x2f
+0xf2,0x8e,0xc1,0x03 = xori $t6, $s0, 0x63
+0x44,0x0e,0x1c,0x00 = mul.w $a0, $t6, $sp
+0xfb,0x82,0x1c,0x00 = mulh.w $s4, $s0, $zero
+0x2a,0x62,0x1d,0x00 = mulh.wu $a6, $t5, $s1
+0xbe,0x65,0x20,0x00 = div.w $s7, $t1, $s2
+0x41,0xab,0x20,0x00 = mod.w $ra, $s3, $a6
+0xf3,0x02,0x21,0x00 = div.wu $t7, $s0, $zero
+0x3b,0xc5,0x21,0x00 = mod.wu $s4, $a5, $t5
--- a/suite/MC/LoongArch/arm-alu.s.cs
+++ b/suite/MC/LoongArch/arm-alu.s.cs
@ -0,0 +1,9 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x91,0x14,0x37,0x00 = armadd.w $a0, $a1, 1
+0x91,0x94,0x37,0x00 = armsub.w $a0, $a1, 1
+0x91,0x14,0x38,0x00 = armadc.w $a0, $a1, 1
+0x91,0x94,0x38,0x00 = armsbc.w $a0, $a1, 1
+0x91,0x14,0x39,0x00 = armand.w $a0, $a1, 1
+0x91,0x94,0x39,0x00 = armor.w $a0, $a1, 1
+0x91,0x14,0x3a,0x00 = armxor.w $a0, $a1, 1
+0x9c,0xc4,0x3f,0x00 = armnot.w $a0, 1
--- a/suite/MC/LoongArch/arm-jump.s.cs
+++ b/suite/MC/LoongArch/arm-jump.s.cs
@ -0,0 +1,2 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x04,0xc4,0x36,0x00 = setarmj $a0, 1
--- a/suite/MC/LoongArch/arm-mov.s.cs
+++ b/suite/MC/LoongArch/arm-mov.s.cs
@ -0,0 +1,6 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xa4,0x44,0x36,0x00 = armmove $a0, $a1, 1
+0x9d,0xc4,0x3f,0x00 = armmov.w $a0, 1
+0x9e,0xc4,0x3f,0x00 = armmov.d $a0, 1
+0x44,0x04,0x5c,0x00 = armmfflag $a0, 1
+0x64,0x04,0x5c,0x00 = armmtflag $a0, 1
--- a/suite/MC/LoongArch/arm-shift.s.cs
+++ b/suite/MC/LoongArch/arm-shift.s.cs
@ -0,0 +1,10 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x91,0x94,0x3a,0x00 = armsll.w $a0, $a1, 1
+0x91,0x14,0x3b,0x00 = armsrl.w $a0, $a1, 1
+0x91,0x94,0x3b,0x00 = armsra.w $a0, $a1, 1
+0x91,0x14,0x3c,0x00 = armrotr.w $a0, $a1, 1
+0x91,0x84,0x3c,0x00 = armslli.w $a0, 1, 1
+0x91,0x04,0x3d,0x00 = armsrli.w $a0, 1, 1
+0x91,0x84,0x3d,0x00 = armsrai.w $a0, 1, 1
+0x91,0x04,0x3e,0x00 = armrotri.w $a0, 1, 1
+0x9f,0xc4,0x3f,0x00 = armrrx.w $a0, 1
--- a/suite/MC/LoongArch/atomic.s.cs
+++ b/suite/MC/LoongArch/atomic.s.cs
@ -0,0 +1,5 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x62,0xdf,0x00,0x20 = ll.w $tp, $s4, 0xdc
+0xd3,0x39,0x00,0x21 = sc.w $t7, $t2, 0x38
+0xcd,0x81,0x57,0x38 = llacq.w $t1, $t2
+0xcd,0x85,0x57,0x38 = screl.w $t1, $t2
--- a/suite/MC/LoongArch/avg.s.cs
+++ b/suite/MC/LoongArch/avg.s.cs
@ -0,0 +1,9 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xc5,0x57,0x64,0x74 = xvavg.b $xr5, $xr30, $xr21
+0x32,0xd6,0x64,0x74 = xvavg.h $xr18, $xr17, $xr21
+0xe3,0x52,0x65,0x74 = xvavg.w $xr3, $xr23, $xr20
+0x1b,0xec,0x65,0x74 = xvavg.d $xr27, $xr0, $xr27
+0x8b,0x40,0x66,0x74 = xvavg.bu $xr11, $xr4, $xr16
+0x22,0xcc,0x66,0x74 = xvavg.hu $xr2, $xr1, $xr19
+0x9b,0x6e,0x67,0x74 = xvavg.wu $xr27, $xr20, $xr27
+0x97,0xf6,0x67,0x74 = xvavg.du $xr23, $xr20, $xr29
--- a/suite/MC/LoongArch/avgr.s.cs
+++ b/suite/MC/LoongArch/avgr.s.cs
@ -0,0 +1,9 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xfd,0x1d,0x68,0x74 = xvavgr.b $xr29, $xr15, $xr7
+0x40,0xbf,0x68,0x74 = xvavgr.h $xr0, $xr26, $xr15
+0x17,0x00,0x69,0x74 = xvavgr.w $xr23, $xr0, $xr0
+0xfd,0x82,0x69,0x74 = xvavgr.d $xr29, $xr23, $xr0
+0x56,0x64,0x6a,0x74 = xvavgr.bu $xr22, $xr2, $xr25
+0x59,0xd5,0x6a,0x74 = xvavgr.hu $xr25, $xr10, $xr21
+0xd1,0x0d,0x6b,0x74 = xvavgr.wu $xr17, $xr14, $xr3
+0x62,0xb5,0x6b,0x74 = xvavgr.du $xr2, $xr11, $xr13
--- a/suite/MC/LoongArch/barrier.s.cs
+++ b/suite/MC/LoongArch/barrier.s.cs
@ -0,0 +1,3 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x00,0x00,0x72,0x38 = dbar 0
+0x00,0x80,0x72,0x38 = ibar 0
--- a/suite/MC/LoongArch/base.s.cs
+++ b/suite/MC/LoongArch/base.s.cs
@ -0,0 +1,34 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xa4,0x04,0x29,0x00 = addu12i.w $a0, $a1, 1
+0xa4,0x84,0x29,0x00 = addu12i.d $a0, $a1, 1
+0xa4,0x18,0x30,0x00 = adc.b $a0, $a1, $a2
+0xa4,0x98,0x30,0x00 = adc.h $a0, $a1, $a2
+0xa4,0x18,0x31,0x00 = adc.w $a0, $a1, $a2
+0xa4,0x98,0x31,0x00 = adc.d $a0, $a1, $a2
+0xa4,0x18,0x32,0x00 = sbc.b $a0, $a1, $a2
+0xa4,0x98,0x32,0x00 = sbc.h $a0, $a1, $a2
+0xa4,0x18,0x33,0x00 = sbc.w $a0, $a1, $a2
+0xa4,0x98,0x33,0x00 = sbc.d $a0, $a1, $a2
+0xa4,0x18,0x1a,0x00 = rotr.b $a0, $a1, $a2
+0xa4,0x98,0x1a,0x00 = rotr.h $a0, $a1, $a2
+0xa4,0x24,0x4c,0x00 = rotri.b $a0, $a1, 1
+0xa4,0x44,0x4c,0x00 = rotri.h $a0, $a1, 1
+0xa4,0x18,0x34,0x00 = rcr.b $a0, $a1, $a2
+0xa4,0x98,0x34,0x00 = rcr.h $a0, $a1, $a2
+0xa4,0x18,0x35,0x00 = rcr.w $a0, $a1, $a2
+0xa4,0x98,0x35,0x00 = rcr.d $a0, $a1, $a2
+0xa4,0x24,0x50,0x00 = rcri.b $a0, $a1, 1
+0xa4,0x44,0x50,0x00 = rcri.h $a0, $a1, 1
+0xa4,0x84,0x50,0x00 = rcri.w $a0, $a1, 1
+0xa4,0x04,0x51,0x00 = rcri.d $a0, $a1, 1
+0x20,0xe4,0x14,0x01 = fcvt.ud.d $fa0, $fa1
+0x20,0xe0,0x14,0x01 = fcvt.ld.d $fa0, $fa1
+0x20,0x08,0x15,0x01 = fcvt.d.ld $fa0, $fa1, $fa2
+0xa4,0x04,0x80,0x2e = ldl.d $a0, $a1, 1
+0xa4,0x04,0x00,0x2e = ldl.w $a0, $a1, 1
+0xa4,0x04,0x40,0x2e = ldr.w $a0, $a1, 1
+0xa4,0x04,0xc0,0x2e = ldr.d $a0, $a1, 1
+0xa4,0x04,0x00,0x2f = stl.w $a0, $a1, 1
+0xa4,0x04,0x80,0x2f = stl.d $a0, $a1, 1
+0xa4,0x04,0x40,0x2f = str.w $a0, $a1, 1
+0xa4,0x04,0xc0,0x2f = str.d $a0, $a1, 1
--- a/suite/MC/LoongArch/bit-manipu.s.cs
+++ b/suite/MC/LoongArch/bit-manipu.s.cs
@ -0,0 +1,13 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x61,0x10,0x00,0x00 = clo.w $ra, $sp
+0x47,0x15,0x00,0x00 = clz.w $a3, $a6
+0xc2,0x18,0x00,0x00 = cto.w $tp, $a2
+0xc5,0x1e,0x00,0x00 = ctz.w $a1, $fp
+0x1d,0x40,0x08,0x00 = bytepick.w $s6, $zero, $t4, 0
+0x74,0x31,0x00,0x00 = revb.2h $t8, $a7
+0x75,0x4b,0x00,0x00 = bitrev.4b $r21, $s4
+0xb9,0x50,0x00,0x00 = bitrev.w $s2, $a1
+0x68,0x09,0x67,0x00 = bstrins.w $a4, $a7, 7, 2
+0x21,0x91,0x6a,0x00 = bstrpick.w $ra, $a5, 0xa, 4
+0x74,0x49,0x13,0x00 = maskeqz $t8, $a7, $t6
+0xb4,0xe9,0x13,0x00 = masknez $t8, $t1, $s3
--- a/suite/MC/LoongArch/bit-shift.s.cs
+++ b/suite/MC/LoongArch/bit-shift.s.cs
@ -0,0 +1,9 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x78,0x5f,0x17,0x00 = sll.w $s1, $s4, $s0
+0x3f,0x9e,0x17,0x00 = srl.w $s8, $t5, $a3
+0x8c,0x2b,0x18,0x00 = sra.w $t0, $s5, $a6
+0x41,0x4b,0x1b,0x00 = rotr.w $ra, $s3, $t6
+0x5a,0x82,0x40,0x00 = slli.w $s3, $t6, 0
+0xca,0xf9,0x44,0x00 = srli.w $a6, $t2, 0x1e
+0x28,0xe2,0x48,0x00 = srai.w $a4, $t5, 0x18
+0x97,0xde,0x4c,0x00 = rotri.w $s0, $t8, 0x17
--- a/suite/MC/LoongArch/bitclr.s.cs
+++ b/suite/MC/LoongArch/bitclr.s.cs
@ -0,0 +1,9 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xb8,0x38,0x0c,0x75 = xvbitclr.b $xr24, $xr5, $xr14
+0x3e,0xb5,0x0c,0x75 = xvbitclr.h $xr30, $xr9, $xr13
+0x62,0x1c,0x0d,0x75 = xvbitclr.w $xr2, $xr3, $xr7
+0xae,0xe4,0x0d,0x75 = xvbitclr.d $xr14, $xr5, $xr25
+0x56,0x3f,0x10,0x77 = xvbitclri.b $xr22, $xr26, 7
+0xc2,0x75,0x10,0x77 = xvbitclri.h $xr2, $xr14, 0xd
+0x43,0x80,0x10,0x77 = xvbitclri.w $xr3, $xr2, 0
+0x8a,0x1d,0x11,0x77 = xvbitclri.d $xr10, $xr12, 7
--- a/suite/MC/LoongArch/bitrev.s.cs
+++ b/suite/MC/LoongArch/bitrev.s.cs
@ -0,0 +1,9 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x90,0x0e,0x10,0x75 = xvbitrev.b $xr16, $xr20, $xr3
+0x70,0xd0,0x10,0x75 = xvbitrev.h $xr16, $xr3, $xr20
+0x58,0x5f,0x11,0x75 = xvbitrev.w $xr24, $xr26, $xr23
+0x2d,0xec,0x11,0x75 = xvbitrev.d $xr13, $xr1, $xr27
+0x67,0x35,0x18,0x77 = xvbitrevi.b $xr7, $xr11, 5
+0xa1,0x7c,0x18,0x77 = xvbitrevi.h $xr1, $xr5, 0xf
+0xad,0xca,0x18,0x77 = xvbitrevi.w $xr13, $xr21, 0x12
+0x61,0x24,0x19,0x77 = xvbitrevi.d $xr1, $xr3, 0x9
--- a/suite/MC/LoongArch/bitsel.s.cs
+++ b/suite/MC/LoongArch/bitsel.s.cs
@ -0,0 +1,2 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xb2,0xbf,0x2a,0x0d = xvbitsel.v $xr18, $xr29, $xr15, $xr21
--- a/suite/MC/LoongArch/bitseli.s.cs
+++ b/suite/MC/LoongArch/bitseli.s.cs
@ -0,0 +1,2 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xad,0xe6,0xc5,0x77 = xvbitseli.b $xr13, $xr21, 0x79
--- a/suite/MC/LoongArch/bitset.s.cs
+++ b/suite/MC/LoongArch/bitset.s.cs
@ -0,0 +1,9 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x06,0x72,0x0e,0x75 = xvbitset.b $xr6, $xr16, $xr28
+0xa5,0xfd,0x0e,0x75 = xvbitset.h $xr5, $xr13, $xr31
+0x87,0x23,0x0f,0x75 = xvbitset.w $xr7, $xr28, $xr8
+0x04,0xb2,0x0f,0x75 = xvbitset.d $xr4, $xr16, $xr12
+0x7a,0x20,0x14,0x77 = xvbitseti.b $xr26, $xr3, 0
+0x69,0x66,0x14,0x77 = xvbitseti.h $xr9, $xr19, 0x9
+0x6c,0x8a,0x14,0x77 = xvbitseti.w $xr12, $xr19, 2
+0xf4,0x08,0x15,0x77 = xvbitseti.d $xr20, $xr7, 2
--- a/suite/MC/LoongArch/bound-check.s.cs
+++ b/suite/MC/LoongArch/bound-check.s.cs
@ -0,0 +1,17 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xc6,0x74,0x78,0x38 = ldgt.b $a2, $a2, $s6
+0xe5,0x87,0x78,0x38 = ldgt.h $a1, $s8, $ra
+0x4f,0x23,0x79,0x38 = ldgt.w $t3, $s3, $a4
+0x37,0xff,0x79,0x38 = ldgt.d $s0, $s2, $s8
+0x89,0x3d,0x7a,0x38 = ldle.b $a5, $t0, $t3
+0x6b,0xdd,0x7a,0x38 = ldle.h $a7, $a7, $s0
+0x58,0x08,0x7b,0x38 = ldle.w $s1, $tp, $tp
+0xf4,0xc1,0x7b,0x38 = ldle.d $t8, $t3, $t4
+0x7b,0x52,0x7c,0x38 = stgt.b $s4, $t7, $t8
+0x90,0x98,0x7c,0x38 = stgt.h $t4, $a0, $a2
+0x9f,0x3b,0x7d,0x38 = stgt.w $s8, $s5, $t2
+0xbe,0xe2,0x7d,0x38 = stgt.d $s7, $r21, $s1
+0x8a,0x40,0x7e,0x38 = stle.b $a6, $a0, $t4
+0x31,0xd6,0x7e,0x38 = stle.h $t5, $t5, $r21
+0x97,0x77,0x7f,0x38 = stle.w $s0, $s5, $s6
+0x19,0xf7,0x7f,0x38 = stle.d $s2, $s1, $s6
--- a/suite/MC/LoongArch/branch.s.cs
+++ b/suite/MC/LoongArch/branch.s.cs
@ -0,0 +1,12 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x47,0xb1,0x00,0x58 = beq $a6, $a3, 0xb0
+0x21,0x8b,0x00,0x5c = bne $s2, $ra, 0x88
+0xfe,0xa9,0x00,0x60 = blt $t3, $s7, 0xa8
+0x8f,0x95,0x00,0x64 = bge $t0, $t3, 0x94
+0x25,0x06,0x00,0x68 = bltu $t5, $a1, 4
+0xd7,0x8c,0x00,0x6c = bgeu $a2, $s0, 0x8c
+0x20,0x61,0x00,0x40 = beqz $a5, 0x60
+0x60,0xd4,0x00,0x44 = bnez $sp, 0xd4
+0x00,0xf8,0x00,0x50 = b 0xf8
+0x00,0xec,0x00,0x54 = bl 0xec
+0x81,0x04,0x00,0x4c = jirl $ra, $a0, 4
--- a/suite/MC/LoongArch/bsll.s.cs
+++ b/suite/MC/LoongArch/bsll.s.cs
@ -0,0 +1,2 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xae,0x52,0x8e,0x76 = xvbsll.v $xr14, $xr21, 0x14
--- a/suite/MC/LoongArch/bsrl.s.cs
+++ b/suite/MC/LoongArch/bsrl.s.cs
@ -0,0 +1,2 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xa4,0xf4,0x8e,0x76 = xvbsrl.v $xr4, $xr5, 0x1d
--- a/suite/MC/LoongArch/clo.s.cs
+++ b/suite/MC/LoongArch/clo.s.cs
@ -0,0 +1,5 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x89,0x01,0x9c,0x76 = xvclo.b $xr9, $xr12
+0xd0,0x05,0x9c,0x76 = xvclo.h $xr16, $xr14
+0x5e,0x0a,0x9c,0x76 = xvclo.w $xr30, $xr18
+0xbf,0x0c,0x9c,0x76 = xvclo.d $xr31, $xr5
--- a/suite/MC/LoongArch/clz.s.cs
+++ b/suite/MC/LoongArch/clz.s.cs
@ -0,0 +1,5 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xc5,0x10,0x9c,0x76 = xvclz.b $xr5, $xr6
+0xe4,0x14,0x9c,0x76 = xvclz.h $xr4, $xr7
+0x0c,0x18,0x9c,0x76 = xvclz.w $xr12, $xr0
+0x01,0x1c,0x9c,0x76 = xvclz.d $xr1, $xr0
--- a/suite/MC/LoongArch/crc.s.cs
+++ b/suite/MC/LoongArch/crc.s.cs
@ -0,0 +1,9 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xf8,0x08,0x24,0x00 = crc.w.b.w $s1, $a3, $tp
+0x5f,0xc9,0x24,0x00 = crc.w.h.w $s8, $a6, $t6
+0xdc,0x28,0x25,0x00 = crc.w.w.w $s5, $a2, $a6
+0x7c,0xfd,0x25,0x00 = crc.w.d.w $s5, $a7, $s8
+0x4f,0x0e,0x26,0x00 = crcc.w.b.w $t3, $t6, $sp
+0xb5,0xcb,0x26,0x00 = crcc.w.h.w $r21, $s6, $t6
+0xd1,0x35,0x27,0x00 = crcc.w.w.w $t5, $t2, $t1
+0xbe,0xee,0x27,0x00 = crcc.w.d.w $s7, $r21, $s4
--- a/suite/MC/LoongArch/d-arith.s.cs
+++ b/suite/MC/LoongArch/d-arith.s.cs
@ -0,0 +1,25 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xfd,0xe5,0x00,0x01 = fadd.s $fs5, $ft7, $fs1
+0xf9,0x34,0x01,0x01 = fadd.d $fs1, $fa7, $ft5
+0x3d,0x48,0x03,0x01 = fsub.d $fs5, $fa1, $ft10
+0xc4,0x1f,0x05,0x01 = fmul.d $fa4, $fs6, $fa7
+0x23,0x73,0x07,0x01 = fdiv.d $fa3, $fs1, $fs4
+0x15,0x73,0x2c,0x08 = fmadd.d $ft13, $fs0, $fs4, $fs0
+0x46,0xd2,0x6d,0x08 = fmsub.d $fa6, $ft10, $ft12, $fs3
+0xb9,0x4d,0xaf,0x08 = fnmadd.d $fs1, $ft5, $ft11, $fs6
+0x5e,0x1f,0xec,0x08 = fnmsub.d $fs6, $fs2, $fa7, $fs0
+0x4b,0x37,0x09,0x01 = fmax.d $ft3, $fs2, $ft5
+0xa1,0x6d,0x0b,0x01 = fmin.d $fa1, $ft5, $fs3
+0xb8,0x11,0x0d,0x01 = fmaxa.d $fs0, $ft5, $fa4
+0x52,0x01,0x0f,0x01 = fmina.d $ft10, $ft2, $fa0
+0x77,0x08,0x14,0x01 = fabs.d $ft15, $fa3
+0x4b,0x1b,0x14,0x01 = fneg.d $ft3, $fs2
+0x62,0x49,0x14,0x01 = fsqrt.d $fa2, $ft3
+0x7b,0x5b,0x14,0x01 = frecip.d $fs3, $fs3
+0x00,0x78,0x14,0x01 = frecipe.d $fa0, $fa0
+0x76,0x68,0x14,0x01 = frsqrt.d $ft14, $fa3
+0x21,0x88,0x14,0x01 = frsqrte.d $fa1, $fa1
+0xcc,0x69,0x11,0x01 = fscaleb.d $ft4, $ft6, $fs2
+0xb5,0x2b,0x14,0x01 = flogb.d $ft13, $fs5
+0x50,0x1b,0x13,0x01 = fcopysign.d $ft8, $fs2, $fa6
+0x53,0x38,0x14,0x01 = fclass.d $ft11, $fa2
--- a/suite/MC/LoongArch/d-bound-check.s.cs
+++ b/suite/MC/LoongArch/d-bound-check.s.cs
@ -0,0 +1,6 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x63,0x37,0x74,0x38 = fldgt.s $fa3, $s4, $t1
+0xba,0xfc,0x74,0x38 = fldgt.d $fs2, $a1, $s8
+0xe3,0xd9,0x75,0x38 = fldle.d $fa3, $t3, $fp
+0x6d,0xe9,0x76,0x38 = fstgt.d $ft5, $a7, $s3
+0x32,0xb5,0x77,0x38 = fstle.d $ft10, $a5, $t1
--- a/suite/MC/LoongArch/d-branch.s.cs
+++ b/suite/MC/LoongArch/d-branch.s.cs
@ -0,0 +1,2 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xc0,0x0c,0x00,0x48 = bceqz $fcc6, 0xc
--- a/suite/MC/LoongArch/d-comp.s.cs
+++ b/suite/MC/LoongArch/d-comp.s.cs
@ -0,0 +1,24 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x00,0x04,0x10,0x0c = fcmp.caf.s $fcc0, $fa0, $fa1
+0x00,0x04,0x20,0x0c = fcmp.caf.d $fcc0, $fa0, $fa1
+0x00,0x04,0x24,0x0c = fcmp.cun.d $fcc0, $fa0, $fa1
+0x00,0x04,0x22,0x0c = fcmp.ceq.d $fcc0, $fa0, $fa1
+0x00,0x04,0x26,0x0c = fcmp.cueq.d $fcc0, $fa0, $fa1
+0x00,0x04,0x21,0x0c = fcmp.clt.d $fcc0, $fa0, $fa1
+0x00,0x04,0x25,0x0c = fcmp.cult.d $fcc0, $fa0, $fa1
+0x00,0x04,0x23,0x0c = fcmp.cle.d $fcc0, $fa0, $fa1
+0x00,0x04,0x27,0x0c = fcmp.cule.d $fcc0, $fa0, $fa1
+0x00,0x04,0x28,0x0c = fcmp.cne.d $fcc0, $fa0, $fa1
+0x00,0x04,0x2a,0x0c = fcmp.cor.d $fcc0, $fa0, $fa1
+0x00,0x04,0x2c,0x0c = fcmp.cune.d $fcc0, $fa0, $fa1
+0x00,0x84,0x20,0x0c = fcmp.saf.d $fcc0, $fa0, $fa1
+0x00,0x84,0x24,0x0c = fcmp.sun.d $fcc0, $fa0, $fa1
+0x00,0x84,0x22,0x0c = fcmp.seq.d $fcc0, $fa0, $fa1
+0x00,0x84,0x26,0x0c = fcmp.sueq.d $fcc0, $fa0, $fa1
+0x00,0x84,0x21,0x0c = fcmp.slt.d $fcc0, $fa0, $fa1
+0x00,0x84,0x25,0x0c = fcmp.sult.d $fcc0, $fa0, $fa1
+0x00,0x84,0x23,0x0c = fcmp.sle.d $fcc0, $fa0, $fa1
+0x00,0x84,0x27,0x0c = fcmp.sule.d $fcc0, $fa0, $fa1
+0x00,0x84,0x28,0x0c = fcmp.sne.d $fcc0, $fa0, $fa1
+0x00,0x84,0x2a,0x0c = fcmp.sor.d $fcc0, $fa0, $fa1
+0x00,0x84,0x2c,0x0c = fcmp.sune.d $fcc0, $fa0, $fa1
--- a/suite/MC/LoongArch/d-conv.s.cs
+++ b/suite/MC/LoongArch/d-conv.s.cs
@ -0,0 +1,23 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x25,0x46,0x1e,0x01 = frint.s $fa5, $ft9
+0x6c,0x1a,0x19,0x01 = fcvt.s.d $ft4, $ft11
+0xca,0x24,0x19,0x01 = fcvt.d.s $ft2, $fa6
+0xa6,0x18,0x1d,0x01 = ffint.s.l $fa6, $fa5
+0x58,0x22,0x1d,0x01 = ffint.d.w $fs0, $ft10
+0x57,0x2b,0x1d,0x01 = ffint.d.l $ft15, $fs2
+0xc3,0x09,0x1b,0x01 = ftint.w.d $fa3, $ft6
+0x1f,0x27,0x1b,0x01 = ftint.l.s $fs7, $fs0
+0x10,0x2b,0x1b,0x01 = ftint.l.d $ft8, $fs0
+0x07,0x09,0x1a,0x01 = ftintrm.w.d $fa7, $ft0
+0x58,0x25,0x1a,0x01 = ftintrm.l.s $fs0, $ft2
+0x29,0x29,0x1a,0x01 = ftintrm.l.d $ft1, $ft1
+0x6c,0x48,0x1a,0x01 = ftintrp.w.d $ft4, $fa3
+0x00,0x66,0x1a,0x01 = ftintrp.l.s $fa0, $ft8
+0xa4,0x6b,0x1a,0x01 = ftintrp.l.d $fa4, $fs5
+0x19,0x8b,0x1a,0x01 = ftintrz.w.d $fs1, $fs0
+0xb7,0xa4,0x1a,0x01 = ftintrz.l.s $ft15, $fa5
+0x43,0xa9,0x1a,0x01 = ftintrz.l.d $fa3, $ft2
+0x9f,0xc9,0x1a,0x01 = ftintrne.w.d $fs7, $ft4
+0x76,0xe7,0x1a,0x01 = ftintrne.l.s $ft14, $fs3
+0xdc,0xe8,0x1a,0x01 = ftintrne.l.d $fs4, $fa6
+0x5d,0x48,0x1e,0x01 = frint.d $fs5, $fa2
--- a/suite/MC/LoongArch/d-memory.s.cs
+++ b/suite/MC/LoongArch/d-memory.s.cs
@ -0,0 +1,6 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xf7,0xe9,0x03,0x2b = fld.s $ft15, $t3, 0xfa
+0x36,0xca,0x81,0x2b = fld.d $ft14, $t5, 0x72
+0xfc,0x18,0xc3,0x2b = fst.d $fs4, $a3, 0xc6
+0xbb,0x7d,0x34,0x38 = fldx.d $fs3, $t1, $s8
+0xe6,0x45,0x3c,0x38 = fstx.d $fa6, $t3, $t5
--- a/suite/MC/LoongArch/d-move.s.cs
+++ b/suite/MC/LoongArch/d-move.s.cs
@ -0,0 +1,4 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xed,0x96,0x14,0x01 = fmov.s $ft5, $ft15
+0x3e,0x99,0x14,0x01 = fmov.d $fs6, $ft1
+0x92,0x56,0x02,0x0d = fsel $ft10, $ft12, $ft13, $fcc4
--- a/suite/MC/LoongArch/div.s.cs
+++ b/suite/MC/LoongArch/div.s.cs
@ -0,0 +1,9 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x29,0x23,0xe0,0x74 = xvdiv.b $xr9, $xr25, $xr8
+0x32,0xec,0xe0,0x74 = xvdiv.h $xr18, $xr1, $xr27
+0x45,0x6f,0xe1,0x74 = xvdiv.w $xr5, $xr26, $xr27
+0x5b,0xb3,0xe1,0x74 = xvdiv.d $xr27, $xr26, $xr12
+0xc0,0x7a,0xe4,0x74 = xvdiv.bu $xr0, $xr22, $xr30
+0xff,0xe6,0xe4,0x74 = xvdiv.hu $xr31, $xr23, $xr25
+0x21,0x1f,0xe5,0x74 = xvdiv.wu $xr1, $xr25, $xr7
+0x27,0x9f,0xe5,0x74 = xvdiv.du $xr7, $xr25, $xr7
--- a/suite/MC/LoongArch/ext2xv.s.cs
+++ b/suite/MC/LoongArch/ext2xv.s.cs
@ -0,0 +1,13 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x7e,0x12,0x9f,0x76 = vext2xv.h.b $xr30, $xr19
+0xbb,0x14,0x9f,0x76 = vext2xv.w.b $xr27, $xr5
+0x39,0x1b,0x9f,0x76 = vext2xv.d.b $xr25, $xr25
+0x94,0x1e,0x9f,0x76 = vext2xv.w.h $xr20, $xr20
+0x68,0x22,0x9f,0x76 = vext2xv.d.h $xr8, $xr19
+0x24,0x27,0x9f,0x76 = vext2xv.d.w $xr4, $xr25
+0x99,0x29,0x9f,0x76 = vext2xv.hu.bu $xr25, $xr12
+0xbf,0x2d,0x9f,0x76 = vext2xv.wu.bu $xr31, $xr13
+0x2c,0x33,0x9f,0x76 = vext2xv.du.bu $xr12, $xr25
+0x97,0x35,0x9f,0x76 = vext2xv.wu.hu $xr23, $xr12
+0xd2,0x38,0x9f,0x76 = vext2xv.du.hu $xr18, $xr6
+0xaa,0x3e,0x9f,0x76 = vext2xv.du.wu $xr10, $xr21
--- a/suite/MC/LoongArch/exth.s.cs
+++ b/suite/MC/LoongArch/exth.s.cs
@ -0,0 +1,9 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x4f,0xe1,0x9e,0x76 = xvexth.h.b $xr15, $xr10
+0x7a,0xe5,0x9e,0x76 = xvexth.w.h $xr26, $xr11
+0x62,0xeb,0x9e,0x76 = xvexth.d.w $xr2, $xr27
+0x36,0xef,0x9e,0x76 = xvexth.q.d $xr22, $xr25
+0xd5,0xf3,0x9e,0x76 = xvexth.hu.bu $xr21, $xr30
+0x7c,0xf5,0x9e,0x76 = xvexth.wu.hu $xr28, $xr11
+0x3b,0xfb,0x9e,0x76 = xvexth.du.wu $xr27, $xr25
+0x90,0xff,0x9e,0x76 = xvexth.qu.du $xr16, $xr28
--- a/suite/MC/LoongArch/extl.s.cs
+++ b/suite/MC/LoongArch/extl.s.cs
@ -0,0 +1,3 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x9d,0x01,0x09,0x77 = xvextl.q.d $xr29, $xr12
+0x9b,0x02,0x0d,0x77 = xvextl.qu.du $xr27, $xr20
--- a/suite/MC/LoongArch/extrins.s.cs
+++ b/suite/MC/LoongArch/extrins.s.cs
@ -0,0 +1,5 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xfe,0xf2,0x8f,0x77 = xvextrins.b $xr30, $xr23, 0xfc
+0xa0,0x21,0x8b,0x77 = xvextrins.h $xr0, $xr13, 0xc8
+0xae,0x62,0x86,0x77 = xvextrins.w $xr14, $xr21, 0x98
+0xdf,0x1f,0x82,0x77 = xvextrins.d $xr31, $xr30, 0x87
--- a/suite/MC/LoongArch/f-arith.s.cs
+++ b/suite/MC/LoongArch/f-arith.s.cs
@ -0,0 +1,24 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xfd,0xe5,0x00,0x01 = fadd.s $fs5, $ft7, $fs1
+0xce,0xfc,0x02,0x01 = fsub.s $ft6, $fa6, $fs7
+0xe0,0xc4,0x04,0x01 = fmul.s $fa0, $fa7, $ft9
+0x14,0xcf,0x06,0x01 = fdiv.s $ft12, $fs0, $ft11
+0x03,0x8e,0x17,0x08 = fmadd.s $fa3, $ft8, $fa3, $ft7
+0x77,0x55,0x52,0x08 = fmsub.s $ft15, $ft3, $ft13, $fa4
+0x3d,0x60,0x9a,0x08 = fnmadd.s $fs5, $fa1, $fs0, $ft12
+0x88,0xe0,0xdc,0x08 = fnmsub.s $ft0, $fa4, $fs0, $fs1
+0xd6,0xec,0x08,0x01 = fmax.s $ft14, $fa6, $fs3
+0x4e,0xcd,0x0a,0x01 = fmin.s $ft6, $ft2, $ft11
+0x69,0xff,0x0c,0x01 = fmaxa.s $ft1, $fs3, $fs7
+0x4f,0x86,0x0e,0x01 = fmina.s $ft7, $ft10, $fa1
+0x9c,0x05,0x14,0x01 = fabs.s $fs4, $ft4
+0x15,0x17,0x14,0x01 = fneg.s $ft13, $fs0
+0x5b,0x46,0x14,0x01 = fsqrt.s $fs3, $ft10
+0x71,0x57,0x14,0x01 = frecip.s $ft9, $fs3
+0x00,0x74,0x14,0x01 = frecipe.s $fa0, $fa0
+0x99,0x65,0x14,0x01 = frsqrt.s $fs1, $ft4
+0x21,0x84,0x14,0x01 = frsqrte.s $fa1, $fa1
+0xf5,0x9a,0x10,0x01 = fscaleb.s $ft13, $ft15, $fa6
+0xff,0x26,0x14,0x01 = flogb.s $fs7, $ft15
+0x0d,0xdf,0x12,0x01 = fcopysign.s $ft5, $fs0, $ft15
+0x34,0x35,0x14,0x01 = fclass.s $ft12, $ft1
--- a/suite/MC/LoongArch/f-bound-check.s.cs
+++ b/suite/MC/LoongArch/f-bound-check.s.cs
@ -0,0 +1,5 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x63,0x37,0x74,0x38 = fldgt.s $fa3, $s4, $t1
+0xb8,0x47,0x75,0x38 = fldle.s $fs0, $s6, $t5
+0xbf,0x79,0x76,0x38 = fstgt.s $fs7, $t1, $s7
+0xad,0x1d,0x77,0x38 = fstle.s $ft5, $t1, $a3
--- a/suite/MC/LoongArch/f-branch.s.cs
+++ b/suite/MC/LoongArch/f-branch.s.cs
@ -0,0 +1,3 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xc0,0x0c,0x00,0x48 = bceqz $fcc6, 0xc
+0xc0,0x49,0x00,0x48 = bcnez $fcc6, 0x48
--- a/suite/MC/LoongArch/f-comp.s.cs
+++ b/suite/MC/LoongArch/f-comp.s.cs
@ -0,0 +1,23 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x00,0x04,0x10,0x0c = fcmp.caf.s $fcc0, $fa0, $fa1
+0x00,0x04,0x14,0x0c = fcmp.cun.s $fcc0, $fa0, $fa1
+0x00,0x04,0x12,0x0c = fcmp.ceq.s $fcc0, $fa0, $fa1
+0x00,0x04,0x16,0x0c = fcmp.cueq.s $fcc0, $fa0, $fa1
+0x00,0x04,0x11,0x0c = fcmp.clt.s $fcc0, $fa0, $fa1
+0x00,0x04,0x15,0x0c = fcmp.cult.s $fcc0, $fa0, $fa1
+0x00,0x04,0x13,0x0c = fcmp.cle.s $fcc0, $fa0, $fa1
+0x00,0x04,0x17,0x0c = fcmp.cule.s $fcc0, $fa0, $fa1
+0x00,0x04,0x18,0x0c = fcmp.cne.s $fcc0, $fa0, $fa1
+0x00,0x04,0x1a,0x0c = fcmp.cor.s $fcc0, $fa0, $fa1
+0x00,0x04,0x1c,0x0c = fcmp.cune.s $fcc0, $fa0, $fa1
+0x00,0x84,0x10,0x0c = fcmp.saf.s $fcc0, $fa0, $fa1
+0x00,0x84,0x14,0x0c = fcmp.sun.s $fcc0, $fa0, $fa1
+0x00,0x84,0x12,0x0c = fcmp.seq.s $fcc0, $fa0, $fa1
+0x00,0x84,0x16,0x0c = fcmp.sueq.s $fcc0, $fa0, $fa1
+0x00,0x84,0x11,0x0c = fcmp.slt.s $fcc0, $fa0, $fa1
+0x00,0x84,0x15,0x0c = fcmp.sult.s $fcc0, $fa0, $fa1
+0x00,0x84,0x13,0x0c = fcmp.sle.s $fcc0, $fa0, $fa1
+0x00,0x84,0x17,0x0c = fcmp.sule.s $fcc0, $fa0, $fa1
+0x00,0x84,0x18,0x0c = fcmp.sne.s $fcc0, $fa0, $fa1
+0x00,0x84,0x1a,0x0c = fcmp.sor.s $fcc0, $fa0, $fa1
+0x00,0x84,0x1c,0x0c = fcmp.sune.s $fcc0, $fa0, $fa1
--- a/suite/MC/LoongArch/f-conv.s.cs
+++ b/suite/MC/LoongArch/f-conv.s.cs
@ -0,0 +1,8 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xbe,0x10,0x1d,0x01 = ffint.s.w $fs6, $fa5
+0xb5,0x05,0x1b,0x01 = ftint.w.s $ft13, $ft5
+0x10,0x06,0x1a,0x01 = ftintrm.w.s $ft8, $ft8
+0xee,0x47,0x1a,0x01 = ftintrp.w.s $ft6, $fs7
+0xa4,0x87,0x1a,0x01 = ftintrz.w.s $fa4, $fs5
+0x24,0xc6,0x1a,0x01 = ftintrne.w.s $fa4, $ft9
+0x25,0x46,0x1e,0x01 = frint.s $fa5, $ft9
--- a/suite/MC/LoongArch/f-memory.s.cs
+++ b/suite/MC/LoongArch/f-memory.s.cs
@ -0,0 +1,5 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xf7,0xe9,0x03,0x2b = fld.s $ft15, $t3, 0xfa
+0x7e,0x9a,0x43,0x2b = fst.s $fs6, $t7, 0xe6
+0xe1,0x4d,0x30,0x38 = fldx.s $fa1, $t3, $t7
+0x7a,0x58,0x38,0x38 = fstx.s $fs2, $sp, $fp
--- a/suite/MC/LoongArch/f-move.s.cs
+++ b/suite/MC/LoongArch/f-move.s.cs
@ -0,0 +1,17 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xed,0x96,0x14,0x01 = fmov.s $ft5, $ft15
+0x92,0x56,0x02,0x0d = fsel $ft10, $ft12, $ft13, $fcc4
+0x46,0xa4,0x14,0x01 = movgr2fr.w $fa6, $tp
+0xca,0xb6,0x14,0x01 = movfr2gr.s $a6, $ft14
+0x80,0xc0,0x14,0x01 = movgr2fcsr $fcsr0, $a0
+0x04,0xc8,0x14,0x01 = movfcsr2gr $a0, $fcsr0
+0x81,0xc0,0x14,0x01 = movgr2fcsr $fcsr1, $a0
+0x24,0xc8,0x14,0x01 = movfcsr2gr $a0, $fcsr1
+0x82,0xc0,0x14,0x01 = movgr2fcsr $fcsr2, $a0
+0x44,0xc8,0x14,0x01 = movfcsr2gr $a0, $fcsr2
+0x83,0xc0,0x14,0x01 = movgr2fcsr $fcsr3, $a0
+0x64,0xc8,0x14,0x01 = movfcsr2gr $a0, $fcsr3
+0x64,0xd1,0x14,0x01 = movfr2cf $fcc4, $ft3
+0x10,0xd4,0x14,0x01 = movcf2fr $ft8, $fcc0
+0x25,0xd8,0x14,0x01 = movgr2cf $fcc5, $ra
+0xf5,0xdc,0x14,0x01 = movcf2gr $r21, $fcc7
--- a/suite/MC/LoongArch/fadd.s.cs
+++ b/suite/MC/LoongArch/fadd.s.cs
@ -0,0 +1,3 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xa6,0xbe,0x30,0x75 = xvfadd.s $xr6, $xr21, $xr15
+0x1b,0x05,0x31,0x75 = xvfadd.d $xr27, $xr8, $xr1
--- a/suite/MC/LoongArch/fclass.s.cs
+++ b/suite/MC/LoongArch/fclass.s.cs
@ -0,0 +1,3 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xe3,0xd4,0x9c,0x76 = xvfclass.s $xr3, $xr7
+0x56,0xd9,0x9c,0x76 = xvfclass.d $xr22, $xr10
--- a/suite/MC/LoongArch/fcmp.s.cs
+++ b/suite/MC/LoongArch/fcmp.s.cs
@ -0,0 +1,45 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x01,0x7d,0x90,0x0c = xvfcmp.caf.s $xr1, $xr8, $xr31
+0xf3,0x53,0xa0,0x0c = xvfcmp.caf.d $xr19, $xr31, $xr20
+0x28,0x75,0x94,0x0c = xvfcmp.cun.s $xr8, $xr9, $xr29
+0xd3,0x72,0xa4,0x0c = xvfcmp.cun.d $xr19, $xr22, $xr28
+0x20,0x00,0x92,0x0c = xvfcmp.ceq.s $xr0, $xr1, $xr0
+0xfd,0x52,0xa2,0x0c = xvfcmp.ceq.d $xr29, $xr23, $xr20
+0xa5,0x7d,0x96,0x0c = xvfcmp.cueq.s $xr5, $xr13, $xr31
+0xc4,0x1e,0xa6,0x0c = xvfcmp.cueq.d $xr4, $xr22, $xr7
+0x24,0x05,0x91,0x0c = xvfcmp.clt.s $xr4, $xr9, $xr1
+0x93,0x54,0xa1,0x0c = xvfcmp.clt.d $xr19, $xr4, $xr21
+0x2f,0x0e,0x95,0x0c = xvfcmp.cult.s $xr15, $xr17, $xr3
+0x34,0x1a,0xa5,0x0c = xvfcmp.cult.d $xr20, $xr17, $xr6
+0xd6,0x3e,0x93,0x0c = xvfcmp.cle.s $xr22, $xr22, $xr15
+0x35,0x33,0xa3,0x0c = xvfcmp.cle.d $xr21, $xr25, $xr12
+0x41,0x74,0x97,0x0c = xvfcmp.cule.s $xr1, $xr2, $xr29
+0xa0,0x2c,0xa7,0x0c = xvfcmp.cule.d $xr0, $xr5, $xr11
+0x27,0x6a,0x98,0x0c = xvfcmp.cne.s $xr7, $xr17, $xr26
+0x32,0x03,0xa8,0x0c = xvfcmp.cne.d $xr18, $xr25, $xr0
+0x41,0x38,0x9a,0x0c = xvfcmp.cor.s $xr1, $xr2, $xr14
+0x6c,0x5e,0xaa,0x0c = xvfcmp.cor.d $xr12, $xr19, $xr23
+0x35,0x12,0x9c,0x0c = xvfcmp.cune.s $xr21, $xr17, $xr4
+0xd4,0x33,0xac,0x0c = xvfcmp.cune.d $xr20, $xr30, $xr12
+0x77,0x89,0x90,0x0c = xvfcmp.saf.s $xr23, $xr11, $xr2
+0x87,0x9d,0xa0,0x0c = xvfcmp.saf.d $xr7, $xr12, $xr7
+0xe0,0xf8,0x94,0x0c = xvfcmp.sun.s $xr0, $xr7, $xr30
+0x64,0xf9,0xa4,0x0c = xvfcmp.sun.d $xr4, $xr11, $xr30
+0xef,0xee,0x92,0x0c = xvfcmp.seq.s $xr15, $xr23, $xr27
+0xcf,0x8e,0xa2,0x0c = xvfcmp.seq.d $xr15, $xr22, $xr3
+0x4c,0xa7,0x96,0x0c = xvfcmp.sueq.s $xr12, $xr26, $xr9
+0x45,0xc6,0xa6,0x0c = xvfcmp.sueq.d $xr5, $xr18, $xr17
+0x59,0xfe,0x91,0x0c = xvfcmp.slt.s $xr25, $xr18, $xr31
+0x51,0xe3,0xa1,0x0c = xvfcmp.slt.d $xr17, $xr26, $xr24
+0xe8,0xc9,0x95,0x0c = xvfcmp.sult.s $xr8, $xr15, $xr18
+0x84,0x94,0xa5,0x0c = xvfcmp.sult.d $xr4, $xr4, $xr5
+0xa1,0xc0,0x93,0x0c = xvfcmp.sle.s $xr1, $xr5, $xr16
+0x23,0xdc,0xa3,0x0c = xvfcmp.sle.d $xr3, $xr1, $xr23
+0x77,0x85,0x97,0x0c = xvfcmp.sule.s $xr23, $xr11, $xr1
+0x4b,0xc5,0xa7,0x0c = xvfcmp.sule.d $xr11, $xr10, $xr17
+0x9b,0xf9,0x98,0x0c = xvfcmp.sne.s $xr27, $xr12, $xr30
+0x94,0xc6,0xa8,0x0c = xvfcmp.sne.d $xr20, $xr20, $xr17
+0xab,0x89,0x9a,0x0c = xvfcmp.sor.s $xr11, $xr13, $xr2
+0x86,0x9b,0xaa,0x0c = xvfcmp.sor.d $xr6, $xr28, $xr6
+0x0b,0xa2,0x9c,0x0c = xvfcmp.sune.s $xr11, $xr16, $xr8
+0xbe,0xec,0xac,0x0c = xvfcmp.sune.d $xr30, $xr5, $xr27
--- a/suite/MC/LoongArch/fcvt.s.cs
+++ b/suite/MC/LoongArch/fcvt.s.cs
@ -0,0 +1,3 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x29,0x5e,0x46,0x75 = xvfcvt.h.s $xr9, $xr17, $xr23
+0x5b,0xf5,0x46,0x75 = xvfcvt.s.d $xr27, $xr10, $xr29
--- a/suite/MC/LoongArch/fcvth.s.cs
+++ b/suite/MC/LoongArch/fcvth.s.cs
@ -0,0 +1,3 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0x29,0xef,0x9d,0x76 = xvfcvth.s.h $xr9, $xr25
+0x3d,0xf6,0x9d,0x76 = xvfcvth.d.s $xr29, $xr17
--- a/suite/MC/LoongArch/fcvtl.s.cs
+++ b/suite/MC/LoongArch/fcvtl.s.cs
@ -0,0 +1,3 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xd0,0xe9,0x9d,0x76 = xvfcvtl.s.h $xr16, $xr14
+0xb8,0xf0,0x9d,0x76 = xvfcvtl.d.s $xr24, $xr5
--- a/suite/MC/LoongArch/fdiv.s.cs
+++ b/suite/MC/LoongArch/fdiv.s.cs
@ -0,0 +1,3 @@
+# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None
+0xbd,0xb0,0x3a,0x75 = xvfdiv.s $xr29, $xr5, $xr12
+0x5f,0x79,0x3b,0x75 = xvfdiv.d $xr31, $xr10, $xr30
--- a/Show More
+++ b/Show More