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https://github.com/capstone-engine/capstone.git
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fix conflicts
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parent
b227acc29c
commit
9b3ead3ab8
@ -31,12 +31,12 @@ __all__ = [
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'CS_ARCH_SPARC',
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'CS_ARCH_SYSZ',
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'CS_ARCH_XCORE',
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'CS_ARCH_MOS65XX',
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'CS_ARCH_M68K',
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'CS_ARCH_TMS320C64X',
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'CS_ARCH_M680X',
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'CS_ARCH_EVM',
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'CS_ARCH_BPF',
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'CS_ARCH_MOS65XX',
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'CS_ARCH_ALL',
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'CS_MODE_LITTLE_ENDIAN',
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@ -3,7 +3,7 @@
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# Capstone Python bindings, by Sebastian Macke <Sebastian Macke>
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from __future__ import print_function
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from capstone import *
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from capstone.mips import *
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from capstone.mos65xx import *
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from xprint import to_hex, to_x
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MOS65XX_CODE = b"\x0d\x34\x12\x00\x81\x65\x87\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42"
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@ -33,18 +33,18 @@ def print_insn_detail(insn):
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# "data" instruction generated by SKIPDATA option has no detail
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if insn.id == 0:
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return
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print("\taddress mode = %s" % (address_modes[insn.am]))
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print("\tmodifies flags = %r" % (insn.modifies_flags != 0))
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print("\taddress mode: %s" % (address_modes[insn.am]))
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print("\tmodifies flags: %s" % ('true' if insn.modifies_flags != 0 else 'false'))
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if len(insn.operands) > 0:
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print("\top_count: %u" % len(insn.operands))
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c = -1
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for i in insn.operands:
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c += 1
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if i.type == MIPS_OP_REG:
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if i.type == MOS65XX_OP_REG:
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print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
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if i.type == MIPS_OP_IMM:
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if i.type == MOS65XX_OP_IMM:
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print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
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if i.type == MIPS_OP_MEM:
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if i.type == MOS65XX_OP_MEM:
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print("\t\toperands[%u].type: MEM = 0x%s" % (c, to_x(i.mem)))
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4
cs.c
4
cs.c
@ -1423,8 +1423,8 @@ int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type)
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case CS_ARCH_EVM:
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break;
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case CS_ARCH_MOS65XX:
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for (i = 0; i < insn->detail->m680x.op_count; i++)
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if (insn->detail->m680x.operands[i].type == (m680x_op_type)op_type)
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for (i = 0; i < insn->detail->mos65xx.op_count; i++)
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if (insn->detail->mos65xx.operands[i].type == (mos65xx_op_type)op_type)
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count++;
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break;
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case CS_ARCH_WASM:
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@ -220,7 +220,7 @@ static void usage(char *prog)
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}
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if (cs_support(CS_ARCH_MOS65XX)) {
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printf(" mox65xx MOS65XX family\n");
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printf(" mos65xx MOS65XX family\n");
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}
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if (cs_support(CS_ARCH_WASM)) {
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@ -390,7 +390,7 @@ int main(int argc, char **argv)
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}
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if (cs_support(CS_ARCH_MOS65XX)) {
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printf("mox65xx=1 ");
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printf("mos65xx=1 ");
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}
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if (cs_support(CS_SUPPORT_DIET)) {
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@ -39,7 +39,7 @@ typedef enum mos65xx_address_mode {
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MOS65XX_AM_IND, ///< absolute indirect addressing
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} mos65xx_address_mode;
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/// M68K instruction
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/// MOS65XX instruction
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typedef enum mos65xx_insn {
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MOS65XX_INS_INVALID = 0,
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MOS65XX_INS_ADC,
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@ -101,7 +101,7 @@ typedef enum mos65xx_insn {
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MOS65XX_INS_ENDING, // <-- mark the end of the list of instructions
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} mos65xx_insn;
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/// Group of M68K instructions
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/// Group of MOS65XX instructions
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typedef enum mos65xx_group_type {
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MOS65XX_GRP_INVALID = 0, ///< CS_GRP_INVALID
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MOS65XX_GRP_JUMP, ///< = CS_GRP_JUMP
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@ -69,7 +69,7 @@ int main()
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}
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if (cs_support(CS_ARCH_MOS65XX)) {
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printf("mox65xx=1 ");
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printf("mos65xx=1 ");
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}
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if (cs_support(CS_SUPPORT_DIET)) {
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@ -23,7 +23,7 @@ static void print_string_hex(const char *comment, unsigned char *str, size_t len
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printf("%s", comment);
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for (c = str; c < str + len; c++) {
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printf("0x%02x ", *c & 0xff);
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printf(" 0x%02x", *c & 0xff);
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}
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printf("\n");
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@ -142,6 +142,7 @@ static void test()
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for (j = 0; j < count; j++) {
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printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
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print_insn_detail(&insn[j]);
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puts("");
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}
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printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
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