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AArch64 update to LLVM 18 (#2298)

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* Run clang-format

* Remove arm.h header from AArch64 files

* Update all AArch64 module files to LLVM-18.

* Add check if the differs save file is up-to-date with the current files.

* Add new generator for MC test trnaslation.

* Fix warnings

* Update generated AsmWriter files

* Remove unused variable

* Change MCPhysReg type to int16_t as LLVM 18 dictates.

With LLVM 18 the MCPhysReg value's type is changed to int16_t.
If we update modules to LLVM 18, they will generate
compiler warnings that uint16_t* should not be casted to int16_t*.

This makes changing the all tables to int16_t necessary, because the alternative is
to duplicate all MCPhysReg related code. Which is even worse.

* Assign enum values to raw_struct member

* Add printAdrAdrpLabel def

* Add header to regression test files.

* Write files to build dir and ignore more parsing errors.

* Fix parsing of MC test files.

* Reset parser after every block

* Add write and patch header step.

* Add and update MC tests for AArch64

* Fix clang-tidy warnings

* Don't warn about padding issues.

They break automatically initialized structs we can not change easily.

* Fix: Incorrect access of LLVM instruction descriptions.

* Initialize DecoderComplete flag

* Add more mapping and flag details

* Add function to get MCInstDesc from table

* Fix incorrect memory operand access types.

* Fix test where memory was not written, ut only read.

* Attempt to fix Windows build

* Fix 2268

The enum values were different and hence lead to different decoding.

* Refactor SME operands.

- Splits SME operands in Matrix and Predicate operands.
- Fixes general problems of incorrect detections with
the vector select/index operands of predicate registers.
- Simplifies code.

* Fix up typo in WRITE

* Print actual path to struct fields

* Add Registers of SME operands to the reg-read list

* Add tests for SME operands.

* Use Capstone reg enum for comparison

* Fix tests: 'Vector arra...' to 'operands[x].vas'

* Add the developer fuzz option.

* Fix Python bindings for SME operands

* Fix variable shadowing.

* Fix clang-tidy warnings

* Add missing break.

* Fix varg usage

* Brackets for case

* Handle AArch64_OP_GROUP_AdrAdrpLabel

* Fix endian issue with fuzzing start bytes

* Move previous sme.pred to it's own operand type.

* Fix calculation for imm ranges

* Print list member flag

* Fix up operand strings for cstest

* Do only a shallow clone of the cmocka stable branch

* Fix: Don't categorize ZT0 as a SME matrix operand.

* Remove unused code.

* Add flag to distinguish Vn and Qn registers.

* Add all registers to detail struct, even if emitted in the asm text

* Fix: Increment op count after each list member is added.

* Remove implicit write to NZCV for MSR Imm instructions.

* Handle several alias operands.

* Add details for zero alias with za0.h

* Add SME tile to write list if written

* Add write access flags to operands which are zeroed.

* Add SME tests of #2285

* Fix tests with latest syntax changes.

* Fix segfault if memory operand is only a label without register.

* Fix python bindings

* Attempt to fix clang-tidy warning for some configurations.

* Add missing test file (accidentially blocked by gitignore.)

* Print clang-tidy version before linting.

* Update differ save file

* Formatting

* Use clang-tidy-15 as if possible.

* Remove search patterns for MC tests, since they need to be reworked anyways.

* Enum to upper case change

* Add information to read the OSS fuzz result.

* Fix special case of SVE2 operands.

Apparently ZT0 registers can an index attached,
get which is BOUND to it. We have no "index for reg" field.
So it is simply saved as an immediate.

* Handle LLVM expressions without asserts.

* Ensure choices are always saved.

* OP_GROUP enums can't be all upper case because they contain type information.

* Fix compatibility header patching

* Update saved_choices.json

* Allow mode == None in test_corpus
This commit is contained in:
Rot127 2024-07-08 02:28:54 +00:00 committed by GitHub
parent 8ce088bf58
commit 9c5b48b57f
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
506 changed files with 169040 additions and 133759 deletions
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1
.github/workflows/CITest.yml vendored
View File

@ -132,7 +132,6 @@ jobs:
clang -lcapstone src/test_arm64_compatibility_header.c -o test_arm64_compatibility_header
fi
./test_arm64_compatibility_header
cd "$(git rev-parse --show-toplevel)"
- name: cstool - reaches disassembler engine
run: |

5
.github/workflows/auto-sync.yml vendored
View File

@ -66,3 +66,8 @@ jobs:
- name: Test Header patcher
run: |
python -m unittest src/autosync/Tests/test_header_patcher.py
python -m unittest src/autosync/Tests/test_mcupdater.py
- name: Differ - Test save file is up-to-date
run: |
./src/autosync/cpptranslator/Differ.py -a AArch64 --check_saved

4
.github/workflows/clang-tidy.yml vendored
View File

@ -26,6 +26,10 @@ jobs:
CC=clang sudo cmake --build . --config Release
cd ..
- name: Install clang-tidy-15
run: |
sudo apt install clang-tidy-15
- name: Check for warnings
env:
base_sha: ${{ github.event.pull_request.base.sha }}

1
CMakeLists.txt
View File

@ -890,6 +890,7 @@ if(CAPSTONE_BUILD_CSTEST)
PREFIX extern
GIT_REPOSITORY "https://git.cryptomilk.org/projects/cmocka.git"
GIT_TAG "origin/stable-1.1"
GIT_SHALLOW true
CONFIGURE_COMMAND cmake -DBUILD_SHARED_LIBS=OFF ../cmocka_ext/
BUILD_COMMAND cmake --build . --config Release
INSTALL_COMMAND ""

28
MCInst.c
View File

@ -1,6 +1,5 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <Availability.h>
#include <libkern/libkern.h>
@ -11,6 +10,7 @@
#include <string.h>
#include <assert.h>
#include "MCInstrDesc.h"
#include "MCInst.h"
#include "utils.h"
@ -105,12 +105,12 @@ bool MCOperand_isValid(const MCOperand *op)
bool MCOperand_isReg(const MCOperand *op)
{
return op->Kind == kRegister;
return op->Kind == kRegister || op->MachineOperandType == kRegister;
}
bool MCOperand_isImm(const MCOperand *op)
{
return op->Kind == kImmediate;
return op->Kind == kImmediate || op->MachineOperandType == kImmediate;
}
bool MCOperand_isFPImm(const MCOperand *op)
@ -224,16 +224,26 @@ bool MCInst_isPredicable(const MCInstrDesc *MIDesc)
/// Checks if tied operands exist in the instruction and sets
/// - The writeback flag in detail
/// - Saves the indices of the tied destination operands.
void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDesc)
void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDescTable, unsigned tbl_size)
{
const MCOperandInfo *OpInfo = InstDesc[MCInst_getOpcode(MI)].OpInfo;
unsigned short NumOps = InstDesc[MCInst_getOpcode(MI)].NumOperands;
const MCInstrDesc *InstDesc = NULL;
const MCOperandInfo *OpInfo = NULL;
unsigned short NumOps = 0;
if (MI->csh->arch == CS_ARCH_ARM) {
// Uses old (pre LLVM 18) indexing method.
InstDesc = &InstDescTable[MCInst_getOpcode(MI)];
OpInfo = InstDescTable[MCInst_getOpcode(MI)].OpInfo;
NumOps = InstDescTable[MCInst_getOpcode(MI)].NumOperands;
} else {
InstDesc = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size);
OpInfo = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size)->OpInfo;
NumOps = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size)->NumOperands;
}
unsigned i;
for (i = 0; i < NumOps; ++i) {
for (unsigned i = 0; i < NumOps; ++i) {
if (MCOperandInfo_isTiedToOp(&OpInfo[i])) {
int idx = MCOperandInfo_getOperandConstraint(
&InstDesc[MCInst_getOpcode(MI)], i,
InstDesc, i,
MCOI_TIED_TO);
if (idx == -1)

2
MCInst.h
View File

@ -159,7 +159,7 @@ void MCInst_addOperand2(MCInst *inst, MCOperand *Op);
bool MCInst_isPredicable(const MCInstrDesc *MIDesc);
void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDesc);
void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDescTable, unsigned tbl_size);
bool MCInst_opIsTied(const MCInst *MI, unsigned OpNum);

9
MCInstrDesc.c
View File

@ -38,4 +38,11 @@ int MCOperandInfo_getOperandConstraint(const MCInstrDesc *InstrDesc,
return (OpInfo.Constraints >> ValuePos) & 0xf;
}
return -1;
}
}
/// Returns the instruction description for the given MCInst opcode.
/// Function should be called like:
/// MCInstrDesc_get(MCInst_getOpcode(MI), ARCHInstDesc, ARR_SIZE(ARCHInstDesc));
const MCInstrDesc *MCInstrDesc_get(unsigned opcode, const MCInstrDesc *table, unsigned tbl_size) {
return &table[tbl_size - 1 - opcode];
}

4
MCInstrDesc.h
View File

@ -163,5 +163,9 @@ bool MCOperandInfo_isTiedToOp(const MCOperandInfo *m);
int MCOperandInfo_getOperandConstraint(const MCInstrDesc *OpInfo,
unsigned OpNum,
MCOI_OperandConstraint Constraint);
const MCInstrDesc *MCInstrDesc_get(unsigned opcode,
const MCInstrDesc *table,
unsigned tbl_size);
#endif

2
MCRegisterInfo.h
View File

@ -23,7 +23,7 @@
/// An unsigned integer type large enough to represent all physical registers,
/// but not necessarily virtual registers.
typedef uint16_t MCPhysReg;
typedef int16_t MCPhysReg;
typedef const MCPhysReg* iterator;
typedef struct MCRegisterClass2 {

1
Mapping.h
View File

@ -31,6 +31,7 @@ typedef struct insn_map {
union {
ppc_suppl_info ppc;
loongarch_suppl_info loongarch;
aarch64_suppl_info aarch64;
} suppl_info; // Supplementary information for each instruction.
#endif
} insn_map;

141
arch/AArch64/AArch64AddressingModes.h
View File

@ -3,8 +3,8 @@
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
@ -27,22 +27,25 @@
#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../MathExtras.h"
#include <assert.h>
#include "../../MathExtras.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
/// AArch64_AM - AArch64 Addressing Mode Stuff
// CS namespace begin: AArch64_AM
//===----------------------------------------------------------------------===//
// Shifts
//
typedef enum {
typedef enum ShiftExtendType {
AArch64_AM_InvalidShiftExtend = -1,
AArch64_AM_LSL = 0,
AArch64_AM_LSR,
@ -59,7 +62,7 @@ typedef enum {
AArch64_AM_SXTH,
AArch64_AM_SXTW,
AArch64_AM_SXTX,
} AArch64_AM_ShiftExtendType ;
} AArch64_AM_ShiftExtendType;
/// getShiftName - Get the string encoding for the shift type.
static inline const char *
@ -133,9 +136,8 @@ static inline unsigned AArch64_AM_getShiftValue(unsigned Imm)
/// {8-6} = shifter
/// {5-0} = imm
static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST,
unsigned Imm)
unsigned Imm)
{
unsigned STEnc = 0;
switch (ST) {
default:
@ -171,7 +173,6 @@ static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm)
/// getExtendType - Extract the extend type for operands of arithmetic ops.
static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm)
{
switch (Imm) {
default:
assert(0 && "Compiler bug!");
@ -209,7 +210,8 @@ AArch64_AM_getArithExtendType(unsigned Imm)
/// 101 ==> sxth
/// 110 ==> sxtw
/// 111 ==> sxtx
static inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET)
static inline unsigned
AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET)
{
switch (ET) {
default:
@ -249,7 +251,6 @@ static inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType E
static inline unsigned
AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm)
{
return (AArch64_AM_getExtendEncoding(ET) << 3) | (Imm & 0x7);
}
@ -281,7 +282,7 @@ AArch64_AM_getMemExtendType(unsigned Imm)
/// {3-1} = shifter
/// {0} = doshift
static inline unsigned AArch64_AM_getMemExtendImm(AArch64_AM_ShiftExtendType ET,
bool DoShift)
bool DoShift)
{
return (AArch64_AM_getExtendEncoding(ET) << 1) | (unsigned)DoShift;
}
@ -296,12 +297,12 @@ static inline uint64_t AArch64_AM_ror(uint64_t elt, unsigned size)
/// size. If so, return true with "encoding" set to the encoded value in
/// the form N:immr:imms.
static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm,
unsigned RegSize,
uint64_t *Encoding)
unsigned RegSize,
uint64_t *Encoding)
{
if (Imm == 0ULL || Imm == ~0ULL ||
(RegSize != 64 &&
(Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize)))))
(RegSize != 64 &&
(Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize)))))
return false;
// First, determine the element size.
@ -368,7 +369,7 @@ static inline bool AArch64_AM_isLogicalImmediate(uint64_t imm, unsigned regSize)
/// encodeLogicalImmediate - Return the encoded immediate value for a logical
/// immediate instruction of the given register size.
static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm,
unsigned regSize)
unsigned regSize)
{
uint64_t encoding = 0;
bool res = AArch64_AM_processLogicalImmediate(imm, regSize, &encoding);
@ -381,7 +382,7 @@ static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm,
/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
/// integer value it represents with regSize bits.
static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val,
unsigned regSize)
unsigned regSize)
{
// Extract the N, imms, and immr fields.
unsigned N = (val >> 12) & 1;
@ -389,6 +390,7 @@ static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val,
unsigned imms = val & 0x3f;
int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
assert(len >= 1);
unsigned size = (1 << len);
unsigned R = immr & (size - 1);
@ -410,7 +412,7 @@ static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val,
/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
/// is a valid encoding for an integer value with regSize bits.
static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val,
unsigned regSize)
unsigned regSize)
{
// Extract the N and imms fields needed for checking.
unsigned N = (val >> 12) & 1;
@ -419,7 +421,7 @@ static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val,
if (regSize == 32 && N != 0) // undefined logical immediate encoding
return false;
int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
if (len < 0) // undefined logical immediate encoding
if (len < 0) // undefined logical immediate encoding
return false;
unsigned size = (1 << len);
unsigned S = imms & (size - 1);
@ -461,7 +463,7 @@ static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xffffff00ffffff00ULL) == 0);
((Imm & 0xffffff00ffffff00ULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm)
@ -479,7 +481,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xffff00ffffff00ffULL) == 0);
((Imm & 0xffff00ffffff00ffULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm)
@ -497,7 +499,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xff00ffffff00ffffULL) == 0);
((Imm & 0xff00ffffff00ffffULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm)
@ -515,7 +517,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0x00ffffff00ffffffULL) == 0);
((Imm & 0x00ffffff00ffffffULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm)
@ -533,8 +535,8 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
(((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
((Imm & 0xff00ff00ff00ff00ULL) == 0);
(((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
((Imm & 0xff00ff00ff00ff00ULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm)
@ -552,8 +554,8 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
(((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
((Imm & 0x00ff00ff00ff00ffULL) == 0);
(((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
((Imm & 0x00ff00ff00ff00ffULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm)
@ -571,7 +573,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm)
@ -589,7 +591,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
}
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm)
@ -607,8 +609,8 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
((Imm >> 56) == (Imm & 0x000000ffULL));
((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
((Imm >> 56) == (Imm & 0x000000ffULL));
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm)
@ -629,6 +631,31 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType9(uint8_t Imm)
// cmode: 1110, op: 1
static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm)
{
#if defined(_MSC_VER) && _MSC_VER == 1937 && !defined(__clang__) && \
defined(_M_ARM64)
// The MSVC compiler 19.37 for ARM64 has an optimization bug that
// causes an incorrect behavior with the orignal version. Work around
// by using a slightly different variation.
// https://developercommunity.visualstudio.com/t/C-ARM64-compiler-optimization-bug/10481261
constexpr uint64_t Mask = 0xFFULL;
uint64_t ByteA = (Imm >> 56) & Mask;
uint64_t ByteB = (Imm >> 48) & Mask;
uint64_t ByteC = (Imm >> 40) & Mask;
uint64_t ByteD = (Imm >> 32) & Mask;
uint64_t ByteE = (Imm >> 24) & Mask;
uint64_t ByteF = (Imm >> 16) & Mask;
uint64_t ByteG = (Imm >> 8) & Mask;
uint64_t ByteH = Imm & Mask;
return (ByteA == 0ULL || ByteA == Mask) &&
(ByteB == 0ULL || ByteB == Mask) &&
(ByteC == 0ULL || ByteC == Mask) &&
(ByteD == 0ULL || ByteD == Mask) &&
(ByteE == 0ULL || ByteE == Mask) &&
(ByteF == 0ULL || ByteF == Mask) &&
(ByteG == 0ULL || ByteG == Mask) &&
(ByteH == 0ULL || ByteH == Mask);
#else
uint64_t ByteA = Imm & 0xff00000000000000ULL;
uint64_t ByteB = Imm & 0x00ff000000000000ULL;
uint64_t ByteC = Imm & 0x0000ff0000000000ULL;
@ -639,13 +666,14 @@ static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm)
uint64_t ByteH = Imm & 0x00000000000000ffULL;
return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
(ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
(ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
(ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
(ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
(ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
(ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
(ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
(ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
(ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
(ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
(ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
(ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
(ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
(ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
#endif
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm)
@ -704,8 +732,8 @@ static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm)
{
uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
(BString == 0x1f || BString == 0x20) &&
((Imm & 0x0007ffff0007ffffULL) == 0);
(BString == 0x1f || BString == 0x20) &&
((Imm & 0x0007ffff0007ffffULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm)
@ -766,7 +794,7 @@ static inline bool AArch64_AM_isAdvSIMDModImmType12(uint64_t Imm)
{
uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;
return ((BString == 0xff || BString == 0x100) &&
((Imm & 0x0000ffffffffffffULL) == 0));
((Imm & 0x0000ffffffffffffULL) == 0));
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm)
@ -822,33 +850,28 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm)
return (EncVal << 32) | EncVal;
}
/// Returns true if Imm is the concatenation of a repeating pattern of type T.
#define DEFINE_isSVEMaskOfIdenticalElements(T) \
static inline bool CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, T)(int64_t Imm) \
{ \
#define DEFINE_isSVEMaskOfIdenticalElements(T) \
static inline bool CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, \
T)(int64_t Imm) \
{ \
union { \
int64_t In; \
T Out[sizeof(int64_t) / sizeof(T)]; \
} U_Parts; \
U_Parts.In = Imm; \
T *Parts = U_Parts.Out; \
for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \
for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \
if (Parts[i] != Parts[0]) \
return false; \
} \
return true; \
return true; \
}
DEFINE_isSVEMaskOfIdenticalElements(int8_t);
DEFINE_isSVEMaskOfIdenticalElements(int16_t);
DEFINE_isSVEMaskOfIdenticalElements(int32_t);
DEFINE_isSVEMaskOfIdenticalElements(int64_t);
static inline bool AArch64_AM_isSVEMaskOfIdenticalElements64(int64_t Imm)
{
return true;
}
static inline bool isSVECpyImm8(int64_t Imm)
{
bool IsImm8 = (int8_t)Imm == Imm;
@ -907,13 +930,13 @@ AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm)
int8_t *B = U_B.Out;
if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int32_t)(Imm) &&
isSVECpyImm32(S[0]))
isSVECpyImm32(S[0]))
return false;
if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int16_t)(Imm) &&
isSVECpyImm16(H[0]))
isSVECpyImm16(H[0]))
return false;
if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int8_t)(Imm) &&
isSVECpyImm8(B[0]))
isSVECpyImm8(B[0]))
return false;
return AArch64_AM_isLogicalImmediate(Imm, 64);
}
@ -928,7 +951,7 @@ inline static bool AArch64_AM_isAnyMOVZMovAlias(uint64_t Value, int RegWidth)
}
inline static bool AArch64_AM_isMOVZMovAlias(uint64_t Value, int Shift,
int RegWidth)
int RegWidth)
{
if (RegWidth == 32)
Value &= 0xffffffffULL;
@ -941,7 +964,7 @@ inline static bool AArch64_AM_isMOVZMovAlias(uint64_t Value, int Shift,
}
inline static bool AArch64_AM_isMOVNMovAlias(uint64_t Value, int Shift,
int RegWidth)
int RegWidth)
{
// MOVZ takes precedence over MOVN.
if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth))
@ -967,6 +990,8 @@ inline static bool AArch64_AM_isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
return AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth);
}
// CS namespace end: AArch64_AM
// end namespace AArch64_AM
// end namespace llvm

10
arch/AArch64/AArch64BaseInfo.c
View File

@ -126,14 +126,16 @@ static void utostr(uint64_t X, bool isNeg, char *result)
char *BufPtr = Buffer + 21;
Buffer[21] = '\0';
if (X == 0) *--BufPtr = '0'; // Handle special case...
if (X == 0)
*--BufPtr = '0'; // Handle special case...
while (X) {
*--BufPtr = X % 10 + '0';
X /= 10;
}
if (isNeg) *--BufPtr = '-'; // Add negative sign...
if (isNeg)
*--BufPtr = '-'; // Add negative sign...
// suppose that result is big enough
strncpy(result, BufPtr, sizeof(Buffer));
@ -158,14 +160,16 @@ void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result)
utostr(CRm, false, CRmStr);
dummy = cs_snprintf(result, AARCH64_GRS_LEN, "s%s_%s_c%s_c%s_%s",
Op0Str, Op1Str, CRnStr, CRmStr, Op2Str);
Op0Str, Op1Str, CRnStr, CRmStr, Op2Str);
(void)dummy;
}
#define GET_TLBITable_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_TLBITable_IMPL
#define GET_SVCR_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_SVCR_IMPL

144
arch/AArch64/AArch64BaseInfo.h
View File

@ -55,7 +55,7 @@
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
inline static unsigned getWRegFromXReg(unsigned Reg)
static inline unsigned getWRegFromXReg(unsigned Reg)
{
switch (Reg) {
case AArch64_X0:
@ -129,7 +129,7 @@ inline static unsigned getWRegFromXReg(unsigned Reg)
return Reg;
}
inline static unsigned getXRegFromWReg(unsigned Reg)
static inline unsigned getXRegFromWReg(unsigned Reg)
{
switch (Reg) {
case AArch64_W0:
@ -203,7 +203,7 @@ inline static unsigned getXRegFromWReg(unsigned Reg)
return Reg;
}
inline static unsigned getXRegFromXRegTuple(unsigned RegTuple)
static inline unsigned getXRegFromXRegTuple(unsigned RegTuple)
{
switch (RegTuple) {
case AArch64_X0_X1_X2_X3_X4_X5_X6_X7:
@ -459,7 +459,10 @@ static inline bool atomicBarrierDroppedOnZero(unsigned Opcode)
return false;
}
// AArch64CC namespace moved to main header aarch64.h
// MOVE-NOTICE: AArch64CC_CondCode : moved to aarch64.h
// MOVE-NOTICE: AArch64CC_getCondCodeName : moved to aarch64.h
// MOVE-NOTICE: AArch64CC_getInvertedCondCode : moved to aarch64.h
// MOVE-NOTICE: AArch64CC_getNZCVToSatisfyCondCode : moved to aarch64.h
typedef struct SysAlias {
const char *Name;
@ -489,6 +492,7 @@ typedef struct SysAliasImm {
#define AArch64SVCR_SVCR SysAlias
#define GET_SVCR_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64SVCR
@ -498,6 +502,7 @@ typedef struct SysAliasImm {
#define AArch64AT_AT SysAlias
#define GET_AT_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64AT
@ -507,6 +512,7 @@ typedef struct SysAliasImm {
#define AArch64DB_DB SysAlias
#define GET_DB_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64DB
@ -516,6 +522,7 @@ typedef struct SysAliasImm {
#define AArch64DBnXS_DBnXS SysAliasImm
#define GET_DBNXS_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64DBnXS
@ -525,6 +532,7 @@ typedef struct SysAliasImm {
#define AArch64DC_DC SysAlias
#define GET_DC_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64DC
@ -534,6 +542,7 @@ typedef struct SysAliasImm {
#define AArch64IC_IC SysAliasReg
#define GET_IC_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64IC
@ -543,6 +552,7 @@ typedef struct SysAliasImm {
#define AArch64ISB_ISB SysAlias
#define GET_ISB_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64ISB
@ -552,6 +562,7 @@ typedef struct SysAliasImm {
#define AArch64TSB_TSB SysAlias
#define GET_TSB_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64TSB
@ -561,6 +572,7 @@ typedef struct SysAliasImm {
#define AArch64PRFM_PRFM SysAlias
#define GET_PRFM_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64PRFM
@ -570,6 +582,7 @@ typedef struct SysAliasImm {
#define AArch64SVEPRFM_SVEPRFM SysAlias
#define GET_SVEPRFM_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64SVEPRFM
@ -579,6 +592,7 @@ typedef struct SysAliasImm {
#define AArch64RPRFM_RPRFM SysAlias
#define GET_RPRFM_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64RPRFM
@ -592,6 +606,7 @@ typedef struct SVEPREDPAT {
} AArch64SVEPredPattern_SVEPREDPAT;
#define GET_SVEPREDPAT_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64SVEPredPattern
@ -605,11 +620,72 @@ typedef struct SVEVECLENSPECIFIER {
} AArch64SVEVecLenSpecifier_SVEVECLENSPECIFIER;
#define GET_SVEVECLENSPECIFIER_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64SVEVecLenSpecifier
// namespace AArch64SVEVecLenSpecifier
/// Return the number of active elements for VL1 to VL256 predicate pattern,
/// zero for all other patterns.
static inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
{
switch (Pattern) {
default:
return 0;
case AARCH64_SVEPREDPAT_VL1:
case AARCH64_SVEPREDPAT_VL2:
case AARCH64_SVEPREDPAT_VL3:
case AARCH64_SVEPREDPAT_VL4:
case AARCH64_SVEPREDPAT_VL5:
case AARCH64_SVEPREDPAT_VL6:
case AARCH64_SVEPREDPAT_VL7:
case AARCH64_SVEPREDPAT_VL8:
return Pattern;
case AARCH64_SVEPREDPAT_VL16:
return 16;
case AARCH64_SVEPREDPAT_VL32:
return 32;
case AARCH64_SVEPREDPAT_VL64:
return 64;
case AARCH64_SVEPREDPAT_VL128:
return 128;
case AARCH64_SVEPREDPAT_VL256:
return 256;
}
}
/// Return specific VL predicate pattern based on the number of elements.
static inline unsigned getSVEPredPatternFromNumElements(unsigned MinNumElts)
{
switch (MinNumElts) {
default:
return 0;
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case 8:
return MinNumElts;
case 16:
return AARCH64_SVEPREDPAT_VL16;
case 32:
return AARCH64_SVEPREDPAT_VL32;
case 64:
return AARCH64_SVEPREDPAT_VL64;
case 128:
return AARCH64_SVEPREDPAT_VL128;
case 256:
return AARCH64_SVEPREDPAT_VL256;
}
}
// CS namespace begin: AArch64ExactFPImm
typedef struct ExactFPImm {
const char *Name;
aarch64_sysop_imm SysImm;
@ -618,13 +694,14 @@ typedef struct ExactFPImm {
} AArch64ExactFPImm_ExactFPImm;
enum {
AArch64ExactFPImm_half = 0,
AArch64ExactFPImm_one = 1,
AArch64ExactFPImm_two = 2,
AArch64ExactFPImm_zero = 3,
AArch64ExactFPImm_half = 1,
AArch64ExactFPImm_one = 2,
AArch64ExactFPImm_two = 3,
AArch64ExactFPImm_zero = 0,
};
#define GET_EXACTFPIMM_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64ExactFPImm
@ -634,11 +711,13 @@ enum {
#define AArch64PState_PStateImm0_15 SysAlias
#define GET_PSTATEIMM0_15_DECL
#include "AArch64GenSystemOperands.inc"
#define AArch64PState_PStateImm0_1 SysAlias
#define GET_PSTATEIMM0_1_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64PState
@ -648,6 +727,7 @@ enum {
#define AArch64PSBHint_PSB SysAlias
#define GET_PSB_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64PSBHint
@ -657,6 +737,7 @@ enum {
#define AArch64BTIHint_BTI SysAlias
#define GET_BTI_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64BTIHint
@ -686,7 +767,9 @@ typedef enum ShiftExtSpecifiers {
// CS namespace begin: AArch64Layout
// Vector layout move to aarch64.h
// MOVE_NOTICE: AArch64Layout_VectorLayout - move to aarch64.h
// MOVE_NOTICE: AArch64VectorLayoutToString - move to aarch64.h
// MOVE_NOTICE: AArch64StringToVectorLayout - move to aarch64.h
// CS namespace end: AArch64Layout
@ -704,10 +787,12 @@ typedef struct SysReg {
} AArch64SysReg_SysReg;
#define GET_SYSREG_DECL
#include "AArch64GenSystemOperands.inc"
const AArch64SysReg_SysReg *AArch64SysReg_lookupSysRegByName(const char *Name);
const AArch64SysReg_SysReg *AArch64SysReg_lookupSysRegByEncoding(uint16_t Encoding);
const AArch64SysReg_SysReg *
AArch64SysReg_lookupSysRegByEncoding(uint16_t Encoding);
#define AARCH64_GRS_LEN 128
void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result);
@ -718,6 +803,7 @@ void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result);
#define AArch64TLBI_TLBI SysAliasReg
#define GET_TLBITable_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64TLBI
@ -727,6 +813,7 @@ void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result);
#define AArch64PRCTX_PRCTX SysAliasReg
#define GET_PRCTX_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64PRCTX
@ -815,20 +902,23 @@ typedef enum TOF {
/// an LDG instruction to obtain the tag value.
AArch64II_MO_TAGGED = 0x400,
/// MO_DLLIMPORTAUX - Symbol refers to "auxiliary" import stub. On
/// Arm64EC, there are two kinds of import stubs used for DLL import of
/// functions: MO_DLLIMPORT refers to natively callable Arm64 code, and
/// MO_DLLIMPORTAUX refers to the original address which can be compared
/// for equality.
AArch64II_MO_DLLIMPORTAUX = 0x800,
/// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version
/// of a symbol, not the original. For dllimport symbols, this means it
/// uses "__imp_aux". For other symbols, this means it uses the mangled
/// ("#" prefix for C) name.
AArch64II_MO_ARM64EC_CALLMANGLE = 0x800,
} AArch64II_TOF;
// CS namespace end: AArch64II
// end namespace AArch64II
//===----------------------------------------------------------------------===//
// v8.3a Pointer Authentication
//
// CS namespace begin: AArch64PACKey
typedef enum ID {
AArch64PACKey_IA = 0,
AArch64PACKey_IB = 1,
@ -837,10 +927,12 @@ typedef enum ID {
AArch64PACKey_LAST = AArch64PACKey_DB
} AArch64PACKey_ID;
// CS namespace end: AArch64PACKey
// namespace AArch64PACKey
/// Return 2-letter identifier string for numeric key ID.
inline static const char *AArch64PACKeyIDToString(AArch64PACKey_ID KeyID)
static inline const char *AArch64PACKeyIDToString(AArch64PACKey_ID KeyID)
{
switch (KeyID) {
case AArch64PACKey_IA:
@ -856,8 +948,7 @@ inline static const char *AArch64PACKeyIDToString(AArch64PACKey_ID KeyID)
}
/// Return numeric key ID for 2-letter identifier string.
inline static AArch64PACKey_ID
AArch64StringToPACKeyID(const char *Name)
static inline AArch64PACKey_ID AArch64StringToPACKeyID(const char *Name)
{
if (strcmp(Name, "ia") == 0)
return AArch64PACKey_IA;
@ -871,6 +962,21 @@ AArch64StringToPACKeyID(const char *Name)
return AArch64PACKey_LAST;
}
// CS namespace begin: AArch64
// The number of bits in a SVE register is architecturally defined
// to be a multiple of this value. If <M x t> has this number of bits,
// a <n x M x t> vector can be stored in a SVE register without any
// redundant bits. If <M x t> has this number of bits divided by P,
// a <n x M x t> vector is stored in a SVE register by placing index i
// in index i*P of a <n x (M*P) x t> vector. The other elements of the
// <n x (M*P) x t> vector (such as index 1) are undefined.
static const unsigned SVEBitsPerBlock = 128;
static const unsigned SVEMaxBitsPerVector = 2048;
// CS namespace end: AArch64
// end namespace AArch64
// end namespace llvm

946
arch/AArch64/AArch64Disassembler.c
View File

File diff suppressed because it is too large Load Diff

36162
arch/AArch64/AArch64GenAsmWriter.inc
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File diff suppressed because it is too large Load Diff

719
arch/AArch64/AArch64GenCSAliasMnemMap.inc
View File

@ -1,6 +1,6 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
@ -11,358 +11,365 @@
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ AArch64_INS_ALIAS_LDAPUR, "ldapur" },
{ AArch64_INS_ALIAS_STLLRB, "stllrb" },
{ AArch64_INS_ALIAS_STLLRH, "stllrh" },
{ AArch64_INS_ALIAS_STLLR, "stllr" },
{ AArch64_INS_ALIAS_STLRB, "stlrb" },
{ AArch64_INS_ALIAS_STLRH, "stlrh" },
{ AArch64_INS_ALIAS_STLR, "stlr" },
{ AArch64_INS_ALIAS_STLUR, "stlur" },
{ AArch64_INS_ALIAS_EOR, "eor" },
{ AArch64_INS_ALIAS_AND, "and" },
{ AArch64_INS_ALIAS_MOV, "mov" },
{ AArch64_INS_ALIAS_LD1B, "ld1b" },
{ AArch64_INS_ALIAS_LD1SW, "ld1sw" },
{ AArch64_INS_ALIAS_LD1H, "ld1h" },
{ AArch64_INS_ALIAS_LD1SH, "ld1sh" },
{ AArch64_INS_ALIAS_LD1W, "ld1w" },
{ AArch64_INS_ALIAS_LD1SB, "ld1sb" },
{ AArch64_INS_ALIAS_LD1D, "ld1d" },
{ AArch64_INS_ALIAS_LD1RB, "ld1rb" },
{ AArch64_INS_ALIAS_LD1RSW, "ld1rsw" },
{ AArch64_INS_ALIAS_LD1RH, "ld1rh" },
{ AArch64_INS_ALIAS_LD1RSH, "ld1rsh" },
{ AArch64_INS_ALIAS_LD1RW, "ld1rw" },
{ AArch64_INS_ALIAS_LD1RSB, "ld1rsb" },
{ AArch64_INS_ALIAS_LD1RD, "ld1rd" },
{ AArch64_INS_ALIAS_LD1RQH, "ld1rqh" },
{ AArch64_INS_ALIAS_LD1RQW, "ld1rqw" },
{ AArch64_INS_ALIAS_LD1RQD, "ld1rqd" },
{ AArch64_INS_ALIAS_LDNF1B, "ldnf1b" },
{ AArch64_INS_ALIAS_LDNF1SW, "ldnf1sw" },
{ AArch64_INS_ALIAS_LDNF1H, "ldnf1h" },
{ AArch64_INS_ALIAS_LDNF1SH, "ldnf1sh" },
{ AArch64_INS_ALIAS_LDNF1W, "ldnf1w" },
{ AArch64_INS_ALIAS_LDNF1SB, "ldnf1sb" },
{ AArch64_INS_ALIAS_LDNF1D, "ldnf1d" },
{ AArch64_INS_ALIAS_LDFF1B, "ldff1b" },
{ AArch64_INS_ALIAS_LDFF1SW, "ldff1sw" },
{ AArch64_INS_ALIAS_LDFF1H, "ldff1h" },
{ AArch64_INS_ALIAS_LDFF1SH, "ldff1sh" },
{ AArch64_INS_ALIAS_LDFF1W, "ldff1w" },
{ AArch64_INS_ALIAS_LDFF1SB, "ldff1sb" },
{ AArch64_INS_ALIAS_LDFF1D, "ldff1d" },
{ AArch64_INS_ALIAS_LD3B, "ld3b" },
{ AArch64_INS_ALIAS_LD4B, "ld4b" },
{ AArch64_INS_ALIAS_LD2H, "ld2h" },
{ AArch64_INS_ALIAS_LD3H, "ld3h" },
{ AArch64_INS_ALIAS_LD4H, "ld4h" },
{ AArch64_INS_ALIAS_LD2W, "ld2w" },
{ AArch64_INS_ALIAS_LD3W, "ld3w" },
{ AArch64_INS_ALIAS_LD4W, "ld4w" },
{ AArch64_INS_ALIAS_LD2D, "ld2d" },
{ AArch64_INS_ALIAS_LD3D, "ld3d" },
{ AArch64_INS_ALIAS_LD4D, "ld4d" },
{ AArch64_INS_ALIAS_LD2Q, "ld2q" },
{ AArch64_INS_ALIAS_LD3Q, "ld3q" },
{ AArch64_INS_ALIAS_LD4Q, "ld4q" },
{ AArch64_INS_ALIAS_LDNT1H, "ldnt1h" },
{ AArch64_INS_ALIAS_LDNT1W, "ldnt1w" },
{ AArch64_INS_ALIAS_LDNT1D, "ldnt1d" },
{ AArch64_INS_ALIAS_ST1B, "st1b" },
{ AArch64_INS_ALIAS_ST1H, "st1h" },
{ AArch64_INS_ALIAS_ST1W, "st1w" },
{ AArch64_INS_ALIAS_ST1D, "st1d" },
{ AArch64_INS_ALIAS_ST3B, "st3b" },
{ AArch64_INS_ALIAS_ST4B, "st4b" },
{ AArch64_INS_ALIAS_ST2H, "st2h" },
{ AArch64_INS_ALIAS_ST3H, "st3h" },
{ AArch64_INS_ALIAS_ST4H, "st4h" },
{ AArch64_INS_ALIAS_ST2W, "st2w" },
{ AArch64_INS_ALIAS_ST3W, "st3w" },
{ AArch64_INS_ALIAS_ST4W, "st4w" },
{ AArch64_INS_ALIAS_ST2D, "st2d" },
{ AArch64_INS_ALIAS_ST3D, "st3d" },
{ AArch64_INS_ALIAS_ST4D, "st4d" },
{ AArch64_INS_ALIAS_ST3Q, "st3q" },
{ AArch64_INS_ALIAS_ST4Q, "st4q" },
{ AArch64_INS_ALIAS_STNT1H, "stnt1h" },
{ AArch64_INS_ALIAS_STNT1W, "stnt1w" },
{ AArch64_INS_ALIAS_STNT1D, "stnt1d" },
{ AArch64_INS_ALIAS_PRFH, "prfh" },
{ AArch64_INS_ALIAS_PRFW, "prfw" },
{ AArch64_INS_ALIAS_PRFD, "prfd" },
{ AArch64_INS_ALIAS_CNTH, "cnth" },
{ AArch64_INS_ALIAS_CNTW, "cntw" },
{ AArch64_INS_ALIAS_CNTD, "cntd" },
{ AArch64_INS_ALIAS_DECB, "decb" },
{ AArch64_INS_ALIAS_INCH, "inch" },
{ AArch64_INS_ALIAS_DECH, "dech" },
{ AArch64_INS_ALIAS_INCW, "incw" },
{ AArch64_INS_ALIAS_DECW, "decw" },
{ AArch64_INS_ALIAS_INCD, "incd" },
{ AArch64_INS_ALIAS_DECD, "decd" },
{ AArch64_INS_ALIAS_SQDECB, "sqdecb" },
{ AArch64_INS_ALIAS_UQDECB, "uqdecb" },
{ AArch64_INS_ALIAS_UQINCB, "uqincb" },
{ AArch64_INS_ALIAS_SQINCH, "sqinch" },
{ AArch64_INS_ALIAS_UQINCH, "uqinch" },
{ AArch64_INS_ALIAS_SQDECH, "sqdech" },
{ AArch64_INS_ALIAS_UQDECH, "uqdech" },
{ AArch64_INS_ALIAS_SQINCW, "sqincw" },
{ AArch64_INS_ALIAS_UQINCW, "uqincw" },
{ AArch64_INS_ALIAS_SQDECW, "sqdecw" },
{ AArch64_INS_ALIAS_UQDECW, "uqdecw" },
{ AArch64_INS_ALIAS_SQINCD, "sqincd" },
{ AArch64_INS_ALIAS_UQINCD, "uqincd" },
{ AArch64_INS_ALIAS_SQDECD, "sqdecd" },
{ AArch64_INS_ALIAS_UQDECD, "uqdecd" },
{ AArch64_INS_ALIAS_MOVS, "movs" },
{ AArch64_INS_ALIAS_NOT, "not" },
{ AArch64_INS_ALIAS_NOTS, "nots" },
{ AArch64_INS_ALIAS_LD1ROH, "ld1roh" },
{ AArch64_INS_ALIAS_LD1ROW, "ld1row" },
{ AArch64_INS_ALIAS_LD1ROD, "ld1rod" },
{ AArch64_INS_ALIAS_BCAX, "bcax" },
{ AArch64_INS_ALIAS_BSL, "bsl" },
{ AArch64_INS_ALIAS_BSL1N, "bsl1n" },
{ AArch64_INS_ALIAS_BSL2N, "bsl2n" },
{ AArch64_INS_ALIAS_NBSL, "nbsl" },
{ AArch64_INS_ALIAS_LDNT1B, "ldnt1b" },
{ AArch64_INS_ALIAS_LDNT1SH, "ldnt1sh" },
{ AArch64_INS_ALIAS_LDNT1SW, "ldnt1sw" },
{ AArch64_INS_ALIAS_STNT1B, "stnt1b" },
{ AArch64_INS_ALIAS_LD1Q, "ld1q" },
{ AArch64_INS_ALIAS_ST1Q, "st1q" },
{ AArch64_INS_ALIAS_SMSTART, "smstart" },
{ AArch64_INS_ALIAS_SMSTOP, "smstop" },
{ AArch64_INS_ALIAS_LDRAA, "ldraa" },
{ AArch64_INS_ALIAS_ADD, "add" },
{ AArch64_INS_ALIAS_CMN, "cmn" },
{ AArch64_INS_ALIAS_ADDS, "adds" },
{ AArch64_INS_ALIAS_ANDS, "ands" },
{ AArch64_INS_ALIAS_LDR, "ldr" },
{ AArch64_INS_ALIAS_STR, "str" },
{ AArch64_INS_ALIAS_LDRB, "ldrb" },
{ AArch64_INS_ALIAS_STRB, "strb" },
{ AArch64_INS_ALIAS_LDRH, "ldrh" },
{ AArch64_INS_ALIAS_STRH, "strh" },
{ AArch64_INS_ALIAS_PRFM, "prfm" },
{ AArch64_INS_ALIAS_LDAPURB, "ldapurb" },
{ AArch64_INS_ALIAS_STLURB, "stlurb" },
{ AArch64_INS_ALIAS_LDUR, "ldur" },
{ AArch64_INS_ALIAS_STUR, "stur" },
{ AArch64_INS_ALIAS_PRFUM, "prfum" },
{ AArch64_INS_ALIAS_LDTR, "ldtr" },
{ AArch64_INS_ALIAS_STTR, "sttr" },
{ AArch64_INS_ALIAS_LDP, "ldp" },
{ AArch64_INS_ALIAS_STGP, "stgp" },
{ AArch64_INS_ALIAS_LDNP, "ldnp" },
{ AArch64_INS_ALIAS_STNP, "stnp" },
{ AArch64_INS_ALIAS_STG, "stg" },
{ AArch64_INS_ALIAS_LD1, "ld1" },
{ AArch64_INS_ALIAS_LD1R, "ld1r" },
{ AArch64_INS_ALIAS_STADDLB, "staddlb" },
{ AArch64_INS_ALIAS_STADDLH, "staddlh" },
{ AArch64_INS_ALIAS_STADDL, "staddl" },
{ AArch64_INS_ALIAS_STADDB, "staddb" },
{ AArch64_INS_ALIAS_STADDH, "staddh" },
{ AArch64_INS_ALIAS_STADD, "stadd" },
{ AArch64_INS_ALIAS_PTRUE, "ptrue" },
{ AArch64_INS_ALIAS_PTRUES, "ptrues" },
{ AArch64_INS_ALIAS_CNTB, "cntb" },
{ AArch64_INS_ALIAS_INCB, "incb" },
{ AArch64_INS_ALIAS_SQINCB, "sqincb" },
{ AArch64_INS_ALIAS_ORR, "orr" },
{ AArch64_INS_ALIAS_DUPM, "dupm" },
{ AArch64_INS_ALIAS_FMOV, "fmov" },
{ AArch64_INS_ALIAS_EOR3, "eor3" },
{ AArch64_INS_ALIAS_ST2B, "st2b" },
{ AArch64_INS_ALIAS_ST2Q, "st2q" },
{ AArch64_INS_ALIAS_LD1RQB, "ld1rqb" },
{ AArch64_INS_ALIAS_LD2B, "ld2b" },
{ AArch64_INS_ALIAS_PRFB, "prfb" },
{ AArch64_INS_ALIAS_LDNT1SB, "ldnt1sb" },
{ AArch64_INS_ALIAS_LD1ROB, "ld1rob" },
{ AArch64_INS_ALIAS_PMOV, "pmov" },
{ AArch64_INS_ALIAS_ZERO, "zero" },
{ AArch64_INS_ALIAS_NOP, "nop" },
{ AArch64_INS_ALIAS_YIELD, "yield" },
{ AArch64_INS_ALIAS_WFE, "wfe" },
{ AArch64_INS_ALIAS_WFI, "wfi" },
{ AArch64_INS_ALIAS_SEV, "sev" },
{ AArch64_INS_ALIAS_SEVL, "sevl" },
{ AArch64_INS_ALIAS_DGH, "dgh" },
{ AArch64_INS_ALIAS_ESB, "esb" },
{ AArch64_INS_ALIAS_CSDB, "csdb" },
{ AArch64_INS_ALIAS_BTI, "bti" },
{ AArch64_INS_ALIAS_PSB, "psb" },
{ AArch64_INS_ALIAS_PACIAZ, "paciaz" },
{ AArch64_INS_ALIAS_PACIBZ, "pacibz" },
{ AArch64_INS_ALIAS_AUTIAZ, "autiaz" },
{ AArch64_INS_ALIAS_AUTIBZ, "autibz" },
{ AArch64_INS_ALIAS_PACIASP, "paciasp" },
{ AArch64_INS_ALIAS_PACIBSP, "pacibsp" },
{ AArch64_INS_ALIAS_AUTIASP, "autiasp" },
{ AArch64_INS_ALIAS_AUTIBSP, "autibsp" },
{ AArch64_INS_ALIAS_PACIA1716, "pacia1716" },
{ AArch64_INS_ALIAS_PACIB1716, "pacib1716" },
{ AArch64_INS_ALIAS_AUTIA1716, "autia1716" },
{ AArch64_INS_ALIAS_AUTIB1716, "autib1716" },
{ AArch64_INS_ALIAS_XPACLRI, "xpaclri" },
{ AArch64_INS_ALIAS_LDRAB, "ldrab" },
{ AArch64_INS_ALIAS_CLREX, "clrex" },
{ AArch64_INS_ALIAS_ISB, "isb" },
{ AArch64_INS_ALIAS_SSBB, "ssbb" },
{ AArch64_INS_ALIAS_PSSBB, "pssbb" },
{ AArch64_INS_ALIAS_DFB, "dfb" },
{ AArch64_INS_ALIAS_SYS, "sys" },
{ AArch64_INS_ALIAS_MOVN, "movn" },
{ AArch64_INS_ALIAS_MOVZ, "movz" },
{ AArch64_INS_ALIAS_NGC, "ngc" },
{ AArch64_INS_ALIAS_NGCS, "ngcs" },
{ AArch64_INS_ALIAS_SUB, "sub" },
{ AArch64_INS_ALIAS_CMP, "cmp" },
{ AArch64_INS_ALIAS_SUBS, "subs" },
{ AArch64_INS_ALIAS_NEG, "neg" },
{ AArch64_INS_ALIAS_NEGS, "negs" },
{ AArch64_INS_ALIAS_MUL, "mul" },
{ AArch64_INS_ALIAS_MNEG, "mneg" },
{ AArch64_INS_ALIAS_SMULL, "smull" },
{ AArch64_INS_ALIAS_SMNEGL, "smnegl" },
{ AArch64_INS_ALIAS_UMULL, "umull" },
{ AArch64_INS_ALIAS_UMNEGL, "umnegl" },
{ AArch64_INS_ALIAS_STCLRLB, "stclrlb" },
{ AArch64_INS_ALIAS_STCLRLH, "stclrlh" },
{ AArch64_INS_ALIAS_STCLRL, "stclrl" },
{ AArch64_INS_ALIAS_STCLRB, "stclrb" },
{ AArch64_INS_ALIAS_STCLRH, "stclrh" },
{ AArch64_INS_ALIAS_STCLR, "stclr" },
{ AArch64_INS_ALIAS_STEORLB, "steorlb" },
{ AArch64_INS_ALIAS_STEORLH, "steorlh" },
{ AArch64_INS_ALIAS_STEORL, "steorl" },
{ AArch64_INS_ALIAS_STEORB, "steorb" },
{ AArch64_INS_ALIAS_STEORH, "steorh" },
{ AArch64_INS_ALIAS_STEOR, "steor" },
{ AArch64_INS_ALIAS_STSETLB, "stsetlb" },
{ AArch64_INS_ALIAS_STSETLH, "stsetlh" },
{ AArch64_INS_ALIAS_STSETL, "stsetl" },
{ AArch64_INS_ALIAS_STSETB, "stsetb" },
{ AArch64_INS_ALIAS_STSETH, "stseth" },
{ AArch64_INS_ALIAS_STSET, "stset" },
{ AArch64_INS_ALIAS_STSMAXLB, "stsmaxlb" },
{ AArch64_INS_ALIAS_STSMAXLH, "stsmaxlh" },
{ AArch64_INS_ALIAS_STSMAXL, "stsmaxl" },
{ AArch64_INS_ALIAS_STSMAXB, "stsmaxb" },
{ AArch64_INS_ALIAS_STSMAXH, "stsmaxh" },
{ AArch64_INS_ALIAS_STSMAX, "stsmax" },
{ AArch64_INS_ALIAS_STSMINLB, "stsminlb" },
{ AArch64_INS_ALIAS_STSMINLH, "stsminlh" },
{ AArch64_INS_ALIAS_STSMINL, "stsminl" },
{ AArch64_INS_ALIAS_STSMINB, "stsminb" },
{ AArch64_INS_ALIAS_STSMINH, "stsminh" },
{ AArch64_INS_ALIAS_STSMIN, "stsmin" },
{ AArch64_INS_ALIAS_STUMAXLB, "stumaxlb" },
{ AArch64_INS_ALIAS_STUMAXLH, "stumaxlh" },
{ AArch64_INS_ALIAS_STUMAXL, "stumaxl" },
{ AArch64_INS_ALIAS_STUMAXB, "stumaxb" },
{ AArch64_INS_ALIAS_STUMAXH, "stumaxh" },
{ AArch64_INS_ALIAS_STUMAX, "stumax" },
{ AArch64_INS_ALIAS_STUMINLB, "stuminlb" },
{ AArch64_INS_ALIAS_STUMINLH, "stuminlh" },
{ AArch64_INS_ALIAS_STUMINL, "stuminl" },
{ AArch64_INS_ALIAS_STUMINB, "stuminb" },
{ AArch64_INS_ALIAS_STUMINH, "stuminh" },
{ AArch64_INS_ALIAS_STUMIN, "stumin" },
{ AArch64_INS_ALIAS_IRG, "irg" },
{ AArch64_INS_ALIAS_LDG, "ldg" },
{ AArch64_INS_ALIAS_STZG, "stzg" },
{ AArch64_INS_ALIAS_ST2G, "st2g" },
{ AArch64_INS_ALIAS_STZ2G, "stz2g" },
{ AArch64_INS_ALIAS_BICS, "bics" },
{ AArch64_INS_ALIAS_BIC, "bic" },
{ AArch64_INS_ALIAS_EON, "eon" },
{ AArch64_INS_ALIAS_ORN, "orn" },
{ AArch64_INS_ALIAS_MVN, "mvn" },
{ AArch64_INS_ALIAS_TST, "tst" },
{ AArch64_INS_ALIAS_ROR, "ror" },
{ AArch64_INS_ALIAS_ASR, "asr" },
{ AArch64_INS_ALIAS_SXTB, "sxtb" },
{ AArch64_INS_ALIAS_SXTH, "sxth" },
{ AArch64_INS_ALIAS_SXTW, "sxtw" },
{ AArch64_INS_ALIAS_LSR, "lsr" },
{ AArch64_INS_ALIAS_UXTB, "uxtb" },
{ AArch64_INS_ALIAS_UXTH, "uxth" },
{ AArch64_INS_ALIAS_UXTW, "uxtw" },
{ AArch64_INS_ALIAS_CSET, "cset" },
{ AArch64_INS_ALIAS_CSETM, "csetm" },
{ AArch64_INS_ALIAS_CINC, "cinc" },
{ AArch64_INS_ALIAS_CINV, "cinv" },
{ AArch64_INS_ALIAS_CNEG, "cneg" },
{ AArch64_INS_ALIAS_RET, "ret" },
{ AArch64_INS_ALIAS_DCPS1, "dcps1" },
{ AArch64_INS_ALIAS_DCPS2, "dcps2" },
{ AArch64_INS_ALIAS_DCPS3, "dcps3" },
{ AArch64_INS_ALIAS_LDPSW, "ldpsw" },
{ AArch64_INS_ALIAS_LDRSH, "ldrsh" },
{ AArch64_INS_ALIAS_LDRSB, "ldrsb" },
{ AArch64_INS_ALIAS_LDRSW, "ldrsw" },
{ AArch64_INS_ALIAS_LDURH, "ldurh" },
{ AArch64_INS_ALIAS_LDURB, "ldurb" },
{ AArch64_INS_ALIAS_LDURSH, "ldursh" },
{ AArch64_INS_ALIAS_LDURSB, "ldursb" },
{ AArch64_INS_ALIAS_LDURSW, "ldursw" },
{ AArch64_INS_ALIAS_LDTRH, "ldtrh" },
{ AArch64_INS_ALIAS_LDTRB, "ldtrb" },
{ AArch64_INS_ALIAS_LDTRSH, "ldtrsh" },
{ AArch64_INS_ALIAS_LDTRSB, "ldtrsb" },
{ AArch64_INS_ALIAS_LDTRSW, "ldtrsw" },
{ AArch64_INS_ALIAS_STP, "stp" },
{ AArch64_INS_ALIAS_STURH, "sturh" },
{ AArch64_INS_ALIAS_STURB, "sturb" },
{ AArch64_INS_ALIAS_STLURH, "stlurh" },
{ AArch64_INS_ALIAS_LDAPURSB, "ldapursb" },
{ AArch64_INS_ALIAS_LDAPURH, "ldapurh" },
{ AArch64_INS_ALIAS_LDAPURSH, "ldapursh" },
{ AArch64_INS_ALIAS_LDAPURSW, "ldapursw" },
{ AArch64_INS_ALIAS_STTRH, "sttrh" },
{ AArch64_INS_ALIAS_STTRB, "sttrb" },
{ AArch64_INS_ALIAS_BIC_4H, "bic_4h" },
{ AArch64_INS_ALIAS_BIC_8H, "bic_8h" },
{ AArch64_INS_ALIAS_BIC_2S, "bic_2s" },
{ AArch64_INS_ALIAS_BIC_4S, "bic_4s" },
{ AArch64_INS_ALIAS_ORR_4H, "orr_4h" },
{ AArch64_INS_ALIAS_ORR_8H, "orr_8h" },
{ AArch64_INS_ALIAS_ORR_2S, "orr_2s" },
{ AArch64_INS_ALIAS_ORR_4S, "orr_4s" },
{ AArch64_INS_ALIAS_SXTL_8H, "sxtl_8h" },
{ AArch64_INS_ALIAS_SXTL, "sxtl" },
{ AArch64_INS_ALIAS_SXTL_4S, "sxtl_4s" },
{ AArch64_INS_ALIAS_SXTL_2D, "sxtl_2d" },
{ AArch64_INS_ALIAS_SXTL2_8H, "sxtl2_8h" },
{ AArch64_INS_ALIAS_SXTL2, "sxtl2" },
{ AArch64_INS_ALIAS_SXTL2_4S, "sxtl2_4s" },
{ AArch64_INS_ALIAS_SXTL2_2D, "sxtl2_2d" },
{ AArch64_INS_ALIAS_UXTL_8H, "uxtl_8h" },
{ AArch64_INS_ALIAS_UXTL, "uxtl" },
{ AArch64_INS_ALIAS_UXTL_4S, "uxtl_4s" },
{ AArch64_INS_ALIAS_UXTL_2D, "uxtl_2d" },
{ AArch64_INS_ALIAS_UXTL2_8H, "uxtl2_8h" },
{ AArch64_INS_ALIAS_UXTL2, "uxtl2" },
{ AArch64_INS_ALIAS_UXTL2_4S, "uxtl2_4s" },
{ AArch64_INS_ALIAS_UXTL2_2D, "uxtl2_2d" },
{ AArch64_INS_ALIAS_LD2, "ld2" },
{ AArch64_INS_ALIAS_LD3, "ld3" },
{ AArch64_INS_ALIAS_LD4, "ld4" },
{ AArch64_INS_ALIAS_ST1, "st1" },
{ AArch64_INS_ALIAS_ST2, "st2" },
{ AArch64_INS_ALIAS_ST3, "st3" },
{ AArch64_INS_ALIAS_ST4, "st4" },
{ AArch64_INS_ALIAS_LD2R, "ld2r" },
{ AArch64_INS_ALIAS_LD3R, "ld3r" },
{ AArch64_INS_ALIAS_LD4R, "ld4r" },
{ AArch64_INS_ALIAS_CLRBHB, "clrbhb" },
{ AArch64_INS_ALIAS_STILP, "stilp" },
{ AArch64_INS_ALIAS_STL1, "stl1" },
{ AArch64_INS_ALIAS_SYSP, "sysp" },
{ AARCH64_INS_ALIAS_ADDPT, "addpt" },
{ AARCH64_INS_ALIAS_GCSB, "gcsb" },
{ AARCH64_INS_ALIAS_GCSPOPM, "gcspopm" },
{ AARCH64_INS_ALIAS_LDAPUR, "ldapur" },
{ AARCH64_INS_ALIAS_STLLRB, "stllrb" },
{ AARCH64_INS_ALIAS_STLLRH, "stllrh" },
{ AARCH64_INS_ALIAS_STLLR, "stllr" },
{ AARCH64_INS_ALIAS_STLRB, "stlrb" },
{ AARCH64_INS_ALIAS_STLRH, "stlrh" },
{ AARCH64_INS_ALIAS_STLR, "stlr" },
{ AARCH64_INS_ALIAS_STLUR, "stlur" },
{ AARCH64_INS_ALIAS_SUBPT, "subpt" },
{ AARCH64_INS_ALIAS_LDRAA, "ldraa" },
{ AARCH64_INS_ALIAS_ADD, "add" },
{ AARCH64_INS_ALIAS_CMN, "cmn" },
{ AARCH64_INS_ALIAS_ADDS, "adds" },
{ AARCH64_INS_ALIAS_AND, "and" },
{ AARCH64_INS_ALIAS_ANDS, "ands" },
{ AARCH64_INS_ALIAS_LDR, "ldr" },
{ AARCH64_INS_ALIAS_STR, "str" },
{ AARCH64_INS_ALIAS_LDRB, "ldrb" },
{ AARCH64_INS_ALIAS_STRB, "strb" },
{ AARCH64_INS_ALIAS_LDRH, "ldrh" },
{ AARCH64_INS_ALIAS_STRH, "strh" },
{ AARCH64_INS_ALIAS_PRFM, "prfm" },
{ AARCH64_INS_ALIAS_LDAPURB, "ldapurb" },
{ AARCH64_INS_ALIAS_STLURB, "stlurb" },
{ AARCH64_INS_ALIAS_LDUR, "ldur" },
{ AARCH64_INS_ALIAS_STUR, "stur" },
{ AARCH64_INS_ALIAS_PRFUM, "prfum" },
{ AARCH64_INS_ALIAS_LDTR, "ldtr" },
{ AARCH64_INS_ALIAS_STTR, "sttr" },
{ AARCH64_INS_ALIAS_LDP, "ldp" },
{ AARCH64_INS_ALIAS_STGP, "stgp" },
{ AARCH64_INS_ALIAS_LDNP, "ldnp" },
{ AARCH64_INS_ALIAS_STNP, "stnp" },
{ AARCH64_INS_ALIAS_STG, "stg" },
{ AARCH64_INS_ALIAS_MOV, "mov" },
{ AARCH64_INS_ALIAS_LD1, "ld1" },
{ AARCH64_INS_ALIAS_LD1R, "ld1r" },
{ AARCH64_INS_ALIAS_STADDLB, "staddlb" },
{ AARCH64_INS_ALIAS_STADDLH, "staddlh" },
{ AARCH64_INS_ALIAS_STADDL, "staddl" },
{ AARCH64_INS_ALIAS_STADDB, "staddb" },
{ AARCH64_INS_ALIAS_STADDH, "staddh" },
{ AARCH64_INS_ALIAS_STADD, "stadd" },
{ AARCH64_INS_ALIAS_PTRUE, "ptrue" },
{ AARCH64_INS_ALIAS_PTRUES, "ptrues" },
{ AARCH64_INS_ALIAS_CNTB, "cntb" },
{ AARCH64_INS_ALIAS_SQINCH, "sqinch" },
{ AARCH64_INS_ALIAS_INCB, "incb" },
{ AARCH64_INS_ALIAS_SQINCB, "sqincb" },
{ AARCH64_INS_ALIAS_UQINCB, "uqincb" },
{ AARCH64_INS_ALIAS_ORR, "orr" },
{ AARCH64_INS_ALIAS_DUPM, "dupm" },
{ AARCH64_INS_ALIAS_FMOV, "fmov" },
{ AARCH64_INS_ALIAS_EOR3, "eor3" },
{ AARCH64_INS_ALIAS_ST1B, "st1b" },
{ AARCH64_INS_ALIAS_ST2B, "st2b" },
{ AARCH64_INS_ALIAS_ST2Q, "st2q" },
{ AARCH64_INS_ALIAS_STNT1B, "stnt1b" },
{ AARCH64_INS_ALIAS_LD1B, "ld1b" },
{ AARCH64_INS_ALIAS_LDNT1B, "ldnt1b" },
{ AARCH64_INS_ALIAS_LD1RQB, "ld1rqb" },
{ AARCH64_INS_ALIAS_LD1RB, "ld1rb" },
{ AARCH64_INS_ALIAS_LDFF1B, "ldff1b" },
{ AARCH64_INS_ALIAS_LDNF1B, "ldnf1b" },
{ AARCH64_INS_ALIAS_LD2B, "ld2b" },
{ AARCH64_INS_ALIAS_LD1SB, "ld1sb" },
{ AARCH64_INS_ALIAS_PRFB, "prfb" },
{ AARCH64_INS_ALIAS_LDNT1SB, "ldnt1sb" },
{ AARCH64_INS_ALIAS_LD1ROB, "ld1rob" },
{ AARCH64_INS_ALIAS_LD1Q, "ld1q" },
{ AARCH64_INS_ALIAS_ST1Q, "st1q" },
{ AARCH64_INS_ALIAS_LD1W, "ld1w" },
{ AARCH64_INS_ALIAS_PMOV, "pmov" },
{ AARCH64_INS_ALIAS_SMSTART, "smstart" },
{ AARCH64_INS_ALIAS_SMSTOP, "smstop" },
{ AARCH64_INS_ALIAS_ZERO, "zero" },
{ AARCH64_INS_ALIAS_MOVT, "movt" },
{ AARCH64_INS_ALIAS_NOP, "nop" },
{ AARCH64_INS_ALIAS_YIELD, "yield" },
{ AARCH64_INS_ALIAS_WFE, "wfe" },
{ AARCH64_INS_ALIAS_WFI, "wfi" },
{ AARCH64_INS_ALIAS_SEV, "sev" },
{ AARCH64_INS_ALIAS_SEVL, "sevl" },
{ AARCH64_INS_ALIAS_DGH, "dgh" },
{ AARCH64_INS_ALIAS_ESB, "esb" },
{ AARCH64_INS_ALIAS_CSDB, "csdb" },
{ AARCH64_INS_ALIAS_BTI, "bti" },
{ AARCH64_INS_ALIAS_PSB, "psb" },
{ AARCH64_INS_ALIAS_CHKFEAT, "chkfeat" },
{ AARCH64_INS_ALIAS_PACIAZ, "paciaz" },
{ AARCH64_INS_ALIAS_PACIBZ, "pacibz" },
{ AARCH64_INS_ALIAS_AUTIAZ, "autiaz" },
{ AARCH64_INS_ALIAS_AUTIBZ, "autibz" },
{ AARCH64_INS_ALIAS_PACIASP, "paciasp" },
{ AARCH64_INS_ALIAS_PACIBSP, "pacibsp" },
{ AARCH64_INS_ALIAS_AUTIASP, "autiasp" },
{ AARCH64_INS_ALIAS_AUTIBSP, "autibsp" },
{ AARCH64_INS_ALIAS_PACIA1716, "pacia1716" },
{ AARCH64_INS_ALIAS_PACIB1716, "pacib1716" },
{ AARCH64_INS_ALIAS_AUTIA1716, "autia1716" },
{ AARCH64_INS_ALIAS_AUTIB1716, "autib1716" },
{ AARCH64_INS_ALIAS_XPACLRI, "xpaclri" },
{ AARCH64_INS_ALIAS_LDRAB, "ldrab" },
{ AARCH64_INS_ALIAS_PACM, "pacm" },
{ AARCH64_INS_ALIAS_CLREX, "clrex" },
{ AARCH64_INS_ALIAS_ISB, "isb" },
{ AARCH64_INS_ALIAS_SSBB, "ssbb" },
{ AARCH64_INS_ALIAS_PSSBB, "pssbb" },
{ AARCH64_INS_ALIAS_DFB, "dfb" },
{ AARCH64_INS_ALIAS_SYS, "sys" },
{ AARCH64_INS_ALIAS_MOVN, "movn" },
{ AARCH64_INS_ALIAS_MOVZ, "movz" },
{ AARCH64_INS_ALIAS_NGC, "ngc" },
{ AARCH64_INS_ALIAS_NGCS, "ngcs" },
{ AARCH64_INS_ALIAS_SUB, "sub" },
{ AARCH64_INS_ALIAS_CMP, "cmp" },
{ AARCH64_INS_ALIAS_SUBS, "subs" },
{ AARCH64_INS_ALIAS_NEG, "neg" },
{ AARCH64_INS_ALIAS_NEGS, "negs" },
{ AARCH64_INS_ALIAS_MUL, "mul" },
{ AARCH64_INS_ALIAS_MNEG, "mneg" },
{ AARCH64_INS_ALIAS_SMULL, "smull" },
{ AARCH64_INS_ALIAS_SMNEGL, "smnegl" },
{ AARCH64_INS_ALIAS_UMULL, "umull" },
{ AARCH64_INS_ALIAS_UMNEGL, "umnegl" },
{ AARCH64_INS_ALIAS_STCLRLB, "stclrlb" },
{ AARCH64_INS_ALIAS_STCLRLH, "stclrlh" },
{ AARCH64_INS_ALIAS_STCLRL, "stclrl" },
{ AARCH64_INS_ALIAS_STCLRB, "stclrb" },
{ AARCH64_INS_ALIAS_STCLRH, "stclrh" },
{ AARCH64_INS_ALIAS_STCLR, "stclr" },
{ AARCH64_INS_ALIAS_STEORLB, "steorlb" },
{ AARCH64_INS_ALIAS_STEORLH, "steorlh" },
{ AARCH64_INS_ALIAS_STEORL, "steorl" },
{ AARCH64_INS_ALIAS_STEORB, "steorb" },
{ AARCH64_INS_ALIAS_STEORH, "steorh" },
{ AARCH64_INS_ALIAS_STEOR, "steor" },
{ AARCH64_INS_ALIAS_STSETLB, "stsetlb" },
{ AARCH64_INS_ALIAS_STSETLH, "stsetlh" },
{ AARCH64_INS_ALIAS_STSETL, "stsetl" },
{ AARCH64_INS_ALIAS_STSETB, "stsetb" },
{ AARCH64_INS_ALIAS_STSETH, "stseth" },
{ AARCH64_INS_ALIAS_STSET, "stset" },
{ AARCH64_INS_ALIAS_STSMAXLB, "stsmaxlb" },
{ AARCH64_INS_ALIAS_STSMAXLH, "stsmaxlh" },
{ AARCH64_INS_ALIAS_STSMAXL, "stsmaxl" },
{ AARCH64_INS_ALIAS_STSMAXB, "stsmaxb" },
{ AARCH64_INS_ALIAS_STSMAXH, "stsmaxh" },
{ AARCH64_INS_ALIAS_STSMAX, "stsmax" },
{ AARCH64_INS_ALIAS_STSMINLB, "stsminlb" },
{ AARCH64_INS_ALIAS_STSMINLH, "stsminlh" },
{ AARCH64_INS_ALIAS_STSMINL, "stsminl" },
{ AARCH64_INS_ALIAS_STSMINB, "stsminb" },
{ AARCH64_INS_ALIAS_STSMINH, "stsminh" },
{ AARCH64_INS_ALIAS_STSMIN, "stsmin" },
{ AARCH64_INS_ALIAS_STUMAXLB, "stumaxlb" },
{ AARCH64_INS_ALIAS_STUMAXLH, "stumaxlh" },
{ AARCH64_INS_ALIAS_STUMAXL, "stumaxl" },
{ AARCH64_INS_ALIAS_STUMAXB, "stumaxb" },
{ AARCH64_INS_ALIAS_STUMAXH, "stumaxh" },
{ AARCH64_INS_ALIAS_STUMAX, "stumax" },
{ AARCH64_INS_ALIAS_STUMINLB, "stuminlb" },
{ AARCH64_INS_ALIAS_STUMINLH, "stuminlh" },
{ AARCH64_INS_ALIAS_STUMINL, "stuminl" },
{ AARCH64_INS_ALIAS_STUMINB, "stuminb" },
{ AARCH64_INS_ALIAS_STUMINH, "stuminh" },
{ AARCH64_INS_ALIAS_STUMIN, "stumin" },
{ AARCH64_INS_ALIAS_IRG, "irg" },
{ AARCH64_INS_ALIAS_LDG, "ldg" },
{ AARCH64_INS_ALIAS_STZG, "stzg" },
{ AARCH64_INS_ALIAS_ST2G, "st2g" },
{ AARCH64_INS_ALIAS_STZ2G, "stz2g" },
{ AARCH64_INS_ALIAS_BICS, "bics" },
{ AARCH64_INS_ALIAS_BIC, "bic" },
{ AARCH64_INS_ALIAS_EON, "eon" },
{ AARCH64_INS_ALIAS_EOR, "eor" },
{ AARCH64_INS_ALIAS_ORN, "orn" },
{ AARCH64_INS_ALIAS_MVN, "mvn" },
{ AARCH64_INS_ALIAS_TST, "tst" },
{ AARCH64_INS_ALIAS_ROR, "ror" },
{ AARCH64_INS_ALIAS_ASR, "asr" },
{ AARCH64_INS_ALIAS_SXTB, "sxtb" },
{ AARCH64_INS_ALIAS_SXTH, "sxth" },
{ AARCH64_INS_ALIAS_SXTW, "sxtw" },
{ AARCH64_INS_ALIAS_LSR, "lsr" },
{ AARCH64_INS_ALIAS_UXTB, "uxtb" },
{ AARCH64_INS_ALIAS_UXTH, "uxth" },
{ AARCH64_INS_ALIAS_UXTW, "uxtw" },
{ AARCH64_INS_ALIAS_CSET, "cset" },
{ AARCH64_INS_ALIAS_CSETM, "csetm" },
{ AARCH64_INS_ALIAS_CINC, "cinc" },
{ AARCH64_INS_ALIAS_CINV, "cinv" },
{ AARCH64_INS_ALIAS_CNEG, "cneg" },
{ AARCH64_INS_ALIAS_RET, "ret" },
{ AARCH64_INS_ALIAS_DCPS1, "dcps1" },
{ AARCH64_INS_ALIAS_DCPS2, "dcps2" },
{ AARCH64_INS_ALIAS_DCPS3, "dcps3" },
{ AARCH64_INS_ALIAS_LDPSW, "ldpsw" },
{ AARCH64_INS_ALIAS_LDRSH, "ldrsh" },
{ AARCH64_INS_ALIAS_LDRSB, "ldrsb" },
{ AARCH64_INS_ALIAS_LDRSW, "ldrsw" },
{ AARCH64_INS_ALIAS_LDURH, "ldurh" },
{ AARCH64_INS_ALIAS_LDURB, "ldurb" },
{ AARCH64_INS_ALIAS_LDURSH, "ldursh" },
{ AARCH64_INS_ALIAS_LDURSB, "ldursb" },
{ AARCH64_INS_ALIAS_LDURSW, "ldursw" },
{ AARCH64_INS_ALIAS_LDTRH, "ldtrh" },
{ AARCH64_INS_ALIAS_LDTRB, "ldtrb" },
{ AARCH64_INS_ALIAS_LDTRSH, "ldtrsh" },
{ AARCH64_INS_ALIAS_LDTRSB, "ldtrsb" },
{ AARCH64_INS_ALIAS_LDTRSW, "ldtrsw" },
{ AARCH64_INS_ALIAS_STP, "stp" },
{ AARCH64_INS_ALIAS_STURH, "sturh" },
{ AARCH64_INS_ALIAS_STURB, "sturb" },
{ AARCH64_INS_ALIAS_STLURH, "stlurh" },
{ AARCH64_INS_ALIAS_LDAPURSB, "ldapursb" },
{ AARCH64_INS_ALIAS_LDAPURH, "ldapurh" },
{ AARCH64_INS_ALIAS_LDAPURSH, "ldapursh" },
{ AARCH64_INS_ALIAS_LDAPURSW, "ldapursw" },
{ AARCH64_INS_ALIAS_STTRH, "sttrh" },
{ AARCH64_INS_ALIAS_STTRB, "sttrb" },
{ AARCH64_INS_ALIAS_BIC_4H, "bic_4h" },
{ AARCH64_INS_ALIAS_BIC_8H, "bic_8h" },
{ AARCH64_INS_ALIAS_BIC_2S, "bic_2s" },
{ AARCH64_INS_ALIAS_BIC_4S, "bic_4s" },
{ AARCH64_INS_ALIAS_ORR_4H, "orr_4h" },
{ AARCH64_INS_ALIAS_ORR_8H, "orr_8h" },
{ AARCH64_INS_ALIAS_ORR_2S, "orr_2s" },
{ AARCH64_INS_ALIAS_ORR_4S, "orr_4s" },
{ AARCH64_INS_ALIAS_SXTL_8H, "sxtl_8h" },
{ AARCH64_INS_ALIAS_SXTL, "sxtl" },
{ AARCH64_INS_ALIAS_SXTL_4S, "sxtl_4s" },
{ AARCH64_INS_ALIAS_SXTL_2D, "sxtl_2d" },
{ AARCH64_INS_ALIAS_SXTL2_8H, "sxtl2_8h" },
{ AARCH64_INS_ALIAS_SXTL2, "sxtl2" },
{ AARCH64_INS_ALIAS_SXTL2_4S, "sxtl2_4s" },
{ AARCH64_INS_ALIAS_SXTL2_2D, "sxtl2_2d" },
{ AARCH64_INS_ALIAS_UXTL_8H, "uxtl_8h" },
{ AARCH64_INS_ALIAS_UXTL, "uxtl" },
{ AARCH64_INS_ALIAS_UXTL_4S, "uxtl_4s" },
{ AARCH64_INS_ALIAS_UXTL_2D, "uxtl_2d" },
{ AARCH64_INS_ALIAS_UXTL2_8H, "uxtl2_8h" },
{ AARCH64_INS_ALIAS_UXTL2, "uxtl2" },
{ AARCH64_INS_ALIAS_UXTL2_4S, "uxtl2_4s" },
{ AARCH64_INS_ALIAS_UXTL2_2D, "uxtl2_2d" },
{ AARCH64_INS_ALIAS_LD2, "ld2" },
{ AARCH64_INS_ALIAS_LD3, "ld3" },
{ AARCH64_INS_ALIAS_LD4, "ld4" },
{ AARCH64_INS_ALIAS_ST1, "st1" },
{ AARCH64_INS_ALIAS_ST2, "st2" },
{ AARCH64_INS_ALIAS_ST3, "st3" },
{ AARCH64_INS_ALIAS_ST4, "st4" },
{ AARCH64_INS_ALIAS_LD2R, "ld2r" },
{ AARCH64_INS_ALIAS_LD3R, "ld3r" },
{ AARCH64_INS_ALIAS_LD4R, "ld4r" },
{ AARCH64_INS_ALIAS_CLRBHB, "clrbhb" },
{ AARCH64_INS_ALIAS_STILP, "stilp" },
{ AARCH64_INS_ALIAS_STL1, "stl1" },
{ AARCH64_INS_ALIAS_SYSP, "sysp" },
{ AARCH64_INS_ALIAS_LD1SW, "ld1sw" },
{ AARCH64_INS_ALIAS_LD1H, "ld1h" },
{ AARCH64_INS_ALIAS_LD1SH, "ld1sh" },
{ AARCH64_INS_ALIAS_LD1D, "ld1d" },
{ AARCH64_INS_ALIAS_LD1RSW, "ld1rsw" },
{ AARCH64_INS_ALIAS_LD1RH, "ld1rh" },
{ AARCH64_INS_ALIAS_LD1RSH, "ld1rsh" },
{ AARCH64_INS_ALIAS_LD1RW, "ld1rw" },
{ AARCH64_INS_ALIAS_LD1RSB, "ld1rsb" },
{ AARCH64_INS_ALIAS_LD1RD, "ld1rd" },
{ AARCH64_INS_ALIAS_LD1RQH, "ld1rqh" },
{ AARCH64_INS_ALIAS_LD1RQW, "ld1rqw" },
{ AARCH64_INS_ALIAS_LD1RQD, "ld1rqd" },
{ AARCH64_INS_ALIAS_LDNF1SW, "ldnf1sw" },
{ AARCH64_INS_ALIAS_LDNF1H, "ldnf1h" },
{ AARCH64_INS_ALIAS_LDNF1SH, "ldnf1sh" },
{ AARCH64_INS_ALIAS_LDNF1W, "ldnf1w" },
{ AARCH64_INS_ALIAS_LDNF1SB, "ldnf1sb" },
{ AARCH64_INS_ALIAS_LDNF1D, "ldnf1d" },
{ AARCH64_INS_ALIAS_LDFF1SW, "ldff1sw" },
{ AARCH64_INS_ALIAS_LDFF1H, "ldff1h" },
{ AARCH64_INS_ALIAS_LDFF1SH, "ldff1sh" },
{ AARCH64_INS_ALIAS_LDFF1W, "ldff1w" },
{ AARCH64_INS_ALIAS_LDFF1SB, "ldff1sb" },
{ AARCH64_INS_ALIAS_LDFF1D, "ldff1d" },
{ AARCH64_INS_ALIAS_LD3B, "ld3b" },
{ AARCH64_INS_ALIAS_LD4B, "ld4b" },
{ AARCH64_INS_ALIAS_LD2H, "ld2h" },
{ AARCH64_INS_ALIAS_LD3H, "ld3h" },
{ AARCH64_INS_ALIAS_LD4H, "ld4h" },
{ AARCH64_INS_ALIAS_LD2W, "ld2w" },
{ AARCH64_INS_ALIAS_LD3W, "ld3w" },
{ AARCH64_INS_ALIAS_LD4W, "ld4w" },
{ AARCH64_INS_ALIAS_LD2D, "ld2d" },
{ AARCH64_INS_ALIAS_LD3D, "ld3d" },
{ AARCH64_INS_ALIAS_LD4D, "ld4d" },
{ AARCH64_INS_ALIAS_LD2Q, "ld2q" },
{ AARCH64_INS_ALIAS_LD3Q, "ld3q" },
{ AARCH64_INS_ALIAS_LD4Q, "ld4q" },
{ AARCH64_INS_ALIAS_LDNT1H, "ldnt1h" },
{ AARCH64_INS_ALIAS_LDNT1W, "ldnt1w" },
{ AARCH64_INS_ALIAS_LDNT1D, "ldnt1d" },
{ AARCH64_INS_ALIAS_ST1H, "st1h" },
{ AARCH64_INS_ALIAS_ST1W, "st1w" },
{ AARCH64_INS_ALIAS_ST1D, "st1d" },
{ AARCH64_INS_ALIAS_ST3B, "st3b" },
{ AARCH64_INS_ALIAS_ST4B, "st4b" },
{ AARCH64_INS_ALIAS_ST2H, "st2h" },
{ AARCH64_INS_ALIAS_ST3H, "st3h" },
{ AARCH64_INS_ALIAS_ST4H, "st4h" },
{ AARCH64_INS_ALIAS_ST2W, "st2w" },
{ AARCH64_INS_ALIAS_ST3W, "st3w" },
{ AARCH64_INS_ALIAS_ST4W, "st4w" },
{ AARCH64_INS_ALIAS_ST2D, "st2d" },
{ AARCH64_INS_ALIAS_ST3D, "st3d" },
{ AARCH64_INS_ALIAS_ST4D, "st4d" },
{ AARCH64_INS_ALIAS_ST3Q, "st3q" },
{ AARCH64_INS_ALIAS_ST4Q, "st4q" },
{ AARCH64_INS_ALIAS_STNT1H, "stnt1h" },
{ AARCH64_INS_ALIAS_STNT1W, "stnt1w" },
{ AARCH64_INS_ALIAS_STNT1D, "stnt1d" },
{ AARCH64_INS_ALIAS_PRFH, "prfh" },
{ AARCH64_INS_ALIAS_PRFW, "prfw" },
{ AARCH64_INS_ALIAS_PRFD, "prfd" },
{ AARCH64_INS_ALIAS_CNTH, "cnth" },
{ AARCH64_INS_ALIAS_CNTW, "cntw" },
{ AARCH64_INS_ALIAS_CNTD, "cntd" },
{ AARCH64_INS_ALIAS_DECB, "decb" },
{ AARCH64_INS_ALIAS_INCH, "inch" },
{ AARCH64_INS_ALIAS_DECH, "dech" },
{ AARCH64_INS_ALIAS_INCW, "incw" },
{ AARCH64_INS_ALIAS_DECW, "decw" },
{ AARCH64_INS_ALIAS_INCD, "incd" },
{ AARCH64_INS_ALIAS_DECD, "decd" },
{ AARCH64_INS_ALIAS_SQDECB, "sqdecb" },
{ AARCH64_INS_ALIAS_UQDECB, "uqdecb" },
{ AARCH64_INS_ALIAS_UQINCH, "uqinch" },
{ AARCH64_INS_ALIAS_SQDECH, "sqdech" },
{ AARCH64_INS_ALIAS_UQDECH, "uqdech" },
{ AARCH64_INS_ALIAS_SQINCW, "sqincw" },
{ AARCH64_INS_ALIAS_UQINCW, "uqincw" },
{ AARCH64_INS_ALIAS_SQDECW, "sqdecw" },
{ AARCH64_INS_ALIAS_UQDECW, "uqdecw" },
{ AARCH64_INS_ALIAS_SQINCD, "sqincd" },
{ AARCH64_INS_ALIAS_UQINCD, "uqincd" },
{ AARCH64_INS_ALIAS_SQDECD, "sqdecd" },
{ AARCH64_INS_ALIAS_UQDECD, "uqdecd" },
{ AARCH64_INS_ALIAS_MOVS, "movs" },
{ AARCH64_INS_ALIAS_NOT, "not" },
{ AARCH64_INS_ALIAS_NOTS, "nots" },
{ AARCH64_INS_ALIAS_LD1ROH, "ld1roh" },
{ AARCH64_INS_ALIAS_LD1ROW, "ld1row" },
{ AARCH64_INS_ALIAS_LD1ROD, "ld1rod" },
{ AARCH64_INS_ALIAS_BCAX, "bcax" },
{ AARCH64_INS_ALIAS_BSL, "bsl" },
{ AARCH64_INS_ALIAS_BSL1N, "bsl1n" },
{ AARCH64_INS_ALIAS_BSL2N, "bsl2n" },
{ AARCH64_INS_ALIAS_NBSL, "nbsl" },
{ AARCH64_INS_ALIAS_LDNT1SH, "ldnt1sh" },
{ AARCH64_INS_ALIAS_LDNT1SW, "ldnt1sw" },

232
arch/AArch64/AArch64GenCSFeatureName.inc
View File

@ -1,6 +1,6 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
@ -11,108 +11,126 @@
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ AArch64_FEATURE_HasV8_0a, "HasV8_0a" },
{ AArch64_FEATURE_HasV8_1a, "HasV8_1a" },
{ AArch64_FEATURE_HasV8_2a, "HasV8_2a" },
{ AArch64_FEATURE_HasV8_3a, "HasV8_3a" },
{ AArch64_FEATURE_HasV8_4a, "HasV8_4a" },
{ AArch64_FEATURE_HasV8_5a, "HasV8_5a" },
{ AArch64_FEATURE_HasV8_6a, "HasV8_6a" },
{ AArch64_FEATURE_HasV8_7a, "HasV8_7a" },
{ AArch64_FEATURE_HasV8_8a, "HasV8_8a" },
{ AArch64_FEATURE_HasV8_9a, "HasV8_9a" },
{ AArch64_FEATURE_HasV9_0a, "HasV9_0a" },
{ AArch64_FEATURE_HasV9_1a, "HasV9_1a" },
{ AArch64_FEATURE_HasV9_2a, "HasV9_2a" },
{ AArch64_FEATURE_HasV9_3a, "HasV9_3a" },
{ AArch64_FEATURE_HasV9_4a, "HasV9_4a" },
{ AArch64_FEATURE_HasV8_0r, "HasV8_0r" },
{ AArch64_FEATURE_HasEL2VMSA, "HasEL2VMSA" },
{ AArch64_FEATURE_HasEL3, "HasEL3" },
{ AArch64_FEATURE_HasVH, "HasVH" },
{ AArch64_FEATURE_HasLOR, "HasLOR" },
{ AArch64_FEATURE_HasPAuth, "HasPAuth" },
{ AArch64_FEATURE_HasJS, "HasJS" },
{ AArch64_FEATURE_HasCCIDX, "HasCCIDX" },
{ AArch64_FEATURE_HasComplxNum, "HasComplxNum" },
{ AArch64_FEATURE_HasNV, "HasNV" },
{ AArch64_FEATURE_HasMPAM, "HasMPAM" },
{ AArch64_FEATURE_HasDIT, "HasDIT" },
{ AArch64_FEATURE_HasTRACEV8_4, "HasTRACEV8_4" },
{ AArch64_FEATURE_HasAM, "HasAM" },
{ AArch64_FEATURE_HasSEL2, "HasSEL2" },
{ AArch64_FEATURE_HasTLB_RMI, "HasTLB_RMI" },
{ AArch64_FEATURE_HasFlagM, "HasFlagM" },
{ AArch64_FEATURE_HasRCPC_IMMO, "HasRCPC_IMMO" },
{ AArch64_FEATURE_HasFPARMv8, "HasFPARMv8" },
{ AArch64_FEATURE_HasNEON, "HasNEON" },
{ AArch64_FEATURE_HasCrypto, "HasCrypto" },
{ AArch64_FEATURE_HasSM4, "HasSM4" },
{ AArch64_FEATURE_HasSHA3, "HasSHA3" },
{ AArch64_FEATURE_HasSHA2, "HasSHA2" },
{ AArch64_FEATURE_HasAES, "HasAES" },
{ AArch64_FEATURE_HasDotProd, "HasDotProd" },
{ AArch64_FEATURE_HasCRC, "HasCRC" },
{ AArch64_FEATURE_HasCSSC, "HasCSSC" },
{ AArch64_FEATURE_HasLSE, "HasLSE" },
{ AArch64_FEATURE_HasRAS, "HasRAS" },
{ AArch64_FEATURE_HasRDM, "HasRDM" },
{ AArch64_FEATURE_HasFullFP16, "HasFullFP16" },
{ AArch64_FEATURE_HasFP16FML, "HasFP16FML" },
{ AArch64_FEATURE_HasSPE, "HasSPE" },
{ AArch64_FEATURE_HasFuseAES, "HasFuseAES" },
{ AArch64_FEATURE_HasSVE, "HasSVE" },
{ AArch64_FEATURE_HasSVE2, "HasSVE2" },
{ AArch64_FEATURE_HasSVE2p1, "HasSVE2p1" },
{ AArch64_FEATURE_HasSVE2AES, "HasSVE2AES" },
{ AArch64_FEATURE_HasSVE2SM4, "HasSVE2SM4" },
{ AArch64_FEATURE_HasSVE2SHA3, "HasSVE2SHA3" },
{ AArch64_FEATURE_HasSVE2BitPerm, "HasSVE2BitPerm" },
{ AArch64_FEATURE_HasB16B16, "HasB16B16" },
{ AArch64_FEATURE_HasSME, "HasSME" },
{ AArch64_FEATURE_HasSMEF64F64, "HasSMEF64F64" },
{ AArch64_FEATURE_HasSMEF16F16, "HasSMEF16F16" },
{ AArch64_FEATURE_HasSMEI16I64, "HasSMEI16I64" },
{ AArch64_FEATURE_HasSME2, "HasSME2" },
{ AArch64_FEATURE_HasSME2p1, "HasSME2p1" },
{ AArch64_FEATURE_HasSVEorSME, "HasSVEorSME" },
{ AArch64_FEATURE_HasSVE2orSME, "HasSVE2orSME" },
{ AArch64_FEATURE_HasSVE2p1_or_HasSME, "HasSVE2p1_or_HasSME" },
{ AArch64_FEATURE_HasSVE2p1_or_HasSME2, "HasSVE2p1_or_HasSME2" },
{ AArch64_FEATURE_HasSVE2p1_or_HasSME2p1, "HasSVE2p1_or_HasSME2p1" },
{ AArch64_FEATURE_HasNEONorSME, "HasNEONorSME" },
{ AArch64_FEATURE_HasRCPC, "HasRCPC" },
{ AArch64_FEATURE_HasAltNZCV, "HasAltNZCV" },
{ AArch64_FEATURE_HasFRInt3264, "HasFRInt3264" },
{ AArch64_FEATURE_HasSB, "HasSB" },
{ AArch64_FEATURE_HasPredRes, "HasPredRes" },
{ AArch64_FEATURE_HasCCDP, "HasCCDP" },
{ AArch64_FEATURE_HasBTI, "HasBTI" },
{ AArch64_FEATURE_HasMTE, "HasMTE" },
{ AArch64_FEATURE_HasTME, "HasTME" },
{ AArch64_FEATURE_HasETE, "HasETE" },
{ AArch64_FEATURE_HasTRBE, "HasTRBE" },
{ AArch64_FEATURE_HasBF16, "HasBF16" },
{ AArch64_FEATURE_HasMatMulInt8, "HasMatMulInt8" },
{ AArch64_FEATURE_HasMatMulFP32, "HasMatMulFP32" },
{ AArch64_FEATURE_HasMatMulFP64, "HasMatMulFP64" },
{ AArch64_FEATURE_HasXS, "HasXS" },
{ AArch64_FEATURE_HasWFxT, "HasWFxT" },
{ AArch64_FEATURE_HasLS64, "HasLS64" },
{ AArch64_FEATURE_HasBRBE, "HasBRBE" },
{ AArch64_FEATURE_HasSPE_EEF, "HasSPE_EEF" },
{ AArch64_FEATURE_HasHBC, "HasHBC" },
{ AArch64_FEATURE_HasMOPS, "HasMOPS" },
{ AArch64_FEATURE_HasCLRBHB, "HasCLRBHB" },
{ AArch64_FEATURE_HasSPECRES2, "HasSPECRES2" },
{ AArch64_FEATURE_HasITE, "HasITE" },
{ AArch64_FEATURE_HasTHE, "HasTHE" },
{ AArch64_FEATURE_HasRCPC3, "HasRCPC3" },
{ AArch64_FEATURE_HasLSE128, "HasLSE128" },
{ AArch64_FEATURE_HasD128, "HasD128" },
{ AArch64_FEATURE_UseNegativeImmediates, "UseNegativeImmediates" },
{ AArch64_FEATURE_HasCCPP, "HasCCPP" },
{ AArch64_FEATURE_HasPAN, "HasPAN" },
{ AArch64_FEATURE_HasPsUAO, "HasPsUAO" },
{ AArch64_FEATURE_HasPAN_RWV, "HasPAN_RWV" },
{ AArch64_FEATURE_HasCONTEXTIDREL2, "HasCONTEXTIDREL2" },
{ AARCH64_FEATURE_HASV8_0A, "HasV8_0a" },
{ AARCH64_FEATURE_HASV8_1A, "HasV8_1a" },
{ AARCH64_FEATURE_HASV8_2A, "HasV8_2a" },
{ AARCH64_FEATURE_HASV8_3A, "HasV8_3a" },
{ AARCH64_FEATURE_HASV8_4A, "HasV8_4a" },
{ AARCH64_FEATURE_HASV8_5A, "HasV8_5a" },
{ AARCH64_FEATURE_HASV8_6A, "HasV8_6a" },
{ AARCH64_FEATURE_HASV8_7A, "HasV8_7a" },
{ AARCH64_FEATURE_HASV8_8A, "HasV8_8a" },
{ AARCH64_FEATURE_HASV8_9A, "HasV8_9a" },
{ AARCH64_FEATURE_HASV9_0A, "HasV9_0a" },
{ AARCH64_FEATURE_HASV9_1A, "HasV9_1a" },
{ AARCH64_FEATURE_HASV9_2A, "HasV9_2a" },
{ AARCH64_FEATURE_HASV9_3A, "HasV9_3a" },
{ AARCH64_FEATURE_HASV9_4A, "HasV9_4a" },
{ AARCH64_FEATURE_HASV8_0R, "HasV8_0r" },
{ AARCH64_FEATURE_HASEL2VMSA, "HasEL2VMSA" },
{ AARCH64_FEATURE_HASEL3, "HasEL3" },
{ AARCH64_FEATURE_HASVH, "HasVH" },
{ AARCH64_FEATURE_HASLOR, "HasLOR" },
{ AARCH64_FEATURE_HASPAUTH, "HasPAuth" },
{ AARCH64_FEATURE_HASPAUTHLR, "HasPAuthLR" },
{ AARCH64_FEATURE_HASJS, "HasJS" },
{ AARCH64_FEATURE_HASCCIDX, "HasCCIDX" },
{ AARCH64_FEATURE_HASCOMPLXNUM, "HasComplxNum" },
{ AARCH64_FEATURE_HASNV, "HasNV" },
{ AARCH64_FEATURE_HASMPAM, "HasMPAM" },
{ AARCH64_FEATURE_HASDIT, "HasDIT" },
{ AARCH64_FEATURE_HASTRACEV8_4, "HasTRACEV8_4" },
{ AARCH64_FEATURE_HASAM, "HasAM" },
{ AARCH64_FEATURE_HASSEL2, "HasSEL2" },
{ AARCH64_FEATURE_HASTLB_RMI, "HasTLB_RMI" },
{ AARCH64_FEATURE_HASFLAGM, "HasFlagM" },
{ AARCH64_FEATURE_HASRCPC_IMMO, "HasRCPC_IMMO" },
{ AARCH64_FEATURE_HASFPARMV8, "HasFPARMv8" },
{ AARCH64_FEATURE_HASNEON, "HasNEON" },
{ AARCH64_FEATURE_HASSM4, "HasSM4" },
{ AARCH64_FEATURE_HASSHA3, "HasSHA3" },
{ AARCH64_FEATURE_HASSHA2, "HasSHA2" },
{ AARCH64_FEATURE_HASAES, "HasAES" },
{ AARCH64_FEATURE_HASDOTPROD, "HasDotProd" },
{ AARCH64_FEATURE_HASCRC, "HasCRC" },
{ AARCH64_FEATURE_HASCSSC, "HasCSSC" },
{ AARCH64_FEATURE_HASLSE, "HasLSE" },
{ AARCH64_FEATURE_HASRAS, "HasRAS" },
{ AARCH64_FEATURE_HASRDM, "HasRDM" },
{ AARCH64_FEATURE_HASFULLFP16, "HasFullFP16" },
{ AARCH64_FEATURE_HASFP16FML, "HasFP16FML" },
{ AARCH64_FEATURE_HASSPE, "HasSPE" },
{ AARCH64_FEATURE_HASFUSEAES, "HasFuseAES" },
{ AARCH64_FEATURE_HASSVE, "HasSVE" },
{ AARCH64_FEATURE_HASSVE2, "HasSVE2" },
{ AARCH64_FEATURE_HASSVE2P1, "HasSVE2p1" },
{ AARCH64_FEATURE_HASSVE2AES, "HasSVE2AES" },
{ AARCH64_FEATURE_HASSVE2SM4, "HasSVE2SM4" },
{ AARCH64_FEATURE_HASSVE2SHA3, "HasSVE2SHA3" },
{ AARCH64_FEATURE_HASSVE2BITPERM, "HasSVE2BitPerm" },
{ AARCH64_FEATURE_HASB16B16, "HasB16B16" },
{ AARCH64_FEATURE_HASSME, "HasSME" },
{ AARCH64_FEATURE_HASSMEF64F64, "HasSMEF64F64" },
{ AARCH64_FEATURE_HASSMEF16F16, "HasSMEF16F16" },
{ AARCH64_FEATURE_HASSMEFA64, "HasSMEFA64" },
{ AARCH64_FEATURE_HASSMEI16I64, "HasSMEI16I64" },
{ AARCH64_FEATURE_HASSME2, "HasSME2" },
{ AARCH64_FEATURE_HASSME2P1, "HasSME2p1" },
{ AARCH64_FEATURE_HASFPMR, "HasFPMR" },
{ AARCH64_FEATURE_HASFP8, "HasFP8" },
{ AARCH64_FEATURE_HASFAMINMAX, "HasFAMINMAX" },
{ AARCH64_FEATURE_HASFP8FMA, "HasFP8FMA" },
{ AARCH64_FEATURE_HASSSVE_FP8FMA, "HasSSVE_FP8FMA" },
{ AARCH64_FEATURE_HASFP8DOT2, "HasFP8DOT2" },
{ AARCH64_FEATURE_HASSSVE_FP8DOT2, "HasSSVE_FP8DOT2" },
{ AARCH64_FEATURE_HASFP8DOT4, "HasFP8DOT4" },
{ AARCH64_FEATURE_HASSSVE_FP8DOT4, "HasSSVE_FP8DOT4" },
{ AARCH64_FEATURE_HASLUT, "HasLUT" },
{ AARCH64_FEATURE_HASSME_LUTV2, "HasSME_LUTv2" },
{ AARCH64_FEATURE_HASSMEF8F16, "HasSMEF8F16" },
{ AARCH64_FEATURE_HASSMEF8F32, "HasSMEF8F32" },
{ AARCH64_FEATURE_HASSVEORSME, "HasSVEorSME" },
{ AARCH64_FEATURE_HASSVE2ORSME, "HasSVE2orSME" },
{ AARCH64_FEATURE_HASSVE2ORSME2, "HasSVE2orSME2" },
{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME, "HasSVE2p1_or_HasSME" },
{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME2, "HasSVE2p1_or_HasSME2" },
{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME2P1, "HasSVE2p1_or_HasSME2p1" },
{ AARCH64_FEATURE_HASNEONORSME, "HasNEONorSME" },
{ AARCH64_FEATURE_HASRCPC, "HasRCPC" },
{ AARCH64_FEATURE_HASALTNZCV, "HasAltNZCV" },
{ AARCH64_FEATURE_HASFRINT3264, "HasFRInt3264" },
{ AARCH64_FEATURE_HASSB, "HasSB" },
{ AARCH64_FEATURE_HASPREDRES, "HasPredRes" },
{ AARCH64_FEATURE_HASCCDP, "HasCCDP" },
{ AARCH64_FEATURE_HASBTI, "HasBTI" },
{ AARCH64_FEATURE_HASMTE, "HasMTE" },
{ AARCH64_FEATURE_HASTME, "HasTME" },
{ AARCH64_FEATURE_HASETE, "HasETE" },
{ AARCH64_FEATURE_HASTRBE, "HasTRBE" },
{ AARCH64_FEATURE_HASBF16, "HasBF16" },
{ AARCH64_FEATURE_HASMATMULINT8, "HasMatMulInt8" },
{ AARCH64_FEATURE_HASMATMULFP32, "HasMatMulFP32" },
{ AARCH64_FEATURE_HASMATMULFP64, "HasMatMulFP64" },
{ AARCH64_FEATURE_HASXS, "HasXS" },
{ AARCH64_FEATURE_HASWFXT, "HasWFxT" },
{ AARCH64_FEATURE_HASLS64, "HasLS64" },
{ AARCH64_FEATURE_HASBRBE, "HasBRBE" },
{ AARCH64_FEATURE_HASSPE_EEF, "HasSPE_EEF" },
{ AARCH64_FEATURE_HASHBC, "HasHBC" },
{ AARCH64_FEATURE_HASMOPS, "HasMOPS" },
{ AARCH64_FEATURE_HASCLRBHB, "HasCLRBHB" },
{ AARCH64_FEATURE_HASSPECRES2, "HasSPECRES2" },
{ AARCH64_FEATURE_HASITE, "HasITE" },
{ AARCH64_FEATURE_HASTHE, "HasTHE" },
{ AARCH64_FEATURE_HASRCPC3, "HasRCPC3" },
{ AARCH64_FEATURE_HASLSE128, "HasLSE128" },
{ AARCH64_FEATURE_HASD128, "HasD128" },
{ AARCH64_FEATURE_HASCHK, "HasCHK" },
{ AARCH64_FEATURE_HASGCS, "HasGCS" },
{ AARCH64_FEATURE_HASCPA, "HasCPA" },
{ AARCH64_FEATURE_USENEGATIVEIMMEDIATES, "UseNegativeImmediates" },
{ AARCH64_FEATURE_HASCCPP, "HasCCPP" },
{ AARCH64_FEATURE_HASPAN, "HasPAN" },
{ AARCH64_FEATURE_HASPSUAO, "HasPsUAO" },
{ AARCH64_FEATURE_HASPAN_RWV, "HasPAN_RWV" },
{ AARCH64_FEATURE_HASCONTEXTIDREL2, "HasCONTEXTIDREL2" },

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arch/AArch64/AArch64GenCSMappingInsn.inc
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arch/AArch64/AArch64GenCSMappingInsnName.inc
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arch/AArch64/AArch64GenCSMappingInsnOp.inc
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arch/AArch64/AArch64GenCSOpGroup.inc
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@ -1,6 +1,6 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
@ -12,165 +12,169 @@
/* https://github.com/capstone-engine/llvm-capstone */
AArch64_OP_GROUP_AMNoIndex = 0,
AArch64_OP_GROUP_BTIHintOp = 1,
AArch64_OP_GROUP_ImplicitlyTypedVectorList = 2,
AArch64_OP_GROUP_InverseCondCode = 3,
AArch64_OP_GROUP_LogicalImm_int16_t = 4,
AArch64_OP_GROUP_LogicalImm_int8_t = 5,
AArch64_OP_GROUP_PSBHintOp = 6,
AArch64_OP_GROUP_PrefetchOp_1 = 7,
AArch64_OP_GROUP_SVELogicalImm_int16_t = 8,
AArch64_OP_GROUP_SVELogicalImm_int32_t = 9,
AArch64_OP_GROUP_SVELogicalImm_int64_t = 10,
AArch64_OP_GROUP_SVERegOp_0 = 11,
AArch64_OP_GROUP_VectorIndex_8 = 12,
AArch64_OP_GROUP_ZPRasFPR_128 = 13,
AArch64_OP_GROUP_Operand = 14,
AArch64_OP_GROUP_SVERegOp_b = 15,
AArch64_OP_GROUP_SVERegOp_d = 16,
AArch64_OP_GROUP_SVERegOp_h = 17,
AArch64_OP_GROUP_SVERegOp_s = 18,
AArch64_OP_GROUP_MatrixIndex = 19,
AArch64_OP_GROUP_TypedVectorList_0_d = 20,
AArch64_OP_GROUP_TypedVectorList_0_s = 21,
AArch64_OP_GROUP_VRegOperand = 22,
AArch64_OP_GROUP_TypedVectorList_0_h = 23,
AArch64_OP_GROUP_VectorIndex_1 = 24,
AArch64_OP_GROUP_ImmRangeScale_2_1 = 25,
AArch64_OP_GROUP_AlignedLabel = 26,
AArch64_OP_GROUP_CondCode = 27,
AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_one = 28,
AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_zero_AArch64ExactFPImm_one = 29,
AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_two = 30,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_d = 31,
AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_d = 32,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_d = 33,
AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_s = 34,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_s = 35,
AArch64_OP_GROUP_ImmScale_8 = 36,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_d = 37,
AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_d = 38,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_d = 39,
AArch64_OP_GROUP_ImmScale_2 = 40,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_d = 41,
AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_d = 42,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_d = 43,
AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_s = 44,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_s = 45,
AArch64_OP_GROUP_ImmScale_4 = 46,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_d = 47,
AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_d = 48,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_d = 49,
AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_s = 50,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_s = 51,
AArch64_OP_GROUP_TypedVectorList_0_b = 52,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_0 = 53,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_0 = 54,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_0 = 55,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_0 = 56,
AArch64_OP_GROUP_SVCROp = 57,
AArch64_OP_GROUP_ImmScale_16 = 58,
AArch64_OP_GROUP_MatrixTile = 59,
AArch64_OP_GROUP_AddSubImm = 60,
AArch64_OP_GROUP_ShiftedRegister = 61,
AArch64_OP_GROUP_ExtendedRegister = 62,
AArch64_OP_GROUP_ArithExtend = 63,
AArch64_OP_GROUP_Matrix_64 = 64,
AArch64_OP_GROUP_Matrix_32 = 65,
AArch64_OP_GROUP_Imm8OptLsl_uint8_t = 66,
AArch64_OP_GROUP_Imm8OptLsl_uint64_t = 67,
AArch64_OP_GROUP_Imm8OptLsl_uint16_t = 68,
AArch64_OP_GROUP_Imm8OptLsl_uint32_t = 69,
AArch64_OP_GROUP_AdrLabel = 70,
AArch64_OP_GROUP_AdrpLabel = 71,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_s = 72,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_s = 73,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_s = 74,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_s = 75,
AArch64_OP_GROUP_LogicalImm_int32_t = 76,
AArch64_OP_GROUP_LogicalImm_int64_t = 77,
AArch64_OP_GROUP_ZPRasFPR_8 = 78,
AArch64_OP_GROUP_ZPRasFPR_64 = 79,
AArch64_OP_GROUP_ZPRasFPR_16 = 80,
AArch64_OP_GROUP_ZPRasFPR_32 = 81,
AArch64_OP_GROUP_Matrix_16 = 82,
AArch64_OP_GROUP_Imm = 83,
AArch64_OP_GROUP_Shifter = 84,
AArch64_OP_GROUP_ImmHex = 85,
AArch64_OP_GROUP_ComplexRotationOp_180_90 = 86,
AArch64_OP_GROUP_GPRSeqPairsClassOperand_32 = 87,
AArch64_OP_GROUP_GPRSeqPairsClassOperand_64 = 88,
AArch64_OP_GROUP_ComplexRotationOp_90_0 = 89,
AArch64_OP_GROUP_SVEPattern = 90,
AArch64_OP_GROUP_PredicateAsCounter_8 = 91,
AArch64_OP_GROUP_SVEVecLenSpecifier = 92,
AArch64_OP_GROUP_PredicateAsCounter_64 = 93,
AArch64_OP_GROUP_PredicateAsCounter_16 = 94,
AArch64_OP_GROUP_PredicateAsCounter_32 = 95,
AArch64_OP_GROUP_Imm8OptLsl_int8_t = 96,
AArch64_OP_GROUP_Imm8OptLsl_int64_t = 97,
AArch64_OP_GROUP_Imm8OptLsl_int16_t = 98,
AArch64_OP_GROUP_Imm8OptLsl_int32_t = 99,
AArch64_OP_GROUP_BarrierOption = 100,
AArch64_OP_GROUP_BarriernXSOption = 101,
AArch64_OP_GROUP_SVERegOp_q = 102,
AArch64_OP_GROUP_MatrixTileVector_0 = 103,
AArch64_OP_GROUP_MatrixTileVector_1 = 104,
AArch64_OP_GROUP_FPImmOperand = 105,
AArch64_OP_GROUP_TypedVectorList_0_q = 106,
AArch64_OP_GROUP_SImm_8 = 107,
AArch64_OP_GROUP_SImm_16 = 108,
AArch64_OP_GROUP_PredicateAsCounter_0 = 109,
AArch64_OP_GROUP_TypedVectorList_16_b = 110,
AArch64_OP_GROUP_PostIncOperand_64 = 111,
AArch64_OP_GROUP_TypedVectorList_1_d = 112,
AArch64_OP_GROUP_PostIncOperand_32 = 113,
AArch64_OP_GROUP_TypedVectorList_2_d = 114,
AArch64_OP_GROUP_TypedVectorList_2_s = 115,
AArch64_OP_GROUP_TypedVectorList_4_h = 116,
AArch64_OP_GROUP_TypedVectorList_4_s = 117,
AArch64_OP_GROUP_TypedVectorList_8_b = 118,
AArch64_OP_GROUP_TypedVectorList_8_h = 119,
AArch64_OP_GROUP_PostIncOperand_16 = 120,
AArch64_OP_GROUP_PostIncOperand_8 = 121,
AArch64_OP_GROUP_ImmScale_32 = 122,
AArch64_OP_GROUP_PostIncOperand_1 = 123,
AArch64_OP_GROUP_PostIncOperand_4 = 124,
AArch64_OP_GROUP_PostIncOperand_2 = 125,
AArch64_OP_GROUP_PostIncOperand_48 = 126,
AArch64_OP_GROUP_PostIncOperand_24 = 127,
AArch64_OP_GROUP_RegWithShiftExtend_0_128_x_0 = 128,
AArch64_OP_GROUP_ImmScale_3 = 129,
AArch64_OP_GROUP_PostIncOperand_3 = 130,
AArch64_OP_GROUP_PostIncOperand_12 = 131,
AArch64_OP_GROUP_PostIncOperand_6 = 132,
AArch64_OP_GROUP_GPR64x8 = 133,
AArch64_OP_GROUP_MemExtend_w_8 = 134,
AArch64_OP_GROUP_MemExtend_x_8 = 135,
AArch64_OP_GROUP_UImm12Offset_1 = 136,
AArch64_OP_GROUP_MemExtend_w_64 = 137,
AArch64_OP_GROUP_MemExtend_x_64 = 138,
AArch64_OP_GROUP_UImm12Offset_8 = 139,
AArch64_OP_GROUP_MemExtend_w_16 = 140,
AArch64_OP_GROUP_MemExtend_x_16 = 141,
AArch64_OP_GROUP_UImm12Offset_2 = 142,
AArch64_OP_GROUP_MemExtend_w_128 = 143,
AArch64_OP_GROUP_MemExtend_x_128 = 144,
AArch64_OP_GROUP_UImm12Offset_16 = 145,
AArch64_OP_GROUP_MemExtend_w_32 = 146,
AArch64_OP_GROUP_MemExtend_x_32 = 147,
AArch64_OP_GROUP_UImm12Offset_4 = 148,
AArch64_OP_GROUP_Matrix_0 = 149,
AArch64_OP_GROUP_ImmRangeScale_4_3 = 150,
AArch64_OP_GROUP_SIMDType10Operand = 151,
AArch64_OP_GROUP_MRSSystemRegister = 152,
AArch64_OP_GROUP_MSRSystemRegister = 153,
AArch64_OP_GROUP_SystemPStateField = 154,
AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_s = 155,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_s = 156,
AArch64_OP_GROUP_PrefetchOp_0 = 157,
AArch64_OP_GROUP_RPRFMOperand = 158,
AArch64_OP_GROUP_GPR64as32 = 159,
AArch64_OP_GROUP_SysCROperand = 160,
AArch64_OP_GROUP_SyspXzrPair = 161,
AArch64_OP_GROUP_MatrixTileList = 162,
AArch64_OP_GROUP_AdrLabel = 1,
AArch64_OP_GROUP_AdrpLabel = 2,
AArch64_OP_GROUP_BTIHintOp = 3,
AArch64_OP_GROUP_ImplicitlyTypedVectorList = 4,
AArch64_OP_GROUP_InverseCondCode = 5,
AArch64_OP_GROUP_LogicalImm_int16_t = 6,
AArch64_OP_GROUP_LogicalImm_int8_t = 7,
AArch64_OP_GROUP_MatrixIndex_0 = 8,
AArch64_OP_GROUP_MatrixIndex_1 = 9,
AArch64_OP_GROUP_MatrixIndex_8 = 10,
AArch64_OP_GROUP_PSBHintOp = 11,
AArch64_OP_GROUP_PrefetchOp_1 = 12,
AArch64_OP_GROUP_SVELogicalImm_int16_t = 13,
AArch64_OP_GROUP_SVELogicalImm_int32_t = 14,
AArch64_OP_GROUP_SVELogicalImm_int64_t = 15,
AArch64_OP_GROUP_SVERegOp_0 = 16,
AArch64_OP_GROUP_VectorIndex_8 = 17,
AArch64_OP_GROUP_ZPRasFPR_128 = 18,
AArch64_OP_GROUP_Operand = 19,
AArch64_OP_GROUP_SVERegOp_b = 20,
AArch64_OP_GROUP_SVERegOp_d = 21,
AArch64_OP_GROUP_SVERegOp_h = 22,
AArch64_OP_GROUP_SVERegOp_s = 23,
AArch64_OP_GROUP_TypedVectorList_0_d = 24,
AArch64_OP_GROUP_TypedVectorList_0_s = 25,
AArch64_OP_GROUP_VRegOperand = 26,
AArch64_OP_GROUP_TypedVectorList_0_h = 27,
AArch64_OP_GROUP_VectorIndex_1 = 28,
AArch64_OP_GROUP_ImmRangeScale_2_1 = 29,
AArch64_OP_GROUP_AlignedLabel = 30,
AArch64_OP_GROUP_CondCode = 31,
AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_one = 32,
AArch64_OP_GROUP_TypedVectorList_0_b = 33,
AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_zero_AArch64ExactFPImm_one = 34,
AArch64_OP_GROUP_ImmRangeScale_4_3 = 35,
AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_two = 36,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_d = 37,
AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_d = 38,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_d = 39,
AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_s = 40,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_s = 41,
AArch64_OP_GROUP_ImmScale_8 = 42,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_d = 43,
AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_d = 44,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_d = 45,
AArch64_OP_GROUP_ImmScale_2 = 46,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_d = 47,
AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_d = 48,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_d = 49,
AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_s = 50,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_s = 51,
AArch64_OP_GROUP_ImmScale_4 = 52,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_d = 53,
AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_d = 54,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_d = 55,
AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_s = 56,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_s = 57,
AArch64_OP_GROUP_PredicateAsCounter_0 = 58,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_0 = 59,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_0 = 60,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_0 = 61,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_0 = 62,
AArch64_OP_GROUP_SVCROp = 63,
AArch64_OP_GROUP_ImmScale_16 = 64,
AArch64_OP_GROUP_MatrixTile = 65,
AArch64_OP_GROUP_Shifter = 66,
AArch64_OP_GROUP_AddSubImm = 67,
AArch64_OP_GROUP_ShiftedRegister = 68,
AArch64_OP_GROUP_ExtendedRegister = 69,
AArch64_OP_GROUP_ArithExtend = 70,
AArch64_OP_GROUP_Matrix_64 = 71,
AArch64_OP_GROUP_Matrix_32 = 72,
AArch64_OP_GROUP_Imm8OptLsl_uint8_t = 73,
AArch64_OP_GROUP_Imm8OptLsl_uint64_t = 74,
AArch64_OP_GROUP_Imm8OptLsl_uint16_t = 75,
AArch64_OP_GROUP_Imm8OptLsl_uint32_t = 76,
AArch64_OP_GROUP_AdrAdrpLabel = 77,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_s = 78,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_s = 79,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_s = 80,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_s = 81,
AArch64_OP_GROUP_LogicalImm_int32_t = 82,
AArch64_OP_GROUP_LogicalImm_int64_t = 83,
AArch64_OP_GROUP_ZPRasFPR_8 = 84,
AArch64_OP_GROUP_ZPRasFPR_64 = 85,
AArch64_OP_GROUP_ZPRasFPR_16 = 86,
AArch64_OP_GROUP_ZPRasFPR_32 = 87,
AArch64_OP_GROUP_Matrix_16 = 88,
AArch64_OP_GROUP_Imm = 89,
AArch64_OP_GROUP_ImmHex = 90,
AArch64_OP_GROUP_ComplexRotationOp_180_90 = 91,
AArch64_OP_GROUP_GPRSeqPairsClassOperand_32 = 92,
AArch64_OP_GROUP_GPRSeqPairsClassOperand_64 = 93,
AArch64_OP_GROUP_ComplexRotationOp_90_0 = 94,
AArch64_OP_GROUP_SVEPattern = 95,
AArch64_OP_GROUP_PredicateAsCounter_8 = 96,
AArch64_OP_GROUP_SVEVecLenSpecifier = 97,
AArch64_OP_GROUP_PredicateAsCounter_64 = 98,
AArch64_OP_GROUP_PredicateAsCounter_16 = 99,
AArch64_OP_GROUP_PredicateAsCounter_32 = 100,
AArch64_OP_GROUP_Imm8OptLsl_int8_t = 101,
AArch64_OP_GROUP_Imm8OptLsl_int64_t = 102,
AArch64_OP_GROUP_Imm8OptLsl_int16_t = 103,
AArch64_OP_GROUP_Imm8OptLsl_int32_t = 104,
AArch64_OP_GROUP_BarrierOption = 105,
AArch64_OP_GROUP_BarriernXSOption = 106,
AArch64_OP_GROUP_SVERegOp_q = 107,
AArch64_OP_GROUP_MatrixTileVector_0 = 108,
AArch64_OP_GROUP_MatrixTileVector_1 = 109,
AArch64_OP_GROUP_FPImmOperand = 110,
AArch64_OP_GROUP_TypedVectorList_0_q = 111,
AArch64_OP_GROUP_SImm_8 = 112,
AArch64_OP_GROUP_SImm_16 = 113,
AArch64_OP_GROUP_TypedVectorList_16_b = 114,
AArch64_OP_GROUP_PostIncOperand_64 = 115,
AArch64_OP_GROUP_TypedVectorList_1_d = 116,
AArch64_OP_GROUP_PostIncOperand_32 = 117,
AArch64_OP_GROUP_TypedVectorList_2_d = 118,
AArch64_OP_GROUP_TypedVectorList_2_s = 119,
AArch64_OP_GROUP_TypedVectorList_4_h = 120,
AArch64_OP_GROUP_TypedVectorList_4_s = 121,
AArch64_OP_GROUP_TypedVectorList_8_b = 122,
AArch64_OP_GROUP_TypedVectorList_8_h = 123,
AArch64_OP_GROUP_PostIncOperand_16 = 124,
AArch64_OP_GROUP_PostIncOperand_8 = 125,
AArch64_OP_GROUP_ImmScale_32 = 126,
AArch64_OP_GROUP_PostIncOperand_1 = 127,
AArch64_OP_GROUP_PostIncOperand_4 = 128,
AArch64_OP_GROUP_PostIncOperand_2 = 129,
AArch64_OP_GROUP_PostIncOperand_48 = 130,
AArch64_OP_GROUP_PostIncOperand_24 = 131,
AArch64_OP_GROUP_RegWithShiftExtend_0_128_x_0 = 132,
AArch64_OP_GROUP_ImmScale_3 = 133,
AArch64_OP_GROUP_PostIncOperand_3 = 134,
AArch64_OP_GROUP_PostIncOperand_12 = 135,
AArch64_OP_GROUP_PostIncOperand_6 = 136,
AArch64_OP_GROUP_GPR64x8 = 137,
AArch64_OP_GROUP_MemExtend_w_8 = 138,
AArch64_OP_GROUP_MemExtend_x_8 = 139,
AArch64_OP_GROUP_UImm12Offset_1 = 140,
AArch64_OP_GROUP_MemExtend_w_64 = 141,
AArch64_OP_GROUP_MemExtend_x_64 = 142,
AArch64_OP_GROUP_UImm12Offset_8 = 143,
AArch64_OP_GROUP_MemExtend_w_16 = 144,
AArch64_OP_GROUP_MemExtend_x_16 = 145,
AArch64_OP_GROUP_UImm12Offset_2 = 146,
AArch64_OP_GROUP_MemExtend_w_128 = 147,
AArch64_OP_GROUP_MemExtend_x_128 = 148,
AArch64_OP_GROUP_UImm12Offset_16 = 149,
AArch64_OP_GROUP_MemExtend_w_32 = 150,
AArch64_OP_GROUP_MemExtend_x_32 = 151,
AArch64_OP_GROUP_UImm12Offset_4 = 152,
AArch64_OP_GROUP_Matrix_0 = 153,
AArch64_OP_GROUP_TypedVectorList_0_0 = 154,
AArch64_OP_GROUP_SIMDType10Operand = 155,
AArch64_OP_GROUP_MRSSystemRegister = 156,
AArch64_OP_GROUP_MSRSystemRegister = 157,
AArch64_OP_GROUP_SystemPStateField = 158,
AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_s = 159,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_s = 160,
AArch64_OP_GROUP_PrefetchOp_0 = 161,
AArch64_OP_GROUP_RPRFMOperand = 162,
AArch64_OP_GROUP_GPR64as32 = 163,
AArch64_OP_GROUP_SysCROperand = 164,
AArch64_OP_GROUP_SyspXzrPair = 165,
AArch64_OP_GROUP_MatrixTileList = 166,

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arch/AArch64/AArch64GenDisassemblerTables.inc
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arch/AArch64/AArch64GenInstrInfo.inc
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arch/AArch64/AArch64GenRegisterInfo.inc
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arch/AArch64/AArch64GenSubtargetInfo.inc
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@ -1,6 +1,6 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
@ -16,248 +16,281 @@
enum {
AArch64_FeatureAES = 0,
AArch64_FeatureAM = 1,
AArch64_FeatureAMVS = 2,
AArch64_FeatureAggressiveFMA = 3,
AArch64_FeatureAll = 4,
AArch64_FeatureAltFPCmp = 5,
AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 6,
AArch64_FeatureAppleA7SysReg = 7,
AArch64_FeatureArithmeticBccFusion = 8,
AArch64_FeatureArithmeticCbzFusion = 9,
AArch64_FeatureAscendStoreAddress = 10,
AArch64_FeatureB16B16 = 11,
AArch64_FeatureBF16 = 12,
AArch64_FeatureBRBE = 13,
AArch64_FeatureBalanceFPOps = 14,
AArch64_FeatureBranchTargetId = 15,
AArch64_FeatureCCIDX = 16,
AArch64_FeatureCCPP = 17,
AArch64_FeatureCLRBHB = 18,
AArch64_FeatureCONTEXTIDREL2 = 19,
AArch64_FeatureCRC = 20,
AArch64_FeatureCSSC = 21,
AArch64_FeatureCacheDeepPersist = 22,
AArch64_FeatureCallSavedX8 = 23,
AArch64_FeatureCallSavedX9 = 24,
AArch64_FeatureCallSavedX10 = 25,
AArch64_FeatureCallSavedX11 = 26,
AArch64_FeatureCallSavedX12 = 27,
AArch64_FeatureCallSavedX13 = 28,
AArch64_FeatureCallSavedX14 = 29,
AArch64_FeatureCallSavedX15 = 30,
AArch64_FeatureCallSavedX18 = 31,
AArch64_FeatureCmpBccFusion = 32,
AArch64_FeatureComplxNum = 33,
AArch64_FeatureCrypto = 34,
AArch64_FeatureCustomCheapAsMoveHandling = 35,
AArch64_FeatureD128 = 36,
AArch64_FeatureDIT = 37,
AArch64_FeatureDisableLatencySchedHeuristic = 38,
AArch64_FeatureDotProd = 39,
AArch64_FeatureEL2VMSA = 40,
AArch64_FeatureEL3 = 41,
AArch64_FeatureETE = 42,
AArch64_FeatureEnableSelectOptimize = 43,
AArch64_FeatureEnhancedCounterVirtualization = 44,
AArch64_FeatureExperimentalZeroingPseudos = 45,
AArch64_FeatureExynosCheapAsMoveHandling = 46,
AArch64_FeatureFMV = 47,
AArch64_FeatureFP16FML = 48,
AArch64_FeatureFPARMv8 = 49,
AArch64_FeatureFRInt3264 = 50,
AArch64_FeatureFineGrainedTraps = 51,
AArch64_FeatureFixCortexA53_835769 = 52,
AArch64_FeatureFlagM = 53,
AArch64_FeatureForce32BitJumpTables = 54,
AArch64_FeatureFullFP16 = 55,
AArch64_FeatureFuseAES = 56,
AArch64_FeatureFuseAddress = 57,
AArch64_FeatureFuseAdrpAdd = 58,
AArch64_FeatureFuseArithmeticLogic = 59,
AArch64_FeatureFuseCCSelect = 60,
AArch64_FeatureFuseCryptoEOR = 61,
AArch64_FeatureFuseLiterals = 62,
AArch64_FeatureHBC = 63,
AArch64_FeatureHCX = 64,
AArch64_FeatureHardenSlsBlr = 65,
AArch64_FeatureHardenSlsNoComdat = 66,
AArch64_FeatureHardenSlsRetBr = 67,
AArch64_FeatureITE = 68,
AArch64_FeatureJS = 69,
AArch64_FeatureLOR = 70,
AArch64_FeatureLS64 = 71,
AArch64_FeatureLSE = 72,
AArch64_FeatureLSE2 = 73,
AArch64_FeatureLSE128 = 74,
AArch64_FeatureLSLFast = 75,
AArch64_FeatureMEC = 76,
AArch64_FeatureMOPS = 77,
AArch64_FeatureMPAM = 78,
AArch64_FeatureMTE = 79,
AArch64_FeatureMatMulFP32 = 80,
AArch64_FeatureMatMulFP64 = 81,
AArch64_FeatureMatMulInt8 = 82,
AArch64_FeatureNEON = 83,
AArch64_FeatureNMI = 84,
AArch64_FeatureNV = 85,
AArch64_FeatureNoBTIAtReturnTwice = 86,
AArch64_FeatureNoNegativeImmediates = 87,
AArch64_FeatureNoZCZeroingFP = 88,
AArch64_FeatureOutlineAtomics = 89,
AArch64_FeaturePAN = 90,
AArch64_FeaturePAN_RWV = 91,
AArch64_FeaturePAuth = 92,
AArch64_FeaturePRFM_SLC = 93,
AArch64_FeaturePerfMon = 94,
AArch64_FeaturePostRAScheduler = 95,
AArch64_FeaturePredRes = 96,
AArch64_FeaturePredictableSelectIsExpensive = 97,
AArch64_FeaturePsUAO = 98,
AArch64_FeatureRAS = 99,
AArch64_FeatureRASv2 = 100,
AArch64_FeatureRCPC = 101,
AArch64_FeatureRCPC3 = 102,
AArch64_FeatureRCPC_IMMO = 103,
AArch64_FeatureRDM = 104,
AArch64_FeatureRME = 105,
AArch64_FeatureRandGen = 106,
AArch64_FeatureReserveX1 = 107,
AArch64_FeatureReserveX2 = 108,
AArch64_FeatureReserveX3 = 109,
AArch64_FeatureReserveX4 = 110,
AArch64_FeatureReserveX5 = 111,
AArch64_FeatureReserveX6 = 112,
AArch64_FeatureReserveX7 = 113,
AArch64_FeatureReserveX9 = 114,
AArch64_FeatureReserveX10 = 115,
AArch64_FeatureReserveX11 = 116,
AArch64_FeatureReserveX12 = 117,
AArch64_FeatureReserveX13 = 118,
AArch64_FeatureReserveX14 = 119,
AArch64_FeatureReserveX15 = 120,
AArch64_FeatureReserveX18 = 121,
AArch64_FeatureReserveX20 = 122,
AArch64_FeatureReserveX21 = 123,
AArch64_FeatureReserveX22 = 124,
AArch64_FeatureReserveX23 = 125,
AArch64_FeatureReserveX24 = 126,
AArch64_FeatureReserveX25 = 127,
AArch64_FeatureReserveX26 = 128,
AArch64_FeatureReserveX27 = 129,
AArch64_FeatureReserveX28 = 130,
AArch64_FeatureReserveX30 = 131,
AArch64_FeatureSB = 132,
AArch64_FeatureSEL2 = 133,
AArch64_FeatureSHA2 = 134,
AArch64_FeatureSHA3 = 135,
AArch64_FeatureSM4 = 136,
AArch64_FeatureSME = 137,
AArch64_FeatureSME2 = 138,
AArch64_FeatureSME2p1 = 139,
AArch64_FeatureSMEF16F16 = 140,
AArch64_FeatureSMEF64F64 = 141,
AArch64_FeatureSMEI16I64 = 142,
AArch64_FeatureSPE = 143,
AArch64_FeatureSPECRES2 = 144,
AArch64_FeatureSPE_EEF = 145,
AArch64_FeatureSSBS = 146,
AArch64_FeatureSVE = 147,
AArch64_FeatureSVE2 = 148,
AArch64_FeatureSVE2AES = 149,
AArch64_FeatureSVE2BitPerm = 150,
AArch64_FeatureSVE2SHA3 = 151,
AArch64_FeatureSVE2SM4 = 152,
AArch64_FeatureSVE2p1 = 153,
AArch64_FeatureSlowMisaligned128Store = 154,
AArch64_FeatureSlowPaired128 = 155,
AArch64_FeatureSlowSTRQro = 156,
AArch64_FeatureSpecRestrict = 157,
AArch64_FeatureStrictAlign = 158,
AArch64_FeatureTHE = 159,
AArch64_FeatureTLB_RMI = 160,
AArch64_FeatureTME = 161,
AArch64_FeatureTRACEV8_4 = 162,
AArch64_FeatureTRBE = 163,
AArch64_FeatureTaggedGlobals = 164,
AArch64_FeatureUseEL1ForTP = 165,
AArch64_FeatureUseEL2ForTP = 166,
AArch64_FeatureUseEL3ForTP = 167,
AArch64_FeatureUseRSqrt = 168,
AArch64_FeatureUseScalarIncVL = 169,
AArch64_FeatureVH = 170,
AArch64_FeatureWFxT = 171,
AArch64_FeatureXS = 172,
AArch64_FeatureZCRegMove = 173,
AArch64_FeatureZCZeroing = 174,
AArch64_FeatureZCZeroingFPWorkaround = 175,
AArch64_FeatureZCZeroingGP = 176,
AArch64_HasV8_0aOps = 177,
AArch64_HasV8_0rOps = 178,
AArch64_HasV8_1aOps = 179,
AArch64_HasV8_2aOps = 180,
AArch64_HasV8_3aOps = 181,
AArch64_HasV8_4aOps = 182,
AArch64_HasV8_5aOps = 183,
AArch64_HasV8_6aOps = 184,
AArch64_HasV8_7aOps = 185,
AArch64_HasV8_8aOps = 186,
AArch64_HasV8_9aOps = 187,
AArch64_HasV9_0aOps = 188,
AArch64_HasV9_1aOps = 189,
AArch64_HasV9_2aOps = 190,
AArch64_HasV9_3aOps = 191,
AArch64_HasV9_4aOps = 192,
AArch64_TuneA35 = 193,
AArch64_TuneA53 = 194,
AArch64_TuneA55 = 195,
AArch64_TuneA57 = 196,
AArch64_TuneA64FX = 197,
AArch64_TuneA65 = 198,
AArch64_TuneA72 = 199,
AArch64_TuneA73 = 200,
AArch64_TuneA75 = 201,
AArch64_TuneA76 = 202,
AArch64_TuneA77 = 203,
AArch64_TuneA78 = 204,
AArch64_TuneA78C = 205,
AArch64_TuneA510 = 206,
AArch64_TuneA710 = 207,
AArch64_TuneA715 = 208,
AArch64_TuneAmpere1 = 209,
AArch64_TuneAmpere1A = 210,
AArch64_TuneAppleA7 = 211,
AArch64_TuneAppleA10 = 212,
AArch64_TuneAppleA11 = 213,
AArch64_TuneAppleA12 = 214,
AArch64_TuneAppleA13 = 215,
AArch64_TuneAppleA14 = 216,
AArch64_TuneAppleA15 = 217,
AArch64_TuneAppleA16 = 218,
AArch64_TuneCarmel = 219,
AArch64_TuneExynosM3 = 220,
AArch64_TuneExynosM4 = 221,
AArch64_TuneFalkor = 222,
AArch64_TuneKryo = 223,
AArch64_TuneNeoverse512TVB = 224,
AArch64_TuneNeoverseE1 = 225,
AArch64_TuneNeoverseN1 = 226,
AArch64_TuneNeoverseN2 = 227,
AArch64_TuneNeoverseV1 = 228,
AArch64_TuneNeoverseV2 = 229,
AArch64_TuneR82 = 230,
AArch64_TuneSaphira = 231,
AArch64_TuneTSV110 = 232,
AArch64_TuneThunderX = 233,
AArch64_TuneThunderX2T99 = 234,
AArch64_TuneThunderX3T110 = 235,
AArch64_TuneThunderXT81 = 236,
AArch64_TuneThunderXT83 = 237,
AArch64_TuneThunderXT88 = 238,
AArch64_TuneX1 = 239,
AArch64_TuneX2 = 240,
AArch64_TuneX3 = 241,
AArch64_NumSubtargetFeatures = 242
AArch64_FeatureALULSLFast = 1,
AArch64_FeatureAM = 2,
AArch64_FeatureAMVS = 3,
AArch64_FeatureAddrLSLFast = 4,
AArch64_FeatureAggressiveFMA = 5,
AArch64_FeatureAll = 6,
AArch64_FeatureAltFPCmp = 7,
AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 8,
AArch64_FeatureAppleA7SysReg = 9,
AArch64_FeatureArithmeticBccFusion = 10,
AArch64_FeatureArithmeticCbzFusion = 11,
AArch64_FeatureAscendStoreAddress = 12,
AArch64_FeatureB16B16 = 13,
AArch64_FeatureBF16 = 14,
AArch64_FeatureBRBE = 15,
AArch64_FeatureBalanceFPOps = 16,
AArch64_FeatureBranchTargetId = 17,
AArch64_FeatureCCIDX = 18,
AArch64_FeatureCCPP = 19,
AArch64_FeatureCHK = 20,
AArch64_FeatureCLRBHB = 21,
AArch64_FeatureCONTEXTIDREL2 = 22,
AArch64_FeatureCPA = 23,
AArch64_FeatureCRC = 24,
AArch64_FeatureCSSC = 25,
AArch64_FeatureCacheDeepPersist = 26,
AArch64_FeatureCallSavedX8 = 27,
AArch64_FeatureCallSavedX9 = 28,
AArch64_FeatureCallSavedX10 = 29,
AArch64_FeatureCallSavedX11 = 30,
AArch64_FeatureCallSavedX12 = 31,
AArch64_FeatureCallSavedX13 = 32,
AArch64_FeatureCallSavedX14 = 33,
AArch64_FeatureCallSavedX15 = 34,
AArch64_FeatureCallSavedX18 = 35,
AArch64_FeatureCmpBccFusion = 36,
AArch64_FeatureComplxNum = 37,
AArch64_FeatureCrypto = 38,
AArch64_FeatureD128 = 39,
AArch64_FeatureDIT = 40,
AArch64_FeatureDisableLatencySchedHeuristic = 41,
AArch64_FeatureDisableLdp = 42,
AArch64_FeatureDisableStp = 43,
AArch64_FeatureDotProd = 44,
AArch64_FeatureEL2VMSA = 45,
AArch64_FeatureEL3 = 46,
AArch64_FeatureETE = 47,
AArch64_FeatureEnableSelectOptimize = 48,
AArch64_FeatureEnhancedCounterVirtualization = 49,
AArch64_FeatureExperimentalZeroingPseudos = 50,
AArch64_FeatureExynosCheapAsMoveHandling = 51,
AArch64_FeatureFAMINMAX = 52,
AArch64_FeatureFMV = 53,
AArch64_FeatureFP8 = 54,
AArch64_FeatureFP8DOT2 = 55,
AArch64_FeatureFP8DOT4 = 56,
AArch64_FeatureFP8FMA = 57,
AArch64_FeatureFP16FML = 58,
AArch64_FeatureFPARMv8 = 59,
AArch64_FeatureFPMR = 60,
AArch64_FeatureFRInt3264 = 61,
AArch64_FeatureFineGrainedTraps = 62,
AArch64_FeatureFixCortexA53_835769 = 63,
AArch64_FeatureFlagM = 64,
AArch64_FeatureForce32BitJumpTables = 65,
AArch64_FeatureFullFP16 = 66,
AArch64_FeatureFuseAES = 67,
AArch64_FeatureFuseAddSub2RegAndConstOne = 68,
AArch64_FeatureFuseAddress = 69,
AArch64_FeatureFuseAdrpAdd = 70,
AArch64_FeatureFuseArithmeticLogic = 71,
AArch64_FeatureFuseCCSelect = 72,
AArch64_FeatureFuseCryptoEOR = 73,
AArch64_FeatureFuseLiterals = 74,
AArch64_FeatureGCS = 75,
AArch64_FeatureHBC = 76,
AArch64_FeatureHCX = 77,
AArch64_FeatureHardenSlsBlr = 78,
AArch64_FeatureHardenSlsNoComdat = 79,
AArch64_FeatureHardenSlsRetBr = 80,
AArch64_FeatureITE = 81,
AArch64_FeatureJS = 82,
AArch64_FeatureLOR = 83,
AArch64_FeatureLS64 = 84,
AArch64_FeatureLSE = 85,
AArch64_FeatureLSE2 = 86,
AArch64_FeatureLSE128 = 87,
AArch64_FeatureLUT = 88,
AArch64_FeatureLdpAlignedOnly = 89,
AArch64_FeatureMEC = 90,
AArch64_FeatureMOPS = 91,
AArch64_FeatureMPAM = 92,
AArch64_FeatureMTE = 93,
AArch64_FeatureMatMulFP32 = 94,
AArch64_FeatureMatMulFP64 = 95,
AArch64_FeatureMatMulInt8 = 96,
AArch64_FeatureNEON = 97,
AArch64_FeatureNMI = 98,
AArch64_FeatureNV = 99,
AArch64_FeatureNoBTIAtReturnTwice = 100,
AArch64_FeatureNoNegativeImmediates = 101,
AArch64_FeatureNoSVEFPLD1R = 102,
AArch64_FeatureNoZCZeroingFP = 103,
AArch64_FeatureOutlineAtomics = 104,
AArch64_FeaturePAN = 105,
AArch64_FeaturePAN_RWV = 106,
AArch64_FeaturePAuth = 107,
AArch64_FeaturePAuthLR = 108,
AArch64_FeaturePRFM_SLC = 109,
AArch64_FeaturePerfMon = 110,
AArch64_FeaturePostRAScheduler = 111,
AArch64_FeaturePredRes = 112,
AArch64_FeaturePredictableSelectIsExpensive = 113,
AArch64_FeaturePsUAO = 114,
AArch64_FeatureRAS = 115,
AArch64_FeatureRASv2 = 116,
AArch64_FeatureRCPC = 117,
AArch64_FeatureRCPC3 = 118,
AArch64_FeatureRCPC_IMMO = 119,
AArch64_FeatureRDM = 120,
AArch64_FeatureRME = 121,
AArch64_FeatureRandGen = 122,
AArch64_FeatureReserveX1 = 123,
AArch64_FeatureReserveX2 = 124,
AArch64_FeatureReserveX3 = 125,
AArch64_FeatureReserveX4 = 126,
AArch64_FeatureReserveX5 = 127,
AArch64_FeatureReserveX6 = 128,
AArch64_FeatureReserveX7 = 129,
AArch64_FeatureReserveX9 = 130,
AArch64_FeatureReserveX10 = 131,
AArch64_FeatureReserveX11 = 132,
AArch64_FeatureReserveX12 = 133,
AArch64_FeatureReserveX13 = 134,
AArch64_FeatureReserveX14 = 135,
AArch64_FeatureReserveX15 = 136,
AArch64_FeatureReserveX18 = 137,
AArch64_FeatureReserveX20 = 138,
AArch64_FeatureReserveX21 = 139,
AArch64_FeatureReserveX22 = 140,
AArch64_FeatureReserveX23 = 141,
AArch64_FeatureReserveX24 = 142,
AArch64_FeatureReserveX25 = 143,
AArch64_FeatureReserveX26 = 144,
AArch64_FeatureReserveX27 = 145,
AArch64_FeatureReserveX28 = 146,
AArch64_FeatureReserveX30 = 147,
AArch64_FeatureSB = 148,
AArch64_FeatureSEL2 = 149,
AArch64_FeatureSHA2 = 150,
AArch64_FeatureSHA3 = 151,
AArch64_FeatureSM4 = 152,
AArch64_FeatureSME = 153,
AArch64_FeatureSME2 = 154,
AArch64_FeatureSME2p1 = 155,
AArch64_FeatureSMEF8F16 = 156,
AArch64_FeatureSMEF8F32 = 157,
AArch64_FeatureSMEF16F16 = 158,
AArch64_FeatureSMEF64F64 = 159,
AArch64_FeatureSMEFA64 = 160,
AArch64_FeatureSMEI16I64 = 161,
AArch64_FeatureSME_LUTv2 = 162,
AArch64_FeatureSPE = 163,
AArch64_FeatureSPECRES2 = 164,
AArch64_FeatureSPE_EEF = 165,
AArch64_FeatureSSBS = 166,
AArch64_FeatureSSVE_FP8DOT2 = 167,
AArch64_FeatureSSVE_FP8DOT4 = 168,
AArch64_FeatureSSVE_FP8FMA = 169,
AArch64_FeatureSVE = 170,
AArch64_FeatureSVE2 = 171,
AArch64_FeatureSVE2AES = 172,
AArch64_FeatureSVE2BitPerm = 173,
AArch64_FeatureSVE2SHA3 = 174,
AArch64_FeatureSVE2SM4 = 175,
AArch64_FeatureSVE2p1 = 176,
AArch64_FeatureSlowMisaligned128Store = 177,
AArch64_FeatureSlowPaired128 = 178,
AArch64_FeatureSlowSTRQro = 179,
AArch64_FeatureSpecRestrict = 180,
AArch64_FeatureStorePairSuppress = 181,
AArch64_FeatureStpAlignedOnly = 182,
AArch64_FeatureStrictAlign = 183,
AArch64_FeatureTHE = 184,
AArch64_FeatureTLBIW = 185,
AArch64_FeatureTLB_RMI = 186,
AArch64_FeatureTME = 187,
AArch64_FeatureTRACEV8_4 = 188,
AArch64_FeatureTRBE = 189,
AArch64_FeatureTaggedGlobals = 190,
AArch64_FeatureUseEL1ForTP = 191,
AArch64_FeatureUseEL2ForTP = 192,
AArch64_FeatureUseEL3ForTP = 193,
AArch64_FeatureUseROEL0ForTP = 194,
AArch64_FeatureUseRSqrt = 195,
AArch64_FeatureUseScalarIncVL = 196,
AArch64_FeatureVH = 197,
AArch64_FeatureWFxT = 198,
AArch64_FeatureXS = 199,
AArch64_FeatureZCRegMove = 200,
AArch64_FeatureZCZeroing = 201,
AArch64_FeatureZCZeroingFPWorkaround = 202,
AArch64_FeatureZCZeroingGP = 203,
AArch64_HasV8_0aOps = 204,
AArch64_HasV8_0rOps = 205,
AArch64_HasV8_1aOps = 206,
AArch64_HasV8_2aOps = 207,
AArch64_HasV8_3aOps = 208,
AArch64_HasV8_4aOps = 209,
AArch64_HasV8_5aOps = 210,
AArch64_HasV8_6aOps = 211,
AArch64_HasV8_7aOps = 212,
AArch64_HasV8_8aOps = 213,
AArch64_HasV8_9aOps = 214,
AArch64_HasV9_0aOps = 215,
AArch64_HasV9_1aOps = 216,
AArch64_HasV9_2aOps = 217,
AArch64_HasV9_3aOps = 218,
AArch64_HasV9_4aOps = 219,
AArch64_HasV9_5aOps = 220,
AArch64_TuneA35 = 221,
AArch64_TuneA53 = 222,
AArch64_TuneA55 = 223,
AArch64_TuneA57 = 224,
AArch64_TuneA64FX = 225,
AArch64_TuneA65 = 226,
AArch64_TuneA72 = 227,
AArch64_TuneA73 = 228,
AArch64_TuneA75 = 229,
AArch64_TuneA76 = 230,
AArch64_TuneA77 = 231,
AArch64_TuneA78 = 232,
AArch64_TuneA78C = 233,
AArch64_TuneA510 = 234,
AArch64_TuneA520 = 235,
AArch64_TuneA710 = 236,
AArch64_TuneA715 = 237,
AArch64_TuneA720 = 238,
AArch64_TuneAmpere1 = 239,
AArch64_TuneAmpere1A = 240,
AArch64_TuneAmpere1B = 241,
AArch64_TuneAppleA7 = 242,
AArch64_TuneAppleA10 = 243,
AArch64_TuneAppleA11 = 244,
AArch64_TuneAppleA12 = 245,
AArch64_TuneAppleA13 = 246,
AArch64_TuneAppleA14 = 247,
AArch64_TuneAppleA15 = 248,
AArch64_TuneAppleA16 = 249,
AArch64_TuneAppleA17 = 250,
AArch64_TuneCarmel = 251,
AArch64_TuneExynosM3 = 252,
AArch64_TuneExynosM4 = 253,
AArch64_TuneFalkor = 254,
AArch64_TuneKryo = 255,
AArch64_TuneNeoverse512TVB = 256,
AArch64_TuneNeoverseE1 = 257,
AArch64_TuneNeoverseN1 = 258,
AArch64_TuneNeoverseN2 = 259,
AArch64_TuneNeoverseV1 = 260,
AArch64_TuneNeoverseV2 = 261,
AArch64_TuneR82 = 262,
AArch64_TuneSaphira = 263,
AArch64_TuneTSV110 = 264,
AArch64_TuneThunderX = 265,
AArch64_TuneThunderX2T99 = 266,
AArch64_TuneThunderX3T110 = 267,
AArch64_TuneThunderXT81 = 268,
AArch64_TuneThunderXT83 = 269,
AArch64_TuneThunderXT88 = 270,
AArch64_TuneX1 = 271,
AArch64_TuneX2 = 272,
AArch64_TuneX3 = 273,
AArch64_TuneX4 = 274,
AArch64_NumSubtargetFeatures = 275
};
#endif // GET_SUBTARGETINFO_ENUM

6401
arch/AArch64/AArch64GenSystemOperands.inc
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File diff suppressed because it is too large Load Diff

1474
arch/AArch64/AArch64InstPrinter.c
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File diff suppressed because it is too large Load Diff

103
arch/AArch64/AArch64InstPrinter.h
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@ -27,16 +27,16 @@
#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "AArch64Mapping.h"
#include "../../MCInst.h"
#include "../../MCInstPrinter.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInstPrinter.h"
#include "../../SStream.h"
#include "../../utils.h"
@ -44,8 +44,7 @@
#define CONCAT_(a, b) a##_##b
#define CHAR(c) #c[0]
void printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O);
void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
void printRegName(SStream *OS, unsigned Reg);
void printRegNameAlt(SStream *OS, unsigned Reg, unsigned AltIdx);
// Autogenerated by tblgen.
@ -62,8 +61,7 @@ void printImmHex(MCInst *MI, unsigned OpNo, SStream *O);
DECLARE_printSImm(16);
DECLARE_printSImm(8);
#define DECLARE_printImmSVE(T) \
void CONCAT(printImmSVE, T)(T Val, SStream *O);
#define DECLARE_printImmSVE(T) void CONCAT(printImmSVE, T)(T Val, SStream * O);
DECLARE_printImmSVE(int16_t);
DECLARE_printImmSVE(int8_t);
DECLARE_printImmSVE(int64_t);
@ -75,10 +73,12 @@ DECLARE_printImmSVE(uint32_t);
void printPostIncOperand(MCInst *MI, unsigned OpNo, unsigned Imm, SStream *O);
#define DEFINE_printPostIncOperand(Amount) \
static inline void CONCAT(printPostIncOperand, Amount)(MCInst * MI, unsigned OpNo, \
SStream *O) \
static inline void CONCAT(printPostIncOperand, Amount)( \
MCInst * MI, unsigned OpNo, SStream *O) \
{ \
add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), OpNo, Amount); \
add_cs_detail(MI, \
CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
OpNo, Amount); \
printPostIncOperand(MI, OpNo, Amount, O); \
}
DEFINE_printPostIncOperand(64);
@ -98,7 +98,8 @@ void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O);
void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printLogicalImm(T) \
void CONCAT(printLogicalImm, T)(MCInst * MI, unsigned OpNum, SStream *O);
void CONCAT(printLogicalImm, T)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printLogicalImm(int64_t);
DECLARE_printLogicalImm(int32_t);
DECLARE_printLogicalImm(int8_t);
@ -110,17 +111,17 @@ void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O);
void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O);
void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
unsigned Width);
unsigned Width);
void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
unsigned Width);
unsigned Width);
#define DEFINE_printMemExtend(SrcRegKind, Width) \
static inline void CONCAT(printMemExtend, CONCAT(SrcRegKind, Width))( \
MCInst * MI, unsigned OpNum, SStream *O) \
{ \
add_cs_detail(MI, \
CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, \
SrcRegKind), \
Width), \
add_cs_detail( \
MI, \
CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
Width), \
OpNum, CHAR(SrcRegKind), Width); \
printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
}
@ -136,10 +137,10 @@ DEFINE_printMemExtend(w, 32);
DEFINE_printMemExtend(x, 32);
#define DECLARE_printRegWithShiftExtend(SignedExtend, ExtWidth, SrcRegKind, \
Suffix) \
void CONCAT( \
printRegWithShiftExtend, \
CONCAT(SignedExtend, CONCAT(ExtWidth, CONCAT(SrcRegKind, Suffix))))( \
Suffix) \
void CONCAT(printRegWithShiftExtend, \
CONCAT(SignedExtend, \
CONCAT(ExtWidth, CONCAT(SrcRegKind, Suffix))))( \
MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printRegWithShiftExtend(false, 8, x, d);
DECLARE_printRegWithShiftExtend(true, 8, w, d);
@ -174,16 +175,16 @@ DECLARE_printRegWithShiftExtend(false, 128, x, 0);
void printCondCode(MCInst *MI, unsigned OpNum, SStream *O);
void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O);
void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
SStream *O);
SStream *O);
void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
#define DEFINE_printUImm12Offset(Scale) \
static inline void CONCAT(printUImm12Offset, Scale)(MCInst * MI, unsigned OpNum, \
SStream *O) \
static inline void CONCAT(printUImm12Offset, Scale)( \
MCInst * MI, unsigned OpNum, SStream *O) \
{ \
add_cs_detail( \
MI, CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
OpNum, Scale); \
add_cs_detail(MI, \
CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
OpNum, Scale); \
printUImm12Offset(MI, OpNum, Scale, O); \
}
DEFINE_printUImm12Offset(1);
@ -194,7 +195,8 @@ DEFINE_printUImm12Offset(4);
void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printImmScale(Scale) \
void CONCAT(printImmScale, Scale)(MCInst * MI, unsigned OpNum, SStream *O);
void CONCAT(printImmScale, Scale)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printImmScale(8);
DECLARE_printImmScale(2);
DECLARE_printImmScale(4);
@ -209,8 +211,8 @@ DECLARE_printImmRangeScale(2, 1);
DECLARE_printImmRangeScale(4, 3);
#define DECLARE_printPrefetchOp(IsSVEPrefetch) \
void CONCAT(printPrefetchOp, IsSVEPrefetch)( \
MCInst * MI, unsigned OpNum, SStream *O);
void CONCAT(printPrefetchOp, \
IsSVEPrefetch)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printPrefetchOp(true);
DECLARE_printPrefetchOp(false);
@ -218,7 +220,7 @@ void printRPRFMOperand(MCInst *MI, unsigned OpNum, SStream *O);
void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O);
void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O);
void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
const char *LayoutSuffix);
const char *LayoutSuffix);
void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O);
/// (i.e. attached to the instruction rather than the registers).
/// Print a list of vector registers where the type suffix is implicit
@ -239,16 +241,16 @@ DECLARE_printTypedVectorList(4, h);
DECLARE_printTypedVectorList(4, s);
DECLARE_printTypedVectorList(8, b);
DECLARE_printTypedVectorList(8, h);
DECLARE_printTypedVectorList(0, 0);
#define DECLARE_printVectorIndex(Scale) \
void CONCAT(printVectorIndex, \
Scale)(MCInst * MI, unsigned OpNum, SStream *O);
void CONCAT(printVectorIndex, Scale)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printVectorIndex(1);
DECLARE_printVectorIndex(8);
void printMatrixIndex(MCInst *MI, unsigned OpNum, SStream *O);
void printAdrLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
void printAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
SStream *O);
void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
void printBarriernXSOption(MCInst *MI, unsigned OpNum, SStream *O);
void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
@ -256,8 +258,8 @@ void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O);
void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printPredicateAsCounter(EltSize) \
void CONCAT(printPredicateAsCounter, EltSize)(MCInst * MI, unsigned OpNum, \
SStream *O);
void CONCAT(printPredicateAsCounter, \
EltSize)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printPredicateAsCounter(8);
DECLARE_printPredicateAsCounter(64);
DECLARE_printPredicateAsCounter(16);
@ -266,12 +268,13 @@ DECLARE_printPredicateAsCounter(0);
#define DECLARE_printGPRSeqPairsClassOperand(size) \
void CONCAT(printGPRSeqPairsClassOperand, \
size)(MCInst * MI, unsigned OpNum, SStream *O);
size)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printGPRSeqPairsClassOperand(32);
DECLARE_printGPRSeqPairsClassOperand(64);
#define DECLARE_printImm8OptLsl(T) \
void CONCAT(printImm8OptLsl, T)(MCInst * MI, unsigned OpNum, SStream *O);
void CONCAT(printImm8OptLsl, T)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printImm8OptLsl(int16_t);
DECLARE_printImm8OptLsl(int8_t);
DECLARE_printImm8OptLsl(int64_t);
@ -282,7 +285,8 @@ DECLARE_printImm8OptLsl(uint64_t);
DECLARE_printImm8OptLsl(uint32_t);
#define DECLARE_printSVELogicalImm(T) \
void CONCAT(printSVELogicalImm, T)(MCInst * MI, unsigned OpNum, SStream *O);
void CONCAT(printSVELogicalImm, T)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printSVELogicalImm(int16_t);
DECLARE_printSVELogicalImm(int32_t);
DECLARE_printSVELogicalImm(int64_t);
@ -291,13 +295,14 @@ void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O);
void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printMatrixTileVector(IsVertical) \
void CONCAT(printMatrixTileVector, \
IsVertical)(MCInst * MI, unsigned OpNum, SStream *O);
IsVertical)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printMatrixTileVector(0);
DECLARE_printMatrixTileVector(1);
void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printMatrix(EltSize) \
void CONCAT(printMatrix, EltSize)(MCInst * MI, unsigned OpNum, SStream *O);
void CONCAT(printMatrix, EltSize)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printMatrix(64);
DECLARE_printMatrix(32);
DECLARE_printMatrix(16);
@ -306,7 +311,7 @@ DECLARE_printMatrix(0);
void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printSVERegOp(char) \
void CONCAT(printSVERegOp, char)(MCInst * MI, unsigned OpNum, \
SStream *O);
SStream *O);
DECLARE_printSVERegOp(b);
DECLARE_printSVERegOp(d);
DECLARE_printSVERegOp(h);
@ -318,7 +323,8 @@ void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O);
void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O);
void printSyspXzrPair(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printZPRasFPR(Width) \
void CONCAT(printZPRasFPR, Width)(MCInst * MI, unsigned OpNum, SStream *O);
void CONCAT(printZPRasFPR, Width)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printZPRasFPR(8);
DECLARE_printZPRasFPR(64);
DECLARE_printZPRasFPR(16);
@ -332,7 +338,12 @@ DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_one);
DECLARE_printExactFPImm(AArch64ExactFPImm_zero, AArch64ExactFPImm_one);
DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_two);
;
#define DECLARE_printMatrixIndex(Scale) \
void CONCAT(printMatrixIndex, Scale)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printMatrixIndex(8);
DECLARE_printMatrixIndex(0);
DECLARE_printMatrixIndex(1);
// end namespace llvm

10
arch/AArch64/AArch64Linkage.h
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@ -12,10 +12,12 @@
#include "../../SStream.h"
#include "capstone/capstone.h"
DecodeStatus AArch64_LLVM_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
MCInst *MI, uint16_t *Size, uint64_t Address,
void *Info);
DecodeStatus AArch64_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
size_t ByteLen, MCInst *MI,
uint16_t *Size, uint64_t Address,
void *Info);
const char *AArch64_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
void AArch64_LLVM_printInstruction(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
void AArch64_LLVM_printInstruction(MCInst *MI, SStream *O,
void * /* MCRegisterInfo* */ info);
#endif // CS_AARCH64_LINKAGE_H

1811
arch/AArch64/AArch64Mapping.c
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File diff suppressed because it is too large Load Diff

40
arch/AArch64/AArch64Mapping.h
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@ -8,8 +8,6 @@
#include "../../MCInst.h"
#include "../../SStream.h"
#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0]))
typedef enum {
#include "AArch64GenCSOpGroup.inc"
} aarch64_op_group;
@ -25,14 +23,14 @@ const char *AArch64_insn_name(csh handle, unsigned int id);
const char *AArch64_group_name(csh handle, unsigned int id);
void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
void AArch64_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
va_list args);
va_list args);
static inline void add_cs_detail(MCInst *MI,
int /* aarch64_op_group */ op_group, ...)
int /* aarch64_op_group */ op_group, ...)
{
if (!MI->flat_insn->detail)
return;
@ -49,26 +47,36 @@ void AArch64_init_cs_detail(MCInst *MI);
void AArch64_set_instr_map_data(MCInst *MI);
bool AArch64_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
void AArch64_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
void AArch64_set_detail_op_reg(MCInst *MI, unsigned OpNum, aarch64_reg Reg);
void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum, aarch64_op_type ImmType,
int64_t Imm);
void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum,
aarch64_op_type ImmType, int64_t Imm);
void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum,
int64_t FirstImm, int64_t offset);
int64_t FirstImm, int64_t offset);
void AArch64_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val);
void AArch64_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val);
void AArch64_set_detail_shift_ext(MCInst *MI, unsigned OpNum, bool SignExtend,
bool DoShift, unsigned ExtWidth, char SrcRegKind);
bool DoShift, unsigned ExtWidth,
char SrcRegKind);
void AArch64_set_detail_op_float(MCInst *MI, unsigned OpNum, float Val);
void AArch64_set_detail_op_sys(MCInst *MI, unsigned OpNum, aarch64_sysop sys_op, aarch64_op_type type);
void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum, aarch64_sme_op_part part, AArch64Layout_VectorLayout vas, ...);
void AArch64_insert_detail_op_reg_at(MCInst *MI, unsigned index, aarch64_reg Reg, cs_ac_type access);
void AArch64_insert_detail_op_float_at(MCInst *MI, unsigned index, double val, cs_ac_type access);
void AArch64_set_detail_op_sys(MCInst *MI, unsigned OpNum, aarch64_sysop sys_op,
aarch64_op_type type);
void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum,
aarch64_sme_op_part part,
AArch64Layout_VectorLayout vas, ...);
void AArch64_set_detail_op_pred(MCInst *MI, unsigned OpNum);
void AArch64_insert_detail_op_reg_at(MCInst *MI, unsigned index,
aarch64_reg Reg, cs_ac_type access);
void AArch64_insert_detail_op_float_at(MCInst *MI, unsigned index, double val,
cs_ac_type access);
void AArch64_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Imm);
void AArch64_insert_detail_op_sys(MCInst *MI, unsigned index, aarch64_sysop sys_op,
aarch64_op_type type);
void AArch64_insert_detail_op_sme(MCInst *MI, unsigned index, aarch64_op_sme sme_op);
void AArch64_add_vas(MCInst *MI, const SStream *OS);
#endif

2
arch/AArch64/AArch64Module.c
View File

@ -34,7 +34,7 @@ cs_err AArch64_global_init(cs_struct *ud)
cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value)
{
if (type == CS_OPT_SYNTAX)
handle->syntax |= (int) value;
handle->syntax |= (int)value;
if (type == CS_OPT_MODE) {
handle->mode |= (cs_mode)value;

2
arch/ARM/ARMDisassembler.c
View File

@ -670,7 +670,7 @@ static DecodeStatus getInstruction(csh ud, const uint8_t *Bytes,
else
Result = getARMInstruction(ud, Bytes, BytesLen, MI, Size,
Address, Info);
MCInst_handleWriteback(MI, ARMInsts);
MCInst_handleWriteback(MI, ARMInsts, ARR_SIZE(ARMInsts));
return Result;
}

2678
arch/ARM/ARMGenRegisterInfo.inc
View File

File diff suppressed because it is too large Load Diff

3
arch/Alpha/AlphaGenRegisterInfo.inc
View File

@ -97,7 +97,7 @@ enum {
#undef GET_REGINFO_MC_DESC
static const MCPhysReg AlphaRegDiffLists[] = {
/* 0 */ 65535, 0,
/* 0 */ -1, 0,
};
static const uint16_t AlphaSubRegIdxLists[] = {
@ -278,4 +278,3 @@ static const uint16_t AlphaRegEncodingTable[] = {
#endif // GET_REGINFO_MC_DESC

112
arch/Mips/MipsGenRegisterInfo.inc
View File

@ -497,7 +497,7 @@ enum {
static const MCPhysReg MipsRegDiffLists[] = {
/* 0 */ 0, 0,
/* 2 */ 4, 1, 1, 1, 1, 0,
/* 8 */ 364, 65286, 1, 1, 1, 0,
/* 8 */ 364, -250, 1, 1, 1, 0,
/* 14 */ 20, 1, 0,
/* 17 */ 21, 1, 0,
/* 20 */ 22, 1, 0,
@ -514,8 +514,8 @@ static const MCPhysReg MipsRegDiffLists[] = {
/* 53 */ 33, 1, 0,
/* 56 */ 34, 1, 0,
/* 59 */ 35, 1, 0,
/* 62 */ 65439, 1, 0,
/* 65 */ 65513, 1, 0,
/* 62 */ -97, 1, 0,
/* 65 */ -23, 1, 0,
/* 68 */ 3, 0,
/* 70 */ 4, 0,
/* 72 */ 6, 0,
@ -525,9 +525,9 @@ static const MCPhysReg MipsRegDiffLists[] = {
/* 80 */ 23, 0,
/* 82 */ 29, 0,
/* 84 */ 30, 0,
/* 86 */ 65308, 72, 0,
/* 89 */ 65346, 72, 0,
/* 92 */ 38, 65322, 73, 0,
/* 86 */ -228, 72, 0,
/* 89 */ -190, 72, 0,
/* 92 */ 38, -214, 73, 0,
/* 96 */ 95, 0,
/* 98 */ 96, 0,
/* 100 */ 106, 0,
@ -536,55 +536,55 @@ static const MCPhysReg MipsRegDiffLists[] = {
/* 106 */ 258, 0,
/* 108 */ 266, 0,
/* 110 */ 310, 0,
/* 112 */ 65031, 0,
/* 114 */ 65108, 0,
/* 116 */ 65172, 0,
/* 118 */ 65226, 0,
/* 120 */ 65229, 0,
/* 122 */ 65270, 0,
/* 124 */ 65278, 0,
/* 126 */ 65295, 0,
/* 128 */ 65317, 0,
/* 130 */ 37, 65430, 103, 65395, 65333, 0,
/* 136 */ 65349, 0,
/* 138 */ 65395, 0,
/* 140 */ 65410, 0,
/* 142 */ 65415, 0,
/* 144 */ 65419, 0,
/* 146 */ 65420, 0,
/* 148 */ 65421, 0,
/* 150 */ 65422, 0,
/* 152 */ 65430, 0,
/* 154 */ 65440, 0,
/* 156 */ 65441, 0,
/* 158 */ 141, 65498, 0,
/* 161 */ 65516, 234, 65498, 0,
/* 165 */ 65515, 235, 65498, 0,
/* 169 */ 65514, 236, 65498, 0,
/* 173 */ 65513, 237, 65498, 0,
/* 177 */ 65512, 238, 65498, 0,
/* 181 */ 65511, 239, 65498, 0,
/* 185 */ 65510, 240, 65498, 0,
/* 189 */ 65509, 241, 65498, 0,
/* 193 */ 65508, 242, 65498, 0,
/* 197 */ 65507, 243, 65498, 0,
/* 201 */ 65506, 244, 65498, 0,
/* 205 */ 65505, 245, 65498, 0,
/* 209 */ 65504, 246, 65498, 0,
/* 213 */ 65503, 247, 65498, 0,
/* 217 */ 65502, 248, 65498, 0,
/* 221 */ 65501, 249, 65498, 0,
/* 225 */ 65500, 250, 65498, 0,
/* 229 */ 65295, 347, 65499, 0,
/* 233 */ 65333, 344, 65502, 0,
/* 237 */ 65507, 0,
/* 239 */ 65510, 0,
/* 241 */ 65511, 0,
/* 243 */ 65512, 0,
/* 245 */ 65516, 0,
/* 247 */ 65521, 0,
/* 249 */ 65522, 0,
/* 251 */ 65535, 0,
/* 112 */ -505, 0,
/* 114 */ -428, 0,
/* 116 */ -364, 0,
/* 118 */ -310, 0,
/* 120 */ -307, 0,
/* 122 */ -266, 0,
/* 124 */ -258, 0,
/* 126 */ -241, 0,
/* 128 */ -219, 0,
/* 130 */ 37, -106, 103, -141, -203, 0,
/* 136 */ -187, 0,
/* 138 */ -141, 0,
/* 140 */ -126, 0,
/* 142 */ -121, 0,
/* 144 */ -117, 0,
/* 146 */ -116, 0,
/* 148 */ -115, 0,
/* 150 */ -114, 0,
/* 152 */ -106, 0,
/* 154 */ -96, 0,
/* 156 */ -95, 0,
/* 158 */ 141, -38, 0,
/* 161 */ -20, 234, -38, 0,
/* 165 */ -21, 235, -38, 0,
/* 169 */ -22, 236, -38, 0,
/* 173 */ -23, 237, -38, 0,
/* 177 */ -24, 238, -38, 0,
/* 181 */ -25, 239, -38, 0,
/* 185 */ -26, 240, -38, 0,
/* 189 */ -27, 241, -38, 0,
/* 193 */ -28, 242, -38, 0,
/* 197 */ -29, 243, -38, 0,
/* 201 */ -30, 244, -38, 0,
/* 205 */ -31, 245, -38, 0,
/* 209 */ -32, 246, -38, 0,
/* 213 */ -33, 247, -38, 0,
/* 217 */ -34, 248, -38, 0,
/* 221 */ -35, 249, -38, 0,
/* 225 */ -36, 250, -38, 0,
/* 229 */ -241, 347, -37, 0,
/* 233 */ -203, 344, -34, 0,
/* 237 */ -29, 0,
/* 239 */ -26, 0,
/* 241 */ -25, 0,
/* 243 */ -24, 0,
/* 245 */ -20, 0,
/* 247 */ -15, 0,
/* 249 */ -14, 0,
/* 251 */ -1, 0,
};
static const uint16_t MipsSubRegIdxLists[] = {
@ -1676,4 +1676,4 @@ static const MCRegisterClass MipsMCRegisterClasses[] = {
{ ACC128, ACC128Bits, sizeof(ACC128Bits) },
};
#endif // GET_REGINFO_MC_DESC
#endif // GET_REGINFO_MC_DESC

509
arch/PowerPC/PPCGenRegisterInfo.inc
View File

@ -677,68 +677,68 @@ static const MCPhysReg PPCRegDiffLists[] = {
/* 19 */ 90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
/* 36 */ 106, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
/* 53 */ 122, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
/* 70 */ 65378, 1, 1, 1, 1, 1, 1, 1, 0,
/* 79 */ 62070, 1, 1, 1, 0,
/* 84 */ 62130, 1, 1, 1, 0,
/* 89 */ 64477, 1, 1, 1, 0,
/* 94 */ 65497, 1, 1, 1, 0,
/* 99 */ 65501, 1, 1, 1, 0,
/* 104 */ 64643, 1, 0,
/* 107 */ 64803, 1, 0,
/* 110 */ 64933, 1, 0,
/* 113 */ 65408, 1, 0,
/* 116 */ 65472, 1, 0,
/* 119 */ 65202, 65472, 1, 64, 65473, 1, 0,
/* 126 */ 65474, 1, 0,
/* 129 */ 406, 65202, 65472, 1, 64, 65473, 1, 403, 65196, 65474, 1, 62, 65475, 1, 0,
/* 144 */ 65476, 1, 0,
/* 147 */ 65205, 65476, 1, 60, 65477, 1, 0,
/* 154 */ 65478, 1, 0,
/* 157 */ 65432, 406, 65202, 65472, 1, 64, 65473, 1, 403, 65196, 65474, 1, 62, 65475, 1, 65522, 406, 65205, 65476, 1, 60, 65477, 1, 396, 65199, 65478, 1, 58, 65479, 1, 0,
/* 188 */ 65480, 1, 0,
/* 191 */ 65208, 65480, 1, 56, 65481, 1, 0,
/* 198 */ 65482, 1, 0,
/* 201 */ 406, 65208, 65480, 1, 56, 65481, 1, 389, 65202, 65482, 1, 54, 65483, 1, 0,
/* 216 */ 65484, 1, 0,
/* 219 */ 65211, 65484, 1, 52, 65485, 1, 0,
/* 226 */ 65486, 1, 0,
/* 229 */ 65433, 406, 65208, 65480, 1, 56, 65481, 1, 389, 65202, 65482, 1, 54, 65483, 1, 65508, 406, 65211, 65484, 1, 52, 65485, 1, 382, 65205, 65486, 1, 50, 65487, 1, 0,
/* 260 */ 65488, 1, 0,
/* 263 */ 65214, 65488, 1, 48, 65489, 1, 0,
/* 270 */ 65490, 1, 0,
/* 273 */ 406, 65214, 65488, 1, 48, 65489, 1, 375, 65208, 65490, 1, 46, 65491, 1, 0,
/* 288 */ 65492, 1, 0,
/* 291 */ 65217, 65492, 1, 44, 65493, 1, 0,
/* 298 */ 65494, 1, 0,
/* 301 */ 65434, 406, 65214, 65488, 1, 48, 65489, 1, 375, 65208, 65490, 1, 46, 65491, 1, 65494, 406, 65217, 65492, 1, 44, 65493, 1, 368, 65211, 65494, 1, 42, 65495, 1, 0,
/* 332 */ 65496, 1, 0,
/* 335 */ 65220, 65496, 1, 40, 65497, 1, 0,
/* 342 */ 65498, 1, 0,
/* 345 */ 406, 65220, 65496, 1, 40, 65497, 1, 361, 65214, 65498, 1, 38, 65499, 1, 0,
/* 360 */ 65500, 1, 0,
/* 363 */ 65223, 65500, 1, 36, 65501, 1, 0,
/* 370 */ 65502, 1, 0,
/* 373 */ 65435, 406, 65220, 65496, 1, 40, 65497, 1, 361, 65214, 65498, 1, 38, 65499, 1, 65480, 406, 65223, 65500, 1, 36, 65501, 1, 354, 65217, 65502, 1, 34, 65503, 1, 0,
/* 70 */ -158, 1, 1, 1, 1, 1, 1, 1, 0,
/* 79 */ -3466, 1, 1, 1, 0,
/* 84 */ -3406, 1, 1, 1, 0,
/* 89 */ -1059, 1, 1, 1, 0,
/* 94 */ -39, 1, 1, 1, 0,
/* 99 */ -35, 1, 1, 1, 0,
/* 104 */ -893, 1, 0,
/* 107 */ -733, 1, 0,
/* 110 */ -603, 1, 0,
/* 113 */ -128, 1, 0,
/* 116 */ -64, 1, 0,
/* 119 */ -334, -64, 1, 64, -63, 1, 0,
/* 126 */ -62, 1, 0,
/* 129 */ 406, -334, -64, 1, 64, -63, 1, 403, -340, -62, 1, 62, -61, 1, 0,
/* 144 */ -60, 1, 0,
/* 147 */ -331, -60, 1, 60, -59, 1, 0,
/* 154 */ -58, 1, 0,
/* 157 */ -104, 406, -334, -64, 1, 64, -63, 1, 403, -340, -62, 1, 62, -61, 1, -14, 406, -331, -60, 1, 60, -59, 1, 396, -337, -58, 1, 58, -57, 1, 0,
/* 188 */ -56, 1, 0,
/* 191 */ -328, -56, 1, 56, -55, 1, 0,
/* 198 */ -54, 1, 0,
/* 201 */ 406, -328, -56, 1, 56, -55, 1, 389, -334, -54, 1, 54, -53, 1, 0,
/* 216 */ -52, 1, 0,
/* 219 */ -325, -52, 1, 52, -51, 1, 0,
/* 226 */ -50, 1, 0,
/* 229 */ -103, 406, -328, -56, 1, 56, -55, 1, 389, -334, -54, 1, 54, -53, 1, -28, 406, -325, -52, 1, 52, -51, 1, 382, -331, -50, 1, 50, -49, 1, 0,
/* 260 */ -48, 1, 0,
/* 263 */ -322, -48, 1, 48, -47, 1, 0,
/* 270 */ -46, 1, 0,
/* 273 */ 406, -322, -48, 1, 48, -47, 1, 375, -328, -46, 1, 46, -45, 1, 0,
/* 288 */ -44, 1, 0,
/* 291 */ -319, -44, 1, 44, -43, 1, 0,
/* 298 */ -42, 1, 0,
/* 301 */ -102, 406, -322, -48, 1, 48, -47, 1, 375, -328, -46, 1, 46, -45, 1, -42, 406, -319, -44, 1, 44, -43, 1, 368, -325, -42, 1, 42, -41, 1, 0,
/* 332 */ -40, 1, 0,
/* 335 */ -316, -40, 1, 40, -39, 1, 0,
/* 342 */ -38, 1, 0,
/* 345 */ 406, -316, -40, 1, 40, -39, 1, 361, -322, -38, 1, 38, -37, 1, 0,
/* 360 */ -36, 1, 0,
/* 363 */ -313, -36, 1, 36, -35, 1, 0,
/* 370 */ -34, 1, 0,
/* 373 */ -101, 406, -316, -40, 1, 40, -39, 1, 361, -322, -38, 1, 38, -37, 1, -56, 406, -313, -36, 1, 36, -35, 1, 354, -319, -34, 1, 34, -33, 1, 0,
/* 404 */ 3, 0,
/* 406 */ 8, 0,
/* 408 */ 18, 0,
/* 410 */ 480, 65528, 65528, 24, 0,
/* 415 */ 65424, 32, 65505, 32, 0,
/* 420 */ 65425, 32, 65505, 32, 0,
/* 425 */ 65426, 32, 65505, 32, 0,
/* 430 */ 65427, 32, 65505, 32, 0,
/* 435 */ 65428, 32, 65505, 32, 0,
/* 440 */ 65429, 32, 65505, 32, 0,
/* 445 */ 65430, 32, 65505, 32, 0,
/* 450 */ 65431, 32, 65505, 32, 0,
/* 455 */ 65432, 32, 65505, 32, 0,
/* 460 */ 65433, 32, 65505, 32, 0,
/* 465 */ 65434, 32, 65505, 32, 0,
/* 470 */ 65435, 32, 65505, 32, 0,
/* 475 */ 65436, 32, 65505, 32, 0,
/* 480 */ 65437, 32, 65505, 32, 0,
/* 485 */ 65438, 32, 65505, 32, 0,
/* 490 */ 65439, 32, 65505, 32, 0,
/* 410 */ 480, -8, -8, 24, 0,
/* 415 */ -112, 32, -31, 32, 0,
/* 420 */ -111, 32, -31, 32, 0,
/* 425 */ -110, 32, -31, 32, 0,
/* 430 */ -109, 32, -31, 32, 0,
/* 435 */ -108, 32, -31, 32, 0,
/* 440 */ -107, 32, -31, 32, 0,
/* 445 */ -106, 32, -31, 32, 0,
/* 450 */ -105, 32, -31, 32, 0,
/* 455 */ -104, 32, -31, 32, 0,
/* 460 */ -103, 32, -31, 32, 0,
/* 465 */ -102, 32, -31, 32, 0,
/* 470 */ -101, 32, -31, 32, 0,
/* 475 */ -100, 32, -31, 32, 0,
/* 480 */ -99, 32, -31, 32, 0,
/* 485 */ -98, 32, -31, 32, 0,
/* 490 */ -97, 32, -31, 32, 0,
/* 495 */ 37, 0,
/* 497 */ 32, 216, 49, 0,
/* 501 */ 32, 216, 50, 0,
@ -757,204 +757,204 @@ static const MCPhysReg PPCRegDiffLists[] = {
/* 553 */ 32, 216, 63, 0,
/* 557 */ 32, 216, 64, 0,
/* 561 */ 32, 216, 65, 0,
/* 565 */ 202, 16, 65168, 184, 72, 0,
/* 571 */ 202, 17, 65168, 183, 73, 0,
/* 577 */ 202, 17, 65169, 182, 74, 0,
/* 583 */ 202, 18, 65169, 181, 75, 0,
/* 589 */ 202, 19, 65169, 180, 76, 0,
/* 595 */ 202, 19, 65170, 179, 77, 0,
/* 601 */ 202, 20, 65170, 178, 78, 0,
/* 607 */ 202, 21, 65170, 177, 79, 0,
/* 613 */ 202, 21, 65171, 176, 80, 0,
/* 619 */ 202, 22, 65171, 175, 81, 0,
/* 625 */ 202, 23, 65171, 174, 82, 0,
/* 631 */ 202, 23, 65172, 173, 83, 0,
/* 637 */ 202, 24, 65172, 172, 84, 0,
/* 643 */ 202, 25, 65172, 171, 85, 0,
/* 649 */ 202, 25, 65173, 170, 86, 0,
/* 655 */ 202, 26, 65173, 169, 87, 0,
/* 661 */ 202, 27, 65173, 168, 88, 0,
/* 667 */ 202, 27, 65174, 167, 89, 0,
/* 673 */ 202, 28, 65174, 166, 90, 0,
/* 679 */ 202, 29, 65174, 165, 91, 0,
/* 685 */ 202, 29, 65175, 164, 92, 0,
/* 691 */ 202, 30, 65175, 163, 93, 0,
/* 697 */ 202, 31, 65175, 162, 94, 0,
/* 703 */ 202, 31, 65176, 161, 95, 0,
/* 709 */ 202, 32, 65176, 160, 96, 0,
/* 715 */ 65504, 96, 0,
/* 718 */ 65504, 97, 0,
/* 721 */ 65504, 98, 0,
/* 724 */ 65504, 99, 0,
/* 727 */ 32, 318, 65122, 100, 0,
/* 732 */ 33, 318, 65122, 100, 0,
/* 737 */ 33, 319, 65122, 100, 0,
/* 742 */ 34, 319, 65122, 100, 0,
/* 747 */ 34, 312, 65130, 100, 0,
/* 752 */ 35, 312, 65130, 100, 0,
/* 757 */ 35, 313, 65130, 100, 0,
/* 762 */ 36, 313, 65130, 100, 0,
/* 767 */ 65504, 100, 0,
/* 770 */ 36, 321, 65122, 101, 0,
/* 775 */ 37, 321, 65122, 101, 0,
/* 780 */ 37, 322, 65122, 101, 0,
/* 785 */ 38, 322, 65122, 101, 0,
/* 790 */ 40, 324, 65122, 101, 0,
/* 795 */ 41, 324, 65122, 101, 0,
/* 800 */ 41, 325, 65122, 101, 0,
/* 805 */ 42, 325, 65122, 101, 0,
/* 810 */ 38, 315, 65130, 101, 0,
/* 815 */ 39, 315, 65130, 101, 0,
/* 820 */ 39, 316, 65130, 101, 0,
/* 825 */ 40, 316, 65130, 101, 0,
/* 830 */ 42, 318, 65130, 101, 0,
/* 835 */ 43, 318, 65130, 101, 0,
/* 840 */ 43, 319, 65130, 101, 0,
/* 845 */ 44, 319, 65130, 101, 0,
/* 850 */ 65504, 101, 0,
/* 853 */ 44, 327, 65122, 102, 0,
/* 858 */ 45, 327, 65122, 102, 0,
/* 863 */ 45, 328, 65122, 102, 0,
/* 868 */ 46, 328, 65122, 102, 0,
/* 873 */ 48, 330, 65122, 102, 0,
/* 878 */ 49, 330, 65122, 102, 0,
/* 883 */ 49, 331, 65122, 102, 0,
/* 888 */ 50, 331, 65122, 102, 0,
/* 893 */ 46, 321, 65130, 102, 0,
/* 898 */ 47, 321, 65130, 102, 0,
/* 903 */ 47, 322, 65130, 102, 0,
/* 908 */ 48, 322, 65130, 102, 0,
/* 913 */ 50, 324, 65130, 102, 0,
/* 918 */ 51, 324, 65130, 102, 0,
/* 923 */ 51, 325, 65130, 102, 0,
/* 928 */ 52, 325, 65130, 102, 0,
/* 933 */ 65504, 102, 0,
/* 936 */ 52, 333, 65122, 103, 0,
/* 941 */ 53, 333, 65122, 103, 0,
/* 946 */ 53, 334, 65122, 103, 0,
/* 951 */ 54, 334, 65122, 103, 0,
/* 956 */ 56, 336, 65122, 103, 0,
/* 961 */ 57, 336, 65122, 103, 0,
/* 966 */ 57, 337, 65122, 103, 0,
/* 971 */ 58, 337, 65122, 103, 0,
/* 976 */ 54, 327, 65130, 103, 0,
/* 981 */ 55, 327, 65130, 103, 0,
/* 986 */ 55, 328, 65130, 103, 0,
/* 991 */ 56, 328, 65130, 103, 0,
/* 996 */ 58, 330, 65130, 103, 0,
/* 1001 */ 59, 330, 65130, 103, 0,
/* 1006 */ 59, 331, 65130, 103, 0,
/* 1011 */ 60, 331, 65130, 103, 0,
/* 1016 */ 65504, 103, 0,
/* 1019 */ 60, 339, 65122, 104, 0,
/* 1024 */ 61, 339, 65122, 104, 0,
/* 1029 */ 61, 340, 65122, 104, 0,
/* 1034 */ 62, 340, 65122, 104, 0,
/* 1039 */ 62, 333, 65130, 104, 0,
/* 1044 */ 63, 333, 65130, 104, 0,
/* 1049 */ 63, 334, 65130, 104, 0,
/* 1054 */ 64, 334, 65130, 104, 0,
/* 1059 */ 65504, 104, 0,
/* 1062 */ 65504, 105, 0,
/* 1065 */ 65504, 106, 0,
/* 1068 */ 65504, 107, 0,
/* 1071 */ 65504, 108, 0,
/* 1074 */ 65504, 109, 0,
/* 1077 */ 65504, 110, 0,
/* 1080 */ 65504, 111, 0,
/* 1083 */ 65504, 112, 0,
/* 565 */ 202, 16, -368, 184, 72, 0,
/* 571 */ 202, 17, -368, 183, 73, 0,
/* 577 */ 202, 17, -367, 182, 74, 0,
/* 583 */ 202, 18, -367, 181, 75, 0,
/* 589 */ 202, 19, -367, 180, 76, 0,
/* 595 */ 202, 19, -366, 179, 77, 0,
/* 601 */ 202, 20, -366, 178, 78, 0,
/* 607 */ 202, 21, -366, 177, 79, 0,
/* 613 */ 202, 21, -365, 176, 80, 0,
/* 619 */ 202, 22, -365, 175, 81, 0,
/* 625 */ 202, 23, -365, 174, 82, 0,
/* 631 */ 202, 23, -364, 173, 83, 0,
/* 637 */ 202, 24, -364, 172, 84, 0,
/* 643 */ 202, 25, -364, 171, 85, 0,
/* 649 */ 202, 25, -363, 170, 86, 0,
/* 655 */ 202, 26, -363, 169, 87, 0,
/* 661 */ 202, 27, -363, 168, 88, 0,
/* 667 */ 202, 27, -362, 167, 89, 0,
/* 673 */ 202, 28, -362, 166, 90, 0,
/* 679 */ 202, 29, -362, 165, 91, 0,
/* 685 */ 202, 29, -361, 164, 92, 0,
/* 691 */ 202, 30, -361, 163, 93, 0,
/* 697 */ 202, 31, -361, 162, 94, 0,
/* 703 */ 202, 31, -360, 161, 95, 0,
/* 709 */ 202, 32, -360, 160, 96, 0,
/* 715 */ -32, 96, 0,
/* 718 */ -32, 97, 0,
/* 721 */ -32, 98, 0,
/* 724 */ -32, 99, 0,
/* 727 */ 32, 318, -414, 100, 0,
/* 732 */ 33, 318, -414, 100, 0,
/* 737 */ 33, 319, -414, 100, 0,
/* 742 */ 34, 319, -414, 100, 0,
/* 747 */ 34, 312, -406, 100, 0,
/* 752 */ 35, 312, -406, 100, 0,
/* 757 */ 35, 313, -406, 100, 0,
/* 762 */ 36, 313, -406, 100, 0,
/* 767 */ -32, 100, 0,
/* 770 */ 36, 321, -414, 101, 0,
/* 775 */ 37, 321, -414, 101, 0,
/* 780 */ 37, 322, -414, 101, 0,
/* 785 */ 38, 322, -414, 101, 0,
/* 790 */ 40, 324, -414, 101, 0,
/* 795 */ 41, 324, -414, 101, 0,
/* 800 */ 41, 325, -414, 101, 0,
/* 805 */ 42, 325, -414, 101, 0,
/* 810 */ 38, 315, -406, 101, 0,
/* 815 */ 39, 315, -406, 101, 0,
/* 820 */ 39, 316, -406, 101, 0,
/* 825 */ 40, 316, -406, 101, 0,
/* 830 */ 42, 318, -406, 101, 0,
/* 835 */ 43, 318, -406, 101, 0,
/* 840 */ 43, 319, -406, 101, 0,
/* 845 */ 44, 319, -406, 101, 0,
/* 850 */ -32, 101, 0,
/* 853 */ 44, 327, -414, 102, 0,
/* 858 */ 45, 327, -414, 102, 0,
/* 863 */ 45, 328, -414, 102, 0,
/* 868 */ 46, 328, -414, 102, 0,
/* 873 */ 48, 330, -414, 102, 0,
/* 878 */ 49, 330, -414, 102, 0,
/* 883 */ 49, 331, -414, 102, 0,
/* 888 */ 50, 331, -414, 102, 0,
/* 893 */ 46, 321, -406, 102, 0,
/* 898 */ 47, 321, -406, 102, 0,
/* 903 */ 47, 322, -406, 102, 0,
/* 908 */ 48, 322, -406, 102, 0,
/* 913 */ 50, 324, -406, 102, 0,
/* 918 */ 51, 324, -406, 102, 0,
/* 923 */ 51, 325, -406, 102, 0,
/* 928 */ 52, 325, -406, 102, 0,
/* 933 */ -32, 102, 0,
/* 936 */ 52, 333, -414, 103, 0,
/* 941 */ 53, 333, -414, 103, 0,
/* 946 */ 53, 334, -414, 103, 0,
/* 951 */ 54, 334, -414, 103, 0,
/* 956 */ 56, 336, -414, 103, 0,
/* 961 */ 57, 336, -414, 103, 0,
/* 966 */ 57, 337, -414, 103, 0,
/* 971 */ 58, 337, -414, 103, 0,
/* 976 */ 54, 327, -406, 103, 0,
/* 981 */ 55, 327, -406, 103, 0,
/* 986 */ 55, 328, -406, 103, 0,
/* 991 */ 56, 328, -406, 103, 0,
/* 996 */ 58, 330, -406, 103, 0,
/* 1001 */ 59, 330, -406, 103, 0,
/* 1006 */ 59, 331, -406, 103, 0,
/* 1011 */ 60, 331, -406, 103, 0,
/* 1016 */ -32, 103, 0,
/* 1019 */ 60, 339, -414, 104, 0,
/* 1024 */ 61, 339, -414, 104, 0,
/* 1029 */ 61, 340, -414, 104, 0,
/* 1034 */ 62, 340, -414, 104, 0,
/* 1039 */ 62, 333, -406, 104, 0,
/* 1044 */ 63, 333, -406, 104, 0,
/* 1049 */ 63, 334, -406, 104, 0,
/* 1054 */ 64, 334, -406, 104, 0,
/* 1059 */ -32, 104, 0,
/* 1062 */ -32, 105, 0,
/* 1065 */ -32, 106, 0,
/* 1068 */ -32, 107, 0,
/* 1071 */ -32, 108, 0,
/* 1074 */ -32, 109, 0,
/* 1077 */ -32, 110, 0,
/* 1080 */ -32, 111, 0,
/* 1083 */ -32, 112, 0,
/* 1086 */ 138, 0,
/* 1088 */ 165, 0,
/* 1090 */ 16, 65168, 256, 0,
/* 1094 */ 17, 65168, 256, 0,
/* 1098 */ 17, 65169, 256, 0,
/* 1102 */ 18, 65169, 256, 0,
/* 1106 */ 19, 65169, 256, 0,
/* 1110 */ 19, 65170, 256, 0,
/* 1114 */ 20, 65170, 256, 0,
/* 1118 */ 21, 65170, 256, 0,
/* 1122 */ 21, 65171, 256, 0,
/* 1126 */ 22, 65171, 256, 0,
/* 1130 */ 23, 65171, 256, 0,
/* 1134 */ 23, 65172, 256, 0,
/* 1138 */ 24, 65172, 256, 0,
/* 1142 */ 25, 65172, 256, 0,
/* 1146 */ 25, 65173, 256, 0,
/* 1150 */ 26, 65173, 256, 0,
/* 1154 */ 27, 65173, 256, 0,
/* 1158 */ 27, 65174, 256, 0,
/* 1162 */ 28, 65174, 256, 0,
/* 1166 */ 29, 65174, 256, 0,
/* 1170 */ 29, 65175, 256, 0,
/* 1174 */ 30, 65175, 256, 0,
/* 1178 */ 31, 65175, 256, 0,
/* 1182 */ 31, 65176, 256, 0,
/* 1186 */ 32, 65176, 256, 0,
/* 1090 */ 16, -368, 256, 0,
/* 1094 */ 17, -368, 256, 0,
/* 1098 */ 17, -367, 256, 0,
/* 1102 */ 18, -367, 256, 0,
/* 1106 */ 19, -367, 256, 0,
/* 1110 */ 19, -366, 256, 0,
/* 1114 */ 20, -366, 256, 0,
/* 1118 */ 21, -366, 256, 0,
/* 1122 */ 21, -365, 256, 0,
/* 1126 */ 22, -365, 256, 0,
/* 1130 */ 23, -365, 256, 0,
/* 1134 */ 23, -364, 256, 0,
/* 1138 */ 24, -364, 256, 0,
/* 1142 */ 25, -364, 256, 0,
/* 1146 */ 25, -363, 256, 0,
/* 1150 */ 26, -363, 256, 0,
/* 1154 */ 27, -363, 256, 0,
/* 1158 */ 27, -362, 256, 0,
/* 1162 */ 28, -362, 256, 0,
/* 1166 */ 29, -362, 256, 0,
/* 1170 */ 29, -361, 256, 0,
/* 1174 */ 30, -361, 256, 0,
/* 1178 */ 31, -361, 256, 0,
/* 1182 */ 31, -360, 256, 0,
/* 1186 */ 32, -360, 256, 0,
/* 1190 */ 473, 0,
/* 1192 */ 63548, 0,
/* 1194 */ 63577, 0,
/* 1196 */ 63610, 0,
/* 1198 */ 63643, 0,
/* 1200 */ 65048, 0,
/* 1202 */ 65056, 0,
/* 1204 */ 65063, 0,
/* 1206 */ 65064, 0,
/* 1208 */ 65072, 0,
/* 1210 */ 65206, 0,
/* 1212 */ 65224, 0,
/* 1214 */ 65471, 65288, 249, 65288, 0,
/* 1219 */ 65472, 65288, 249, 65288, 0,
/* 1224 */ 65473, 65288, 249, 65288, 0,
/* 1229 */ 65474, 65288, 249, 65288, 0,
/* 1234 */ 65475, 65288, 249, 65288, 0,
/* 1239 */ 65476, 65288, 249, 65288, 0,
/* 1244 */ 65477, 65288, 249, 65288, 0,
/* 1249 */ 65478, 65288, 249, 65288, 0,
/* 1254 */ 65479, 65288, 249, 65288, 0,
/* 1259 */ 65480, 65288, 249, 65288, 0,
/* 1264 */ 65481, 65288, 249, 65288, 0,
/* 1269 */ 65482, 65288, 249, 65288, 0,
/* 1274 */ 65483, 65288, 249, 65288, 0,
/* 1279 */ 65484, 65288, 249, 65288, 0,
/* 1284 */ 65485, 65288, 249, 65288, 0,
/* 1289 */ 65486, 65288, 249, 65288, 0,
/* 1294 */ 65504, 65334, 203, 65334, 0,
/* 1299 */ 104, 65504, 65334, 203, 65334, 234, 65505, 65334, 203, 65334, 0,
/* 1310 */ 360, 65504, 65334, 203, 65334, 234, 65505, 65334, 203, 65334, 0,
/* 1321 */ 65506, 65334, 203, 65334, 0,
/* 1326 */ 105, 65506, 65334, 203, 65334, 232, 65507, 65334, 203, 65334, 0,
/* 1337 */ 361, 65506, 65334, 203, 65334, 232, 65507, 65334, 203, 65334, 0,
/* 1348 */ 65508, 65334, 203, 65334, 0,
/* 1353 */ 106, 65508, 65334, 203, 65334, 230, 65509, 65334, 203, 65334, 0,
/* 1364 */ 362, 65508, 65334, 203, 65334, 230, 65509, 65334, 203, 65334, 0,
/* 1375 */ 65510, 65334, 203, 65334, 0,
/* 1380 */ 107, 65510, 65334, 203, 65334, 228, 65511, 65334, 203, 65334, 0,
/* 1391 */ 363, 65510, 65334, 203, 65334, 228, 65511, 65334, 203, 65334, 0,
/* 1402 */ 65512, 65334, 203, 65334, 0,
/* 1407 */ 108, 65512, 65334, 203, 65334, 226, 65513, 65334, 203, 65334, 0,
/* 1418 */ 364, 65512, 65334, 203, 65334, 226, 65513, 65334, 203, 65334, 0,
/* 1429 */ 65514, 65334, 203, 65334, 0,
/* 1434 */ 109, 65514, 65334, 203, 65334, 224, 65515, 65334, 203, 65334, 0,
/* 1445 */ 365, 65514, 65334, 203, 65334, 224, 65515, 65334, 203, 65334, 0,
/* 1456 */ 65516, 65334, 203, 65334, 0,
/* 1461 */ 110, 65516, 65334, 203, 65334, 222, 65517, 65334, 203, 65334, 0,
/* 1472 */ 366, 65516, 65334, 203, 65334, 222, 65517, 65334, 203, 65334, 0,
/* 1483 */ 65518, 65334, 203, 65334, 0,
/* 1488 */ 111, 65518, 65334, 203, 65334, 220, 65519, 65334, 203, 65334, 0,
/* 1499 */ 367, 65518, 65334, 203, 65334, 220, 65519, 65334, 203, 65334, 0,
/* 1510 */ 65336, 0,
/* 1512 */ 65371, 0,
/* 1514 */ 65374, 0,
/* 1516 */ 65400, 0,
/* 1518 */ 65408, 0,
/* 1520 */ 65432, 0,
/* 1522 */ 65440, 0,
/* 1524 */ 65472, 0,
/* 1526 */ 65474, 0,
/* 1528 */ 65502, 0,
/* 1530 */ 65504, 0,
/* 1532 */ 65518, 0,
/* 1534 */ 65535, 0,
/* 1192 */ -1988, 0,
/* 1194 */ -1959, 0,
/* 1196 */ -1926, 0,
/* 1198 */ -1893, 0,
/* 1200 */ -488, 0,
/* 1202 */ -480, 0,
/* 1204 */ -473, 0,
/* 1206 */ -472, 0,
/* 1208 */ -464, 0,
/* 1210 */ -330, 0,
/* 1212 */ -312, 0,
/* 1214 */ -65, -248, 249, -248, 0,
/* 1219 */ -64, -248, 249, -248, 0,
/* 1224 */ -63, -248, 249, -248, 0,
/* 1229 */ -62, -248, 249, -248, 0,
/* 1234 */ -61, -248, 249, -248, 0,
/* 1239 */ -60, -248, 249, -248, 0,
/* 1244 */ -59, -248, 249, -248, 0,
/* 1249 */ -58, -248, 249, -248, 0,
/* 1254 */ -57, -248, 249, -248, 0,
/* 1259 */ -56, -248, 249, -248, 0,
/* 1264 */ -55, -248, 249, -248, 0,
/* 1269 */ -54, -248, 249, -248, 0,
/* 1274 */ -53, -248, 249, -248, 0,
/* 1279 */ -52, -248, 249, -248, 0,
/* 1284 */ -51, -248, 249, -248, 0,
/* 1289 */ -50, -248, 249, -248, 0,
/* 1294 */ -32, -202, 203, -202, 0,
/* 1299 */ 104, -32, -202, 203, -202, 234, -31, -202, 203, -202, 0,
/* 1310 */ 360, -32, -202, 203, -202, 234, -31, -202, 203, -202, 0,
/* 1321 */ -30, -202, 203, -202, 0,
/* 1326 */ 105, -30, -202, 203, -202, 232, -29, -202, 203, -202, 0,
/* 1337 */ 361, -30, -202, 203, -202, 232, -29, -202, 203, -202, 0,
/* 1348 */ -28, -202, 203, -202, 0,
/* 1353 */ 106, -28, -202, 203, -202, 230, -27, -202, 203, -202, 0,
/* 1364 */ 362, -28, -202, 203, -202, 230, -27, -202, 203, -202, 0,
/* 1375 */ -26, -202, 203, -202, 0,
/* 1380 */ 107, -26, -202, 203, -202, 228, -25, -202, 203, -202, 0,
/* 1391 */ 363, -26, -202, 203, -202, 228, -25, -202, 203, -202, 0,
/* 1402 */ -24, -202, 203, -202, 0,
/* 1407 */ 108, -24, -202, 203, -202, 226, -23, -202, 203, -202, 0,
/* 1418 */ 364, -24, -202, 203, -202, 226, -23, -202, 203, -202, 0,
/* 1429 */ -22, -202, 203, -202, 0,
/* 1434 */ 109, -22, -202, 203, -202, 224, -21, -202, 203, -202, 0,
/* 1445 */ 365, -22, -202, 203, -202, 224, -21, -202, 203, -202, 0,
/* 1456 */ -20, -202, 203, -202, 0,
/* 1461 */ 110, -20, -202, 203, -202, 222, -19, -202, 203, -202, 0,
/* 1472 */ 366, -20, -202, 203, -202, 222, -19, -202, 203, -202, 0,
/* 1483 */ -18, -202, 203, -202, 0,
/* 1488 */ 111, -18, -202, 203, -202, 220, -17, -202, 203, -202, 0,
/* 1499 */ 367, -18, -202, 203, -202, 220, -17, -202, 203, -202, 0,
/* 1510 */ -200, 0,
/* 1512 */ -165, 0,
/* 1514 */ -162, 0,
/* 1516 */ -136, 0,
/* 1518 */ -128, 0,
/* 1520 */ -104, 0,
/* 1522 */ -96, 0,
/* 1524 */ -64, 0,
/* 1526 */ -62, 0,
/* 1528 */ -34, 0,
/* 1530 */ -32, 0,
/* 1532 */ -18, 0,
/* 1534 */ -1, 0,
};
static const uint16_t PPCSubRegIdxLists[] = {
@ -2661,4 +2661,3 @@ const uint16_t PPCRegEncodingTable[] = {
#endif // GET_REGINFO_MC_DESC

4
arch/RISCV/RISCVGenRegisterInfo.inc
View File

@ -192,7 +192,7 @@ static const MCPhysReg RISCVRegDiffLists[] = {
/* 60 */ 61, 0,
/* 62 */ 62, 0,
/* 64 */ 63, 0,
/* 66 */ 65535, 0,
/* 66 */ -1, 0,
};
static const uint16_t RISCVSubRegIdxLists[] = {
@ -423,4 +423,4 @@ static const MCRegisterClass RISCVMCRegisterClasses[] = {
{ FPR64C, FPR64CBits, sizeof(FPR64CBits) },
};
#endif // GET_REGINFO_MC_DESC
#endif // GET_REGINFO_MC_DESC

96
arch/Sparc/SparcGenRegisterInfo.inc
View File

@ -163,33 +163,33 @@ enum {
#undef GET_REGINFO_MC_DESC
static const MCPhysReg SparcRegDiffLists[] = {
/* 0 */ 65126, 1, 1, 1, 0,
/* 0 */ -410, 1, 1, 1, 0,
/* 5 */ 32, 1, 0,
/* 8 */ 65436, 32, 1, 65504, 33, 1, 0,
/* 8 */ -100, 32, 1, -32, 33, 1, 0,
/* 15 */ 34, 1, 0,
/* 18 */ 65437, 34, 1, 65502, 35, 1, 0,
/* 18 */ -99, 34, 1, -34, 35, 1, 0,
/* 25 */ 36, 1, 0,
/* 28 */ 65438, 36, 1, 65500, 37, 1, 0,
/* 28 */ -98, 36, 1, -36, 37, 1, 0,
/* 35 */ 38, 1, 0,
/* 38 */ 65439, 38, 1, 65498, 39, 1, 0,
/* 38 */ -97, 38, 1, -38, 39, 1, 0,
/* 45 */ 40, 1, 0,
/* 48 */ 65440, 40, 1, 65496, 41, 1, 0,
/* 48 */ -96, 40, 1, -40, 41, 1, 0,
/* 55 */ 42, 1, 0,
/* 58 */ 65441, 42, 1, 65494, 43, 1, 0,
/* 58 */ -95, 42, 1, -42, 43, 1, 0,
/* 65 */ 44, 1, 0,
/* 68 */ 65442, 44, 1, 65492, 45, 1, 0,
/* 68 */ -94, 44, 1, -44, 45, 1, 0,
/* 75 */ 46, 1, 0,
/* 78 */ 65443, 46, 1, 65490, 47, 1, 0,
/* 85 */ 65348, 1, 0,
/* 88 */ 65444, 1, 0,
/* 91 */ 65445, 1, 0,
/* 94 */ 65446, 1, 0,
/* 97 */ 65447, 1, 0,
/* 100 */ 65448, 1, 0,
/* 103 */ 65449, 1, 0,
/* 106 */ 65450, 1, 0,
/* 109 */ 65451, 1, 0,
/* 112 */ 65532, 1, 0,
/* 78 */ -93, 46, 1, -46, 47, 1, 0,
/* 85 */ -188, 1, 0,
/* 88 */ -92, 1, 0,
/* 91 */ -91, 1, 0,
/* 94 */ -90, 1, 0,
/* 97 */ -89, 1, 0,
/* 100 */ -88, 1, 0,
/* 103 */ -87, 1, 0,
/* 106 */ -86, 1, 0,
/* 109 */ -85, 1, 0,
/* 112 */ -4, 1, 0,
/* 115 */ 15, 0,
/* 117 */ 84, 0,
/* 119 */ 85, 0,
@ -199,34 +199,34 @@ static const MCPhysReg SparcRegDiffLists[] = {
/* 127 */ 89, 0,
/* 129 */ 90, 0,
/* 131 */ 91, 0,
/* 133 */ 65488, 92, 0,
/* 136 */ 65489, 92, 0,
/* 139 */ 65489, 93, 0,
/* 142 */ 65490, 93, 0,
/* 145 */ 65491, 93, 0,
/* 148 */ 65491, 94, 0,
/* 151 */ 65492, 94, 0,
/* 154 */ 65493, 94, 0,
/* 157 */ 65493, 95, 0,
/* 160 */ 65494, 95, 0,
/* 163 */ 65495, 95, 0,
/* 166 */ 65495, 96, 0,
/* 169 */ 65496, 96, 0,
/* 172 */ 65497, 96, 0,
/* 175 */ 65497, 97, 0,
/* 178 */ 65498, 97, 0,
/* 181 */ 65499, 97, 0,
/* 184 */ 65499, 98, 0,
/* 187 */ 65500, 98, 0,
/* 190 */ 65501, 98, 0,
/* 193 */ 65501, 99, 0,
/* 196 */ 65502, 99, 0,
/* 199 */ 65503, 99, 0,
/* 202 */ 65503, 100, 0,
/* 205 */ 65504, 100, 0,
/* 208 */ 65503, 0,
/* 210 */ 65519, 0,
/* 212 */ 65535, 0,
/* 133 */ -48, 92, 0,
/* 136 */ -47, 92, 0,
/* 139 */ -47, 93, 0,
/* 142 */ -46, 93, 0,
/* 145 */ -45, 93, 0,
/* 148 */ -45, 94, 0,
/* 151 */ -44, 94, 0,
/* 154 */ -43, 94, 0,
/* 157 */ -43, 95, 0,
/* 160 */ -42, 95, 0,
/* 163 */ -41, 95, 0,
/* 166 */ -41, 96, 0,
/* 169 */ -40, 96, 0,
/* 172 */ -39, 96, 0,
/* 175 */ -39, 97, 0,
/* 178 */ -38, 97, 0,
/* 181 */ -37, 97, 0,
/* 184 */ -37, 98, 0,
/* 187 */ -36, 98, 0,
/* 190 */ -35, 98, 0,
/* 193 */ -35, 99, 0,
/* 196 */ -34, 99, 0,
/* 199 */ -33, 99, 0,
/* 202 */ -33, 100, 0,
/* 205 */ -32, 100, 0,
/* 208 */ -33, 0,
/* 210 */ -17, 0,
/* 212 */ -1, 0,
};
static const uint16_t SparcSubRegIdxLists[] = {
@ -448,4 +448,4 @@ static const MCRegisterClass SparcMCRegisterClasses[] = {
{ QFPRegs_with_sub_even, QFPRegs_with_sub_evenBits, sizeof(QFPRegs_with_sub_evenBits) },
};
#endif // GET_REGINFO_MC_DESC
#endif // GET_REGINFO_MC_DESC

96
arch/SystemZ/SystemZGenRegisterInfo.inc
View File

@ -250,54 +250,54 @@ enum {
#undef GET_REGINFO_MC_DESC
static const MCPhysReg SystemZRegDiffLists[] = {
/* 0 */ 64857, 1, 1, 1, 0,
/* 5 */ 65325, 1, 0,
/* 8 */ 65471, 2, 0,
/* 11 */ 65473, 2, 0,
/* 14 */ 65475, 2, 0,
/* 17 */ 65477, 2, 0,
/* 0 */ -679, 1, 1, 1, 0,
/* 5 */ -211, 1, 0,
/* 8 */ -65, 2, 0,
/* 11 */ -63, 2, 0,
/* 14 */ -61, 2, 0,
/* 17 */ -59, 2, 0,
/* 20 */ 32, 40, 0,
/* 23 */ 65506, 40, 65494, 40, 0,
/* 28 */ 65508, 40, 65494, 40, 0,
/* 33 */ 65510, 40, 65494, 40, 0,
/* 38 */ 65512, 40, 65494, 40, 0,
/* 43 */ 65504, 40, 0,
/* 46 */ 65520, 40, 0,
/* 49 */ 65504, 41, 0,
/* 52 */ 65520, 41, 0,
/* 55 */ 65504, 42, 0,
/* 58 */ 65520, 42, 0,
/* 61 */ 65504, 43, 0,
/* 64 */ 65520, 43, 0,
/* 67 */ 65504, 44, 0,
/* 70 */ 65520, 44, 0,
/* 73 */ 65504, 45, 0,
/* 76 */ 65520, 45, 0,
/* 79 */ 65504, 46, 0,
/* 82 */ 65520, 46, 0,
/* 85 */ 65504, 47, 0,
/* 88 */ 65520, 47, 0,
/* 91 */ 65504, 48, 0,
/* 94 */ 65520, 48, 0,
/* 97 */ 65496, 65504, 56, 0,
/* 101 */ 65496, 65504, 58, 0,
/* 105 */ 65496, 65504, 60, 0,
/* 109 */ 65496, 65504, 62, 0,
/* 113 */ 65496, 65504, 64, 0,
/* 117 */ 65261, 0,
/* 119 */ 65294, 0,
/* 121 */ 65463, 0,
/* 123 */ 65503, 0,
/* 125 */ 65496, 65504, 0,
/* 128 */ 65489, 32, 65520, 65519, 32, 65520, 0,
/* 135 */ 65490, 32, 65520, 65519, 32, 65520, 0,
/* 142 */ 65491, 32, 65520, 65519, 32, 65520, 0,
/* 149 */ 65492, 32, 65520, 65519, 32, 65520, 0,
/* 156 */ 65493, 32, 65520, 65519, 32, 65520, 0,
/* 163 */ 65494, 32, 65520, 65519, 32, 65520, 0,
/* 170 */ 65495, 32, 65520, 65519, 32, 65520, 0,
/* 177 */ 65496, 32, 65520, 65519, 32, 65520, 0,
/* 184 */ 65535, 0,
/* 23 */ -30, 40, -42, 40, 0,
/* 28 */ -28, 40, -42, 40, 0,
/* 33 */ -26, 40, -42, 40, 0,
/* 38 */ -24, 40, -42, 40, 0,
/* 43 */ -32, 40, 0,
/* 46 */ -16, 40, 0,
/* 49 */ -32, 41, 0,
/* 52 */ -16, 41, 0,
/* 55 */ -32, 42, 0,
/* 58 */ -16, 42, 0,
/* 61 */ -32, 43, 0,
/* 64 */ -16, 43, 0,
/* 67 */ -32, 44, 0,
/* 70 */ -16, 44, 0,
/* 73 */ -32, 45, 0,
/* 76 */ -16, 45, 0,
/* 79 */ -32, 46, 0,
/* 82 */ -16, 46, 0,
/* 85 */ -32, 47, 0,
/* 88 */ -16, 47, 0,
/* 91 */ -32, 48, 0,
/* 94 */ -16, 48, 0,
/* 97 */ -40, -32, 56, 0,
/* 101 */ -40, -32, 58, 0,
/* 105 */ -40, -32, 60, 0,
/* 109 */ -40, -32, 62, 0,
/* 113 */ -40, -32, 64, 0,
/* 117 */ -275, 0,
/* 119 */ -242, 0,
/* 121 */ -73, 0,
/* 123 */ -33, 0,
/* 125 */ -40, -32, 0,
/* 128 */ -47, 32, -16, -17, 32, -16, 0,
/* 135 */ -46, 32, -16, -17, 32, -16, 0,
/* 142 */ -45, 32, -16, -17, 32, -16, 0,
/* 149 */ -44, 32, -16, -17, 32, -16, 0,
/* 156 */ -43, 32, -16, -17, 32, -16, 0,
/* 163 */ -42, 32, -16, -17, 32, -16, 0,
/* 170 */ -41, 32, -16, -17, 32, -16, 0,
/* 177 */ -40, 32, -16, -17, 32, -16, 0,
/* 184 */ -1, 0,
};
static const uint16_t SystemZSubRegIdxLists[] = {
@ -738,4 +738,4 @@ static const MCRegisterClass SystemZMCRegisterClasses[] = {
{ ADDR128Bit, ADDR128BitBits, sizeof(ADDR128BitBits) },
};
#endif // GET_REGINFO_MC_DESC
#endif // GET_REGINFO_MC_DESC

4
arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc
View File

@ -127,7 +127,7 @@ enum {
#undef GET_REGINFO_MC_DESC
static const MCPhysReg TMS320C64xRegDiffLists[] = {
/* 0 */ 65535, 0,
/* 0 */ -1, 0,
};
static const uint16_t TMS320C64xSubRegIdxLists[] = {
@ -274,4 +274,4 @@ static const MCRegisterClass TMS320C64xMCRegisterClasses[] = {
{ ControlRegs, ControlRegsBits, TMS320C64x_ControlRegsRegClassID },
};
#endif // GET_REGINFO_MC_DESC
#endif // GET_REGINFO_MC_DESC

57
arch/TriCore/TriCoreGenRegisterInfo.inc
View File

@ -105,33 +105,33 @@ enum {
#undef GET_REGINFO_MC_DESC
static const MCPhysReg TriCoreRegDiffLists[] = {
/* 0 */ 65434, 1, 0,
/* 3 */ 65450, 1, 0,
/* 6 */ 65482, 1, 0,
/* 9 */ 65488, 1, 0,
/* 12 */ 65489, 1, 0,
/* 15 */ 65490, 1, 0,
/* 18 */ 65491, 1, 0,
/* 21 */ 65492, 1, 0,
/* 24 */ 65493, 1, 0,
/* 27 */ 65494, 1, 0,
/* 30 */ 65495, 1, 0,
/* 33 */ 65496, 1, 0,
/* 36 */ 65497, 1, 0,
/* 39 */ 65498, 1, 0,
/* 42 */ 65499, 1, 0,
/* 45 */ 65500, 1, 0,
/* 48 */ 65501, 1, 0,
/* 51 */ 65502, 1, 0,
/* 54 */ 65503, 1, 0,
/* 57 */ 65520, 1, 0,
/* 60 */ 65521, 1, 0,
/* 63 */ 65522, 1, 0,
/* 66 */ 65523, 1, 0,
/* 69 */ 65524, 1, 0,
/* 72 */ 65525, 1, 0,
/* 75 */ 65526, 1, 0,
/* 78 */ 65527, 1, 0,
/* 0 */ -102, 1, 0,
/* 3 */ -86, 1, 0,
/* 6 */ -54, 1, 0,
/* 9 */ -48, 1, 0,
/* 12 */ -47, 1, 0,
/* 15 */ -46, 1, 0,
/* 18 */ -45, 1, 0,
/* 21 */ -44, 1, 0,
/* 24 */ -43, 1, 0,
/* 27 */ -42, 1, 0,
/* 30 */ -41, 1, 0,
/* 33 */ -40, 1, 0,
/* 36 */ -39, 1, 0,
/* 39 */ -38, 1, 0,
/* 42 */ -37, 1, 0,
/* 45 */ -36, 1, 0,
/* 48 */ -35, 1, 0,
/* 51 */ -34, 1, 0,
/* 54 */ -33, 1, 0,
/* 57 */ -16, 1, 0,
/* 60 */ -15, 1, 0,
/* 63 */ -14, 1, 0,
/* 66 */ -13, 1, 0,
/* 69 */ -12, 1, 0,
/* 72 */ -11, 1, 0,
/* 75 */ -10, 1, 0,
/* 78 */ -9, 1, 0,
/* 81 */ 32, 8, 0,
/* 84 */ 33, 8, 0,
/* 87 */ 34, 8, 0,
@ -149,7 +149,7 @@ static const MCPhysReg TriCoreRegDiffLists[] = {
/* 118 */ 14, 0,
/* 120 */ 15, 0,
/* 122 */ 16, 0,
/* 124 */ 65535, 0,
/* 124 */ -1, 0,
};
static const uint16_t TriCoreSubRegIdxLists[] = {
@ -292,4 +292,3 @@ static const MCRegisterClass TriCoreMCRegisterClasses[] = {
#endif // GET_REGINFO_MC_DESC

126
arch/X86/X86GenRegisterInfo.inc
View File

@ -390,10 +390,10 @@ enum {
static const MCPhysReg X86RegDiffLists[] = {
/* 0 */ 0, 1, 0,
/* 3 */ 64875, 1, 1, 0,
/* 7 */ 65259, 1, 1, 0,
/* 11 */ 65397, 1, 1, 0,
/* 15 */ 65466, 1, 1, 0,
/* 3 */ -661, 1, 1, 0,
/* 7 */ -277, 1, 1, 0,
/* 11 */ -139, 1, 1, 0,
/* 15 */ -70, 1, 1, 0,
/* 19 */ 2, 1, 0,
/* 22 */ 4, 1, 0,
/* 25 */ 6, 1, 0,
@ -401,81 +401,81 @@ static const MCPhysReg X86RegDiffLists[] = {
/* 31 */ 22, 1, 0,
/* 34 */ 26, 1, 0,
/* 37 */ 29, 1, 0,
/* 40 */ 64851, 1, 0,
/* 40 */ -685, 1, 0,
/* 43 */ 10, 3, 0,
/* 46 */ 4, 0,
/* 48 */ 5, 0,
/* 50 */ 65292, 1, 7, 0,
/* 54 */ 65417, 1, 7, 0,
/* 50 */ -244, 1, 7, 0,
/* 54 */ -119, 1, 7, 0,
/* 58 */ 10, 3, 7, 0,
/* 62 */ 65512, 8, 0,
/* 65 */ 65342, 1, 11, 0,
/* 69 */ 65348, 1, 11, 0,
/* 73 */ 65442, 1, 11, 0,
/* 77 */ 65448, 1, 11, 0,
/* 62 */ -24, 8, 0,
/* 65 */ -194, 1, 11, 0,
/* 69 */ -188, 1, 11, 0,
/* 73 */ -94, 1, 11, 0,
/* 77 */ -88, 1, 11, 0,
/* 81 */ 12, 0,
/* 83 */ 65342, 1, 14, 0,
/* 87 */ 65348, 1, 14, 0,
/* 91 */ 65442, 1, 14, 0,
/* 95 */ 65448, 1, 14, 0,
/* 83 */ -194, 1, 14, 0,
/* 87 */ -188, 1, 14, 0,
/* 91 */ -94, 1, 14, 0,
/* 95 */ -88, 1, 14, 0,
/* 99 */ 21, 0,
/* 101 */ 22, 0,
/* 103 */ 65534, 65509, 23, 0,
/* 107 */ 65535, 65509, 23, 0,
/* 111 */ 65534, 65511, 23, 0,
/* 115 */ 65535, 65511, 23, 0,
/* 119 */ 65524, 23, 0,
/* 122 */ 128, 8, 65512, 8, 24, 0,
/* 128 */ 65519, 24, 0,
/* 131 */ 65522, 24, 0,
/* 134 */ 65511, 65526, 2, 65535, 24, 0,
/* 103 */ -2, -27, 23, 0,
/* 107 */ -1, -27, 23, 0,
/* 111 */ -2, -25, 23, 0,
/* 115 */ -1, -25, 23, 0,
/* 119 */ -12, 23, 0,
/* 122 */ 128, 8, -24, 8, 24, 0,
/* 128 */ -17, 24, 0,
/* 131 */ -14, 24, 0,
/* 134 */ -25, -10, 2, -1, 24, 0,
/* 140 */ 2, 6, 25, 0,
/* 144 */ 6, 6, 25, 0,
/* 148 */ 65534, 10, 25, 0,
/* 152 */ 65535, 10, 25, 0,
/* 148 */ -2, 10, 25, 0,
/* 152 */ -1, 10, 25, 0,
/* 156 */ 2, 12, 25, 0,
/* 160 */ 3, 12, 25, 0,
/* 164 */ 4, 15, 25, 0,
/* 168 */ 5, 15, 25, 0,
/* 172 */ 65534, 17, 25, 0,
/* 176 */ 65535, 17, 25, 0,
/* 172 */ -2, 17, 25, 0,
/* 176 */ -1, 17, 25, 0,
/* 180 */ 1, 19, 25, 0,
/* 184 */ 2, 19, 25, 0,
/* 188 */ 65521, 25, 0,
/* 188 */ -15, 25, 0,
/* 191 */ 26, 0,
/* 193 */ 65511, 65530, 65534, 65532, 27, 0,
/* 199 */ 65511, 65524, 65534, 65535, 30, 0,
/* 205 */ 65511, 65519, 2, 65535, 31, 0,
/* 193 */ -25, -6, -2, -4, 27, 0,
/* 199 */ -25, -12, -2, -1, 30, 0,
/* 205 */ -25, -17, 2, -1, 31, 0,
/* 211 */ 32, 32, 0,
/* 214 */ 65511, 65521, 65532, 65535, 35, 0,
/* 220 */ 65511, 65517, 65535, 65535, 36, 0,
/* 226 */ 64829, 0,
/* 228 */ 64900, 0,
/* 230 */ 64923, 0,
/* 232 */ 65131, 0,
/* 234 */ 65520, 65408, 0,
/* 237 */ 16, 65528, 65408, 0,
/* 241 */ 24, 65528, 65408, 0,
/* 245 */ 65430, 0,
/* 247 */ 65432, 0,
/* 249 */ 65461, 0,
/* 251 */ 65493, 0,
/* 253 */ 65504, 65504, 0,
/* 256 */ 65509, 0,
/* 258 */ 65511, 0,
/* 260 */ 65514, 0,
/* 262 */ 65513, 27, 2, 65535, 65520, 0,
/* 268 */ 65513, 25, 2, 65535, 65522, 0,
/* 274 */ 65525, 0,
/* 276 */ 65530, 0,
/* 278 */ 65531, 0,
/* 280 */ 65534, 65532, 0,
/* 283 */ 65512, 17, 65533, 0,
/* 287 */ 65534, 0,
/* 289 */ 2, 65535, 0,
/* 292 */ 65532, 65535, 0,
/* 295 */ 65534, 65535, 0,
/* 298 */ 65535, 65535, 0,
/* 214 */ -25, -15, -4, -1, 35, 0,
/* 220 */ -25, -19, -1, -1, 36, 0,
/* 226 */ -707, 0,
/* 228 */ -636, 0,
/* 230 */ -613, 0,
/* 232 */ -405, 0,
/* 234 */ -16, -128, 0,
/* 237 */ 16, -8, -128, 0,
/* 241 */ 24, -8, -128, 0,
/* 245 */ -106, 0,
/* 247 */ -104, 0,
/* 249 */ -75, 0,
/* 251 */ -43, 0,
/* 253 */ -32, -32, 0,
/* 256 */ -27, 0,
/* 258 */ -25, 0,
/* 260 */ -22, 0,
/* 262 */ -23, 27, 2, -1, -16, 0,
/* 268 */ -23, 25, 2, -1, -14, 0,
/* 274 */ -11, 0,
/* 276 */ -6, 0,
/* 278 */ -5, 0,
/* 280 */ -2, -4, 0,
/* 283 */ -24, 17, -3, 0,
/* 287 */ -2, 0,
/* 289 */ 2, -1, 0,
/* 292 */ -4, -1, 0,
/* 295 */ -2, -1, 0,
/* 298 */ -1, -1, 0,
};
static const uint16_t X86SubRegIdxLists[] = {
@ -1546,4 +1546,4 @@ static const MCRegisterClass X86MCRegisterClasses[] = {
{ VR512_with_sub_xmm_in_VR128L, VR512_with_sub_xmm_in_VR128LBits, sizeof(VR512_with_sub_xmm_in_VR128LBits) },
};
#endif // GET_REGINFO_MC_DESC
#endif // GET_REGINFO_MC_DESC

4
arch/XCore/XCoreGenRegisterInfo.inc
View File

@ -55,7 +55,7 @@ enum {
#undef GET_REGINFO_MC_DESC
static const MCPhysReg XCoreRegDiffLists[] = {
/* 0 */ 65535, 0,
/* 0 */ -1, 0,
};
static const uint16_t XCoreSubRegIdxLists[] = {
@ -107,4 +107,4 @@ static const MCRegisterClass XCoreMCRegisterClasses[] = {
{ GRRegs, GRRegsBits, sizeof(GRRegsBits) },
};
#endif // GET_REGINFO_MC_DESC
#endif // GET_REGINFO_MC_DESC

28
bindings/const_generator.py
View File

@ -5,7 +5,7 @@ import sys, re
INCL_DIR = '../include/capstone/'
include = [ 'arm.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h', 'alpha.h', 'hppa.h' ]
include = [ 'arm.h', 'aarch64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h', 'alpha.h', 'hppa.h' ]
template = {
'java': {
@ -30,13 +30,14 @@ template = {
'comment_close': '',
},
'python': {
'header': "from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM\n"
'header': "from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX\n"
"# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.py]\n",
'footer': "",
'line_format': '%s = %s\n',
'out_file': './python/capstone/%s_const.py',
# prefixes for constant filenames of all archs - case sensitive
'arm.h': 'arm',
'aarch64.h': ['AArch64', 'AARCH64'],
'm68k.h': 'm68k',
'mips.h': 'mips',
'x86.h': 'x86',
@ -158,6 +159,7 @@ template = {
excluded_prefixes = {
'arm.h': ["ARMCC_CondCodes", "ARMVCC_VPTCodes"],
'aarch64.h': ["AArch64CC_CondCode", "AArch64Layout_VectorLayout"],
}
# markup for comments to be added to autogen files
@ -217,6 +219,7 @@ def gen(lang):
enums = {}
values = {}
doc_lines = []
rhs = ""
count = 0
for line in lines:
@ -277,8 +280,25 @@ def gen(lang):
elif len(f) > 1 and f[1] == '=':
rhs = ''.join(f[2:])
else:
rhs = str(count)
count += 1
# Dirty fix: This line is reached for enum values which
# have no value assigned (as in `ARCH_SOMETHING,`).
# Because the binding constants require a fixed value,
# `count` was used (as it is now the `except` case).
# Which is of course incorrect,
# because it doesn't match the actual value in the C code.
# So we just test here if the previous `rhs` was an actual number,
# and set `rhs = rhs + 1`. If it wasn't a number, we just continue the incorrect design and
# set it to `str(count)`.
try:
if "0x" in rhs:
prev_val = int(rhs, 16)
else:
prev_val = int(rhs)
prev_val += 1
rhs = str(prev_val)
except ValueError:
rhs = str(count)
count += 1
try:
count = int(rhs) + 1

6
bindings/python/capstone/__init__.py
View File

@ -168,6 +168,8 @@ __all__ = [
'CS_OP_RESERVED_15',
'CS_OP_SPECIAL',
'CS_OP_MEM',
'CS_OP_MEM_REG',
'CS_OP_MEM_IMM',
'CS_GRP_INVALID',
'CS_GRP_JUMP',
@ -187,6 +189,8 @@ __all__ = [
'__version__',
]
UINT16_MAX = 0xffff
# Capstone C interface
# API version
@ -326,6 +330,8 @@ CS_OP_RESERVED_14 = 14
CS_OP_RESERVED_15 = 15
CS_OP_SPECIAL = 0x10 # Special operands from archs
CS_OP_MEM = 0x80 # Memory operand. Can be ORed with another operand type.
CS_OP_MEM_REG = CS_OP_MEM | CS_OP_IMM,
CS_OP_MEM_IMM = CS_OP_MEM | CS_OP_IMM,
# Common instruction groups - to be consistent across all architectures.
CS_GRP_INVALID = 0 # uninitialized/invalid group.

9
bindings/python/capstone/aarch64.py
View File

@ -34,6 +34,13 @@ class AArch64OpSme(ctypes.Structure):
('is_vertical', ctypes.c_bool),
)
class AArch64OpPred(ctypes.Structure):
_fileds_ = (
('reg', ctypes.c_uint),
('vec_select', ctypes.c_uint),
('imm_index', ctypes.c_int),
)
class AArch64OpShift(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
@ -91,6 +98,7 @@ class AArch64OpValue(ctypes.Union):
('mem', AArch64OpMem),
('sysop', AArch64SysOp),
('sme', AArch64OpSme),
('pred', AArch64OpPred),
)
class AArch64Op(ctypes.Structure):
@ -100,6 +108,7 @@ class AArch64Op(ctypes.Structure):
('shift', AArch64OpShift),
('ext', ctypes.c_uint),
('type', ctypes.c_uint),
('is_vreg', ctypes.c_bool),
('value', AArch64OpValue),
('access', ctypes.c_uint8),
('is_list_member', ctypes.c_bool),

6551
bindings/python/capstone/aarch64_const.py
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File diff suppressed because it is too large Load Diff

2
bindings/python/capstone/alpha_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [alpha_const.py]
# Operand type for instruction's operands

2
bindings/python/capstone/arm_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.py]
ARMCC_EQ = 0

2
bindings/python/capstone/bpf_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [bpf_const.py]
BPF_OP_INVALID = 0

2
bindings/python/capstone/evm_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [evm_const.py]
EVM_INS_STOP = 0

2
bindings/python/capstone/hppa_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hppa_const.py]
HPPA_MAX_OPS = 5
HPPA_STR_MODIFIER_LEN = 8

2
bindings/python/capstone/m680x_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m680x_const.py]
M680X_OPERAND_COUNT = 9

2
bindings/python/capstone/m68k_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py]
M68K_OPERAND_COUNT = 4

2
bindings/python/capstone/mips_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py]
MIPS_OP_INVALID = 0

2
bindings/python/capstone/mos65xx_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mos65xx_const.py]
MOS65XX_REG_INVALID = 0

2
bindings/python/capstone/ppc_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.py]
PPC_PRED_INVALID = 0xffff
PPC_PRED_LT = (0<<5)|12

2
bindings/python/capstone/riscv_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py]
# Operand type for instruction's operands

2
bindings/python/capstone/sh_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sh_const.py]
SH_REG_INVALID = 0

2
bindings/python/capstone/sparc_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.py]
SPARC_CC_INVALID = 0

2
bindings/python/capstone/sysz_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sysz_const.py]
SYSZ_CC_INVALID = 0

2
bindings/python/capstone/tms320c64x_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tms320c64x_const.py]
TMS320C64X_OP_INVALID = 0

2
bindings/python/capstone/tricore_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tricore_const.py]
TRICORE_OP_INVALID = CS_OP_INVALID
TRICORE_OP_REG = CS_OP_REG

2
bindings/python/capstone/wasm_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [wasm_const.py]
WASM_OP_INVALID = 0

2
bindings/python/capstone/x86_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.py]
X86_REG_INVALID = 0

2
bindings/python/capstone/xcore_const.py
View File

@ -1,4 +1,4 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xcore_const.py]
XCORE_OP_INVALID = 0

89
bindings/python/test_aarch64.py
View File

@ -27,15 +27,15 @@ def print_insn_detail(insn):
c = -1
for i in insn.operands:
c += 1
if i.type == AArch64_OP_REG:
if i.type == AARCH64_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == AArch64_OP_IMM:
if i.type == AARCH64_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
if i.type == AArch64_OP_CIMM:
if i.type == AARCH64_OP_CIMM:
print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
if i.type == AArch64_OP_FP:
if i.type == AARCH64_OP_FP:
print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
if i.type == AArch64_OP_MEM:
if i.type == AARCH64_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
@ -48,13 +48,13 @@ def print_insn_detail(insn):
% (c, to_x_32(i.mem.disp)))
if insn.post_index:
print("\t\t\tpost-indexed: true");
if i.type == AArch64_OP_SME_MATRIX:
if i.type == AARCH64_OP_SME:
print("\t\toperands[%u].type: SME_MATRIX" % (c))
print("\t\toperands[%u].sme.type: %d" % (c, i.sme.type))
if i.sme.tile != AArch64_REG_INVALID:
if i.sme.tile != AARCH64_REG_INVALID:
print("\t\toperands[%u].sme.tile: %s" % (c, insn.reg_name(i.sme.tile)))
if i.sme.slice_reg != AArch64_REG_INVALID:
if i.sme.slice_reg != AARCH64_REG_INVALID:
print("\t\toperands[%u].sme.slice_reg: %s" % (c, insn.reg_name(i.sme.slice_reg)))
if i.sme.slice_offset.imm != -1 or i.sme.slice_offset.imm_range.first != -1:
print("\t\toperands[%u].sme.slice_offset: " % (c))
@ -62,60 +62,69 @@ def print_insn_detail(insn):
print("%hhd:%hhd" % (i.sme.slice_offset.imm_range.first, i.sme.slice_offset.imm_range.offset))
else:
print("%d" % (i.sme.slice_offset.imm))
if i.sme.slice_reg != AArch64_REG_INVALID or i.sme.slice_offset.imm != -1:
if i.sme.slice_reg != AARCH64_REG_INVALID or i.sme.slice_offset.imm != -1:
print("\t\toperands[%u].sme.is_vertical: %s" % (c, ("true" if i.sme.is_vertical else "false")))
if i.type == AArch64_OP_SYSREG:
if i.type == AARCH64_OP_PRED:
print("\t\toperands[%u].type: PREDICATE\n" % c);
if (op.pred.reg != AARCH64_REG_INVALID):
print("\t\toperands[%u].pred.reg: %s\n" % (c, insn.reg_name(i.pred.reg)));
if (op.pred.vec_select != AARCH64_REG_INVALID):
print("\t\toperands[%u].pred.vec_select: %s\n" % (c, insn.reg_name(i.pred.vec_select)));
if (op.pred.imm_index != -1):
print("\t\toperands[%u].pred.imm_index: %d\n" % (i, op.pred.imm_index));
break;
if i.type == AARCH64_OP_SYSREG:
print("\t\toperands[%u].type: SYS REG:" % (c))
if i.sysop.sub_type == AArch64_OP_REG_MRS:
if i.sysop.sub_type == AARCH64_OP_REG_MRS:
print("\t\toperands[%u].subtype: REG_MRS = 0x%x" % (c, i.sysop.reg.sysreg))
if i.sysop.sub_type == AArch64_OP_REG_MSR:
if i.sysop.sub_type == AARCH64_OP_REG_MSR:
print("\t\toperands[%u].subtype: REG_MSR = 0x%x" % (c, i.sysop.reg.sysreg))
if i.sysop.sub_type == AArch64_OP_TLBI:
if i.sysop.sub_type == AARCH64_OP_TLBI:
print("\t\toperands[%u].subtype TLBI = 0x%x" % (c, i.sysop.reg.tlbi))
if i.sysop.sub_type == AArch64_OP_IC:
if i.sysop.sub_type == AARCH64_OP_IC:
print("\t\toperands[%u].subtype IC = 0x%x" % (c, i.sysop.reg.ic))
if i.type == AArch64_OP_SYSALIAS:
if i.type == AARCH64_OP_SYSALIAS:
print("\t\toperands[%u].type: SYS ALIAS:" % (c))
if i.sysop.sub_type == AArch64_OP_SVCR:
if i.sysop.alias.svcr == AArch64_SVCR_SVCRSM:
if i.sysop.sub_type == AARCH64_OP_SVCR:
if i.sysop.alias.svcr == AARCH64_SVCR_SVCRSM:
print("\t\t\toperands[%u].svcr: BIT = SM" % (c))
elif i.sysop.alias.svcr == AArch64_SVCR_SVCRZA:
elif i.sysop.alias.svcr == AARCH64_SVCR_SVCRZA:
print("\t\t\toperands[%u].svcr: BIT = ZA" % (c))
elif i.sysop.alias.svcr == AArch64_SVCR_SVCRSMZA:
elif i.sysop.alias.svcr == AARCH64_SVCR_SVCRSMZA:
print("\t\t\toperands[%u].svcr: BIT = SM & ZA" % (c))
if i.sysop.sub_type == AArch64_OP_AT:
if i.sysop.sub_type == AARCH64_OP_AT:
print("\t\toperands[%u].subtype AT = 0x%x" % (c, i.sysop.alias.at))
if i.sysop.sub_type == AArch64_OP_DB:
if i.sysop.sub_type == AARCH64_OP_DB:
print("\t\toperands[%u].subtype DB = 0x%x" % (c, i.sysop.alias.db))
if i.sysop.sub_type == AArch64_OP_DC:
if i.sysop.sub_type == AARCH64_OP_DC:
print("\t\toperands[%u].subtype DC = 0x%x" % (c, i.sysop.alias.dc))
if i.sysop.sub_type == AArch64_OP_ISB:
if i.sysop.sub_type == AARCH64_OP_ISB:
print("\t\toperands[%u].subtype ISB = 0x%x" % (c, i.sysop.alias.isb))
if i.sysop.sub_type == AArch64_OP_TSB:
if i.sysop.sub_type == AARCH64_OP_TSB:
print("\t\toperands[%u].subtype TSB = 0x%x" % (c, i.sysop.alias.tsb))
if i.sysop.sub_type == AArch64_OP_PRFM:
if i.sysop.sub_type == AARCH64_OP_PRFM:
print("\t\toperands[%u].subtype PRFM = 0x%x" % (c, i.sysop.alias.prfm))
if i.sysop.sub_type == AArch64_OP_SVEPRFM:
if i.sysop.sub_type == AARCH64_OP_SVEPRFM:
print("\t\toperands[%u].subtype SVEPRFM = 0x%x" % (c, i.sysop.alias.sveprfm))
if i.sysop.sub_type == AArch64_OP_RPRFM:
if i.sysop.sub_type == AARCH64_OP_RPRFM:
print("\t\toperands[%u].subtype RPRFM = 0x%x" % (c, i.sysop.alias.rprfm))
if i.sysop.sub_type == AArch64_OP_PSTATEIMM0_15:
if i.sysop.sub_type == AARCH64_OP_PSTATEIMM0_15:
print("\t\toperands[%u].subtype PSTATEIMM0_15 = 0x%x" % (c, i.sysop.alias.pstateimm0_15))
if i.sysop.sub_type == AArch64_OP_PSTATEIMM0_1:
if i.sysop.sub_type == AARCH64_OP_PSTATEIMM0_1:
print("\t\toperands[%u].subtype PSTATEIMM0_1 = 0x%x" % (c, i.sysop.alias.pstateimm0_1))
if i.sysop.sub_type == AArch64_OP_PSB:
if i.sysop.sub_type == AARCH64_OP_PSB:
print("\t\toperands[%u].subtype PSB = 0x%x" % (c, i.sysop.alias.psb))
if i.sysop.sub_type == AArch64_OP_BTI:
if i.sysop.sub_type == AARCH64_OP_BTI:
print("\t\toperands[%u].subtype BTI = 0x%x" % (c, i.sysop.alias.bti))
if i.sysop.sub_type == AArch64_OP_SVEPREDPAT:
if i.sysop.sub_type == AARCH64_OP_SVEPREDPAT:
print("\t\toperands[%u].subtype SVEPREDPAT = 0x%x" % (c, i.sysop.alias.svepredpat))
if i.sysop.sub_type == AArch64_OP_SVEVECLENSPECIFIER:
if i.sysop.sub_type == AARCH64_OP_SVEVECLENSPECIFIER:
print("\t\toperands[%u].subtype SVEVECLENSPECIFIER = 0x%x" % (c, i.sysop.alias.sveveclenspecifier))
if i.type == AArch64_OP_SYSIMM:
if i.type == AARCH64_OP_SYSIMM:
print("\t\toperands[%u].type: SYS IMM:" % (c))
if i.sysop.sub_type == AArch64_OP_EXACTFPIMM:
if i.sysop.sub_type == AARCH64_OP_EXACTFPIMM:
print("\t\toperands[%u].subtype EXACTFPIMM = %d" % (c, i.sysop.imm.exactfpimm))
if i.sysop.sub_type == AArch64_OP_DBNXS:
if i.sysop.sub_type == AARCH64_OP_DBNXS:
print("\t\toperands[%u].subtype DBNXS = %d" % (c, i.sysop.imm.dbnxs))
if i.access == CS_AC_READ:
@ -125,13 +134,13 @@ def print_insn_detail(insn):
elif i.access == CS_AC_READ | CS_AC_WRITE:
print("\t\toperands[%u].access: READ | WRITE" % (c))
if i.shift.type != AArch64_SFT_INVALID and i.shift.value:
if i.shift.type != AARCH64_SFT_INVALID and i.shift.value:
print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value))
if i.ext != AArch64_EXT_INVALID:
if i.ext != AARCH64_EXT_INVALID:
print("\t\t\tExt: %u" % i.ext)
if i.vas != AArch64Layout_Invalid:
if i.vas != AARCH64LAYOUT_INVALID:
print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas)
if i.vector_index != -1:
@ -140,7 +149,7 @@ def print_insn_detail(insn):
if insn.writeback:
print("\tWrite-back: True")
if not insn.cc in [AArch64CC_AL, AArch64CC_Invalid]:
if insn.cc != AArch64CC_Invalid:
print("\tCode-condition: %u" % insn.cc)
if insn.update_flags:
print("\tUpdate-flags: True")

2
cs.c
View File

@ -1963,7 +1963,7 @@ cs_err CAPSTONE_API cs_regs_access(csh ud, const cs_insn *insn,
struct cs_struct *handle;
if (!ud)
return -1;
return CS_ERR_CSH;
handle = (struct cs_struct *)(uintptr_t)ud;

1
cs_simple_types.h
View File

@ -275,6 +275,7 @@ typedef enum {
CS_DATA_TYPE_externref = 193, // WebAssembly's externref type
CS_DATA_TYPE_x86amx = 194, // This is an X86 AMX value
CS_DATA_TYPE_i64x8 = 195, // 8 Consecutive GPRs (AArch64)
CS_DATA_TYPE_aarch64svcount = 196,// AArch64, Value is of a scalable size
CS_DATA_TYPE_FIRST_VALUETYPE =
1, // This is always the beginning of the list.

60
cstool/cstool.c
View File

@ -355,6 +355,7 @@ static void usage(char *prog)
printf(" -a Print Capstone register alias (if any). Otherwise LLVM register names are emitted.\n");
printf(" -s decode in SKIPDATA mode\n");
printf(" -u show immediates as unsigned\n");
printf(" -f Dev fuzzing: Disassembles <assembly-hexstring> to 0xffffffff.\n\n");
printf(" -v show version & Capstone core build info\n\n");
}
@ -446,6 +447,53 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
printf("\n");
}
static uint32_t read_le(uint8_t *buf, size_t size) {
uint32_t res = 0;
for (size_t i = 0, j = size - 1; i < size; ++i, --j) {
res |= buf[i] << j * 8;
}
return res;
}
static void to_buf(uint32_t num, uint8_t *buf) {
for (size_t i = 0, j = 3; i < 4; ++i, --j) {
buf[i] = (num >> j) & 0xff;
}
}
static void run_dev_fuzz(csh handle, uint8_t *bytes, uint32_t size) {
uint8_t buf[4] = {0};
uint32_t bytes_as_num = read_le(bytes, size);
uint32_t address = 0xffffffff;
printf("Run dev fuzz\n");
printf("Start: 0x%" PRIx32 "\n", bytes_as_num);
printf("End: 0xffffffff\n"
"Address: 0x%" PRIx32 "\n", address);
cs_insn *insn;
while (true) {
printf("\rProgress: 0x%08x\t\t", bytes_as_num);
fflush(stdout);
cs_disasm(handle, buf, 4, address, 0, &insn);
if (insn && insn->detail)
free(insn->detail);
free(insn);
bytes_as_num++;
to_buf(bytes_as_num, buf);
if (bytes_as_num == 0xffffffff) {
printf("\rProgress: 0x%08x\t\t", bytes_as_num);
fflush(stdout);
cs_disasm(handle, (uint8_t*)&buf, 4, address, 0, &insn);
if (insn && insn->detail)
free(insn->detail);
free(insn);
printf("\n");
return;
}
}
}
int main(int argc, char **argv)
{
int i, c;
@ -463,9 +511,10 @@ int main(int argc, char **argv)
bool skipdata = false;
bool custom_reg_alias = false;
bool set_real_detail = false;
bool dev_fuzz = false;
int args_left;
while ((c = getopt (argc, argv, "rasudhv")) != -1) {
while ((c = getopt (argc, argv, "rasudhvf")) != -1) {
switch (c) {
case 'a':
custom_reg_alias = true;
@ -580,6 +629,9 @@ int main(int argc, char **argv)
printf("\n");
return 0;
case 'f':
dev_fuzz = true;
break;
case 'h':
usage(argv[0]);
return 0;
@ -657,6 +709,12 @@ int main(int argc, char **argv)
cs_option(handle, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL);
}
if (dev_fuzz) {
run_dev_fuzz(handle, assembly, size);
cs_close(&handle);
return 0;
}
count = cs_disasm(handle, assembly, size, address, 0, &insn);
if (count > 0) {
for (i = 0; i < count; i++) {

96
cstool/cstool_aarch64.c
View File

@ -29,13 +29,16 @@ void print_insn_detail_aarch64(csh handle, cs_insn *ins)
switch(op->type) {
default:
break;
case AArch64_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
case AARCH64_OP_REG:
printf("\t\toperands[%u].type: REG = %s%s\n", i, cs_reg_name(handle, op->reg), op->is_vreg ? " (vreg)" : "");
if (op->is_list_member) {
printf("\t\toperands[%u].is_list_member: true\n", i);
}
break;
case AArch64_OP_IMM:
case AARCH64_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
break;
case AArch64_OP_FP:
case AARCH64_OP_FP:
#if defined(_KERNEL_MODE)
// Issue #681: Windows kernel does not support formatting float point
printf("\t\toperands[%u].type: FP = <float_point_unsupported>\n", i);
@ -43,11 +46,11 @@ void print_insn_detail_aarch64(csh handle, cs_insn *ins)
printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
#endif
break;
case AArch64_OP_MEM:
case AARCH64_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != AArch64_REG_INVALID)
if (op->mem.base != AARCH64_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
if (op->mem.index != AArch64_REG_INVALID)
if (op->mem.index != AARCH64_REG_INVALID)
printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
@ -55,13 +58,13 @@ void print_insn_detail_aarch64(csh handle, cs_insn *ins)
printf("\t\t\tpost-indexed: true\n");
break;
case AArch64_OP_SME_MATRIX:
case AARCH64_OP_SME:
printf("\t\toperands[%u].type: SME_MATRIX\n", i);
printf("\t\toperands[%u].sme.type: %d\n", i, op->sme.type);
if (op->sme.tile != AArch64_REG_INVALID)
if (op->sme.tile != AARCH64_REG_INVALID)
printf("\t\toperands[%u].sme.tile: %s\n", i, cs_reg_name(handle, op->sme.tile));
if (op->sme.slice_reg != AArch64_REG_INVALID)
if (op->sme.slice_reg != AARCH64_REG_INVALID)
printf("\t\toperands[%u].sme.slice_reg: %s\n", i, cs_reg_name(handle, op->sme.slice_reg));
if (op->sme.slice_offset.imm != -1 || op->sme.slice_offset.imm_range.first != -1) {
printf("\t\toperands[%u].sme.slice_offset: ", i);
@ -70,100 +73,109 @@ void print_insn_detail_aarch64(csh handle, cs_insn *ins)
else
printf("%d\n", op->sme.slice_offset.imm);
}
if (op->sme.slice_reg != AArch64_REG_INVALID || op->sme.slice_offset.imm != -1)
if (op->sme.slice_reg != AARCH64_REG_INVALID || op->sme.slice_offset.imm != -1)
printf("\t\toperands[%u].sme.is_vertical: %s\n", i, (op->sme.is_vertical ? "true" : "false"));
break;
case AArch64_OP_CIMM:
case AARCH64_OP_PRED:
printf("\t\toperands[%u].type: PREDICATE\n", i);
if (op->pred.reg != AARCH64_REG_INVALID)
printf("\t\toperands[%u].pred.reg: %s\n", i, cs_reg_name(handle, op->pred.reg));
if (op->pred.vec_select != AARCH64_REG_INVALID)
printf("\t\toperands[%u].pred.vec_select: %s\n", i, cs_reg_name(handle, op->pred.vec_select));
if (op->pred.imm_index != -1)
printf("\t\toperands[%u].pred.imm_index: %d\n", i, op->pred.imm_index);
break;
case AARCH64_OP_CIMM:
printf("\t\toperands[%u].type: C-IMM = %u\n", i, (int)op->imm);
break;
case AArch64_OP_SYSREG:
case AARCH64_OP_SYSREG:
printf("\t\toperands[%u].type: SYS REG:\n", i);
switch (op->sysop.sub_type) {
default:
printf("Sub type %d not handled.\n", op->sysop.sub_type);
break;
case AArch64_OP_REG_MRS:
case AARCH64_OP_REG_MRS:
printf("\t\toperands[%u].subtype: REG_MRS = 0x%x\n", i, op->sysop.reg.sysreg);
break;
case AArch64_OP_REG_MSR:
case AARCH64_OP_REG_MSR:
printf("\t\toperands[%u].subtype: REG_MSR = 0x%x\n", i, op->sysop.reg.sysreg);
break;
case AArch64_OP_TLBI:
case AARCH64_OP_TLBI:
printf("\t\toperands[%u].subtype TLBI = 0x%x\n", i, op->sysop.reg.tlbi);
break;
case AArch64_OP_IC:
case AARCH64_OP_IC:
printf("\t\toperands[%u].subtype IC = 0x%x\n", i, op->sysop.reg.ic);
break;
}
break;
case AArch64_OP_SYSALIAS:
case AARCH64_OP_SYSALIAS:
printf("\t\toperands[%u].type: SYS ALIAS:\n", i);
switch (op->sysop.sub_type) {
default:
printf("Sub type %d not handled.\n", op->sysop.sub_type);
break;
case AArch64_OP_SVCR:
if(op->sysop.alias.svcr == AArch64_SVCR_SVCRSM)
case AARCH64_OP_SVCR:
if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRSM)
printf("\t\t\toperands[%u].svcr: BIT = SM\n", i);
else if(op->sysop.alias.svcr == AArch64_SVCR_SVCRZA)
else if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRZA)
printf("\t\t\toperands[%u].svcr: BIT = ZA\n", i);
else if(op->sysop.alias.svcr == AArch64_SVCR_SVCRSMZA)
else if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRSMZA)
printf("\t\t\toperands[%u].svcr: BIT = SM & ZA\n", i);
break;
case AArch64_OP_AT:
case AARCH64_OP_AT:
printf("\t\toperands[%u].subtype AT = 0x%x\n", i, op->sysop.alias.at);
break;
case AArch64_OP_DB:
case AARCH64_OP_DB:
printf("\t\toperands[%u].subtype DB = 0x%x\n", i, op->sysop.alias.db);
break;
case AArch64_OP_DC:
case AARCH64_OP_DC:
printf("\t\toperands[%u].subtype DC = 0x%x\n", i, op->sysop.alias.dc);
break;
case AArch64_OP_ISB:
case AARCH64_OP_ISB:
printf("\t\toperands[%u].subtype ISB = 0x%x\n", i, op->sysop.alias.isb);
break;
case AArch64_OP_TSB:
case AARCH64_OP_TSB:
printf("\t\toperands[%u].subtype TSB = 0x%x\n", i, op->sysop.alias.tsb);
break;
case AArch64_OP_PRFM:
case AARCH64_OP_PRFM:
printf("\t\toperands[%u].subtype PRFM = 0x%x\n", i, op->sysop.alias.prfm);
break;
case AArch64_OP_SVEPRFM:
case AARCH64_OP_SVEPRFM:
printf("\t\toperands[%u].subtype SVEPRFM = 0x%x\n", i, op->sysop.alias.sveprfm);
break;
case AArch64_OP_RPRFM:
case AARCH64_OP_RPRFM:
printf("\t\toperands[%u].subtype RPRFM = 0x%x\n", i, op->sysop.alias.rprfm);
break;
case AArch64_OP_PSTATEIMM0_15:
case AARCH64_OP_PSTATEIMM0_15:
printf("\t\toperands[%u].subtype PSTATEIMM0_15 = 0x%x\n", i, op->sysop.alias.pstateimm0_15);
break;
case AArch64_OP_PSTATEIMM0_1:
case AARCH64_OP_PSTATEIMM0_1:
printf("\t\toperands[%u].subtype PSTATEIMM0_1 = 0x%x\n", i, op->sysop.alias.pstateimm0_1);
break;
case AArch64_OP_PSB:
case AARCH64_OP_PSB:
printf("\t\toperands[%u].subtype PSB = 0x%x\n", i, op->sysop.alias.psb);
break;
case AArch64_OP_BTI:
case AARCH64_OP_BTI:
printf("\t\toperands[%u].subtype BTI = 0x%x\n", i, op->sysop.alias.bti);
break;
case AArch64_OP_SVEPREDPAT:
case AARCH64_OP_SVEPREDPAT:
printf("\t\toperands[%u].subtype SVEPREDPAT = 0x%x\n", i, op->sysop.alias.svepredpat);
break;
case AArch64_OP_SVEVECLENSPECIFIER:
case AARCH64_OP_SVEVECLENSPECIFIER:
printf("\t\toperands[%u].subtype SVEVECLENSPECIFIER = 0x%x\n", i, op->sysop.alias.sveveclenspecifier);
break;
}
break;
case AArch64_OP_SYSIMM:
case AARCH64_OP_SYSIMM:
printf("\t\toperands[%u].type: SYS IMM:\n", i);
switch(op->sysop.sub_type) {
default:
printf("Sub type %d not handled.\n", op->sysop.sub_type);
break;
case AArch64_OP_EXACTFPIMM:
case AARCH64_OP_EXACTFPIMM:
printf("\t\toperands[%u].subtype EXACTFPIMM = %d\n", i, op->sysop.imm.exactfpimm);
break;
case AArch64_OP_DBNXS:
case AARCH64_OP_DBNXS:
printf("\t\toperands[%u].subtype DBNXS = %d\n", i, op->sysop.imm.dbnxs);
break;
}
@ -185,15 +197,15 @@ void print_insn_detail_aarch64(csh handle, cs_insn *ins)
break;
}
if (op->shift.type != AArch64_SFT_INVALID &&
if (op->shift.type != AARCH64_SFT_INVALID &&
op->shift.value)
printf("\t\t\tShift: type = %u, value = %u\n",
op->shift.type, op->shift.value);
if (op->ext != AArch64_EXT_INVALID)
if (op->ext != AARCH64_EXT_INVALID)
printf("\t\t\tExt: %u\n", op->ext);
if (op->vas != AArch64Layout_Invalid)
if (op->vas != AARCH64LAYOUT_INVALID)
printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas);
if (op->vector_index != -1)

8413
include/capstone/aarch64.h
View File

File diff suppressed because it is too large Load Diff

8394
include/capstone/arm64.h
View File

File diff suppressed because it is too large Load Diff

4
include/capstone/capstone.h
View File

@ -70,7 +70,7 @@ extern "C" {
#if CS_NEXT_VERSION < 6
#define CS_AARCH64(x) ARM64##x
#else
#define CS_AARCH64(x) AArch64##x
#define CS_AARCH64(x) AARCH64##x
#endif
#if CS_NEXT_VERSION < 6
@ -88,7 +88,7 @@ extern "C" {
#if CS_NEXT_VERSION < 6
#define CS_AARCH64_VL_(x) ARM64_VAS_##x
#else
#define CS_AARCH64_VL_(x) AArch64Layout_VL_##x
#define CS_AARCH64_VL_(x) AARCH64LAYOUT_VL_##x
#endif
#if CS_NEXT_VERSION < 6

1
include/capstone/cs_operand.h
View File

@ -24,6 +24,7 @@ typedef enum cs_op_type {
CS_OP_RESERVED_14 = 14,
CS_OP_RESERVED_15 = 15,
CS_OP_SPECIAL = 0x10, ///< Special operands from archs
CS_OP_BOUND = 0x40, ///< Operand is associated with a previous operand. Used by AArch64 for SME operands.
CS_OP_MEM =
0x80, ///< Memory operand. Can be ORed with another operand type.
CS_OP_MEM_REG = CS_OP_MEM | CS_OP_REG, ///< Memory referencing register operand.

12
run-clang-tidy.sh
View File

@ -11,9 +11,19 @@ if [ -z $base_sha ] || [ -z $head_sha ]; then
exit 0
fi
echo "Running with version:"
clang-tidy --version
BUILD_PATH="$1"
clang-tidy $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks=clang-analyzer-*,-clang-analyzer-cplusplus* > ct-warnings.txt
check_list="clang-analyzer-*,-clang-analyzer-cplusplus*,-clang-analyzer-optin.performance.Padding"
if $(hash clang-tidy-15); then
clang-tidy-15 $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks="$check_list" > ct-warnings.txt
else
clang-tidy $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks="$check_list" > ct-warnings.txt
fi
if [ $? -ne 0 ]; then
echo "clang-tidy failed"
exit 1

3
suite/MC/AArch64/a64-ignored-fields.txt.cs
View File

@ -1,2 +1,3 @@
# CS_ARCH_AARCH64, 0, None
0xe8,0x23,0x20,0x1e = fcmp s31, #0.0
0xe8,0x23,0x20,0x1e == fcmp s31, #0.0

346
suite/MC/AArch64/add.s.cs Normal file
View File

@ -0,0 +1,346 @@
# CS_ARCH_AARCH64, None, None
0xc160a300 == {z0.h, z1.h}, {z0.h, z1.h}, z0.h
0xc165a314 == {z20.h, z21.h}, {z20.h, z21.h}, z5.h
0xc168a316 == {z22.h, z23.h}, {z22.h, z23.h}, z8.h
0xc16fa31e == {z30.h, z31.h}, {z30.h, z31.h}, z15.h
0xc1a01c10 == za.s[w8, 0, vgx2], {z0.s, z1.s}
0xc1a01c10 == za.s[w8, 0], {z0.s, z1.s}
0xc1a05d55 == za.s[w10, 5, vgx2], {z10.s, z11.s}
0xc1a05d55 == za.s[w10, 5], {z10.s, z11.s}
0xc1a07d97 == za.s[w11, 7, vgx2], {z12.s, z13.s}
0xc1a07d97 == za.s[w11, 7], {z12.s, z13.s}
0xc1a07fd7 == za.s[w11, 7, vgx2], {z30.s, z31.s}
0xc1a07fd7 == za.s[w11, 7], {z30.s, z31.s}
0xc1a01e15 == za.s[w8, 5, vgx2], {z16.s, z17.s}
0xc1a01e15 == za.s[w8, 5], {z16.s, z17.s}
0xc1a01c11 == za.s[w8, 1, vgx2], {z0.s, z1.s}
0xc1a01c11 == za.s[w8, 1], {z0.s, z1.s}
0xc1a05e50 == za.s[w10, 0, vgx2], {z18.s, z19.s}
0xc1a05e50 == za.s[w10, 0], {z18.s, z19.s}
0xc1a01d90 == za.s[w8, 0], {z12.s, z13.s}
0xc1a05c11 == za.s[w10, 1, vgx2], {z0.s, z1.s}
0xc1a05c11 == za.s[w10, 1], {z0.s, z1.s}
0xc1a01ed5 == za.s[w8, 5, vgx2], {z22.s, z23.s}
0xc1a01ed5 == za.s[w8, 5], {z22.s, z23.s}
0xc1a07d12 == za.s[w11, 2, vgx2], {z8.s, z9.s}
0xc1a07d12 == za.s[w11, 2], {z8.s, z9.s}
0xc1a03d97 == za.s[w9, 7, vgx2], {z12.s, z13.s}
0xc1a03d97 == za.s[w9, 7], {z12.s, z13.s}
0xc1201810 == za.s[w8, 0, vgx2], {z0.s, z1.s}, z0.s
0xc1201810 == za.s[w8, 0], {z0.s - z1.s}, z0.s
0xc1255955 == za.s[w10, 5, vgx2], {z10.s, z11.s}, z5.s
0xc1255955 == za.s[w10, 5], {z10.s - z11.s}, z5.s
0xc12879b7 == za.s[w11, 7, vgx2], {z13.s, z14.s}, z8.s
0xc12879b7 == za.s[w11, 7], {z13.s - z14.s}, z8.s
0x1825ebbf7 == (faulty numer in LLVM. 1 or 0?) za.s[w11, 7, vgx2], {z31.s, z0.s}, z15.s
0x1825efbf7 == (faulty numer in LLVM. 1 or 0?) za.s[w11, 7, vgx2], {z31.s, z0.s}, z15.s
0xc12f7bf7 == za.s[w11, 7], {z31.s - z0.s}, z15.s
0xc1201a35 == za.s[w8, 5, vgx2], {z17.s, z18.s}, z0.s
0xc1201a35 == za.s[w8, 5], {z17.s - z18.s}, z0.s
0xc12e1831 == za.s[w8, 1, vgx2], {z1.s, z2.s}, z14.s
0xc12e1831 == za.s[w8, 1], {z1.s - z2.s}, z14.s
0xc1245a70 == za.s[w10, 0, vgx2], {z19.s, z20.s}, z4.s
0xc1245a70 == za.s[w10, 0], {z19.s - z20.s}, z4.s
0xc1221990 == za.s[w8, 0, vgx2], {z12.s, z13.s}, z2.s
0xc1221990 == za.s[w8, 0], {z12.s - z13.s}, z2.s
0xc12a5831 == za.s[w10, 1, vgx2], {z1.s, z2.s}, z10.s
0xc12a5831 == za.s[w10, 1], {z1.s - z2.s}, z10.s
0xc12e1ad5 == za.s[w8, 5, vgx2], {z22.s, z23.s}, z14.s
0xc12e1ad5 == za.s[w8, 5], {z22.s - z23.s}, z14.s
0xc1217932 == za.s[w11, 2, vgx2], {z9.s, z10.s}, z1.s
0xc1217932 == za.s[w11, 2], {z9.s - z10.s}, z1.s
0xc12b3997 == za.s[w9, 7, vgx2], {z12.s, z13.s}, z11.s
0xc12b3997 == za.s[w9, 7], {z12.s - z13.s}, z11.s
0xc1a0a300 == {z0.s-z1.s}, {z0.s-z1.s}, z0.s
0xc1a5a314 == {z20.s-z21.s}, {z20.s-z21.s}, z5.s
0xc1a8a316 == {z22.s-z23.s}, {z22.s-z23.s}, z8.s
0xc1afa31e == {z30.s-z31.s}, {z30.s-z31.s}, z15.s
0xc1a01810 == za.s[w8, 0, vgx2], {z0.s, z1.s}, {z0.s, z1.s}
0xc1a01810 == za.s[w8, 0], {z0.s - z1.s}, {z0.s - z1.s}
0xc1b45955 == za.s[w10, 5, vgx2], {z10.s, z11.s}, {z20.s, z21.s}
0xc1b45955 == za.s[w10, 5], {z10.s - z11.s}, {z20.s - z21.s}
0xc1a87997 == za.s[w11, 7, vgx2], {z12.s, z13.s}, {z8.s, z9.s}
0xc1a87997 == za.s[w11, 7], {z12.s - z13.s}, {z8.s - z9.s}
0xc1be7bd7 == za.s[w11, 7, vgx2], {z30.s, z31.s}, {z30.s, z31.s}
0xc1be7bd7 == za.s[w11, 7], {z30.s - z31.s}, {z30.s - z31.s}
0xc1b01a15 == za.s[w8, 5, vgx2], {z16.s, z17.s}, {z16.s, z17.s}
0xc1b01a15 == za.s[w8, 5], {z16.s - z17.s}, {z16.s - z17.s}
0xc1be1811 == za.s[w8, 1, vgx2], {z0.s, z1.s}, {z30.s, z31.s}
0xc1be1811 == za.s[w8, 1], {z0.s - z1.s}, {z30.s - z31.s}
0xc1b45a50 == za.s[w10, 0, vgx2], {z18.s, z19.s}, {z20.s, z21.s}
0xc1b45a50 == za.s[w10, 0], {z18.s - z19.s}, {z20.s - z21.s}
0xc1a21990 == za.s[w8, 0, vgx2], {z12.s, z13.s}, {z2.s, z3.s}
0xc1a21990 == za.s[w8, 0], {z12.s - z13.s}, {z2.s - z3.s}
0xc1ba5811 == za.s[w10, 1, vgx2], {z0.s, z1.s}, {z26.s, z27.s}
0xc1ba5811 == za.s[w10, 1], {z0.s - z1.s}, {z26.s - z27.s}
0xc1be1ad5 == za.s[w8, 5, vgx2], {z22.s, z23.s}, {z30.s, z31.s}
0xc1be1ad5 == za.s[w8, 5], {z22.s - z23.s}, {z30.s - z31.s}
0xc1a07912 == za.s[w11, 2, vgx2], {z8.s, z9.s}, {z0.s, z1.s}
0xc1a07912 == za.s[w11, 2], {z8.s - z9.s}, {z0.s - z1.s}
0xc1aa3997 == za.s[w9, 7, vgx2], {z12.s, z13.s}, {z10.s, z11.s}
0xc1aa3997 == za.s[w9, 7], {z12.s - z13.s}, {z10.s - z11.s}
0xc1e01c10 == za.d[w8, 0, vgx2], {z0.d, z1.d}
0xc1e01c10 == za.d[w8, 0], {z0.d, z1.d}
0xc1e05d55 == za.d[w10, 5, vgx2], {z10.d, z11.d}
0xc1e05d55 == za.d[w10, 5], {z10.d, z11.d}
0xc1e07d97 == za.d[w11, 7, vgx2], {z12.d, z13.d}
0xc1e07d97 == za.d[w11, 7], {z12.d, z13.d}
0xc1e07fd7 == za.d[w11, 7, vgx2], {z30.d, z31.d}
0xc1e07fd7 == za.d[w11, 7], {z30.d, z31.d}
0xc1e01e15 == za.d[w8, 5, vgx2], {z16.d, z17.d}
0xc1e01e15 == za.d[w8, 5], {z16.d, z17.d}
0xc1e01c11 == za.d[w8, 1, vgx2], {z0.d, z1.d}
0xc1e01c11 == za.d[w8, 1], {z0.d, z1.d}
0xc1e05e50 == za.d[w10, 0, vgx2], {z18.d, z19.d}
0xc1e05e50 == za.d[w10, 0], {z18.d, z19.d}
0xc1e01d90 == za.d[w8, 0, vgx2], {z12.d, z13.d}
0xc1e01d90 == za.d[w8, 0], {z12.d, z13.d}
0xc1e05c11 == za.d[w10, 1, vgx2], {z0.d, z1.d}
0xc1e05c11 == za.d[w10, 1], {z0.d, z1.d}
0xc1e01ed5 == za.d[w8, 5, vgx2], {z22.d, z23.d}
0xc1e01ed5 == za.d[w8, 5], {z22.d, z23.d}
0xc1e07d12 == za.d[w11, 2, vgx2], {z8.d, z9.d}
0xc1e07d12 == za.d[w11, 2], {z8.d, z9.d}
0xc1e03d97 == za.d[w9, 7, vgx2], {z12.d, z13.d}
0xc1e03d97 == za.d[w9, 7], {z12.d, z13.d}
0xc1601810 == za.d[w8, 0, vgx2], {z0.d, z1.d}, z0.d
0xc1601810 == za.d[w8, 0], {z0.d - z1.d}, z0.d
0xc1655955 == za.d[w10, 5, vgx2], {z10.d, z11.d}, z5.d
0xc1655955 == za.d[w10, 5], {z10.d - z11.d}, z5.d
0xc16879b7 == za.d[w11, 7, vgx2], {z13.d, z14.d}, z8.d
0xc16879b7 == (1 or 0?) za.d[w11, 7], {z13.d - z14.d}, z8.d
0x182debbf7 == (1 or 0?) za.d[w11, 7, vgx2], {z31.d, z0.d}, z15.d
0x182defbf7 == za.d[w11, 7, vgx2], {z31.d, z0.d}, z15.d
0xc16f7bf7 == za.d[w11, 7], {z31.d - z0.d}, z15.d
0xc1601a35 == za.d[w8, 5, vgx2], {z17.d, z18.d}, z0.d
0xc1601a35 == za.d[w8, 5], {z17.d - z18.d}, z0.d
0xc16e1831 == za.d[w8, 1, vgx2], {z1.d, z2.d}, z14.d
0xc16e1831 == za.d[w8, 1], {z1.d - z2.d}, z14.d
0xc1645a70 == za.d[w10, 0, vgx2], {z19.d, z20.d}, z4.d
0xc1645a70 == za.d[w10, 0], {z19.d - z20.d}, z4.d
0xc1621990 == za.d[w8, 0, vgx2], {z12.d, z13.d}, z2.d
0xc1621990 == za.d[w8, 0], {z12.d - z13.d}, z2.d
0xc16a5831 == za.d[w10, 1, vgx2], {z1.d, z2.d}, z10.d
0xc16a5831 == za.d[w10, 1], {z1.d - z2.d}, z10.d
0xc16e1ad5 == za.d[w8, 5, vgx2], {z22.d, z23.d}, z14.d
0xc16e1ad5 == za.d[w8, 5], {z22.d - z23.d}, z14.d
0xc1617932 == za.d[w11, 2, vgx2], {z9.d, z10.d}, z1.d
0xc1617932 == za.d[w11, 2], {z9.d - z10.d}, z1.d
0xc16b3997 == za.d[w9, 7, vgx2], {z12.d, z13.d}, z11.d
0xc16b3997 == za.d[w9, 7], {z12.d - z13.d}, z11.d
0xc1e0a300 == {z0.d-z1.d}, {z0.d-z1.d}, z0.d
0xc1e5a314 == {z20.d-z21.d}, {z20.d-z21.d}, z5.d
0xc1e8a316 == {z22.d-z23.d}, {z22.d-z23.d}, z8.d
0xc1efa31e == {z30.d-z31.d}, {z30.d-z31.d}, z15.d
0xc1e01810 == za.d[w8, 0, vgx2], {z0.d, z1.d}, {z0.d, z1.d}
0xc1e01810 == za.d[w8, 0], {z0.d - z1.d}, {z0.d - z1.d}
0xc1f45955 == za.d[w10, 5, vgx2], {z10.d, z11.d}, {z20.d, z21.d}
0xc1f45955 == za.d[w10, 5], {z10.d - z11.d}, {z20.d - z21.d}
0xc1e87997 == za.d[w11, 7, vgx2], {z12.d, z13.d}, {z8.d, z9.d}
0xc1e87997 == za.d[w11, 7], {z12.d - z13.d}, {z8.d - z9.d}
0xc1fe7bd7 == za.d[w11, 7, vgx2], {z30.d, z31.d}, {z30.d, z31.d}
0xc1fe7bd7 == za.d[w11, 7], {z30.d - z31.d}, {z30.d - z31.d}
0xc1f01a15 == za.d[w8, 5, vgx2], {z16.d, z17.d}, {z16.d, z17.d}
0xc1f01a15 == za.d[w8, 5], {z16.d - z17.d}, {z16.d - z17.d}
0xc1fe1811 == za.d[w8, 1, vgx2], {z0.d, z1.d}, {z30.d, z31.d}
0xc1fe1811 == za.d[w8, 1], {z0.d - z1.d}, {z30.d - z31.d}
0xc1f45a50 == za.d[w10, 0, vgx2], {z18.d, z19.d}, {z20.d, z21.d}
0xc1f45a50 == za.d[w10, 0], {z18.d - z19.d}, {z20.d - z21.d}
0xc1e21990 == za.d[w8, 0, vgx2], {z12.d, z13.d}, {z2.d, z3.d}
0xc1e21990 == za.d[w8, 0], {z12.d - z13.d}, {z2.d - z3.d}
0xc1fa5811 == za.d[w10, 1, vgx2], {z0.d, z1.d}, {z26.d, z27.d}
0xc1fa5811 == za.d[w10, 1], {z0.d - z1.d}, {z26.d - z27.d}
0xc1fe1ad5 == za.d[w8, 5, vgx2], {z22.d, z23.d}, {z30.d, z31.d}
0xc1fe1ad5 == za.d[w8, 5], {z22.d - z23.d}, {z30.d - z31.d}
0xc1e07912 == za.d[w11, 2, vgx2], {z8.d, z9.d}, {z0.d, z1.d}
0xc1e07912 == za.d[w11, 2], {z8.d - z9.d}, {z0.d - z1.d}
0xc1ea3997 == za.d[w9, 7, vgx2], {z12.d, z13.d}, {z10.d, z11.d}
0xc1ea3997 == za.d[w9, 7], {z12.d - z13.d}, {z10.d - z11.d}
0xc120a300 == {z0.b-z1.b}, {z0.b-z1.b}, z0.b
0xc125a314 == {z20.b-z21.b}, {z20.b-z21.b}, z5.b
0xc128a316 == {z22.b-z23.b}, {z22.b-z23.b}, z8.b
0xc12fa31e == {z30.b-z31.b}, {z30.b-z31.b}, z15.b
0xc160ab00 == {z0.h - z3.h}, {z0.h - z3.h}, z0.h
0xc165ab14 == {z20.h - z23.h}, {z20.h - z23.h}, z5.h
0xc168ab14 == {z20.h - z23.h}, {z20.h - z23.h}, z8.h
0xc16fab1c == {z28.h - z31.h}, {z28.h - z31.h}, z15.h
0xc1a11c10 == za.s[w8, 0, vgx4], {z0.s - z3.s}
0xc1a11c10 == za.s[w8, 0], {z0.s - z3.s}
0xc1a15d15 == za.s[w10, 5, vgx4], {z8.s - z11.s}
0xc1a15d15 == za.s[w10, 5], {z8.s - z11.s}
0xc1a17d97 == za.s[w11, 7, vgx4], {z12.s - z15.s}
0xc1a17d97 == za.s[w11, 7], {z12.s - z15.s}
0xc1a17f97 == za.s[w11, 7, vgx4], {z28.s - z31.s}
0xc1a17f97 == za.s[w11, 7], {z28.s - z31.s}
0xc1a11e15 == za.s[w8, 5, vgx4], {z16.s - z19.s}
0xc1a11e15 == za.s[w8, 5], {z16.s - z19.s}
0xc1a11c11 == za.s[w8, 1, vgx4], {z0.s - z3.s}
0xc1a11c11 == za.s[w8, 1], {z0.s - z3.s}
0xc1a15e10 == za.s[w10, 0, vgx4], {z16.s - z19.s}
0xc1a15e10 == za.s[w10, 0], {z16.s - z19.s}
0xc1a11d90 == za.s[w8, 0, vgx4], {z12.s - z15.s}
0xc1a11d90 == za.s[w8, 0], {z12.s - z15.s}
0xc1a15c11 == za.s[w10, 1, vgx4], {z0.s - z3.s}
0xc1a15c11 == za.s[w10, 1], {z0.s - z3.s}
0xc1a11e95 == za.s[w8, 5, vgx4], {z20.s - z23.s}
0xc1a11e95 == za.s[w8, 5], {z20.s - z23.s}
0xc1a17d12 == za.s[w11, 2, vgx4], {z8.s - z11.s}
0xc1a17d12 == za.s[w11, 2], {z8.s - z11.s}
0xc1a13d97 == za.s[w9, 7, vgx4], {z12.s - z15.s}
0xc1a13d97 == za.s[w9, 7], {z12.s - z15.s}
0xc1301810 == za.s[w8, 0, vgx4], {z0.s - z3.s}, z0.s
0xc1301810 == za.s[w8, 0], {z0.s - z3.s}, z0.s
0xc1355955 == za.s[w10, 5, vgx4], {z10.s - z13.s}, z5.s
0xc1355955 == za.s[w10, 5], {z10.s - z13.s}, z5.s
0xc13879b7 == za.s[w11, 7, vgx4], {z13.s - z16.s}, z8.s
0xc13879b7 == za.s[w11, 7], {z13.s - z16.s}, z8.s
0xc13f7bf7 == za.s[w11, 7, vgx4], {z31.s - z2.s}, z15.s
0xc13f7bf7 == za.s[w11, 7], {z31.s - z2.s}, z15.s
0xc1301a35 == za.s[w8, 5, vgx4], {z17.s - z20.s}, z0.s
0xc1301a35 == za.s[w8, 5], {z17.s - z20.s}, z0.s
0xc13e1831 == za.s[w8, 1, vgx4], {z1.s - z4.s}, z14.s
0xc13e1831 == za.s[w8, 1], {z1.s - z4.s}, z14.s
0xc1345a70 == za.s[w10, 0, vgx4], {z19.s - z22.s}, z4.s
0xc1345a70 == za.s[w10, 0], {z19.s - z22.s}, z4.s
0xc1321990 == za.s[w8, 0, vgx4], {z12.s - z15.s}, z2.s
0xc1321990 == za.s[w8, 0], {z12.s - z15.s}, z2.s
0xc13a5831 == za.s[w10, 1, vgx4], {z1.s - z4.s}, z10.s
0xc13a5831 == za.s[w10, 1], {z1.s - z4.s}, z10.s
0xc13e1ad5 == za.s[w8, 5, vgx4], {z22.s - z25.s}, z14.s
0xc13e1ad5 == za.s[w8, 5], {z22.s - z25.s}, z14.s
0xc1317932 == za.s[w11, 2, vgx4], {z9.s - z12.s}, z1.s
0xc1317932 == za.s[w11, 2], {z9.s - z12.s}, z1.s
0xc13b3997 == za.s[w9, 7, vgx4], {z12.s - z15.s}, z11.s
0xc13b3997 == za.s[w9, 7], {z12.s - z15.s}, z11.s
0xc1a0ab00 == {z0.s-z3.s}, {z0.s-z3.s}, z0.s
0xc1a5ab14 == {z20.s-z23.s}, {z20.s-z23.s}, z5.s
0xc1a8ab14 == {z20.s-z23.s}, {z20.s-z23.s}, z8.s
0xc1afab1c == {z28.s-z31.s}, {z28.s-z31.s}, z15.s
0xc1a11810 == za.s[w8, 0, vgx4], {z0.s-z3.s}, {z0.s-z3.s}
0xc1a11810 == za.s[w8, 0], {z0.s-z3.s}, {z0.s-z3.s}
0xc1b55915 == za.s[w10, 5, vgx4], {z8.s - z11.s}, {z20.s - z23.s}
0xc1b55915 == za.s[w10, 5], {z8.s - z11.s}, {z20.s - z23.s}
0xc1a97997 == za.s[w11, 7, vgx4], {z12.s - z15.s}, {z8.s - z11.s}
0xc1a97997 == za.s[w11, 7], {z12.s - z15.s}, {z8.s - z11.s}
0xc1bd7b97 == za.s[w11, 7, vgx4], {z28.s - z31.s}, {z28.s - z31.s}
0xc1bd7b97 == za.s[w11, 7], {z28.s - z31.s}, {z28.s - z31.s}
0xc1b11a15 == za.s[w8, 5, vgx4], {z16.s - z19.s}, {z16.s - z19.s}
0xc1b11a15 == za.s[w8, 5], {z16.s - z19.s}, {z16.s - z19.s}
0xc1bd1811 == za.s[w8, 1, vgx4], {z0.s - z3.s}, {z28.s - z31.s}
0xc1bd1811 == za.s[w8, 1], {z0.s - z3.s}, {z28.s - z31.s}
0xc1b55a10 == za.s[w10, 0, vgx4], {z16.s - z19.s}, {z20.s - z23.s}
0xc1b55a10 == za.s[w10, 0], {z16.s - z19.s}, {z20.s - z23.s}
0xc1a11990 == za.s[w8, 0, vgx4], {z12.s - z15.s}, {z0.s - z3.s}
0xc1a11990 == za.s[w8, 0], {z12.s - z15.s}, {z0.s - z3.s}
0xc1b95811 == za.s[w10, 1, vgx4], {z0.s - z3.s}, {z24.s - z27.s}
0xc1b95811 == za.s[w10, 1], {z0.s - z3.s}, {z24.s - z27.s}
0xc1bd1a95 == za.s[w8, 5, vgx4], {z20.s - z23.s}, {z28.s - z31.s}
0xc1bd1a95 == za.s[w8, 5], {z20.s - z23.s}, {z28.s - z31.s}
0xc1a17912 == za.s[w11, 2, vgx4], {z8.s - z11.s}, {z0.s - z3.s}
0xc1a17912 == za.s[w11, 2], {z8.s - z11.s}, {z0.s - z3.s}
0xc1a93997 == za.s[w9, 7, vgx4], {z12.s - z15.s}, {z8.s - z11.s}
0xc1a93997 == za.s[w9, 7], {z12.s - z15.s}, {z8.s - z11.s}
0xc1e11c10 == za.d[w8, 0, vgx4], {z0.d - z3.d}
0xc1e11c10 == za.d[w8, 0], {z0.d - z3.d}
0xc1e15d15 == za.d[w10, 5, vgx4], {z8.d - z11.d}
0xc1e15d15 == za.d[w10, 5], {z8.d - z11.d}
0xc1e17d97 == za.d[w11, 7, vgx4], {z12.d - z15.d}
0xc1e17d97 == za.d[w11, 7], {z12.d - z15.d}
0xc1e17f97 == za.d[w11, 7, vgx4], {z28.d - z31.d}
0xc1e17f97 == za.d[w11, 7], {z28.d - z31.d}
0xc1e11e15 == za.d[w8, 5, vgx4], {z16.d - z19.d}
0xc1e11e15 == za.d[w8, 5], {z16.d - z19.d}
0xc1e11c11 == za.d[w8, 1, vgx4], {z0.d - z3.d}
0xc1e11c11 == za.d[w8, 1], {z0.d - z3.d}
0xc1e15e10 == za.d[w10, 0, vgx4], {z16.d - z19.d}
0xc1e15e10 == za.d[w10, 0], {z16.d - z19.d}
0xc1e11d90 == za.d[w8, 0, vgx4], {z12.d - z15.d}
0xc1e11d90 == za.d[w8, 0], {z12.d - z15.d}
0xc1e15c11 == za.d[w10, 1, vgx4], {z0.d - z3.d}
0xc1e15c11 == za.d[w10, 1], {z0.d - z3.d}
0xc1e11e95 == za.d[w8, 5, vgx4], {z20.d - z23.d}
0xc1e11e95 == za.d[w8, 5], {z20.d - z23.d}
0xc1e17d12 == za.d[w11, 2, vgx4], {z8.d - z11.d}
0xc1e17d12 == za.d[w11, 2], {z8.d - z11.d}
0xc1e13d97 == za.d[w9, 7, vgx4], {z12.d - z15.d}
0xc1e13d97 == za.d[w9, 7], {z12.d - z15.d}
0xc1701810 == za.d[w8, 0, vgx4], {z0.d - z3.d}, z0.d
0xc1701810 == za.d[w8, 0], {z0.d - z3.d}, z0.d
0xc1755955 == za.d[w10, 5, vgx4], {z10.d - z13.d}, z5.d
0xc1755955 == za.d[w10, 5], {z10.d - z13.d}, z5.d
0xc17879b7 == za.d[w11, 7, vgx4], {z13.d - z16.d}, z8.d
0xc17879b7 == za.d[w11, 7], {z13.d - z16.d}, z8.d
0xc17f7bf7 == za.d[w11, 7, vgx4], {z31.d - z2.d}, z15.d
0xc17f7bf7 == za.d[w11, 7], {z31.d - z2.d}, z15.d
0xc1701a35 == za.d[w8, 5, vgx4], {z17.d - z20.d}, z0.d
0xc1701a35 == za.d[w8, 5], {z17.d - z20.d}, z0.d
0xc17e1831 == za.d[w8, 1, vgx4], {z1.d - z4.d}, z14.d
0xc17e1831 == za.d[w8, 1], {z1.d - z4.d}, z14.d
0xc1745a70 == za.d[w10, 0, vgx4], {z19.d - z22.d}, z4.d
0xc1745a70 == za.d[w10, 0], {z19.d - z22.d}, z4.d
0xc1721990 == za.d[w8, 0, vgx4], {z12.d - z15.d}, z2.d
0xc1721990 == za.d[w8, 0], {z12.d - z15.d}, z2.d
0xc17a5831 == za.d[w10, 1, vgx4], {z1.d - z4.d}, z10.d
0xc17a5831 == za.d[w10, 1], {z1.d - z4.d}, z10.d
0xc17e1ad5 == za.d[w8, 5, vgx4], {z22.d - z25.d}, z14.d
0xc17e1ad5 == za.d[w8, 5], {z22.d - z25.d}, z14.d
0xc1717932 == za.d[w11, 2, vgx4], {z9.d - z12.d}, z1.d
0xc1717932 == za.d[w11, 2], {z9.d - z12.d}, z1.d
0xc17b3997 == za.d[w9, 7, vgx4], {z12.d - z15.d}, z11.d
0xc17b3997 == za.d[w9, 7], {z12.d - z15.d}, z11.d
0xc1e11810 == za.d[w8, 0, vgx4], {z0.d - z3.d}, {z0.d - z3.d}
0xc1e11810 == za.d[w8, 0], {z0.d - z3.d}, {z0.d - z3.d}
0xc1f55915 == za.d[w10, 5, vgx4], {z8.d - z11.d}, {z20.d - z23.d}
0xc1f55915 == za.d[w10, 5], {z8.d - z11.d}, {z20.d - z23.d}
0xc1e97997 == za.d[w11, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d}
0xc1e97997 == za.d[w11, 7], {z12.d - z15.d}, {z8.d - z11.d}
0xc1fd7b97 == za.d[w11, 7, vgx4], {z28.d - z31.d}, {z28.d - z31.d}
0xc1fd7b97 == za.d[w11, 7], {z28.d - z31.d}, {z28.d - z31.d}
0xc1f11a15 == za.d[w8, 5, vgx4], {z16.d - z19.d}, {z16.d - z19.d}
0xc1f11a15 == za.d[w8, 5], {z16.d - z19.d}, {z16.d - z19.d}
0xc1fd1811 == za.d[w8, 1, vgx4], {z0.d - z3.d}, {z28.d - z31.d}
0xc1fd1811 == za.d[w8, 1], {z0.d - z3.d}, {z28.d - z31.d}
0xc1f55a10 == za.d[w10, 0, vgx4], {z16.d - z19.d}, {z20.d - z23.d}
0xc1f55a10 == za.d[w10, 0], {z16.d - z19.d}, {z20.d - z23.d}
0xc1e11990 == za.d[w8, 0, vgx4], {z12.d - z15.d}, {z0.d - z3.d}
0xc1e11990 == za.d[w8, 0], {z12.d - z15.d}, {z0.d - z3.d}
0xc1f95811 == za.d[w10, 1, vgx4], {z0.d - z3.d}, {z24.d - z27.d}
0xc1f95811 == za.d[w10, 1], {z0.d - z3.d}, {z24.d - z27.d}
0xc1fd1a95 == za.d[w8, 5, vgx4], {z20.d - z23.d}, {z28.d - z31.d}
0xc1fd1a95 == za.d[w8, 5], {z20.d - z23.d}, {z28.d - z31.d}
0xc1e17912 == za.d[w11, 2, vgx4], {z8.d - z11.d}, {z0.d - z3.d}
0xc1e17912 == za.d[w11, 2], {z8.d - z11.d}, {z0.d - z3.d}
0xc1e93997 == za.d[w9, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d}
0xc1e93997 == za.d[w9, 7], {z12.d - z15.d}, {z8.d - z11.d}
0xc1e0ab00 == {z0.d-z3.d}, {z0.d-z3.d}, z0.d
0xc1e5ab14 == {z20.d-z23.d}, {z20.d-z23.d}, z5.d
0xc1e8ab14 == {z20.d-z23.d}, {z20.d-z23.d}, z8.d
0xc1efab1c == {z28.d-z31.d}, {z28.d-z31.d}, z15.d
0xc1e11810 == za.d[w8, 0, vgx4], {z0.d - z3.d}, {z0.d - z3.d}
0xc1e11810 == za.d[w8, 0], {z0.d - z3.d}, {z0.d - z3.d}
0xc1f55915 == za.d[w10, 5, vgx4], {z8.d - z11.d}, {z20.d - z23.d}
0xc1f55915 == za.d[w10, 5], {z8.d - z11.d}, {z20.d - z23.d}
0xc1e97997 == za.d[w11, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d}
0xc1e97997 == za.d[w11, 7], {z12.d - z15.d}, {z8.d - z11.d}
0xc1fd7b97 == za.d[w11, 7, vgx4], {z28.d - z31.d}, {z28.d - z31.d}
0xc1fd7b97 == za.d[w11, 7], {z28.d - z31.d}, {z28.d - z31.d}
0xc1f11a15 == za.d[w8, 5, vgx4], {z16.d - z19.d}, {z16.d - z19.d}
0xc1f11a15 == za.d[w8, 5], {z16.d - z19.d}, {z16.d - z19.d}
0xc1fd1811 == za.d[w8, 1, vgx4], {z0.d - z3.d}, {z28.d - z31.d}
0xc1fd1811 == za.d[w8, 1], {z0.d - z3.d}, {z28.d - z31.d}
0xc1f55a10 == za.d[w10, 0, vgx4], {z16.d - z19.d}, {z20.d - z23.d}
0xc1f55a10 == za.d[w10, 0], {z16.d - z19.d}, {z20.d - z23.d}
0xc1e11990 == za.d[w8, 0, vgx4], {z12.d - z15.d}, {z0.d - z3.d}
0xc1e11990 == za.d[w8, 0], {z12.d - z15.d}, {z0.d - z3.d}
0xc1f95811 == za.d[w10, 1, vgx4], {z0.d - z3.d}, {z24.d - z27.d}
0xc1f95811 == za.d[w10, 1], {z0.d - z3.d}, {z24.d - z27.d}
0xc1fd1a95 == za.d[w8, 5, vgx4], {z20.d - z23.d}, {z28.d - z31.d}
0xc1fd1a95 == za.d[w8, 5], {z20.d - z23.d}, {z28.d - z31.d}
0xc1e17912 == za.d[w11, 2, vgx4], {z8.d - z11.d}, {z0.d - z3.d}
0xc1e17912 == za.d[w11, 2], {z8.d - z11.d}, {z0.d - z3.d}
0xc1e93997 == za.d[w9, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d}
0xc1e93997 == za.d[w9, 7], {z12.d - z15.d}, {z8.d - z11.d}
0xc120ab00 == {z0.b-z3.b}, {z0.b-z3.b}, z0.b
0xc125ab14 == {z20.b-z23.b}, {z20.b-z23.b}, z5.b
0xc128ab14 == {z20.b-z23.b}, {z20.b-z23.b}, z8.b
0xc12fab1c == {z28.b-z31.b}, {z28.b-z31.b}, z15.b

17
suite/MC/AArch64/addqv.s.cs Normal file
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@ -0,0 +1,17 @@
# CS_ARCH_AARCH64, None, None
0x4452000 == v0.8h, p0, z0.h
0x4453555 == v21.8h, p5, z10.h
0x4452db7 == v23.8h, p3, z13.h
0x4453fff == v31.8h, p7, z31.h
0x4852000 == v0.4s, p0, z0.s
0x4853555 == v21.4s, p5, z10.s
0x4852db7 == v23.4s, p3, z13.s
0x4853fff == v31.4s, p7, z31.s
0x4c52000 == v0.2d, p0, z0.d
0x4c53555 == v21.2d, p5, z10.d
0x4c52db7 == v23.2d, p3, z13.d
0x4c53fff == v31.2d, p7, z31.d
0x4052000 == v0.16b, p0, z0.b
0x4053555 == v21.16b, p5, z10.b
0x4052db7 == v23.16b, p3, z13.b
0x4053fff == v31.16b, p7, z31.b

17
suite/MC/AArch64/andqv.s.cs Normal file
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@ -0,0 +1,17 @@
# CS_ARCH_AARCH64, None, None
0x45e2000 == v0.8h, p0, z0.h
0x45e3555 == v21.8h, p5, z10.h
0x45e2db7 == v23.8h, p3, z13.h
0x45e3fff == v31.8h, p7, z31.h
0x49e2000 == v0.4s, p0, z0.s
0x49e3555 == v21.4s, p5, z10.s
0x49e2db7 == v23.4s, p3, z13.s
0x49e3fff == v31.4s, p7, z31.s
0x4de2000 == v0.2d, p0, z0.d
0x4de3555 == v21.2d, p5, z10.d
0x4de2db7 == v23.2d, p3, z13.d
0x4de3fff == v31.2d, p7, z31.d
0x41e2000 == v0.16b, p0, z0.b
0x41e3555 == v21.16b, p5, z10.b
0x41e2db7 == v23.16b, p3, z13.b
0x41e3fff == v31.16b, p7, z31.b

9
suite/MC/AArch64/arm64-adr.s.cs
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@ -1,5 +1,6 @@
# CS_ARCH_AARCH64, 0, None
0x00,0x00,0x00,0x10 = adr x0, #0
0x00,0x00,0x00,0x30 = adr x0, #1
0x00,0x00,0x00,0x90 = adrp x0, #0
0x00,0x00,0x00,0xb0 = adrp x0, #4096
0x00,0x00,0x00,0x10 == adr x0, #0
0x00,0x00,0x00,0x30 == adr x0, #1
0x00,0x00,0x00,0x90 == adrp x0, #0
0x00,0x00,0x00,0xb0 == adrp x0, #4096

22
suite/MC/AArch64/arm64-advsimd.txt.cs Normal file
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# CS_ARCH_AARCH64, None, None
# This regression test file is new. The option flags could not be determined.
# LLVM uses the following mattr = ['mattr=crypto']
0x41 0xd8 0x70 0x7e == faddp.2d d1, v2
0x83 0xd8 0x30 0x7e == faddp.2s s3, v4
0x82 0x70 0x01 0x4e == tbl.16b v2, { v4, v5, v6, v7 }, v1
0x80 0x70 0x01 0x0e == tbl.8b v0, { v4, v5, v6, v7 }, v1
0xa2 0x10 0x01 0x4e == tbl.16b v2, { v5 }, v1
0xa0 0x10 0x01 0x0e == tbl.8b v0, { v5 }, v1
0xa2 0x50 0x01 0x4e == tbl.16b v2, { v5, v6, v7 }, v1
0xa0 0x50 0x01 0x0e == tbl.8b v0, { v5, v6, v7 }, v1
0xc2 0x30 0x01 0x4e == tbl.16b v2, { v6, v7 }, v1
0xc0 0x30 0x01 0x0e == tbl.8b v0, { v6, v7 }, v1
0x00 0xd0 0x60 0x5e == sqdmull s0, h0, h0
0x00 0xd0 0xa0 0x5e == sqdmull d0, s0, s0
0xca 0xcd 0xc7 0x4d == ld1r.2d { v10 }, [x14], x7
0xea 0xc9 0xe7 0x4d == ld2r.4s { v10, v11 }, [x15], x7
0xea 0xe9 0xc7 0x4d == ld3r.4s { v10, v11, v12 }, [x15], x7
0xea 0xe9 0xe7 0x4d == ld4r.4s { v10, v11, v12, v13 }, [x15], x7
0x62 0xdc 0x21 0x5e == fmulx s2, s3, s1
0x62 0xdc 0x61 0x5e == fmulx d2, d3, d1
0xe8 0x6b 0xdf 0x4c == ld1.4s { v8, v9, v10 }, [sp], #48

40
suite/MC/AArch64/arm64-arithmetic.txt.cs Normal file
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@ -0,0 +1,40 @@
# CS_ARCH_AARCH64, None, None
# This regression test file is new. The option flags could not be determined.
# LLVM uses the following mattr = []
0x41 0x28 0xc3 0x1a == asr w1, w2, w3
0x41 0x28 0xc3 0x9a == asr x1, x2, x3
0x41 0x20 0xc3 0x1a == lsl w1, w2, w3
0x41 0x20 0xc3 0x9a == lsl x1, x2, x3
0x41 0x24 0xc3 0x1a == lsr w1, w2, w3
0x41 0x24 0xc3 0x9a == lsr x1, x2, x3
0x41 0x2c 0xc3 0x1a == ror w1, w2, w3
0x41 0x2c 0xc3 0x9a == ror x1, x2, x3
0x41 0x14 0xc0 0x5a == cls w1, w2
0x41 0x14 0xc0 0xda == cls x1, x2
0x41 0x10 0xc0 0x5a == clz w1, w2
0x41 0x10 0xc0 0xda == clz x1, x2
0x41 0x00 0xc0 0x5a == rbit w1, w2
0x41 0x00 0xc0 0xda == rbit x1, x2
0x41 0x08 0xc0 0x5a == rev w1, w2
0x41 0x0c 0xc0 0xda == rev x1, x2
0x41 0x04 0xc0 0x5a == rev16 w1, w2
0x41 0x04 0xc0 0xda == rev16 x1, x2
0x41 0x08 0xc0 0xda == rev32 x1, x2
0x1f 0x00 0x00 0x31 == cmn w0, #0
0x1f 0xfc 0x03 0xb1 == x0, #255
0x23 0x08 0x42 0x3a == ccmn w1, #2, #3, eq
0x23 0x08 0x42 0xba == ccmn x1, #2, #3, eq
0x23 0x08 0x42 0x7a == ccmp w1, #2, #3, eq
0x23 0x08 0x42 0xfa == ccmp x1, #2, #3, eq
0x23 0x00 0x42 0x3a == ccmn w1, w2, #3, eq
0x23 0x00 0x42 0xba == ccmn x1, x2, #3, eq
0x23 0x00 0x42 0x7a == ccmp w1, w2, #3, eq
0x23 0x00 0x42 0xfa == ccmp x1, x2, #3, eq
0x41 0x00 0x83 0x1a == csel w1, w2, w3, eq
0x41 0x00 0x83 0x9a == csel x1, x2, x3, eq
0x41 0x04 0x83 0x1a == csinc w1, w2, w3, eq
0x41 0x04 0x83 0x9a == csinc x1, x2, x3, eq
0x41 0x00 0x83 0x5a == csinv w1, w2, w3, eq
0x41 0x00 0x83 0xda == csinv x1, x2, x3, eq
0x41 0x04 0x83 0x5a == csneg w1, w2, w3, eq
0x41 0x04 0x83 0xda == csneg x1, x2, x3, eq

17
suite/MC/AArch64/arm64-basic-a64-instructions.s.cs
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@ -1,9 +1,10 @@
# CS_ARCH_AARCH64, 0, None
0xe5,0x40,0xd4,0x1a = crc32b w5, w7, w20
0xfc,0x47,0xde,0x1a = crc32h w28, wzr, w30
0x20,0x48,0xc2,0x1a = crc32w w0, w1, w2
0x27,0x4d,0xd4,0x9a = crc32x w7, w9, x20
0xa9,0x50,0xc4,0x1a = crc32cb w9, w5, w4
0x2d,0x56,0xd9,0x1a = crc32ch w13, w17, w25
0x7f,0x58,0xc5,0x1a = crc32cw wzr, w3, w5
0x12,0x5e,0xdf,0x9a = crc32cx w18, w16, xzr
0xe5,0x40,0xd4,0x1a == crc32b w5, w7, w20
0xfc,0x47,0xde,0x1a == crc32h w28, wzr, w30
0x20,0x48,0xc2,0x1a == crc32w w0, w1, w2
0x27,0x4d,0xd4,0x9a == crc32x w7, w9, x20
0xa9,0x50,0xc4,0x1a == crc32cb w9, w5, w4
0x2d,0x56,0xd9,0x1a == crc32ch w13, w17, w25
0x7f,0x58,0xc5,0x1a == crc32cw wzr, w3, w5
0x12,0x5e,0xdf,0x9a == crc32cx w18, w16, xzr

32
suite/MC/AArch64/arm64-branch.txt.cs Normal file
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@ -0,0 +1,32 @@
# CS_ARCH_AARCH64, None, None
# This regression test file is new. The option flags could not be determined.
# LLVM uses the following mattr = []
0xc0 0x03 0x5f 0xd6 == ret
0x20 0x00 0x5f 0xd6 == ret x1
0xe0 0x03 0xbf 0xd6 == drps
0xe0 0x03 0x9f 0xd6 == eret
0xa0 0x00 0x1f 0xd6 == br x5
0x20 0x01 0x3f 0xd6 == blr x9
0x0B 0x00 0x18 0x37 == tbnz w11, #3, #0
0x20 0x00 0x20 0xd4 == brk #0x1
0x41 0x00 0xa0 0xd4 == dcps1 #0x2
0x62 0x00 0xa0 0xd4 == dcps2 #0x3
0x83 0x00 0xa0 0xd4 == dcps3 #0x4
0xa0 0x00 0x40 0xd4 == hlt #0x5
0xc2 0x00 0x00 0xd4 == hvc #0x6
0xe3 0x00 0x00 0xd4 == smc #0x7
0x01 0x01 0x00 0xd4 == svc #0x8
0x07 0x00 0x00 0x14 == b #28
0x06 0x00 0x00 0x94 == bl #24
0xa1 0x00 0x00 0x54 == b.ne #20
0x80 0x00 0x08 0x36 == tbz w0, #1, #16
0xe1 0xff 0xf7 0x36 == tbz w1, #30, #-4
0x60 0x00 0x08 0x37 == tbnz w0, #1, #12
0x40 0x00 0x00 0xb4 == cbz x0, #8
0x20 0x00 0x00 0xb5 == cbnz x0, #4
0x1f 0x20 0x03 0xd5 == nop
0xff 0xff 0xff 0x17 == b #-4
0xc1 0xff 0xff 0x54 == b.ne #-8
0xa0 0xff 0x0f 0x36 == tbz w0, #1, #-12
0x80 0xff 0xff 0xb4 == cbz x0, #-16
0x1f 0x20 0x03 0xd5 == nop

7
suite/MC/AArch64/arm64-compact-unwind-fallback.s.cs Normal file
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@ -0,0 +1,7 @@
# CS_ARCH_AARCH64, None, None
# This regression test file is new. The option flags could not be determined.
# LLVM uses the following mattr = []
0x03 == compact encoding: 0x03000000
0x03 == compact encoding: 0x03000000
0x03 == compact encoding: 0x03000000
0x03 == compact encoding: 0x03000000

11
suite/MC/AArch64/arm64-crc32.txt.cs Normal file
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@ -0,0 +1,11 @@
# CS_ARCH_AARCH64, None, None
# This regression test file is new. The option flags could not be determined.
# LLVM uses the following mattr = ['mattr=+crc']
0xe5 0x40 0xd4 0x1a == crc32b w5, w7, w20
0xfc 0x47 0xde 0x1a == crc32h w28, wzr, w30
0x20 0x48 0xc2 0x1a == crc32w w0, w1, w2
0x27 0x4d 0xd4 0x9a == crc32x w7, w9, x20
0xa9 0x50 0xc4 0x1a == crc32cb w9, w5, w4
0x2d 0x56 0xd9 0x1a == crc32ch w13, w17, w25
0x7f 0x58 0xc5 0x1a == crc32cw wzr, w3, w5
0x12 0x5e 0xdf 0x9a == crc32cx w18, w16, xzr

4
suite/MC/AArch64/arm64-invalid-logical.txt.cs Normal file
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@ -0,0 +1,4 @@
# CS_ARCH_AARCH64, None, None
# This regression test file is new. The option flags could not be determined.
# LLVM uses the following mattr = []
0x7b 0xbf 0x25 0x72 == invalid instruction encoding

7
suite/MC/AArch64/arm64-leaf-compact-unwind.s.cs Normal file
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@ -0,0 +1,7 @@
# CS_ARCH_AARCH64, None, None
# This regression test file is new. The option flags could not be determined.
# LLVM uses the following mattr = []
0x02 == compact encoding: 0x02000000
0x02 == compact encoding: 0x02009000
0x02 == compact encoding: 0x0200400f
0x02 == compact encoding: 0x02021010

9
suite/MC/AArch64/arm64-nv-cond.s.cs
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@ -1,5 +1,6 @@
# CS_ARCH_AARCH64, 0, None
0xfc,0xff,0x7f,0x1e = fcsel d28, d31, d31, nv
0x00,0xf0,0x80,0x9a = csel x0, x0, x0, nv
0x00,0xf0,0x40,0xfa = ccmp x0, x0, #0, nv
0x0f,0x00,0x00,0x54 = b.nv #0
0xfc,0xff,0x7f,0x1e == fcsel d28, d31, d31, nv
0x00,0xf0,0x80,0x9a == csel x0, x0, x0, nv
0x00,0xf0,0x40,0xfa == ccmp x0, x0, #0, nv
0x0f,0x00,0x00,0x54 == b.nv #0

13
suite/MC/AArch64/arm64-spsel-sysreg.s.cs
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@ -1,7 +1,8 @@
# CS_ARCH_AARCH64, 0, None
0xbf,0x40,0x00,0xd5 = msr SPSel, #0
0x00,0x42,0x18,0xd5 = msr SPSel, x0
0xdf,0x40,0x03,0xd5 = msr DAIFSet, #0
0x00,0x52,0x18,0xd5 = msr ESR_EL1, x0
0x00,0x42,0x38,0xd5 = mrs x0, SPSel
0x00,0x52,0x38,0xd5 = mrs x0, ESR_EL1
0xbf,0x40,0x00,0xd5 == msr SPSel, #0
0x00,0x42,0x18,0xd5 == msr SPSel, x0
0xdf,0x40,0x03,0xd5 == msr DAIFSet, #0
0x00,0x52,0x18,0xd5 == msr ESR_EL1, x0
0x00,0x42,0x38,0xd5 == mrs x0, SPSel
0x00,0x52,0x38,0xd5 == mrs x0, ESR_EL1

15
suite/MC/AArch64/arm64-system.txt.cs Normal file
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@ -0,0 +1,15 @@
# CS_ARCH_AARCH64, None, None
# This regression test file is new. The option flags could not be determined.
# LLVM uses the following mattr = []
0x1f 0x20 0x03 0xd5 == nop
0x9f 0x20 0x03 0xd5 == sev
0xbf 0x20 0x03 0xd5 == sevl
0x5f 0x20 0x03 0xd5 == wfe
0x7f 0x20 0x03 0xd5 == wfi
0x3f 0x20 0x03 0xd5 == yield
0x5f 0x3a 0x03 0xd5 == clrex #10
0xdf 0x3f 0x03 0xd5 == isb{{$}}
0xdf 0x31 0x03 0xd5 == isb #1
0xbf 0x33 0x03 0xd5 == dmb osh
0x9f 0x37 0x03 0xd5 == dsb nsh
0x3f 0x76 0x08 0xd5 == dc ivac

5
suite/MC/AArch64/arm64-vector-lists.s.cs
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@ -1,3 +1,4 @@
# CS_ARCH_AARCH64, 0, None
0x00,0x00,0x00,0x0c = st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
0x00,0x04,0x00,0x0c = st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]
0x00,0x00,0x00,0x0c == st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
0x00,0x04,0x00,0x0c == st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]

17
suite/MC/AArch64/arm64-verbose-vector-case.s.cs
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@ -1,9 +1,10 @@
# CS_ARCH_AARCH64, 0, None
0x08,0xe1,0x28,0x0e = pmull v8.8h, v8.8b, v8.8b
0x08,0xe1,0x28,0x4e = pmull2 v8.8h, v8.16b, v8.16b
0x08,0xe1,0xe8,0x0e = pmull v8.1q, v8.1d, v8.1d
0x08,0xe1,0xe8,0x4e = pmull2 v8.1q, v8.2d, v8.2d
0x08,0xe1,0x28,0x0e = pmull v8.8h, v8.8b, v8.8b
0x08,0xe1,0x28,0x4e = pmull2 v8.8h, v8.16b, v8.16b
0x08,0xe1,0xe8,0x0e = pmull v8.1q, v8.1d, v8.1d
0x08,0xe1,0xe8,0x4e = pmull2 v8.1q, v8.2d, v8.2d
0x08,0xe1,0x28,0x0e == pmull v8.8h, v8.8b, v8.8b
0x08,0xe1,0x28,0x4e == pmull2 v8.8h, v8.16b, v8.16b
0x08,0xe1,0xe8,0x0e == pmull v8.1q, v8.1d, v8.1d
0x08,0xe1,0xe8,0x4e == pmull2 v8.1q, v8.2d, v8.2d
0x08,0xe1,0x28,0x0e == pmull v8.8h, v8.8b, v8.8b
0x08,0xe1,0x28,0x4e == pmull2 v8.8h, v8.16b, v8.16b
0x08,0xe1,0xe8,0x0e == pmull v8.1q, v8.1d, v8.1d
0x08,0xe1,0xe8,0x4e == pmull2 v8.1q, v8.2d, v8.2d

81
suite/MC/AArch64/armv8.1a-atomic.s.cs
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@ -1,41 +1,42 @@
# CS_ARCH_AARCH64, 0, None
0x41,0x7c,0xa0,0x08 = casb w0, w1, [x2]
0x41,0x7c,0xe0,0x08 = casab w0, w1, [x2]
0x41,0xfc,0xa0,0x08 = caslb w0, w1, [x2]
0x41,0xfc,0xe0,0x08 = casalb w0, w1, [x2]
0x41,0x7c,0xa0,0x48 = cash w0, w1, [x2]
0x41,0x7c,0xe0,0x48 = casah w0, w1, [x2]
0x41,0xfc,0xa0,0x48 = caslh w0, w1, [x2]
0x41,0xfc,0xe0,0x48 = casalh w0, w1, [x2]
0x41,0x7c,0xa0,0x88 = cas w0, w1, [x2]
0x41,0x7c,0xe0,0x88 = casa w0, w1, [x2]
0x41,0xfc,0xa0,0x88 = casl w0, w1, [x2]
0x41,0xfc,0xe0,0x88 = casal w0, w1, [x2]
0x41,0x7c,0xa0,0xc8 = cas x0, x1, [x2]
0x41,0x7c,0xe0,0xc8 = casa x0, x1, [x2]
0x41,0xfc,0xa0,0xc8 = casl x0, x1, [x2]
0x41,0xfc,0xe0,0xc8 = casal x0, x1, [x2]
0x41,0x00,0xa0,0xf8 = ldadda x0, x1, [x2]
0x41,0x10,0x60,0xf8 = ldclrl x0, x1, [x2]
0x41,0x20,0xe0,0xf8 = ldeoral x0, x1, [x2]
0x41,0x30,0x20,0xf8 = ldset x0, x1, [x2]
0x41,0x40,0xa0,0xb8 = ldsmaxa w0, w1, [x2]
0x41,0x50,0x60,0x38 = ldsminlb w0, w1, [x2]
0x41,0x60,0xe0,0x78 = ldumaxalh w0, w1, [x2]
0x41,0x70,0x20,0xb8 = ldumin w0, w1, [x2]
0xa3,0x50,0x22,0x38 = ldsminb w2, w3, [x5]
0x5f,0x00,0x60,0x38 = staddlb w0, [x2]
0x5f,0x10,0x60,0x78 = stclrlh w0, [x2]
0x5f,0x20,0x60,0xb8 = steorl w0, [x2]
0x5f,0x30,0x60,0xf8 = stsetl x0, [x2]
0x5f,0x40,0x20,0x38 = stsmaxb w0, [x2]
0x5f,0x50,0x20,0x78 = stsminh w0, [x2]
0x5f,0x60,0x20,0xb8 = stumax w0, [x2]
0x5f,0x70,0x20,0xf8 = stumin x0, [x2]
0xff,0x53,0x7d,0xf8 = stsminl x29, [sp]
0x41,0x80,0x20,0xf8 = swp x0, x1, [x2]
0x41,0x80,0x20,0x38 = swpb w0, w1, [x2]
0x41,0x80,0x60,0x78 = swplh w0, w1, [x2]
0xe1,0x83,0xe0,0xf8 = swpal x0, x1, [sp]
0x82,0x7c,0x20,0x48 = casp x0, x1, x2, x3, [x4]
0x82,0x7c,0x20,0x08 = casp w0, w1, w2, w3, [x4]
0x41,0x7c,0xa0,0x08 == casb w0, w1, [x2]
0x41,0x7c,0xe0,0x08 == casab w0, w1, [x2]
0x41,0xfc,0xa0,0x08 == caslb w0, w1, [x2]
0x41,0xfc,0xe0,0x08 == casalb w0, w1, [x2]
0x41,0x7c,0xa0,0x48 == cash w0, w1, [x2]
0x41,0x7c,0xe0,0x48 == casah w0, w1, [x2]
0x41,0xfc,0xa0,0x48 == caslh w0, w1, [x2]
0x41,0xfc,0xe0,0x48 == casalh w0, w1, [x2]
0x41,0x7c,0xa0,0x88 == cas w0, w1, [x2]
0x41,0x7c,0xe0,0x88 == casa w0, w1, [x2]
0x41,0xfc,0xa0,0x88 == casl w0, w1, [x2]
0x41,0xfc,0xe0,0x88 == casal w0, w1, [x2]
0x41,0x7c,0xa0,0xc8 == cas x0, x1, [x2]
0x41,0x7c,0xe0,0xc8 == casa x0, x1, [x2]
0x41,0xfc,0xa0,0xc8 == casl x0, x1, [x2]
0x41,0xfc,0xe0,0xc8 == casal x0, x1, [x2]
0x41,0x00,0xa0,0xf8 == ldadda x0, x1, [x2]
0x41,0x10,0x60,0xf8 == ldclrl x0, x1, [x2]
0x41,0x20,0xe0,0xf8 == ldeoral x0, x1, [x2]
0x41,0x30,0x20,0xf8 == ldset x0, x1, [x2]
0x41,0x40,0xa0,0xb8 == ldsmaxa w0, w1, [x2]
0x41,0x50,0x60,0x38 == ldsminlb w0, w1, [x2]
0x41,0x60,0xe0,0x78 == ldumaxalh w0, w1, [x2]
0x41,0x70,0x20,0xb8 == ldumin w0, w1, [x2]
0xa3,0x50,0x22,0x38 == ldsminb w2, w3, [x5]
0x5f,0x00,0x60,0x38 == staddlb w0, [x2]
0x5f,0x10,0x60,0x78 == stclrlh w0, [x2]
0x5f,0x20,0x60,0xb8 == steorl w0, [x2]
0x5f,0x30,0x60,0xf8 == stsetl x0, [x2]
0x5f,0x40,0x20,0x38 == stsmaxb w0, [x2]
0x5f,0x50,0x20,0x78 == stsminh w0, [x2]
0x5f,0x60,0x20,0xb8 == stumax w0, [x2]
0x5f,0x70,0x20,0xf8 == stumin x0, [x2]
0xff,0x53,0x7d,0xf8 == stsminl x29, [sp]
0x41,0x80,0x20,0xf8 == swp x0, x1, [x2]
0x41,0x80,0x20,0x38 == swpb w0, w1, [x2]
0x41,0x80,0x60,0x78 == swplh w0, w1, [x2]
0xe1,0x83,0xe0,0xf8 == swpal x0, x1, [sp]
0x82,0x7c,0x20,0x48 == casp x0, x1, x2, x3, [x4]
0x82,0x7c,0x20,0x08 == casp w0, w1, w2, w3, [x4]

43
suite/MC/AArch64/armv8.1a-atomic.txt.cs Normal file
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@ -0,0 +1,43 @@
# CS_ARCH_AARCH64, None, None
# This regression test file is new. The option flags could not be determined.
# LLVM uses the following mattr = ['mattr=+v8.1a']
0x41,0x7c,0xa0,0x08 == casb w0, w1, [x2]
0x41,0x7c,0xe0,0x08 == casab w0, w1, [x2]
0x41,0xfc,0xa0,0x08 == caslb w0, w1, [x2]
0x41,0xfc,0xe0,0x08 == casalb w0, w1, [x2]
0x41,0x7c,0xa0,0x48 == cash w0, w1, [x2]
0x41,0x7c,0xe0,0x48 == casah w0, w1, [x2]
0x41,0xfc,0xa0,0x48 == caslh w0, w1, [x2]
0x41,0xfc,0xe0,0x48 == casalh w0, w1, [x2]
0x41,0x7c,0xa0,0x88 == cas w0, w1, [x2]
0x41,0x7c,0xe0,0x88 == casa w0, w1, [x2]
0x41,0xfc,0xa0,0x88 == casl w0, w1, [x2]
0x41,0xfc,0xe0,0x88 == casal w0, w1, [x2]
0x41,0x7c,0xa0,0xc8 == cas x0, x1, [x2]
0x41,0x7c,0xe0,0xc8 == casa x0, x1, [x2]
0x41,0xfc,0xa0,0xc8 == casl x0, x1, [x2]
0x41,0xfc,0xe0,0xc8 == casal x0, x1, [x2]
0x41,0x80,0x20,0xf8 == swp x0, x1, [x2]
0x41,0x80,0x20,0x38 == swpb w0, w1, [x2]
0x41,0x80,0x60,0x78 == swplh w0, w1, [x2]
0xe1,0x83,0xe0,0xf8 == swpal x0, x1, [sp]
0x41,0x00,0xa0,0xf8 == ldadda x0, x1, [x2]
0x41,0x10,0x60,0xf8 == ldclrl x0, x1, [x2]
0x41,0x20,0xe0,0xf8 == ldeoral x0, x1, [x2]
0x41,0x30,0x20,0xf8 == ldset x0, x1, [x2]
0x41,0x40,0xa0,0xb8 == ldsmaxa w0, w1, [x2]
0x41,0x50,0x60,0x38 == ldsminlb w0, w1, [x2]
0x41,0x60,0xe0,0x78 == ldumaxalh w0, w1, [x2]
0x41,0x70,0x20,0xb8 == ldumin w0, w1, [x2]
0xab,0x51,0xe7,0x78 == ldsminalh w7, w11, [x13]
0x5f,0x00,0x60,0x38 == staddlb w0, [x2]
0x5f,0x10,0x60,0x78 == stclrlh w0, [x2]
0x5f,0x20,0x60,0xb8 == steorl w0, [x2]
0x5f,0x30,0x60,0xf8 == stsetl x0, [x2]
0x5f,0x40,0x20,0x38 == stsmaxb w0, [x2]
0x5f,0x50,0x20,0x78 == stsminh w0, [x2]
0x5f,0x60,0x20,0xb8 == stumax w0, [x2]
0x5f,0x70,0x20,0xf8 == stumin x0, [x2]
0xff,0x53,0x7d,0xf8 == stsminl x29, [sp]
0x82,0x7c,0x20,0x48 == casp x0, x1, x2, x3, [x4]
0x82,0x7c,0x20,0x08 == casp w0, w1, w2, w3, [x4]

27
suite/MC/AArch64/armv8.1a-lor.s.cs
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@ -1,14 +1,15 @@
# CS_ARCH_AARCH64, 0, None
0x20,0x7c,0xdf,0x08 = ldlarb w0, [x1]
0x20,0x7c,0xdf,0x48 = ldlarh w0, [x1]
0x20,0x7c,0xdf,0x88 = ldlar w0, [x1]
0x20,0x7c,0xdf,0xc8 = ldlar x0, [x1]
0x20,0x7c,0x9f,0x08 = stllrb w0, [x1]
0x20,0x7c,0x9f,0x48 = stllrh w0, [x1]
0x20,0x7c,0x9f,0x88 = stllr w0, [x1]
0x20,0x7c,0x9f,0xc8 = stllr x0, [x1]
0x00,0xa4,0x18,0xd5 = msr LORSA_EL1, x0
0x20,0xa4,0x18,0xd5 = msr LOREA_EL1, x0
0x40,0xa4,0x18,0xd5 = msr LORN_EL1, x0
0x60,0xa4,0x18,0xd5 = msr LORC_EL1, x0
0xe0,0xa4,0x38,0xd5 = mrs x0, LORID_EL1
0x20,0x7c,0xdf,0x08 == ldlarb w0, [x1]
0x20,0x7c,0xdf,0x48 == ldlarh w0, [x1]
0x20,0x7c,0xdf,0x88 == ldlar w0, [x1]
0x20,0x7c,0xdf,0xc8 == ldlar x0, [x1]
0x20,0x7c,0x9f,0x08 == stllrb w0, [x1]
0x20,0x7c,0x9f,0x48 == stllrh w0, [x1]
0x20,0x7c,0x9f,0x88 == stllr w0, [x1]
0x20,0x7c,0x9f,0xc8 == stllr x0, [x1]
0x00,0xa4,0x18,0xd5 == msr LORSA_EL1, x0
0x20,0xa4,0x18,0xd5 == msr LOREA_EL1, x0
0x40,0xa4,0x18,0xd5 == msr LORN_EL1, x0
0x60,0xa4,0x18,0xd5 == msr LORC_EL1, x0
0xe0,0xa4,0x38,0xd5 == mrs x0, LORID_EL1

21
suite/MC/AArch64/armv8.1a-lor.txt.cs Normal file
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@ -0,0 +1,21 @@
# CS_ARCH_AARCH64, None, None
# This regression test file is new. The option flags could not be determined.
# LLVM uses the following mattr = ['mattr=+v8.1a']
0x20,0x7c,0xdf,0x08 == ldlarb w0, [x1]
0x20,0x7c,0xdf,0x48 == ldlarh w0, [x1]
0x20,0x7c,0xdf,0x88 == ldlar w0, [x1]
0x20,0x7c,0xdf,0xc8 == ldlar x0, [x1]
0x20,0x7c,0x9f,0x08 == stllrb w0, [x1]
0x20,0x7c,0x9f,0x48 == stllrh w0, [x1]
0x20,0x7c,0x9f,0x88 == stllr w0, [x1]
0x20,0x7c,0x9f,0xc8 == stllr x0, [x1]
0x00,0xa4,0x18,0xd5 == msr LORSA_EL1, x0
0x20,0xa4,0x18,0xd5 == msr LOREA_EL1, x0
0x40,0xa4,0x18,0xd5 == msr LORN_EL1, x0
0x60,0xa4,0x18,0xd5 == msr LORC_EL1, x0
0xe0,0xa4,0x18,0xd5 == msr S3_0_C10_C4_7, x0
0x00,0xa4,0x38,0xd5 == mrs x0, LORSA_EL1
0x20,0xa4,0x38,0xd5 == mrs x0, LOREA_EL1
0x40,0xa4,0x38,0xd5 == mrs x0, LORN_EL1
0x60,0xa4,0x38,0xd5 == mrs x0, LORC_EL1
0xe0,0xa4,0x38,0xd5 == mrs x0, LORID_EL1

913
suite/MC/AArch64/armv8.1a-lse.s.cs
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@ -1,457 +1,458 @@
# CS_ARCH_AARCH64, 0, None
0x41,0x7c,0xa0,0x88 = cas w0, w1, [x2]
0xe3,0x7f,0xa2,0x88 = cas w2, w3, [sp]
0x41,0x7c,0xe0,0x88 = casa w0, w1, [x2]
0xe3,0x7f,0xe2,0x88 = casa w2, w3, [sp]
0x41,0xfc,0xa0,0x88 = casl w0, w1, [x2]
0xe3,0xff,0xa2,0x88 = casl w2, w3, [sp]
0x41,0xfc,0xe0,0x88 = casal w0, w1, [x2]
0xe3,0xff,0xe2,0x88 = casal w2, w3, [sp]
0x41,0x7c,0xa0,0x08 = casb w0, w1, [x2]
0xe3,0x7f,0xa2,0x08 = casb w2, w3, [sp]
0x41,0x7c,0xa0,0x48 = cash w0, w1, [x2]
0xe3,0x7f,0xa2,0x48 = cash w2, w3, [sp]
0x41,0x7c,0xe0,0x08 = casab w0, w1, [x2]
0xe3,0x7f,0xe2,0x08 = casab w2, w3, [sp]
0x41,0xfc,0xa0,0x08 = caslb w0, w1, [x2]
0xe3,0xff,0xa2,0x08 = caslb w2, w3, [sp]
0x41,0xfc,0xe0,0x08 = casalb w0, w1, [x2]
0xe3,0xff,0xe2,0x08 = casalb w2, w3, [sp]
0x41,0x7c,0xe0,0x48 = casah w0, w1, [x2]
0xe3,0x7f,0xe2,0x48 = casah w2, w3, [sp]
0x41,0xfc,0xa0,0x48 = caslh w0, w1, [x2]
0xe3,0xff,0xa2,0x48 = caslh w2, w3, [sp]
0x41,0xfc,0xe0,0x48 = casalh w0, w1, [x2]
0xe3,0xff,0xe2,0x48 = casalh w2, w3, [sp]
0x41,0x7c,0xa0,0xc8 = cas x0, x1, [x2]
0xe3,0x7f,0xa2,0xc8 = cas x2, x3, [sp]
0x41,0x7c,0xe0,0xc8 = casa x0, x1, [x2]
0xe3,0x7f,0xe2,0xc8 = casa x2, x3, [sp]
0x41,0xfc,0xa0,0xc8 = casl x0, x1, [x2]
0xe3,0xff,0xa2,0xc8 = casl x2, x3, [sp]
0x41,0xfc,0xe0,0xc8 = casal x0, x1, [x2]
0xe3,0xff,0xe2,0xc8 = casal x2, x3, [sp]
0x41,0x80,0x20,0xb8 = swp w0, w1, [x2]
0xe3,0x83,0x22,0xb8 = swp w2, w3, [sp]
0x41,0x80,0xa0,0xb8 = swpa w0, w1, [x2]
0xe3,0x83,0xa2,0xb8 = swpa w2, w3, [sp]
0x41,0x80,0x60,0xb8 = swpl w0, w1, [x2]
0xe3,0x83,0x62,0xb8 = swpl w2, w3, [sp]
0x41,0x80,0xe0,0xb8 = swpal w0, w1, [x2]
0xe3,0x83,0xe2,0xb8 = swpal w2, w3, [sp]
0x41,0x80,0x20,0x38 = swpb w0, w1, [x2]
0xe3,0x83,0x22,0x38 = swpb w2, w3, [sp]
0x41,0x80,0x20,0x78 = swph w0, w1, [x2]
0xe3,0x83,0x22,0x78 = swph w2, w3, [sp]
0x41,0x80,0xa0,0x38 = swpab w0, w1, [x2]
0xe3,0x83,0xa2,0x38 = swpab w2, w3, [sp]
0x41,0x80,0x60,0x38 = swplb w0, w1, [x2]
0xe3,0x83,0x62,0x38 = swplb w2, w3, [sp]
0x41,0x80,0xe0,0x38 = swpalb w0, w1, [x2]
0xe3,0x83,0xe2,0x38 = swpalb w2, w3, [sp]
0x41,0x80,0xa0,0x78 = swpah w0, w1, [x2]
0xe3,0x83,0xa2,0x78 = swpah w2, w3, [sp]
0x41,0x80,0x60,0x78 = swplh w0, w1, [x2]
0xe3,0x83,0x62,0x78 = swplh w2, w3, [sp]
0x41,0x80,0xe0,0x78 = swpalh w0, w1, [x2]
0xe3,0x83,0xe2,0x78 = swpalh w2, w3, [sp]
0x41,0x80,0x20,0xf8 = swp x0, x1, [x2]
0xe3,0x83,0x22,0xf8 = swp x2, x3, [sp]
0x41,0x80,0xa0,0xf8 = swpa x0, x1, [x2]
0xe3,0x83,0xa2,0xf8 = swpa x2, x3, [sp]
0x41,0x80,0x60,0xf8 = swpl x0, x1, [x2]
0xe3,0x83,0x62,0xf8 = swpl x2, x3, [sp]
0x41,0x80,0xe0,0xf8 = swpal x0, x1, [x2]
0xe3,0x83,0xe2,0xf8 = swpal x2, x3, [sp]
0xa2,0x7c,0x20,0x08 = casp w0, w1, w2, w3, [x5]
0xe6,0x7f,0x24,0x08 = casp w4, w5, w6, w7, [sp]
0x42,0x7c,0x20,0x48 = casp x0, x1, x2, x3, [x2]
0xe6,0x7f,0x24,0x48 = casp x4, x5, x6, x7, [sp]
0xa2,0x7c,0x60,0x08 = caspa w0, w1, w2, w3, [x5]
0xe6,0x7f,0x64,0x08 = caspa w4, w5, w6, w7, [sp]
0x42,0x7c,0x60,0x48 = caspa x0, x1, x2, x3, [x2]
0xe6,0x7f,0x64,0x48 = caspa x4, x5, x6, x7, [sp]
0xa2,0xfc,0x20,0x08 = caspl w0, w1, w2, w3, [x5]
0xe6,0xff,0x24,0x08 = caspl w4, w5, w6, w7, [sp]
0x42,0xfc,0x20,0x48 = caspl x0, x1, x2, x3, [x2]
0xe6,0xff,0x24,0x48 = caspl x4, x5, x6, x7, [sp]
0xa2,0xfc,0x60,0x08 = caspal w0, w1, w2, w3, [x5]
0xe6,0xff,0x64,0x08 = caspal w4, w5, w6, w7, [sp]
0x42,0xfc,0x60,0x48 = caspal x0, x1, x2, x3, [x2]
0xe6,0xff,0x64,0x48 = caspal x4, x5, x6, x7, [sp]
0x41,0x00,0x20,0xb8 = ldadd w0, w1, [x2]
0xe3,0x03,0x22,0xb8 = ldadd w2, w3, [sp]
0x41,0x00,0xa0,0xb8 = ldadda w0, w1, [x2]
0xe3,0x03,0xa2,0xb8 = ldadda w2, w3, [sp]
0x41,0x00,0x60,0xb8 = ldaddl w0, w1, [x2]
0xe3,0x03,0x62,0xb8 = ldaddl w2, w3, [sp]
0x41,0x00,0xe0,0xb8 = ldaddal w0, w1, [x2]
0xe3,0x03,0xe2,0xb8 = ldaddal w2, w3, [sp]
0x41,0x00,0x20,0x38 = ldaddb w0, w1, [x2]
0xe3,0x03,0x22,0x38 = ldaddb w2, w3, [sp]
0x41,0x00,0x20,0x78 = ldaddh w0, w1, [x2]
0xe3,0x03,0x22,0x78 = ldaddh w2, w3, [sp]
0x41,0x00,0xa0,0x38 = ldaddab w0, w1, [x2]
0xe3,0x03,0xa2,0x38 = ldaddab w2, w3, [sp]
0x41,0x00,0x60,0x38 = ldaddlb w0, w1, [x2]
0xe3,0x03,0x62,0x38 = ldaddlb w2, w3, [sp]
0x41,0x00,0xe0,0x38 = ldaddalb w0, w1, [x2]
0xe3,0x03,0xe2,0x38 = ldaddalb w2, w3, [sp]
0x41,0x00,0xa0,0x78 = ldaddah w0, w1, [x2]
0xe3,0x03,0xa2,0x78 = ldaddah w2, w3, [sp]
0x41,0x00,0x60,0x78 = ldaddlh w0, w1, [x2]
0xe3,0x03,0x62,0x78 = ldaddlh w2, w3, [sp]
0x41,0x00,0xe0,0x78 = ldaddalh w0, w1, [x2]
0xe3,0x03,0xe2,0x78 = ldaddalh w2, w3, [sp]
0x41,0x00,0x20,0xf8 = ldadd x0, x1, [x2]
0xe3,0x03,0x22,0xf8 = ldadd x2, x3, [sp]
0x41,0x00,0xa0,0xf8 = ldadda x0, x1, [x2]
0xe3,0x03,0xa2,0xf8 = ldadda x2, x3, [sp]
0x41,0x00,0x60,0xf8 = ldaddl x0, x1, [x2]
0xe3,0x03,0x62,0xf8 = ldaddl x2, x3, [sp]
0x41,0x00,0xe0,0xf8 = ldaddal x0, x1, [x2]
0xe3,0x03,0xe2,0xf8 = ldaddal x2, x3, [sp]
0x41,0x10,0x20,0xb8 = ldclr w0, w1, [x2]
0xe3,0x13,0x22,0xb8 = ldclr w2, w3, [sp]
0x41,0x10,0xa0,0xb8 = ldclra w0, w1, [x2]
0xe3,0x13,0xa2,0xb8 = ldclra w2, w3, [sp]
0x41,0x10,0x60,0xb8 = ldclrl w0, w1, [x2]
0xe3,0x13,0x62,0xb8 = ldclrl w2, w3, [sp]
0x41,0x10,0xe0,0xb8 = ldclral w0, w1, [x2]
0xe3,0x13,0xe2,0xb8 = ldclral w2, w3, [sp]
0x41,0x10,0x20,0x38 = ldclrb w0, w1, [x2]
0xe3,0x13,0x22,0x38 = ldclrb w2, w3, [sp]
0x41,0x10,0x20,0x78 = ldclrh w0, w1, [x2]
0xe3,0x13,0x22,0x78 = ldclrh w2, w3, [sp]
0x41,0x10,0xa0,0x38 = ldclrab w0, w1, [x2]
0xe3,0x13,0xa2,0x38 = ldclrab w2, w3, [sp]
0x41,0x10,0x60,0x38 = ldclrlb w0, w1, [x2]
0xe3,0x13,0x62,0x38 = ldclrlb w2, w3, [sp]
0x41,0x10,0xe0,0x38 = ldclralb w0, w1, [x2]
0xe3,0x13,0xe2,0x38 = ldclralb w2, w3, [sp]
0x41,0x10,0xa0,0x78 = ldclrah w0, w1, [x2]
0xe3,0x13,0xa2,0x78 = ldclrah w2, w3, [sp]
0x41,0x10,0x60,0x78 = ldclrlh w0, w1, [x2]
0xe3,0x13,0x62,0x78 = ldclrlh w2, w3, [sp]
0x41,0x10,0xe0,0x78 = ldclralh w0, w1, [x2]
0xe3,0x13,0xe2,0x78 = ldclralh w2, w3, [sp]
0x41,0x10,0x20,0xf8 = ldclr x0, x1, [x2]
0xe3,0x13,0x22,0xf8 = ldclr x2, x3, [sp]
0x41,0x10,0xa0,0xf8 = ldclra x0, x1, [x2]
0xe3,0x13,0xa2,0xf8 = ldclra x2, x3, [sp]
0x41,0x10,0x60,0xf8 = ldclrl x0, x1, [x2]
0xe3,0x13,0x62,0xf8 = ldclrl x2, x3, [sp]
0x41,0x10,0xe0,0xf8 = ldclral x0, x1, [x2]
0xe3,0x13,0xe2,0xf8 = ldclral x2, x3, [sp]
0x41,0x20,0x20,0xb8 = ldeor w0, w1, [x2]
0xe3,0x23,0x22,0xb8 = ldeor w2, w3, [sp]
0x41,0x20,0xa0,0xb8 = ldeora w0, w1, [x2]
0xe3,0x23,0xa2,0xb8 = ldeora w2, w3, [sp]
0x41,0x20,0x60,0xb8 = ldeorl w0, w1, [x2]
0xe3,0x23,0x62,0xb8 = ldeorl w2, w3, [sp]
0x41,0x20,0xe0,0xb8 = ldeoral w0, w1, [x2]
0xe3,0x23,0xe2,0xb8 = ldeoral w2, w3, [sp]
0x41,0x20,0x20,0x38 = ldeorb w0, w1, [x2]
0xe3,0x23,0x22,0x38 = ldeorb w2, w3, [sp]
0x41,0x20,0x20,0x78 = ldeorh w0, w1, [x2]
0xe3,0x23,0x22,0x78 = ldeorh w2, w3, [sp]
0x41,0x20,0xa0,0x38 = ldeorab w0, w1, [x2]
0xe3,0x23,0xa2,0x38 = ldeorab w2, w3, [sp]
0x41,0x20,0x60,0x38 = ldeorlb w0, w1, [x2]
0xe3,0x23,0x62,0x38 = ldeorlb w2, w3, [sp]
0x41,0x20,0xe0,0x38 = ldeoralb w0, w1, [x2]
0xe3,0x23,0xe2,0x38 = ldeoralb w2, w3, [sp]
0x41,0x20,0xa0,0x78 = ldeorah w0, w1, [x2]
0xe3,0x23,0xa2,0x78 = ldeorah w2, w3, [sp]
0x41,0x20,0x60,0x78 = ldeorlh w0, w1, [x2]
0xe3,0x23,0x62,0x78 = ldeorlh w2, w3, [sp]
0x41,0x20,0xe0,0x78 = ldeoralh w0, w1, [x2]
0xe3,0x23,0xe2,0x78 = ldeoralh w2, w3, [sp]
0x41,0x20,0x20,0xf8 = ldeor x0, x1, [x2]
0xe3,0x23,0x22,0xf8 = ldeor x2, x3, [sp]
0x41,0x20,0xa0,0xf8 = ldeora x0, x1, [x2]
0xe3,0x23,0xa2,0xf8 = ldeora x2, x3, [sp]
0x41,0x20,0x60,0xf8 = ldeorl x0, x1, [x2]
0xe3,0x23,0x62,0xf8 = ldeorl x2, x3, [sp]
0x41,0x20,0xe0,0xf8 = ldeoral x0, x1, [x2]
0xe3,0x23,0xe2,0xf8 = ldeoral x2, x3, [sp]
0x41,0x30,0x20,0xb8 = ldset w0, w1, [x2]
0xe3,0x33,0x22,0xb8 = ldset w2, w3, [sp]
0x41,0x30,0xa0,0xb8 = ldseta w0, w1, [x2]
0xe3,0x33,0xa2,0xb8 = ldseta w2, w3, [sp]
0x41,0x30,0x60,0xb8 = ldsetl w0, w1, [x2]
0xe3,0x33,0x62,0xb8 = ldsetl w2, w3, [sp]
0x41,0x30,0xe0,0xb8 = ldsetal w0, w1, [x2]
0xe3,0x33,0xe2,0xb8 = ldsetal w2, w3, [sp]
0x41,0x30,0x20,0x38 = ldsetb w0, w1, [x2]
0xe3,0x33,0x22,0x38 = ldsetb w2, w3, [sp]
0x41,0x30,0x20,0x78 = ldseth w0, w1, [x2]
0xe3,0x33,0x22,0x78 = ldseth w2, w3, [sp]
0x41,0x30,0xa0,0x38 = ldsetab w0, w1, [x2]
0xe3,0x33,0xa2,0x38 = ldsetab w2, w3, [sp]
0x41,0x30,0x60,0x38 = ldsetlb w0, w1, [x2]
0xe3,0x33,0x62,0x38 = ldsetlb w2, w3, [sp]
0x41,0x30,0xe0,0x38 = ldsetalb w0, w1, [x2]
0xe3,0x33,0xe2,0x38 = ldsetalb w2, w3, [sp]
0x41,0x30,0xa0,0x78 = ldsetah w0, w1, [x2]
0xe3,0x33,0xa2,0x78 = ldsetah w2, w3, [sp]
0x41,0x30,0x60,0x78 = ldsetlh w0, w1, [x2]
0xe3,0x33,0x62,0x78 = ldsetlh w2, w3, [sp]
0x41,0x30,0xe0,0x78 = ldsetalh w0, w1, [x2]
0xe3,0x33,0xe2,0x78 = ldsetalh w2, w3, [sp]
0x41,0x30,0x20,0xf8 = ldset x0, x1, [x2]
0xe3,0x33,0x22,0xf8 = ldset x2, x3, [sp]
0x41,0x30,0xa0,0xf8 = ldseta x0, x1, [x2]
0xe3,0x33,0xa2,0xf8 = ldseta x2, x3, [sp]
0x41,0x30,0x60,0xf8 = ldsetl x0, x1, [x2]
0xe3,0x33,0x62,0xf8 = ldsetl x2, x3, [sp]
0x41,0x30,0xe0,0xf8 = ldsetal x0, x1, [x2]
0xe3,0x33,0xe2,0xf8 = ldsetal x2, x3, [sp]
0x41,0x40,0x20,0xb8 = ldsmax w0, w1, [x2]
0xe3,0x43,0x22,0xb8 = ldsmax w2, w3, [sp]
0x41,0x40,0xa0,0xb8 = ldsmaxa w0, w1, [x2]
0xe3,0x43,0xa2,0xb8 = ldsmaxa w2, w3, [sp]
0x41,0x40,0x60,0xb8 = ldsmaxl w0, w1, [x2]
0xe3,0x43,0x62,0xb8 = ldsmaxl w2, w3, [sp]
0x41,0x40,0xe0,0xb8 = ldsmaxal w0, w1, [x2]
0xe3,0x43,0xe2,0xb8 = ldsmaxal w2, w3, [sp]
0x41,0x40,0x20,0x38 = ldsmaxb w0, w1, [x2]
0xe3,0x43,0x22,0x38 = ldsmaxb w2, w3, [sp]
0x41,0x40,0x20,0x78 = ldsmaxh w0, w1, [x2]
0xe3,0x43,0x22,0x78 = ldsmaxh w2, w3, [sp]
0x41,0x40,0xa0,0x38 = ldsmaxab w0, w1, [x2]
0xe3,0x43,0xa2,0x38 = ldsmaxab w2, w3, [sp]
0x41,0x40,0x60,0x38 = ldsmaxlb w0, w1, [x2]
0xe3,0x43,0x62,0x38 = ldsmaxlb w2, w3, [sp]
0x41,0x40,0xe0,0x38 = ldsmaxalb w0, w1, [x2]
0xe3,0x43,0xe2,0x38 = ldsmaxalb w2, w3, [sp]
0x41,0x40,0xa0,0x78 = ldsmaxah w0, w1, [x2]
0xe3,0x43,0xa2,0x78 = ldsmaxah w2, w3, [sp]
0x41,0x40,0x60,0x78 = ldsmaxlh w0, w1, [x2]
0xe3,0x43,0x62,0x78 = ldsmaxlh w2, w3, [sp]
0x41,0x40,0xe0,0x78 = ldsmaxalh w0, w1, [x2]
0xe3,0x43,0xe2,0x78 = ldsmaxalh w2, w3, [sp]
0x41,0x40,0x20,0xf8 = ldsmax x0, x1, [x2]
0xe3,0x43,0x22,0xf8 = ldsmax x2, x3, [sp]
0x41,0x40,0xa0,0xf8 = ldsmaxa x0, x1, [x2]
0xe3,0x43,0xa2,0xf8 = ldsmaxa x2, x3, [sp]
0x41,0x40,0x60,0xf8 = ldsmaxl x0, x1, [x2]
0xe3,0x43,0x62,0xf8 = ldsmaxl x2, x3, [sp]
0x41,0x40,0xe0,0xf8 = ldsmaxal x0, x1, [x2]
0xe3,0x43,0xe2,0xf8 = ldsmaxal x2, x3, [sp]
0x41,0x50,0x20,0xb8 = ldsmin w0, w1, [x2]
0xe3,0x53,0x22,0xb8 = ldsmin w2, w3, [sp]
0x41,0x50,0xa0,0xb8 = ldsmina w0, w1, [x2]
0xe3,0x53,0xa2,0xb8 = ldsmina w2, w3, [sp]
0x41,0x50,0x60,0xb8 = ldsminl w0, w1, [x2]
0xe3,0x53,0x62,0xb8 = ldsminl w2, w3, [sp]
0x41,0x50,0xe0,0xb8 = ldsminal w0, w1, [x2]
0xe3,0x53,0xe2,0xb8 = ldsminal w2, w3, [sp]
0x41,0x50,0x20,0x38 = ldsminb w0, w1, [x2]
0xe3,0x53,0x22,0x38 = ldsminb w2, w3, [sp]
0x41,0x50,0x20,0x78 = ldsminh w0, w1, [x2]
0xe3,0x53,0x22,0x78 = ldsminh w2, w3, [sp]
0x41,0x50,0xa0,0x38 = ldsminab w0, w1, [x2]
0xe3,0x53,0xa2,0x38 = ldsminab w2, w3, [sp]
0x41,0x50,0x60,0x38 = ldsminlb w0, w1, [x2]
0xe3,0x53,0x62,0x38 = ldsminlb w2, w3, [sp]
0x41,0x50,0xe0,0x38 = ldsminalb w0, w1, [x2]
0xe3,0x53,0xe2,0x38 = ldsminalb w2, w3, [sp]
0x41,0x50,0xa0,0x78 = ldsminah w0, w1, [x2]
0xe3,0x53,0xa2,0x78 = ldsminah w2, w3, [sp]
0x41,0x50,0x60,0x78 = ldsminlh w0, w1, [x2]
0xe3,0x53,0x62,0x78 = ldsminlh w2, w3, [sp]
0x41,0x50,0xe0,0x78 = ldsminalh w0, w1, [x2]
0xe3,0x53,0xe2,0x78 = ldsminalh w2, w3, [sp]
0x41,0x50,0x20,0xf8 = ldsmin x0, x1, [x2]
0xe3,0x53,0x22,0xf8 = ldsmin x2, x3, [sp]
0x41,0x50,0xa0,0xf8 = ldsmina x0, x1, [x2]
0xe3,0x53,0xa2,0xf8 = ldsmina x2, x3, [sp]
0x41,0x50,0x60,0xf8 = ldsminl x0, x1, [x2]
0xe3,0x53,0x62,0xf8 = ldsminl x2, x3, [sp]
0x41,0x50,0xe0,0xf8 = ldsminal x0, x1, [x2]
0xe3,0x53,0xe2,0xf8 = ldsminal x2, x3, [sp]
0x41,0x60,0x20,0xb8 = ldumax w0, w1, [x2]
0xe3,0x63,0x22,0xb8 = ldumax w2, w3, [sp]
0x41,0x60,0xa0,0xb8 = ldumaxa w0, w1, [x2]
0xe3,0x63,0xa2,0xb8 = ldumaxa w2, w3, [sp]
0x41,0x60,0x60,0xb8 = ldumaxl w0, w1, [x2]
0xe3,0x63,0x62,0xb8 = ldumaxl w2, w3, [sp]
0x41,0x60,0xe0,0xb8 = ldumaxal w0, w1, [x2]
0xe3,0x63,0xe2,0xb8 = ldumaxal w2, w3, [sp]
0x41,0x60,0x20,0x38 = ldumaxb w0, w1, [x2]
0xe3,0x63,0x22,0x38 = ldumaxb w2, w3, [sp]
0x41,0x60,0x20,0x78 = ldumaxh w0, w1, [x2]
0xe3,0x63,0x22,0x78 = ldumaxh w2, w3, [sp]
0x41,0x60,0xa0,0x38 = ldumaxab w0, w1, [x2]
0xe3,0x63,0xa2,0x38 = ldumaxab w2, w3, [sp]
0x41,0x60,0x60,0x38 = ldumaxlb w0, w1, [x2]
0xe3,0x63,0x62,0x38 = ldumaxlb w2, w3, [sp]
0x41,0x60,0xe0,0x38 = ldumaxalb w0, w1, [x2]
0xe3,0x63,0xe2,0x38 = ldumaxalb w2, w3, [sp]
0x41,0x60,0xa0,0x78 = ldumaxah w0, w1, [x2]
0xe3,0x63,0xa2,0x78 = ldumaxah w2, w3, [sp]
0x41,0x60,0x60,0x78 = ldumaxlh w0, w1, [x2]
0xe3,0x63,0x62,0x78 = ldumaxlh w2, w3, [sp]
0x41,0x60,0xe0,0x78 = ldumaxalh w0, w1, [x2]
0xe3,0x63,0xe2,0x78 = ldumaxalh w2, w3, [sp]
0x41,0x60,0x20,0xf8 = ldumax x0, x1, [x2]
0xe3,0x63,0x22,0xf8 = ldumax x2, x3, [sp]
0x41,0x60,0xa0,0xf8 = ldumaxa x0, x1, [x2]
0xe3,0x63,0xa2,0xf8 = ldumaxa x2, x3, [sp]
0x41,0x60,0x60,0xf8 = ldumaxl x0, x1, [x2]
0xe3,0x63,0x62,0xf8 = ldumaxl x2, x3, [sp]
0x41,0x60,0xe0,0xf8 = ldumaxal x0, x1, [x2]
0xe3,0x63,0xe2,0xf8 = ldumaxal x2, x3, [sp]
0x41,0x70,0x20,0xb8 = ldumin w0, w1, [x2]
0xe3,0x73,0x22,0xb8 = ldumin w2, w3, [sp]
0x41,0x70,0xa0,0xb8 = ldumina w0, w1, [x2]
0xe3,0x73,0xa2,0xb8 = ldumina w2, w3, [sp]
0x41,0x70,0x60,0xb8 = lduminl w0, w1, [x2]
0xe3,0x73,0x62,0xb8 = lduminl w2, w3, [sp]
0x41,0x70,0xe0,0xb8 = lduminal w0, w1, [x2]
0xe3,0x73,0xe2,0xb8 = lduminal w2, w3, [sp]
0x41,0x70,0x20,0x38 = lduminb w0, w1, [x2]
0xe3,0x73,0x22,0x38 = lduminb w2, w3, [sp]
0x41,0x70,0x20,0x78 = lduminh w0, w1, [x2]
0xe3,0x73,0x22,0x78 = lduminh w2, w3, [sp]
0x41,0x70,0xa0,0x38 = lduminab w0, w1, [x2]
0xe3,0x73,0xa2,0x38 = lduminab w2, w3, [sp]
0x41,0x70,0x60,0x38 = lduminlb w0, w1, [x2]
0xe3,0x73,0x62,0x38 = lduminlb w2, w3, [sp]
0x41,0x70,0xe0,0x38 = lduminalb w0, w1, [x2]
0xe3,0x73,0xe2,0x38 = lduminalb w2, w3, [sp]
0x41,0x70,0xa0,0x78 = lduminah w0, w1, [x2]
0xe3,0x73,0xa2,0x78 = lduminah w2, w3, [sp]
0x41,0x70,0x60,0x78 = lduminlh w0, w1, [x2]
0xe3,0x73,0x62,0x78 = lduminlh w2, w3, [sp]
0x41,0x70,0xe0,0x78 = lduminalh w0, w1, [x2]
0xe3,0x73,0xe2,0x78 = lduminalh w2, w3, [sp]
0x41,0x70,0x20,0xf8 = ldumin x0, x1, [x2]
0xe3,0x73,0x22,0xf8 = ldumin x2, x3, [sp]
0x41,0x70,0xa0,0xf8 = ldumina x0, x1, [x2]
0xe3,0x73,0xa2,0xf8 = ldumina x2, x3, [sp]
0x41,0x70,0x60,0xf8 = lduminl x0, x1, [x2]
0xe3,0x73,0x62,0xf8 = lduminl x2, x3, [sp]
0x41,0x70,0xe0,0xf8 = lduminal x0, x1, [x2]
0xe3,0x73,0xe2,0xf8 = lduminal x2, x3, [sp]
0x5f,0x00,0x20,0xb8 = stadd w0, [x2]
0xff,0x03,0x22,0xb8 = stadd w2, [sp]
0x5f,0x00,0x60,0xb8 = staddl w0, [x2]
0xff,0x03,0x62,0xb8 = staddl w2, [sp]
0x5f,0x00,0x20,0x38 = staddb w0, [x2]
0xff,0x03,0x22,0x38 = staddb w2, [sp]
0x5f,0x00,0x20,0x78 = staddh w0, [x2]
0xff,0x03,0x22,0x78 = staddh w2, [sp]
0x5f,0x00,0x60,0x38 = staddlb w0, [x2]
0xff,0x03,0x62,0x38 = staddlb w2, [sp]
0x5f,0x00,0x60,0x78 = staddlh w0, [x2]
0xff,0x03,0x62,0x78 = staddlh w2, [sp]
0x5f,0x00,0x20,0xf8 = stadd x0, [x2]
0xff,0x03,0x22,0xf8 = stadd x2, [sp]
0x5f,0x00,0x60,0xf8 = staddl x0, [x2]
0xff,0x03,0x62,0xf8 = staddl x2, [sp]
0x5f,0x10,0x20,0xb8 = stclr w0, [x2]
0xff,0x13,0x22,0xb8 = stclr w2, [sp]
0x5f,0x10,0x60,0xb8 = stclrl w0, [x2]
0xff,0x13,0x62,0xb8 = stclrl w2, [sp]
0x5f,0x10,0x20,0x38 = stclrb w0, [x2]
0xff,0x13,0x22,0x38 = stclrb w2, [sp]
0x5f,0x10,0x20,0x78 = stclrh w0, [x2]
0xff,0x13,0x22,0x78 = stclrh w2, [sp]
0x5f,0x10,0x60,0x38 = stclrlb w0, [x2]
0xff,0x13,0x62,0x38 = stclrlb w2, [sp]
0x5f,0x10,0x60,0x78 = stclrlh w0, [x2]
0xff,0x13,0x62,0x78 = stclrlh w2, [sp]
0x5f,0x10,0x20,0xf8 = stclr x0, [x2]
0xff,0x13,0x22,0xf8 = stclr x2, [sp]
0x5f,0x10,0x60,0xf8 = stclrl x0, [x2]
0xff,0x13,0x62,0xf8 = stclrl x2, [sp]
0x5f,0x20,0x20,0xb8 = steor w0, [x2]
0xff,0x23,0x22,0xb8 = steor w2, [sp]
0x5f,0x20,0x60,0xb8 = steorl w0, [x2]
0xff,0x23,0x62,0xb8 = steorl w2, [sp]
0x5f,0x20,0x20,0x38 = steorb w0, [x2]
0xff,0x23,0x22,0x38 = steorb w2, [sp]
0x5f,0x20,0x20,0x78 = steorh w0, [x2]
0xff,0x23,0x22,0x78 = steorh w2, [sp]
0x5f,0x20,0x60,0x38 = steorlb w0, [x2]
0xff,0x23,0x62,0x38 = steorlb w2, [sp]
0x5f,0x20,0x60,0x78 = steorlh w0, [x2]
0xff,0x23,0x62,0x78 = steorlh w2, [sp]
0x5f,0x20,0x20,0xf8 = steor x0, [x2]
0xff,0x23,0x22,0xf8 = steor x2, [sp]
0x5f,0x20,0x60,0xf8 = steorl x0, [x2]
0xff,0x23,0x62,0xf8 = steorl x2, [sp]
0x5f,0x30,0x20,0xb8 = stset w0, [x2]
0xff,0x33,0x22,0xb8 = stset w2, [sp]
0x5f,0x30,0x60,0xb8 = stsetl w0, [x2]
0xff,0x33,0x62,0xb8 = stsetl w2, [sp]
0x5f,0x30,0x20,0x38 = stsetb w0, [x2]
0xff,0x33,0x22,0x38 = stsetb w2, [sp]
0x5f,0x30,0x20,0x78 = stseth w0, [x2]
0xff,0x33,0x22,0x78 = stseth w2, [sp]
0x5f,0x30,0x60,0x38 = stsetlb w0, [x2]
0xff,0x33,0x62,0x38 = stsetlb w2, [sp]
0x5f,0x30,0x60,0x78 = stsetlh w0, [x2]
0xff,0x33,0x62,0x78 = stsetlh w2, [sp]
0x5f,0x30,0x20,0xf8 = stset x0, [x2]
0xff,0x33,0x22,0xf8 = stset x2, [sp]
0x5f,0x30,0x60,0xf8 = stsetl x0, [x2]
0xff,0x33,0x62,0xf8 = stsetl x2, [sp]
0x5f,0x40,0x20,0xb8 = stsmax w0, [x2]
0xff,0x43,0x22,0xb8 = stsmax w2, [sp]
0x5f,0x40,0x60,0xb8 = stsmaxl w0, [x2]
0xff,0x43,0x62,0xb8 = stsmaxl w2, [sp]
0x5f,0x40,0x20,0x38 = stsmaxb w0, [x2]
0xff,0x43,0x22,0x38 = stsmaxb w2, [sp]
0x5f,0x40,0x20,0x78 = stsmaxh w0, [x2]
0xff,0x43,0x22,0x78 = stsmaxh w2, [sp]
0x5f,0x40,0x60,0x38 = stsmaxlb w0, [x2]
0xff,0x43,0x62,0x38 = stsmaxlb w2, [sp]
0x5f,0x40,0x60,0x78 = stsmaxlh w0, [x2]
0xff,0x43,0x62,0x78 = stsmaxlh w2, [sp]
0x5f,0x40,0x20,0xf8 = stsmax x0, [x2]
0xff,0x43,0x22,0xf8 = stsmax x2, [sp]
0x5f,0x40,0x60,0xf8 = stsmaxl x0, [x2]
0xff,0x43,0x62,0xf8 = stsmaxl x2, [sp]
0x5f,0x50,0x20,0xb8 = stsmin w0, [x2]
0xff,0x53,0x22,0xb8 = stsmin w2, [sp]
0x5f,0x50,0x60,0xb8 = stsminl w0, [x2]
0xff,0x53,0x62,0xb8 = stsminl w2, [sp]
0x5f,0x50,0x20,0x38 = stsminb w0, [x2]
0xff,0x53,0x22,0x38 = stsminb w2, [sp]
0x5f,0x50,0x20,0x78 = stsminh w0, [x2]
0xff,0x53,0x22,0x78 = stsminh w2, [sp]
0x5f,0x50,0x60,0x38 = stsminlb w0, [x2]
0xff,0x53,0x62,0x38 = stsminlb w2, [sp]
0x5f,0x50,0x60,0x78 = stsminlh w0, [x2]
0xff,0x53,0x62,0x78 = stsminlh w2, [sp]
0x5f,0x50,0x20,0xf8 = stsmin x0, [x2]
0xff,0x53,0x22,0xf8 = stsmin x2, [sp]
0x5f,0x50,0x60,0xf8 = stsminl x0, [x2]
0xff,0x53,0x62,0xf8 = stsminl x2, [sp]
0x5f,0x60,0x20,0xb8 = stumax w0, [x2]
0xff,0x63,0x22,0xb8 = stumax w2, [sp]
0x5f,0x60,0x60,0xb8 = stumaxl w0, [x2]
0xff,0x63,0x62,0xb8 = stumaxl w2, [sp]
0x5f,0x60,0x20,0x38 = stumaxb w0, [x2]
0xff,0x63,0x22,0x38 = stumaxb w2, [sp]
0x5f,0x60,0x20,0x78 = stumaxh w0, [x2]
0xff,0x63,0x22,0x78 = stumaxh w2, [sp]
0x5f,0x60,0x60,0x38 = stumaxlb w0, [x2]
0xff,0x63,0x62,0x38 = stumaxlb w2, [sp]
0x5f,0x60,0x60,0x78 = stumaxlh w0, [x2]
0xff,0x63,0x62,0x78 = stumaxlh w2, [sp]
0x5f,0x60,0x20,0xf8 = stumax x0, [x2]
0xff,0x63,0x22,0xf8 = stumax x2, [sp]
0x5f,0x60,0x60,0xf8 = stumaxl x0, [x2]
0xff,0x63,0x62,0xf8 = stumaxl x2, [sp]
0x5f,0x70,0x20,0xb8 = stumin w0, [x2]
0xff,0x73,0x22,0xb8 = stumin w2, [sp]
0x5f,0x70,0x60,0xb8 = stuminl w0, [x2]
0xff,0x73,0x62,0xb8 = stuminl w2, [sp]
0x5f,0x70,0x20,0x38 = stuminb w0, [x2]
0xff,0x73,0x22,0x38 = stuminb w2, [sp]
0x5f,0x70,0x20,0x78 = stuminh w0, [x2]
0xff,0x73,0x22,0x78 = stuminh w2, [sp]
0x41,0x7c,0xa0,0x88 == cas w0, w1, [x2]
0xe3,0x7f,0xa2,0x88 == cas w2, w3, [sp]
0x41,0x7c,0xe0,0x88 == casa w0, w1, [x2]
0xe3,0x7f,0xe2,0x88 == casa w2, w3, [sp]
0x41,0xfc,0xa0,0x88 == casl w0, w1, [x2]
0xe3,0xff,0xa2,0x88 == casl w2, w3, [sp]
0x41,0xfc,0xe0,0x88 == casal w0, w1, [x2]
0xe3,0xff,0xe2,0x88 == casal w2, w3, [sp]
0x41,0x7c,0xa0,0x08 == casb w0, w1, [x2]
0xe3,0x7f,0xa2,0x08 == casb w2, w3, [sp]
0x41,0x7c,0xa0,0x48 == cash w0, w1, [x2]
0xe3,0x7f,0xa2,0x48 == cash w2, w3, [sp]
0x41,0x7c,0xe0,0x08 == casab w0, w1, [x2]
0xe3,0x7f,0xe2,0x08 == casab w2, w3, [sp]
0x41,0xfc,0xa0,0x08 == caslb w0, w1, [x2]
0xe3,0xff,0xa2,0x08 == caslb w2, w3, [sp]
0x41,0xfc,0xe0,0x08 == casalb w0, w1, [x2]
0xe3,0xff,0xe2,0x08 == casalb w2, w3, [sp]
0x41,0x7c,0xe0,0x48 == casah w0, w1, [x2]
0xe3,0x7f,0xe2,0x48 == casah w2, w3, [sp]
0x41,0xfc,0xa0,0x48 == caslh w0, w1, [x2]
0xe3,0xff,0xa2,0x48 == caslh w2, w3, [sp]
0x41,0xfc,0xe0,0x48 == casalh w0, w1, [x2]
0xe3,0xff,0xe2,0x48 == casalh w2, w3, [sp]
0x41,0x7c,0xa0,0xc8 == cas x0, x1, [x2]
0xe3,0x7f,0xa2,0xc8 == cas x2, x3, [sp]
0x41,0x7c,0xe0,0xc8 == casa x0, x1, [x2]
0xe3,0x7f,0xe2,0xc8 == casa x2, x3, [sp]
0x41,0xfc,0xa0,0xc8 == casl x0, x1, [x2]
0xe3,0xff,0xa2,0xc8 == casl x2, x3, [sp]
0x41,0xfc,0xe0,0xc8 == casal x0, x1, [x2]
0xe3,0xff,0xe2,0xc8 == casal x2, x3, [sp]
0x41,0x80,0x20,0xb8 == swp w0, w1, [x2]
0xe3,0x83,0x22,0xb8 == swp w2, w3, [sp]
0x41,0x80,0xa0,0xb8 == swpa w0, w1, [x2]
0xe3,0x83,0xa2,0xb8 == swpa w2, w3, [sp]
0x41,0x80,0x60,0xb8 == swpl w0, w1, [x2]
0xe3,0x83,0x62,0xb8 == swpl w2, w3, [sp]
0x41,0x80,0xe0,0xb8 == swpal w0, w1, [x2]
0xe3,0x83,0xe2,0xb8 == swpal w2, w3, [sp]
0x41,0x80,0x20,0x38 == swpb w0, w1, [x2]
0xe3,0x83,0x22,0x38 == swpb w2, w3, [sp]
0x41,0x80,0x20,0x78 == swph w0, w1, [x2]
0xe3,0x83,0x22,0x78 == swph w2, w3, [sp]
0x41,0x80,0xa0,0x38 == swpab w0, w1, [x2]
0xe3,0x83,0xa2,0x38 == swpab w2, w3, [sp]
0x41,0x80,0x60,0x38 == swplb w0, w1, [x2]
0xe3,0x83,0x62,0x38 == swplb w2, w3, [sp]
0x41,0x80,0xe0,0x38 == swpalb w0, w1, [x2]
0xe3,0x83,0xe2,0x38 == swpalb w2, w3, [sp]
0x41,0x80,0xa0,0x78 == swpah w0, w1, [x2]
0xe3,0x83,0xa2,0x78 == swpah w2, w3, [sp]
0x41,0x80,0x60,0x78 == swplh w0, w1, [x2]
0xe3,0x83,0x62,0x78 == swplh w2, w3, [sp]
0x41,0x80,0xe0,0x78 == swpalh w0, w1, [x2]
0xe3,0x83,0xe2,0x78 == swpalh w2, w3, [sp]
0x41,0x80,0x20,0xf8 == swp x0, x1, [x2]
0xe3,0x83,0x22,0xf8 == swp x2, x3, [sp]
0x41,0x80,0xa0,0xf8 == swpa x0, x1, [x2]
0xe3,0x83,0xa2,0xf8 == swpa x2, x3, [sp]
0x41,0x80,0x60,0xf8 == swpl x0, x1, [x2]
0xe3,0x83,0x62,0xf8 == swpl x2, x3, [sp]
0x41,0x80,0xe0,0xf8 == swpal x0, x1, [x2]
0xe3,0x83,0xe2,0xf8 == swpal x2, x3, [sp]
0xa2,0x7c,0x20,0x08 == casp w0, w1, w2, w3, [x5]
0xe6,0x7f,0x24,0x08 == casp w4, w5, w6, w7, [sp]
0x42,0x7c,0x20,0x48 == casp x0, x1, x2, x3, [x2]
0xe6,0x7f,0x24,0x48 == casp x4, x5, x6, x7, [sp]
0xa2,0x7c,0x60,0x08 == caspa w0, w1, w2, w3, [x5]
0xe6,0x7f,0x64,0x08 == caspa w4, w5, w6, w7, [sp]
0x42,0x7c,0x60,0x48 == caspa x0, x1, x2, x3, [x2]
0xe6,0x7f,0x64,0x48 == caspa x4, x5, x6, x7, [sp]
0xa2,0xfc,0x20,0x08 == caspl w0, w1, w2, w3, [x5]
0xe6,0xff,0x24,0x08 == caspl w4, w5, w6, w7, [sp]
0x42,0xfc,0x20,0x48 == caspl x0, x1, x2, x3, [x2]
0xe6,0xff,0x24,0x48 == caspl x4, x5, x6, x7, [sp]
0xa2,0xfc,0x60,0x08 == caspal w0, w1, w2, w3, [x5]
0xe6,0xff,0x64,0x08 == caspal w4, w5, w6, w7, [sp]
0x42,0xfc,0x60,0x48 == caspal x0, x1, x2, x3, [x2]
0xe6,0xff,0x64,0x48 == caspal x4, x5, x6, x7, [sp]
0x41,0x00,0x20,0xb8 == ldadd w0, w1, [x2]
0xe3,0x03,0x22,0xb8 == ldadd w2, w3, [sp]
0x41,0x00,0xa0,0xb8 == ldadda w0, w1, [x2]
0xe3,0x03,0xa2,0xb8 == ldadda w2, w3, [sp]
0x41,0x00,0x60,0xb8 == ldaddl w0, w1, [x2]
0xe3,0x03,0x62,0xb8 == ldaddl w2, w3, [sp]
0x41,0x00,0xe0,0xb8 == ldaddal w0, w1, [x2]
0xe3,0x03,0xe2,0xb8 == ldaddal w2, w3, [sp]
0x41,0x00,0x20,0x38 == ldaddb w0, w1, [x2]
0xe3,0x03,0x22,0x38 == ldaddb w2, w3, [sp]
0x41,0x00,0x20,0x78 == ldaddh w0, w1, [x2]
0xe3,0x03,0x22,0x78 == ldaddh w2, w3, [sp]
0x41,0x00,0xa0,0x38 == ldaddab w0, w1, [x2]
0xe3,0x03,0xa2,0x38 == ldaddab w2, w3, [sp]
0x41,0x00,0x60,0x38 == ldaddlb w0, w1, [x2]
0xe3,0x03,0x62,0x38 == ldaddlb w2, w3, [sp]
0x41,0x00,0xe0,0x38 == ldaddalb w0, w1, [x2]
0xe3,0x03,0xe2,0x38 == ldaddalb w2, w3, [sp]
0x41,0x00,0xa0,0x78 == ldaddah w0, w1, [x2]
0xe3,0x03,0xa2,0x78 == ldaddah w2, w3, [sp]
0x41,0x00,0x60,0x78 == ldaddlh w0, w1, [x2]
0xe3,0x03,0x62,0x78 == ldaddlh w2, w3, [sp]
0x41,0x00,0xe0,0x78 == ldaddalh w0, w1, [x2]
0xe3,0x03,0xe2,0x78 == ldaddalh w2, w3, [sp]
0x41,0x00,0x20,0xf8 == ldadd x0, x1, [x2]
0xe3,0x03,0x22,0xf8 == ldadd x2, x3, [sp]
0x41,0x00,0xa0,0xf8 == ldadda x0, x1, [x2]
0xe3,0x03,0xa2,0xf8 == ldadda x2, x3, [sp]
0x41,0x00,0x60,0xf8 == ldaddl x0, x1, [x2]
0xe3,0x03,0x62,0xf8 == ldaddl x2, x3, [sp]
0x41,0x00,0xe0,0xf8 == ldaddal x0, x1, [x2]
0xe3,0x03,0xe2,0xf8 == ldaddal x2, x3, [sp]
0x41,0x10,0x20,0xb8 == ldclr w0, w1, [x2]
0xe3,0x13,0x22,0xb8 == ldclr w2, w3, [sp]
0x41,0x10,0xa0,0xb8 == ldclra w0, w1, [x2]
0xe3,0x13,0xa2,0xb8 == ldclra w2, w3, [sp]
0x41,0x10,0x60,0xb8 == ldclrl w0, w1, [x2]
0xe3,0x13,0x62,0xb8 == ldclrl w2, w3, [sp]
0x41,0x10,0xe0,0xb8 == ldclral w0, w1, [x2]
0xe3,0x13,0xe2,0xb8 == ldclral w2, w3, [sp]
0x41,0x10,0x20,0x38 == ldclrb w0, w1, [x2]
0xe3,0x13,0x22,0x38 == ldclrb w2, w3, [sp]
0x41,0x10,0x20,0x78 == ldclrh w0, w1, [x2]
0xe3,0x13,0x22,0x78 == ldclrh w2, w3, [sp]
0x41,0x10,0xa0,0x38 == ldclrab w0, w1, [x2]
0xe3,0x13,0xa2,0x38 == ldclrab w2, w3, [sp]
0x41,0x10,0x60,0x38 == ldclrlb w0, w1, [x2]
0xe3,0x13,0x62,0x38 == ldclrlb w2, w3, [sp]
0x41,0x10,0xe0,0x38 == ldclralb w0, w1, [x2]
0xe3,0x13,0xe2,0x38 == ldclralb w2, w3, [sp]
0x41,0x10,0xa0,0x78 == ldclrah w0, w1, [x2]
0xe3,0x13,0xa2,0x78 == ldclrah w2, w3, [sp]
0x41,0x10,0x60,0x78 == ldclrlh w0, w1, [x2]
0xe3,0x13,0x62,0x78 == ldclrlh w2, w3, [sp]
0x41,0x10,0xe0,0x78 == ldclralh w0, w1, [x2]
0xe3,0x13,0xe2,0x78 == ldclralh w2, w3, [sp]
0x41,0x10,0x20,0xf8 == ldclr x0, x1, [x2]
0xe3,0x13,0x22,0xf8 == ldclr x2, x3, [sp]
0x41,0x10,0xa0,0xf8 == ldclra x0, x1, [x2]
0xe3,0x13,0xa2,0xf8 == ldclra x2, x3, [sp]
0x41,0x10,0x60,0xf8 == ldclrl x0, x1, [x2]
0xe3,0x13,0x62,0xf8 == ldclrl x2, x3, [sp]
0x41,0x10,0xe0,0xf8 == ldclral x0, x1, [x2]
0xe3,0x13,0xe2,0xf8 == ldclral x2, x3, [sp]
0x41,0x20,0x20,0xb8 == ldeor w0, w1, [x2]
0xe3,0x23,0x22,0xb8 == ldeor w2, w3, [sp]
0x41,0x20,0xa0,0xb8 == ldeora w0, w1, [x2]
0xe3,0x23,0xa2,0xb8 == ldeora w2, w3, [sp]
0x41,0x20,0x60,0xb8 == ldeorl w0, w1, [x2]
0xe3,0x23,0x62,0xb8 == ldeorl w2, w3, [sp]
0x41,0x20,0xe0,0xb8 == ldeoral w0, w1, [x2]
0xe3,0x23,0xe2,0xb8 == ldeoral w2, w3, [sp]
0x41,0x20,0x20,0x38 == ldeorb w0, w1, [x2]
0xe3,0x23,0x22,0x38 == ldeorb w2, w3, [sp]
0x41,0x20,0x20,0x78 == ldeorh w0, w1, [x2]
0xe3,0x23,0x22,0x78 == ldeorh w2, w3, [sp]
0x41,0x20,0xa0,0x38 == ldeorab w0, w1, [x2]
0xe3,0x23,0xa2,0x38 == ldeorab w2, w3, [sp]
0x41,0x20,0x60,0x38 == ldeorlb w0, w1, [x2]
0xe3,0x23,0x62,0x38 == ldeorlb w2, w3, [sp]
0x41,0x20,0xe0,0x38 == ldeoralb w0, w1, [x2]
0xe3,0x23,0xe2,0x38 == ldeoralb w2, w3, [sp]
0x41,0x20,0xa0,0x78 == ldeorah w0, w1, [x2]
0xe3,0x23,0xa2,0x78 == ldeorah w2, w3, [sp]
0x41,0x20,0x60,0x78 == ldeorlh w0, w1, [x2]
0xe3,0x23,0x62,0x78 == ldeorlh w2, w3, [sp]
0x41,0x20,0xe0,0x78 == ldeoralh w0, w1, [x2]
0xe3,0x23,0xe2,0x78 == ldeoralh w2, w3, [sp]
0x41,0x20,0x20,0xf8 == ldeor x0, x1, [x2]
0xe3,0x23,0x22,0xf8 == ldeor x2, x3, [sp]
0x41,0x20,0xa0,0xf8 == ldeora x0, x1, [x2]
0xe3,0x23,0xa2,0xf8 == ldeora x2, x3, [sp]
0x41,0x20,0x60,0xf8 == ldeorl x0, x1, [x2]
0xe3,0x23,0x62,0xf8 == ldeorl x2, x3, [sp]
0x41,0x20,0xe0,0xf8 == ldeoral x0, x1, [x2]
0xe3,0x23,0xe2,0xf8 == ldeoral x2, x3, [sp]
0x41,0x30,0x20,0xb8 == ldset w0, w1, [x2]
0xe3,0x33,0x22,0xb8 == ldset w2, w3, [sp]
0x41,0x30,0xa0,0xb8 == ldseta w0, w1, [x2]
0xe3,0x33,0xa2,0xb8 == ldseta w2, w3, [sp]
0x41,0x30,0x60,0xb8 == ldsetl w0, w1, [x2]
0xe3,0x33,0x62,0xb8 == ldsetl w2, w3, [sp]
0x41,0x30,0xe0,0xb8 == ldsetal w0, w1, [x2]
0xe3,0x33,0xe2,0xb8 == ldsetal w2, w3, [sp]
0x41,0x30,0x20,0x38 == ldsetb w0, w1, [x2]
0xe3,0x33,0x22,0x38 == ldsetb w2, w3, [sp]
0x41,0x30,0x20,0x78 == ldseth w0, w1, [x2]
0xe3,0x33,0x22,0x78 == ldseth w2, w3, [sp]
0x41,0x30,0xa0,0x38 == ldsetab w0, w1, [x2]
0xe3,0x33,0xa2,0x38 == ldsetab w2, w3, [sp]
0x41,0x30,0x60,0x38 == ldsetlb w0, w1, [x2]
0xe3,0x33,0x62,0x38 == ldsetlb w2, w3, [sp]
0x41,0x30,0xe0,0x38 == ldsetalb w0, w1, [x2]
0xe3,0x33,0xe2,0x38 == ldsetalb w2, w3, [sp]
0x41,0x30,0xa0,0x78 == ldsetah w0, w1, [x2]
0xe3,0x33,0xa2,0x78 == ldsetah w2, w3, [sp]
0x41,0x30,0x60,0x78 == ldsetlh w0, w1, [x2]
0xe3,0x33,0x62,0x78 == ldsetlh w2, w3, [sp]
0x41,0x30,0xe0,0x78 == ldsetalh w0, w1, [x2]
0xe3,0x33,0xe2,0x78 == ldsetalh w2, w3, [sp]
0x41,0x30,0x20,0xf8 == ldset x0, x1, [x2]
0xe3,0x33,0x22,0xf8 == ldset x2, x3, [sp]
0x41,0x30,0xa0,0xf8 == ldseta x0, x1, [x2]
0xe3,0x33,0xa2,0xf8 == ldseta x2, x3, [sp]
0x41,0x30,0x60,0xf8 == ldsetl x0, x1, [x2]
0xe3,0x33,0x62,0xf8 == ldsetl x2, x3, [sp]
0x41,0x30,0xe0,0xf8 == ldsetal x0, x1, [x2]
0xe3,0x33,0xe2,0xf8 == ldsetal x2, x3, [sp]
0x41,0x40,0x20,0xb8 == ldsmax w0, w1, [x2]
0xe3,0x43,0x22,0xb8 == ldsmax w2, w3, [sp]
0x41,0x40,0xa0,0xb8 == ldsmaxa w0, w1, [x2]
0xe3,0x43,0xa2,0xb8 == ldsmaxa w2, w3, [sp]
0x41,0x40,0x60,0xb8 == ldsmaxl w0, w1, [x2]
0xe3,0x43,0x62,0xb8 == ldsmaxl w2, w3, [sp]
0x41,0x40,0xe0,0xb8 == ldsmaxal w0, w1, [x2]
0xe3,0x43,0xe2,0xb8 == ldsmaxal w2, w3, [sp]
0x41,0x40,0x20,0x38 == ldsmaxb w0, w1, [x2]
0xe3,0x43,0x22,0x38 == ldsmaxb w2, w3, [sp]
0x41,0x40,0x20,0x78 == ldsmaxh w0, w1, [x2]
0xe3,0x43,0x22,0x78 == ldsmaxh w2, w3, [sp]
0x41,0x40,0xa0,0x38 == ldsmaxab w0, w1, [x2]
0xe3,0x43,0xa2,0x38 == ldsmaxab w2, w3, [sp]
0x41,0x40,0x60,0x38 == ldsmaxlb w0, w1, [x2]
0xe3,0x43,0x62,0x38 == ldsmaxlb w2, w3, [sp]
0x41,0x40,0xe0,0x38 == ldsmaxalb w0, w1, [x2]
0xe3,0x43,0xe2,0x38 == ldsmaxalb w2, w3, [sp]
0x41,0x40,0xa0,0x78 == ldsmaxah w0, w1, [x2]
0xe3,0x43,0xa2,0x78 == ldsmaxah w2, w3, [sp]
0x41,0x40,0x60,0x78 == ldsmaxlh w0, w1, [x2]
0xe3,0x43,0x62,0x78 == ldsmaxlh w2, w3, [sp]
0x41,0x40,0xe0,0x78 == ldsmaxalh w0, w1, [x2]
0xe3,0x43,0xe2,0x78 == ldsmaxalh w2, w3, [sp]
0x41,0x40,0x20,0xf8 == ldsmax x0, x1, [x2]
0xe3,0x43,0x22,0xf8 == ldsmax x2, x3, [sp]
0x41,0x40,0xa0,0xf8 == ldsmaxa x0, x1, [x2]
0xe3,0x43,0xa2,0xf8 == ldsmaxa x2, x3, [sp]
0x41,0x40,0x60,0xf8 == ldsmaxl x0, x1, [x2]
0xe3,0x43,0x62,0xf8 == ldsmaxl x2, x3, [sp]
0x41,0x40,0xe0,0xf8 == ldsmaxal x0, x1, [x2]
0xe3,0x43,0xe2,0xf8 == ldsmaxal x2, x3, [sp]
0x41,0x50,0x20,0xb8 == ldsmin w0, w1, [x2]
0xe3,0x53,0x22,0xb8 == ldsmin w2, w3, [sp]
0x41,0x50,0xa0,0xb8 == ldsmina w0, w1, [x2]
0xe3,0x53,0xa2,0xb8 == ldsmina w2, w3, [sp]
0x41,0x50,0x60,0xb8 == ldsminl w0, w1, [x2]
0xe3,0x53,0x62,0xb8 == ldsminl w2, w3, [sp]
0x41,0x50,0xe0,0xb8 == ldsminal w0, w1, [x2]
0xe3,0x53,0xe2,0xb8 == ldsminal w2, w3, [sp]
0x41,0x50,0x20,0x38 == ldsminb w0, w1, [x2]
0xe3,0x53,0x22,0x38 == ldsminb w2, w3, [sp]
0x41,0x50,0x20,0x78 == ldsminh w0, w1, [x2]
0xe3,0x53,0x22,0x78 == ldsminh w2, w3, [sp]
0x41,0x50,0xa0,0x38 == ldsminab w0, w1, [x2]
0xe3,0x53,0xa2,0x38 == ldsminab w2, w3, [sp]
0x41,0x50,0x60,0x38 == ldsminlb w0, w1, [x2]
0xe3,0x53,0x62,0x38 == ldsminlb w2, w3, [sp]
0x41,0x50,0xe0,0x38 == ldsminalb w0, w1, [x2]
0xe3,0x53,0xe2,0x38 == ldsminalb w2, w3, [sp]
0x41,0x50,0xa0,0x78 == ldsminah w0, w1, [x2]
0xe3,0x53,0xa2,0x78 == ldsminah w2, w3, [sp]
0x41,0x50,0x60,0x78 == ldsminlh w0, w1, [x2]
0xe3,0x53,0x62,0x78 == ldsminlh w2, w3, [sp]
0x41,0x50,0xe0,0x78 == ldsminalh w0, w1, [x2]
0xe3,0x53,0xe2,0x78 == ldsminalh w2, w3, [sp]
0x41,0x50,0x20,0xf8 == ldsmin x0, x1, [x2]
0xe3,0x53,0x22,0xf8 == ldsmin x2, x3, [sp]
0x41,0x50,0xa0,0xf8 == ldsmina x0, x1, [x2]
0xe3,0x53,0xa2,0xf8 == ldsmina x2, x3, [sp]
0x41,0x50,0x60,0xf8 == ldsminl x0, x1, [x2]
0xe3,0x53,0x62,0xf8 == ldsminl x2, x3, [sp]
0x41,0x50,0xe0,0xf8 == ldsminal x0, x1, [x2]
0xe3,0x53,0xe2,0xf8 == ldsminal x2, x3, [sp]
0x41,0x60,0x20,0xb8 == ldumax w0, w1, [x2]
0xe3,0x63,0x22,0xb8 == ldumax w2, w3, [sp]
0x41,0x60,0xa0,0xb8 == ldumaxa w0, w1, [x2]
0xe3,0x63,0xa2,0xb8 == ldumaxa w2, w3, [sp]
0x41,0x60,0x60,0xb8 == ldumaxl w0, w1, [x2]
0xe3,0x63,0x62,0xb8 == ldumaxl w2, w3, [sp]
0x41,0x60,0xe0,0xb8 == ldumaxal w0, w1, [x2]
0xe3,0x63,0xe2,0xb8 == ldumaxal w2, w3, [sp]
0x41,0x60,0x20,0x38 == ldumaxb w0, w1, [x2]
0xe3,0x63,0x22,0x38 == ldumaxb w2, w3, [sp]
0x41,0x60,0x20,0x78 == ldumaxh w0, w1, [x2]
0xe3,0x63,0x22,0x78 == ldumaxh w2, w3, [sp]
0x41,0x60,0xa0,0x38 == ldumaxab w0, w1, [x2]
0xe3,0x63,0xa2,0x38 == ldumaxab w2, w3, [sp]
0x41,0x60,0x60,0x38 == ldumaxlb w0, w1, [x2]
0xe3,0x63,0x62,0x38 == ldumaxlb w2, w3, [sp]
0x41,0x60,0xe0,0x38 == ldumaxalb w0, w1, [x2]
0xe3,0x63,0xe2,0x38 == ldumaxalb w2, w3, [sp]
0x41,0x60,0xa0,0x78 == ldumaxah w0, w1, [x2]
0xe3,0x63,0xa2,0x78 == ldumaxah w2, w3, [sp]
0x41,0x60,0x60,0x78 == ldumaxlh w0, w1, [x2]
0xe3,0x63,0x62,0x78 == ldumaxlh w2, w3, [sp]
0x41,0x60,0xe0,0x78 == ldumaxalh w0, w1, [x2]
0xe3,0x63,0xe2,0x78 == ldumaxalh w2, w3, [sp]
0x41,0x60,0x20,0xf8 == ldumax x0, x1, [x2]
0xe3,0x63,0x22,0xf8 == ldumax x2, x3, [sp]
0x41,0x60,0xa0,0xf8 == ldumaxa x0, x1, [x2]
0xe3,0x63,0xa2,0xf8 == ldumaxa x2, x3, [sp]
0x41,0x60,0x60,0xf8 == ldumaxl x0, x1, [x2]
0xe3,0x63,0x62,0xf8 == ldumaxl x2, x3, [sp]
0x41,0x60,0xe0,0xf8 == ldumaxal x0, x1, [x2]
0xe3,0x63,0xe2,0xf8 == ldumaxal x2, x3, [sp]
0x41,0x70,0x20,0xb8 == ldumin w0, w1, [x2]
0xe3,0x73,0x22,0xb8 == ldumin w2, w3, [sp]
0x41,0x70,0xa0,0xb8 == ldumina w0, w1, [x2]
0xe3,0x73,0xa2,0xb8 == ldumina w2, w3, [sp]
0x41,0x70,0x60,0xb8 == lduminl w0, w1, [x2]
0xe3,0x73,0x62,0xb8 == lduminl w2, w3, [sp]
0x41,0x70,0xe0,0xb8 == lduminal w0, w1, [x2]
0xe3,0x73,0xe2,0xb8 == lduminal w2, w3, [sp]
0x41,0x70,0x20,0x38 == lduminb w0, w1, [x2]
0xe3,0x73,0x22,0x38 == lduminb w2, w3, [sp]
0x41,0x70,0x20,0x78 == lduminh w0, w1, [x2]
0xe3,0x73,0x22,0x78 == lduminh w2, w3, [sp]
0x41,0x70,0xa0,0x38 == lduminab w0, w1, [x2]
0xe3,0x73,0xa2,0x38 == lduminab w2, w3, [sp]
0x41,0x70,0x60,0x38 == lduminlb w0, w1, [x2]
0xe3,0x73,0x62,0x38 == lduminlb w2, w3, [sp]
0x41,0x70,0xe0,0x38 == lduminalb w0, w1, [x2]
0xe3,0x73,0xe2,0x38 == lduminalb w2, w3, [sp]
0x41,0x70,0xa0,0x78 == lduminah w0, w1, [x2]
0xe3,0x73,0xa2,0x78 == lduminah w2, w3, [sp]
0x41,0x70,0x60,0x78 == lduminlh w0, w1, [x2]
0xe3,0x73,0x62,0x78 == lduminlh w2, w3, [sp]
0x41,0x70,0xe0,0x78 == lduminalh w0, w1, [x2]
0xe3,0x73,0xe2,0x78 == lduminalh w2, w3, [sp]
0x41,0x70,0x20,0xf8 == ldumin x0, x1, [x2]
0xe3,0x73,0x22,0xf8 == ldumin x2, x3, [sp]
0x41,0x70,0xa0,0xf8 == ldumina x0, x1, [x2]
0xe3,0x73,0xa2,0xf8 == ldumina x2, x3, [sp]
0x41,0x70,0x60,0xf8 == lduminl x0, x1, [x2]
0xe3,0x73,0x62,0xf8 == lduminl x2, x3, [sp]
0x41,0x70,0xe0,0xf8 == lduminal x0, x1, [x2]
0xe3,0x73,0xe2,0xf8 == lduminal x2, x3, [sp]
0x5f,0x00,0x20,0xb8 == stadd w0, [x2]
0xff,0x03,0x22,0xb8 == stadd w2, [sp]
0x5f,0x00,0x60,0xb8 == staddl w0, [x2]
0xff,0x03,0x62,0xb8 == staddl w2, [sp]
0x5f,0x00,0x20,0x38 == staddb w0, [x2]
0xff,0x03,0x22,0x38 == staddb w2, [sp]
0x5f,0x00,0x20,0x78 == staddh w0, [x2]
0xff,0x03,0x22,0x78 == staddh w2, [sp]
0x5f,0x00,0x60,0x38 == staddlb w0, [x2]
0xff,0x03,0x62,0x38 == staddlb w2, [sp]
0x5f,0x00,0x60,0x78 == staddlh w0, [x2]
0xff,0x03,0x62,0x78 == staddlh w2, [sp]
0x5f,0x00,0x20,0xf8 == stadd x0, [x2]
0xff,0x03,0x22,0xf8 == stadd x2, [sp]
0x5f,0x00,0x60,0xf8 == staddl x0, [x2]
0xff,0x03,0x62,0xf8 == staddl x2, [sp]
0x5f,0x10,0x20,0xb8 == stclr w0, [x2]
0xff,0x13,0x22,0xb8 == stclr w2, [sp]
0x5f,0x10,0x60,0xb8 == stclrl w0, [x2]
0xff,0x13,0x62,0xb8 == stclrl w2, [sp]
0x5f,0x10,0x20,0x38 == stclrb w0, [x2]
0xff,0x13,0x22,0x38 == stclrb w2, [sp]
0x5f,0x10,0x20,0x78 == stclrh w0, [x2]
0xff,0x13,0x22,0x78 == stclrh w2, [sp]
0x5f,0x10,0x60,0x38 == stclrlb w0, [x2]
0xff,0x13,0x62,0x38 == stclrlb w2, [sp]
0x5f,0x10,0x60,0x78 == stclrlh w0, [x2]
0xff,0x13,0x62,0x78 == stclrlh w2, [sp]
0x5f,0x10,0x20,0xf8 == stclr x0, [x2]
0xff,0x13,0x22,0xf8 == stclr x2, [sp]
0x5f,0x10,0x60,0xf8 == stclrl x0, [x2]
0xff,0x13,0x62,0xf8 == stclrl x2, [sp]
0x5f,0x20,0x20,0xb8 == steor w0, [x2]
0xff,0x23,0x22,0xb8 == steor w2, [sp]
0x5f,0x20,0x60,0xb8 == steorl w0, [x2]
0xff,0x23,0x62,0xb8 == steorl w2, [sp]
0x5f,0x20,0x20,0x38 == steorb w0, [x2]
0xff,0x23,0x22,0x38 == steorb w2, [sp]
0x5f,0x20,0x20,0x78 == steorh w0, [x2]
0xff,0x23,0x22,0x78 == steorh w2, [sp]
0x5f,0x20,0x60,0x38 == steorlb w0, [x2]
0xff,0x23,0x62,0x38 == steorlb w2, [sp]
0x5f,0x20,0x60,0x78 == steorlh w0, [x2]
0xff,0x23,0x62,0x78 == steorlh w2, [sp]
0x5f,0x20,0x20,0xf8 == steor x0, [x2]
0xff,0x23,0x22,0xf8 == steor x2, [sp]
0x5f,0x20,0x60,0xf8 == steorl x0, [x2]
0xff,0x23,0x62,0xf8 == steorl x2, [sp]
0x5f,0x30,0x20,0xb8 == stset w0, [x2]
0xff,0x33,0x22,0xb8 == stset w2, [sp]
0x5f,0x30,0x60,0xb8 == stsetl w0, [x2]
0xff,0x33,0x62,0xb8 == stsetl w2, [sp]
0x5f,0x30,0x20,0x38 == stsetb w0, [x2]
0xff,0x33,0x22,0x38 == stsetb w2, [sp]
0x5f,0x30,0x20,0x78 == stseth w0, [x2]
0xff,0x33,0x22,0x78 == stseth w2, [sp]
0x5f,0x30,0x60,0x38 == stsetlb w0, [x2]
0xff,0x33,0x62,0x38 == stsetlb w2, [sp]
0x5f,0x30,0x60,0x78 == stsetlh w0, [x2]
0xff,0x33,0x62,0x78 == stsetlh w2, [sp]
0x5f,0x30,0x20,0xf8 == stset x0, [x2]
0xff,0x33,0x22,0xf8 == stset x2, [sp]
0x5f,0x30,0x60,0xf8 == stsetl x0, [x2]
0xff,0x33,0x62,0xf8 == stsetl x2, [sp]
0x5f,0x40,0x20,0xb8 == stsmax w0, [x2]
0xff,0x43,0x22,0xb8 == stsmax w2, [sp]
0x5f,0x40,0x60,0xb8 == stsmaxl w0, [x2]
0xff,0x43,0x62,0xb8 == stsmaxl w2, [sp]
0x5f,0x40,0x20,0x38 == stsmaxb w0, [x2]
0xff,0x43,0x22,0x38 == stsmaxb w2, [sp]
0x5f,0x40,0x20,0x78 == stsmaxh w0, [x2]
0xff,0x43,0x22,0x78 == stsmaxh w2, [sp]
0x5f,0x40,0x60,0x38 == stsmaxlb w0, [x2]
0xff,0x43,0x62,0x38 == stsmaxlb w2, [sp]
0x5f,0x40,0x60,0x78 == stsmaxlh w0, [x2]
0xff,0x43,0x62,0x78 == stsmaxlh w2, [sp]
0x5f,0x40,0x20,0xf8 == stsmax x0, [x2]
0xff,0x43,0x22,0xf8 == stsmax x2, [sp]
0x5f,0x40,0x60,0xf8 == stsmaxl x0, [x2]
0xff,0x43,0x62,0xf8 == stsmaxl x2, [sp]
0x5f,0x50,0x20,0xb8 == stsmin w0, [x2]
0xff,0x53,0x22,0xb8 == stsmin w2, [sp]
0x5f,0x50,0x60,0xb8 == stsminl w0, [x2]
0xff,0x53,0x62,0xb8 == stsminl w2, [sp]
0x5f,0x50,0x20,0x38 == stsminb w0, [x2]
0xff,0x53,0x22,0x38 == stsminb w2, [sp]
0x5f,0x50,0x20,0x78 == stsminh w0, [x2]
0xff,0x53,0x22,0x78 == stsminh w2, [sp]
0x5f,0x50,0x60,0x38 == stsminlb w0, [x2]
0xff,0x53,0x62,0x38 == stsminlb w2, [sp]
0x5f,0x50,0x60,0x78 == stsminlh w0, [x2]
0xff,0x53,0x62,0x78 == stsminlh w2, [sp]
0x5f,0x50,0x20,0xf8 == stsmin x0, [x2]
0xff,0x53,0x22,0xf8 == stsmin x2, [sp]
0x5f,0x50,0x60,0xf8 == stsminl x0, [x2]
0xff,0x53,0x62,0xf8 == stsminl x2, [sp]
0x5f,0x60,0x20,0xb8 == stumax w0, [x2]
0xff,0x63,0x22,0xb8 == stumax w2, [sp]
0x5f,0x60,0x60,0xb8 == stumaxl w0, [x2]
0xff,0x63,0x62,0xb8 == stumaxl w2, [sp]
0x5f,0x60,0x20,0x38 == stumaxb w0, [x2]
0xff,0x63,0x22,0x38 == stumaxb w2, [sp]
0x5f,0x60,0x20,0x78 == stumaxh w0, [x2]
0xff,0x63,0x22,0x78 == stumaxh w2, [sp]
0x5f,0x60,0x60,0x38 == stumaxlb w0, [x2]
0xff,0x63,0x62,0x38 == stumaxlb w2, [sp]
0x5f,0x60,0x60,0x78 == stumaxlh w0, [x2]
0xff,0x63,0x62,0x78 == stumaxlh w2, [sp]
0x5f,0x60,0x20,0xf8 == stumax x0, [x2]
0xff,0x63,0x22,0xf8 == stumax x2, [sp]
0x5f,0x60,0x60,0xf8 == stumaxl x0, [x2]
0xff,0x63,0x62,0xf8 == stumaxl x2, [sp]
0x5f,0x70,0x20,0xb8 == stumin w0, [x2]
0xff,0x73,0x22,0xb8 == stumin w2, [sp]
0x5f,0x70,0x60,0xb8 == stuminl w0, [x2]
0xff,0x73,0x62,0xb8 == stuminl w2, [sp]
0x5f,0x70,0x20,0x38 == stuminb w0, [x2]
0xff,0x73,0x22,0x38 == stuminb w2, [sp]
0x5f,0x70,0x20,0x78 == stuminh w0, [x2]
0xff,0x73,0x22,0x78 == stuminh w2, [sp]

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