From 6751c53aec5d4c3bc30adf4595b502aa7eaf8ad2 Mon Sep 17 00:00:00 2001 From: stevielavern Date: Tue, 22 Feb 2022 15:22:41 +0100 Subject: [PATCH 1/2] Fix ldapr detailed information #1839 --- arch/AArch64/AArch64MappingInsnOp.inc | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/AArch64/AArch64MappingInsnOp.inc b/arch/AArch64/AArch64MappingInsnOp.inc index 49449a406..3983a36ca 100644 --- a/arch/AArch64/AArch64MappingInsnOp.inc +++ b/arch/AArch64/AArch64MappingInsnOp.inc @@ -9925,67 +9925,67 @@ { /* AArch64_LDAPRB, AArch64_INS_LDAPRB: ldaprb */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAPRH, AArch64_INS_LDAPRH: ldaprh */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAPRW, AArch64_INS_LDAPR: ldapr */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAPRX, AArch64_INS_LDAPR: ldapr */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAPURBi, AArch64_INS_LDAPURB: ldapurb */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAPURHi, AArch64_INS_LDAPURH: ldapurh */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAPURSBWi, AArch64_INS_LDAPURSB: ldapursb */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAPURSBXi, AArch64_INS_LDAPURSB: ldapursb */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAPURSHWi, AArch64_INS_LDAPURSH: ldapursh */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAPURSHXi, AArch64_INS_LDAPURSH: ldapursh */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAPURSWi, AArch64_INS_LDAPURSW: ldapursw */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAPURXi, AArch64_INS_LDAPUR: ldapur */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAPURi, AArch64_INS_LDAPUR: ldapur */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDARB, AArch64_INS_LDARB: ldarb */ From e1c9ecbb1f9858f97a9836a87ee144ff47f6bf4c Mon Sep 17 00:00:00 2001 From: stevielavern Date: Tue, 22 Feb 2022 15:35:24 +0100 Subject: [PATCH 2/2] Add unit test for #1839 --- suite/regress/test_arm64_ldr_registers.py | 57 +++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 suite/regress/test_arm64_ldr_registers.py diff --git a/suite/regress/test_arm64_ldr_registers.py b/suite/regress/test_arm64_ldr_registers.py new file mode 100644 index 000000000..d366c4037 --- /dev/null +++ b/suite/regress/test_arm64_ldr_registers.py @@ -0,0 +1,57 @@ +import unittest +from capstone import * +from capstone.arm64 import * + +class SubRegTest(unittest.TestCase): + + PATTERNS = [ + ("41 00 40 F9", "ldr x1, [x2]"), + ("41 00 40 39", "ldrb w1, [x2]"), + ("41 00 C0 39", "ldrsb w1, [x2]"), + ("41 00 40 79", "ldrh w1, [x2]"), + ("88 c2 bf f8", "ldapr x8, [x20]"), + ] + + def setUp(self): + self.insts = [] + self.cs = Cs(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN) + self.cs.detail = True + + for pattern, asm in self.PATTERNS: + l = list(self.cs.disasm(bytes.fromhex(pattern), 0)) + self.assertTrue(len(l) == 1) + + _, expected_reg_written, expected_reg_read = asm.split() + # strip comma and [] + expected_reg_written = expected_reg_written[:-1] + expected_reg_read = expected_reg_read[1:-1] + expected_regs = [expected_reg_read, expected_reg_written] + + self.insts.append((l[0], asm, expected_regs)) + + + def test_registers(self): + """Check that the `regs_access` API provides correct data""" + + for inst, asm, expected_regs in self.insts: + + # Check that the instruction writes the first register operand and reads the second + for i, decoded_regs in enumerate(map(lambda l: list(map(self.cs.reg_name, l)), inst.regs_access())): + self.assertEqual(len(decoded_regs), 1, "%s has %d %s registers instead of 1" % (asm, len(decoded_regs), ["read", "written"][i])) + decoded_reg = decoded_regs[0] + self.assertEqual(expected_regs[i], decoded_reg, "%s test"%i) + + def test_operands(self): + """Check that the `operands` API provides correct data""" + for inst, asm, expected_regs in self.insts: + ops = inst.operands + self.assertEqual(len(ops), 2) + + self.assertEqual(ops[0].type, CS_OP_REG, "%s has operand 0 with invalid type" % asm) + self.assertEqual(ops[0].access, CS_AC_WRITE, "%s has operand 0 with invalid access" % asm) + self.assertEqual(ops[1].type, CS_OP_MEM, "%s has operand 0 with invalid type" % asm) + self.assertEqual(self.cs.reg_name(ops[1].mem.base), expected_regs[0], "%s has operand 1 with invalid reg" % asm) + self.assertEqual(ops[1].access, CS_AC_READ, "%s has operand 1 with invalid access" % asm) + +if __name__ == '__main__': + unittest.main()