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fix: TriCore architecture disassembly codes

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- Rename `ISLR_post_increment` to `ISLR_pos` for clarity
- Fix register decoding for TriCore architecture in `TriCoreDisassembler.c`
- Add new file `LoadStore.s.cs` to `suite/MC/TriCore`
This commit is contained in:
billow 2023-03-28 05:50:30 +08:00
parent 2299215eaf
commit a78a46a397
5 changed files with 558 additions and 554 deletions
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6
arch/TriCore/TriCoreDisassembler.c
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@ -455,11 +455,11 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
} }
if (desc->NumOperands > 2) { if (desc->NumOperands > 2) {
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], Decoder); status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder);
if (status != MCDisassembler_Success) if (status != MCDisassembler_Success)
return status; return status;
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder); status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder);
if (status != MCDisassembler_Success) if (status != MCDisassembler_Success)
return status; return status;
@ -866,7 +866,7 @@ static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn, uint64_t A
return status; return status;
// Decode s1. // Decode s1.
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder); status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
if (status != MCDisassembler_Success) if (status != MCDisassembler_Success)
return status; return status;

1009
arch/TriCore/TriCoreGenAsmWriter.inc
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File diff suppressed because it is too large Load Diff

82
arch/TriCore/TriCoreGenInstrInfo.inc
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@ -1205,14 +1205,12 @@ static const MCOperandInfo OperandInfo107[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0
static const MCOperandInfo OperandInfo108[] = { { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo108[] = { { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo109[] = { { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo109[] = { { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo110[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; static const MCOperandInfo OperandInfo110[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo111[] = { { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo111[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo112[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo112[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo113[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; static const MCOperandInfo OperandInfo113[] = { { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo114[] = { { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_DataRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo114[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo115[] = { { TriCore_AddrRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo115[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo116[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo116[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo117[] = { { TriCore_AddrExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_ExtRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo118[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCInstrDesc TriCoreInsts[] = { static const MCInstrDesc TriCoreInsts[] = {
{ 1, OperandInfo2 }, { 1, OperandInfo2 },
@ -2189,53 +2187,53 @@ static const MCInstrDesc TriCoreInsts[] = {
{ 2, OperandInfo52 }, { 2, OperandInfo52 },
{ 2, OperandInfo51 }, { 2, OperandInfo51 },
{ 2, OperandInfo89 }, { 2, OperandInfo89 },
{ 3, OperandInfo90 },
{ 3, OperandInfo111 }, { 3, OperandInfo111 },
{ 3, OperandInfo112 },
{ 3, OperandInfo90 }, { 3, OperandInfo90 },
{ 3, OperandInfo90 }, { 3, OperandInfo90 },
{ 2, OperandInfo113 }, { 2, OperandInfo112 },
{ 3, OperandInfo114 }, { 3, OperandInfo113 },
{ 2, OperandInfo51 }, { 2, OperandInfo51 },
{ 2, OperandInfo52 }, { 2, OperandInfo52 },
{ 2, OperandInfo52 }, { 2, OperandInfo52 },
{ 2, OperandInfo51 }, { 2, OperandInfo51 },
{ 2, OperandInfo94 }, { 2, OperandInfo94 },
{ 3, OperandInfo87 }, { 3, OperandInfo62 },
{ 3, OperandInfo95 }, { 3, OperandInfo95 },
{ 3, OperandInfo62 }, { 3, OperandInfo62 },
{ 3, OperandInfo62 }, { 3, OperandInfo62 },
{ 2, OperandInfo96 }, { 2, OperandInfo96 },
{ 2, OperandInfo85 }, { 2, OperandInfo85 },
{ 3, OperandInfo115 }, { 3, OperandInfo97 },
{ 3, OperandInfo114 },
{ 3, OperandInfo97 },
{ 3, OperandInfo97 },
{ 2, OperandInfo115 },
{ 2, OperandInfo89 },
{ 3, OperandInfo90 },
{ 3, OperandInfo111 },
{ 3, OperandInfo90 },
{ 3, OperandInfo90 },
{ 2, OperandInfo112 },
{ 3, OperandInfo113 },
{ 2, OperandInfo51 },
{ 2, OperandInfo52 },
{ 2, OperandInfo52 },
{ 2, OperandInfo51 },
{ 2, OperandInfo89 },
{ 3, OperandInfo90 },
{ 3, OperandInfo111 },
{ 3, OperandInfo90 },
{ 3, OperandInfo90 },
{ 2, OperandInfo112 },
{ 3, OperandInfo116 }, { 3, OperandInfo116 },
{ 3, OperandInfo97 },
{ 3, OperandInfo97 },
{ 2, OperandInfo117 },
{ 2, OperandInfo89 }, { 2, OperandInfo89 },
{ 3, OperandInfo90 },
{ 3, OperandInfo111 }, { 3, OperandInfo111 },
{ 3, OperandInfo112 },
{ 3, OperandInfo90 }, { 3, OperandInfo90 },
{ 3, OperandInfo90 }, { 3, OperandInfo90 },
{ 2, OperandInfo113 }, { 2, OperandInfo112 },
{ 3, OperandInfo114 }, { 3, OperandInfo113 },
{ 2, OperandInfo51 },
{ 2, OperandInfo52 },
{ 2, OperandInfo52 },
{ 2, OperandInfo51 },
{ 2, OperandInfo89 },
{ 3, OperandInfo111 },
{ 3, OperandInfo112 },
{ 3, OperandInfo90 },
{ 3, OperandInfo90 },
{ 2, OperandInfo113 },
{ 3, OperandInfo118 },
{ 2, OperandInfo89 },
{ 3, OperandInfo111 },
{ 3, OperandInfo112 },
{ 3, OperandInfo90 },
{ 3, OperandInfo90 },
{ 2, OperandInfo113 },
{ 3, OperandInfo114 },
{ 2, OperandInfo53 }, { 2, OperandInfo53 },
{ 2, OperandInfo105 }, { 2, OperandInfo105 },
{ 2, OperandInfo105 }, { 2, OperandInfo105 },
@ -2257,17 +2255,17 @@ static const MCInstrDesc TriCoreInsts[] = {
{ 2, OperandInfo47 }, { 2, OperandInfo47 },
{ 2, OperandInfo47 }, { 2, OperandInfo47 },
{ 0, 0 }, { 0, 0 },
{ 3, OperandInfo115 }, { 3, OperandInfo97 },
{ 3, OperandInfo116 }, { 3, OperandInfo114 },
{ 3, OperandInfo97 }, { 3, OperandInfo97 },
{ 3, OperandInfo97 }, { 3, OperandInfo97 },
{ 2, OperandInfo117 }, { 2, OperandInfo115 },
{ 2, OperandInfo89 }, { 2, OperandInfo89 },
{ 3, OperandInfo90 },
{ 3, OperandInfo111 }, { 3, OperandInfo111 },
{ 3, OperandInfo112 },
{ 3, OperandInfo90 }, { 3, OperandInfo90 },
{ 3, OperandInfo90 }, { 3, OperandInfo90 },
{ 2, OperandInfo113 }, { 2, OperandInfo112 },
{ 1, OperandInfo2 }, { 1, OperandInfo2 },
{ 0, 0 }, { 0, 0 },
{ 0, 0 }, { 0, 0 },

10
arch/TriCore/TriCoreInstrInfo.td
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@ -1135,9 +1135,9 @@ class IBOL_AbOR<bits<8> op1, string asmstr, RegisterClass dc>
class ISLR<bits<8> op1, string asmstr, RegisterClass dc> class ISLR<bits<8> op1, string asmstr, RegisterClass dc>
: SLR<op1, (outs dc:$d), (ins AddrRegs:$s2), : SLR<op1, (outs dc:$d), (ins AddrRegs:$s2),
asmstr # " $d, $s2", []>; asmstr # " $d, $s2", []>;
class ISLR_post_increment<bits<8> op1, string asmstr, RegisterClass dc> class ISLR_pos<bits<8> op1, string asmstr, RegisterClass dc>
: SLR<op1, (outs dc:$d), (ins AddrRegs:$s2), : SLR<op1, (outs dc:$d), (ins AddrRegs:$s2),
asmstr # " [+$d]$s2", []>; asmstr # " $d, [$s2+]", []>;
class ISLRO<bits<8> op1, string asmstr, RegisterClass dc> class ISLRO<bits<8> op1, string asmstr, RegisterClass dc>
: SLRO<op1, (outs dc:$d), (ins u4imm:$off4), : SLRO<op1, (outs dc:$d), (ins u4imm:$off4),
@ -1186,7 +1186,7 @@ multiclass mIABS_BO<bits<8> abs1, bits<2> abs2, ///_abs
multiclass mISLR_SLRO_SRO<bits<8> slr, bits<8> slrp, bits<8> slro, bits<8> sro, multiclass mISLR_SLRO_SRO<bits<8> slr, bits<8> slrp, bits<8> slro, bits<8> sro,
string asmstr, RegisterClass c>{ string asmstr, RegisterClass c>{
def _slr : ISLR<slr, asmstr, c>; def _slr : ISLR<slr, asmstr, c>;
def _slr_post : ISLR_post_increment<slrp, asmstr, c>; def _slr_post : ISLR_pos<slrp, asmstr, c>;
def _slro : ISLRO<slro, asmstr, c>; def _slro : ISLRO<slro, asmstr, c>;
def _sro : ISRO<sro, asmstr, c>; def _sro : ISRO<sro, asmstr, c>;
} }
@ -1611,7 +1611,7 @@ def SHUFFLE_rc : IRC_2<0x8F, 0x07, "shuffle">;
// A[b], off10, A[a] (BO)(Base + Short Offset Addressing Mode) // A[b], off10, A[a] (BO)(Base + Short Offset Addressing Mode)
class IBO_bso_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc> class IBO_bso_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc>
: BO<op1, op2, (outs AddrRegs:$d), (ins rc:$s1, s10imm:$off10), : BO<op1, op2, (outs rc:$d), (ins AddrRegs:$s1, s10imm:$off10),
asmstr # " [$s1]$off10, $d", []>; asmstr # " [$s1]$off10, $d", []>;
// P[b], A[a] (BO)(Bit-reverse Addressing Mode) // P[b], A[a] (BO)(Bit-reverse Addressing Mode)
class IBO_r_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc> class IBO_r_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc>
@ -1666,7 +1666,7 @@ multiclass mISRO_SSR_SSRO_st<bits<8> sro, bits<8> ssr, bits<8> ssrpos, bits<8> s
def _ssr : SSR<ssr, (outs AddrRegs:$d), (ins rc:$s1), def _ssr : SSR<ssr, (outs AddrRegs:$d), (ins rc:$s1),
asmstr # " $d, $s1", []>; asmstr # " $d, $s1", []>;
def _ssr_pos : SSR<ssrpos, (outs AddrRegs:$d), (ins rc:$s1), def _ssr_pos : SSR<ssrpos, (outs AddrRegs:$d), (ins rc:$s1),
asmstr # " [+$d]$s1", []>; asmstr # " [$d+], $s1", []>;
def _ssro : SSRO<ssro, (outs), (ins rc:$s1, s4imm:$off4), def _ssro : SSRO<ssro, (outs), (ins rc:$s1, s4imm:$off4),
asmstr # " %a15, $off4, $s1", []>; asmstr # " %a15, $off4, $s1", []>;
} }

5
suite/MC/TriCore/LoadStore.s.cs Normal file
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@ -0,0 +1,5 @@
# CS_ARCH_TRICORE, CS_MODE_TRICORE, None
0x64,0xc1 = st.w [%a12+], %d1
0x44,0x21 = ld.w %d1, [%a2+]
0x89,0xa2,0x40,0x09 = st.d [%sp]0, %e2
0x09,0xa0,0x40,0x09 = ld.d %e0, [%sp]0