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Constify backends (#1549)
* Constify registerinfo.py output Remove two conditionals separating identical bits of code. Add "const" markup to MCRegisterDesc and MCRegisterClass. Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify instrinfo-arch.py output In this case, do not actively strip const. Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the AArch64 backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the EVM backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify M680X backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify M68K backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the Mips backend The Mips backend has not been regenerated from LLVM recently, and there are more fixups required than I'd like. Just apply the fixes to the tables by hand for now. Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the Sparc backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the TMS320C64x backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the X86 backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the XCore backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify systemregister.py output Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the ARM backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the PowerPC backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the MOS65XX backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the SystemZ backend The mapping of system register to indexes is easy to generate read-only. Since we know the indexes are between 0 and 31, use uint8_t instead of unsigned. Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the WASM backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify cs.c Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the BPF backend Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
Nguyen Anh Quynh
parent
9fe1087ca3
commit
aaffb38c44
@ -4539,422 +4539,422 @@ enum {
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#define nullptr 0
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#define nullptr 0
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static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
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static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
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static MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
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static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
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static MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
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static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
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static MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
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static MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
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static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
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static MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
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static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
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static MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
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static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
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static MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
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static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
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static MCOperandInfo OperandInfo31[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo31[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo32[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo32[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo33[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo33[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo34[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo34[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo35[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo35[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo36[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo36[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo37[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo37[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo38[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo38[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo39[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo39[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo40[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo40[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo41[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo41[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo42[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo42[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo43[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo43[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo44[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo44[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo45[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo45[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo46[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo46[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo47[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo47[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo48[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo48[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo49[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo49[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo50[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo50[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo51[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo51[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo52[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo52[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo53[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo53[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo54[] = { { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo54[] = { { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo55[] = { { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo55[] = { { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo56[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo56[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo57[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo57[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo58[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo58[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo59[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo59[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo60[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo60[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo61[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo61[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo62[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo62[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo63[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo63[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo64[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo64[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo65[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
|
static const MCOperandInfo OperandInfo65[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
|
||||||
static MCOperandInfo OperandInfo66[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo66[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo67[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo67[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo68[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo68[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo69[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo69[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo70[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo70[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo71[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo71[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo72[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo72[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo73[] = { { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo73[] = { { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo74[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo74[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo75[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo75[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo76[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo76[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo77[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo77[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo78[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo78[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo79[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo79[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo80[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
static const MCOperandInfo OperandInfo80[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo81[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo81[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo82[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo82[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo83[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo83[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo84[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo84[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo85[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo85[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo86[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo86[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo87[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo87[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo88[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo88[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo89[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
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static const MCOperandInfo OperandInfo89[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
|
||||||
static MCOperandInfo OperandInfo90[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
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static const MCOperandInfo OperandInfo90[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo91[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo91[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo92[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo92[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo93[] = { { AArch64_WSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_WSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_WSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo93[] = { { AArch64_WSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_WSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_WSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo94[] = { { AArch64_XSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_XSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_XSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo94[] = { { AArch64_XSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_XSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_XSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo95[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
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static const MCOperandInfo OperandInfo95[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo96[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
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static const MCOperandInfo OperandInfo96[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo97[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo97[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo98[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo98[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo99[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo99[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo100[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo100[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo101[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo101[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo102[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo102[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo103[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo103[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo104[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo104[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo105[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo105[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo106[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo106[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo107[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo107[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo108[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo108[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo109[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo109[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo110[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo110[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo111[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo111[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo112[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo112[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo113[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo113[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo114[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo114[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo115[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo115[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo116[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo116[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo117[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo117[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo118[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo118[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo119[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo119[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo120[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo120[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo121[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo121[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo122[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo122[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo123[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo123[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo124[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo124[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo125[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo125[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo126[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo126[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo127[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo127[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo128[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo128[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo129[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo129[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo130[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo130[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo131[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo131[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo132[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo132[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo133[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
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static const MCOperandInfo OperandInfo133[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
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||||||
static MCOperandInfo OperandInfo134[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo134[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo135[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo135[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo136[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo136[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo137[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo137[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo138[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo138[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo139[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo139[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo140[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo140[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo141[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo141[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo142[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo142[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo143[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo143[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo144[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo144[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo145[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo145[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo146[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo146[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo147[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo147[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo148[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo148[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo149[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo149[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo150[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo150[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo151[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo151[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo152[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo152[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo153[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo153[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo154[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo154[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo155[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo155[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo156[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo156[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo157[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo157[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo158[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo158[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo159[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo159[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo160[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPR_4bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo160[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPR_4bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo161[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo161[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo162[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo162[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo163[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo163[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo164[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo164[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo165[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo165[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo166[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo166[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo167[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo167[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo168[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo168[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo169[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo169[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo170[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo170[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo171[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo171[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo172[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo172[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo173[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo173[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo174[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo174[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo175[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo175[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo176[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo176[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo177[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo177[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo178[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo178[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo179[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo179[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo180[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo180[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo181[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo181[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo182[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo182[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo183[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo183[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo184[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo184[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo185[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo185[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo186[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo186[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo187[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo187[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo188[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo188[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo189[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo189[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo190[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo190[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo191[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo191[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo192[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo192[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo193[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo193[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo194[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo194[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo195[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo195[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo196[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPR_4bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo196[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPR_4bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo197[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo197[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo198[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo198[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo199[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo199[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo200[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo200[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo201[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo201[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo202[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo202[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo203[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo203[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo204[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo204[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo205[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo205[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo206[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo206[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo207[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo207[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo208[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo208[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo209[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo209[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo210[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo210[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo211[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo211[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo212[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo212[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo213[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo213[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo214[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo214[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo215[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo215[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo216[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo216[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo217[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo217[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo218[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPR_4bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo218[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPR_4bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo219[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo219[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo220[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo220[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo221[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo221[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo222[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo222[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo223[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo223[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo224[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo224[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo225[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo225[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo226[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo226[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo227[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo227[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo228[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo228[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo229[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo229[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo230[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo230[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo231[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo231[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo232[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo232[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo233[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo233[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo234[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo234[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo235[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo235[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo236[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo236[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo237[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo237[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo238[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo238[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo239[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo239[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo240[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo240[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo241[] = { { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo241[] = { { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo242[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo242[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo243[] = { { AArch64_DDDDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo243[] = { { AArch64_DDDDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo244[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_DDDDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo244[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_DDDDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo245[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo245[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo246[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo246[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo247[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo247[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo248[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo248[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo249[] = { { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo249[] = { { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo250[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo250[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo251[] = { { AArch64_DDDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo251[] = { { AArch64_DDDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo252[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_DDDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo252[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_DDDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo253[] = { { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo253[] = { { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo254[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo254[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo255[] = { { AArch64_DDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo255[] = { { AArch64_DDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo256[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_DDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo256[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_DDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo257[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo257[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo258[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo258[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo259[] = { { AArch64_ZPR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo259[] = { { AArch64_ZPR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo260[] = { { AArch64_ZPR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo260[] = { { AArch64_ZPR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo261[] = { { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo261[] = { { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo262[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo262[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo263[] = { { AArch64_ZPR3RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo263[] = { { AArch64_ZPR3RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo264[] = { { AArch64_ZPR3RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo264[] = { { AArch64_ZPR3RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo265[] = { { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo265[] = { { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo266[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo266[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo267[] = { { AArch64_ZPR4RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo267[] = { { AArch64_ZPR4RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo268[] = { { AArch64_ZPR4RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo268[] = { { AArch64_ZPR4RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo269[] = { { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo269[] = { { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo270[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo270[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo271[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo271[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo272[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo272[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo273[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo273[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo274[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo274[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo275[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo275[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo276[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo276[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo277[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo277[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo278[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo278[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo279[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo279[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo280[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo280[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo281[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo281[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo282[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo282[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo283[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo283[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo284[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo284[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo285[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo285[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo286[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo286[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo287[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo287[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo288[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo288[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo289[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo289[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo290[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo290[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo291[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo291[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo292[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo292[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo293[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo293[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo294[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo294[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo295[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
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static const MCOperandInfo OperandInfo295[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
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||||||
static MCOperandInfo OperandInfo296[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo296[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo297[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo297[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo298[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo298[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo299[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo299[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo300[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo300[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo301[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo301[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo302[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo302[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo303[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo303[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo304[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
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static const MCOperandInfo OperandInfo304[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo305[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo305[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo306[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo306[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo307[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo307[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo308[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo308[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo309[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo309[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo310[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo310[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo311[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
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static const MCOperandInfo OperandInfo311[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo312[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo312[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo313[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo313[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo314[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo314[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo315[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo315[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo316[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo316[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo317[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo317[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo318[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo318[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo319[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo319[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo320[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo320[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo321[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo321[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo322[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo322[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo323[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo323[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo324[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo324[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo325[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo325[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo326[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo326[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo327[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo327[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo328[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo328[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo329[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo329[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo330[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
|
static const MCOperandInfo OperandInfo330[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
|
||||||
static MCOperandInfo OperandInfo331[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo331[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo332[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo332[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo333[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo333[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo334[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo334[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo335[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo335[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo336[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo336[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo337[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo337[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo338[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo338[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo339[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo339[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo340[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo340[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo341[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo341[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo342[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo342[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo343[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo343[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo344[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo344[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo345[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo345[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo346[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo346[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo347[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo347[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo348[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo348[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo349[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo349[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo350[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo350[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo351[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo351[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo352[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo352[] = { { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo353[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo353[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo354[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo354[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo355[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
|
static const MCOperandInfo OperandInfo355[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
|
||||||
static MCOperandInfo OperandInfo356[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo356[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo357[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo357[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo358[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo358[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo359[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo359[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo360[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo360[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo361[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo361[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo362[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo362[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo363[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo363[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo364[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo364[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo365[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo365[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo366[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo366[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo367[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo367[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo368[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo368[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo369[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo369[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo370[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo370[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo371[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo371[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo372[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo372[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo373[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo373[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo374[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo374[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo375[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo375[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo376[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo376[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo377[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo377[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo378[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo378[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo379[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo379[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo380[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo380[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo381[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo381[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo382[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo382[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo383[] = { { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo383[] = { { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo384[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo384[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo385[] = { { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo385[] = { { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo386[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo386[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo387[] = { { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo387[] = { { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo388[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo388[] = { { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo389[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo389[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo390[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo390[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo391[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo391[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo392[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo392[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo393[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo393[] = { { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo394[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo394[] = { { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo395[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo395[] = { { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo396[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo396[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo397[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo397[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo398[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo398[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo399[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo399[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo400[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo400[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo401[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo401[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo402[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo402[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo403[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo403[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo404[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo404[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo405[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
static const MCOperandInfo OperandInfo405[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo406[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
static const MCOperandInfo OperandInfo406[] = { { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo407[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo407[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo408[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo408[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo409[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo409[] = { { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo410[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo410[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo411[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo411[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo412[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo412[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo413[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo413[] = { { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo414[] = { { AArch64_tcGPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo414[] = { { AArch64_tcGPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo415[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
|
static const MCOperandInfo OperandInfo415[] = { { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
|
||||||
static MCOperandInfo OperandInfo416[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo416[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo417[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo417[] = { { AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
|
|
||||||
static const MCInstrDesc AArch64Insts[] = {
|
static const MCInstrDesc AArch64Insts[] = {
|
||||||
{ 1, OperandInfo2 },
|
{ 1, OperandInfo2 },
|
||||||
|
|||||||
@ -1032,7 +1032,7 @@ static const uint16_t AArch64SubRegIdxLists[] = {
|
|||||||
/* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0,
|
/* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MCRegisterDesc AArch64RegDesc[] = {
|
static const MCRegisterDesc AArch64RegDesc[] = {
|
||||||
{ 3, 0, 0, 0, 0, 0 },
|
{ 3, 0, 0, 0, 0, 0 },
|
||||||
{ 2489, 8, 8, 4, 20465, 0 },
|
{ 2489, 8, 8, 4, 20465, 0 },
|
||||||
{ 2482, 878, 405, 5, 20465, 27 },
|
{ 2482, 878, 405, 5, 20465, 27 },
|
||||||
@ -2498,7 +2498,7 @@ static MCRegisterDesc AArch64RegDesc[] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
static MCRegisterClass AArch64MCRegisterClasses[] = {
|
static const MCRegisterClass AArch64MCRegisterClasses[] = {
|
||||||
{ FPR8, FPR8Bits, sizeof(FPR8Bits) },
|
{ FPR8, FPR8Bits, sizeof(FPR8Bits) },
|
||||||
{ FPR16, FPR16Bits, sizeof(FPR16Bits) },
|
{ FPR16, FPR16Bits, sizeof(FPR16Bits) },
|
||||||
{ PPR, PPRBits, sizeof(PPRBits) },
|
{ PPR, PPRBits, sizeof(PPRBits) },
|
||||||
|
|||||||
@ -54,7 +54,7 @@ static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
|
|||||||
static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int index)
|
static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int index)
|
||||||
{
|
{
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
uint8_t *arr = AArch64_get_op_access(h, id);
|
const uint8_t *arr = AArch64_get_op_access(h, id);
|
||||||
|
|
||||||
if (arr[index] == CS_AC_IGNORE)
|
if (arr[index] == CS_AC_IGNORE)
|
||||||
return 0;
|
return 0;
|
||||||
|
|||||||
@ -15,7 +15,7 @@
|
|||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
// NOTE: this reg_name_maps[] reflects the order of registers in arm64_reg
|
// NOTE: this reg_name_maps[] reflects the order of registers in arm64_reg
|
||||||
static const char *reg_name_maps[] = {
|
static const char * const reg_name_maps[] = {
|
||||||
NULL, /* ARM64_REG_INVALID */
|
NULL, /* ARM64_REG_INVALID */
|
||||||
|
|
||||||
"ffr",
|
"ffr",
|
||||||
@ -389,7 +389,7 @@ void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static const char *insn_name_maps[] = {
|
static const char * const insn_name_maps[] = {
|
||||||
NULL, // ARM64_INS_INVALID
|
NULL, // ARM64_INS_INVALID
|
||||||
#include "AArch64MappingInsnName.inc"
|
#include "AArch64MappingInsnName.inc"
|
||||||
"sbfiz",
|
"sbfiz",
|
||||||
@ -523,7 +523,7 @@ typedef struct insn_op {
|
|||||||
uint8_t access[5];
|
uint8_t access[5];
|
||||||
} insn_op;
|
} insn_op;
|
||||||
|
|
||||||
static insn_op insn_ops[] = {
|
static const insn_op insn_ops[] = {
|
||||||
{
|
{
|
||||||
/* NULL item */
|
/* NULL item */
|
||||||
0, { 0 }
|
0, { 0 }
|
||||||
@ -533,7 +533,7 @@ static insn_op insn_ops[] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
// given internal insn id, return operand access info
|
// given internal insn id, return operand access info
|
||||||
uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id)
|
const uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id)
|
||||||
{
|
{
|
||||||
int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
|
int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
|
||||||
if (i != 0) {
|
if (i != 0) {
|
||||||
|
|||||||
@ -32,7 +32,7 @@ void arm64_op_addFP(MCInst *MI, float fp);
|
|||||||
|
|
||||||
void arm64_op_addImm(MCInst *MI, int64_t imm);
|
void arm64_op_addImm(MCInst *MI, int64_t imm);
|
||||||
|
|
||||||
uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id);
|
const uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id);
|
||||||
|
|
||||||
void AArch64_reg_access(const cs_insn *insn,
|
void AArch64_reg_access(const cs_insn *insn,
|
||||||
cs_regs regs_read, uint8_t *regs_read_count,
|
cs_regs regs_read, uint8_t *regs_read_count,
|
||||||
|
|||||||
@ -443,30 +443,30 @@ enum TraceSyncBOpt {
|
|||||||
CSYNC = 0
|
CSYNC = 0
|
||||||
};
|
};
|
||||||
|
|
||||||
MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding);
|
const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding);
|
||||||
MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);
|
const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);
|
||||||
|
|
||||||
// returns APSR with _<bits> qualifier.
|
// returns APSR with _<bits> qualifier.
|
||||||
// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
|
// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
|
||||||
static inline MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
|
static inline const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
|
||||||
{
|
{
|
||||||
return lookupMClassSysRegByM2M3Encoding8((1<<9) | (SYSm & 0xFF));
|
return lookupMClassSysRegByM2M3Encoding8((1<<9) | (SYSm & 0xFF));
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
|
static inline const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
|
||||||
{
|
{
|
||||||
return lookupMClassSysRegByM2M3Encoding8((1<<8) | (SYSm & 0xFF));
|
return lookupMClassSysRegByM2M3Encoding8((1<<8) | (SYSm & 0xFF));
|
||||||
}
|
}
|
||||||
|
|
||||||
// returns true if TestFeatures are all present in FeaturesRequired
|
// returns true if TestFeatures are all present in FeaturesRequired
|
||||||
static inline bool MClassSysReg_isInRequiredFeatures(MClassSysReg *TheReg, int TestFeatures)
|
static inline bool MClassSysReg_isInRequiredFeatures(const MClassSysReg *TheReg, int TestFeatures)
|
||||||
{
|
{
|
||||||
return (TheReg->FeaturesRequired[0] == TestFeatures || TheReg->FeaturesRequired[1] == TestFeatures);
|
return (TheReg->FeaturesRequired[0] == TestFeatures || TheReg->FeaturesRequired[1] == TestFeatures);
|
||||||
}
|
}
|
||||||
|
|
||||||
// lookup system register using 12-bit SYSm value.
|
// lookup system register using 12-bit SYSm value.
|
||||||
// Note: the search is uniqued using M1 mask
|
// Note: the search is uniqued using M1 mask
|
||||||
static inline MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
|
static inline const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
|
||||||
{
|
{
|
||||||
return lookupMClassSysRegByM1Encoding12(SYSm);
|
return lookupMClassSysRegByM1Encoding12(SYSm);
|
||||||
}
|
}
|
||||||
|
|||||||
@ -2990,424 +2990,424 @@ enum {
|
|||||||
|
|
||||||
#define nullptr 0
|
#define nullptr 0
|
||||||
|
|
||||||
static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
||||||
static MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
||||||
static MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
||||||
static MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
||||||
static MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
|
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
|
||||||
static MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
|
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
|
||||||
static MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
|
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
|
||||||
static MCOperandInfo OperandInfo31[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo31[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo32[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo32[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo34[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo34[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo35[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo35[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo38[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo38[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo42[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo42[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo43[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo43[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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||||||
static MCOperandInfo OperandInfo44[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo44[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo45[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo45[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo46[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo46[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo47[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo47[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo48[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo48[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo49[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo49[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo50[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo50[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo52[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo52[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo53[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo53[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo54[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo54[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo55[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo55[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo56[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo56[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo57[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo57[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo58[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo58[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo59[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo59[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo63[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo63[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo64[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo64[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo69[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo69[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo70[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo70[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo71[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo71[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo73[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo73[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo74[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo74[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo75[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo75[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo76[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo76[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo77[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo77[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo78[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo78[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo79[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo79[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo80[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo80[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo81[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo81[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo82[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo82[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo83[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo83[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo84[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo84[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo85[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo85[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo86[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo86[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo87[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo87[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo88[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo88[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo89[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo89[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo90[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo90[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo91[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo91[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo92[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo92[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo93[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo93[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo94[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo94[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo95[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo95[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo96[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo96[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo97[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo97[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo98[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo98[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo99[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo99[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo100[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo100[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo101[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo101[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo102[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo102[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo103[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo103[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo104[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo104[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo105[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo105[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo106[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo106[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo107[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo107[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo108[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo108[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo109[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo109[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo110[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo110[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo111[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo111[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo112[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo112[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo113[] = { { ARM_tGPRwithpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo113[] = { { ARM_tGPRwithpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo116[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo116[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo118[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo118[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo119[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo119[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo120[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo120[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo121[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo121[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo122[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo122[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo123[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo123[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo124[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo124[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo125[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo125[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo126[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo126[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo127[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo127[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo128[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo128[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo130[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo130[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo131[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo131[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo132[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo132[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo133[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo133[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo134[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
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static const MCOperandInfo OperandInfo134[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
|
||||||
static MCOperandInfo OperandInfo135[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo135[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo136[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo136[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo137[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo137[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo138[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo138[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo139[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo139[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo140[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo140[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo141[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo141[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo142[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo142[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo143[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo143[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo144[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo144[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo145[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo145[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo146[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo146[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo147[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo147[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo148[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo148[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo149[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo149[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo150[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo150[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo151[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo151[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo152[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo152[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo153[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo153[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo154[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo154[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo155[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo155[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo156[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo156[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo157[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo157[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo158[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo158[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo159[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo159[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo160[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo160[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo161[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo161[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo162[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo162[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo163[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo163[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo164[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo164[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo165[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo165[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo166[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo166[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo167[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo167[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo168[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo168[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo169[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
|
static const MCOperandInfo OperandInfo169[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
|
||||||
static MCOperandInfo OperandInfo170[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
|
static const MCOperandInfo OperandInfo170[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
|
||||||
static MCOperandInfo OperandInfo171[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo171[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo172[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo172[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo173[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo173[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo174[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo174[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo175[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo175[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo176[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo176[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo177[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo177[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo178[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo178[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo179[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo179[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo180[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo180[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo181[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo181[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo182[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo182[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo183[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo183[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo184[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo184[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo185[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo185[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo186[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo186[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo187[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo187[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo188[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo188[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo189[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo189[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo190[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo190[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo191[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo191[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo192[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo192[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo193[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo193[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo194[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo194[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo196[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo196[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo198[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo198[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo199[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo199[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo200[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo200[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo201[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo201[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo202[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo202[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo203[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo203[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo204[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo204[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo205[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo205[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo206[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo206[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo207[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo207[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo208[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo208[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo209[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo209[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo210[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo210[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo211[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo211[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo212[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo212[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo214[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo214[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo215[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo215[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo216[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo216[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo217[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo217[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo218[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo218[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo220[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo220[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo221[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo221[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo222[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo222[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo223[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo223[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo225[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo225[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo226[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo226[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo227[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo227[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo228[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo228[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo229[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo229[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo230[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo230[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo231[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo231[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo232[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo232[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo233[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo233[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo234[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo234[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo235[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo235[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo237[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo237[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo238[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo238[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo239[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo239[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo240[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo240[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo241[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo241[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo242[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo242[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo243[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo243[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo244[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo244[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo245[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo245[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo246[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo246[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo247[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo247[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo248[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo248[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo249[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo249[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo250[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo250[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo251[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo251[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo252[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo252[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo253[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo253[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo254[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo254[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo255[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo255[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo256[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo256[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo257[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo257[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo258[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo258[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo259[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo259[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo260[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo260[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo261[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo261[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo263[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo263[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo264[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo264[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo267[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo267[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo268[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo268[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo269[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo269[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo270[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo270[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo271[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo271[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo272[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo272[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo273[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo273[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo274[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo274[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo275[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo275[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo276[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo276[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo277[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo277[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo278[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo278[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo279[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo279[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo280[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo280[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo281[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo281[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo282[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo282[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo283[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo283[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo284[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo284[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo285[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo285[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo286[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo286[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo287[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo287[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo288[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo288[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo289[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo289[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo290[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo290[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo291[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo291[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo292[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo292[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo293[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo293[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo294[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo294[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo295[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo295[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo296[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo296[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo297[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo297[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo298[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo298[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo299[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo299[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo300[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo300[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo301[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo301[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo302[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo302[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo303[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo303[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo304[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo304[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo305[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo305[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo306[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo306[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo307[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo307[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo308[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo308[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo309[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo309[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo310[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo310[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo311[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo311[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo312[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo312[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo313[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo313[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo314[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo314[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo316[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo316[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo317[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo317[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo318[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo318[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo319[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo319[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo320[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo320[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo321[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo321[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo322[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo322[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo323[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo323[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo324[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo324[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo325[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo325[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo326[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo326[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo327[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo327[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo328[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo328[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo329[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo329[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo330[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo330[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo331[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo331[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo332[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo332[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo333[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo333[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo334[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo334[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo335[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo335[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo336[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo336[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo337[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo337[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo338[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo338[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo339[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo339[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo340[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo340[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo341[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo341[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo342[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo342[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo343[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo343[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo344[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo344[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo345[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo345[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo346[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo346[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo347[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo347[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo348[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo348[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo349[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo349[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo350[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo350[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo351[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo351[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo352[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo352[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo353[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo353[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo354[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo354[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo355[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo355[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo356[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo356[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo357[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo357[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo358[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo358[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo359[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo359[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo360[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo360[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo361[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo361[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo362[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo362[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo363[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo363[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo364[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo364[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo365[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo365[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo366[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo366[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo367[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo367[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo368[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo368[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo369[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo369[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo370[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo370[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo371[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo371[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo372[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo372[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo373[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo373[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo374[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo374[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo375[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo375[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo376[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo376[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo377[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo377[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo378[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo378[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo379[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo379[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo380[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo380[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo381[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo381[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo382[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo382[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo383[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo383[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo384[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo384[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo385[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo385[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo386[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo386[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo387[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo387[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo388[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo388[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo389[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo389[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo390[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo390[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo391[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo391[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo392[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo392[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo393[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo393[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo394[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo394[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo395[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo395[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo396[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo396[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo397[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo397[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo398[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo398[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo399[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo399[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo400[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo400[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo401[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo401[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo402[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo402[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo403[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo403[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo404[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo404[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo405[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo405[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo406[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
static const MCOperandInfo OperandInfo406[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo407[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo407[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo408[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo408[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo409[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
static const MCOperandInfo OperandInfo409[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||||
static MCOperandInfo OperandInfo410[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo410[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo411[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo411[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo412[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo412[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo413[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo413[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo414[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo414[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo415[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo415[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo416[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo416[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo417[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo417[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo418[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo418[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo419[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo419[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
|
|
||||||
static const MCInstrDesc ARMInsts[] = {
|
static const MCInstrDesc ARMInsts[] = {
|
||||||
{ 1, OperandInfo2 },
|
{ 1, OperandInfo2 },
|
||||||
|
|||||||
@ -875,7 +875,7 @@ static const uint16_t ARMSubRegIdxLists[] = {
|
|||||||
/* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
|
/* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MCRegisterDesc ARMRegDesc[] = {
|
static const MCRegisterDesc ARMRegDesc[] = {
|
||||||
{ 12, 0, 0, 0, 0, 0 },
|
{ 12, 0, 0, 0, 0, 0 },
|
||||||
{ 1235, 16, 16, 2, 66945, 0 },
|
{ 1235, 16, 16, 2, 66945, 0 },
|
||||||
{ 1268, 16, 16, 2, 66945, 0 },
|
{ 1268, 16, 16, 2, 66945, 0 },
|
||||||
@ -1993,7 +1993,7 @@ static MCRegisterDesc ARMRegDesc[] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
static MCRegisterClass ARMMCRegisterClasses[] = {
|
static const MCRegisterClass ARMMCRegisterClasses[] = {
|
||||||
{ HPR, HPRBits, sizeof(HPRBits) },
|
{ HPR, HPRBits, sizeof(HPRBits) },
|
||||||
{ SPR, SPRBits, sizeof(SPRBits) },
|
{ SPR, SPRBits, sizeof(SPRBits) },
|
||||||
{ GPR, GPRBits, sizeof(GPRBits) },
|
{ GPR, GPRBits, sizeof(GPRBits) },
|
||||||
|
|||||||
@ -46,7 +46,7 @@ enum BankedRegValues {
|
|||||||
spsr_und = 32,
|
spsr_und = 32,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MClassSysReg MClassSysRegsList[] = {
|
static const MClassSysReg MClassSysRegsList[] = {
|
||||||
{ "apsr_g", ARM_SYSREG_APSR_G, 0x400, 0x0, 0x400, {ARM_FeatureDSP} }, // 0
|
{ "apsr_g", ARM_SYSREG_APSR_G, 0x400, 0x0, 0x400, {ARM_FeatureDSP} }, // 0
|
||||||
{ "apsr_nzcvqg", ARM_SYSREG_APSR_NZCVQG, 0xC00, 0x300, 0xC00, {ARM_FeatureDSP} }, // 1
|
{ "apsr_nzcvqg", ARM_SYSREG_APSR_NZCVQG, 0xC00, 0x300, 0xC00, {ARM_FeatureDSP} }, // 1
|
||||||
{ "iapsr_g", ARM_SYSREG_IAPSR_G, 0x401, 0x1, 0x401, {ARM_FeatureDSP} }, // 2
|
{ "iapsr_g", ARM_SYSREG_IAPSR_G, 0x401, 0x1, 0x401, {ARM_FeatureDSP} }, // 2
|
||||||
@ -86,7 +86,7 @@ static MClassSysReg MClassSysRegsList[] = {
|
|||||||
{ "sp_ns", ARM_SYSREG_SP_NS, 0x898, 0x198, 0x898, {ARM_Feature8MSecExt} }, // 36
|
{ "sp_ns", ARM_SYSREG_SP_NS, 0x898, 0x198, 0x898, {ARM_Feature8MSecExt} }, // 36
|
||||||
};
|
};
|
||||||
|
|
||||||
static BankedReg BankedRegsList[] = {
|
static const BankedReg BankedRegsList[] = {
|
||||||
{ "r8_usr", ARM_SYSREG_R8_USR, 0x0 }, // 0
|
{ "r8_usr", ARM_SYSREG_R8_USR, 0x0 }, // 0
|
||||||
{ "r9_usr", ARM_SYSREG_R9_USR, 0x1 }, // 1
|
{ "r9_usr", ARM_SYSREG_R9_USR, 0x1 }, // 1
|
||||||
{ "r10_usr", ARM_SYSREG_R10_USR, 0x2 }, // 2
|
{ "r10_usr", ARM_SYSREG_R10_USR, 0x2 }, // 2
|
||||||
@ -122,7 +122,7 @@ static BankedReg BankedRegsList[] = {
|
|||||||
{ "spsr_hyp", ARM_SYSREG_SPSR_HYP, 0x3E }, // 32
|
{ "spsr_hyp", ARM_SYSREG_SPSR_HYP, 0x3E }, // 32
|
||||||
};
|
};
|
||||||
|
|
||||||
MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)
|
const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)
|
||||||
{
|
{
|
||||||
unsigned int i;
|
unsigned int i;
|
||||||
static const struct IndexType Index[] = {
|
static const struct IndexType Index[] = {
|
||||||
@ -172,7 +172,7 @@ MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)
|
|||||||
return &MClassSysRegsList[Index[i].index];
|
return &MClassSysRegsList[Index[i].index];
|
||||||
}
|
}
|
||||||
|
|
||||||
MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)
|
const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)
|
||||||
{
|
{
|
||||||
unsigned int i;
|
unsigned int i;
|
||||||
static const struct IndexType Index[] = {
|
static const struct IndexType Index[] = {
|
||||||
@ -222,7 +222,7 @@ MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)
|
|||||||
return &MClassSysRegsList[Index[i].index];
|
return &MClassSysRegsList[Index[i].index];
|
||||||
}
|
}
|
||||||
|
|
||||||
BankedReg *lookupBankedRegByEncoding(uint8_t encoding)
|
const BankedReg *lookupBankedRegByEncoding(uint8_t encoding)
|
||||||
{
|
{
|
||||||
unsigned int i;
|
unsigned int i;
|
||||||
static const struct IndexType Index[] = {
|
static const struct IndexType Index[] = {
|
||||||
|
|||||||
@ -131,7 +131,7 @@ static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O, bo
|
|||||||
// copy & normalize access info
|
// copy & normalize access info
|
||||||
static uint8_t get_op_access(cs_struct *h, unsigned int id, unsigned int index)
|
static uint8_t get_op_access(cs_struct *h, unsigned int id, unsigned int index)
|
||||||
{
|
{
|
||||||
uint8_t *arr = ARM_get_op_access(h, id);
|
const uint8_t *arr = ARM_get_op_access(h, id);
|
||||||
|
|
||||||
if (!arr || arr[index] == CS_AC_IGNORE)
|
if (!arr || arr[index] == CS_AC_IGNORE)
|
||||||
return 0;
|
return 0;
|
||||||
@ -1734,7 +1734,7 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
|
|||||||
unsigned reg;
|
unsigned reg;
|
||||||
|
|
||||||
if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) {
|
if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) {
|
||||||
MClassSysReg *TheReg;
|
const MClassSysReg *TheReg;
|
||||||
unsigned SYSm = (unsigned)MCOperand_getImm(Op) & 0xFFF; // 12-bit SYMm
|
unsigned SYSm = (unsigned)MCOperand_getImm(Op) & 0xFFF; // 12-bit SYMm
|
||||||
unsigned Opcode = MCInst_getOpcode(MI);
|
unsigned Opcode = MCInst_getOpcode(MI);
|
||||||
|
|
||||||
@ -1827,7 +1827,7 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
|
|||||||
static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
|
static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||||
{
|
{
|
||||||
uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||||
BankedReg *TheReg = lookupBankedRegByEncoding(Banked);
|
const BankedReg *TheReg = lookupBankedRegByEncoding(Banked);
|
||||||
|
|
||||||
SStream_concat0(O, TheReg->Name);
|
SStream_concat0(O, TheReg->Name);
|
||||||
ARM_addSysReg(MI, TheReg->sysreg);
|
ARM_addSysReg(MI, TheReg->sysreg);
|
||||||
|
|||||||
@ -345,7 +345,7 @@ void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static const char *insn_name_maps[] = {
|
static const char * const insn_name_maps[] = {
|
||||||
NULL, // ARM_INS_INVALID
|
NULL, // ARM_INS_INVALID
|
||||||
#include "ARMMappingInsnName.inc"
|
#include "ARMMappingInsnName.inc"
|
||||||
};
|
};
|
||||||
@ -475,7 +475,7 @@ typedef struct insn_op {
|
|||||||
uint8_t access[7];
|
uint8_t access[7];
|
||||||
} insn_op;
|
} insn_op;
|
||||||
|
|
||||||
static insn_op insn_ops[] = {
|
static const insn_op insn_ops[] = {
|
||||||
{
|
{
|
||||||
// NULL item
|
// NULL item
|
||||||
{ 0 }
|
{ 0 }
|
||||||
@ -485,7 +485,7 @@ static insn_op insn_ops[] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
// given internal insn id, return operand access info
|
// given internal insn id, return operand access info
|
||||||
uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id)
|
const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id)
|
||||||
{
|
{
|
||||||
int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
|
int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
|
||||||
if (i != 0) {
|
if (i != 0) {
|
||||||
|
|||||||
@ -23,7 +23,7 @@ bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
|
|||||||
|
|
||||||
bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);
|
bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);
|
||||||
|
|
||||||
uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id);
|
const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id);
|
||||||
|
|
||||||
void ARM_reg_access(const cs_insn *insn,
|
void ARM_reg_access(const cs_insn *insn,
|
||||||
cs_regs regs_read, uint8_t *regs_read_count,
|
cs_regs regs_read, uint8_t *regs_read_count,
|
||||||
@ -35,6 +35,6 @@ typedef struct BankedReg {
|
|||||||
uint16_t Encoding;
|
uint16_t Encoding;
|
||||||
} BankedReg;
|
} BankedReg;
|
||||||
|
|
||||||
BankedReg *lookupBankedRegByEncoding(uint8_t encoding);
|
const BankedReg *lookupBankedRegByEncoding(uint8_t encoding);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@ -137,7 +137,7 @@ const char *BPF_reg_name(csh handle, unsigned int reg)
|
|||||||
if (EBPF_MODE(handle)) {
|
if (EBPF_MODE(handle)) {
|
||||||
if (reg < BPF_REG_R0 || reg > BPF_REG_R10)
|
if (reg < BPF_REG_R0 || reg > BPF_REG_R10)
|
||||||
return NULL;
|
return NULL;
|
||||||
static const char* reg_names[11] = {
|
static const char reg_names[11][4] = {
|
||||||
"r0", "r1", "r2", "r3", "r4",
|
"r0", "r1", "r2", "r3", "r4",
|
||||||
"r5", "r6", "r7", "r8", "r9",
|
"r5", "r6", "r7", "r8", "r9",
|
||||||
"r10"
|
"r10"
|
||||||
|
|||||||
@ -8,7 +8,7 @@
|
|||||||
#include "EVMDisassembler.h"
|
#include "EVMDisassembler.h"
|
||||||
#include "EVMMapping.h"
|
#include "EVMMapping.h"
|
||||||
|
|
||||||
static short opcodes[256] = {
|
static const short opcodes[256] = {
|
||||||
EVM_INS_STOP,
|
EVM_INS_STOP,
|
||||||
EVM_INS_ADD,
|
EVM_INS_ADD,
|
||||||
EVM_INS_MUL,
|
EVM_INS_MUL,
|
||||||
|
|||||||
@ -11,14 +11,14 @@
|
|||||||
#include "EVMMapping.h"
|
#include "EVMMapping.h"
|
||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static cs_evm insns[256] = {
|
static const cs_evm insns[256] = {
|
||||||
#include "EVMMappingInsn.inc"
|
#include "EVMMappingInsn.inc"
|
||||||
};
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// look for @id in @insns, given its size in @max.
|
// look for @id in @insns, given its size in @max.
|
||||||
// return -1 if not found
|
// return -1 if not found
|
||||||
static int evm_insn_find(cs_evm *insns, unsigned int max, unsigned int id)
|
static int evm_insn_find(const cs_evm *insns, unsigned int max, unsigned int id)
|
||||||
{
|
{
|
||||||
if (id >= max)
|
if (id >= max)
|
||||||
return -1;
|
return -1;
|
||||||
@ -44,7 +44,7 @@ void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static name_map insn_name_maps[256] = {
|
static const name_map insn_name_maps[256] = {
|
||||||
{ EVM_INS_STOP, "stop" },
|
{ EVM_INS_STOP, "stop" },
|
||||||
{ EVM_INS_ADD, "add" },
|
{ EVM_INS_ADD, "add" },
|
||||||
{ EVM_INS_MUL, "mul" },
|
{ EVM_INS_MUL, "mul" },
|
||||||
@ -317,7 +317,7 @@ const char *EVM_insn_name(csh handle, unsigned int id)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static name_map group_name_maps[] = {
|
static const name_map group_name_maps[] = {
|
||||||
// generic groups
|
// generic groups
|
||||||
{ EVM_GRP_INVALID, NULL },
|
{ EVM_GRP_INVALID, NULL },
|
||||||
{ EVM_GRP_JUMP, "jump" },
|
{ EVM_GRP_JUMP, "jump" },
|
||||||
|
|||||||
@ -1399,11 +1399,11 @@ static void indexed09_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
m680x_reg g_idx12_to_reg_ids[4] = {
|
static const m680x_reg g_idx12_to_reg_ids[4] = {
|
||||||
M680X_REG_X, M680X_REG_Y, M680X_REG_S, M680X_REG_PC,
|
M680X_REG_X, M680X_REG_Y, M680X_REG_S, M680X_REG_PC,
|
||||||
};
|
};
|
||||||
|
|
||||||
m680x_reg g_or12_to_reg_ids[3] = {
|
static const m680x_reg g_or12_to_reg_ids[3] = {
|
||||||
M680X_REG_A, M680X_REG_B, M680X_REG_D
|
M680X_REG_A, M680X_REG_B, M680X_REG_D
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -2130,7 +2130,7 @@ static const cpu_tables g_cpu_tables[] = {
|
|||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *s_cpu_type[] = {
|
static const char * const s_cpu_type[] = {
|
||||||
"INVALID", "6301", "6309", "6800", "6801", "6805", "6808",
|
"INVALID", "6301", "6309", "6800", "6801", "6805", "6808",
|
||||||
"6809", "6811", "CPU12", "HCS08",
|
"6809", "6811", "CPU12", "HCS08",
|
||||||
};
|
};
|
||||||
|
|||||||
@ -87,7 +87,7 @@ static const char s_instruction_names[][6] = {
|
|||||||
"xgdx", "xgdy",
|
"xgdx", "xgdy",
|
||||||
};
|
};
|
||||||
|
|
||||||
static name_map s_group_names[] = {
|
static const name_map s_group_names[] = {
|
||||||
{ M680X_GRP_INVALID, "<invalid>" },
|
{ M680X_GRP_INVALID, "<invalid>" },
|
||||||
{ M680X_GRP_JUMP, "jump" },
|
{ M680X_GRP_JUMP, "jump" },
|
||||||
{ M680X_GRP_CALL, "call" },
|
{ M680X_GRP_CALL, "call" },
|
||||||
|
|||||||
@ -222,38 +222,38 @@ typedef struct {
|
|||||||
/* ================================= DATA ================================= */
|
/* ================================= DATA ================================= */
|
||||||
/* ======================================================================== */
|
/* ======================================================================== */
|
||||||
|
|
||||||
static instruction_struct g_instruction_table[0x10000];
|
static const instruction_struct g_instruction_table[0x10000];
|
||||||
|
|
||||||
/* used by ops like asr, ror, addq, etc */
|
/* used by ops like asr, ror, addq, etc */
|
||||||
static uint32_t g_3bit_qdata_table[8] = {8, 1, 2, 3, 4, 5, 6, 7};
|
static const uint32_t g_3bit_qdata_table[8] = {8, 1, 2, 3, 4, 5, 6, 7};
|
||||||
|
|
||||||
static uint32_t g_5bit_data_table[32] = {
|
static const uint32_t g_5bit_data_table[32] = {
|
||||||
32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
|
32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
|
||||||
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
|
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
|
||||||
};
|
};
|
||||||
|
|
||||||
static m68k_insn s_branch_lut[] = {
|
static const m68k_insn s_branch_lut[] = {
|
||||||
M68K_INS_INVALID, M68K_INS_INVALID, M68K_INS_BHI, M68K_INS_BLS,
|
M68K_INS_INVALID, M68K_INS_INVALID, M68K_INS_BHI, M68K_INS_BLS,
|
||||||
M68K_INS_BCC, M68K_INS_BCS, M68K_INS_BNE, M68K_INS_BEQ,
|
M68K_INS_BCC, M68K_INS_BCS, M68K_INS_BNE, M68K_INS_BEQ,
|
||||||
M68K_INS_BVC, M68K_INS_BVS, M68K_INS_BPL, M68K_INS_BMI,
|
M68K_INS_BVC, M68K_INS_BVS, M68K_INS_BPL, M68K_INS_BMI,
|
||||||
M68K_INS_BGE, M68K_INS_BLT, M68K_INS_BGT, M68K_INS_BLE,
|
M68K_INS_BGE, M68K_INS_BLT, M68K_INS_BGT, M68K_INS_BLE,
|
||||||
};
|
};
|
||||||
|
|
||||||
static m68k_insn s_dbcc_lut[] = {
|
static const m68k_insn s_dbcc_lut[] = {
|
||||||
M68K_INS_DBT, M68K_INS_DBF, M68K_INS_DBHI, M68K_INS_DBLS,
|
M68K_INS_DBT, M68K_INS_DBF, M68K_INS_DBHI, M68K_INS_DBLS,
|
||||||
M68K_INS_DBCC, M68K_INS_DBCS, M68K_INS_DBNE, M68K_INS_DBEQ,
|
M68K_INS_DBCC, M68K_INS_DBCS, M68K_INS_DBNE, M68K_INS_DBEQ,
|
||||||
M68K_INS_DBVC, M68K_INS_DBVS, M68K_INS_DBPL, M68K_INS_DBMI,
|
M68K_INS_DBVC, M68K_INS_DBVS, M68K_INS_DBPL, M68K_INS_DBMI,
|
||||||
M68K_INS_DBGE, M68K_INS_DBLT, M68K_INS_DBGT, M68K_INS_DBLE,
|
M68K_INS_DBGE, M68K_INS_DBLT, M68K_INS_DBGT, M68K_INS_DBLE,
|
||||||
};
|
};
|
||||||
|
|
||||||
static m68k_insn s_scc_lut[] = {
|
static const m68k_insn s_scc_lut[] = {
|
||||||
M68K_INS_ST, M68K_INS_SF, M68K_INS_SHI, M68K_INS_SLS,
|
M68K_INS_ST, M68K_INS_SF, M68K_INS_SHI, M68K_INS_SLS,
|
||||||
M68K_INS_SCC, M68K_INS_SCS, M68K_INS_SNE, M68K_INS_SEQ,
|
M68K_INS_SCC, M68K_INS_SCS, M68K_INS_SNE, M68K_INS_SEQ,
|
||||||
M68K_INS_SVC, M68K_INS_SVS, M68K_INS_SPL, M68K_INS_SMI,
|
M68K_INS_SVC, M68K_INS_SVS, M68K_INS_SPL, M68K_INS_SMI,
|
||||||
M68K_INS_SGE, M68K_INS_SLT, M68K_INS_SGT, M68K_INS_SLE,
|
M68K_INS_SGE, M68K_INS_SLT, M68K_INS_SGT, M68K_INS_SLE,
|
||||||
};
|
};
|
||||||
|
|
||||||
static m68k_insn s_trap_lut[] = {
|
static const m68k_insn s_trap_lut[] = {
|
||||||
M68K_INS_TRAPT, M68K_INS_TRAPF, M68K_INS_TRAPHI, M68K_INS_TRAPLS,
|
M68K_INS_TRAPT, M68K_INS_TRAPF, M68K_INS_TRAPHI, M68K_INS_TRAPLS,
|
||||||
M68K_INS_TRAPCC, M68K_INS_TRAPCS, M68K_INS_TRAPNE, M68K_INS_TRAPEQ,
|
M68K_INS_TRAPCC, M68K_INS_TRAPCS, M68K_INS_TRAPNE, M68K_INS_TRAPEQ,
|
||||||
M68K_INS_TRAPVC, M68K_INS_TRAPVS, M68K_INS_TRAPPL, M68K_INS_TRAPMI,
|
M68K_INS_TRAPVC, M68K_INS_TRAPVS, M68K_INS_TRAPPL, M68K_INS_TRAPMI,
|
||||||
@ -3379,7 +3379,7 @@ static void d68020_unpk_mm(m68k_info *info)
|
|||||||
static int instruction_is_valid(m68k_info *info, const unsigned int word_check)
|
static int instruction_is_valid(m68k_info *info, const unsigned int word_check)
|
||||||
{
|
{
|
||||||
const unsigned int instruction = info->ir;
|
const unsigned int instruction = info->ir;
|
||||||
instruction_struct *i = &g_instruction_table[instruction];
|
const instruction_struct *i = &g_instruction_table[instruction];
|
||||||
|
|
||||||
if ( (i->word2_mask && ((word_check & i->word2_mask) != i->word2_match)) ||
|
if ( (i->word2_mask && ((word_check & i->word2_mask) != i->word2_match)) ||
|
||||||
(i->instruction == d68000_invalid) ) {
|
(i->instruction == d68000_invalid) ) {
|
||||||
|
|||||||
@ -28,9 +28,9 @@
|
|||||||
#include "../../MCRegisterInfo.h"
|
#include "../../MCRegisterInfo.h"
|
||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static const char* s_spacing = " ";
|
static const char s_spacing[] = " ";
|
||||||
|
|
||||||
static const char* s_reg_names[] = {
|
static const char* const s_reg_names[] = {
|
||||||
"invalid",
|
"invalid",
|
||||||
"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
|
"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
|
||||||
"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
|
"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
|
||||||
@ -43,7 +43,7 @@ static const char* s_reg_names[] = {
|
|||||||
"fpcr", "fpsr", "fpiar",
|
"fpcr", "fpsr", "fpiar",
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char* s_instruction_names[] = {
|
static const char* const s_instruction_names[] = {
|
||||||
"invalid",
|
"invalid",
|
||||||
"abcd", "add", "adda", "addi", "addq", "addx", "and", "andi", "asl", "asr", "bhs", "blo", "bhi", "bls", "bcc", "bcs", "bne", "beq", "bvc",
|
"abcd", "add", "adda", "addi", "addq", "addx", "and", "andi", "asl", "asr", "bhs", "blo", "bhi", "bls", "bcc", "bcs", "bne", "beq", "bvc",
|
||||||
"bvs", "bpl", "bmi", "bge", "blt", "bgt", "ble", "bra", "bsr", "bchg", "bclr", "bset", "btst", "bfchg", "bfclr", "bfexts", "bfextu", "bfffo", "bfins",
|
"bvs", "bpl", "bmi", "bge", "blt", "bgt", "ble", "bra", "bsr", "bchg", "bclr", "bset", "btst", "bfchg", "bfclr", "bfexts", "bfextu", "bfffo", "bfins",
|
||||||
@ -367,7 +367,7 @@ const char* M68K_insn_name(csh handle, unsigned int id)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static name_map group_name_maps[] = {
|
static const name_map group_name_maps[] = {
|
||||||
{ M68K_GRP_INVALID , NULL },
|
{ M68K_GRP_INVALID , NULL },
|
||||||
{ M68K_GRP_JUMP, "jump" },
|
{ M68K_GRP_JUMP, "jump" },
|
||||||
{ M68K_GRP_RET , "ret" },
|
{ M68K_GRP_RET , "ret" },
|
||||||
|
|||||||
@ -1,5 +1,5 @@
|
|||||||
/* This table is auto-generated. DO NOT MANUALLY EDIT! Look in M68KInstructionTblGen.c for more info */
|
/* This table is auto-generated. DO NOT MANUALLY EDIT! Look in M68KInstructionTblGen.c for more info */
|
||||||
static instruction_struct g_instruction_table[] = {
|
static const instruction_struct g_instruction_table[] = {
|
||||||
{ d68000_ori_8, 0x0, 0x0 },
|
{ d68000_ori_8, 0x0, 0x0 },
|
||||||
{ d68000_ori_8, 0x0, 0x0 },
|
{ d68000_ori_8, 0x0, 0x0 },
|
||||||
{ d68000_ori_8, 0x0, 0x0 },
|
{ d68000_ori_8, 0x0, 0x0 },
|
||||||
|
|||||||
@ -20,12 +20,12 @@ static const struct OpInfo OpInfoTable[]= {
|
|||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char* RegNames[] = {
|
static const char* const RegNames[] = {
|
||||||
"invalid", "A", "X", "Y", "P", "SP", "DP", "B", "K"
|
"invalid", "A", "X", "Y", "P", "SP", "DP", "B", "K"
|
||||||
};
|
};
|
||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static const char* GroupNames[] = {
|
static const char* const GroupNames[] = {
|
||||||
NULL,
|
NULL,
|
||||||
"jump",
|
"jump",
|
||||||
"call",
|
"call",
|
||||||
|
|||||||
@ -24,7 +24,7 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
|
|||||||
return (insn & fieldMask) >> startBit; \
|
return (insn & fieldMask) >> startBit; \
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint8_t DecoderTableCOP3_32[] = {
|
static const uint8_t DecoderTableCOP3_32[] = {
|
||||||
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
|
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
|
||||||
/* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15
|
/* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15
|
||||||
/* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51
|
/* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51
|
||||||
@ -42,7 +42,7 @@ static uint8_t DecoderTableCOP3_32[] = {
|
|||||||
0
|
0
|
||||||
};
|
};
|
||||||
|
|
||||||
static uint8_t DecoderTableMicroMips16[] = {
|
static const uint8_t DecoderTableMicroMips16[] = {
|
||||||
/* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
|
/* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
|
||||||
/* 3 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 33
|
/* 3 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 33
|
||||||
/* 7 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ...
|
/* 7 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ...
|
||||||
|
|||||||
@ -494,7 +494,7 @@ enum {
|
|||||||
#ifdef GET_REGINFO_MC_DESC
|
#ifdef GET_REGINFO_MC_DESC
|
||||||
#undef GET_REGINFO_MC_DESC
|
#undef GET_REGINFO_MC_DESC
|
||||||
|
|
||||||
static MCPhysReg MipsRegDiffLists[] = {
|
static const MCPhysReg MipsRegDiffLists[] = {
|
||||||
/* 0 */ 0, 0,
|
/* 0 */ 0, 0,
|
||||||
/* 2 */ 4, 1, 1, 1, 1, 0,
|
/* 2 */ 4, 1, 1, 1, 1, 0,
|
||||||
/* 8 */ 364, 65286, 1, 1, 1, 0,
|
/* 8 */ 364, 65286, 1, 1, 1, 0,
|
||||||
@ -587,14 +587,14 @@ static MCPhysReg MipsRegDiffLists[] = {
|
|||||||
/* 251 */ 65535, 0,
|
/* 251 */ 65535, 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
static uint16_t MipsSubRegIdxLists[] = {
|
static const uint16_t MipsSubRegIdxLists[] = {
|
||||||
/* 0 */ 1, 0,
|
/* 0 */ 1, 0,
|
||||||
/* 2 */ 3, 4, 5, 6, 7, 0,
|
/* 2 */ 3, 4, 5, 6, 7, 0,
|
||||||
/* 8 */ 2, 9, 8, 0,
|
/* 8 */ 2, 9, 8, 0,
|
||||||
/* 12 */ 9, 1, 8, 10, 11, 0,
|
/* 12 */ 9, 1, 8, 10, 11, 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MCRegisterDesc MipsRegDesc[] = { // Descriptors
|
static const MCRegisterDesc MipsRegDesc[] = { // Descriptors
|
||||||
{ 6, 0, 0, 0, 0, 0 },
|
{ 6, 0, 0, 0, 0, 0 },
|
||||||
{ 2007, 1, 82, 1, 4017, 0 },
|
{ 2007, 1, 82, 1, 4017, 0 },
|
||||||
{ 2010, 1, 1, 1, 4017, 0 },
|
{ 2010, 1, 1, 1, 4017, 0 },
|
||||||
@ -992,626 +992,626 @@ static MCRegisterDesc MipsRegDesc[] = { // Descriptors
|
|||||||
};
|
};
|
||||||
|
|
||||||
// OddSP Register Class...
|
// OddSP Register Class...
|
||||||
static MCPhysReg OddSP[] = {
|
static const MCPhysReg OddSP[] = {
|
||||||
Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
|
Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// OddSP Bit set.
|
// OddSP Bit set.
|
||||||
static uint8_t OddSPBits[] = {
|
static const uint8_t OddSPBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CCR Register Class...
|
// CCR Register Class...
|
||||||
static MCPhysReg CCR[] = {
|
static const MCPhysReg CCR[] = {
|
||||||
Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31,
|
Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CCR Bit set.
|
// CCR Bit set.
|
||||||
static uint8_t CCRBits[] = {
|
static const uint8_t CCRBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||||
};
|
};
|
||||||
|
|
||||||
// COP2 Register Class...
|
// COP2 Register Class...
|
||||||
static MCPhysReg COP2[] = {
|
static const MCPhysReg COP2[] = {
|
||||||
Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231,
|
Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231,
|
||||||
};
|
};
|
||||||
|
|
||||||
// COP2 Bit set.
|
// COP2 Bit set.
|
||||||
static uint8_t COP2Bits[] = {
|
static const uint8_t COP2Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01,
|
0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
// COP3 Register Class...
|
// COP3 Register Class...
|
||||||
static MCPhysReg COP3[] = {
|
static const MCPhysReg COP3[] = {
|
||||||
Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331,
|
Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331,
|
||||||
};
|
};
|
||||||
|
|
||||||
// COP3 Bit set.
|
// COP3 Bit set.
|
||||||
static uint8_t COP3Bits[] = {
|
static const uint8_t COP3Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f,
|
||||||
};
|
};
|
||||||
|
|
||||||
// DSPR Register Class...
|
// DSPR Register Class...
|
||||||
static MCPhysReg DSPR[] = {
|
static const MCPhysReg DSPR[] = {
|
||||||
Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA,
|
Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA,
|
||||||
};
|
};
|
||||||
|
|
||||||
// DSPR Bit set.
|
// DSPR Bit set.
|
||||||
static uint8_t DSPRBits[] = {
|
static const uint8_t DSPRBits[] = {
|
||||||
0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
|
0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGR32 Register Class...
|
// FGR32 Register Class...
|
||||||
static MCPhysReg FGR32[] = {
|
static const MCPhysReg FGR32[] = {
|
||||||
Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
|
Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGR32 Bit set.
|
// FGR32 Bit set.
|
||||||
static uint8_t FGR32Bits[] = {
|
static const uint8_t FGR32Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGRCC Register Class...
|
// FGRCC Register Class...
|
||||||
static MCPhysReg FGRCC[] = {
|
static const MCPhysReg FGRCC[] = {
|
||||||
Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
|
Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGRCC Bit set.
|
// FGRCC Bit set.
|
||||||
static uint8_t FGRCCBits[] = {
|
static const uint8_t FGRCCBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGRH32 Register Class...
|
// FGRH32 Register Class...
|
||||||
static MCPhysReg FGRH32[] = {
|
static const MCPhysReg FGRH32[] = {
|
||||||
Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31,
|
Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGRH32 Bit set.
|
// FGRH32 Bit set.
|
||||||
static uint8_t FGRH32Bits[] = {
|
static const uint8_t FGRH32Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR32 Register Class...
|
// GPR32 Register Class...
|
||||||
static MCPhysReg GPR32[] = {
|
static const MCPhysReg GPR32[] = {
|
||||||
Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA,
|
Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR32 Bit set.
|
// GPR32 Bit set.
|
||||||
static uint8_t GPR32Bits[] = {
|
static const uint8_t GPR32Bits[] = {
|
||||||
0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
|
0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
|
||||||
};
|
};
|
||||||
|
|
||||||
// HWRegs Register Class...
|
// HWRegs Register Class...
|
||||||
static MCPhysReg HWRegs[] = {
|
static const MCPhysReg HWRegs[] = {
|
||||||
Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31,
|
Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// HWRegs Bit set.
|
// HWRegs Bit set.
|
||||||
static uint8_t HWRegsBits[] = {
|
static const uint8_t HWRegsBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
// OddSP_with_sub_hi Register Class...
|
// OddSP_with_sub_hi Register Class...
|
||||||
static MCPhysReg OddSP_with_sub_hi[] = {
|
static const MCPhysReg OddSP_with_sub_hi[] = {
|
||||||
Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
|
Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// OddSP_with_sub_hi Bit set.
|
// OddSP_with_sub_hi Bit set.
|
||||||
static uint8_t OddSP_with_sub_hiBits[] = {
|
static const uint8_t OddSP_with_sub_hiBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGR32_and_OddSP Register Class...
|
// FGR32_and_OddSP Register Class...
|
||||||
static MCPhysReg FGR32_and_OddSP[] = {
|
static const MCPhysReg FGR32_and_OddSP[] = {
|
||||||
Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31,
|
Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGR32_and_OddSP Bit set.
|
// FGR32_and_OddSP Bit set.
|
||||||
static uint8_t FGR32_and_OddSPBits[] = {
|
static const uint8_t FGR32_and_OddSPBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGRH32_and_OddSP Register Class...
|
// FGRH32_and_OddSP Register Class...
|
||||||
static MCPhysReg FGRH32_and_OddSP[] = {
|
static const MCPhysReg FGRH32_and_OddSP[] = {
|
||||||
Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31,
|
Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGRH32_and_OddSP Bit set.
|
// FGRH32_and_OddSP Bit set.
|
||||||
static uint8_t FGRH32_and_OddSPBits[] = {
|
static const uint8_t FGRH32_and_OddSPBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a,
|
||||||
};
|
};
|
||||||
|
|
||||||
// OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class...
|
// OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class...
|
||||||
static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = {
|
static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = {
|
||||||
Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
|
Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set.
|
// OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set.
|
||||||
static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = {
|
static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CPU16RegsPlusSP Register Class...
|
// CPU16RegsPlusSP Register Class...
|
||||||
static MCPhysReg CPU16RegsPlusSP[] = {
|
static const MCPhysReg CPU16RegsPlusSP[] = {
|
||||||
Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP,
|
Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CPU16RegsPlusSP Bit set.
|
// CPU16RegsPlusSP Bit set.
|
||||||
static uint8_t CPU16RegsPlusSPBits[] = {
|
static const uint8_t CPU16RegsPlusSPBits[] = {
|
||||||
0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CC Register Class...
|
// CC Register Class...
|
||||||
static MCPhysReg CC[] = {
|
static const MCPhysReg CC[] = {
|
||||||
Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7,
|
Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CC Bit set.
|
// CC Bit set.
|
||||||
static uint8_t CCBits[] = {
|
static const uint8_t CCBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x80, 0x7f,
|
0x00, 0x00, 0x00, 0x80, 0x7f,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CPU16Regs Register Class...
|
// CPU16Regs Register Class...
|
||||||
static MCPhysReg CPU16Regs[] = {
|
static const MCPhysReg CPU16Regs[] = {
|
||||||
Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1,
|
Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CPU16Regs Bit set.
|
// CPU16Regs Bit set.
|
||||||
static uint8_t CPU16RegsBits[] = {
|
static const uint8_t CPU16RegsBits[] = {
|
||||||
0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FCC Register Class...
|
// FCC Register Class...
|
||||||
static MCPhysReg FCC[] = {
|
static const MCPhysReg FCC[] = {
|
||||||
Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7,
|
Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FCC Bit set.
|
// FCC Bit set.
|
||||||
static uint8_t FCCBits[] = {
|
static const uint8_t FCCBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPRMM16 Register Class...
|
// GPRMM16 Register Class...
|
||||||
static MCPhysReg GPRMM16[] = {
|
static const MCPhysReg GPRMM16[] = {
|
||||||
Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3,
|
Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPRMM16 Bit set.
|
// GPRMM16 Bit set.
|
||||||
static uint8_t GPRMM16Bits[] = {
|
static const uint8_t GPRMM16Bits[] = {
|
||||||
0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPRMM16MoveP Register Class...
|
// GPRMM16MoveP Register Class...
|
||||||
static MCPhysReg GPRMM16MoveP[] = {
|
static const MCPhysReg GPRMM16MoveP[] = {
|
||||||
Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4,
|
Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPRMM16MoveP Bit set.
|
// GPRMM16MoveP Bit set.
|
||||||
static uint8_t GPRMM16MovePBits[] = {
|
static const uint8_t GPRMM16MovePBits[] = {
|
||||||
0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
|
0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPRMM16Zero Register Class...
|
// GPRMM16Zero Register Class...
|
||||||
static MCPhysReg GPRMM16Zero[] = {
|
static const MCPhysReg GPRMM16Zero[] = {
|
||||||
Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3,
|
Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPRMM16Zero Bit set.
|
// GPRMM16Zero Bit set.
|
||||||
static uint8_t GPRMM16ZeroBits[] = {
|
static const uint8_t GPRMM16ZeroBits[] = {
|
||||||
0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
|
0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSACtrl Register Class...
|
// MSACtrl Register Class...
|
||||||
static MCPhysReg MSACtrl[] = {
|
static const MCPhysReg MSACtrl[] = {
|
||||||
Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap,
|
Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSACtrl Bit set.
|
// MSACtrl Bit set.
|
||||||
static uint8_t MSACtrlBits[] = {
|
static const uint8_t MSACtrlBits[] = {
|
||||||
0x00, 0xfc, 0x03,
|
0x00, 0xfc, 0x03,
|
||||||
};
|
};
|
||||||
|
|
||||||
// OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class...
|
// OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class...
|
||||||
static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = {
|
static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = {
|
||||||
Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15,
|
Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15,
|
||||||
};
|
};
|
||||||
|
|
||||||
// OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set.
|
// OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set.
|
||||||
static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = {
|
static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CPU16Regs_and_GPRMM16Zero Register Class...
|
// CPU16Regs_and_GPRMM16Zero Register Class...
|
||||||
static MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
|
static const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
|
||||||
Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3,
|
Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CPU16Regs_and_GPRMM16Zero Bit set.
|
// CPU16Regs_and_GPRMM16Zero Bit set.
|
||||||
static uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
|
static const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
|
||||||
0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
|
0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CPU16Regs_and_GPRMM16MoveP Register Class...
|
// CPU16Regs_and_GPRMM16MoveP Register Class...
|
||||||
static MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
|
static const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
|
||||||
Mips_S1, Mips_V0, Mips_V1, Mips_S0,
|
Mips_S1, Mips_V0, Mips_V1, Mips_S0,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CPU16Regs_and_GPRMM16MoveP Bit set.
|
// CPU16Regs_and_GPRMM16MoveP Bit set.
|
||||||
static uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
|
static const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPRMM16MoveP_and_GPRMM16Zero Register Class...
|
// GPRMM16MoveP_and_GPRMM16Zero Register Class...
|
||||||
static MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
|
static const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
|
||||||
Mips_ZERO, Mips_S1, Mips_V0, Mips_V1,
|
Mips_ZERO, Mips_S1, Mips_V0, Mips_V1,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPRMM16MoveP_and_GPRMM16Zero Bit set.
|
// GPRMM16MoveP_and_GPRMM16Zero Bit set.
|
||||||
static uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
|
static const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
|
||||||
0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
|
0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
|
||||||
};
|
};
|
||||||
|
|
||||||
// HI32DSP Register Class...
|
// HI32DSP Register Class...
|
||||||
static MCPhysReg HI32DSP[] = {
|
static const MCPhysReg HI32DSP[] = {
|
||||||
Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3,
|
Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3,
|
||||||
};
|
};
|
||||||
|
|
||||||
// HI32DSP Bit set.
|
// HI32DSP Bit set.
|
||||||
static uint8_t HI32DSPBits[] = {
|
static const uint8_t HI32DSPBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
// LO32DSP Register Class...
|
// LO32DSP Register Class...
|
||||||
static MCPhysReg LO32DSP[] = {
|
static const MCPhysReg LO32DSP[] = {
|
||||||
Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3,
|
Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3,
|
||||||
};
|
};
|
||||||
|
|
||||||
// LO32DSP Bit set.
|
// LO32DSP Bit set.
|
||||||
static uint8_t LO32DSPBits[] = {
|
static const uint8_t LO32DSPBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
|
// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
|
||||||
static MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
|
static const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
|
||||||
Mips_S1, Mips_V0, Mips_V1,
|
Mips_S1, Mips_V0, Mips_V1,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
|
// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
|
||||||
static uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
|
static const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CPURAReg Register Class...
|
// CPURAReg Register Class...
|
||||||
static MCPhysReg CPURAReg[] = {
|
static const MCPhysReg CPURAReg[] = {
|
||||||
Mips_RA,
|
Mips_RA,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CPURAReg Bit set.
|
// CPURAReg Bit set.
|
||||||
static uint8_t CPURARegBits[] = {
|
static const uint8_t CPURARegBits[] = {
|
||||||
0x00, 0x00, 0x08,
|
0x00, 0x00, 0x08,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CPUSPReg Register Class...
|
// CPUSPReg Register Class...
|
||||||
static MCPhysReg CPUSPReg[] = {
|
static const MCPhysReg CPUSPReg[] = {
|
||||||
Mips_SP,
|
Mips_SP,
|
||||||
};
|
};
|
||||||
|
|
||||||
// CPUSPReg Bit set.
|
// CPUSPReg Bit set.
|
||||||
static uint8_t CPUSPRegBits[] = {
|
static const uint8_t CPUSPRegBits[] = {
|
||||||
0x00, 0x00, 0x10,
|
0x00, 0x00, 0x10,
|
||||||
};
|
};
|
||||||
|
|
||||||
// DSPCC Register Class...
|
// DSPCC Register Class...
|
||||||
static MCPhysReg DSPCC[] = {
|
static const MCPhysReg DSPCC[] = {
|
||||||
Mips_DSPCCond,
|
Mips_DSPCCond,
|
||||||
};
|
};
|
||||||
|
|
||||||
// DSPCC Bit set.
|
// DSPCC Bit set.
|
||||||
static uint8_t DSPCCBits[] = {
|
static const uint8_t DSPCCBits[] = {
|
||||||
0x04,
|
0x04,
|
||||||
};
|
};
|
||||||
|
|
||||||
// HI32 Register Class...
|
// HI32 Register Class...
|
||||||
static MCPhysReg HI32[] = {
|
static const MCPhysReg HI32[] = {
|
||||||
Mips_HI0,
|
Mips_HI0,
|
||||||
};
|
};
|
||||||
|
|
||||||
// HI32 Bit set.
|
// HI32 Bit set.
|
||||||
static uint8_t HI32Bits[] = {
|
static const uint8_t HI32Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
||||||
};
|
};
|
||||||
|
|
||||||
// LO32 Register Class...
|
// LO32 Register Class...
|
||||||
static MCPhysReg LO32[] = {
|
static const MCPhysReg LO32[] = {
|
||||||
Mips_LO0,
|
Mips_LO0,
|
||||||
};
|
};
|
||||||
|
|
||||||
// LO32 Bit set.
|
// LO32 Bit set.
|
||||||
static uint8_t LO32Bits[] = {
|
static const uint8_t LO32Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGR64 Register Class...
|
// FGR64 Register Class...
|
||||||
static MCPhysReg FGR64[] = {
|
static const MCPhysReg FGR64[] = {
|
||||||
Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64,
|
Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGR64 Bit set.
|
// FGR64 Bit set.
|
||||||
static uint8_t FGR64Bits[] = {
|
static const uint8_t FGR64Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64 Register Class...
|
// GPR64 Register Class...
|
||||||
static MCPhysReg GPR64[] = {
|
static const MCPhysReg GPR64[] = {
|
||||||
Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64,
|
Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64 Bit set.
|
// GPR64 Bit set.
|
||||||
static uint8_t GPR64Bits[] = {
|
static const uint8_t GPR64Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
|
0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
|
||||||
};
|
};
|
||||||
|
|
||||||
// AFGR64 Register Class...
|
// AFGR64 Register Class...
|
||||||
static MCPhysReg AFGR64[] = {
|
static const MCPhysReg AFGR64[] = {
|
||||||
Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15,
|
Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15,
|
||||||
};
|
};
|
||||||
|
|
||||||
// AFGR64 Bit set.
|
// AFGR64 Bit set.
|
||||||
static uint8_t AFGR64Bits[] = {
|
static const uint8_t AFGR64Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGR64_and_OddSP Register Class...
|
// FGR64_and_OddSP Register Class...
|
||||||
static MCPhysReg FGR64_and_OddSP[] = {
|
static const MCPhysReg FGR64_and_OddSP[] = {
|
||||||
Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
|
Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// FGR64_and_OddSP Bit set.
|
// FGR64_and_OddSP Bit set.
|
||||||
static uint8_t FGR64_and_OddSPBits[] = {
|
static const uint8_t FGR64_and_OddSPBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
|
// GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
|
||||||
static MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
|
static const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
|
||||||
Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64,
|
Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
|
// GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
|
||||||
static uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
|
static const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
|
||||||
};
|
};
|
||||||
|
|
||||||
// AFGR64_and_OddSP Register Class...
|
// AFGR64_and_OddSP Register Class...
|
||||||
static MCPhysReg AFGR64_and_OddSP[] = {
|
static const MCPhysReg AFGR64_and_OddSP[] = {
|
||||||
Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15,
|
Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15,
|
||||||
};
|
};
|
||||||
|
|
||||||
// AFGR64_and_OddSP Bit set.
|
// AFGR64_and_OddSP Bit set.
|
||||||
static uint8_t AFGR64_and_OddSPBits[] = {
|
static const uint8_t AFGR64_and_OddSPBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_CPU16Regs Register Class...
|
// GPR64_with_sub_32_in_CPU16Regs Register Class...
|
||||||
static MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
|
static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
|
||||||
Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64,
|
Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_CPU16Regs Bit set.
|
// GPR64_with_sub_32_in_CPU16Regs Bit set.
|
||||||
static uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
|
static const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
|
// GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
|
||||||
static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
|
static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
|
||||||
Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64,
|
Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
|
// GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
|
||||||
static uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
|
static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_GPRMM16Zero Register Class...
|
// GPR64_with_sub_32_in_GPRMM16Zero Register Class...
|
||||||
static MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
|
static const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
|
||||||
Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64,
|
Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_GPRMM16Zero Bit set.
|
// GPR64_with_sub_32_in_GPRMM16Zero Bit set.
|
||||||
static uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
|
static const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
|
// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
|
||||||
static MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
|
static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
|
||||||
Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64,
|
Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
|
// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
|
||||||
static uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
|
static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
|
||||||
};
|
};
|
||||||
|
|
||||||
// ACC64DSP Register Class...
|
// ACC64DSP Register Class...
|
||||||
static MCPhysReg ACC64DSP[] = {
|
static const MCPhysReg ACC64DSP[] = {
|
||||||
Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3,
|
Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3,
|
||||||
};
|
};
|
||||||
|
|
||||||
// ACC64DSP Bit set.
|
// ACC64DSP Bit set.
|
||||||
static uint8_t ACC64DSPBits[] = {
|
static const uint8_t ACC64DSPBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x3c,
|
0x00, 0x00, 0x00, 0x3c,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
|
// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
|
||||||
static MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
|
static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
|
||||||
Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64,
|
Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
|
// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
|
||||||
static uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
|
static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
|
// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
|
||||||
static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
|
static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
|
||||||
Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64,
|
Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
|
// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
|
||||||
static uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
|
static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
|
// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
|
||||||
static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
|
static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
|
||||||
Mips_V0_64, Mips_V1_64, Mips_S1_64,
|
Mips_V0_64, Mips_V1_64, Mips_S1_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
|
// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
|
||||||
static uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
|
static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
|
||||||
};
|
};
|
||||||
|
|
||||||
// OCTEON_MPL Register Class...
|
// OCTEON_MPL Register Class...
|
||||||
static MCPhysReg OCTEON_MPL[] = {
|
static const MCPhysReg OCTEON_MPL[] = {
|
||||||
Mips_MPL0, Mips_MPL1, Mips_MPL2,
|
Mips_MPL0, Mips_MPL1, Mips_MPL2,
|
||||||
};
|
};
|
||||||
|
|
||||||
// OCTEON_MPL Bit set.
|
// OCTEON_MPL Bit set.
|
||||||
static uint8_t OCTEON_MPLBits[] = {
|
static const uint8_t OCTEON_MPLBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
|
||||||
};
|
};
|
||||||
|
|
||||||
// OCTEON_P Register Class...
|
// OCTEON_P Register Class...
|
||||||
static MCPhysReg OCTEON_P[] = {
|
static const MCPhysReg OCTEON_P[] = {
|
||||||
Mips_P0, Mips_P1, Mips_P2,
|
Mips_P0, Mips_P1, Mips_P2,
|
||||||
};
|
};
|
||||||
|
|
||||||
// OCTEON_P Bit set.
|
// OCTEON_P Bit set.
|
||||||
static uint8_t OCTEON_PBits[] = {
|
static const uint8_t OCTEON_PBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
|
||||||
};
|
};
|
||||||
|
|
||||||
// ACC64 Register Class...
|
// ACC64 Register Class...
|
||||||
static MCPhysReg ACC64[] = {
|
static const MCPhysReg ACC64[] = {
|
||||||
Mips_AC0,
|
Mips_AC0,
|
||||||
};
|
};
|
||||||
|
|
||||||
// ACC64 Bit set.
|
// ACC64 Bit set.
|
||||||
static uint8_t ACC64Bits[] = {
|
static const uint8_t ACC64Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x04,
|
0x00, 0x00, 0x00, 0x04,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_CPURAReg Register Class...
|
// GPR64_with_sub_32_in_CPURAReg Register Class...
|
||||||
static MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
|
static const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
|
||||||
Mips_RA_64,
|
Mips_RA_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_CPURAReg Bit set.
|
// GPR64_with_sub_32_in_CPURAReg Bit set.
|
||||||
static uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
|
static const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_CPUSPReg Register Class...
|
// GPR64_with_sub_32_in_CPUSPReg Register Class...
|
||||||
static MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = {
|
static const MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = {
|
||||||
Mips_SP_64,
|
Mips_SP_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPR64_with_sub_32_in_CPUSPReg Bit set.
|
// GPR64_with_sub_32_in_CPUSPReg Bit set.
|
||||||
static uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = {
|
static const uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
|
||||||
};
|
};
|
||||||
|
|
||||||
// HI64 Register Class...
|
// HI64 Register Class...
|
||||||
static MCPhysReg HI64[] = {
|
static const MCPhysReg HI64[] = {
|
||||||
Mips_HI0_64,
|
Mips_HI0_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// HI64 Bit set.
|
// HI64 Bit set.
|
||||||
static uint8_t HI64Bits[] = {
|
static const uint8_t HI64Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
|
||||||
};
|
};
|
||||||
|
|
||||||
// LO64 Register Class...
|
// LO64 Register Class...
|
||||||
static MCPhysReg LO64[] = {
|
static const MCPhysReg LO64[] = {
|
||||||
Mips_LO0_64,
|
Mips_LO0_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// LO64 Bit set.
|
// LO64 Bit set.
|
||||||
static uint8_t LO64Bits[] = {
|
static const uint8_t LO64Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSA128B Register Class...
|
// MSA128B Register Class...
|
||||||
static MCPhysReg MSA128B[] = {
|
static const MCPhysReg MSA128B[] = {
|
||||||
Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
|
Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSA128B Bit set.
|
// MSA128B Bit set.
|
||||||
static uint8_t MSA128BBits[] = {
|
static const uint8_t MSA128BBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSA128D Register Class...
|
// MSA128D Register Class...
|
||||||
static MCPhysReg MSA128D[] = {
|
static const MCPhysReg MSA128D[] = {
|
||||||
Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
|
Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSA128D Bit set.
|
// MSA128D Bit set.
|
||||||
static uint8_t MSA128DBits[] = {
|
static const uint8_t MSA128DBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSA128H Register Class...
|
// MSA128H Register Class...
|
||||||
static MCPhysReg MSA128H[] = {
|
static const MCPhysReg MSA128H[] = {
|
||||||
Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
|
Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSA128H Bit set.
|
// MSA128H Bit set.
|
||||||
static uint8_t MSA128HBits[] = {
|
static const uint8_t MSA128HBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSA128W Register Class...
|
// MSA128W Register Class...
|
||||||
static MCPhysReg MSA128W[] = {
|
static const MCPhysReg MSA128W[] = {
|
||||||
Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
|
Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSA128W Bit set.
|
// MSA128W Bit set.
|
||||||
static uint8_t MSA128WBits[] = {
|
static const uint8_t MSA128WBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSA128B_with_sub_64_in_OddSP Register Class...
|
// MSA128B_with_sub_64_in_OddSP Register Class...
|
||||||
static MCPhysReg MSA128B_with_sub_64_in_OddSP[] = {
|
static const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = {
|
||||||
Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31,
|
Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSA128B_with_sub_64_in_OddSP Bit set.
|
// MSA128B_with_sub_64_in_OddSP Bit set.
|
||||||
static uint8_t MSA128B_with_sub_64_in_OddSPBits[] = {
|
static const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSA128WEvens Register Class...
|
// MSA128WEvens Register Class...
|
||||||
static MCPhysReg MSA128WEvens[] = {
|
static const MCPhysReg MSA128WEvens[] = {
|
||||||
Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30,
|
Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30,
|
||||||
};
|
};
|
||||||
|
|
||||||
// MSA128WEvens Bit set.
|
// MSA128WEvens Bit set.
|
||||||
static uint8_t MSA128WEvensBits[] = {
|
static const uint8_t MSA128WEvensBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,
|
||||||
};
|
};
|
||||||
|
|
||||||
// ACC128 Register Class...
|
// ACC128 Register Class...
|
||||||
static MCPhysReg ACC128[] = {
|
static const MCPhysReg ACC128[] = {
|
||||||
Mips_AC0_64,
|
Mips_AC0_64,
|
||||||
};
|
};
|
||||||
|
|
||||||
// ACC128 Bit set.
|
// ACC128 Bit set.
|
||||||
static uint8_t ACC128Bits[] = {
|
static const uint8_t ACC128Bits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MCRegisterClass MipsMCRegisterClasses[] = {
|
static const MCRegisterClass MipsMCRegisterClasses[] = {
|
||||||
{ OddSP, OddSPBits, sizeof(OddSPBits) },
|
{ OddSP, OddSPBits, sizeof(OddSPBits) },
|
||||||
{ CCR, CCRBits, sizeof(CCRBits) },
|
{ CCR, CCRBits, sizeof(CCRBits) },
|
||||||
{ COP2, COP2Bits, sizeof(COP2Bits) },
|
{ COP2, COP2Bits, sizeof(COP2Bits) },
|
||||||
|
|||||||
@ -210,7 +210,7 @@ const char *Mips_reg_name(csh handle, unsigned int reg)
|
|||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
static insn_map insns[] = {
|
static const insn_map insns[] = {
|
||||||
// dummy item
|
// dummy item
|
||||||
{
|
{
|
||||||
0, 0,
|
0, 0,
|
||||||
|
|||||||
@ -2178,313 +2178,313 @@ enum {
|
|||||||
|
|
||||||
#define nullptr 0
|
#define nullptr 0
|
||||||
|
|
||||||
static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
||||||
static MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
||||||
static MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
||||||
static MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
|
||||||
static MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
|
||||||
static MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
|
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
|
||||||
static MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
|
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
|
||||||
static MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
|
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
|
||||||
static MCOperandInfo OperandInfo31[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo31[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo32[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo32[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo33[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo33[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo34[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo34[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo35[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo35[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo36[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo36[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo37[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo37[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo38[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo38[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo39[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo39[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo40[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo40[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo41[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo41[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo42[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo42[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo43[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo43[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo44[] = { { PPC_SPILLTOVSRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo44[] = { { PPC_SPILLTOVSRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo45[] = { { PPC_SPILLTOVSRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo45[] = { { PPC_SPILLTOVSRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo46[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo46[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo47[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo47[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo48[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo48[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo49[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo49[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo50[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo50[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo51[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo51[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo52[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo52[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo53[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo53[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo54[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo54[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo55[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo55[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo56[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo56[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo57[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo57[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo58[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo58[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo59[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo59[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo60[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo60[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo61[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo61[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo62[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo62[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo63[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo63[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo64[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo64[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo65[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo65[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo66[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo66[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo67[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo67[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo68[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo68[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo69[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo69[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo70[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo70[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo71[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo71[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo72[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo72[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo73[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo73[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo74[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo74[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo75[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo75[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo76[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo76[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo77[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo77[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo78[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo78[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo79[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo79[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo80[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo80[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo81[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo81[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo82[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo82[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo83[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo83[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo84[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo84[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo85[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo85[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo86[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo86[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo87[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo87[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo88[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo88[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo89[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo89[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo90[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo90[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo91[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo91[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo92[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo92[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo93[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo93[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo94[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo94[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo95[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo95[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo96[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo96[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo97[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo97[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo98[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo98[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo99[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo99[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo100[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo100[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo101[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo101[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo102[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo102[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo103[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo103[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo104[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo104[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo105[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo105[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo106[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo106[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo107[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo107[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo108[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo108[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo109[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo109[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo110[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo110[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo111[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo111[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo112[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo112[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo113[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo113[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo114[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo114[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo115[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo115[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
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static MCOperandInfo OperandInfo116[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo116[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo117[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo117[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
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static MCOperandInfo OperandInfo118[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo118[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo119[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo119[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo120[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, };
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static const MCOperandInfo OperandInfo120[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, };
|
||||||
static MCOperandInfo OperandInfo121[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, };
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static const MCOperandInfo OperandInfo121[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, };
|
||||||
static MCOperandInfo OperandInfo122[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo122[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo123[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo123[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo124[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo124[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo125[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo125[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo126[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo126[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo127[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo127[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo128[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo128[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo129[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo129[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo130[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo130[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo131[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo131[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo132[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, };
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static const MCOperandInfo OperandInfo132[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, };
|
||||||
static MCOperandInfo OperandInfo133[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo133[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo134[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo134[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo135[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, };
|
static const MCOperandInfo OperandInfo135[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, };
|
||||||
static MCOperandInfo OperandInfo136[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo136[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo137[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo137[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo138[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo138[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo139[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo139[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo140[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo140[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo141[] = { { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo141[] = { { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo142[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo142[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo143[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo143[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo144[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo144[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo145[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo145[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo146[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo146[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo147[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo147[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo148[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo148[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo149[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo149[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo150[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo150[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo151[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo151[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo152[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo152[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo153[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo153[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo154[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRSAVERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo154[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRSAVERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo155[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo155[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo156[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo156[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo157[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo157[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo158[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo158[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo159[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo159[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo160[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo160[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo161[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo161[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo162[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo162[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo163[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo163[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo164[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo164[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo165[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo165[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo166[] = { { PPC_VRSAVERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo166[] = { { PPC_VRSAVERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo167[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo167[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo168[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo168[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo169[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo169[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo170[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo170[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo171[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo171[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo172[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo172[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo173[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo173[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo174[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo174[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo175[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo175[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo176[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo176[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo177[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo177[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo178[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo178[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo179[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo179[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo180[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo180[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo181[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo181[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo182[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo182[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo183[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo183[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo184[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo184[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo185[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo185[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo186[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo186[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo187[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo187[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo188[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo188[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo189[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo189[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo190[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo190[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo191[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo191[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo192[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo192[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo193[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo193[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo194[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo194[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo195[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo195[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo196[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo196[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo197[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo197[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
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static MCOperandInfo OperandInfo198[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo198[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo199[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo199[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo200[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo200[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo201[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo201[] = { { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo202[] = { { PPC_VRSAVERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo202[] = { { PPC_VRSAVERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo203[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo203[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo204[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo204[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo205[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo205[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo206[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo206[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo207[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo207[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo208[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo208[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo209[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo209[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo210[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo210[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo211[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo211[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo212[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo212[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo213[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo213[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo214[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo214[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo215[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo215[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo216[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo216[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo217[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo217[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo218[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo218[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo219[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo219[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo220[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo220[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo221[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo221[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo222[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo222[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo223[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo223[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo224[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo224[] = { { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo225[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo225[] = { { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo226[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo226[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRC_NOR0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo227[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo227[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RC_NOX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo228[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo228[] = { { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QBRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo229[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo229[] = { { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo230[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo230[] = { { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_QSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo231[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo231[] = { { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPERCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo232[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo232[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo233[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo233[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo234[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo234[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo235[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo235[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static MCOperandInfo OperandInfo236[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo236[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo237[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo237[] = { { PPC_SPE4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo238[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
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static const MCOperandInfo OperandInfo238[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
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static MCOperandInfo OperandInfo239[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
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static const MCOperandInfo OperandInfo239[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
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static MCOperandInfo OperandInfo240[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo240[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo241[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo241[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo242[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
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static const MCOperandInfo OperandInfo242[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
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||||||
static MCOperandInfo OperandInfo243[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo243[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_F8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static MCOperandInfo OperandInfo244[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
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static const MCOperandInfo OperandInfo244[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
|
||||||
static MCOperandInfo OperandInfo245[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo245[] = { { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { PPC_F4RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
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||||||
static MCOperandInfo OperandInfo246[] = { { PPC_CRRC0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo246[] = { { PPC_CRRC0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo247[] = { { PPC_CRRC0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo247[] = { { PPC_CRRC0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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||||||
static MCOperandInfo OperandInfo248[] = { { PPC_CRRC0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo248[] = { { PPC_CRRC0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo249[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo249[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo250[] = { { PPC_CTRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo250[] = { { PPC_CTRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo251[] = { { PPC_CTRRC8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo251[] = { { PPC_CTRRC8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo252[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo252[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo253[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo253[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo254[] = { { PPC_CRRC0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo254[] = { { PPC_CRRC0RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo255[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo255[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
static MCOperandInfo OperandInfo256[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo256[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo257[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo257[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo258[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo258[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo259[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo259[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo260[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo260[] = { { PPC_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo261[] = { { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo261[] = { { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo262[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo262[] = { { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo263[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo263[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo264[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
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static const MCOperandInfo OperandInfo264[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, };
|
||||||
static MCOperandInfo OperandInfo265[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo265[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo266[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo266[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo267[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo267[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo268[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo268[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo269[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo269[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo270[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo270[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo271[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo271[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo272[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo272[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo273[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo273[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo274[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo274[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo275[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo275[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo276[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo276[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo277[] = { { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo277[] = { { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo278[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo278[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo279[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo279[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo280[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo280[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_G8RCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo281[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo281[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo282[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo282[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo283[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo283[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo284[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo284[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo285[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo285[] = { { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo286[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo286[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo287[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo287[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo288[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo288[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo289[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo289[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo290[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo290[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo291[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo291[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo292[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo292[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo293[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo293[] = { { PPC_CRRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo294[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo294[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo295[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo295[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo296[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo296[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo297[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo297[] = { { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo298[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo298[] = { { PPC_VSSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo299[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo299[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo300[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo300[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo301[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo301[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo302[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
static const MCOperandInfo OperandInfo302[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||||
static MCOperandInfo OperandInfo303[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo303[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo304[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo304[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo305[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo305[] = { { PPC_VSRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { PPC_VFRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo306[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo306[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo307[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
static const MCOperandInfo OperandInfo307[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||||
static MCOperandInfo OperandInfo308[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
static const MCOperandInfo OperandInfo308[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { PPC_CRBITRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||||
|
|
||||||
static const MCInstrDesc PPCInsts[] = {
|
static const MCInstrDesc PPCInsts[] = {
|
||||||
{ 1, OperandInfo2 },
|
{ 1, OperandInfo2 },
|
||||||
|
|||||||
@ -453,7 +453,7 @@ static const uint16_t PPCSubRegIdxLists[] = {
|
|||||||
/* 4 */ 5, 4, 3, 6, 0,
|
/* 4 */ 5, 4, 3, 6, 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MCRegisterDesc PPCRegDesc[] = {
|
static const MCRegisterDesc PPCRegDesc[] = {
|
||||||
{ 4, 0, 0, 0, 0, 0 },
|
{ 4, 0, 0, 0, 0, 0 },
|
||||||
{ 1237, 1, 9, 1, 1281, 0 },
|
{ 1237, 1, 9, 1, 1281, 0 },
|
||||||
{ 1406, 1, 1, 1, 1281, 0 },
|
{ 1406, 1, 1, 1, 1281, 0 },
|
||||||
@ -1090,7 +1090,7 @@ static MCRegisterDesc PPCRegDesc[] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
static MCRegisterClass PPCMCRegisterClasses[] = {
|
static const MCRegisterClass PPCMCRegisterClasses[] = {
|
||||||
{ VSSRC, VSSRCBits, sizeof(VSSRCBits) },
|
{ VSSRC, VSSRCBits, sizeof(VSSRCBits) },
|
||||||
{ GPRC, GPRCBits, sizeof(GPRCBits) },
|
{ GPRC, GPRCBits, sizeof(GPRCBits) },
|
||||||
{ GPRC_NOR0, GPRC_NOR0Bits, sizeof(GPRC_NOR0Bits) },
|
{ GPRC_NOR0, GPRC_NOR0Bits, sizeof(GPRC_NOR0Bits) },
|
||||||
|
|||||||
@ -353,7 +353,7 @@ void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static const char *insn_name_maps[] = {
|
static const char * const insn_name_maps[] = {
|
||||||
NULL, // PPC_INS_BCT
|
NULL, // PPC_INS_BCT
|
||||||
#include "PPCMappingInsnName.inc"
|
#include "PPCMappingInsnName.inc"
|
||||||
};
|
};
|
||||||
|
|||||||
@ -235,7 +235,7 @@ static const uint16_t SparcSubRegIdxLists[] = {
|
|||||||
/* 6 */ 2, 1, 3, 4, 5, 6, 0,
|
/* 6 */ 2, 1, 3, 4, 5, 6, 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MCRegisterDesc SparcRegDesc[] = { // Descriptors
|
static const MCRegisterDesc SparcRegDesc[] = { // Descriptors
|
||||||
{ 3, 0, 0, 0, 0, 0 },
|
{ 3, 0, 0, 0, 0, 0 },
|
||||||
{ 406, 4, 4, 2, 3393, 0 },
|
{ 406, 4, 4, 2, 3393, 0 },
|
||||||
{ 410, 4, 4, 2, 3393, 0 },
|
{ 410, 4, 4, 2, 3393, 0 },
|
||||||
@ -437,7 +437,7 @@ static MCRegisterDesc SparcRegDesc[] = { // Descriptors
|
|||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MCRegisterClass SparcMCRegisterClasses[] = {
|
static const MCRegisterClass SparcMCRegisterClasses[] = {
|
||||||
{ FCCRegs, FCCRegsBits, sizeof(FCCRegsBits) },
|
{ FCCRegs, FCCRegsBits, sizeof(FCCRegsBits) },
|
||||||
{ FPRegs, FPRegsBits, sizeof(FPRegsBits) },
|
{ FPRegs, FPRegsBits, sizeof(FPRegsBits) },
|
||||||
{ IntRegs, IntRegsBits, sizeof(IntRegsBits) },
|
{ IntRegs, IntRegsBits, sizeof(IntRegsBits) },
|
||||||
|
|||||||
@ -12,6 +12,7 @@
|
|||||||
|
|
||||||
#ifdef CAPSTONE_HAS_SYSZ
|
#ifdef CAPSTONE_HAS_SYSZ
|
||||||
|
|
||||||
|
#include <capstone/platform.h>
|
||||||
#include "SystemZMCTargetDesc.h"
|
#include "SystemZMCTargetDesc.h"
|
||||||
|
|
||||||
#define GET_REGINFO_ENUM
|
#define GET_REGINFO_ENUM
|
||||||
@ -113,30 +114,80 @@ const unsigned SystemZMC_CR64Regs[16] = {
|
|||||||
SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15
|
SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* All register classes that have 0-15. */
|
||||||
|
#define DEF_REG16(N) \
|
||||||
|
[SystemZ_R ## N ## L] = N, \
|
||||||
|
[SystemZ_R ## N ## H] = N, \
|
||||||
|
[SystemZ_R ## N ## D] = N, \
|
||||||
|
[SystemZ_F ## N ## S] = N, \
|
||||||
|
[SystemZ_F ## N ## D] = N, \
|
||||||
|
[SystemZ_V ## N] = N, \
|
||||||
|
[SystemZ_A ## N] = N, \
|
||||||
|
[SystemZ_C ## N] = N
|
||||||
|
|
||||||
|
/* All register classes that (also) have 16-31. */
|
||||||
|
#define DEF_REG32(N) \
|
||||||
|
[SystemZ_F ## N ## S] = N, \
|
||||||
|
[SystemZ_F ## N ## D] = N, \
|
||||||
|
[SystemZ_V ## N] = N
|
||||||
|
|
||||||
|
static const uint8_t Map[SystemZ_NUM_TARGET_REGS] = {
|
||||||
|
DEF_REG16(0),
|
||||||
|
DEF_REG16(1),
|
||||||
|
DEF_REG16(2),
|
||||||
|
DEF_REG16(3),
|
||||||
|
DEF_REG16(4),
|
||||||
|
DEF_REG16(5),
|
||||||
|
DEF_REG16(6),
|
||||||
|
DEF_REG16(8),
|
||||||
|
DEF_REG16(9),
|
||||||
|
DEF_REG16(10),
|
||||||
|
DEF_REG16(11),
|
||||||
|
DEF_REG16(12),
|
||||||
|
DEF_REG16(13),
|
||||||
|
DEF_REG16(14),
|
||||||
|
DEF_REG16(15),
|
||||||
|
|
||||||
|
DEF_REG32(16),
|
||||||
|
DEF_REG32(17),
|
||||||
|
DEF_REG32(18),
|
||||||
|
DEF_REG32(19),
|
||||||
|
DEF_REG32(20),
|
||||||
|
DEF_REG32(21),
|
||||||
|
DEF_REG32(22),
|
||||||
|
DEF_REG32(23),
|
||||||
|
DEF_REG32(24),
|
||||||
|
DEF_REG32(25),
|
||||||
|
DEF_REG32(26),
|
||||||
|
DEF_REG32(27),
|
||||||
|
DEF_REG32(28),
|
||||||
|
DEF_REG32(29),
|
||||||
|
DEF_REG32(30),
|
||||||
|
DEF_REG32(31),
|
||||||
|
|
||||||
|
/* The float Q registers are non-sequential. */
|
||||||
|
[SystemZ_F0Q] = 0,
|
||||||
|
[SystemZ_F1Q] = 1,
|
||||||
|
[SystemZ_F4Q] = 4,
|
||||||
|
[SystemZ_F5Q] = 5,
|
||||||
|
[SystemZ_F8Q] = 8,
|
||||||
|
[SystemZ_F9Q] = 9,
|
||||||
|
[SystemZ_F12Q] = 12,
|
||||||
|
[SystemZ_F13Q] = 13,
|
||||||
|
|
||||||
|
/* The integer Q registers are all even. */
|
||||||
|
[SystemZ_R0Q] = 0,
|
||||||
|
[SystemZ_R2Q] = 2,
|
||||||
|
[SystemZ_R4Q] = 4,
|
||||||
|
[SystemZ_R6Q] = 6,
|
||||||
|
[SystemZ_R8Q] = 8,
|
||||||
|
[SystemZ_R10Q] = 10,
|
||||||
|
[SystemZ_R12Q] = 12,
|
||||||
|
[SystemZ_R14Q] = 14,
|
||||||
|
};
|
||||||
|
|
||||||
unsigned SystemZMC_getFirstReg(unsigned Reg)
|
unsigned SystemZMC_getFirstReg(unsigned Reg)
|
||||||
{
|
{
|
||||||
static unsigned Map[SystemZ_NUM_TARGET_REGS];
|
|
||||||
static int Initialized = 0;
|
|
||||||
unsigned I;
|
|
||||||
|
|
||||||
if (!Initialized) {
|
|
||||||
Initialized = 1;
|
|
||||||
for (I = 0; I < 16; ++I) {
|
|
||||||
Map[SystemZMC_GR32Regs[I]] = I;
|
|
||||||
Map[SystemZMC_GRH32Regs[I]] = I;
|
|
||||||
Map[SystemZMC_GR64Regs[I]] = I;
|
|
||||||
Map[SystemZMC_GR128Regs[I]] = I;
|
|
||||||
Map[SystemZMC_FP32Regs[I]] = I;
|
|
||||||
Map[SystemZMC_FP64Regs[I]] = I;
|
|
||||||
Map[SystemZMC_FP128Regs[I]] = I;
|
|
||||||
Map[SystemZMC_VR32Regs[I]] = I;
|
|
||||||
Map[SystemZMC_VR64Regs[I]] = I;
|
|
||||||
Map[SystemZMC_VR128Regs[I]] = I;
|
|
||||||
Map[SystemZMC_AR32Regs[I]] = I;
|
|
||||||
Map[SystemZMC_CR64Regs[I]] = I;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
// assert(Reg < SystemZ_NUM_TARGET_REGS);
|
// assert(Reg < SystemZ_NUM_TARGET_REGS);
|
||||||
return Map[Reg];
|
return Map[Reg];
|
||||||
}
|
}
|
||||||
|
|||||||
@ -295,7 +295,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) {
|
|||||||
0U
|
0U
|
||||||
};
|
};
|
||||||
|
|
||||||
static char AsmStrs[] = {
|
static const char AsmStrs[] = {
|
||||||
/* 0 */ 'n', 'o', 'p', 9, 9, 0,
|
/* 0 */ 'n', 'o', 'p', 9, 9, 0,
|
||||||
/* 6 */ 's', 'u', 'b', '2', 9, 0,
|
/* 6 */ 's', 'u', 'b', '2', 9, 0,
|
||||||
/* 12 */ 's', 'a', 'd', 'd', '2', 9, 0,
|
/* 12 */ 's', 'a', 'd', 'd', '2', 9, 0,
|
||||||
@ -576,9 +576,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) {
|
|||||||
/// getRegisterName - This method is automatically generated by tblgen
|
/// getRegisterName - This method is automatically generated by tblgen
|
||||||
/// from the register set description. This returns the assembler name
|
/// from the register set description. This returns the assembler name
|
||||||
/// for the specified register.
|
/// for the specified register.
|
||||||
static char *getRegisterName(unsigned RegNo) {
|
static const char *getRegisterName(unsigned RegNo) {
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static char AsmStrs[] = {
|
static const char AsmStrs[] = {
|
||||||
/* 0 */ 'a', '1', '0', 0,
|
/* 0 */ 'a', '1', '0', 0,
|
||||||
/* 4 */ 'b', '1', '0', 0,
|
/* 4 */ 'b', '1', '0', 0,
|
||||||
/* 8 */ 'a', '2', '0', 0,
|
/* 8 */ 'a', '2', '0', 0,
|
||||||
|
|||||||
@ -21,7 +21,7 @@ static InsnType fname(InsnType insn, unsigned startBit, \
|
|||||||
return (insn & fieldMask) >> startBit; \
|
return (insn & fieldMask) >> startBit; \
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint8_t DecoderTable32[] = {
|
static const uint8_t DecoderTable32[] = {
|
||||||
/* 0 */ MCD_OPC_ExtractField, 2, 5, // Inst{6-2} ...
|
/* 0 */ MCD_OPC_ExtractField, 2, 5, // Inst{6-2} ...
|
||||||
/* 3 */ MCD_OPC_FilterValue, 0, 199, 0, // Skip to: 206
|
/* 3 */ MCD_OPC_FilterValue, 0, 199, 0, // Skip to: 206
|
||||||
/* 7 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ...
|
/* 7 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ...
|
||||||
@ -1268,12 +1268,12 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
|
|||||||
}
|
}
|
||||||
|
|
||||||
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
|
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
|
||||||
static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
|
static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
|
||||||
InsnType insn, uint64_t Address, \
|
InsnType insn, uint64_t Address, \
|
||||||
MCRegisterInfo *MRI, \
|
MCRegisterInfo *MRI, \
|
||||||
int feature) { \
|
int feature) { \
|
||||||
uint64_t Bits = getFeatureBits(feature); \
|
uint64_t Bits = getFeatureBits(feature); \
|
||||||
uint8_t *Ptr = DecodeTable; \
|
const uint8_t *Ptr = DecodeTable; \
|
||||||
uint32_t CurFieldValue = 0, ExpectedValue; \
|
uint32_t CurFieldValue = 0, ExpectedValue; \
|
||||||
DecodeStatus S = MCDisassembler_Success; \
|
DecodeStatus S = MCDisassembler_Success; \
|
||||||
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
|
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
|
||||||
|
|||||||
@ -126,15 +126,15 @@ enum {
|
|||||||
#ifdef GET_REGINFO_MC_DESC
|
#ifdef GET_REGINFO_MC_DESC
|
||||||
#undef GET_REGINFO_MC_DESC
|
#undef GET_REGINFO_MC_DESC
|
||||||
|
|
||||||
static MCPhysReg TMS320C64xRegDiffLists[] = {
|
static const MCPhysReg TMS320C64xRegDiffLists[] = {
|
||||||
/* 0 */ 65535, 0,
|
/* 0 */ 65535, 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
static uint16_t TMS320C64xSubRegIdxLists[] = {
|
static const uint16_t TMS320C64xSubRegIdxLists[] = {
|
||||||
/* 0 */ 0,
|
/* 0 */ 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MCRegisterDesc TMS320C64xRegDesc[] = { // Descriptors
|
static const MCRegisterDesc TMS320C64xRegDesc[] = { // Descriptors
|
||||||
{ 3, 0, 0, 0, 0 },
|
{ 3, 0, 0, 0, 0 },
|
||||||
{ 310, 1, 1, 0, 1 },
|
{ 310, 1, 1, 0, 1 },
|
||||||
{ 319, 1, 1, 0, 1 },
|
{ 319, 1, 1, 0, 1 },
|
||||||
@ -228,46 +228,46 @@ static MCRegisterDesc TMS320C64xRegDesc[] = { // Descriptors
|
|||||||
};
|
};
|
||||||
|
|
||||||
// GPRegs Register Class...
|
// GPRegs Register Class...
|
||||||
static MCPhysReg GPRegs[] = {
|
static const MCPhysReg GPRegs[] = {
|
||||||
TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31, TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31,
|
TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31, TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// GPRegs Bit set.
|
// GPRegs Bit set.
|
||||||
static uint8_t GPRegsBits[] = {
|
static const uint8_t GPRegsBits[] = {
|
||||||
0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01,
|
0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
// AFRegs Register Class...
|
// AFRegs Register Class...
|
||||||
static MCPhysReg AFRegs[] = {
|
static const MCPhysReg AFRegs[] = {
|
||||||
TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31,
|
TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// AFRegs Bit set.
|
// AFRegs Bit set.
|
||||||
static uint8_t AFRegsBits[] = {
|
static const uint8_t AFRegsBits[] = {
|
||||||
0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
|
0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
// BFRegs Register Class...
|
// BFRegs Register Class...
|
||||||
static MCPhysReg BFRegs[] = {
|
static const MCPhysReg BFRegs[] = {
|
||||||
TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31,
|
TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31,
|
||||||
};
|
};
|
||||||
|
|
||||||
// BFRegs Bit set.
|
// BFRegs Bit set.
|
||||||
static uint8_t BFRegsBits[] = {
|
static const uint8_t BFRegsBits[] = {
|
||||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
// ControlRegs Register Class...
|
// ControlRegs Register Class...
|
||||||
static MCPhysReg ControlRegs[] = {
|
static const MCPhysReg ControlRegs[] = {
|
||||||
TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_DIER, TMS320C64x_DNUM, TMS320C64x_ECR, TMS320C64x_GFPGFR, TMS320C64x_GPLYA, TMS320C64x_GPLYB, TMS320C64x_ICR, TMS320C64x_IER, TMS320C64x_IERR, TMS320C64x_ILC, TMS320C64x_IRP, TMS320C64x_ISR, TMS320C64x_ISTP, TMS320C64x_ITSR, TMS320C64x_NRP, TMS320C64x_NTSR, TMS320C64x_PCE1, TMS320C64x_REP, TMS320C64x_RILC, TMS320C64x_SSR, TMS320C64x_TSCH, TMS320C64x_TSCL, TMS320C64x_TSR,
|
TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_DIER, TMS320C64x_DNUM, TMS320C64x_ECR, TMS320C64x_GFPGFR, TMS320C64x_GPLYA, TMS320C64x_GPLYB, TMS320C64x_ICR, TMS320C64x_IER, TMS320C64x_IERR, TMS320C64x_ILC, TMS320C64x_IRP, TMS320C64x_ISR, TMS320C64x_ISTP, TMS320C64x_ITSR, TMS320C64x_NRP, TMS320C64x_NTSR, TMS320C64x_PCE1, TMS320C64x_REP, TMS320C64x_RILC, TMS320C64x_SSR, TMS320C64x_TSCH, TMS320C64x_TSCL, TMS320C64x_TSR,
|
||||||
};
|
};
|
||||||
|
|
||||||
// ControlRegs Bit set.
|
// ControlRegs Bit set.
|
||||||
static uint8_t ControlRegsBits[] = {
|
static const uint8_t ControlRegsBits[] = {
|
||||||
0xfe, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
|
0xfe, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MCRegisterClass TMS320C64xMCRegisterClasses[] = {
|
static const MCRegisterClass TMS320C64xMCRegisterClasses[] = {
|
||||||
{ GPRegs, GPRegsBits, TMS320C64x_GPRegsRegClassID },
|
{ GPRegs, GPRegsBits, TMS320C64x_GPRegsRegClassID },
|
||||||
{ AFRegs, AFRegsBits, TMS320C64x_AFRegsRegClassID },
|
{ AFRegs, AFRegsBits, TMS320C64x_AFRegsRegClassID },
|
||||||
{ BFRegs, BFRegsBits, TMS320C64x_BFRegsRegClassID },
|
{ BFRegs, BFRegsBits, TMS320C64x_BFRegsRegClassID },
|
||||||
|
|||||||
@ -27,7 +27,7 @@
|
|||||||
|
|
||||||
#include "capstone/tms320c64x.h"
|
#include "capstone/tms320c64x.h"
|
||||||
|
|
||||||
static char *getRegisterName(unsigned RegNo);
|
static const char *getRegisterName(unsigned RegNo);
|
||||||
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
|
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
|
||||||
static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
|
static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
|
||||||
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
|
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
|
||||||
|
|||||||
@ -13,7 +13,7 @@
|
|||||||
#define GET_INSTRINFO_ENUM
|
#define GET_INSTRINFO_ENUM
|
||||||
#include "TMS320C64xGenInstrInfo.inc"
|
#include "TMS320C64xGenInstrInfo.inc"
|
||||||
|
|
||||||
static name_map reg_name_maps[] = {
|
static const name_map reg_name_maps[] = {
|
||||||
{ TMS320C64X_REG_INVALID, NULL },
|
{ TMS320C64X_REG_INVALID, NULL },
|
||||||
|
|
||||||
{ TMS320C64X_REG_AMR, "amr" },
|
{ TMS320C64X_REG_AMR, "amr" },
|
||||||
@ -131,7 +131,7 @@ tms320c64x_reg TMS320C64x_reg_id(char *name)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static insn_map insns[] = {
|
static const insn_map insns[] = {
|
||||||
{
|
{
|
||||||
0, 0,
|
0, 0,
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
@ -1719,7 +1719,7 @@ void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
//grep TMS320C64X_INS include/capstone/tms320c64x.h | awk '{print "{"$1 "\""tolower(substr($1, 16, length($1)-16))"\"""},"}'
|
//grep TMS320C64X_INS include/capstone/tms320c64x.h | awk '{print "{"$1 "\""tolower(substr($1, 16, length($1)-16))"\"""},"}'
|
||||||
static name_map insn_name_maps[] = {
|
static const name_map insn_name_maps[] = {
|
||||||
{TMS320C64X_INS_INVALID, NULL},
|
{TMS320C64X_INS_INVALID, NULL},
|
||||||
{TMS320C64X_INS_ABS, "abs"},
|
{TMS320C64X_INS_ABS, "abs"},
|
||||||
{TMS320C64X_INS_ABS2, "abs2"},
|
{TMS320C64X_INS_ABS2, "abs2"},
|
||||||
@ -1882,7 +1882,7 @@ const char *TMS320C64x_insn_name(csh handle, unsigned int id)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static name_map group_name_maps[] = {
|
static const name_map group_name_maps[] = {
|
||||||
{ TMS320C64X_GRP_INVALID, NULL },
|
{ TMS320C64X_GRP_INVALID, NULL },
|
||||||
{ TMS320C64X_GRP_FUNIT_D, "funit_d" },
|
{ TMS320C64X_GRP_FUNIT_D, "funit_d" },
|
||||||
{ TMS320C64X_GRP_FUNIT_L, "funit_l" },
|
{ TMS320C64X_GRP_FUNIT_L, "funit_l" },
|
||||||
|
|||||||
@ -9,7 +9,7 @@
|
|||||||
#include "WASMMapping.h"
|
#include "WASMMapping.h"
|
||||||
#include "../../cs_priv.h"
|
#include "../../cs_priv.h"
|
||||||
|
|
||||||
static short opcodes[256] = {
|
static const short opcodes[256] = {
|
||||||
WASM_INS_UNREACHABLE,
|
WASM_INS_UNREACHABLE,
|
||||||
WASM_INS_NOP,
|
WASM_INS_NOP,
|
||||||
WASM_INS_BLOCK,
|
WASM_INS_BLOCK,
|
||||||
|
|||||||
@ -17,7 +17,7 @@ void WASM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static name_map insn_name_maps[256] = {
|
static const name_map insn_name_maps[256] = {
|
||||||
{ WASM_INS_UNREACHABLE, "unreachable" },
|
{ WASM_INS_UNREACHABLE, "unreachable" },
|
||||||
{ WASM_INS_NOP, "nop" },
|
{ WASM_INS_NOP, "nop" },
|
||||||
{ WASM_INS_BLOCK, "block" },
|
{ WASM_INS_BLOCK, "block" },
|
||||||
@ -290,7 +290,7 @@ const char *WASM_insn_name(csh handle, unsigned int id)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static name_map group_name_maps[] = {
|
static const name_map group_name_maps[] = {
|
||||||
// generic groups
|
// generic groups
|
||||||
{ WASM_GRP_INVALID, NULL },
|
{ WASM_GRP_INVALID, NULL },
|
||||||
// special groups
|
// special groups
|
||||||
@ -303,7 +303,7 @@ static name_map group_name_maps[] = {
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static name_map kind_name_maps[] = {
|
static const name_map kind_name_maps[] = {
|
||||||
{ WASM_OP_INVALID, "Invalid" },
|
{ WASM_OP_INVALID, "Invalid" },
|
||||||
{ WASM_OP_NONE, "None" },
|
{ WASM_OP_NONE, "None" },
|
||||||
{ WASM_OP_INT7, "uint7" },
|
{ WASM_OP_INT7, "uint7" },
|
||||||
|
|||||||
@ -284,7 +284,7 @@ static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
|||||||
static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags)
|
static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags)
|
||||||
{
|
{
|
||||||
uint8_t count, i;
|
uint8_t count, i;
|
||||||
uint8_t *arr = X86_get_op_access(h, id, eflags);
|
const uint8_t *arr = X86_get_op_access(h, id, eflags);
|
||||||
|
|
||||||
if (!arr) {
|
if (!arr) {
|
||||||
access[0] = 0;
|
access[0] = 0;
|
||||||
|
|||||||
@ -160,7 +160,7 @@ static InstrUID decode(OpcodeType type,
|
|||||||
{
|
{
|
||||||
const struct ModRMDecision *dec = NULL;
|
const struct ModRMDecision *dec = NULL;
|
||||||
unsigned int index;
|
unsigned int index;
|
||||||
static struct OpcodeDecision emptyDecision = { 0 };
|
static const struct OpcodeDecision emptyDecision = { 0 };
|
||||||
|
|
||||||
switch (type) {
|
switch (type) {
|
||||||
default: break; // never reach
|
default: break; // never reach
|
||||||
|
|||||||
@ -487,7 +487,7 @@ static const uint16_t X86SubRegIdxLists[] = {
|
|||||||
/* 22 */ 8, 7, 0,
|
/* 22 */ 8, 7, 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MCRegisterDesc X86RegDesc[] = {
|
static const MCRegisterDesc X86RegDesc[] = {
|
||||||
{ 5, 0, 0, 0, 0, 0 },
|
{ 5, 0, 0, 0, 0, 0 },
|
||||||
{ 873, 2, 184, 2, 4641, 0 },
|
{ 873, 2, 184, 2, 4641, 0 },
|
||||||
{ 1014, 2, 180, 2, 4641, 0 },
|
{ 1014, 2, 180, 2, 4641, 0 },
|
||||||
@ -1457,7 +1457,7 @@ static MCRegisterDesc X86RegDesc[] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
static MCRegisterClass X86MCRegisterClasses[] = {
|
static const MCRegisterClass X86MCRegisterClasses[] = {
|
||||||
{ GR8, GR8Bits, sizeof(GR8Bits) },
|
{ GR8, GR8Bits, sizeof(GR8Bits) },
|
||||||
{ GRH8, GRH8Bits, sizeof(GRH8Bits) },
|
{ GRH8, GRH8Bits, sizeof(GRH8Bits) },
|
||||||
{ GR8_NOREX, GR8_NOREXBits, sizeof(GR8_NOREXBits) },
|
{ GR8_NOREX, GR8_NOREXBits, sizeof(GR8_NOREXBits) },
|
||||||
|
|||||||
@ -428,7 +428,7 @@ static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64
|
|||||||
{
|
{
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
uint8_t i;
|
uint8_t i;
|
||||||
uint8_t *arr = X86_get_op_access(h, id, eflags);
|
const uint8_t *arr = X86_get_op_access(h, id, eflags);
|
||||||
|
|
||||||
if (!arr) {
|
if (!arr) {
|
||||||
access[0] = 0;
|
access[0] = 0;
|
||||||
|
|||||||
@ -856,7 +856,7 @@ const char *X86_reg_name(csh handle, unsigned int reg)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#ifndef CAPSTONE_DIET
|
#ifndef CAPSTONE_DIET
|
||||||
static const char *insn_name_maps[] = {
|
static const char * const insn_name_maps[] = {
|
||||||
NULL, // X86_INS_INVALID
|
NULL, // X86_INS_INVALID
|
||||||
#ifndef CAPSTONE_X86_REDUCE
|
#ifndef CAPSTONE_X86_REDUCE
|
||||||
#include "X86MappingInsnName.inc"
|
#include "X86MappingInsnName.inc"
|
||||||
@ -1216,7 +1216,7 @@ struct insn_reg2 {
|
|||||||
enum cs_ac_type access1, access2;
|
enum cs_ac_type access1, access2;
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct insn_reg insn_regs_att[] = {
|
static const struct insn_reg insn_regs_att[] = {
|
||||||
{ X86_INSB, X86_REG_DX, CS_AC_READ },
|
{ X86_INSB, X86_REG_DX, CS_AC_READ },
|
||||||
{ X86_INSL, X86_REG_DX, CS_AC_READ },
|
{ X86_INSL, X86_REG_DX, CS_AC_READ },
|
||||||
{ X86_INSW, X86_REG_DX, CS_AC_READ },
|
{ X86_INSW, X86_REG_DX, CS_AC_READ },
|
||||||
@ -1309,7 +1309,7 @@ static struct insn_reg insn_regs_att[] = {
|
|||||||
{ X86_XCHG64ar, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
|
{ X86_XCHG64ar, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct insn_reg insn_regs_att_extra[] = {
|
static const struct insn_reg insn_regs_att_extra[] = {
|
||||||
// dummy entry, to avoid empty array
|
// dummy entry, to avoid empty array
|
||||||
{ 0, 0 },
|
{ 0, 0 },
|
||||||
#ifndef CAPSTONE_X86_REDUCE
|
#ifndef CAPSTONE_X86_REDUCE
|
||||||
@ -1330,7 +1330,7 @@ static struct insn_reg insn_regs_att_extra[] = {
|
|||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct insn_reg insn_regs_intel[] = {
|
static const struct insn_reg insn_regs_intel[] = {
|
||||||
{ X86_ADC16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
|
{ X86_ADC16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
|
||||||
{ X86_ADC32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
|
{ X86_ADC32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
|
||||||
{ X86_ADC64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
|
{ X86_ADC64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
|
||||||
@ -1420,7 +1420,7 @@ static struct insn_reg insn_regs_intel[] = {
|
|||||||
{ X86_XOR8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ },
|
{ X86_XOR8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ },
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct insn_reg insn_regs_intel_extra[] = {
|
static const struct insn_reg insn_regs_intel_extra[] = {
|
||||||
// dummy entry, to avoid empty array
|
// dummy entry, to avoid empty array
|
||||||
{ 0, 0, 0 },
|
{ 0, 0, 0 },
|
||||||
#ifndef CAPSTONE_X86_REDUCE
|
#ifndef CAPSTONE_X86_REDUCE
|
||||||
@ -1446,7 +1446,7 @@ static struct insn_reg insn_regs_intel_extra[] = {
|
|||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct insn_reg2 insn_regs_intel2[] = {
|
static const struct insn_reg2 insn_regs_intel2[] = {
|
||||||
{ X86_IN16rr, X86_REG_AX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ },
|
{ X86_IN16rr, X86_REG_AX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ },
|
||||||
{ X86_IN32rr, X86_REG_EAX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ },
|
{ X86_IN32rr, X86_REG_EAX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ },
|
||||||
{ X86_IN8rr, X86_REG_AL, X86_REG_DX, CS_AC_WRITE, CS_AC_READ },
|
{ X86_IN8rr, X86_REG_AL, X86_REG_DX, CS_AC_WRITE, CS_AC_READ },
|
||||||
@ -1457,7 +1457,7 @@ static struct insn_reg2 insn_regs_intel2[] = {
|
|||||||
{ X86_OUT8rr, X86_REG_DX, X86_REG_AL, CS_AC_READ, CS_AC_READ },
|
{ X86_OUT8rr, X86_REG_DX, X86_REG_AL, CS_AC_READ, CS_AC_READ },
|
||||||
};
|
};
|
||||||
|
|
||||||
static int binary_search1(struct insn_reg *insns, unsigned int max, unsigned int id)
|
static int binary_search1(const struct insn_reg *insns, unsigned int max, unsigned int id)
|
||||||
{
|
{
|
||||||
unsigned int first, last, mid;
|
unsigned int first, last, mid;
|
||||||
|
|
||||||
@ -1486,7 +1486,7 @@ static int binary_search1(struct insn_reg *insns, unsigned int max, unsigned int
|
|||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int binary_search2(struct insn_reg2 *insns, unsigned int max, unsigned int id)
|
static int binary_search2(const struct insn_reg2 *insns, unsigned int max, unsigned int id)
|
||||||
{
|
{
|
||||||
unsigned int first, last, mid;
|
unsigned int first, last, mid;
|
||||||
|
|
||||||
@ -2042,7 +2042,7 @@ typedef struct insn_op {
|
|||||||
uint8_t access[6];
|
uint8_t access[6];
|
||||||
} insn_op;
|
} insn_op;
|
||||||
|
|
||||||
static insn_op insn_ops[] = {
|
static const insn_op insn_ops[] = {
|
||||||
#ifdef CAPSTONE_X86_REDUCE
|
#ifdef CAPSTONE_X86_REDUCE
|
||||||
#include "X86MappingInsnOp_reduce.inc"
|
#include "X86MappingInsnOp_reduce.inc"
|
||||||
#else
|
#else
|
||||||
@ -2051,7 +2051,7 @@ static insn_op insn_ops[] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
// given internal insn id, return operand access info
|
// given internal insn id, return operand access info
|
||||||
uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags)
|
const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags)
|
||||||
{
|
{
|
||||||
unsigned int i = find_insn(id);
|
unsigned int i = find_insn(id);
|
||||||
if (i != -1) {
|
if (i != -1) {
|
||||||
@ -2117,7 +2117,7 @@ void X86_reg_access(const cs_insn *insn,
|
|||||||
|
|
||||||
// map immediate size to instruction id
|
// map immediate size to instruction id
|
||||||
// this array is sorted for binary searching
|
// this array is sorted for binary searching
|
||||||
static struct size_id {
|
static const struct size_id {
|
||||||
uint8_t enc_size;
|
uint8_t enc_size;
|
||||||
uint8_t size;
|
uint8_t size;
|
||||||
uint16_t id;
|
uint16_t id;
|
||||||
@ -2165,7 +2165,7 @@ uint8_t X86_immediate_size(unsigned int id, uint8_t *enc_size)
|
|||||||
#include "X86GenRegisterInfo.inc"
|
#include "X86GenRegisterInfo.inc"
|
||||||
|
|
||||||
// map internal register id to public register id
|
// map internal register id to public register id
|
||||||
static struct register_map {
|
static const struct register_map {
|
||||||
unsigned short id;
|
unsigned short id;
|
||||||
unsigned short pub_id;
|
unsigned short pub_id;
|
||||||
} reg_map [] = {
|
} reg_map [] = {
|
||||||
|
|||||||
@ -78,7 +78,7 @@ void op_addAvxSae(MCInst *MI);
|
|||||||
void op_addAvxRoundingMode(MCInst *MI, int v);
|
void op_addAvxRoundingMode(MCInst *MI, int v);
|
||||||
|
|
||||||
// given internal insn id, return operand access info
|
// given internal insn id, return operand access info
|
||||||
uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags);
|
const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags);
|
||||||
|
|
||||||
void X86_reg_access(const cs_insn *insn,
|
void X86_reg_access(const cs_insn *insn,
|
||||||
cs_regs regs_read, uint8_t *regs_read_count,
|
cs_regs regs_read, uint8_t *regs_read_count,
|
||||||
|
|||||||
@ -62,7 +62,7 @@ static const uint16_t XCoreSubRegIdxLists[] = {
|
|||||||
/* 0 */ 0,
|
/* 0 */ 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MCRegisterDesc XCoreRegDesc[] = { // Descriptors
|
static const MCRegisterDesc XCoreRegDesc[] = { // Descriptors
|
||||||
{ 3, 0, 0, 0, 0, 0 },
|
{ 3, 0, 0, 0, 0, 0 },
|
||||||
{ 38, 1, 1, 0, 1, 0 },
|
{ 38, 1, 1, 0, 1, 0 },
|
||||||
{ 41, 1, 1, 0, 1, 0 },
|
{ 41, 1, 1, 0, 1, 0 },
|
||||||
@ -102,7 +102,7 @@ static MCRegisterDesc XCoreRegDesc[] = { // Descriptors
|
|||||||
0xe0, 0xff, 0x01,
|
0xe0, 0xff, 0x01,
|
||||||
};
|
};
|
||||||
|
|
||||||
static MCRegisterClass XCoreMCRegisterClasses[] = {
|
static const MCRegisterClass XCoreMCRegisterClasses[] = {
|
||||||
{ RRegs, RRegsBits, sizeof(RRegsBits) },
|
{ RRegs, RRegsBits, sizeof(RRegsBits) },
|
||||||
{ GRRegs, GRRegsBits, sizeof(GRRegsBits) },
|
{ GRRegs, GRRegsBits, sizeof(GRRegsBits) },
|
||||||
};
|
};
|
||||||
|
|||||||
@ -1,6 +1,7 @@
|
|||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
#include <stdlib.h>
|
#include <stdlib.h>
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
/* This code is used to build the static lookup table used inside the M68KDisassembler.c code
|
/* This code is used to build the static lookup table used inside the M68KDisassembler.c code
|
||||||
* To run this use the Makefile in the same directory
|
* To run this use the Makefile in the same directory
|
||||||
@ -422,7 +423,7 @@ static void build_opcode_table(void)
|
|||||||
qsort((void *)g_opcode_info, opcode_info_length, sizeof(g_opcode_info[0]), compare_nof_true_bits);
|
qsort((void *)g_opcode_info, opcode_info_length, sizeof(g_opcode_info[0]), compare_nof_true_bits);
|
||||||
|
|
||||||
printf("/* This table is auto-generated. DO NOT MANUALLY EDIT! Look in M68KInstructionTblGen.c for more info */\n");
|
printf("/* This table is auto-generated. DO NOT MANUALLY EDIT! Look in M68KInstructionTblGen.c for more info */\n");
|
||||||
printf("static instruction_struct g_instruction_table[] = {\n");
|
printf("static const instruction_struct g_instruction_table[] = {\n");
|
||||||
|
|
||||||
for(i=0;i<0x10000;i++) {
|
for(i=0;i<0x10000;i++) {
|
||||||
const char *name = "d68000_invalid";
|
const char *name = "d68000_invalid";
|
||||||
|
|||||||
4
cs.c
4
cs.c
@ -69,7 +69,7 @@
|
|||||||
#include "arch/MOS65XX/MOS65XXModule.h"
|
#include "arch/MOS65XX/MOS65XXModule.h"
|
||||||
#include "arch/BPF/BPFModule.h"
|
#include "arch/BPF/BPFModule.h"
|
||||||
|
|
||||||
static struct {
|
static const struct {
|
||||||
// constructor initialization
|
// constructor initialization
|
||||||
cs_err (*arch_init)(cs_struct *);
|
cs_err (*arch_init)(cs_struct *);
|
||||||
// support cs_option()
|
// support cs_option()
|
||||||
@ -234,7 +234,7 @@ static struct {
|
|||||||
};
|
};
|
||||||
|
|
||||||
// bitmask of enabled architectures
|
// bitmask of enabled architectures
|
||||||
static uint32_t all_arch = 0
|
static const uint32_t all_arch = 0
|
||||||
#ifdef CAPSTONE_HAS_ARM
|
#ifdef CAPSTONE_HAS_ARM
|
||||||
| (1 << CS_ARCH_ARM)
|
| (1 << CS_ARCH_ARM)
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@ -134,8 +134,7 @@ for line in lines:
|
|||||||
line = line.rstrip()
|
line = line.rstrip()
|
||||||
|
|
||||||
if 'static const MCOperandInfo ' in line:
|
if 'static const MCOperandInfo ' in line:
|
||||||
line2 = line.replace('static const MCOperandInfo ', 'static MCOperandInfo ')
|
line2 = line.replace('::', '_')
|
||||||
line2 = line2.replace('::', '_')
|
|
||||||
print(line2)
|
print(line2)
|
||||||
|
|
||||||
elif 'Insts[] = {' in line:
|
elif 'Insts[] = {' in line:
|
||||||
|
|||||||
@ -215,7 +215,7 @@ for line in lines:
|
|||||||
|
|
||||||
if arch + 'RegDesc' in line:
|
if arch + 'RegDesc' in line:
|
||||||
finding_struct = False
|
finding_struct = False
|
||||||
print("static MCRegisterDesc " + arch + "RegDesc[] = {")
|
print("static const MCRegisterDesc " + arch + "RegDesc[] = {")
|
||||||
continue
|
continue
|
||||||
|
|
||||||
if finding_struct:
|
if finding_struct:
|
||||||
@ -266,11 +266,7 @@ for line in lines:
|
|||||||
|
|
||||||
if 'MCRegisterClass ' + arch + 'MCRegisterClasses[] = {' in line:
|
if 'MCRegisterClass ' + arch + 'MCRegisterClasses[] = {' in line:
|
||||||
finding_struct = False
|
finding_struct = False
|
||||||
if arch.upper() == 'ARM':
|
print("static const MCRegisterClass " + arch + "MCRegisterClasses[] = {")
|
||||||
print("static MCRegisterClass " + arch + "MCRegisterClasses[] = {")
|
|
||||||
else:
|
|
||||||
print("static MCRegisterClass " + arch + "MCRegisterClasses[] = {")
|
|
||||||
#print("static MCRegisterClass2 " + arch + "MCRegisterClasses[] = {")
|
|
||||||
continue
|
continue
|
||||||
|
|
||||||
if finding_struct:
|
if finding_struct:
|
||||||
@ -285,10 +281,6 @@ for line in lines:
|
|||||||
|
|
||||||
# { GR8, GR8Bits, 130, 20, sizeof(GR8Bits), X86_GR8RegClassID, 1, 1, 1, 1 },
|
# { GR8, GR8Bits, 130, 20, sizeof(GR8Bits), X86_GR8RegClassID, 1, 1, 1, 1 },
|
||||||
tmp = line.split(',')
|
tmp = line.split(',')
|
||||||
if arch.upper() == 'ARM':
|
|
||||||
print(" %s, %s, %s }," %(tmp[0].strip(), tmp[1].strip(), tmp[4].strip()))
|
print(" %s, %s, %s }," %(tmp[0].strip(), tmp[1].strip(), tmp[4].strip()))
|
||||||
else: # AArch64
|
|
||||||
print(" %s, %s, %s }," %(tmp[0].strip(), tmp[1].strip(), tmp[4].strip()))
|
|
||||||
#print(" %s, %s, %s, %s }," %(tmp[0].strip(), tmp[1].strip(), tmp[3].strip(), tmp[4].strip()))
|
|
||||||
|
|
||||||
print("#endif // GET_REGINFO_MC_DESC")
|
print("#endif // GET_REGINFO_MC_DESC")
|
||||||
|
|||||||
@ -62,7 +62,7 @@ for line in lines:
|
|||||||
|
|
||||||
if 'MClassSysRegsList[]' in line:
|
if 'MClassSysRegsList[]' in line:
|
||||||
count += 1
|
count += 1
|
||||||
print('static MClassSysReg MClassSysRegsList[] = {')
|
print('static const MClassSysReg MClassSysRegsList[] = {')
|
||||||
continue
|
continue
|
||||||
|
|
||||||
if count == 1:
|
if count == 1:
|
||||||
@ -89,7 +89,7 @@ for line in lines:
|
|||||||
|
|
||||||
if 'BankedRegsList[]' in line:
|
if 'BankedRegsList[]' in line:
|
||||||
count += 1
|
count += 1
|
||||||
print('static BankedReg BankedRegsList[] = {')
|
print('static const BankedReg BankedRegsList[] = {')
|
||||||
continue
|
continue
|
||||||
|
|
||||||
if count == 1:
|
if count == 1:
|
||||||
@ -115,7 +115,7 @@ for line in lines:
|
|||||||
|
|
||||||
if 'lookupMClassSysRegByM2M3Encoding8' in line and '{' in line:
|
if 'lookupMClassSysRegByM2M3Encoding8' in line and '{' in line:
|
||||||
count += 1
|
count += 1
|
||||||
print('MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)\n{')
|
print('const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)\n{')
|
||||||
print(' unsigned int i;')
|
print(' unsigned int i;')
|
||||||
continue
|
continue
|
||||||
|
|
||||||
@ -151,7 +151,7 @@ for line in lines:
|
|||||||
|
|
||||||
if 'lookupMClassSysRegByM1Encoding12' in line and '{' in line:
|
if 'lookupMClassSysRegByM1Encoding12' in line and '{' in line:
|
||||||
count += 1
|
count += 1
|
||||||
print('MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)\n{')
|
print('const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)\n{')
|
||||||
print(' unsigned int i;')
|
print(' unsigned int i;')
|
||||||
continue
|
continue
|
||||||
|
|
||||||
@ -186,7 +186,7 @@ for line in lines:
|
|||||||
|
|
||||||
if 'lookupBankedRegByEncoding' in line and '{' in line:
|
if 'lookupBankedRegByEncoding' in line and '{' in line:
|
||||||
count += 1
|
count += 1
|
||||||
print('BankedReg *lookupBankedRegByEncoding(uint8_t encoding)\n{')
|
print('const BankedReg *lookupBankedRegByEncoding(uint8_t encoding)\n{')
|
||||||
print(' unsigned int i;')
|
print(' unsigned int i;')
|
||||||
continue
|
continue
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user