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mips: optimize Mips_map_register() to O(1). suggested by Pancake

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Nguyen Anh Quynh 2013-12-11 23:20:34 +08:00
parent 2b4258997f
commit ad89d25d05
4 changed files with 79 additions and 134 deletions
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199
arch/Mips/mapping.c
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@ -1954,139 +1954,74 @@ mips_reg Mips_map_register(unsigned int r)
// for some reasons different Mips modes can map different register number to
// the same Mips register. this function handles the issue for exposing Mips
// operands by mapping internal registers to 'public' register.
static struct reg_map {
unsigned int reg; // 'public' register that we will map to
unsigned int raw[8]; // array of internal registers mapped to 'public' register
} reg_maps[] = {
{ MIPS_REG_0, { 12, 31, 123, 0 } }, { MIPS_REG_ZERO, { 21, 254, 0 }},
{ MIPS_REG_1, { 1, 11, 30, 32, 124, 0 }},
{ MIPS_REG_2, { 10, 33, 125, 220, 315, 0 }},
{ MIPS_REG_3, { 16, 34, 126, 221, 316, 0 }},
{ MIPS_REG_4, { 14, 22, 35, 127, 255, 0 }},
{ MIPS_REG_5, { 15, 23, 36, 128, 256, 0 }},
{ MIPS_REG_6, { 13, 24, 37, 129, 257, 0 }},
{ MIPS_REG_7, { 17, 25, 38, 130, 258, 0 }},
{ MIPS_REG_8, { 39, 131, 210, 305, 0 }},
{ MIPS_REG_9, { 40, 132, 211, 306, 0 }},
{ MIPS_REG_10, { 41, 133, 212, 307, 0 }},
{ MIPS_REG_11, { 42, 134, 213, 308, 0 }},
{ MIPS_REG_12, { 43, 135, 214, 309, 0 }},
{ MIPS_REG_13, { 44, 136, 215, 310, 0 }},
{ MIPS_REG_14, { 45, 137, 216, 311, 0 }},
{ MIPS_REG_15, { 46, 138, 217, 312, 0 }},
{ MIPS_REG_16, { 47, 139, 201, 297, 0 }},
{ MIPS_REG_17, { 48, 140, 202, 298, 0 }},
{ MIPS_REG_18, { 49, 141, 203, 299, 0 }},
{ MIPS_REG_19, { 50, 142, 204, 300, 0 }},
{ MIPS_REG_20, { 51, 143, 205, 301, 0 }},
{ MIPS_REG_21, { 52, 144, 206, 302, 0 }},
{ MIPS_REG_22, { 53, 145, 207, 303, 0 }},
{ MIPS_REG_23, { 54, 146, 208, 304, 0 }},
{ MIPS_REG_24, { 55, 147, 218, 313, 0 }},
{ MIPS_REG_25, { 56, 148, 219, 314, 0 }},
{ MIPS_REG_26, { 57, 149, 194, 294, 0 }},
{ MIPS_REG_27, { 58, 150, 195, 295, 0 }},
{ MIPS_REG_28, { 59, 151, 0 }}, { MIPS_REG_GP, { 9, 188, 0 }},
{ MIPS_REG_29, { 60, 152, 193, 0 }}, { MIPS_REG_SP, { 20, 209, 0 }},
{ MIPS_REG_30, { 61, 153, 0 }}, { MIPS_REG_FP, { 8, 155, 0 }},
{ MIPS_REG_31, { 62, 154, 0 }}, { MIPS_REG_RA, { 19, 200, 0 }},
{ MIPS_REG_AC0, { 26, 189, 196, 259, 0 }},
{ MIPS_REG_AC1, { 27, 190, 197, 0 }},
{ MIPS_REG_AC2, { 28, 191, 198, 0 }},
{ MIPS_REG_AC3, { 29, 192, 199, 0 }},
{ MIPS_REG_F0, { 63, 83, 156, 260, 0 }},
{ MIPS_REG_F1, { 84, 157, 261, 0 }},
{ MIPS_REG_F2, { 64, 85, 158, 262, 0 }},
{ MIPS_REG_F3, { 86, 159, 263, 0 }},
{ MIPS_REG_F4, { 65, 87, 160, 264, 0 }},
{ MIPS_REG_F5, { 88, 161, 265, 0 }},
{ MIPS_REG_F6, { 66, 89, 162, 266, 0 }},
{ MIPS_REG_F7, { 90, 163, 267, 0 }},
{ MIPS_REG_F8, { 67, 91, 164, 268, 0 }},
{ MIPS_REG_F9, { 92, 165, 269, 0 }},
{ MIPS_REG_F10, { 68, 93, 166, 270, 0 }},
{ MIPS_REG_F11, { 94, 167, 271, 0 }},
{ MIPS_REG_F12, { 69, 95, 168, 272, 0 }},
{ MIPS_REG_F13, { 96, 169, 273, 0 }},
{ MIPS_REG_F14, { 70, 97, 170, 274, 0 }},
{ MIPS_REG_F15, { 98, 171, 275, 0 }},
{ MIPS_REG_F16, { 71, 99, 172, 276, 0 }},
{ MIPS_REG_F17, { 100, 173, 277, 0 }},
{ MIPS_REG_F18, { 72, 101, 174, 278, 0 }},
{ MIPS_REG_F19, { 102, 175, 279, 0 }},
{ MIPS_REG_F20, { 73, 103, 176, 280, 0 }},
{ MIPS_REG_F21, { 104, 177, 281, 0 }},
{ MIPS_REG_F22, { 74, 105, 178, 282, 0 }},
{ MIPS_REG_F23, { 106, 179, 283, 0 }},
{ MIPS_REG_F24, { 75, 107, 180, 284, 0 }},
{ MIPS_REG_F25, { 108, 181, 285, 0 }},
{ MIPS_REG_F26, { 76, 109, 182, 286, 0 }},
{ MIPS_REG_F27, { 110, 183, 287, 0 }},
{ MIPS_REG_F28, { 77, 111, 184, 288, 0 }},
{ MIPS_REG_F29, { 112, 185, 289, 0 }},
{ MIPS_REG_F30, { 78, 113, 186, 290, 0 }},
{ MIPS_REG_F31, { 114, 187, 291, 0 }},
unsigned int map[] = { 0,
MIPS_REG_1, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG,
MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2,
MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5,
MIPS_REG_3, MIPS_REG_7, MIPS_REG_PC, MIPS_REG_RA, MIPS_REG_SP,
MIPS_REG_ZERO, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7,
MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_1,
MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, MIPS_REG_3, MIPS_REG_4,
MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, MIPS_REG_8, MIPS_REG_9,
MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14,
MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19,
MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24,
MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29,
MIPS_REG_30, MIPS_REG_31, MIPS_REG_F0, MIPS_REG_F2, MIPS_REG_F4,
MIPS_REG_F6, MIPS_REG_F8, MIPS_REG_F10, MIPS_REG_F12, MIPS_REG_F14,
MIPS_REG_F16, MIPS_REG_F18, MIPS_REG_F20, MIPS_REG_F22, MIPS_REG_F24,
MIPS_REG_F26, MIPS_REG_F28, MIPS_REG_F30, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21,
MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2,
MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7,
MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12,
MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17,
MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22,
MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27,
MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0,
MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5,
MIPS_REG_FCC6, MIPS_REG_FCC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2,
MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7,
MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12,
MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17,
MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22,
MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27,
MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_FP,
MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4,
MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9,
MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14,
MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19,
MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24,
MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29,
MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_GP, MIPS_REG_AC0, MIPS_REG_AC1,
MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_29, MIPS_REG_26, MIPS_REG_27,
MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_RA,
MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20,
MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_SP, MIPS_REG_8,
MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13,
MIPS_REG_14, MIPS_REG_15, MIPS_REG_24, MIPS_REG_25, MIPS_REG_2,
MIPS_REG_3, MIPS_REG_W0, MIPS_REG_W1, MIPS_REG_W2, MIPS_REG_W3,
MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6, MIPS_REG_W7, MIPS_REG_W8,
MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11, MIPS_REG_W12, MIPS_REG_W13,
MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16, MIPS_REG_W17, MIPS_REG_W18,
MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21, MIPS_REG_W22, MIPS_REG_W23,
MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26, MIPS_REG_W27, MIPS_REG_W28,
MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31, MIPS_REG_ZERO, MIPS_REG_4,
MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, MIPS_REG_AC0, MIPS_REG_F0,
MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5,
MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10,
MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15,
MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20,
MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25,
MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30,
MIPS_REG_F31, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_HI, MIPS_REG_26, MIPS_REG_27,
MIPS_REG_LO, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19,
MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_8,
MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13,
MIPS_REG_14, MIPS_REG_15, MIPS_REG_24, MIPS_REG_25, MIPS_REG_2,
MIPS_REG_3 };
{ MIPS_REG_W0, { 222, 0 }},
{ MIPS_REG_W1, { 223, 0 }},
{ MIPS_REG_W2, { 224, 0 }},
{ MIPS_REG_W3, { 225, 0 }},
{ MIPS_REG_W4, { 226, 0 }},
{ MIPS_REG_W5, { 227, 0 }},
{ MIPS_REG_W6, { 228, 0 }},
{ MIPS_REG_W7, { 229, 0 }},
{ MIPS_REG_W8, { 230, 0 }},
{ MIPS_REG_W9, { 231, 0 }},
{ MIPS_REG_W10, { 232, 0 }},
{ MIPS_REG_W11, { 233, 0 }},
{ MIPS_REG_W12, { 234, 0 }},
{ MIPS_REG_W13, { 235, 0 }},
{ MIPS_REG_W14, { 236, 0 }},
{ MIPS_REG_W15, { 237, 0 }},
{ MIPS_REG_W16, { 238, 0 }},
{ MIPS_REG_W17, { 239, 0 }},
{ MIPS_REG_W18, { 240, 0 }},
{ MIPS_REG_W19, { 241, 0 }},
{ MIPS_REG_W20, { 242, 0 }},
{ MIPS_REG_W21, { 243, 0 }},
{ MIPS_REG_W22, { 244, 0 }},
{ MIPS_REG_W23, { 245, 0 }},
{ MIPS_REG_W24, { 246, 0 }},
{ MIPS_REG_W25, { 247, 0 }},
{ MIPS_REG_W26, { 248, 0 }},
{ MIPS_REG_W27, { 249, 0 }},
{ MIPS_REG_W28, { 250, 0 }},
{ MIPS_REG_W29, { 251, 0 }},
{ MIPS_REG_W30, { 252, 0 }},
{ MIPS_REG_W31, { 253, 0 }},
{ MIPS_REG_FCC0, { 115, 0 }},
{ MIPS_REG_FCC1, { 116, 0 }},
{ MIPS_REG_FCC2, { 117, 0 }},
{ MIPS_REG_FCC3, { 118, 0 }},
{ MIPS_REG_FCC4, { 119, 0 }},
{ MIPS_REG_FCC5, { 120, 0 }},
{ MIPS_REG_FCC6, { 121, 0 }},
{ MIPS_REG_FCC7, { 122, 0 }},
{ MIPS_REG_DSPCCOND, { 2, 0 }},
{ MIPS_REG_DSPCARRY, { 3, 0 }},
{ MIPS_REG_DSPEFI, { 4, 0 }},
{ MIPS_REG_DSPOUTFLAG, { 5, 0 }},
{ MIPS_REG_DSPOUTFLAG16_19, { 292, 0 }},
{ MIPS_REG_DSPOUTFLAG20, { 79, 0 }},
{ MIPS_REG_DSPOUTFLAG21, { 80, 0 }},
{ MIPS_REG_DSPOUTFLAG22, { 81, 0 }},
{ MIPS_REG_DSPOUTFLAG23, { 82, 0 }},
{ MIPS_REG_DSPPOS, { 6, 0 }},
{ MIPS_REG_DSPSCOUNT, { 7, 0 }},
};
unsigned int i, j;
for (i = 0; i < ARR_SIZE(reg_maps); i++) {
for (j = 0; reg_maps[i].raw[j] != 0; j++)
if (reg_maps[i].raw[j] == r)
return reg_maps[i].reg;
}
if (r < ARR_SIZE(map))
return map[r];
// cannot find this register
return 0;

5
bindings/java/capstone/Mips_const.java
View File

@ -130,7 +130,10 @@ public class Mips_const {
public static final int MIPS_REG_W29 = 117;
public static final int MIPS_REG_W30 = 118;
public static final int MIPS_REG_W31 = 119;
public static final int MIPS_REG_MAX = 120;
public static final int MIPS_REG_HI = 120;
public static final int MIPS_REG_LO = 121;
public static final int MIPS_REG_PC = 122;
public static final int MIPS_REG_MAX = 123;
public static final int MIPS_REG_ZERO = MIPS_REG_0;
public static final int MIPS_REG_AT = MIPS_REG_1;
public static final int MIPS_REG_V0 = MIPS_REG_2;

5
bindings/python/capstone/mips_const.py
View File

@ -127,7 +127,10 @@ MIPS_REG_W28 = 116
MIPS_REG_W29 = 117
MIPS_REG_W30 = 118
MIPS_REG_W31 = 119
MIPS_REG_MAX = 120
MIPS_REG_HI = 120
MIPS_REG_LO = 121
MIPS_REG_PC = 122
MIPS_REG_MAX = 123
MIPS_REG_ZERO = MIPS_REG_0
MIPS_REG_AT = MIPS_REG_1
MIPS_REG_V0 = MIPS_REG_2

4
include/mips.h
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@ -177,6 +177,10 @@ typedef enum mips_reg {
MIPS_REG_W30,
MIPS_REG_W31,
MIPS_REG_HI,
MIPS_REG_LO,
MIPS_REG_PC,
MIPS_REG_MAX, // <-- mark the end of the list or registers
// alias registers