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Merge branch 'next' of https://github.com/aquynh/capstone into next

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This commit is contained in:
Nguyen Anh Quynh 2014-11-14 10:11:39 +08:00
commit b0ee0c9c4e
78 changed files with 173 additions and 159 deletions
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21
arch/Mips/MipsDisassembler.c
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@ -227,17 +227,19 @@ static uint64_t getFeatureBits(int mode)
} else if (mode & CS_MODE_32) {
Bits &= ~Mips_FeatureMips16;
Bits &= ~Mips_FeatureFP64Bit;
Bits &= ~Mips_FeatureMips64r2;
Bits &= ~Mips_FeatureMips32r6;
Bits &= ~Mips_FeatureMips64r6;
} else if (mode & CS_MODE_64) {
Bits &= ~Mips_FeatureMips16;
Bits &= ~Mips_FeatureMips64r6;
Bits &= ~Mips_FeatureMips64r6;
Bits &= ~Mips_FeatureMips32r6;
}
if (mode & CS_MODE_MIPS32R6) {
} else if (mode & CS_MODE_MIPS32R6) {
Bits |= Mips_FeatureMips32r6;
Bits &= ~Mips_FeatureMips16;
Bits &= ~Mips_FeatureFP64Bit;
Bits &= ~Mips_FeatureMips64r6;
Bits &= ~Mips_FeatureMips64r2;
}
if (mode & CS_MODE_MICRO) {
@ -346,6 +348,8 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
return MCDisassembler_Fail;
}
#if 0
// TODO: properly handle this in the future with MIPS1/2 modes
if (((mode & CS_MODE_32) == 0) && ((mode & CS_MODE_MIPS3) == 0)) { // COP3
// DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode);
@ -354,6 +358,7 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
return Result;
}
}
#endif
if (((mode & CS_MODE_MIPS32R6) != 0) && ((mode & CS_MODE_MIPSGP64) != 0)) {
// DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
@ -1215,8 +1220,8 @@ static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
static DecodeStatus DecodeBranchTarget(MCInst *Inst,
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
{
int32_t BranchOffset = (SignExtend32(Offset, 16) * 4) + 4;
MCOperand_CreateImm0(Inst, BranchOffset);
uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4;
MCOperand_CreateImm0(Inst, TargetAddress);
return MCDisassembler_Success;
}
@ -1224,8 +1229,8 @@ static DecodeStatus DecodeBranchTarget(MCInst *Inst,
static DecodeStatus DecodeJumpTarget(MCInst *Inst,
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
{
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
MCOperand_CreateImm0(Inst, JumpOffset);
uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF);
MCOperand_CreateImm0(Inst, TargetAddress);
return MCDisassembler_Success;
}

3
arch/Mips/MipsGenDisassemblerTables.inc
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@ -24,6 +24,8 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
return (insn & fieldMask) >> startBit; \
}
#if 0
// TODO: properly handle this in the future with MIPS1/2 modes
static uint8_t DecoderTableCOP3_32[] = {
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
/* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15
@ -41,6 +43,7 @@ static uint8_t DecoderTableCOP3_32[] = {
/* 51 */ MCD_OPC_Fail,
0
};
#endif
static uint8_t DecoderTableMicroMips32[] = {
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...

25
arch/Mips/MipsInstPrinter.c
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@ -180,27 +180,6 @@ void Mips_printInst(MCInst *MI, SStream *O, void *info)
}
}
// check to see if @id is opcode of a relative branch instruction
static bool relativeBranch(unsigned int id)
{
static unsigned int branchIns[] = {
Mips_BEQ, Mips_BC1F, Mips_BGEZ, Mips_BGEZAL, Mips_BGTZ,
Mips_BLEZ, Mips_BLTZ, Mips_BLTZAL, Mips_BNE, Mips_BC1T,
Mips_BEQL, Mips_BGEZALL, Mips_BGEZL, Mips_BGTZL, Mips_BLEZL,
Mips_BLTZALL, Mips_BLTZL, Mips_BNEL, Mips_BC1F, Mips_BC1FL,
Mips_BC1TL, Mips_BC0F,
};
int i;
for(i = 0; i < ARR_SIZE(branchIns); i++) {
if (id == branchIns[i])
return true;
}
// not found
return false;
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
@ -236,10 +215,6 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
if (MI->csh->detail)
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
} else {
if (relativeBranch(MI->Opcode)) {
imm += MI->address;
}
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);

2
arch/Mips/MipsModule.c
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@ -30,7 +30,7 @@ static cs_err init(cs_struct *ud)
ud->insn_name = Mips_insn_name;
ud->group_name = Mips_group_name;
if (ud->mode & CS_MODE_32)
if (ud->mode & CS_MODE_32 || ud->mode & CS_MODE_MIPS32R6)
ud->disasm = Mips_getInstruction;
else
ud->disasm = Mips64_getInstruction;

4
bindings/java/Test.java
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@ -98,13 +98,13 @@ public class Test {
),
new platform(
Capstone.CS_ARCH_MIPS,
Capstone.CS_MODE_32 + Capstone.CS_MODE_BIG_ENDIAN,
Capstone.CS_MODE_MIPS32 + Capstone.CS_MODE_BIG_ENDIAN,
new byte[] {(byte)0x0C, (byte)0x10, (byte)0x00, (byte)0x97, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x24, (byte)0x02, (byte)0x00, (byte)0x0c, (byte)0x8f, (byte)0xa2, (byte)0x00, (byte)0x00, (byte)0x34, (byte)0x21, (byte)0x34, (byte)0x56 },
"MIPS-32 (Big-endian)"
),
new platform(
Capstone.CS_ARCH_MIPS,
Capstone.CS_MODE_64+ Capstone.CS_MODE_LITTLE_ENDIAN,
Capstone.CS_MODE_MIPS64+ Capstone.CS_MODE_LITTLE_ENDIAN,
new byte[] {(byte)0x56, (byte)0x34, (byte)0x21, (byte)0x34, (byte)0xc2, (byte)0x17, (byte)0x01, (byte)0x00 },
"MIPS-64-EL (Little-endian)"
),

4
bindings/java/TestMips.java
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@ -61,8 +61,8 @@ public class TestMips {
public static void main(String argv[]) {
final Test.platform[] all_tests = {
new Test.platform(Capstone.CS_ARCH_MIPS, Capstone.CS_MODE_32 + Capstone.CS_MODE_BIG_ENDIAN, hexString2Byte(MIPS_CODE), "MIPS-32 (Big-endian)"),
new Test.platform(Capstone.CS_ARCH_MIPS, Capstone.CS_MODE_64 + Capstone.CS_MODE_LITTLE_ENDIAN, hexString2Byte(MIPS_CODE2), "MIPS-64-EL (Little-endian)"),
new Test.platform(Capstone.CS_ARCH_MIPS, Capstone.CS_MODE_MIPS32 + Capstone.CS_MODE_BIG_ENDIAN, hexString2Byte(MIPS_CODE), "MIPS-32 (Big-endian)"),
new Test.platform(Capstone.CS_ARCH_MIPS, Capstone.CS_MODE_MIPS64 + Capstone.CS_MODE_LITTLE_ENDIAN, hexString2Byte(MIPS_CODE2), "MIPS-64-EL (Little-endian)"),
};
for (int i=0; i<all_tests.length; i++) {

3
bindings/java/capstone/Arm_const.java
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@ -72,6 +72,7 @@ public class Arm_const {
public static final int ARM_SYSREG_CONTROL = 278;
// The memory barrier constants map directly to the 4-bit encoding of
// the option field for Memory Barrier operations.
public static final int ARM_MB_INVALID = 0;
@ -766,4 +767,4 @@ public class Arm_const {
public static final int ARM_GRP_DPVFP = 157;
public static final int ARM_GRP_V6M = 158;
public static final int ARM_GRP_ENDING = 159;
}
}

12
bindings/java/capstone/Capstone.java
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@ -289,11 +289,11 @@ public class Capstone {
public static final int CS_ARCH_ALL = 0xFFFF; // query id for cs_support()
// disasm mode
public static final int CS_MODE_LITTLE_ENDIAN = 0; // default mode
public static final int CS_MODE_LITTLE_ENDIAN = 0; // little-endian mode (default mode)
public static final int CS_MODE_ARM = 0; // 32-bit ARM
public static final int CS_MODE_16 = 1 << 1;
public static final int CS_MODE_32 = 1 << 2;
public static final int CS_MODE_64 = 1 << 3;
public static final int CS_MODE_16 = 1 << 1; // 16-bit mode for X86
public static final int CS_MODE_32 = 1 << 2; // 32-bit mode for X86
public static final int CS_MODE_64 = 1 << 3; // 64-bit mode for X86, PPC
public static final int CS_MODE_THUMB = 1 << 4; // ARM's Thumb mode, including Thumb-2
public static final int CS_MODE_MCLASS = 1 << 5; // ARM's Cortex-M series
public static final int CS_MODE_V8 = 1 << 6; // ARMv8 A32 encodings for ARM
@ -301,8 +301,10 @@ public class Capstone {
public static final int CS_MODE_MIPS3 = 1 << 5; // Mips III ISA
public static final int CS_MODE_MIPS32R6 = 1 << 6; // Mips32r6 ISA
public static final int CS_MODE_MIPSGP64 = 1 << 7; // General Purpose Registers are 64-bit wide (MIPS arch)
public static final int CS_MODE_BIG_ENDIAN = 1 << 31;
public static final int CS_MODE_BIG_ENDIAN = 1 << 31; // big-endian mode
public static final int CS_MODE_V9 = 1 << 4; // SparcV9 mode (Sparc arch)
public static final int CS_MODE_MIPS32 = CS_MODE_32; // Mips32 ISA
public static final int CS_MODE_MIPS64 = CS_MODE_64; // Mips64 ISA
// Capstone error
public static final int CS_ERR_OK = 0;

8
bindings/ocaml/capstone.ml
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@ -26,9 +26,9 @@ type arch =
type mode =
| CS_MODE_LITTLE_ENDIAN (* little-endian mode (default mode) *)
| CS_MODE_ARM (* ARM mode *)
| CS_MODE_16 (* 16-bit mode (for X86, Mips) *)
| CS_MODE_32 (* 32-bit mode (for X86, Mips) *)
| CS_MODE_64 (* 64-bit mode (for X86, Mips) *)
| CS_MODE_16 (* 16-bit mode (for X86) *)
| CS_MODE_32 (* 32-bit mode (for X86) *)
| CS_MODE_64 (* 64-bit mode (for X86, PPC) *)
| CS_MODE_THUMB (* ARM's Thumb mode, including Thumb-2 *)
| CS_MODE_MCLASS (* ARM's MClass mode *)
| CS_MODE_V8 (* ARMv8 A32 encodings for ARM *)
@ -38,6 +38,8 @@ type mode =
| CS_MODE_MIPSGP64 (* MipsGP64 mode (MIPS architecture) *)
| CS_MODE_V9 (* SparcV9 mode (Sparc architecture) *)
| CS_MODE_BIG_ENDIAN (* big-endian mode *)
| CS_MODE_MIPS32 (* Mips32 mode (for Mips) *)
| CS_MODE_MIPS64 (* Mips64 mode (for Mips) *)
(* Runtime option for the disassembled engine *)

12
bindings/ocaml/ocaml.c
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@ -706,6 +706,12 @@ CAMLprim value ocaml_cs_disasm(value _arch, value _mode, value _code, value _add
case 13:
mode |= CS_MODE_BIG_ENDIAN;
break;
case 14:
mode |= CS_MODE_MIPS32;
break;
case 15:
mode |= CS_MODE_MIPS64;
break;
default:
caml_invalid_argument("Invalid mode");
return Val_emptylist;
@ -831,6 +837,12 @@ CAMLprim value ocaml_open(value _arch, value _mode)
case 13:
mode |= CS_MODE_BIG_ENDIAN;
break;
case 14:
mode |= CS_MODE_MIPS32;
break;
case 15:
mode |= CS_MODE_MIPS64;
break;
default:
caml_invalid_argument("Invalid mode");
return Val_emptylist;

4
bindings/ocaml/test.ml
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@ -31,8 +31,8 @@ let all_tests = [
(CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE, "THUMB", 0L);
(CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE2, "THUMB-2", 0L);
(CS_ARCH_ARM64, [CS_MODE_ARM], _ARM64_CODE, "ARM-64", 0L);
(CS_ARCH_MIPS, [CS_MODE_32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)", 0L);
(CS_ARCH_MIPS, [CS_MODE_64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0L);
(CS_ARCH_MIPS, [CS_MODE_MIPS32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)", 0L);
(CS_ARCH_MIPS, [CS_MODE_MIPS64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0L);
(CS_ARCH_PPC, [CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64", 0L);
(CS_ARCH_PPC, [CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64, print register with number only", 0L);
(CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN], _SPARC_CODE, "Sparc", 0L);

6
bindings/ocaml/test_detail.ml
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@ -31,9 +31,9 @@ let all_tests = [
(CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE, "THUMB", 0);
(CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE2, "THUMB-2", 0);
(CS_ARCH_ARM64, [CS_MODE_ARM], _ARM64_CODE, "ARM-64", 0);
(CS_ARCH_MIPS, [CS_MODE_32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)", 0);
(CS_ARCH_MIPS, [CS_MODE_64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0);
(CS_ARCH_PPC, [CS_MODE_32; CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64", 0);
(CS_ARCH_MIPS, [CS_MODE_MIPS32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)", 0);
(CS_ARCH_MIPS, [CS_MODE_MIPS64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0);
(CS_ARCH_PPC, [CS_MODE_64; CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64", 0);
(CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN], _SPARC_CODE, "Sparc", 0);
(CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN; CS_MODE_V9], _SPARCV9_CODE, "SparcV9", 0);
(CS_ARCH_SYSZ, [CS_MODE_LITTLE_ENDIAN], _SYSZ_CODE, "SystemZ", 0);

4
bindings/ocaml/test_mips.ml
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@ -18,8 +18,8 @@ let _MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\
let _MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00";;
let all_tests = [
(CS_ARCH_MIPS, [CS_MODE_32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)");
(CS_ARCH_MIPS, [CS_MODE_64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)");
(CS_ARCH_MIPS, [CS_MODE_MIPS32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)");
(CS_ARCH_MIPS, [CS_MODE_MIPS64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)");
];;
let print_op handle i op =

2
bindings/ocaml/test_ppc.ml
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@ -17,7 +17,7 @@ let print_string_hex comment str =
let _PPC_CODE = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21";;
let all_tests = [
(CS_ARCH_PPC, [CS_MODE_32; CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64");
(CS_ARCH_PPC, [CS_MODE_64; CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64");
];;
let print_op handle i op =

12
bindings/python/capstone/__init__.py
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@ -43,6 +43,8 @@ __all__ = [
'CS_MODE_MIPSGP64',
'CS_MODE_V8',
'CS_MODE_V9',
'CS_MODE_MIPS32',
'CS_MODE_MIPS64',
'CS_OPT_SYNTAX',
'CS_OPT_SYNTAX_DEFAULT',
@ -98,9 +100,9 @@ CS_ARCH_ALL = 0xFFFF
# disasm mode
CS_MODE_LITTLE_ENDIAN = 0 # little-endian mode (default mode)
CS_MODE_ARM = 0 # ARM mode
CS_MODE_16 = (1 << 1) # 16-bit mode (for X86, Mips)
CS_MODE_32 = (1 << 2) # 32-bit mode (for X86, Mips)
CS_MODE_64 = (1 << 3) # 64-bit mode (for X86, Mips)
CS_MODE_16 = (1 << 1) # 16-bit mode (for X86)
CS_MODE_32 = (1 << 2) # 32-bit mode (for X86)
CS_MODE_64 = (1 << 3) # 64-bit mode (for X86, PPC)
CS_MODE_THUMB = (1 << 4) # ARM's Thumb mode, including Thumb-2
CS_MODE_MCLASS = (1 << 5) # ARM's Cortex-M series
CS_MODE_V8 = (1 << 6) # ARMv8 A32 encodings for ARM
@ -108,8 +110,10 @@ CS_MODE_MICRO = (1 << 4) # MicroMips mode (MIPS architecture)
CS_MODE_MIPS3 = (1 << 5) # Mips III ISA
CS_MODE_MIPS32R6 = (1 << 6) # Mips32r6 ISA
CS_MODE_MIPSGP64 = (1 << 7) # General Purpose Registers are 64-bit wide (MIPS arch)
CS_MODE_V9 = (1 << 4) # Nintendo-64 mode (MIPS architecture)
CS_MODE_V9 = (1 << 4) # Sparc V9 mode (for Sparc)
CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode
CS_MODE_MIPS32 = CS_MODE_32 # Mips32 ISA
CS_MODE_MIPS64 = CS_MODE_64 # Mips64 ISA
# Capstone option type
CS_OPT_SYNTAX = 1 # Intel X86 asm syntax (CS_ARCH_X86 arch)

8
bindings/python/test.py
View File

@ -42,10 +42,10 @@ all_tests = (
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", 0),
(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", 0),
(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", 0),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", 0),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),

8
bindings/python/test_detail.py
View File

@ -37,10 +37,10 @@ all_tests = (
(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", 0),
(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", 0),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", 0),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", 0),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", 0),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", 0),

4
bindings/python/test_lite.py
View File

@ -28,8 +28,8 @@ all_tests = (
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", 0),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", 0),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", 0),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),

8
bindings/python/test_mips.py
View File

@ -13,10 +13,10 @@ MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
all_tests = (
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"),
(CS_ARCH_MIPS, CS_MODE_64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)"),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)"),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)"),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)"),
)

18
include/capstone.h
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@ -73,20 +73,22 @@ typedef enum cs_arch {
// Mode type
typedef enum cs_mode {
CS_MODE_LITTLE_ENDIAN = 0, // little endian mode (default mode)
CS_MODE_LITTLE_ENDIAN = 0, // little-endian mode (default mode)
CS_MODE_ARM = 0, // 32-bit ARM
CS_MODE_16 = 1 << 1, // 16-bit mode
CS_MODE_32 = 1 << 2, // 32-bit mode. Also use for MIPS32 ISA
CS_MODE_64 = 1 << 3, // 64-bit mode. Also use for MIPS64 ISA
CS_MODE_16 = 1 << 1, // 16-bit mode (X86)
CS_MODE_32 = 1 << 2, // 32-bit mode (X86)
CS_MODE_64 = 1 << 3, // 64-bit mode (X86, PPC)
CS_MODE_THUMB = 1 << 4, // ARM's Thumb mode, including Thumb-2
CS_MODE_MCLASS = 1 << 5, // ARM's Cortex-M series
CS_MODE_V8 = 1 << 6, // ARMv8 A32 encodings for ARM
CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS architecture)
CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS)
CS_MODE_MIPS3 = 1 << 5, // Mips III ISA
CS_MODE_MIPS32R6 = 1 << 6, // Mips32r6 ISA
CS_MODE_MIPSGP64 = 1 << 7, // General Purpose Registers are 64-bit wide (MIPS arch)
CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc architecture)
CS_MODE_BIG_ENDIAN = 1 << 31 // big endian mode
CS_MODE_MIPSGP64 = 1 << 7, // General Purpose Registers are 64-bit wide (MIPS)
CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc)
CS_MODE_BIG_ENDIAN = 1 << 31, // big-endian mode
CS_MODE_MIPS32 = CS_MODE_32, // Mips32 ISA (Mips)
CS_MODE_MIPS64 = CS_MODE_64, // Mips64 ISA (Mips)
} cs_mode;
typedef void* (*cs_malloc_t)(size_t size);

2
suite/MC/Mips/hilo-addressing.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x3c,0x04,0xde,0xae = lui $4, %hi(addr)
0x03,0xe0,0x00,0x08 = jr $31
0x80,0x82,0xbe,0xef = lb $2, %lo(addr)($4)

2
suite/MC/Mips/micromips-alu-instructions-EB.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO, None
0x00,0xe6,0x49,0x10 = add $9, $6, $7
0x11,0x26,0x45,0x67 = addi $9, $6, 17767
0x31,0x26,0xc5,0x67 = addiu $9, $6, -15001

2
suite/MC/Mips/micromips-alu-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0xe6,0x00,0x10,0x49 = add $9, $6, $7
0x26,0x11,0x67,0x45 = addi $9, $6, 17767
0x26,0x31,0x67,0xc5 = addiu $9, $6, -15001

2
suite/MC/Mips/micromips-branch-instructions-EB.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x94,0x00,0x02,0x9a = b 1332
0x94,0xc9,0x02,0x9a = beq $9, $6, 1332
0x40,0x46,0x02,0x9a = bgez $6, 1332

2
suite/MC/Mips/micromips-branch-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0x00,0x94,0x9a,0x02 = b 1332
0xc9,0x94,0x9a,0x02 = beq $9, $6, 1332
0x46,0x40,0x9a,0x02 = bgez $6, 1332

2
suite/MC/Mips/micromips-expansions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0xa0,0x50,0x7b,0x00 = ori $5, $zero, 123
0xc0,0x30,0xd7,0xf6 = addiu $6, $zero, -2345
0xa7,0x41,0x01,0x00 = lui $7, 1

2
suite/MC/Mips/micromips-jump-instructions-EB.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0xd4,0x00,0x02,0x98 = j 1328
0xf4,0x00,0x02,0x98 = jal 1328
0x03,0xe6,0x0f,0x3c = jalr $6

2
suite/MC/Mips/micromips-jump-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0x00,0xd4,0x98,0x02 = j 1328
0x00,0xf4,0x98,0x02 = jal 1328
0xe6,0x03,0x3c,0x0f = jalr $6

2
suite/MC/Mips/micromips-loadstore-instructions-EB.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x1c,0xa4,0x00,0x08 = lb $5, 8($4)
0x14,0xc4,0x00,0x08 = lbu $6, 8($4)
0x3c,0x44,0x00,0x08 = lh $2, 8($4)

2
suite/MC/Mips/micromips-loadstore-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0xa4,0x1c,0x08,0x00 = lb $5, 8($4)
0xc4,0x14,0x08,0x00 = lbu $6, 8($4)
0x44,0x3c,0x08,0x00 = lh $2, 8($4)

2
suite/MC/Mips/micromips-loadstore-unaligned-EB.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x60,0x85,0x00,0x10 = lwl $4, 16($5)
0x60,0x85,0x10,0x10 = lwr $4, 16($5)
0x60,0x85,0x80,0x10 = swl $4, 16($5)

2
suite/MC/Mips/micromips-loadstore-unaligned.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0x85,0x60,0x10,0x00 = lwl $4, 16($5)
0x85,0x60,0x10,0x10 = lwr $4, 16($5)
0x85,0x60,0x10,0x80 = swl $4, 16($5)

2
suite/MC/Mips/micromips-movcond-instructions-EB.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x00,0xe6,0x48,0x58 = movz $9, $6, $7
0x00,0xe6,0x48,0x18 = movn $9, $6, $7
0x55,0x26,0x09,0x7b = movt $9, $6, $fcc0

2
suite/MC/Mips/micromips-movcond-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0xe6,0x00,0x58,0x48 = movz $9, $6, $7
0xe6,0x00,0x18,0x48 = movn $9, $6, $7
0x26,0x55,0x7b,0x09 = movt $9, $6, $fcc0

2
suite/MC/Mips/micromips-multiply-instructions-EB.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x00,0xa4,0xcb,0x3c = madd $4, $5
0x00,0xa4,0xdb,0x3c = maddu $4, $5
0x00,0xa4,0xeb,0x3c = msub $4, $5

2
suite/MC/Mips/micromips-multiply-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0xa4,0x00,0x3c,0xcb = madd $4, $5
0xa4,0x00,0x3c,0xdb = maddu $4, $5
0xa4,0x00,0x3c,0xeb = msub $4, $5

2
suite/MC/Mips/micromips-shift-instructions-EB.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x00,0x83,0x38,0x00 = sll $4, $3, 7
0x00,0x65,0x10,0x10 = sllv $2, $3, $5
0x00,0x83,0x38,0x80 = sra $4, $3, 7

2
suite/MC/Mips/micromips-shift-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0x83,0x00,0x00,0x38 = sll $4, $3, 7
0x65,0x00,0x10,0x10 = sllv $2, $3, $5
0x83,0x00,0x80,0x38 = sra $4, $3, 7

2
suite/MC/Mips/micromips-trap-instructions-EB.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x01,0x28,0x00,0x3c = teq $8, $9
0x01,0x28,0x02,0x3c = tge $8, $9
0x01,0x28,0x04,0x3c = tgeu $8, $9

2
suite/MC/Mips/micromips-trap-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0x28,0x01,0x3c,0x00 = teq $8, $9
0x28,0x01,0x3c,0x02 = tge $8, $9
0x28,0x01,0x3c,0x04 = tgeu $8, $9

2
suite/MC/Mips/mips-alu-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32, None
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x24,0x48,0xc7,0x00 = and $9, $6, $7
0x67,0x45,0xc9,0x30 = andi $9, $6, 17767
0x67,0x45,0xc9,0x30 = andi $9, $6, 17767

2
suite/MC/Mips/mips-control-instructions-64.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_64+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
0x00,0x00,0x00,0x0d = break
0x00,0x07,0x00,0x0d = break 7, 0
0x00,0x07,0x01,0x4d = break 7, 5

2
suite/MC/Mips/mips-control-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x00,0x00,0x00,0x0d = break
0x00,0x07,0x00,0x0d = break 7, 0
0x00,0x07,0x01,0x4d = break 7, 5

2
suite/MC/Mips/mips-coprocessor-encodings.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_64+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
0x40,0xac,0x80,0x02 = dmtc0 $12, $16, 2
0x40,0xac,0x80,0x00 = dmtc0 $12, $16, 0
0x40,0x8c,0x80,0x02 = mtc0 $12, $16, 2

2
suite/MC/Mips/mips-dsp-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7e,0x32,0x83,0x11 = precrq.qb.ph $16, $17, $18
0x7e,0x53,0x8d,0x11 = precrq.ph.w $17, $18, $19
0x7e,0x74,0x95,0x51 = precrq_rs.ph.w $18, $19, $20

2
suite/MC/Mips/mips-expansions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32, None
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x7b,0x00,0x05,0x34 = ori $5, $zero, 123
0xd7,0xf6,0x06,0x24 = addiu $6, $zero, -2345
0x01,0x00,0x07,0x3c = lui $7, 1

2
suite/MC/Mips/mips-fpu-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32, None
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x05,0x73,0x20,0x46 = abs.d $f12, $f14
0x85,0x39,0x00,0x46 = abs.s $f6, $f7
0x00,0x62,0x2e,0x46 = add.d $f8, $f12, $f14

2
suite/MC/Mips/mips-jump-instructions.s.cs
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@ -1 +1 @@
# CS_ARCH_MIPS, CS_MODE_32, None
# CS_ARCH_MIPS, CS_MODE_MIPS32, None

2
suite/MC/Mips/mips-memory-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32, None
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x10,0x00,0xa4,0xa0 = sb $4, 16($5)
0x10,0x00,0xa4,0xe0 = sc $4, 16($5)
0x10,0x00,0xa4,0xa4 = sh $4, 16($5)

2
suite/MC/Mips/mips-register-names.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x24,0x00,0x00,0x00 = addiu $zero, $zero, 0
0x24,0x01,0x00,0x00 = addiu $at, $zero, 0
0x24,0x02,0x00,0x00 = addiu $v0, $zero, 0

2
suite/MC/Mips/mips64-alu-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_64, None
# CS_ARCH_MIPS, CS_MODE_MIPS64, None
0x24,0x48,0xc7,0x00 = and $9, $6, $7
0x67,0x45,0xc9,0x30 = andi $9, $6, 17767
0x67,0x45,0xc9,0x30 = andi $9, $6, 17767

2
suite/MC/Mips/mips64-instructions.s.cs
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@ -1,3 +1,3 @@
# CS_ARCH_MIPS, CS_MODE_64, None
# CS_ARCH_MIPS, CS_MODE_MIPS64, None
0x81,0x00,0x42,0x4d = ldxc1 $f2, $2($10)
0x09,0x40,0x24,0x4f = sdxc1 $f8, $4($25)

2
suite/MC/Mips/mips64-register-names.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_64+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
0x64,0x00,0x00,0x00 = daddiu $zero, $zero, 0
0x64,0x01,0x00,0x00 = daddiu $at, $zero, 0
0x64,0x02,0x00,0x00 = daddiu $v0, $zero, 0

2
suite/MC/Mips/mips_directives.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x10,0x00,0x01,0x4d = b 1332
0x08,0x00,0x01,0x4c = j 1328
0x0c,0x00,0x01,0x4c = jal 1328

2
suite/MC/Mips/nabi-regs.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_64+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
0x02,0x04,0x80,0x20 = add $16, $16, $4
0x02,0x06,0x80,0x20 = add $16, $16, $6
0x02,0x07,0x80,0x20 = add $16, $16, $7

2
suite/MC/Mips/set-at-directive.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32, None
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x08,0x00,0x60,0x00 = jr $3
0x08,0x00,0x80,0x03 = jr $gp
0x08,0x00,0xc0,0x03 = jr $fp

2
suite/MC/Mips/test_2r.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7b,0x00,0x4f,0x9e = fill.b $w30, $9
0x7b,0x01,0xbf,0xde = fill.h $w31, $23
0x7b,0x02,0xc4,0x1e = fill.w $w16, $24

2
suite/MC/Mips/test_2rf.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7b,0x20,0x66,0x9e = fclass.w $w26, $w12
0x7b,0x21,0x8e,0x1e = fclass.d $w24, $w17
0x7b,0x30,0x02,0x1e = fexupl.w $w8, $w0

2
suite/MC/Mips/test_3r.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x04,0x4e,0x90 = add_a.b $w26, $w9, $w4
0x78,0x3f,0xdd,0xd0 = add_a.h $w23, $w27, $w31
0x78,0x56,0x32,0xd0 = add_a.w $w11, $w6, $w22

2
suite/MC/Mips/test_3rf.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x1c,0x9f,0x1b = fadd.w $w28, $w19, $w28
0x78,0x3d,0x13,0x5b = fadd.d $w13, $w2, $w29
0x78,0x19,0x5b,0x9a = fcaf.w $w14, $w11, $w25

2
suite/MC/Mips/test_bit.s.cs
View File

@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x79,0xf2,0xf5,0x49 = bclri.b $w21, $w30, 2
0x79,0xe0,0xae,0x09 = bclri.h $w24, $w21, 0
0x79,0xc3,0xf5,0xc9 = bclri.w $w23, $w30, 3

2
suite/MC/Mips/test_cbranch.s.cs
View File

@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x47,0x80,0x00,0x01 = bnz.b $w0, 4
0x47,0xa1,0x00,0x04 = bnz.h $w1, 16
0x47,0xc2,0x00,0x20 = bnz.w $w2, 128

2
suite/MC/Mips/test_ctrlregs.s.cs
View File

@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x7e,0x00,0x59 = cfcmsa $1, $0
0x78,0x7e,0x00,0x59 = cfcmsa $1, $0
0x78,0x7e,0x08,0x99 = cfcmsa $2, $1

2
suite/MC/Mips/test_elm.s.cs
View File

@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x82,0x43,0x59 = copy_s.b $13, $w8[2]
0x78,0xa0,0xc8,0x59 = copy_s.h $1, $w25[0]
0x78,0xb1,0x2d,0x99 = copy_s.w $22, $w5[1]

2
suite/MC/Mips/test_elm_insert.s.cs
View File

@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x79,0x03,0xed,0xd9 = insert.b $w23[3], $sp
0x79,0x22,0x2d,0x19 = insert.h $w20[2], $5
0x79,0x32,0x7a,0x19 = insert.w $w8[2], $15

2
suite/MC/Mips/test_elm_insve.s.cs
View File

@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x79,0x43,0x4e,0x59 = insve.b $w25[3], $w9[0]
0x79,0x62,0x16,0x19 = insve.h $w24[2], $w2[0]
0x79,0x72,0x68,0x19 = insve.w $w0[2], $w13[0]

2
suite/MC/Mips/test_i10.s.cs
View File

@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7b,0x06,0x32,0x07 = ldi.b $w8, 198
0x7b,0x29,0xcd,0x07 = ldi.h $w20, 313
0x7b,0x4f,0x66,0x07 = ldi.w $w24, 492

2
suite/MC/Mips/test_i5.s.cs
View File

@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x1e,0xf8,0xc6 = addvi.b $w3, $w31, 30
0x78,0x3a,0x6e,0x06 = addvi.h $w24, $w13, 26
0x78,0x5a,0xa6,0x86 = addvi.w $w26, $w20, 26

2
suite/MC/Mips/test_i8.s.cs
View File

@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x30,0xe8,0x80 = andi.b $w2, $w29, 48
0x78,0x7e,0xb1,0x81 = bmnzi.b $w6, $w22, 126
0x79,0x58,0x0e,0xc1 = bmzi.b $w27, $w1, 88

2
suite/MC/Mips/test_lsa.s.cs
View File

@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x01,0x2a,0x40,0x05 = lsa $8, $9, $10, 1
0x01,0x2a,0x40,0x45 = lsa $8, $9, $10, 2
0x01,0x2a,0x40,0x85 = lsa $8, $9, $10, 3

2
suite/MC/Mips/test_mi10.s.cs
View File

@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7a,0x00,0x08,0x20 = ld.b $w0, -512($1)
0x78,0x00,0x10,0x60 = ld.b $w1, 0($2)
0x79,0xff,0x18,0xa0 = ld.b $w2, 511($3)

2
suite/MC/Mips/test_vec.s.cs
View File

@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x1b,0xa6,0x5e = and.v $w25, $w20, $w27
0x78,0x87,0x34,0x5e = bmnz.v $w17, $w6, $w7
0x78,0xa9,0x88,0xde = bmz.v $w3, $w17, $w9

4
suite/test_c.sh
View File

@ -5,9 +5,13 @@
../tests/test > /tmp/$1
../tests/test_detail >> /tmp/$1
../tests/test_skipdata >> /tmp/$1
../tests/test_iter >> /tmp/$1
../tests/test_arm >> /tmp/$1
../tests/test_arm64 >> /tmp/$1
../tests/test_mips >> /tmp/$1
../tests/test_ppc >> /tmp/$1
../tests/test_sparc >> /tmp/$1
../tests/test_x86 >> /tmp/$1
../tests/test_systemz >> /tmp/$1
../tests/test_xcore >> /tmp/$1

28
suite/test_mc.py
View File

@ -97,6 +97,8 @@ def test_file(fname):
"CS_MODE_16": CS_MODE_16,
"CS_MODE_32": CS_MODE_32,
"CS_MODE_64": CS_MODE_64,
"CS_MODE_MIPS32": CS_MODE_MIPS32,
"CS_MODE_MIPS64": CS_MODE_MIPS64,
"0": CS_MODE_ARM,
"CS_MODE_ARM": CS_MODE_ARM,
"CS_MODE_THUMB": CS_MODE_THUMB,
@ -105,14 +107,16 @@ def test_file(fname):
"CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS,
"CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN,
"CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN,
"CS_MODE_32+CS_MODE_BIG_ENDIAN": CS_MODE_32+CS_MODE_BIG_ENDIAN,
"CS_MODE_32+CS_MODE_LITTLE_ENDIAN": CS_MODE_32+CS_MODE_LITTLE_ENDIAN,
"CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN,
"CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64+CS_MODE_BIG_ENDIAN,
"CS_MODE_32+CS_MODE_MICRO": CS_MODE_32+CS_MODE_MICRO,
"CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
"CS_MODE_32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
"CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO,
"CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
"CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
"CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9,
"CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN,
"CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN,
"CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN,
"CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN,
}
options = {
@ -129,13 +133,13 @@ def test_file(fname):
("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): ['-triple=thumbv8'],
("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): ['-triple=thumbv7m'],
("CS_ARCH_ARM64", "0"): ['-triple=aarch64'],
("CS_ARCH_MIPS", "CS_MODE_32+CS_MODE_BIG_ENDIAN"): ['-triple=mips'],
("CS_ARCH_MIPS", "CS_MODE_32+CS_MODE_MICRO"): ['-triple=mipsel', '-mattr=+micromips'],
("CS_ARCH_MIPS", "CS_MODE_64"): ['-triple=mips64el'],
("CS_ARCH_MIPS", "CS_MODE_32"): ['-triple=mipsel'],
("CS_ARCH_MIPS", "CS_MODE_64+CS_MODE_BIG_ENDIAN"): ['-triple=mips64'],
("CS_ARCH_MIPS", "CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): ['-triple=mips', '-mattr=+micromips'],
("CS_ARCH_MIPS", "CS_MODE_32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): ['-triple=mips', '-mattr=+micromips'],
("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): ['-triple=mips'],
("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): ['-triple=mipsel', '-mattr=+micromips'],
("CS_ARCH_MIPS", "CS_MODE_MIPS64"): ['-triple=mips64el'],
("CS_ARCH_MIPS", "CS_MODE_MIPS32"): ['-triple=mipsel'],
("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): ['-triple=mips64'],
("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): ['-triple=mips', '-mattr=+micromips'],
("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): ['-triple=mips', '-mattr=+micromips'],
("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): ['-triple=powerpc64'],
('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN'): ['-triple=sparc'],
('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN+CS_MODE_V9'): ['-triple=sparcv9'],

8
tests/test.c
View File

@ -139,28 +139,28 @@ static void test()
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_32 + CS_MODE_BIG_ENDIAN),
(cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
(unsigned char*)MIPS_CODE,
sizeof(MIPS_CODE) - 1,
"MIPS-32 (Big-endian)"
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_64 + CS_MODE_LITTLE_ENDIAN),
(cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
(unsigned char*)MIPS_CODE2,
sizeof(MIPS_CODE2) - 1,
"MIPS-64-EL (Little-endian)"
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_32 + CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
(unsigned char*)MIPS_32R6M,
sizeof(MIPS_32R6M) - 1,
"MIPS-32R6 | Micro (Big-endian)"
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_32 + CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
(unsigned char*)MIPS_32R6,
sizeof(MIPS_32R6) - 1,
"MIPS-32R6 (Big-endian)"

8
tests/test_detail.c
View File

@ -139,28 +139,28 @@ static void test()
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_32 + CS_MODE_BIG_ENDIAN),
(cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
(unsigned char *)MIPS_CODE,
sizeof(MIPS_CODE) - 1,
"MIPS-32 (Big-endian)"
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_64 + CS_MODE_LITTLE_ENDIAN),
(cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
(unsigned char *)MIPS_CODE2,
sizeof(MIPS_CODE2) - 1,
"MIPS-64-EL (Little-endian)"
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_32 + CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
(unsigned char*)MIPS_32R6M,
sizeof(MIPS_32R6M) - 1,
"MIPS-32R6 | Micro (Big-endian)"
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_32 + CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
(unsigned char*)MIPS_32R6,
sizeof(MIPS_32R6) - 1,
"MIPS-32R6 (Big-endian)"

4
tests/test_iter.c
View File

@ -122,14 +122,14 @@ static void test()
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_32 + CS_MODE_BIG_ENDIAN),
(cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
(unsigned char *)MIPS_CODE,
sizeof(MIPS_CODE) - 1,
"MIPS-32 (Big-endian)"
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_64 + CS_MODE_LITTLE_ENDIAN),
(cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
(unsigned char *)MIPS_CODE2,
sizeof(MIPS_CODE2) - 1,
"MIPS-64-EL (Little-endian)"

8
tests/test_mips.c
View File

@ -86,28 +86,28 @@ static void test()
struct platform platforms[] = {
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_32 + CS_MODE_BIG_ENDIAN),
(cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
(unsigned char *)MIPS_CODE,
sizeof(MIPS_CODE) - 1,
"MIPS-32 (Big-endian)"
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_64 + CS_MODE_LITTLE_ENDIAN),
(cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
(unsigned char *)MIPS_CODE2,
sizeof(MIPS_CODE2) - 1,
"MIPS-64-EL (Little-endian)"
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_32 + CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
(unsigned char*)MIPS_32R6M,
sizeof(MIPS_32R6M) - 1,
"MIPS-32R6 | Micro (Big-endian)"
},
{
CS_ARCH_MIPS,
(cs_mode)(CS_MODE_32 + CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
(unsigned char*)MIPS_32R6,
sizeof(MIPS_32R6) - 1,
"MIPS-32R6 (Big-endian)"