From b87f855281ba9233d2564547522e480427667c50 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Sun, 2 Nov 2014 23:38:35 +0800 Subject: [PATCH] x86: print negative number in memory reference address (more friendly). issue reported by @pancake --- arch/X86/X86ATTInstPrinter.c | 29 ++++++++++++++++++------ arch/X86/X86IntelInstPrinter.c | 41 ++++++++++++++++++++++------------ suite/x86odd.py | 1 + 3 files changed, 50 insertions(+), 21 deletions(-) diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c index 8fd96ce04..445b7edd4 100644 --- a/arch/X86/X86ATTInstPrinter.c +++ b/arch/X86/X86ATTInstPrinter.c @@ -539,14 +539,29 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O) int64_t DispVal = MCOperand_getImm(DispSpec); if (MI->csh->detail) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal; - if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) { - if (DispVal < 0) { - SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); + if (DispVal) { + if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { + if (DispVal < 0) { + if (DispVal < -HEX_THRESHOLD) + SStream_concat(O, " -0x%"PRIx64, -DispVal); + else + SStream_concat(O, " -%"PRIu64, -DispVal); + } else { + if (DispVal > HEX_THRESHOLD) + SStream_concat(O, "0x%"PRIx64, DispVal); + else + SStream_concat(O, "%"PRIu64, DispVal); + } } else { - if (DispVal > HEX_THRESHOLD) - SStream_concat(O, "0x%"PRIx64, DispVal); - else - SStream_concat(O, "%"PRIu64, DispVal); + // only immediate as address of memory + if (DispVal < 0) { + SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); + } else { + if (DispVal > HEX_THRESHOLD) + SStream_concat(O, "0x%"PRIx64, DispVal); + else + SStream_concat(O, "%"PRIu64, DispVal); + } } } } diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c index db91e7491..d7cb1a3b5 100644 --- a/arch/X86/X86IntelInstPrinter.c +++ b/arch/X86/X86IntelInstPrinter.c @@ -617,26 +617,39 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O) NeedPlus = true; } - if (!MCOperand_isImm(DispSpec)) { - if (NeedPlus) - SStream_concat0(O, " + "); - } else { + if (MCOperand_isImm(DispSpec)) { int64_t DispVal = MCOperand_getImm(DispSpec); if (MI->csh->detail) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal; - if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) { + if (DispVal) { if (NeedPlus) { - SStream_concat0(O, " + "); + if (DispVal < 0) { + if (DispVal < -HEX_THRESHOLD) + SStream_concat(O, " - 0x%"PRIx64, -DispVal); + else + SStream_concat(O, " - %"PRIu64, -DispVal); + } else { + if (DispVal > HEX_THRESHOLD) + SStream_concat(O, " + 0x%"PRIx64, DispVal); + else + SStream_concat(O, " + %"PRIu64, DispVal); + } + } else { + // memory reference to an immediate address + if (DispVal < 0) { + SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); + } else { + if (DispVal > HEX_THRESHOLD) + SStream_concat(O, "0x%"PRIx64, DispVal); + else + SStream_concat(O, "%"PRIu64, DispVal); + } } - if (DispVal < 0) { - SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); - } else { - if (DispVal > HEX_THRESHOLD) - SStream_concat(O, "0x%"PRIx64, DispVal); - else - SStream_concat(O, "%"PRIu64, DispVal); - } + } else { + // DispVal = 0 + if (!NeedPlus) // [0] + SStream_concat0(O, "0"); } } diff --git a/suite/x86odd.py b/suite/x86odd.py index 861f21f54..fa19d0502 100755 --- a/suite/x86odd.py +++ b/suite/x86odd.py @@ -40,6 +40,7 @@ CODE32_MEMREF += b"\x8b\x04\x95\xdd\xfe\xff\xff" CODE32_MEMREF += b"\xa1\x23\x01\x00\x00" CODE32_MEMREF += b"\xa1\x00\x00\x00\x00" CODE32_MEMREF += b"\xa1\xdd\xfe\xff\xff" +CODE32_MEMREF += b"\x8b\x04\x91" _python3 = sys.version_info.major == 3