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x86: print negative number in memory reference address (more friendly). issue reported by @pancake

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This commit is contained in:
Nguyen Anh Quynh 2014-11-02 23:38:35 +08:00
parent c2d353c454
commit b87f855281
3 changed files with 50 additions and 21 deletions
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29
arch/X86/X86ATTInstPrinter.c
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@ -539,14 +539,29 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
int64_t DispVal = MCOperand_getImm(DispSpec); int64_t DispVal = MCOperand_getImm(DispSpec);
if (MI->csh->detail) if (MI->csh->detail)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal;
if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) { if (DispVal) {
if (DispVal < 0) { if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) {
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); if (DispVal < 0) {
if (DispVal < -HEX_THRESHOLD)
SStream_concat(O, " -0x%"PRIx64, -DispVal);
else
SStream_concat(O, " -%"PRIu64, -DispVal);
} else {
if (DispVal > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, DispVal);
else
SStream_concat(O, "%"PRIu64, DispVal);
}
} else { } else {
if (DispVal > HEX_THRESHOLD) // only immediate as address of memory
SStream_concat(O, "0x%"PRIx64, DispVal); if (DispVal < 0) {
else SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal);
SStream_concat(O, "%"PRIu64, DispVal); } else {
if (DispVal > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, DispVal);
else
SStream_concat(O, "%"PRIu64, DispVal);
}
} }
} }
} }

41
arch/X86/X86IntelInstPrinter.c
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@ -617,26 +617,39 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
NeedPlus = true; NeedPlus = true;
} }
if (!MCOperand_isImm(DispSpec)) { if (MCOperand_isImm(DispSpec)) {
if (NeedPlus)
SStream_concat0(O, " + ");
} else {
int64_t DispVal = MCOperand_getImm(DispSpec); int64_t DispVal = MCOperand_getImm(DispSpec);
if (MI->csh->detail) if (MI->csh->detail)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal;
if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) { if (DispVal) {
if (NeedPlus) { if (NeedPlus) {
SStream_concat0(O, " + "); if (DispVal < 0) {
if (DispVal < -HEX_THRESHOLD)
SStream_concat(O, " - 0x%"PRIx64, -DispVal);
else
SStream_concat(O, " - %"PRIu64, -DispVal);
} else {
if (DispVal > HEX_THRESHOLD)
SStream_concat(O, " + 0x%"PRIx64, DispVal);
else
SStream_concat(O, " + %"PRIu64, DispVal);
}
} else {
// memory reference to an immediate address
if (DispVal < 0) {
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal);
} else {
if (DispVal > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, DispVal);
else
SStream_concat(O, "%"PRIu64, DispVal);
}
} }
if (DispVal < 0) { } else {
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); // DispVal = 0
} else { if (!NeedPlus) // [0]
if (DispVal > HEX_THRESHOLD) SStream_concat0(O, "0");
SStream_concat(O, "0x%"PRIx64, DispVal);
else
SStream_concat(O, "%"PRIu64, DispVal);
}
} }
} }

1
suite/x86odd.py
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@ -40,6 +40,7 @@ CODE32_MEMREF += b"\x8b\x04\x95\xdd\xfe\xff\xff"
CODE32_MEMREF += b"\xa1\x23\x01\x00\x00" CODE32_MEMREF += b"\xa1\x23\x01\x00\x00"
CODE32_MEMREF += b"\xa1\x00\x00\x00\x00" CODE32_MEMREF += b"\xa1\x00\x00\x00\x00"
CODE32_MEMREF += b"\xa1\xdd\xfe\xff\xff" CODE32_MEMREF += b"\xa1\xdd\xfe\xff\xff"
CODE32_MEMREF += b"\x8b\x04\x91"
_python3 = sys.version_info.major == 3 _python3 = sys.version_info.major == 3