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systemz & xcore: create details only when detail mode is ON. this fixes some crashes in tests/test

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Nguyen Anh Quynh 2014-06-09 18:49:37 +07:00
parent 69582d71ae
commit b95647d2c1
2 changed files with 50 additions and 30 deletions
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32
arch/SystemZ/SystemZInstPrinter.c
View File

@ -59,15 +59,19 @@ static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index
SStream_concat(O, "%%%s, ", getRegisterName(Index)); SStream_concat(O, "%%%s, ", getRegisterName(Index));
SStream_concat(O, "%%%s)", getRegisterName(Base)); SStream_concat(O, "%%%s)", getRegisterName(Base));
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; if (MI->csh->detail) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index); MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index);
MI->flat_insn->detail->sysz.op_count++; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp;
MI->flat_insn->detail->sysz.op_count++;
}
} else if (!Index) { } else if (!Index) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; if (MI->csh->detail) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.op_count++; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp;
MI->flat_insn->detail->sysz.op_count++;
}
} }
} }
@ -349,11 +353,13 @@ static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O)
SStream_concat(O, ", %%%s", getRegisterName(Base)); SStream_concat(O, ", %%%s", getRegisterName(Base));
SStream_concat(O, ")"); SStream_concat(O, ")");
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; if (MI->csh->detail) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = Length; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = Length;
MI->flat_insn->detail->sysz.op_count++; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp;
MI->flat_insn->detail->sysz.op_count++;
}
} }
static void printCond4Operand(MCInst *MI, int OpNum, SStream *O) static void printCond4Operand(MCInst *MI, int OpNum, SStream *O)

48
arch/XCore/XCoreInstPrinter.c
View File

@ -67,9 +67,11 @@ void XCore_insn_extract(MCInst *MI, const char *code)
id = XCore_reg_id(p); id = XCore_reg_id(p);
if (id) { if (id) {
// register // register
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
MI->flat_insn->detail->xcore.op_count++; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
MI->flat_insn->detail->xcore.op_count++;
}
} }
// next should be register, or memory? // next should be register, or memory?
// skip space // skip space
@ -87,11 +89,13 @@ void XCore_insn_extract(MCInst *MI, const char *code)
id = XCore_reg_id(p2); id = XCore_reg_id(p2);
if (id) { if (id) {
// base register // base register
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = id; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = id;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
}
p++; p++;
p2 = p; p2 = p;
@ -104,23 +108,31 @@ void XCore_insn_extract(MCInst *MI, const char *code)
id = XCore_reg_id(p2); id = XCore_reg_id(p2);
if (id) { if (id) {
// index register // index register
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = id; if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = id;
}
} else { } else {
// a number means disp // a number means disp
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = atoi(p2); if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = atoi(p2);
}
} }
} }
MI->flat_insn->detail->xcore.op_count++; if (MI->csh->detail) {
MI->flat_insn->detail->xcore.op_count++;
}
} }
} else { } else {
// a register? // a register?
id = XCore_reg_id(p2); id = XCore_reg_id(p2);
if (id) { if (id) {
// register // register
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
MI->flat_insn->detail->xcore.op_count++; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
MI->flat_insn->detail->xcore.op_count++;
}
} }
} }
} }
@ -128,9 +140,11 @@ void XCore_insn_extract(MCInst *MI, const char *code)
id = XCore_reg_id(p); id = XCore_reg_id(p);
if (id) { if (id) {
// register // register
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
MI->flat_insn->detail->xcore.op_count++; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
MI->flat_insn->detail->xcore.op_count++;
}
} }
} }
} }