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Merge pull request #2007 from peace-maker/riscv_insn_groups

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RISCV: Add call, int and branch_relative instruction groups
This commit is contained in:
Wu ChenXu 2023-06-10 20:08:47 +08:00 committed by GitHub
commit b98189dce9
7 changed files with 90 additions and 16 deletions
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9
arch/RISCV/RISCVMapping.c
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@ -190,8 +190,15 @@ const char *RISCV_insn_name(csh handle, unsigned int id)
#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
// generic groups
{ RISCV_GRP_INVALID, NULL },
{ RISCV_GRP_JUMP, "jump" },
{ RISCV_GRP_CALL, "call" },
{ RISCV_GRP_RET, "ret" },
{ RISCV_GRP_INT, "int" },
{ RISCV_GRP_IRET, "iret" },
{ RISCV_GRP_PRIVILEGE, "privileged" },
{ RISCV_GRP_BRANCH_RELATIVE, "branch_relative" },
// architecture specific
{ RISCV_GRP_ISRV32, "isrv32" },
@ -226,7 +233,7 @@ const char *RISCV_group_name(csh handle, unsigned int id)
#ifndef CAPSTONE_DIET
// verify group id
if (id >= RISCV_GRP_ENDING ||
(id > RISCV_GRP_JUMP && id < RISCV_GRP_ISRV32))
(id > RISCV_GRP_BRANCH_RELATIVE && id < RISCV_GRP_ISRV32))
return NULL;
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else

26
arch/RISCV/RISCVMappingInsn.inc
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@ -478,37 +478,37 @@
{
RISCV_BEQ, RISCV_INS_BEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 1, 0
{ 0 }, { 0 }, { RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
RISCV_BGE, RISCV_INS_BGE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 1, 0
{ 0 }, { 0 }, { RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
RISCV_BGEU, RISCV_INS_BGEU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 1, 0
{ 0 }, { 0 }, { RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
RISCV_BLT, RISCV_INS_BLT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 1, 0
{ 0 }, { 0 }, { RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
RISCV_BLTU, RISCV_INS_BLTU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 1, 0
{ 0 }, { 0 }, { RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
RISCV_BNE, RISCV_INS_BNE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 1, 0
{ 0 }, { 0 }, { RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
@ -598,13 +598,13 @@
{
RISCV_C_BEQZ, RISCV_INS_C_BEQZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 1, 0
{ 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
RISCV_C_BNEZ, RISCV_INS_C_BNEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 1, 0
{ 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
@ -670,13 +670,13 @@
{
RISCV_C_JAL, RISCV_INS_C_JAL,
#ifndef CAPSTONE_DIET
{ 0 }, { RISCV_REG_X1, 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV32, 0 }, 0, 0
{ 0 }, { RISCV_REG_X1, 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV32, RISCV_GRP_CALL, 0 }, 0, 0
#endif
},
{
RISCV_C_JALR, RISCV_INS_C_JALR,
#ifndef CAPSTONE_DIET
{ 0 }, { RISCV_REG_X1, 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0
{ 0 }, { RISCV_REG_X1, 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_CALL, 0 }, 0, 0
#endif
},
{
@ -838,7 +838,7 @@
{
RISCV_ECALL, RISCV_INS_ECALL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
{ 0 }, { 0 }, { RISCV_GRP_INT, 0 }, 0, 0
#endif
},
{
@ -1234,13 +1234,13 @@
{
RISCV_JAL, RISCV_INS_JAL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
{ 0 }, { 0 }, { RISCV_GRP_CALL, 0 }, 0, 0
#endif
},
{
RISCV_JALR, RISCV_INS_JALR,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
{ 0 }, { 0 }, { RISCV_GRP_CALL, 0 }, 0, 0
#endif
},
{

6
bindings/python/capstone/riscv_const.py
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@ -426,6 +426,12 @@ RISCV_INS_ENDING = 273
RISCV_GRP_INVALID = 0
RISCV_GRP_JUMP = 1
RISCV_GRP_CALL = 2
RISCV_GRP_RET = 3
RISCV_GRP_INT = 4
RISCV_GRP_IRET = 5
RISCV_GRP_PRIVILEGE = 6
RISCV_GRP_BRANCH_RELATIVE = 7
RISCV_GRP_ISRV32 = 128
RISCV_GRP_ISRV64 = 129
RISCV_GRP_HASSTDEXTA = 130

20
include/capstone/riscv.h
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@ -479,9 +479,25 @@ typedef enum riscv_insn {
//> Group of RISCV instructions
typedef enum riscv_insn_group {
RISCV_GRP_INVALID = 0, // = CS_GRP_INVALID
RISCV_GRP_JUMP,
RISCV_GRP_INVALID = 0, ///< = CS_GRP_INVALID
// Generic groups
// all jump instructions (conditional+direct+indirect jumps)
RISCV_GRP_JUMP, ///< = CS_GRP_JUMP
// all call instructions
RISCV_GRP_CALL, ///< = CS_GRP_CALL
// all return instructions
RISCV_GRP_RET, ///< = CS_GRP_RET
// all interrupt instructions (int+syscall)
RISCV_GRP_INT, ///< = CS_GRP_INT
// all interrupt return instructions
RISCV_GRP_IRET, ///< = CS_GRP_IRET
// all privileged instructions
RISCV_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE
// all relative branching instructions
RISCV_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
// Architecture-specific groups
RISCV_GRP_ISRV32 = 128,
RISCV_GRP_ISRV64,
RISCV_GRP_HASSTDEXTA,

32
suite/cstest/issues.cs
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@ -1,3 +1,35 @@
!# issue 2007 RISCV64 instruction groups
!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
0x63,0x04,0x03,0x00 == beqz t1, 8 ; op_count: 2 ; operands[0].type: REG = t1 ; operands[1].type: IMM = 0x8 ; Groups: branch_relative jump
!# issue 2007 RISCV64 instruction groups
!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
0x73,0x00,0x00,0x00 == ecall ; Groups: int
!# issue 2007 RISCV64 instruction groups
!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
0xef,0x00,0x40,0x00 == jal 4 ; op_count: 1 ; operands[0].type: IMM = 0x4 ; Groups: call
!# issue 2007 RISCV32 instruction groups
!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
0x63,0x04,0x03,0x00 == beqz t1, 8 ; op_count: 2 ; operands[0].type: REG = t1 ; operands[1].type: IMM = 0x8 ; Groups: branch_relative jump
!# issue 2007 RISCV32 instruction groups
!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
0x73,0x00,0x00,0x00 == ecall ; Groups: int
!# issue 2007 RISCV32 instruction groups
!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
0xef,0x00,0x40,0x00 == jal 4 ; op_count: 1 ; operands[0].type: IMM = 0x4 ; Groups: call
!# issue 2007 RISCV32 instruction groups
!# CS_ARCH_RISCV, CS_MODE_RISCV32 CS_MODE_RISCVC, CS_OPT_DETAIL
0x11,0x20 == c.jal 4 ; op_count: 1 ; operands[0].type: IMM = 0x4 ; Groups: hasStdExtC isrv32 call
!# issue 2007 RISCV32 instruction groups
!# CS_ARCH_RISCV, CS_MODE_RISCV32 CS_MODE_RISCVC, CS_OPT_DETAIL
0x91,0xc1 == c.beqz a1, 4 ; op_count: 2 ; operands[0].type: REG = a1 ; operands[1].type: IMM = 0x4 ; Groups: hasStdExtC branch_relative jump
!# issue 1997 notrack jmp
!# CS_ARCH_X86, CS_MODE_64, None
0x3e,0xff,0xe0 == notrack jmp rax

1
suite/cstest/src/main.c
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@ -62,6 +62,7 @@ static single_dict arches[] = {
{"CS_MODE_BPF_EXTENDED", CS_MODE_BPF_EXTENDED},
{"CS_MODE_RISCV32", CS_MODE_RISCV32},
{"CS_MODE_RISCV64", CS_MODE_RISCV64},
{"CS_MODE_RISCVC", CS_MODE_RISCVC},
{"CS_MODE_TRICORE_110", CS_MODE_TRICORE_110},
{"CS_MODE_TRICORE_120", CS_MODE_TRICORE_120},
{"CS_MODE_TRICORE_130", CS_MODE_TRICORE_130},

12
suite/test_group_name.py
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@ -228,6 +228,12 @@ xcore_dict = {
riscv32_dict = {
RISCV_GRP_JUMP : "jump",
RISCV_GRP_CALL : "call",
RISCV_GRP_RET : "ret",
RISCV_GRP_INT : "int",
RISCV_GRP_IRET : "iret",
RISCV_GRP_PRIVILEGE : "privileged",
RISCV_GRP_BRANCH_RELATIVE: "branch_relative",
RISCV_GRP_ISRV32 : "isrv32",
RISCV_GRP_HASSTDEXTA : "hasstdexta",
RISCV_GRP_HASSTDEXTC : "hasstdextc",
@ -238,6 +244,12 @@ riscv32_dict = {
riscv64_dict = {
RISCV_GRP_JUMP : "jump",
RISCV_GRP_CALL : "call",
RISCV_GRP_RET : "ret",
RISCV_GRP_INT : "int",
RISCV_GRP_IRET : "iret",
RISCV_GRP_PRIVILEGE : "privileged",
RISCV_GRP_BRANCH_RELATIVE: "branch_relative",
RISCV_GRP_ISRV64 : "isrv64",
RISCV_GRP_HASSTDEXTA : "hasstdexta",
RISCV_GRP_HASSTDEXTC : "hasstdextc",