Merge pull request #278 from radare/arm-priv

add ARM_GRP_PRIVILEGE group and tag some instructions
This commit is contained in:
Nguyen Anh Quynh 2015-03-12 17:41:52 +08:00
commit ba7bf10dbb
2 changed files with 19 additions and 18 deletions

View File

@ -208,13 +208,13 @@
{ {
ARM_CDP, ARM_INS_CDP, ARM_CDP, ARM_INS_CDP,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0
#endif #endif
}, },
{ {
ARM_CDP2, ARM_INS_CDP2, ARM_CDP2, ARM_INS_CDP2,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0
#endif #endif
}, },
{ {
@ -880,25 +880,25 @@
{ {
ARM_MCR, ARM_INS_MCR, ARM_MCR, ARM_INS_MCR,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0
#endif #endif
}, },
{ {
ARM_MCR2, ARM_INS_MCR2, ARM_MCR2, ARM_INS_MCR2,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0
#endif #endif
}, },
{ {
ARM_MCRR, ARM_INS_MCRR, ARM_MCRR, ARM_INS_MCRR,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0
#endif #endif
}, },
{ {
ARM_MCRR2, ARM_INS_MCRR2, ARM_MCRR2, ARM_INS_MCRR2,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0
#endif #endif
}, },
{ {
@ -964,13 +964,13 @@
{ {
ARM_MRC, ARM_INS_MRC, ARM_MRC, ARM_INS_MRC,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0
#endif #endif
}, },
{ {
ARM_MRC2, ARM_INS_MRC2, ARM_MRC2, ARM_INS_MRC2,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0
#endif #endif
}, },
{ {
@ -1468,7 +1468,7 @@
{ {
ARM_SMC, ARM_INS_SMC, ARM_SMC, ARM_INS_SMC,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0 }, 0, 0
#endif #endif
}, },
{ {
@ -10780,13 +10780,13 @@
{ {
ARM_t2CDP, ARM_INS_CDP, ARM_t2CDP, ARM_INS_CDP,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0
#endif #endif
}, },
{ {
ARM_t2CDP2, ARM_INS_CDP2, ARM_t2CDP2, ARM_INS_CDP2,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0
#endif #endif
}, },
{ {
@ -11410,25 +11410,25 @@
{ {
ARM_t2MCR, ARM_INS_MCR, ARM_t2MCR, ARM_INS_MCR,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0
#endif #endif
}, },
{ {
ARM_t2MCR2, ARM_INS_MCR2, ARM_t2MCR2, ARM_INS_MCR2,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0
#endif #endif
}, },
{ {
ARM_t2MCRR, ARM_INS_MCRR, ARM_t2MCRR, ARM_INS_MCRR,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0
#endif #endif
}, },
{ {
ARM_t2MCRR2, ARM_INS_MCRR2, ARM_t2MCRR2, ARM_INS_MCRR2,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0
#endif #endif
}, },
{ {
@ -11482,13 +11482,13 @@
{ {
ARM_t2MRC, ARM_INS_MRC, ARM_t2MRC, ARM_INS_MRC,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0
#endif #endif
}, },
{ {
ARM_t2MRC2, ARM_INS_MRC2, ARM_t2MRC2, ARM_INS_MRC2,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0
#endif #endif
}, },
{ {
@ -11920,7 +11920,7 @@
{ {
ARM_t2SMC, ARM_INS_SMC, ARM_t2SMC, ARM_INS_SMC,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_TRUSTZONE, 0 }, 0, 0 { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_TRUSTZONE, 0 }, 0, 0
#endif #endif
}, },
{ {

View File

@ -878,6 +878,7 @@ typedef enum arm_insn_group {
//> Generic groups //> Generic groups
// all jump instructions (conditional+direct+indirect jumps) // all jump instructions (conditional+direct+indirect jumps)
ARM_GRP_JUMP, // = CS_GRP_JUMP ARM_GRP_JUMP, // = CS_GRP_JUMP
ARM_GRP_PRIVILEGE = 6, // = CS_GRP_PRIVILEGE
//> Architecture-specific groups //> Architecture-specific groups
ARM_GRP_CRYPTO = 128, ARM_GRP_CRYPTO = 128,