mirror of
https://github.com/capstone-engine/capstone.git
synced 2025-02-12 18:08:42 +00:00
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
This commit is contained in:
Nguyen Anh Quynh
parent
14ebaafb06
commit
bb0744df5d
@ -18,7 +18,8 @@ void SStream_concat(SStream *ss, const char *fmt, ...)
|
||||
{
|
||||
#ifndef CAPSTONE_DIET
|
||||
va_list ap;
|
||||
int ret = 0;
|
||||
int ret;
|
||||
|
||||
va_start(ap, fmt);
|
||||
ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
|
||||
va_end(ap);
|
||||
|
||||
@ -11,8 +11,8 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/* Capstone Disassembler Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
|
||||
#pragma warning(disable:4996)
|
||||
@ -79,7 +79,7 @@ static char *utostr(uint64_t X, bool isNeg)
|
||||
{
|
||||
char Buffer[22];
|
||||
char *BufPtr = Buffer+21;
|
||||
char *result = NULL;
|
||||
char *result;
|
||||
|
||||
Buffer[21] = '\0';
|
||||
if (X == 0) *--BufPtr = '0'; // Handle special case...
|
||||
@ -577,9 +577,9 @@ static NamedImmMapper_Mapping SysRegPairs[] = {
|
||||
// result must be a big enough buffer: 128 bytes is more than enough
|
||||
void SysRegMapper_toString(SysRegMapper *S, uint32_t Bits, bool *Valid, char *result)
|
||||
{
|
||||
int dummy = 0;
|
||||
uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
|
||||
char *Op1S = NULL, *CRnS = NULL, *CRmS = NULL, *Op2S = NULL;
|
||||
int dummy;
|
||||
uint32_t Op0, Op1, CRn, CRm, Op2;
|
||||
char *Op1S, *CRnS, *CRmS, *Op2S;
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
|
||||
@ -946,9 +946,9 @@ bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm)
|
||||
uint32_t N = Bits >> 12;
|
||||
uint32_t ImmR = (Bits >> 6) & 0x3f;
|
||||
uint32_t ImmS = Bits & 0x3f;
|
||||
uint64_t Mask = 0, WidthMask = 0;
|
||||
unsigned i = 0;
|
||||
int Width = 0, Num1s = 0, Rotation = 0;
|
||||
uint64_t Mask, WidthMask;
|
||||
unsigned i;
|
||||
int Width = 0, Num1s, Rotation;
|
||||
|
||||
// N=1 encodes a 64-bit replication and is invalid for the 32-bit
|
||||
// instructions.
|
||||
@ -974,7 +974,8 @@ bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm)
|
||||
Num1s = (ImmS & (Width - 1)) + 1;
|
||||
|
||||
// All encodings which would map to -1 (signed) are RESERVED.
|
||||
if (Num1s == Width) return false;
|
||||
if (Num1s == Width)
|
||||
return false;
|
||||
|
||||
Rotation = (ImmR & (Width - 1));
|
||||
Mask = (1ULL << Num1s) - 1;
|
||||
|
||||
@ -14,8 +14,8 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/* Capstone Disassembler Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
#ifndef CS_LLVM_AARCH64_BASEINFO_H
|
||||
#define CS_LLVM_AARCH64_BASEINFO_H
|
||||
|
||||
@ -260,7 +260,7 @@ static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI,
|
||||
uint16_t *Size,
|
||||
uint64_t Address, MCRegisterInfo *MRI)
|
||||
{
|
||||
uint32_t insn = 0;
|
||||
uint32_t insn;
|
||||
DecodeStatus result;
|
||||
|
||||
if (code_len < 4) {
|
||||
@ -1166,7 +1166,7 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst *Inst, unsigned Insn,
|
||||
// TransferBytes = NumVecs * OneLaneBytes
|
||||
unsigned TransferBytes = 0;
|
||||
unsigned NumVecs = 0;
|
||||
unsigned Rt = 0, Rn = 0, Rm = 0, Q = 0, S = 0, lane = 0, NumLanes = 0;
|
||||
unsigned Rt, Rn, Rm, Q, S, lane, NumLanes;
|
||||
unsigned Opc = MCInst_getOpcode(Inst);
|
||||
switch (Opc) {
|
||||
case AArch64_LD1R_WB_8B_fixed: case AArch64_LD1R_WB_8B_register:
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
\*===----------------------------------------------------------------------===*/
|
||||
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
/// printInstruction - This method is automatically generated by tablegen
|
||||
/// from the instruction set description.
|
||||
@ -8871,7 +8871,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
|
||||
{
|
||||
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
|
||||
const char *AsmString;
|
||||
char *tmp = NULL, *AsmMnem = NULL, *AsmOps = NULL, *c = NULL;
|
||||
char *tmp, *AsmMnem, *AsmOps, *c;
|
||||
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
|
||||
switch (MCInst_getOpcode(MI)) {
|
||||
default: return NULL;
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
\*===----------------------------------------------------------------------===*/
|
||||
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
#include "../../MCInst.h"
|
||||
#include "../../LEB128.h"
|
||||
@ -14036,9 +14036,9 @@ static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
|
||||
{ \
|
||||
uint64_t Bits = getFeatureBits(feature); \
|
||||
uint8_t *Ptr = DecodeTable; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue = 0; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue; \
|
||||
DecodeStatus S = MCDisassembler_Success; \
|
||||
unsigned Start = 0, Len = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0; \
|
||||
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
|
||||
InsnType Val, FieldValue, PositiveMask, NegativeMask; \
|
||||
bool Pred, Fail; \
|
||||
for (;;) { \
|
||||
|
||||
@ -11,8 +11,8 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/* Capstone Disassembler Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <stdio.h>
|
||||
@ -399,7 +399,8 @@ static void printShiftOperand(MCInst *MI, unsigned OpNum,
|
||||
SStream *O, A64SE_ShiftExtSpecifiers Shift)
|
||||
{
|
||||
MCOperand *MO = MCInst_getOperand(MI, OpNum);
|
||||
unsigned int imm = 0;
|
||||
unsigned int imm;
|
||||
|
||||
// LSL #0 is not printed
|
||||
if (Shift == A64SE_LSL && MCOperand_isImm(MO) && MCOperand_getImm(MO) == 0)
|
||||
return;
|
||||
@ -660,7 +661,7 @@ static void printNeonMovImmShiftOperand(MCInst *MI, unsigned OpNum,
|
||||
SStream *O, A64SE_ShiftExtSpecifiers Ext, bool isHalf)
|
||||
{
|
||||
MCOperand *MO = MCInst_getOperand(MI, OpNum);
|
||||
int64_t Imm = 0;
|
||||
int64_t Imm;
|
||||
//assert(MO.isImm() &&
|
||||
// "Immediate operand required for Neon vector immediate inst.");
|
||||
|
||||
|
||||
@ -11,8 +11,8 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/* Capstone Disassembler Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
#ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
|
||||
#define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
|
||||
@ -148,7 +148,7 @@ static inline unsigned getSOImmValRot(unsigned Imm)
|
||||
/// take a maximal chunk of bits out of the immediate.
|
||||
static inline unsigned getSOImmValRotate(unsigned Imm)
|
||||
{
|
||||
unsigned TZ = 0, RotAmt = 0;
|
||||
unsigned TZ, RotAmt;
|
||||
// 8-bit (or less) immediates are trivially shifter_operands with a rotate
|
||||
// of zero.
|
||||
if ((Imm & ~255U) == 0) return 0;
|
||||
@ -184,7 +184,7 @@ static inline unsigned getSOImmValRotate(unsigned Imm)
|
||||
/// it. If not, return -1.
|
||||
static inline int getSOImmVal(unsigned Arg)
|
||||
{
|
||||
unsigned RotAmt = 0;
|
||||
unsigned RotAmt;
|
||||
// 8-bit (or less) immediates are trivially shifter_operands with a rotate
|
||||
// of zero.
|
||||
if ((Arg & ~255U) == 0) return Arg;
|
||||
@ -339,7 +339,7 @@ static inline int getT2SOImmValRotateVal(unsigned V)
|
||||
/// See ARM Reference Manual A6.3.2.
|
||||
static inline int getT2SOImmVal(unsigned Arg)
|
||||
{
|
||||
int Rot = 0;
|
||||
int Rot;
|
||||
// If 'Arg' is an 8-bit splat, then get the encoded value.
|
||||
int Splat = getT2SOImmValSplatVal(Arg);
|
||||
if (Splat != -1)
|
||||
@ -355,8 +355,11 @@ static inline int getT2SOImmVal(unsigned Arg)
|
||||
|
||||
static inline unsigned getT2SOImmValRotate(unsigned V)
|
||||
{
|
||||
unsigned RotAmt = 0;
|
||||
if ((V & ~255U) == 0) return 0;
|
||||
unsigned RotAmt;
|
||||
|
||||
if ((V & ~255U) == 0)
|
||||
return 0;
|
||||
|
||||
// Use CTZ to compute the rotate amount.
|
||||
RotAmt = CountTrailingZeros_32(V);
|
||||
return (32 - RotAmt) & 31;
|
||||
|
||||
@ -7,8 +7,8 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/* Capstone Disassembler Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
@ -437,7 +437,7 @@ void ARM_init(MCRegisterInfo *MRI)
|
||||
static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len,
|
||||
uint16_t *Size, uint64_t Address)
|
||||
{
|
||||
uint32_t insn = 0;
|
||||
uint32_t insn;
|
||||
uint8_t bytes[4];
|
||||
DecodeStatus result;
|
||||
|
||||
@ -671,11 +671,11 @@ static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8
|
||||
uint16_t *Size, uint64_t Address)
|
||||
{
|
||||
uint8_t bytes[4];
|
||||
uint16_t insn16 = 0;
|
||||
uint16_t insn16;
|
||||
DecodeStatus result;
|
||||
bool InITBlock;
|
||||
unsigned Firstcond = 0, Mask = 0;
|
||||
uint32_t NEONLdStInsn = 0, insn32 = 0, NEONDataInsn = 0, NEONCryptoInsn = 0, NEONv8Insn = 0;
|
||||
unsigned Firstcond, Mask;
|
||||
uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn;
|
||||
|
||||
ud->ITBlock.size = 0;
|
||||
|
||||
@ -885,7 +885,7 @@ static const uint16_t GPRDecoderTable[] = {
|
||||
static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned Register = 0;
|
||||
unsigned Register;
|
||||
if (RegNo > 15)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -937,7 +937,7 @@ static const uint16_t GPRPairDecoderTable[] = {
|
||||
static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned RegisterPair = 0;
|
||||
unsigned RegisterPair;
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
|
||||
if (RegNo > 13)
|
||||
@ -1006,7 +1006,7 @@ static const uint16_t SPRDecoderTable[] = {
|
||||
static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned Register = 0;
|
||||
unsigned Register;
|
||||
if (RegNo > 31)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -1065,7 +1065,7 @@ static const uint16_t QPRDecoderTable[] = {
|
||||
static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned Register = 0;
|
||||
unsigned Register;
|
||||
if (RegNo > 31 || (RegNo & 1) != 0)
|
||||
return MCDisassembler_Fail;
|
||||
RegNo >>= 1;
|
||||
@ -1087,7 +1087,7 @@ static const uint16_t DPairDecoderTable[] = {
|
||||
static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned Register = 0;
|
||||
unsigned Register;
|
||||
if (RegNo > 30)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -1110,7 +1110,7 @@ static const uint16_t DPairSpacedDecoderTable[] = {
|
||||
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned Register = 0;
|
||||
unsigned Register;
|
||||
if (RegNo > 29)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -1144,7 +1144,7 @@ static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val,
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
ARM_AM_ShiftOpc Shift;
|
||||
unsigned Op = 0;
|
||||
unsigned Op;
|
||||
unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
|
||||
unsigned type = fieldFromInstruction_4(Val, 5, 2);
|
||||
unsigned imm = fieldFromInstruction_4(Val, 7, 5);
|
||||
@ -1218,7 +1218,7 @@ static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val,
|
||||
static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned i = 0;
|
||||
unsigned i;
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
|
||||
bool NeedDisjointWriteback = false;
|
||||
@ -1258,7 +1258,7 @@ static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned i = 0;
|
||||
unsigned i;
|
||||
unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
|
||||
unsigned regs = fieldFromInstruction_4(Val, 0, 8);
|
||||
|
||||
@ -1283,7 +1283,7 @@ static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned i = 0;
|
||||
unsigned i;
|
||||
unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
|
||||
unsigned regs = fieldFromInstruction_4(Val, 1, 7);
|
||||
|
||||
@ -1297,6 +1297,7 @@ static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
|
||||
|
||||
if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
for (i = 0; i < (regs - 1); ++i) {
|
||||
if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
|
||||
return MCDisassembler_Fail;
|
||||
@ -1315,7 +1316,7 @@ static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val,
|
||||
// create the final mask.
|
||||
unsigned msb = fieldFromInstruction_4(Val, 5, 5);
|
||||
unsigned lsb = fieldFromInstruction_4(Val, 0, 5);
|
||||
uint32_t lsb_mask, msb_mask = 0;
|
||||
uint32_t lsb_mask, msb_mask;
|
||||
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
if (lsb > msb) {
|
||||
@ -1494,7 +1495,7 @@ static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
|
||||
unsigned reg = fieldFromInstruction_4(Insn, 25, 1);
|
||||
unsigned P = fieldFromInstruction_4(Insn, 24, 1);
|
||||
unsigned W = fieldFromInstruction_4(Insn, 21, 1);
|
||||
unsigned idx_mode = 0, amt = 0, tmp = 0;
|
||||
unsigned idx_mode = 0, amt, tmp;
|
||||
|
||||
// On stores, the writeback operand precedes Rt.
|
||||
switch (MCInst_getOpcode(Inst)) {
|
||||
@ -1592,7 +1593,7 @@ static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val,
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
ARM_AM_ShiftOpc ShOp;
|
||||
unsigned shift = 0;
|
||||
unsigned shift;
|
||||
unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
|
||||
unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
|
||||
unsigned type = fieldFromInstruction_4(Val, 5, 2);
|
||||
@ -2256,7 +2257,7 @@ static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned wb = 0, Rn = 0, Rm = 0;
|
||||
unsigned wb, Rn, Rm;
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
|
||||
wb = fieldFromInstruction_4(Insn, 16, 4);
|
||||
@ -2530,7 +2531,7 @@ static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn,
|
||||
static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned load = 0;
|
||||
unsigned load;
|
||||
unsigned type = fieldFromInstruction_4(Insn, 8, 4);
|
||||
unsigned align = fieldFromInstruction_4(Insn, 4, 2);
|
||||
if (type == 6 && (align & 2)) return MCDisassembler_Fail;
|
||||
@ -2545,7 +2546,7 @@ static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn,
|
||||
static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned type = 0, align = 0, load = 0;
|
||||
unsigned type, align, load;
|
||||
unsigned size = fieldFromInstruction_4(Insn, 6, 2);
|
||||
if (size == 3) return MCDisassembler_Fail;
|
||||
|
||||
@ -2562,7 +2563,7 @@ static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn,
|
||||
static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned align = 0, load = 0;
|
||||
unsigned align, load;
|
||||
unsigned size = fieldFromInstruction_4(Insn, 6, 2);
|
||||
if (size == 3) return MCDisassembler_Fail;
|
||||
|
||||
@ -2577,7 +2578,7 @@ static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn,
|
||||
static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned load = 0;
|
||||
unsigned load;
|
||||
unsigned size = fieldFromInstruction_4(Insn, 6, 2);
|
||||
if (size == 3) return MCDisassembler_Fail;
|
||||
|
||||
@ -2590,7 +2591,7 @@ static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned wb = 0, Rn = 0, Rm = 0;
|
||||
unsigned wb, Rn, Rm;
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
|
||||
wb = fieldFromInstruction_4(Insn, 16, 4);
|
||||
@ -2862,7 +2863,7 @@ static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned Rn = 0, Rm = 0, align = 0, size = 0;
|
||||
unsigned Rn, Rm, align, size;
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
|
||||
Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
@ -2910,7 +2911,7 @@ static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned Rn = 0, Rm = 0, align = 0, size = 0;
|
||||
unsigned Rn, Rm, align, size;
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
|
||||
Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
@ -2959,7 +2960,7 @@ static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned Rn = 0, Rm = 0, inc = 0;
|
||||
unsigned Rn, Rm, inc;
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
|
||||
Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
@ -2995,7 +2996,7 @@ static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned Rn = 0, Rm = 0, size = 0, inc = 0, align = 0;
|
||||
unsigned Rn, Rm, size, inc, align;
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
|
||||
Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
@ -3044,12 +3045,11 @@ static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn,
|
||||
return S;
|
||||
}
|
||||
|
||||
static DecodeStatus
|
||||
DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn,
|
||||
static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned imm = 0, Q = 0;
|
||||
unsigned imm, Q;
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
|
||||
imm = fieldFromInstruction_4(Insn, 0, 4);
|
||||
@ -3095,7 +3095,7 @@ static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned Rm = 0, size = 0;
|
||||
unsigned Rm, size;
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
|
||||
Rm = fieldFromInstruction_4(Insn, 0, 4);
|
||||
@ -3143,7 +3143,7 @@ static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned Rn = 0, Rm = 0, op = 0;
|
||||
unsigned Rn, Rm, op;
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
|
||||
Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
@ -3306,7 +3306,7 @@ static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned addrmode = 0;
|
||||
unsigned addrmode;
|
||||
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
|
||||
@ -3702,7 +3702,7 @@ static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned load = 0;
|
||||
unsigned load;
|
||||
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
|
||||
@ -3902,9 +3902,10 @@ static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned imm = 0, brtarget = 0;
|
||||
unsigned brtarget;
|
||||
unsigned pred = fieldFromInstruction_4(Insn, 22, 4);
|
||||
if (pred == 0xE || pred == 0xF) {
|
||||
unsigned imm;
|
||||
unsigned opc = fieldFromInstruction_4(Insn, 4, 28);
|
||||
switch (opc) {
|
||||
default:
|
||||
@ -4082,7 +4083,7 @@ static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned pred = 0;
|
||||
unsigned pred;
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
|
||||
@ -4108,7 +4109,7 @@ static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned pred = 0, Rm = 0;
|
||||
unsigned pred, Rm;
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
|
||||
@ -4136,7 +4137,7 @@ static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned pred = 0;
|
||||
unsigned pred;
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
|
||||
@ -4162,7 +4163,7 @@ static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned pred = 0;
|
||||
unsigned pred;
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
|
||||
unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
|
||||
@ -4188,7 +4189,7 @@ static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned size = 0, align = 0, index = 0;
|
||||
unsigned size, align = 0, index = 0;
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
@ -4254,7 +4255,7 @@ static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned size = 0, align = 0, index = 0;
|
||||
unsigned size, align = 0, index = 0;
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
@ -4318,7 +4319,7 @@ static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned size = 0, align = 0, index = 0, inc = 1;
|
||||
unsigned size, align = 0, index = 0, inc = 1;
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
@ -4383,7 +4384,7 @@ static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned size = 0, align = 0, index = 0, inc = 1;
|
||||
unsigned size, align = 0, index = 0, inc = 1;
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
@ -4444,7 +4445,7 @@ static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned size = 0, align = 0, index = 0, inc = 1;
|
||||
unsigned size, align = 0, index = 0, inc = 1;
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
@ -4512,7 +4513,7 @@ static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned size = 0, align = 0, index = 0, inc = 1;
|
||||
unsigned size, align = 0, index = 0, inc = 1;
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
@ -4573,7 +4574,7 @@ static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned size = 0, align = 0, index = 0, inc = 1;
|
||||
unsigned size, align = 0, index = 0, inc = 1;
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
@ -4652,7 +4653,7 @@ static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned size = 0, align = 0, index = 0, inc = 1;
|
||||
unsigned size, align = 0, index = 0, inc = 1;
|
||||
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
|
||||
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
|
||||
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
|
||||
@ -4867,7 +4868,7 @@ static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn,
|
||||
static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned Val = 0;
|
||||
unsigned Val;
|
||||
unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1);
|
||||
unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1);
|
||||
if (sign1 != sign2) return MCDisassembler_Fail;
|
||||
@ -4926,7 +4927,7 @@ static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned Vm = 0, imm = 0, cmode = 0, op = 0;
|
||||
unsigned Vm, imm, cmode, op;
|
||||
unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
|
||||
Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
|
||||
Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
|
||||
@ -4957,7 +4958,7 @@ static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned Vm = 0, imm = 0, cmode = 0, op = 0;
|
||||
unsigned Vm, imm, cmode, op;
|
||||
unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
|
||||
Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
|
||||
Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
|
||||
@ -4988,7 +4989,7 @@ static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned Cond = 0;
|
||||
unsigned Cond;
|
||||
unsigned Rn = fieldFromInstruction_4(Val, 16, 4);
|
||||
unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
|
||||
unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
|
||||
|
||||
@ -13449,9 +13449,9 @@ static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
|
||||
{ \
|
||||
uint64_t Bits = getFeatureBits(feature); \
|
||||
uint8_t *Ptr = DecodeTable; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue = 0; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue; \
|
||||
DecodeStatus S = MCDisassembler_Success; \
|
||||
unsigned Start = 0, Len = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0; \
|
||||
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
|
||||
InsnType Val, FieldValue, PositiveMask, NegativeMask; \
|
||||
bool Pred, Fail; \
|
||||
for (;;) { \
|
||||
|
||||
@ -269,7 +269,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
|
||||
{
|
||||
MCRegisterInfo *MRI = (MCRegisterInfo *)Info;
|
||||
|
||||
unsigned Opcode = MCInst_getOpcode(MI), tmp = 0, i = 0;
|
||||
unsigned Opcode = MCInst_getOpcode(MI), tmp, i;
|
||||
|
||||
switch(Opcode) {
|
||||
// Check for HINT instructions w/ canonical names.
|
||||
@ -546,7 +546,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
|
||||
|
||||
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
int32_t imm = 0;
|
||||
int32_t imm;
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNo);
|
||||
if (MCOperand_isReg(Op)) {
|
||||
unsigned Reg = MCOperand_getReg(Op);
|
||||
@ -618,7 +618,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
|
||||
int32_t OffImm = 0;
|
||||
int32_t OffImm;
|
||||
bool isSub;
|
||||
SStream_concat(O, "%s[pc, ", markup("<mem:"));
|
||||
|
||||
@ -840,7 +840,7 @@ static void printAM3PostIndexOp(MCInst *MI, unsigned Op, SStream *O)
|
||||
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
|
||||
MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
|
||||
ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO3));
|
||||
unsigned ImmOffs = 0;
|
||||
unsigned ImmOffs;
|
||||
|
||||
SStream_concat(O, "%s[", markup("<mem:"));
|
||||
set_mem_access(MI, true);
|
||||
@ -890,7 +890,7 @@ static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
|
||||
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
|
||||
MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
|
||||
ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO3));
|
||||
unsigned ImmOffs = 0;
|
||||
unsigned ImmOffs;
|
||||
|
||||
SStream_concat(O, "%s[", markup("<mem:"));
|
||||
set_mem_access(MI, true);
|
||||
@ -937,8 +937,8 @@ static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
|
||||
static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O,
|
||||
bool AlwaysPrintImm0)
|
||||
{
|
||||
unsigned IdxMode = 0;
|
||||
MCOperand *MO3 = NULL;
|
||||
unsigned IdxMode;
|
||||
MCOperand *MO3;
|
||||
MCOperand *MO1 = MCInst_getOperand(MI, Op);
|
||||
if (!MCOperand_isReg(MO1)) { // For label symbolic references.
|
||||
printOperand(MI, Op, O);
|
||||
@ -961,7 +961,7 @@ static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
|
||||
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
|
||||
ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO2));
|
||||
unsigned ImmOffs = 0;
|
||||
unsigned ImmOffs;
|
||||
|
||||
if (MCOperand_getReg(MO1)) {
|
||||
SStream_concat(O, ARM_AM_getAddrOpcStr(op));
|
||||
@ -1043,7 +1043,7 @@ static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O,
|
||||
{
|
||||
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
|
||||
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
|
||||
unsigned ImmOffs = 0, Op = 0;
|
||||
unsigned ImmOffs, Op;
|
||||
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
|
||||
printOperand(MI, OpNum, O);
|
||||
return;
|
||||
@ -1071,7 +1071,7 @@ static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
|
||||
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
|
||||
unsigned tmp = 0;
|
||||
unsigned tmp;
|
||||
|
||||
SStream_concat(O, "%s[", markup("<mem:"));
|
||||
set_mem_access(MI, true);
|
||||
@ -1556,7 +1556,7 @@ static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O)
|
||||
{
|
||||
MCOperand *MO1 = MCInst_getOperand(MI, Op);
|
||||
MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
|
||||
unsigned RegNum = 0;
|
||||
unsigned RegNum;
|
||||
|
||||
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
|
||||
printOperand(MI, Op, O);
|
||||
@ -1586,7 +1586,7 @@ static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O,
|
||||
{
|
||||
MCOperand *MO1 = MCInst_getOperand(MI, Op);
|
||||
MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
|
||||
unsigned ImmOffs = 0, tmp = 0;
|
||||
unsigned ImmOffs, tmp;
|
||||
|
||||
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
|
||||
printOperand(MI, Op, O);
|
||||
@ -1792,7 +1792,7 @@ static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStrea
|
||||
{
|
||||
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
|
||||
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
|
||||
unsigned tmp = 0;
|
||||
unsigned tmp;
|
||||
|
||||
SStream_concat(O, markup("<mem:"));
|
||||
SStream_concat(O, "[");
|
||||
@ -1891,7 +1891,7 @@ static void printT2AddrModeSoRegOperand(MCInst *MI,
|
||||
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
|
||||
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
|
||||
MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
|
||||
unsigned ShAmt = 0;
|
||||
unsigned ShAmt;
|
||||
|
||||
SStream_concat(O, "%s[", markup("<mem:"));
|
||||
set_mem_access(MI, true);
|
||||
@ -1984,7 +1984,8 @@ static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
|
||||
static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
unsigned tmp = 0;
|
||||
unsigned tmp;
|
||||
|
||||
SStream_concat(O, markup("<imm:"));
|
||||
tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
if (tmp > HEX_THRESHOLD)
|
||||
@ -2001,7 +2002,8 @@ static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
|
||||
static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
unsigned tmp = 0;
|
||||
unsigned tmp;
|
||||
|
||||
SStream_concat(O, markup("<imm:"));
|
||||
tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
if (tmp > HEX_THRESHOLD)
|
||||
|
||||
@ -11,8 +11,8 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/* Capstone Disassembler Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
@ -349,7 +349,8 @@ static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 31)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -361,9 +362,11 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 31)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo);
|
||||
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
|
||||
return MCDisassembler_Success;
|
||||
@ -387,7 +390,8 @@ static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 31)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -399,7 +403,8 @@ static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 31)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -411,7 +416,8 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeFGRH32RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 31)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -423,7 +429,8 @@ static DecodeStatus DecodeFGRH32RegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 31)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -435,7 +442,8 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 7)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -577,8 +585,9 @@ static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
if (RegNo > 30 || RegNo %2)
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 30 || RegNo % 2)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2);
|
||||
@ -589,7 +598,8 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo >= 4)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -601,7 +611,8 @@ static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo >= 4)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -613,7 +624,8 @@ static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo >= 4)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -625,7 +637,8 @@ static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 31)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -638,7 +651,8 @@ static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 31)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -651,7 +665,8 @@ static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 31)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -664,7 +679,8 @@ static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 31)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
@ -677,7 +693,8 @@ static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg = 0;
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 7)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
\*===----------------------------------------------------------------------===*/
|
||||
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
/// printInstruction - This method is automatically generated by tablegen
|
||||
/// from the instruction set description.
|
||||
@ -4408,7 +4408,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
|
||||
{
|
||||
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
|
||||
const char *AsmString;
|
||||
char *tmp = NULL, *AsmMnem = NULL, *AsmOps = NULL, *c = NULL;
|
||||
char *tmp, *AsmMnem, *AsmOps, *c;
|
||||
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
|
||||
switch (MCInst_getOpcode(MI)) {
|
||||
default: return NULL;
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
\*===----------------------------------------------------------------------===*/
|
||||
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
#include "../../MCInst.h"
|
||||
#include "../../LEB128.h"
|
||||
@ -5501,9 +5501,9 @@ static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
|
||||
{ \
|
||||
uint64_t Bits = getFeatureBits(feature); \
|
||||
uint8_t *Ptr = DecodeTable; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue = 0; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue; \
|
||||
DecodeStatus S = MCDisassembler_Success; \
|
||||
unsigned Start = 0, Len = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0; \
|
||||
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
|
||||
InsnType Val, FieldValue, PositiveMask, NegativeMask; \
|
||||
bool Pred, Fail; \
|
||||
for (;;) { \
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* Capstone Unified Disassembler Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
#include <stdio.h> // debug
|
||||
#include <string.h>
|
||||
|
||||
@ -6,8 +6,8 @@
|
||||
|* *|
|
||||
\*===----------------------------------------------------------------------===*/
|
||||
|
||||
/* Capstone Disassembler Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
#include "../../MCInst.h"
|
||||
#include "../../LEB128.h"
|
||||
@ -2329,9 +2329,9 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
|
||||
{ \
|
||||
uint64_t Bits = getFeatureBits(feature); \
|
||||
const uint8_t *Ptr = DecodeTable; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue = 0; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue; \
|
||||
DecodeStatus S = MCDisassembler_Success; \
|
||||
unsigned Start = 0, Len = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0; \
|
||||
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
|
||||
InsnType Val, FieldValue, PositiveMask, NegativeMask; \
|
||||
bool Pred, Fail; \
|
||||
for (;;) { \
|
||||
|
||||
@ -374,7 +374,7 @@ static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
|
||||
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
int tmp = 0;
|
||||
int tmp;
|
||||
if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
|
||||
printOperand(MI, OpNo, O);
|
||||
return;
|
||||
|
||||
@ -1942,9 +1942,9 @@ static DecodeStatus decodeInstruction_4(uint8_t DecodeTable[], MCInst *MI,
|
||||
{
|
||||
uint64_t Bits = getFeatureBits(feature);
|
||||
uint8_t *Ptr = DecodeTable;
|
||||
uint32_t CurFieldValue = 0, ExpectedValue = 0;
|
||||
uint32_t CurFieldValue = 0, ExpectedValue;
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
unsigned Start = 0, Len = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0;
|
||||
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx;
|
||||
uint32_t Val, FieldValue, PositiveMask, NegativeMask;
|
||||
bool Pred, Fail;
|
||||
for (;;) {
|
||||
|
||||
@ -2920,9 +2920,9 @@ static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
|
||||
{ \
|
||||
uint64_t Bits = getFeatureBits(feature); \
|
||||
uint8_t *Ptr = DecodeTable; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue = 0; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue; \
|
||||
DecodeStatus S = MCDisassembler_Success; \
|
||||
unsigned Len = 0, Start = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0; \
|
||||
unsigned Len, Start, NumToSkip, PIdx, Opc, DecodeIdx; \
|
||||
InsnType FieldValue, Val, PositiveMask, NegativeMask; \
|
||||
bool Pred, Fail; \
|
||||
for (;;) { \
|
||||
|
||||
@ -428,7 +428,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
|
||||
MCOperand *IndexReg = MCInst_getOperand(MI, Op+2);
|
||||
MCOperand *DispSpec = MCInst_getOperand(MI, Op+3);
|
||||
MCOperand *SegReg = MCInst_getOperand(MI, Op+4);
|
||||
uint64_t ScaleVal = 0;
|
||||
uint64_t ScaleVal;
|
||||
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
|
||||
|
||||
@ -13830,7 +13830,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
|
||||
{
|
||||
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
|
||||
const char *AsmString;
|
||||
char *tmp = NULL, *AsmMnem = NULL, *AsmOps = NULL, *c = NULL;
|
||||
char *tmp, *AsmMnem, *AsmOps, *c;
|
||||
// MCRegisterInfo *MRI = (MCRegisterInfo *)info;
|
||||
switch (MCInst_getOpcode(MI)) {
|
||||
default: return 0;
|
||||
|
||||
@ -13334,8 +13334,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
|
||||
{
|
||||
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
|
||||
const char *AsmString;
|
||||
char *c = NULL;
|
||||
char *tmp = NULL, *AsmMnem = NULL, *AsmOps = NULL;
|
||||
char *tmp, *AsmMnem, *AsmOps, *c;
|
||||
// MCRegisterInfo *MRI = (MCRegisterInfo *)info;
|
||||
switch (MCInst_getOpcode(MI)) {
|
||||
default: return 0;
|
||||
|
||||
@ -12,8 +12,8 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/* Capstone Disassembler Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
|
||||
#include <ctype.h>
|
||||
#include <inttypes.h>
|
||||
@ -492,7 +492,6 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
|
||||
|
||||
SStream_concat(O, "[");
|
||||
|
||||
NeedPlus = false;
|
||||
if (MCOperand_getReg(BaseReg)) {
|
||||
_printOperand(MI, Op, O);
|
||||
NeedPlus = true;
|
||||
|
||||
26
cs.c
26
cs.c
@ -129,7 +129,7 @@ bool cs_support(int query)
|
||||
|
||||
cs_err cs_errno(csh handle)
|
||||
{
|
||||
struct cs_struct *ud = NULL;
|
||||
struct cs_struct *ud;
|
||||
if (!handle)
|
||||
return CS_ERR_CSH;
|
||||
|
||||
@ -173,7 +173,7 @@ const char *cs_strerror(cs_err code)
|
||||
cs_err cs_open(cs_arch arch, cs_mode mode, csh *handle)
|
||||
{
|
||||
cs_err err;
|
||||
struct cs_struct *ud = NULL;
|
||||
struct cs_struct *ud;
|
||||
if (!cs_mem_malloc || !cs_mem_calloc || !cs_mem_realloc || !cs_mem_free || !cs_vsnprintf)
|
||||
// Error: before cs_open(), dynamic memory management must be initialized
|
||||
// with cs_option(CS_OPT_MEM)
|
||||
@ -216,7 +216,8 @@ cs_err cs_open(cs_arch arch, cs_mode mode, csh *handle)
|
||||
|
||||
cs_err cs_close(csh *handle)
|
||||
{
|
||||
struct cs_struct *ud = NULL;
|
||||
struct cs_struct *ud;
|
||||
|
||||
if (*handle == 0)
|
||||
// invalid handle
|
||||
return CS_ERR_CSH;
|
||||
@ -243,7 +244,8 @@ cs_err cs_close(csh *handle)
|
||||
static void fill_insn(struct cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mci,
|
||||
PostPrinter_t postprinter, const uint8_t *code)
|
||||
{
|
||||
char *sp = NULL;
|
||||
char *sp;
|
||||
|
||||
if (handle->detail) {
|
||||
// avoiding copy insn->detail
|
||||
memcpy(insn, &mci->flat_insn, sizeof(*insn) - sizeof(insn->detail));
|
||||
@ -334,7 +336,7 @@ static uint8_t skipdata_size(cs_struct *handle)
|
||||
|
||||
cs_err cs_option(csh ud, cs_opt_type type, size_t value)
|
||||
{
|
||||
struct cs_struct *handle = NULL;
|
||||
struct cs_struct *handle;
|
||||
archs_enable();
|
||||
|
||||
// cs_option() can be called with NULL handle just for CS_OPT_MEM
|
||||
@ -605,7 +607,7 @@ static bool arr_exist(unsigned char *arr, unsigned char max, unsigned int id)
|
||||
|
||||
bool cs_insn_group(csh ud, cs_insn *insn, unsigned int group_id)
|
||||
{
|
||||
struct cs_struct *handle = NULL;
|
||||
struct cs_struct *handle;
|
||||
if (!ud)
|
||||
return false;
|
||||
|
||||
@ -631,7 +633,7 @@ bool cs_insn_group(csh ud, cs_insn *insn, unsigned int group_id)
|
||||
|
||||
bool cs_reg_read(csh ud, cs_insn *insn, unsigned int reg_id)
|
||||
{
|
||||
struct cs_struct *handle = NULL;
|
||||
struct cs_struct *handle;
|
||||
if (!ud)
|
||||
return false;
|
||||
|
||||
@ -657,7 +659,7 @@ bool cs_reg_read(csh ud, cs_insn *insn, unsigned int reg_id)
|
||||
|
||||
bool cs_reg_write(csh ud, cs_insn *insn, unsigned int reg_id)
|
||||
{
|
||||
struct cs_struct *handle = NULL;
|
||||
struct cs_struct *handle;
|
||||
if (!ud)
|
||||
return false;
|
||||
|
||||
@ -683,8 +685,8 @@ bool cs_reg_write(csh ud, cs_insn *insn, unsigned int reg_id)
|
||||
|
||||
int cs_op_count(csh ud, cs_insn *insn, unsigned int op_type)
|
||||
{
|
||||
struct cs_struct *handle = NULL;
|
||||
unsigned int count = 0, i = 0;
|
||||
struct cs_struct *handle;
|
||||
unsigned int count = 0, i;
|
||||
if (!ud)
|
||||
return -1;
|
||||
|
||||
@ -754,8 +756,8 @@ int cs_op_count(csh ud, cs_insn *insn, unsigned int op_type)
|
||||
int cs_op_index(csh ud, cs_insn *insn, unsigned int op_type,
|
||||
unsigned int post)
|
||||
{
|
||||
struct cs_struct *handle = NULL;
|
||||
unsigned int count = 0, i = 0;
|
||||
struct cs_struct *handle;
|
||||
unsigned int count = 0, i;
|
||||
if (!ud)
|
||||
return -1;
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user