mirror of
https://github.com/capstone-engine/capstone.git
synced 2024-12-14 17:08:39 +00:00
Merge branch 'next' of https://github.com/aquynh/capstone into next
This commit is contained in:
Nguyen Anh Quynh
commit
bb77154a4f
@ -318,453 +318,6 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
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}
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}
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#if 0
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static bool isTblTbxInstruction(unsigned Opcode, char **Layout, bool *IsTbx)
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{
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switch (Opcode) {
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case AArch64_TBXv8i8One:
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case AArch64_TBXv8i8Two:
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case AArch64_TBXv8i8Three:
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case AArch64_TBXv8i8Four:
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*IsTbx = true;
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*Layout = ".8b";
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return true;
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case AArch64_TBLv8i8One:
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case AArch64_TBLv8i8Two:
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case AArch64_TBLv8i8Three:
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case AArch64_TBLv8i8Four:
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*IsTbx = false;
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*Layout = ".8b";
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return true;
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case AArch64_TBXv16i8One:
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case AArch64_TBXv16i8Two:
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case AArch64_TBXv16i8Three:
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case AArch64_TBXv16i8Four:
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*IsTbx = true;
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*Layout = ".16b";
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return true;
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case AArch64_TBLv16i8One:
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case AArch64_TBLv16i8Two:
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case AArch64_TBLv16i8Three:
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case AArch64_TBLv16i8Four:
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*IsTbx = false;
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*Layout = ".16b";
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return true;
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default:
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return false;
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}
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}
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struct LdStNInstrDesc {
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unsigned Opcode;
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char *Mnemonic;
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char *Layout;
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int ListOperand;
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bool HasLane;
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int NaturalOffset;
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};
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static struct LdStNInstrDesc LdStNInstInfo[] = {
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{ AArch64_LD1i8, "ld1", ".b", 1, true, 0 },
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{ AArch64_LD1i16, "ld1", ".h", 1, true, 0 },
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{ AArch64_LD1i32, "ld1", ".s", 1, true, 0 },
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{ AArch64_LD1i64, "ld1", ".d", 1, true, 0 },
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{ AArch64_LD1i8_POST, "ld1", ".b", 2, true, 1 },
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{ AArch64_LD1i16_POST, "ld1", ".h", 2, true, 2 },
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{ AArch64_LD1i32_POST, "ld1", ".s", 2, true, 4 },
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{ AArch64_LD1i64_POST, "ld1", ".d", 2, true, 8 },
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{ AArch64_LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
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{ AArch64_LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
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{ AArch64_LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
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{ AArch64_LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
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{ AArch64_LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
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{ AArch64_LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
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{ AArch64_LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
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{ AArch64_LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
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{ AArch64_LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
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{ AArch64_LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
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{ AArch64_LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
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{ AArch64_LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
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{ AArch64_LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
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{ AArch64_LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
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{ AArch64_LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
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{ AArch64_LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
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{ AArch64_LD1Onev16b, "ld1", ".16b", 0, false, 0 },
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{ AArch64_LD1Onev8h, "ld1", ".8h", 0, false, 0 },
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{ AArch64_LD1Onev4s, "ld1", ".4s", 0, false, 0 },
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{ AArch64_LD1Onev2d, "ld1", ".2d", 0, false, 0 },
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{ AArch64_LD1Onev8b, "ld1", ".8b", 0, false, 0 },
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{ AArch64_LD1Onev4h, "ld1", ".4h", 0, false, 0 },
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{ AArch64_LD1Onev2s, "ld1", ".2s", 0, false, 0 },
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{ AArch64_LD1Onev1d, "ld1", ".1d", 0, false, 0 },
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{ AArch64_LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
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{ AArch64_LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
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{ AArch64_LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
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{ AArch64_LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
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{ AArch64_LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
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{ AArch64_LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
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{ AArch64_LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
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{ AArch64_LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
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{ AArch64_LD1Twov16b, "ld1", ".16b", 0, false, 0 },
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{ AArch64_LD1Twov8h, "ld1", ".8h", 0, false, 0 },
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{ AArch64_LD1Twov4s, "ld1", ".4s", 0, false, 0 },
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{ AArch64_LD1Twov2d, "ld1", ".2d", 0, false, 0 },
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{ AArch64_LD1Twov8b, "ld1", ".8b", 0, false, 0 },
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{ AArch64_LD1Twov4h, "ld1", ".4h", 0, false, 0 },
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{ AArch64_LD1Twov2s, "ld1", ".2s", 0, false, 0 },
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{ AArch64_LD1Twov1d, "ld1", ".1d", 0, false, 0 },
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{ AArch64_LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
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{ AArch64_LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
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{ AArch64_LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
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{ AArch64_LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
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{ AArch64_LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
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{ AArch64_LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
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{ AArch64_LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
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{ AArch64_LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
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{ AArch64_LD1Threev16b, "ld1", ".16b", 0, false, 0 },
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{ AArch64_LD1Threev8h, "ld1", ".8h", 0, false, 0 },
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{ AArch64_LD1Threev4s, "ld1", ".4s", 0, false, 0 },
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{ AArch64_LD1Threev2d, "ld1", ".2d", 0, false, 0 },
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{ AArch64_LD1Threev8b, "ld1", ".8b", 0, false, 0 },
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{ AArch64_LD1Threev4h, "ld1", ".4h", 0, false, 0 },
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{ AArch64_LD1Threev2s, "ld1", ".2s", 0, false, 0 },
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{ AArch64_LD1Threev1d, "ld1", ".1d", 0, false, 0 },
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{ AArch64_LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
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{ AArch64_LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
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{ AArch64_LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
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{ AArch64_LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
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{ AArch64_LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
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{ AArch64_LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
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{ AArch64_LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
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{ AArch64_LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
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{ AArch64_LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
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{ AArch64_LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
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{ AArch64_LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
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{ AArch64_LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
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{ AArch64_LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
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{ AArch64_LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
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{ AArch64_LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
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{ AArch64_LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
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{ AArch64_LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
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{ AArch64_LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
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{ AArch64_LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
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{ AArch64_LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
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{ AArch64_LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
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{ AArch64_LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
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{ AArch64_LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
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{ AArch64_LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
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{ AArch64_LD2i8, "ld2", ".b", 1, true, 0 },
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{ AArch64_LD2i16, "ld2", ".h", 1, true, 0 },
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{ AArch64_LD2i32, "ld2", ".s", 1, true, 0 },
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{ AArch64_LD2i64, "ld2", ".d", 1, true, 0 },
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{ AArch64_LD2i8_POST, "ld2", ".b", 2, true, 2 },
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{ AArch64_LD2i16_POST, "ld2", ".h", 2, true, 4 },
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{ AArch64_LD2i32_POST, "ld2", ".s", 2, true, 8 },
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{ AArch64_LD2i64_POST, "ld2", ".d", 2, true, 16 },
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{ AArch64_LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
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{ AArch64_LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
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{ AArch64_LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
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{ AArch64_LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
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{ AArch64_LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
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{ AArch64_LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
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{ AArch64_LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
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{ AArch64_LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
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{ AArch64_LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
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{ AArch64_LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
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{ AArch64_LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
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{ AArch64_LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
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{ AArch64_LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
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{ AArch64_LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
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{ AArch64_LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
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{ AArch64_LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
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{ AArch64_LD2Twov16b, "ld2", ".16b", 0, false, 0 },
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{ AArch64_LD2Twov8h, "ld2", ".8h", 0, false, 0 },
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{ AArch64_LD2Twov4s, "ld2", ".4s", 0, false, 0 },
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{ AArch64_LD2Twov2d, "ld2", ".2d", 0, false, 0 },
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{ AArch64_LD2Twov8b, "ld2", ".8b", 0, false, 0 },
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{ AArch64_LD2Twov4h, "ld2", ".4h", 0, false, 0 },
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{ AArch64_LD2Twov2s, "ld2", ".2s", 0, false, 0 },
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{ AArch64_LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
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{ AArch64_LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
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{ AArch64_LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
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{ AArch64_LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
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{ AArch64_LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
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{ AArch64_LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
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{ AArch64_LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
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{ AArch64_LD3i8, "ld3", ".b", 1, true, 0 },
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{ AArch64_LD3i16, "ld3", ".h", 1, true, 0 },
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{ AArch64_LD3i32, "ld3", ".s", 1, true, 0 },
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{ AArch64_LD3i64, "ld3", ".d", 1, true, 0 },
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{ AArch64_LD3i8_POST, "ld3", ".b", 2, true, 3 },
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{ AArch64_LD3i16_POST, "ld3", ".h", 2, true, 6 },
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{ AArch64_LD3i32_POST, "ld3", ".s", 2, true, 12 },
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{ AArch64_LD3i64_POST, "ld3", ".d", 2, true, 24 },
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{ AArch64_LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
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{ AArch64_LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
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{ AArch64_LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
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{ AArch64_LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
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{ AArch64_LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
|
||||
{ AArch64_LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
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{ AArch64_LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
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{ AArch64_LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
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{ AArch64_LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
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{ AArch64_LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
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{ AArch64_LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
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||||
{ AArch64_LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
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{ AArch64_LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
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{ AArch64_LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
|
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{ AArch64_LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
|
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{ AArch64_LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
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{ AArch64_LD3Threev16b, "ld3", ".16b", 0, false, 0 },
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{ AArch64_LD3Threev8h, "ld3", ".8h", 0, false, 0 },
|
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{ AArch64_LD3Threev4s, "ld3", ".4s", 0, false, 0 },
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||||
{ AArch64_LD3Threev2d, "ld3", ".2d", 0, false, 0 },
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||||
{ AArch64_LD3Threev8b, "ld3", ".8b", 0, false, 0 },
|
||||
{ AArch64_LD3Threev4h, "ld3", ".4h", 0, false, 0 },
|
||||
{ AArch64_LD3Threev2s, "ld3", ".2s", 0, false, 0 },
|
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{ AArch64_LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
|
||||
{ AArch64_LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
|
||||
{ AArch64_LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
|
||||
{ AArch64_LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
|
||||
{ AArch64_LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
|
||||
{ AArch64_LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
|
||||
{ AArch64_LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
|
||||
{ AArch64_LD4i8, "ld4", ".b", 1, true, 0 },
|
||||
{ AArch64_LD4i16, "ld4", ".h", 1, true, 0 },
|
||||
{ AArch64_LD4i32, "ld4", ".s", 1, true, 0 },
|
||||
{ AArch64_LD4i64, "ld4", ".d", 1, true, 0 },
|
||||
{ AArch64_LD4i8_POST, "ld4", ".b", 2, true, 4 },
|
||||
{ AArch64_LD4i16_POST, "ld4", ".h", 2, true, 8 },
|
||||
{ AArch64_LD4i32_POST, "ld4", ".s", 2, true, 16 },
|
||||
{ AArch64_LD4i64_POST, "ld4", ".d", 2, true, 32 },
|
||||
{ AArch64_LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
|
||||
{ AArch64_LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
|
||||
{ AArch64_LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
|
||||
{ AArch64_LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
|
||||
{ AArch64_LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
|
||||
{ AArch64_LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
|
||||
{ AArch64_LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
|
||||
{ AArch64_LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
|
||||
{ AArch64_LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
|
||||
{ AArch64_LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
|
||||
{ AArch64_LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
|
||||
{ AArch64_LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
|
||||
{ AArch64_LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
|
||||
{ AArch64_LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
|
||||
{ AArch64_LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
|
||||
{ AArch64_LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
|
||||
{ AArch64_LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
|
||||
{ AArch64_LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
|
||||
{ AArch64_LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
|
||||
{ AArch64_LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
|
||||
{ AArch64_LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
|
||||
{ AArch64_LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
|
||||
{ AArch64_LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
|
||||
{ AArch64_LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
|
||||
{ AArch64_LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
|
||||
{ AArch64_LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
|
||||
{ AArch64_LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
|
||||
{ AArch64_LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
|
||||
{ AArch64_LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
|
||||
{ AArch64_LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
|
||||
{ AArch64_ST1i8, "st1", ".b", 0, true, 0 },
|
||||
{ AArch64_ST1i16, "st1", ".h", 0, true, 0 },
|
||||
{ AArch64_ST1i32, "st1", ".s", 0, true, 0 },
|
||||
{ AArch64_ST1i64, "st1", ".d", 0, true, 0 },
|
||||
{ AArch64_ST1i8_POST, "st1", ".b", 1, true, 1 },
|
||||
{ AArch64_ST1i16_POST, "st1", ".h", 1, true, 2 },
|
||||
{ AArch64_ST1i32_POST, "st1", ".s", 1, true, 4 },
|
||||
{ AArch64_ST1i64_POST, "st1", ".d", 1, true, 8 },
|
||||
{ AArch64_ST1Onev16b, "st1", ".16b", 0, false, 0 },
|
||||
{ AArch64_ST1Onev8h, "st1", ".8h", 0, false, 0 },
|
||||
{ AArch64_ST1Onev4s, "st1", ".4s", 0, false, 0 },
|
||||
{ AArch64_ST1Onev2d, "st1", ".2d", 0, false, 0 },
|
||||
{ AArch64_ST1Onev8b, "st1", ".8b", 0, false, 0 },
|
||||
{ AArch64_ST1Onev4h, "st1", ".4h", 0, false, 0 },
|
||||
{ AArch64_ST1Onev2s, "st1", ".2s", 0, false, 0 },
|
||||
{ AArch64_ST1Onev1d, "st1", ".1d", 0, false, 0 },
|
||||
{ AArch64_ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
|
||||
{ AArch64_ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
|
||||
{ AArch64_ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
|
||||
{ AArch64_ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
|
||||
{ AArch64_ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
|
||||
{ AArch64_ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
|
||||
{ AArch64_ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
|
||||
{ AArch64_ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
|
||||
{ AArch64_ST1Twov16b, "st1", ".16b", 0, false, 0 },
|
||||
{ AArch64_ST1Twov8h, "st1", ".8h", 0, false, 0 },
|
||||
{ AArch64_ST1Twov4s, "st1", ".4s", 0, false, 0 },
|
||||
{ AArch64_ST1Twov2d, "st1", ".2d", 0, false, 0 },
|
||||
{ AArch64_ST1Twov8b, "st1", ".8b", 0, false, 0 },
|
||||
{ AArch64_ST1Twov4h, "st1", ".4h", 0, false, 0 },
|
||||
{ AArch64_ST1Twov2s, "st1", ".2s", 0, false, 0 },
|
||||
{ AArch64_ST1Twov1d, "st1", ".1d", 0, false, 0 },
|
||||
{ AArch64_ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
|
||||
{ AArch64_ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
|
||||
{ AArch64_ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
|
||||
{ AArch64_ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
|
||||
{ AArch64_ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
|
||||
{ AArch64_ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
|
||||
{ AArch64_ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
|
||||
{ AArch64_ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
|
||||
{ AArch64_ST1Threev16b, "st1", ".16b", 0, false, 0 },
|
||||
{ AArch64_ST1Threev8h, "st1", ".8h", 0, false, 0 },
|
||||
{ AArch64_ST1Threev4s, "st1", ".4s", 0, false, 0 },
|
||||
{ AArch64_ST1Threev2d, "st1", ".2d", 0, false, 0 },
|
||||
{ AArch64_ST1Threev8b, "st1", ".8b", 0, false, 0 },
|
||||
{ AArch64_ST1Threev4h, "st1", ".4h", 0, false, 0 },
|
||||
{ AArch64_ST1Threev2s, "st1", ".2s", 0, false, 0 },
|
||||
{ AArch64_ST1Threev1d, "st1", ".1d", 0, false, 0 },
|
||||
{ AArch64_ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
|
||||
{ AArch64_ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
|
||||
{ AArch64_ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
|
||||
{ AArch64_ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
|
||||
{ AArch64_ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
|
||||
{ AArch64_ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
|
||||
{ AArch64_ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
|
||||
{ AArch64_ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
|
||||
{ AArch64_ST1Fourv16b, "st1", ".16b", 0, false, 0 },
|
||||
{ AArch64_ST1Fourv8h, "st1", ".8h", 0, false, 0 },
|
||||
{ AArch64_ST1Fourv4s, "st1", ".4s", 0, false, 0 },
|
||||
{ AArch64_ST1Fourv2d, "st1", ".2d", 0, false, 0 },
|
||||
{ AArch64_ST1Fourv8b, "st1", ".8b", 0, false, 0 },
|
||||
{ AArch64_ST1Fourv4h, "st1", ".4h", 0, false, 0 },
|
||||
{ AArch64_ST1Fourv2s, "st1", ".2s", 0, false, 0 },
|
||||
{ AArch64_ST1Fourv1d, "st1", ".1d", 0, false, 0 },
|
||||
{ AArch64_ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
|
||||
{ AArch64_ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
|
||||
{ AArch64_ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
|
||||
{ AArch64_ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
|
||||
{ AArch64_ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
|
||||
{ AArch64_ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
|
||||
{ AArch64_ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
|
||||
{ AArch64_ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
|
||||
{ AArch64_ST2i8, "st2", ".b", 0, true, 0 },
|
||||
{ AArch64_ST2i16, "st2", ".h", 0, true, 0 },
|
||||
{ AArch64_ST2i32, "st2", ".s", 0, true, 0 },
|
||||
{ AArch64_ST2i64, "st2", ".d", 0, true, 0 },
|
||||
{ AArch64_ST2i8_POST, "st2", ".b", 1, true, 2 },
|
||||
{ AArch64_ST2i16_POST, "st2", ".h", 1, true, 4 },
|
||||
{ AArch64_ST2i32_POST, "st2", ".s", 1, true, 8 },
|
||||
{ AArch64_ST2i64_POST, "st2", ".d", 1, true, 16 },
|
||||
{ AArch64_ST2Twov16b, "st2", ".16b", 0, false, 0 },
|
||||
{ AArch64_ST2Twov8h, "st2", ".8h", 0, false, 0 },
|
||||
{ AArch64_ST2Twov4s, "st2", ".4s", 0, false, 0 },
|
||||
{ AArch64_ST2Twov2d, "st2", ".2d", 0, false, 0 },
|
||||
{ AArch64_ST2Twov8b, "st2", ".8b", 0, false, 0 },
|
||||
{ AArch64_ST2Twov4h, "st2", ".4h", 0, false, 0 },
|
||||
{ AArch64_ST2Twov2s, "st2", ".2s", 0, false, 0 },
|
||||
{ AArch64_ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
|
||||
{ AArch64_ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
|
||||
{ AArch64_ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
|
||||
{ AArch64_ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
|
||||
{ AArch64_ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
|
||||
{ AArch64_ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
|
||||
{ AArch64_ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
|
||||
{ AArch64_ST3i8, "st3", ".b", 0, true, 0 },
|
||||
{ AArch64_ST3i16, "st3", ".h", 0, true, 0 },
|
||||
{ AArch64_ST3i32, "st3", ".s", 0, true, 0 },
|
||||
{ AArch64_ST3i64, "st3", ".d", 0, true, 0 },
|
||||
{ AArch64_ST3i8_POST, "st3", ".b", 1, true, 3 },
|
||||
{ AArch64_ST3i16_POST, "st3", ".h", 1, true, 6 },
|
||||
{ AArch64_ST3i32_POST, "st3", ".s", 1, true, 12 },
|
||||
{ AArch64_ST3i64_POST, "st3", ".d", 1, true, 24 },
|
||||
{ AArch64_ST3Threev16b, "st3", ".16b", 0, false, 0 },
|
||||
{ AArch64_ST3Threev8h, "st3", ".8h", 0, false, 0 },
|
||||
{ AArch64_ST3Threev4s, "st3", ".4s", 0, false, 0 },
|
||||
{ AArch64_ST3Threev2d, "st3", ".2d", 0, false, 0 },
|
||||
{ AArch64_ST3Threev8b, "st3", ".8b", 0, false, 0 },
|
||||
{ AArch64_ST3Threev4h, "st3", ".4h", 0, false, 0 },
|
||||
{ AArch64_ST3Threev2s, "st3", ".2s", 0, false, 0 },
|
||||
{ AArch64_ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
|
||||
{ AArch64_ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
|
||||
{ AArch64_ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
|
||||
{ AArch64_ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
|
||||
{ AArch64_ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
|
||||
{ AArch64_ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
|
||||
{ AArch64_ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
|
||||
{ AArch64_ST4i8, "st4", ".b", 0, true, 0 },
|
||||
{ AArch64_ST4i16, "st4", ".h", 0, true, 0 },
|
||||
{ AArch64_ST4i32, "st4", ".s", 0, true, 0 },
|
||||
{ AArch64_ST4i64, "st4", ".d", 0, true, 0 },
|
||||
{ AArch64_ST4i8_POST, "st4", ".b", 1, true, 4 },
|
||||
{ AArch64_ST4i16_POST, "st4", ".h", 1, true, 8 },
|
||||
{ AArch64_ST4i32_POST, "st4", ".s", 1, true, 16 },
|
||||
{ AArch64_ST4i64_POST, "st4", ".d", 1, true, 32 },
|
||||
{ AArch64_ST4Fourv16b, "st4", ".16b", 0, false, 0 },
|
||||
{ AArch64_ST4Fourv8h, "st4", ".8h", 0, false, 0 },
|
||||
{ AArch64_ST4Fourv4s, "st4", ".4s", 0, false, 0 },
|
||||
{ AArch64_ST4Fourv2d, "st4", ".2d", 0, false, 0 },
|
||||
{ AArch64_ST4Fourv8b, "st4", ".8b", 0, false, 0 },
|
||||
{ AArch64_ST4Fourv4h, "st4", ".4h", 0, false, 0 },
|
||||
{ AArch64_ST4Fourv2s, "st4", ".2s", 0, false, 0 },
|
||||
{ AArch64_ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
|
||||
{ AArch64_ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
|
||||
{ AArch64_ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
|
||||
{ AArch64_ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
|
||||
{ AArch64_ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
|
||||
{ AArch64_ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
|
||||
{ AArch64_ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
|
||||
};
|
||||
|
||||
static LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode)
|
||||
{
|
||||
unsigned Idx;
|
||||
|
||||
for (Idx = 0; Idx != ARR_SIZE(LdStNInstInfo); ++Idx)
|
||||
if (LdStNInstInfo[Idx].Opcode == Opcode)
|
||||
return &LdStNInstInfo[Idx];
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
SStream_concat(O, "[%s]", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName));
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM;
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = MCInst_getOperand(MI, OpNum);
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID;
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0;
|
||||
MI->flat_insn->detail->arm64.op_count++;
|
||||
}
|
||||
}
|
||||
|
||||
static void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O)
|
||||
{
|
||||
MCOperand *MO1 = MCInst_getOperand(MI, OpNum + 1);
|
||||
|
||||
SStream_concat(O, "[%s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName));
|
||||
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM;
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID;
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0;
|
||||
}
|
||||
|
||||
if (MCOperand_isImm(MO1)) {
|
||||
int64_t val = Scale * MCOperand_getImm(MO1);
|
||||
printInt64Bang(O, val);
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = val;
|
||||
}
|
||||
}
|
||||
|
||||
SStream_concat0(O, "]");
|
||||
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->arm64.op_count++;
|
||||
}
|
||||
}
|
||||
|
||||
static void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI)
|
||||
{
|
||||
printVectorList(MI, OpNum, O, "", MRI, 0, 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static bool printSysAlias(MCInst *MI, SStream *O)
|
||||
{
|
||||
// unsigned Opcode = MCInst_getOpcode(MI);
|
||||
@ -1693,20 +1246,6 @@ static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
#if 0
|
||||
// If the branch target is simply an address then print it in hex.
|
||||
const MCConstantExpr *BranchTarget =
|
||||
dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
|
||||
int64_t Address;
|
||||
if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
|
||||
O << "0x";
|
||||
O.write_hex(Address);
|
||||
} else {
|
||||
// Otherwise, just print the expression.
|
||||
O << *MI->getOperand(OpNum).getExpr();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user