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python: add access field for ARM64

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This commit is contained in:
Nguyen Anh Quynh 2016-04-12 13:42:07 +08:00
parent ae73149d67
commit c6397bf354
2 changed files with 23 additions and 0 deletions
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1
bindings/python/capstone/arm64.py
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@ -38,6 +38,7 @@ class Arm64Op(ctypes.Structure):
('ext', ctypes.c_uint),
('type', ctypes.c_uint),
('value', Arm64OpValue),
('access', ctypes.c_uint8),
)
@property

22
bindings/python/test_arm64.py
View File

@ -75,6 +75,14 @@ def print_insn_detail(insn):
if i.vector_index != -1:
print("\t\t\tVector Index: %u" % i.vector_index)
if i.access == CS_AC_READ:
print("\t\toperands[%u].access: READ\n" % (c))
elif i.access == CS_AC_WRITE:
print("\t\toperands[%u].access: WRITE\n" % (c))
elif i.access == CS_AC_READ | CS_AC_WRITE:
print("\t\toperands[%u].access: READ | WRITE\n" % (c))
if insn.writeback:
print("\tWrite-back: True")
if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
@ -82,6 +90,20 @@ def print_insn_detail(insn):
if insn.update_flags:
print("\tUpdate-flags: True")
(regs_read, regs_write) = insn.regs_access()
if len(regs_read) > 0:
print("\tRegisters read:", end="")
for r in regs_read:
print(" %s" %(insn.reg_name(r)), end="")
print("")
if len(regs_write) > 0:
print("\tRegisters modified:", end="")
for r in regs_write:
print(" %s" %(insn.reg_name(r)), end="")
print("")
# ## Test class Cs
def test_class():