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Update AARCH64 to ARMv8.1-4 (minus tablegen stuff) (#1425)
* updates for armv8.1-4 * Update AArch64Disassembler.c * adding clang-format * fix tabs * fix indents * fix tabs * Update AArch64Disassembler.c * Update AArch64Disassembler.c * Update AArch64Disassembler.c * Update AArch64Disassembler.c * fix tables * revert disass * Update AArch64Disassembler.c * Update AArch64Disassembler.c * add AArch64InstPrinter new func stubs * Update AArch64Mapping.c * add baseinfo * fix dates * add AddressingModes.h * Update AArch64Disassembler.c * Update AArch64InstPrinter.c
This commit is contained in:
blacktop
Nguyen Anh Quynh
parent
e889a41e3a
commit
caa4a98e34
6
.clang-format
Normal file
6
.clang-format
Normal file
@ -0,0 +1,6 @@
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BraceWrapping:
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AfterClass: true
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AfterControlStatement: false
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AfterFunction: true
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BreakBeforeBraces: Custom
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UseTab: Always
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@ -83,3 +83,4 @@ Ilya Leoshkevich: SystemZ architecture improvements.
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Do Minh Tuan: Regression testing tool (cstest)
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david942j: BPF (both classic and extended) architecture.
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fanfuqiang & citypw & porto703 : RISCV architecture.
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Josh "blacktop" Maine: Arm64 architecture improvements.
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@ -15,7 +15,7 @@
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#define CS_AARCH64_ADDRESSINGMODES_H
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#include "../../MathExtras.h"
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@ -84,6 +84,21 @@ static inline unsigned AArch64_AM_getShiftValue(unsigned Imm)
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return Imm & 0x3f;
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}
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static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST, unsigned Imm)
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{
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// assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
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unsigned STEnc = 0;
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switch (ST) {
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default: // llvm_unreachable("Invalid shift requested");
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case AArch64_AM_LSL: STEnc = 0; break;
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case AArch64_AM_LSR: STEnc = 1; break;
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case AArch64_AM_ASR: STEnc = 2; break;
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case AArch64_AM_ROR: STEnc = 3; break;
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case AArch64_AM_MSL: STEnc = 4; break;
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}
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return (STEnc << 6) | (Imm & 0x3f);
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}
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//===----------------------------------------------------------------------===//
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// Extends
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//
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@ -116,11 +131,149 @@ static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned
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return AArch64_AM_getExtendType((Imm >> 3) & 0x7);
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}
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/// Mapping from extend bits to required operation:
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/// shifter: 000 ==> uxtb
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/// 001 ==> uxth
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/// 010 ==> uxtw
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/// 011 ==> uxtx
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/// 100 ==> sxtb
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/// 101 ==> sxth
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/// 110 ==> sxtw
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/// 111 ==> sxtx
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inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET)
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{
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switch (ET) {
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default: // llvm_unreachable("Invalid extend type requested");
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case AArch64_AM_UXTB: return 0; break;
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case AArch64_AM_UXTH: return 1; break;
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case AArch64_AM_UXTW: return 2; break;
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case AArch64_AM_UXTX: return 3; break;
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case AArch64_AM_SXTB: return 4; break;
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case AArch64_AM_SXTH: return 5; break;
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case AArch64_AM_SXTW: return 6; break;
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case AArch64_AM_SXTX: return 7; break;
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}
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}
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/// getArithExtendImm - Encode the extend type and shift amount for an
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/// arithmetic instruction:
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/// imm: 3-bit extend amount
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/// {5-3} = shifter
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/// {2-0} = imm3
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static inline unsigned AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm)
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{
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// assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!");
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return (getExtendEncoding(ET) << 3) | (Imm & 0x7);
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}
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/// getMemDoShift - Extract the "do shift" flag value for load/store
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/// instructions.
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static inline bool AArch64_AM_getMemDoShift(unsigned Imm)
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{
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return (Imm & 0x1) != 0;
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}
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/// getExtendType - Extract the extend type for the offset operand of
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/// loads/stores.
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static inline AArch64_AM_ShiftExtendType AArch64_AM_getMemExtendType(unsigned Imm)
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{
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return AArch64_AM_getMemExtendType((Imm >> 1) & 0x7);
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}
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/// getExtendImm - Encode the extend type and amount for a load/store inst:
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/// doshift: should the offset be scaled by the access size
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/// shifter: 000 ==> uxtb
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/// 001 ==> uxth
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/// 010 ==> uxtw
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/// 011 ==> uxtx
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/// 100 ==> sxtb
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/// 101 ==> sxth
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/// 110 ==> sxtw
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/// 111 ==> sxtx
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/// {3-1} = shifter
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/// {0} = doshift
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static inline unsigned AArch64_AM_getMemExtendImm(AArch64_AM_ShiftExtendType ET, bool DoShift)
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{
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return (getExtendEncoding(ET) << 1) | unsigned(DoShift);
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}
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static inline uint64_t ror(uint64_t elt, unsigned size)
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{
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return ((elt & 1) << (size-1)) | (elt >> 1);
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}
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/// processLogicalImmediate - Determine if an immediate value can be encoded
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/// as the immediate operand of a logical instruction for the given register
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/// size. If so, return true with "encoding" set to the encoded value in
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/// the form N:immr:imms.
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static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t &Encoding)
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{
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if (Imm == 0ULL || Imm == ~0ULL ||
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(RegSize != 64 && (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) {
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return false;
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}
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// First, determine the element size.
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unsigned Size = RegSize;
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do {
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Size /= 2;
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uint64_t Mask = (1ULL << Size) - 1;
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if ((Imm & Mask) != ((Imm >> Size) & Mask)) {
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Size *= 2;
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break;
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}
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} while (Size > 2);
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// Second, determine the rotation to make the element be: 0^m 1^n.
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uint32_t CTO, I;
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uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size);
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Imm &= Mask;
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if (isShiftedMask_64(Imm)) {
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I = countTrailingZeros(Imm);
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// assert(I < 64 && "undefined behavior");
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CTO = countTrailingOnes(Imm >> I);
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} else {
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Imm |= ~Mask;
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if (!isShiftedMask_64(~Imm))
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return false;
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unsigned CLO = countLeadingOnes(Imm);
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I = 64 - CLO;
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CTO = CLO + countTrailingOnes(Imm) - (64 - Size);
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}
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// Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
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// to our target value, where I is the number of RORs to go the opposite
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// direction.
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// assert(Size > I && "I should be smaller than element size");
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unsigned Immr = (Size - I) & (Size - 1);
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// If size has a 1 in the n'th bit, create a value that has zeroes in
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// bits [0, n] and ones above that.
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uint64_t NImms = ~(Size-1) << 1;
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// Or the CTO value into the low bits, which must be below the Nth bit
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// bit mentioned above.
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NImms |= (CTO-1);
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// Extract the seventh bit and toggle it to create the N field.
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unsigned N = ((NImms >> 6) & 1) ^ 1;
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Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);
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return true;
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}
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/// isLogicalImmediate - Return true if the immediate is valid for a logical
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/// immediate instruction of the given register size. Return false otherwise.
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static inline bool AArch64_AM_isLogicalImmediate(uint64_t imm, unsigned regSize)
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{
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uint64_t encoding;
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return AArch64_AM_processLogicalImmediate(imm, regSize, encoding);
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}
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/// encodeLogicalImmediate - Return the encoded immediate value for a logical
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/// immediate instruction of the given register size.
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static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm, unsigned regSize)
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{
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uint64_t encoding = 0;
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bool res = AArch64_AM_processLogicalImmediate(imm, regSize, encoding);
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// assert(res && "invalid logical immediate");
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(void)res;
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return encoding;
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}
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/// decodeLogicalImmediate - Decode a logical immediate value in the form
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/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
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/// integer value it represents with regSize bits.
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@ -207,19 +360,570 @@ static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
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return FPUnion.F;
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}
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/// getFP16Imm - Return an 8-bit floating-point version of the 16-bit
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/// floating-point value. If the value cannot be represented as an 8-bit
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/// floating-point value, then return -1.
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static inline int AArch64_AM_getFP16Imm(const APInt &Imm)
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{
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uint32_t Sign = Imm.lshr(15).getZExtValue() & 1;
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int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15; // -14 to 15
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int32_t Mantissa = Imm.getZExtValue() & 0x3ff; // 10 bits
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// We can handle 4 bits of mantissa.
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// mantissa = (16+UInt(e:f:g:h))/16.
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if (Mantissa & 0x3f)
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return -1;
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Mantissa >>= 6;
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// We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
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if (Exp < -3 || Exp > 4)
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return -1;
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Exp = ((Exp + 3) & 0x7) ^ 4;
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return ((int)Sign << 7) | (Exp << 4) | Mantissa;
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}
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static inline int getFP16Imm(const APFloat &FPImm)
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{
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return getFP16Imm(FPImm.bitcastToAPInt());
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}
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/// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
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/// floating-point value. If the value cannot be represented as an 8-bit
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/// floating-point value, then return -1.
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static inline int AArch64_AM_getFP32Imm(const APInt &Imm)
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{
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uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
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int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
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int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
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// We can handle 4 bits of mantissa.
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// mantissa = (16+UInt(e:f:g:h))/16.
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if (Mantissa & 0x7ffff)
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return -1;
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Mantissa >>= 19;
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if ((Mantissa & 0xf) != Mantissa)
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return -1;
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// We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
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if (Exp < -3 || Exp > 4)
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return -1;
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Exp = ((Exp + 3) & 0x7) ^ 4;
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return ((int)Sign << 7) | (Exp << 4) | Mantissa;
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}
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static inline int AArch64_AM_getFP32Imm(const APFloat &FPImm)
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{
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return getFP32Imm(FPImm.bitcastToAPInt());
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}
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/// getFP64Imm - Return an 8-bit floating-point version of the 64-bit
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/// floating-point value. If the value cannot be represented as an 8-bit
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/// floating-point value, then return -1.
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static inline int AArch64_AM_getFP64Imm(const APInt &Imm)
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{
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uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
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int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
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uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
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// We can handle 4 bits of mantissa.
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// mantissa = (16+UInt(e:f:g:h))/16.
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if (Mantissa & 0xffffffffffffULL)
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return -1;
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Mantissa >>= 48;
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if ((Mantissa & 0xf) != Mantissa)
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return -1;
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// We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
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if (Exp < -3 || Exp > 4)
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return -1;
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Exp = ((Exp + 3) & 0x7) ^ 4;
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return ((int)Sign << 7) | (Exp << 4) | Mantissa;
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}
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static inline int AArch64_AM_getFP64Imm(const APFloat &FPImm)
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{
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return getFP64Imm(FPImm.bitcastToAPInt());
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}
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//===--------------------------------------------------------------------===//
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// AdvSIMD Modified Immediates
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//===--------------------------------------------------------------------===//
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// 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh
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static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0xffffff00ffffff00ULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm)
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{
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return (Imm & 0xffULL);
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}
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static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm)
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{
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uint64_t EncVal = Imm;
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return (EncVal << 32) | EncVal;
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}
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// 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00
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static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0xffff00ffffff00ffULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm)
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{
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return (Imm & 0xff00ULL) >> 8;
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}
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static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm)
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{
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uint64_t EncVal = Imm;
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return (EncVal << 40) | (EncVal << 8);
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}
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// 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00
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static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0xff00ffffff00ffffULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm)
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{
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return (Imm & 0xff0000ULL) >> 16;
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}
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static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm)
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{
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uint64_t EncVal = Imm;
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return (EncVal << 48) | (EncVal << 16);
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}
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// abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00
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static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0x00ffffff00ffffffULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm)
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{
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return (Imm & 0xff000000ULL) >> 24;
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}
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static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm)
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{
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uint64_t EncVal = Imm;
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return (EncVal << 56) | (EncVal << 24);
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}
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// 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh
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static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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(((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
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((Imm & 0xff00ff00ff00ff00ULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm)
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{
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return (Imm & 0xffULL);
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}
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static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm)
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{
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uint64_t EncVal = Imm;
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return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal;
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}
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// abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00
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static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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(((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
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((Imm & 0x00ff00ff00ff00ffULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm)
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{
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return (Imm & 0xff00ULL) >> 8;
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}
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static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm)
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{
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uint64_t EncVal = Imm;
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return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8);
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}
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// 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF
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static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm)
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{
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return (Imm & 0xff00ULL) >> 8;
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}
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|
||||
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm)
|
||||
{
|
||||
uint64_t EncVal = Imm;
|
||||
return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL;
|
||||
}
|
||||
|
||||
// 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF
|
||||
static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm)
|
||||
{
|
||||
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
||||
((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
|
||||
}
|
||||
|
||||
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm)
|
||||
{
|
||||
uint64_t EncVal = Imm;
|
||||
return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL;
|
||||
}
|
||||
|
||||
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm)
|
||||
{
|
||||
return (Imm & 0x00ff0000ULL) >> 16;
|
||||
}
|
||||
|
||||
// abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh
|
||||
static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm)
|
||||
{
|
||||
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
||||
((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
|
||||
((Imm >> 56) == (Imm & 0x000000ffULL));
|
||||
}
|
||||
|
||||
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm)
|
||||
{
|
||||
return (Imm & 0xffULL);
|
||||
}
|
||||
|
||||
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType9(uint8_t Imm)
|
||||
{
|
||||
uint64_t EncVal = Imm;
|
||||
EncVal |= (EncVal << 8);
|
||||
EncVal |= (EncVal << 16);
|
||||
EncVal |= (EncVal << 32);
|
||||
return EncVal;
|
||||
}
|
||||
|
||||
// aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
|
||||
// cmode: 1110, op: 1
|
||||
static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm)
|
||||
{
|
||||
uint64_t ByteA = Imm & 0xff00000000000000ULL;
|
||||
uint64_t ByteB = Imm & 0x00ff000000000000ULL;
|
||||
uint64_t ByteC = Imm & 0x0000ff0000000000ULL;
|
||||
uint64_t ByteD = Imm & 0x000000ff00000000ULL;
|
||||
uint64_t ByteE = Imm & 0x00000000ff000000ULL;
|
||||
uint64_t ByteF = Imm & 0x0000000000ff0000ULL;
|
||||
uint64_t ByteG = Imm & 0x000000000000ff00ULL;
|
||||
uint64_t ByteH = Imm & 0x00000000000000ffULL;
|
||||
|
||||
return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
|
||||
(ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
|
||||
(ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
|
||||
(ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
|
||||
(ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
|
||||
(ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
|
||||
(ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
|
||||
(ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
|
||||
}
|
||||
|
||||
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm)
|
||||
{
|
||||
uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0;
|
||||
uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0;
|
||||
uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0;
|
||||
uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0;
|
||||
uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0;
|
||||
uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0;
|
||||
uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0;
|
||||
uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0;
|
||||
|
||||
uint8_t EncVal = BitA;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitB;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitC;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitD;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitE;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitF;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitG;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitH;
|
||||
return EncVal;
|
||||
}
|
||||
|
||||
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm)
|
||||
{
|
||||
static const uint32_t lookup[16] = {
|
||||
0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
|
||||
0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
|
||||
0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff,
|
||||
0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff
|
||||
};
|
||||
return lookup[Imm & 0x0f] | ((uint64_t)lookup[Imm >> 4] << 32);
|
||||
uint64_t EncVal = 0;
|
||||
if (Imm & 0x80)
|
||||
EncVal |= 0xff00000000000000ULL;
|
||||
if (Imm & 0x40)
|
||||
EncVal |= 0x00ff000000000000ULL;
|
||||
if (Imm & 0x20)
|
||||
EncVal |= 0x0000ff0000000000ULL;
|
||||
if (Imm & 0x10)
|
||||
EncVal |= 0x000000ff00000000ULL;
|
||||
if (Imm & 0x08)
|
||||
EncVal |= 0x00000000ff000000ULL;
|
||||
if (Imm & 0x04)
|
||||
EncVal |= 0x0000000000ff0000ULL;
|
||||
if (Imm & 0x02)
|
||||
EncVal |= 0x000000000000ff00ULL;
|
||||
if (Imm & 0x01)
|
||||
EncVal |= 0x00000000000000ffULL;
|
||||
return EncVal;
|
||||
}
|
||||
|
||||
// aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00
|
||||
static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm)
|
||||
{
|
||||
uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
|
||||
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
||||
(BString == 0x1f || BString == 0x20) &&
|
||||
((Imm & 0x0007ffff0007ffffULL) == 0);
|
||||
}
|
||||
|
||||
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm)
|
||||
{
|
||||
uint8_t BitA = (Imm & 0x80000000ULL) != 0;
|
||||
uint8_t BitB = (Imm & 0x20000000ULL) != 0;
|
||||
uint8_t BitC = (Imm & 0x01000000ULL) != 0;
|
||||
uint8_t BitD = (Imm & 0x00800000ULL) != 0;
|
||||
uint8_t BitE = (Imm & 0x00400000ULL) != 0;
|
||||
uint8_t BitF = (Imm & 0x00200000ULL) != 0;
|
||||
uint8_t BitG = (Imm & 0x00100000ULL) != 0;
|
||||
uint8_t BitH = (Imm & 0x00080000ULL) != 0;
|
||||
|
||||
uint8_t EncVal = BitA;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitB;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitC;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitD;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitE;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitF;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitG;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitH;
|
||||
return EncVal;
|
||||
}
|
||||
|
||||
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType11(uint8_t Imm)
|
||||
{
|
||||
uint64_t EncVal = 0;
|
||||
if (Imm & 0x80)
|
||||
EncVal |= 0x80000000ULL;
|
||||
if (Imm & 0x40)
|
||||
EncVal |= 0x3e000000ULL;
|
||||
else
|
||||
EncVal |= 0x40000000ULL;
|
||||
if (Imm & 0x20)
|
||||
EncVal |= 0x01000000ULL;
|
||||
if (Imm & 0x10)
|
||||
EncVal |= 0x00800000ULL;
|
||||
if (Imm & 0x08)
|
||||
EncVal |= 0x00400000ULL;
|
||||
if (Imm & 0x04)
|
||||
EncVal |= 0x00200000ULL;
|
||||
if (Imm & 0x02)
|
||||
EncVal |= 0x00100000ULL;
|
||||
if (Imm & 0x01)
|
||||
EncVal |= 0x00080000ULL;
|
||||
return (EncVal << 32) | EncVal;
|
||||
}
|
||||
|
||||
// aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00
|
||||
static inline bool AArch64_AM_isAdvSIMDModImmType12(uint64_t Imm)
|
||||
{
|
||||
uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;
|
||||
return ((BString == 0xff || BString == 0x100) &&
|
||||
((Imm & 0x0000ffffffffffffULL) == 0));
|
||||
}
|
||||
|
||||
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm)
|
||||
{
|
||||
uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0;
|
||||
uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0;
|
||||
uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0;
|
||||
uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0;
|
||||
uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0;
|
||||
uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0;
|
||||
uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0;
|
||||
uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0;
|
||||
|
||||
uint8_t EncVal = BitA;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitB;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitC;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitD;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitE;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitF;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitG;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitH;
|
||||
return EncVal;
|
||||
}
|
||||
|
||||
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm)
|
||||
{
|
||||
uint64_t EncVal = 0;
|
||||
if (Imm & 0x80)
|
||||
EncVal |= 0x8000000000000000ULL;
|
||||
if (Imm & 0x40)
|
||||
EncVal |= 0x3fc0000000000000ULL;
|
||||
else
|
||||
EncVal |= 0x4000000000000000ULL;
|
||||
if (Imm & 0x20)
|
||||
EncVal |= 0x0020000000000000ULL;
|
||||
if (Imm & 0x10)
|
||||
EncVal |= 0x0010000000000000ULL;
|
||||
if (Imm & 0x08)
|
||||
EncVal |= 0x0008000000000000ULL;
|
||||
if (Imm & 0x04)
|
||||
EncVal |= 0x0004000000000000ULL;
|
||||
if (Imm & 0x02)
|
||||
EncVal |= 0x0002000000000000ULL;
|
||||
if (Imm & 0x01)
|
||||
EncVal |= 0x0001000000000000ULL;
|
||||
return (EncVal << 32) | EncVal;
|
||||
}
|
||||
|
||||
/// Returns true if Imm is the concatenation of a repeating pattern of type T.
|
||||
// static inline bool AArch64_AM_isSVEMaskOfIdenticalElements(int64_t Imm)
|
||||
// {
|
||||
// union {
|
||||
// int64_t Whole;
|
||||
// T Parts[sizeof(int64_t) / sizeof(T)];
|
||||
// } Vec{Imm};
|
||||
|
||||
// return all_of(Vec.Parts, [Vec](T Elem) { return Elem == Vec.Parts[0]; });
|
||||
// }
|
||||
|
||||
// /// Returns true if Imm is valid for CPY/DUP.
|
||||
// static inline bool AArch64_AM_isSVECpyImm(int64_t Imm)
|
||||
// {
|
||||
// bool IsImm8 = int8_t(Imm) == Imm;
|
||||
// bool IsImm16 = int16_t(Imm & ~0xff) == Imm;
|
||||
|
||||
// if (std::is_same<int8_t, typename std::make_signed<T>::type>::value)
|
||||
// return IsImm8 || uint8_t(Imm) == Imm;
|
||||
|
||||
// if (std::is_same<int16_t, typename std::make_signed<T>::type>::value)
|
||||
// return IsImm8 || IsImm16 || uint16_t(Imm & ~0xff) == Imm;
|
||||
|
||||
// return IsImm8 || IsImm16;
|
||||
// }
|
||||
|
||||
// /// Returns true if Imm is valid for ADD/SUB.
|
||||
// static inline bool AArch64_AM_isSVEAddSubImm(int64_t Imm)
|
||||
// {
|
||||
// bool IsInt8t =
|
||||
// std::is_same<int8_t, typename std::make_signed<T>::type>::value;
|
||||
// return uint8_t(Imm) == Imm || (!IsInt8t && uint16_t(Imm & ~0xff) == Imm);
|
||||
// }
|
||||
|
||||
/// Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.
|
||||
static inline bool AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm)
|
||||
{
|
||||
union {
|
||||
int64_t D;
|
||||
int32_t S[2];
|
||||
int16_t H[4];
|
||||
int8_t B[8];
|
||||
} Vec = {Imm};
|
||||
|
||||
if (isSVECpyImm<int64_t>(Vec.D))
|
||||
return false;
|
||||
|
||||
if (isSVEMaskOfIdenticalElements<int32_t>(Imm) &&
|
||||
isSVECpyImm<int32_t>(Vec.S[0]))
|
||||
return false;
|
||||
|
||||
if (isSVEMaskOfIdenticalElements<int16_t>(Imm) &&
|
||||
isSVECpyImm<int16_t>(Vec.H[0]))
|
||||
return false;
|
||||
|
||||
if (isSVEMaskOfIdenticalElements<int8_t>(Imm) &&
|
||||
isSVECpyImm<int8_t>(Vec.B[0]))
|
||||
return false;
|
||||
|
||||
return isLogicalImmediate(Vec.D, 64);
|
||||
}
|
||||
|
||||
inline static bool AArch64_AM_isAnyMOVZMovAlias(uint64_t Value, int RegWidth)
|
||||
{
|
||||
for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16)
|
||||
if ((Value & ~(0xffffULL << Shift)) == 0)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
inline static bool AArch64_AM_isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
|
||||
{
|
||||
if (RegWidth == 32)
|
||||
Value &= 0xffffffffULL;
|
||||
|
||||
// "lsl #0" takes precedence: in practice this only affects "#0, lsl #0".
|
||||
if (Value == 0 && Shift != 0)
|
||||
return false;
|
||||
|
||||
return (Value & ~(0xffffULL << Shift)) == 0;
|
||||
}
|
||||
|
||||
inline static bool AArch64_AM_isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth)
|
||||
{
|
||||
// MOVZ takes precedence over MOVN.
|
||||
if (isAnyMOVZMovAlias(Value, RegWidth))
|
||||
return false;
|
||||
|
||||
Value = ~Value;
|
||||
if (RegWidth == 32)
|
||||
Value &= 0xffffffffULL;
|
||||
|
||||
return isMOVZMovAlias(Value, Shift, RegWidth);
|
||||
}
|
||||
|
||||
inline static bool AArch64_AM_isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
|
||||
{
|
||||
if (isAnyMOVZMovAlias(Value, RegWidth))
|
||||
return true;
|
||||
|
||||
// It's not a MOVZ, but it might be a MOVN.
|
||||
Value = ~Value;
|
||||
if (RegWidth == 32)
|
||||
Value &= 0xffffffffULL;
|
||||
|
||||
return isAnyMOVZMovAlias(Value, RegWidth);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
#ifdef CAPSTONE_HAS_ARM64
|
||||
|
||||
@ -27,6 +27,7 @@
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "AArch64BaseInfo.h"
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
|
||||
const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid)
|
||||
{
|
||||
@ -98,534 +99,6 @@ static char *utostr(uint64_t X, bool isNeg)
|
||||
return result;
|
||||
}
|
||||
|
||||
static const A64NamedImmMapper_Mapping SysRegPairs[] = {
|
||||
{"pan", A64SysReg_PAN},
|
||||
{"uao", A64SysReg_UAO},
|
||||
{"osdtrrx_el1", A64SysReg_OSDTRRX_EL1},
|
||||
{"osdtrtx_el1", A64SysReg_OSDTRTX_EL1},
|
||||
{"teecr32_el1", A64SysReg_TEECR32_EL1},
|
||||
{"mdccint_el1", A64SysReg_MDCCINT_EL1},
|
||||
{"mdscr_el1", A64SysReg_MDSCR_EL1},
|
||||
{"dbgdtr_el0", A64SysReg_DBGDTR_EL0},
|
||||
{"oseccr_el1", A64SysReg_OSECCR_EL1},
|
||||
{"dbgvcr32_el2", A64SysReg_DBGVCR32_EL2},
|
||||
{"dbgbvr0_el1", A64SysReg_DBGBVR0_EL1},
|
||||
{"dbgbvr1_el1", A64SysReg_DBGBVR1_EL1},
|
||||
{"dbgbvr2_el1", A64SysReg_DBGBVR2_EL1},
|
||||
{"dbgbvr3_el1", A64SysReg_DBGBVR3_EL1},
|
||||
{"dbgbvr4_el1", A64SysReg_DBGBVR4_EL1},
|
||||
{"dbgbvr5_el1", A64SysReg_DBGBVR5_EL1},
|
||||
{"dbgbvr6_el1", A64SysReg_DBGBVR6_EL1},
|
||||
{"dbgbvr7_el1", A64SysReg_DBGBVR7_EL1},
|
||||
{"dbgbvr8_el1", A64SysReg_DBGBVR8_EL1},
|
||||
{"dbgbvr9_el1", A64SysReg_DBGBVR9_EL1},
|
||||
{"dbgbvr10_el1", A64SysReg_DBGBVR10_EL1},
|
||||
{"dbgbvr11_el1", A64SysReg_DBGBVR11_EL1},
|
||||
{"dbgbvr12_el1", A64SysReg_DBGBVR12_EL1},
|
||||
{"dbgbvr13_el1", A64SysReg_DBGBVR13_EL1},
|
||||
{"dbgbvr14_el1", A64SysReg_DBGBVR14_EL1},
|
||||
{"dbgbvr15_el1", A64SysReg_DBGBVR15_EL1},
|
||||
{"dbgbcr0_el1", A64SysReg_DBGBCR0_EL1},
|
||||
{"dbgbcr1_el1", A64SysReg_DBGBCR1_EL1},
|
||||
{"dbgbcr2_el1", A64SysReg_DBGBCR2_EL1},
|
||||
{"dbgbcr3_el1", A64SysReg_DBGBCR3_EL1},
|
||||
{"dbgbcr4_el1", A64SysReg_DBGBCR4_EL1},
|
||||
{"dbgbcr5_el1", A64SysReg_DBGBCR5_EL1},
|
||||
{"dbgbcr6_el1", A64SysReg_DBGBCR6_EL1},
|
||||
{"dbgbcr7_el1", A64SysReg_DBGBCR7_EL1},
|
||||
{"dbgbcr8_el1", A64SysReg_DBGBCR8_EL1},
|
||||
{"dbgbcr9_el1", A64SysReg_DBGBCR9_EL1},
|
||||
{"dbgbcr10_el1", A64SysReg_DBGBCR10_EL1},
|
||||
{"dbgbcr11_el1", A64SysReg_DBGBCR11_EL1},
|
||||
{"dbgbcr12_el1", A64SysReg_DBGBCR12_EL1},
|
||||
{"dbgbcr13_el1", A64SysReg_DBGBCR13_EL1},
|
||||
{"dbgbcr14_el1", A64SysReg_DBGBCR14_EL1},
|
||||
{"dbgbcr15_el1", A64SysReg_DBGBCR15_EL1},
|
||||
{"dbgwvr0_el1", A64SysReg_DBGWVR0_EL1},
|
||||
{"dbgwvr1_el1", A64SysReg_DBGWVR1_EL1},
|
||||
{"dbgwvr2_el1", A64SysReg_DBGWVR2_EL1},
|
||||
{"dbgwvr3_el1", A64SysReg_DBGWVR3_EL1},
|
||||
{"dbgwvr4_el1", A64SysReg_DBGWVR4_EL1},
|
||||
{"dbgwvr5_el1", A64SysReg_DBGWVR5_EL1},
|
||||
{"dbgwvr6_el1", A64SysReg_DBGWVR6_EL1},
|
||||
{"dbgwvr7_el1", A64SysReg_DBGWVR7_EL1},
|
||||
{"dbgwvr8_el1", A64SysReg_DBGWVR8_EL1},
|
||||
{"dbgwvr9_el1", A64SysReg_DBGWVR9_EL1},
|
||||
{"dbgwvr10_el1", A64SysReg_DBGWVR10_EL1},
|
||||
{"dbgwvr11_el1", A64SysReg_DBGWVR11_EL1},
|
||||
{"dbgwvr12_el1", A64SysReg_DBGWVR12_EL1},
|
||||
{"dbgwvr13_el1", A64SysReg_DBGWVR13_EL1},
|
||||
{"dbgwvr14_el1", A64SysReg_DBGWVR14_EL1},
|
||||
{"dbgwvr15_el1", A64SysReg_DBGWVR15_EL1},
|
||||
{"dbgwcr0_el1", A64SysReg_DBGWCR0_EL1},
|
||||
{"dbgwcr1_el1", A64SysReg_DBGWCR1_EL1},
|
||||
{"dbgwcr2_el1", A64SysReg_DBGWCR2_EL1},
|
||||
{"dbgwcr3_el1", A64SysReg_DBGWCR3_EL1},
|
||||
{"dbgwcr4_el1", A64SysReg_DBGWCR4_EL1},
|
||||
{"dbgwcr5_el1", A64SysReg_DBGWCR5_EL1},
|
||||
{"dbgwcr6_el1", A64SysReg_DBGWCR6_EL1},
|
||||
{"dbgwcr7_el1", A64SysReg_DBGWCR7_EL1},
|
||||
{"dbgwcr8_el1", A64SysReg_DBGWCR8_EL1},
|
||||
{"dbgwcr9_el1", A64SysReg_DBGWCR9_EL1},
|
||||
{"dbgwcr10_el1", A64SysReg_DBGWCR10_EL1},
|
||||
{"dbgwcr11_el1", A64SysReg_DBGWCR11_EL1},
|
||||
{"dbgwcr12_el1", A64SysReg_DBGWCR12_EL1},
|
||||
{"dbgwcr13_el1", A64SysReg_DBGWCR13_EL1},
|
||||
{"dbgwcr14_el1", A64SysReg_DBGWCR14_EL1},
|
||||
{"dbgwcr15_el1", A64SysReg_DBGWCR15_EL1},
|
||||
{"teehbr32_el1", A64SysReg_TEEHBR32_EL1},
|
||||
{"osdlr_el1", A64SysReg_OSDLR_EL1},
|
||||
{"dbgprcr_el1", A64SysReg_DBGPRCR_EL1},
|
||||
{"dbgclaimset_el1", A64SysReg_DBGCLAIMSET_EL1},
|
||||
{"dbgclaimclr_el1", A64SysReg_DBGCLAIMCLR_EL1},
|
||||
{"csselr_el1", A64SysReg_CSSELR_EL1},
|
||||
{"vpidr_el2", A64SysReg_VPIDR_EL2},
|
||||
{"vmpidr_el2", A64SysReg_VMPIDR_EL2},
|
||||
{"sctlr_el1", A64SysReg_SCTLR_EL1},
|
||||
{"sctlr_el12", A64SysReg_SCTLR_EL12},
|
||||
{"sctlr_el2", A64SysReg_SCTLR_EL2},
|
||||
{"sctlr_el3", A64SysReg_SCTLR_EL3},
|
||||
{"actlr_el1", A64SysReg_ACTLR_EL1},
|
||||
{"actlr_el2", A64SysReg_ACTLR_EL2},
|
||||
{"actlr_el3", A64SysReg_ACTLR_EL3},
|
||||
{"cpacr_el1", A64SysReg_CPACR_EL1},
|
||||
{"cpacr_el12", A64SysReg_CPACR_EL12},
|
||||
{"hcr_el2", A64SysReg_HCR_EL2},
|
||||
{"scr_el3", A64SysReg_SCR_EL3},
|
||||
{"mdcr_el2", A64SysReg_MDCR_EL2},
|
||||
{"sder32_el3", A64SysReg_SDER32_EL3},
|
||||
{"cptr_el2", A64SysReg_CPTR_EL2},
|
||||
{"cptr_el3", A64SysReg_CPTR_EL3},
|
||||
{"hstr_el2", A64SysReg_HSTR_EL2},
|
||||
{"hacr_el2", A64SysReg_HACR_EL2},
|
||||
{"mdcr_el3", A64SysReg_MDCR_EL3},
|
||||
{"ttbr0_el1", A64SysReg_TTBR0_EL1},
|
||||
{"ttbr0_el12", A64SysReg_TTBR0_EL12},
|
||||
{"ttbr0_el2", A64SysReg_TTBR0_EL2},
|
||||
{"ttbr0_el3", A64SysReg_TTBR0_EL3},
|
||||
{"ttbr1_el1", A64SysReg_TTBR1_EL1},
|
||||
{"ttbr1_el12", A64SysReg_TTBR1_EL12},
|
||||
{"ttbr1_el2", A64SysReg_TTBR1_EL2},
|
||||
{"tcr_el1", A64SysReg_TCR_EL1},
|
||||
{"tcr_el12", A64SysReg_TCR_EL12},
|
||||
{"tcr_el2", A64SysReg_TCR_EL2},
|
||||
{"tcr_el3", A64SysReg_TCR_EL3},
|
||||
{"vttbr_el2", A64SysReg_VTTBR_EL2},
|
||||
{"vtcr_el2", A64SysReg_VTCR_EL2},
|
||||
{"dacr32_el2", A64SysReg_DACR32_EL2},
|
||||
{"spsr_el1", A64SysReg_SPSR_EL1},
|
||||
{"spsr_el12", A64SysReg_SPSR_EL12},
|
||||
{"spsr_el2", A64SysReg_SPSR_EL2},
|
||||
{"spsr_el3", A64SysReg_SPSR_EL3},
|
||||
{"elr_el1", A64SysReg_ELR_EL1},
|
||||
{"elr_el12", A64SysReg_ELR_EL12},
|
||||
{"elr_el2", A64SysReg_ELR_EL2},
|
||||
{"elr_el3", A64SysReg_ELR_EL3},
|
||||
{"sp_el0", A64SysReg_SP_EL0},
|
||||
{"sp_el1", A64SysReg_SP_EL1},
|
||||
{"sp_el2", A64SysReg_SP_EL2},
|
||||
{"spsel", A64SysReg_SPSel},
|
||||
{"nzcv", A64SysReg_NZCV},
|
||||
{"daif", A64SysReg_DAIF},
|
||||
{"currentel", A64SysReg_CurrentEL},
|
||||
{"spsr_irq", A64SysReg_SPSR_irq},
|
||||
{"spsr_abt", A64SysReg_SPSR_abt},
|
||||
{"spsr_und", A64SysReg_SPSR_und},
|
||||
{"spsr_fiq", A64SysReg_SPSR_fiq},
|
||||
{"fpcr", A64SysReg_FPCR},
|
||||
{"fpsr", A64SysReg_FPSR},
|
||||
{"dspsr_el0", A64SysReg_DSPSR_EL0},
|
||||
{"dlr_el0", A64SysReg_DLR_EL0},
|
||||
{"ifsr32_el2", A64SysReg_IFSR32_EL2},
|
||||
{"afsr0_el1", A64SysReg_AFSR0_EL1},
|
||||
{"afsr0_el12", A64SysReg_AFSR0_EL12},
|
||||
{"afsr0_el2", A64SysReg_AFSR0_EL2},
|
||||
{"afsr0_el3", A64SysReg_AFSR0_EL3},
|
||||
{"afsr1_el1", A64SysReg_AFSR1_EL1},
|
||||
{"afsr1_el12", A64SysReg_AFSR1_EL12},
|
||||
{"afsr1_el2", A64SysReg_AFSR1_EL2},
|
||||
{"afsr1_el3", A64SysReg_AFSR1_EL3},
|
||||
{"esr_el1", A64SysReg_ESR_EL1},
|
||||
{"esr_el12", A64SysReg_ESR_EL12},
|
||||
{"esr_el2", A64SysReg_ESR_EL2},
|
||||
{"esr_el3", A64SysReg_ESR_EL3},
|
||||
{"fpexc32_el2", A64SysReg_FPEXC32_EL2},
|
||||
{"far_el1", A64SysReg_FAR_EL1},
|
||||
{"far_el12", A64SysReg_FAR_EL12},
|
||||
{"far_el2", A64SysReg_FAR_EL2},
|
||||
{"far_el3", A64SysReg_FAR_EL3},
|
||||
{"hpfar_el2", A64SysReg_HPFAR_EL2},
|
||||
{"par_el1", A64SysReg_PAR_EL1},
|
||||
{"pmcr_el0", A64SysReg_PMCR_EL0},
|
||||
{"pmcntenset_el0", A64SysReg_PMCNTENSET_EL0},
|
||||
{"pmcntenclr_el0", A64SysReg_PMCNTENCLR_EL0},
|
||||
{"pmovsclr_el0", A64SysReg_PMOVSCLR_EL0},
|
||||
{"pmselr_el0", A64SysReg_PMSELR_EL0},
|
||||
{"pmccntr_el0", A64SysReg_PMCCNTR_EL0},
|
||||
{"pmxevtyper_el0", A64SysReg_PMXEVTYPER_EL0},
|
||||
{"pmxevcntr_el0", A64SysReg_PMXEVCNTR_EL0},
|
||||
{"pmuserenr_el0", A64SysReg_PMUSERENR_EL0},
|
||||
{"pmintenset_el1", A64SysReg_PMINTENSET_EL1},
|
||||
{"pmintenclr_el1", A64SysReg_PMINTENCLR_EL1},
|
||||
{"pmovsset_el0", A64SysReg_PMOVSSET_EL0},
|
||||
{"mair_el1", A64SysReg_MAIR_EL1},
|
||||
{"mair_el12", A64SysReg_MAIR_EL12},
|
||||
{"mair_el2", A64SysReg_MAIR_EL2},
|
||||
{"mair_el3", A64SysReg_MAIR_EL3},
|
||||
{"amair_el1", A64SysReg_AMAIR_EL1},
|
||||
{"amair_el12", A64SysReg_AMAIR_EL12},
|
||||
{"amair_el2", A64SysReg_AMAIR_EL2},
|
||||
{"amair_el3", A64SysReg_AMAIR_EL3},
|
||||
{"vbar_el1", A64SysReg_VBAR_EL1},
|
||||
{"vbar_el12", A64SysReg_VBAR_EL12},
|
||||
{"vbar_el2", A64SysReg_VBAR_EL2},
|
||||
{"vbar_el3", A64SysReg_VBAR_EL3},
|
||||
{"rmr_el1", A64SysReg_RMR_EL1},
|
||||
{"rmr_el2", A64SysReg_RMR_EL2},
|
||||
{"rmr_el3", A64SysReg_RMR_EL3},
|
||||
{"contextidr_el1", A64SysReg_CONTEXTIDR_EL1},
|
||||
{"contextidr_el12", A64SysReg_CONTEXTIDR_EL12},
|
||||
{"contextidr_el2", A64SysReg_CONTEXTIDR_EL2},
|
||||
{"tpidr_el0", A64SysReg_TPIDR_EL0},
|
||||
{"tpidr_el2", A64SysReg_TPIDR_EL2},
|
||||
{"tpidr_el3", A64SysReg_TPIDR_EL3},
|
||||
{"tpidrro_el0", A64SysReg_TPIDRRO_EL0},
|
||||
{"tpidr_el1", A64SysReg_TPIDR_EL1},
|
||||
{"cntfrq_el0", A64SysReg_CNTFRQ_EL0},
|
||||
{"cntvoff_el2", A64SysReg_CNTVOFF_EL2},
|
||||
{"cntkctl_el1", A64SysReg_CNTKCTL_EL1},
|
||||
{"cntkctl_el12", A64SysReg_CNTKCTL_EL12},
|
||||
{"cnthctl_el2", A64SysReg_CNTHCTL_EL2},
|
||||
{"cntp_tval_el0", A64SysReg_CNTP_TVAL_EL0},
|
||||
{"cntp_tval_el02", A64SysReg_CNTP_TVAL_EL02},
|
||||
{"cnthp_tval_el2", A64SysReg_CNTHP_TVAL_EL2},
|
||||
{"cntps_tval_el1", A64SysReg_CNTPS_TVAL_EL1},
|
||||
{"cntp_ctl_el0", A64SysReg_CNTP_CTL_EL0},
|
||||
{"cnthp_ctl_el2", A64SysReg_CNTHP_CTL_EL2},
|
||||
{"cnthv_ctl_el2", A64SysReg_CNTHVCTL_EL2},
|
||||
{"cnthv_cval_el2", A64SysReg_CNTHV_CVAL_EL2},
|
||||
{"cnthv_tval_el2", A64SysReg_CNTHV_TVAL_EL2},
|
||||
{"cntps_ctl_el1", A64SysReg_CNTPS_CTL_EL1},
|
||||
{"cntp_cval_el0", A64SysReg_CNTP_CVAL_EL0},
|
||||
{"cntp_cval_el02", A64SysReg_CNTP_CVAL_EL02},
|
||||
{"cnthp_cval_el2", A64SysReg_CNTHP_CVAL_EL2},
|
||||
{"cntps_cval_el1", A64SysReg_CNTPS_CVAL_EL1},
|
||||
{"cntv_tval_el0", A64SysReg_CNTV_TVAL_EL0},
|
||||
{"cntv_tval_el02", A64SysReg_CNTV_TVAL_EL02},
|
||||
{"cntv_ctl_el0", A64SysReg_CNTV_CTL_EL0},
|
||||
{"cntv_ctl_el02", A64SysReg_CNTV_CTL_EL02},
|
||||
{"cntv_cval_el0", A64SysReg_CNTV_CVAL_EL0},
|
||||
{"cntv_cval_el02", A64SysReg_CNTV_CVAL_EL02},
|
||||
{"pmevcntr0_el0", A64SysReg_PMEVCNTR0_EL0},
|
||||
{"pmevcntr1_el0", A64SysReg_PMEVCNTR1_EL0},
|
||||
{"pmevcntr2_el0", A64SysReg_PMEVCNTR2_EL0},
|
||||
{"pmevcntr3_el0", A64SysReg_PMEVCNTR3_EL0},
|
||||
{"pmevcntr4_el0", A64SysReg_PMEVCNTR4_EL0},
|
||||
{"pmevcntr5_el0", A64SysReg_PMEVCNTR5_EL0},
|
||||
{"pmevcntr6_el0", A64SysReg_PMEVCNTR6_EL0},
|
||||
{"pmevcntr7_el0", A64SysReg_PMEVCNTR7_EL0},
|
||||
{"pmevcntr8_el0", A64SysReg_PMEVCNTR8_EL0},
|
||||
{"pmevcntr9_el0", A64SysReg_PMEVCNTR9_EL0},
|
||||
{"pmevcntr10_el0", A64SysReg_PMEVCNTR10_EL0},
|
||||
{"pmevcntr11_el0", A64SysReg_PMEVCNTR11_EL0},
|
||||
{"pmevcntr12_el0", A64SysReg_PMEVCNTR12_EL0},
|
||||
{"pmevcntr13_el0", A64SysReg_PMEVCNTR13_EL0},
|
||||
{"pmevcntr14_el0", A64SysReg_PMEVCNTR14_EL0},
|
||||
{"pmevcntr15_el0", A64SysReg_PMEVCNTR15_EL0},
|
||||
{"pmevcntr16_el0", A64SysReg_PMEVCNTR16_EL0},
|
||||
{"pmevcntr17_el0", A64SysReg_PMEVCNTR17_EL0},
|
||||
{"pmevcntr18_el0", A64SysReg_PMEVCNTR18_EL0},
|
||||
{"pmevcntr19_el0", A64SysReg_PMEVCNTR19_EL0},
|
||||
{"pmevcntr20_el0", A64SysReg_PMEVCNTR20_EL0},
|
||||
{"pmevcntr21_el0", A64SysReg_PMEVCNTR21_EL0},
|
||||
{"pmevcntr22_el0", A64SysReg_PMEVCNTR22_EL0},
|
||||
{"pmevcntr23_el0", A64SysReg_PMEVCNTR23_EL0},
|
||||
{"pmevcntr24_el0", A64SysReg_PMEVCNTR24_EL0},
|
||||
{"pmevcntr25_el0", A64SysReg_PMEVCNTR25_EL0},
|
||||
{"pmevcntr26_el0", A64SysReg_PMEVCNTR26_EL0},
|
||||
{"pmevcntr27_el0", A64SysReg_PMEVCNTR27_EL0},
|
||||
{"pmevcntr28_el0", A64SysReg_PMEVCNTR28_EL0},
|
||||
{"pmevcntr29_el0", A64SysReg_PMEVCNTR29_EL0},
|
||||
{"pmevcntr30_el0", A64SysReg_PMEVCNTR30_EL0},
|
||||
{"pmccfiltr_el0", A64SysReg_PMCCFILTR_EL0},
|
||||
{"pmevtyper0_el0", A64SysReg_PMEVTYPER0_EL0},
|
||||
{"pmevtyper1_el0", A64SysReg_PMEVTYPER1_EL0},
|
||||
{"pmevtyper2_el0", A64SysReg_PMEVTYPER2_EL0},
|
||||
{"pmevtyper3_el0", A64SysReg_PMEVTYPER3_EL0},
|
||||
{"pmevtyper4_el0", A64SysReg_PMEVTYPER4_EL0},
|
||||
{"pmevtyper5_el0", A64SysReg_PMEVTYPER5_EL0},
|
||||
{"pmevtyper6_el0", A64SysReg_PMEVTYPER6_EL0},
|
||||
{"pmevtyper7_el0", A64SysReg_PMEVTYPER7_EL0},
|
||||
{"pmevtyper8_el0", A64SysReg_PMEVTYPER8_EL0},
|
||||
{"pmevtyper9_el0", A64SysReg_PMEVTYPER9_EL0},
|
||||
{"pmevtyper10_el0", A64SysReg_PMEVTYPER10_EL0},
|
||||
{"pmevtyper11_el0", A64SysReg_PMEVTYPER11_EL0},
|
||||
{"pmevtyper12_el0", A64SysReg_PMEVTYPER12_EL0},
|
||||
{"pmevtyper13_el0", A64SysReg_PMEVTYPER13_EL0},
|
||||
{"pmevtyper14_el0", A64SysReg_PMEVTYPER14_EL0},
|
||||
{"pmevtyper15_el0", A64SysReg_PMEVTYPER15_EL0},
|
||||
{"pmevtyper16_el0", A64SysReg_PMEVTYPER16_EL0},
|
||||
{"pmevtyper17_el0", A64SysReg_PMEVTYPER17_EL0},
|
||||
{"pmevtyper18_el0", A64SysReg_PMEVTYPER18_EL0},
|
||||
{"pmevtyper19_el0", A64SysReg_PMEVTYPER19_EL0},
|
||||
{"pmevtyper20_el0", A64SysReg_PMEVTYPER20_EL0},
|
||||
{"pmevtyper21_el0", A64SysReg_PMEVTYPER21_EL0},
|
||||
{"pmevtyper22_el0", A64SysReg_PMEVTYPER22_EL0},
|
||||
{"pmevtyper23_el0", A64SysReg_PMEVTYPER23_EL0},
|
||||
{"pmevtyper24_el0", A64SysReg_PMEVTYPER24_EL0},
|
||||
{"pmevtyper25_el0", A64SysReg_PMEVTYPER25_EL0},
|
||||
{"pmevtyper26_el0", A64SysReg_PMEVTYPER26_EL0},
|
||||
{"pmevtyper27_el0", A64SysReg_PMEVTYPER27_EL0},
|
||||
{"pmevtyper28_el0", A64SysReg_PMEVTYPER28_EL0},
|
||||
{"pmevtyper29_el0", A64SysReg_PMEVTYPER29_EL0},
|
||||
{"pmevtyper30_el0", A64SysReg_PMEVTYPER30_EL0},
|
||||
{"lorc_el1", A64SysReg_LORC_EL1},
|
||||
{"lorea_el1", A64SysReg_LOREA_EL1},
|
||||
{"lorn_el1", A64SysReg_LORN_EL1},
|
||||
{"lorsa_el1", A64SysReg_LORSA_EL1},
|
||||
|
||||
// Trace registers
|
||||
{"trcprgctlr", A64SysReg_TRCPRGCTLR},
|
||||
{"trcprocselr", A64SysReg_TRCPROCSELR},
|
||||
{"trcconfigr", A64SysReg_TRCCONFIGR},
|
||||
{"trcauxctlr", A64SysReg_TRCAUXCTLR},
|
||||
{"trceventctl0r", A64SysReg_TRCEVENTCTL0R},
|
||||
{"trceventctl1r", A64SysReg_TRCEVENTCTL1R},
|
||||
{"trcstallctlr", A64SysReg_TRCSTALLCTLR},
|
||||
{"trctsctlr", A64SysReg_TRCTSCTLR},
|
||||
{"trcsyncpr", A64SysReg_TRCSYNCPR},
|
||||
{"trcccctlr", A64SysReg_TRCCCCTLR},
|
||||
{"trcbbctlr", A64SysReg_TRCBBCTLR},
|
||||
{"trctraceidr", A64SysReg_TRCTRACEIDR},
|
||||
{"trcqctlr", A64SysReg_TRCQCTLR},
|
||||
{"trcvictlr", A64SysReg_TRCVICTLR},
|
||||
{"trcviiectlr", A64SysReg_TRCVIIECTLR},
|
||||
{"trcvissctlr", A64SysReg_TRCVISSCTLR},
|
||||
{"trcvipcssctlr", A64SysReg_TRCVIPCSSCTLR},
|
||||
{"trcvdctlr", A64SysReg_TRCVDCTLR},
|
||||
{"trcvdsacctlr", A64SysReg_TRCVDSACCTLR},
|
||||
{"trcvdarcctlr", A64SysReg_TRCVDARCCTLR},
|
||||
{"trcseqevr0", A64SysReg_TRCSEQEVR0},
|
||||
{"trcseqevr1", A64SysReg_TRCSEQEVR1},
|
||||
{"trcseqevr2", A64SysReg_TRCSEQEVR2},
|
||||
{"trcseqrstevr", A64SysReg_TRCSEQRSTEVR},
|
||||
{"trcseqstr", A64SysReg_TRCSEQSTR},
|
||||
{"trcextinselr", A64SysReg_TRCEXTINSELR},
|
||||
{"trccntrldvr0", A64SysReg_TRCCNTRLDVR0},
|
||||
{"trccntrldvr1", A64SysReg_TRCCNTRLDVR1},
|
||||
{"trccntrldvr2", A64SysReg_TRCCNTRLDVR2},
|
||||
{"trccntrldvr3", A64SysReg_TRCCNTRLDVR3},
|
||||
{"trccntctlr0", A64SysReg_TRCCNTCTLR0},
|
||||
{"trccntctlr1", A64SysReg_TRCCNTCTLR1},
|
||||
{"trccntctlr2", A64SysReg_TRCCNTCTLR2},
|
||||
{"trccntctlr3", A64SysReg_TRCCNTCTLR3},
|
||||
{"trccntvr0", A64SysReg_TRCCNTVR0},
|
||||
{"trccntvr1", A64SysReg_TRCCNTVR1},
|
||||
{"trccntvr2", A64SysReg_TRCCNTVR2},
|
||||
{"trccntvr3", A64SysReg_TRCCNTVR3},
|
||||
{"trcimspec0", A64SysReg_TRCIMSPEC0},
|
||||
{"trcimspec1", A64SysReg_TRCIMSPEC1},
|
||||
{"trcimspec2", A64SysReg_TRCIMSPEC2},
|
||||
{"trcimspec3", A64SysReg_TRCIMSPEC3},
|
||||
{"trcimspec4", A64SysReg_TRCIMSPEC4},
|
||||
{"trcimspec5", A64SysReg_TRCIMSPEC5},
|
||||
{"trcimspec6", A64SysReg_TRCIMSPEC6},
|
||||
{"trcimspec7", A64SysReg_TRCIMSPEC7},
|
||||
{"trcrsctlr2", A64SysReg_TRCRSCTLR2},
|
||||
{"trcrsctlr3", A64SysReg_TRCRSCTLR3},
|
||||
{"trcrsctlr4", A64SysReg_TRCRSCTLR4},
|
||||
{"trcrsctlr5", A64SysReg_TRCRSCTLR5},
|
||||
{"trcrsctlr6", A64SysReg_TRCRSCTLR6},
|
||||
{"trcrsctlr7", A64SysReg_TRCRSCTLR7},
|
||||
{"trcrsctlr8", A64SysReg_TRCRSCTLR8},
|
||||
{"trcrsctlr9", A64SysReg_TRCRSCTLR9},
|
||||
{"trcrsctlr10", A64SysReg_TRCRSCTLR10},
|
||||
{"trcrsctlr11", A64SysReg_TRCRSCTLR11},
|
||||
{"trcrsctlr12", A64SysReg_TRCRSCTLR12},
|
||||
{"trcrsctlr13", A64SysReg_TRCRSCTLR13},
|
||||
{"trcrsctlr14", A64SysReg_TRCRSCTLR14},
|
||||
{"trcrsctlr15", A64SysReg_TRCRSCTLR15},
|
||||
{"trcrsctlr16", A64SysReg_TRCRSCTLR16},
|
||||
{"trcrsctlr17", A64SysReg_TRCRSCTLR17},
|
||||
{"trcrsctlr18", A64SysReg_TRCRSCTLR18},
|
||||
{"trcrsctlr19", A64SysReg_TRCRSCTLR19},
|
||||
{"trcrsctlr20", A64SysReg_TRCRSCTLR20},
|
||||
{"trcrsctlr21", A64SysReg_TRCRSCTLR21},
|
||||
{"trcrsctlr22", A64SysReg_TRCRSCTLR22},
|
||||
{"trcrsctlr23", A64SysReg_TRCRSCTLR23},
|
||||
{"trcrsctlr24", A64SysReg_TRCRSCTLR24},
|
||||
{"trcrsctlr25", A64SysReg_TRCRSCTLR25},
|
||||
{"trcrsctlr26", A64SysReg_TRCRSCTLR26},
|
||||
{"trcrsctlr27", A64SysReg_TRCRSCTLR27},
|
||||
{"trcrsctlr28", A64SysReg_TRCRSCTLR28},
|
||||
{"trcrsctlr29", A64SysReg_TRCRSCTLR29},
|
||||
{"trcrsctlr30", A64SysReg_TRCRSCTLR30},
|
||||
{"trcrsctlr31", A64SysReg_TRCRSCTLR31},
|
||||
{"trcssccr0", A64SysReg_TRCSSCCR0},
|
||||
{"trcssccr1", A64SysReg_TRCSSCCR1},
|
||||
{"trcssccr2", A64SysReg_TRCSSCCR2},
|
||||
{"trcssccr3", A64SysReg_TRCSSCCR3},
|
||||
{"trcssccr4", A64SysReg_TRCSSCCR4},
|
||||
{"trcssccr5", A64SysReg_TRCSSCCR5},
|
||||
{"trcssccr6", A64SysReg_TRCSSCCR6},
|
||||
{"trcssccr7", A64SysReg_TRCSSCCR7},
|
||||
{"trcsscsr0", A64SysReg_TRCSSCSR0},
|
||||
{"trcsscsr1", A64SysReg_TRCSSCSR1},
|
||||
{"trcsscsr2", A64SysReg_TRCSSCSR2},
|
||||
{"trcsscsr3", A64SysReg_TRCSSCSR3},
|
||||
{"trcsscsr4", A64SysReg_TRCSSCSR4},
|
||||
{"trcsscsr5", A64SysReg_TRCSSCSR5},
|
||||
{"trcsscsr6", A64SysReg_TRCSSCSR6},
|
||||
{"trcsscsr7", A64SysReg_TRCSSCSR7},
|
||||
{"trcsspcicr0", A64SysReg_TRCSSPCICR0},
|
||||
{"trcsspcicr1", A64SysReg_TRCSSPCICR1},
|
||||
{"trcsspcicr2", A64SysReg_TRCSSPCICR2},
|
||||
{"trcsspcicr3", A64SysReg_TRCSSPCICR3},
|
||||
{"trcsspcicr4", A64SysReg_TRCSSPCICR4},
|
||||
{"trcsspcicr5", A64SysReg_TRCSSPCICR5},
|
||||
{"trcsspcicr6", A64SysReg_TRCSSPCICR6},
|
||||
{"trcsspcicr7", A64SysReg_TRCSSPCICR7},
|
||||
{"trcpdcr", A64SysReg_TRCPDCR},
|
||||
{"trcacvr0", A64SysReg_TRCACVR0},
|
||||
{"trcacvr1", A64SysReg_TRCACVR1},
|
||||
{"trcacvr2", A64SysReg_TRCACVR2},
|
||||
{"trcacvr3", A64SysReg_TRCACVR3},
|
||||
{"trcacvr4", A64SysReg_TRCACVR4},
|
||||
{"trcacvr5", A64SysReg_TRCACVR5},
|
||||
{"trcacvr6", A64SysReg_TRCACVR6},
|
||||
{"trcacvr7", A64SysReg_TRCACVR7},
|
||||
{"trcacvr8", A64SysReg_TRCACVR8},
|
||||
{"trcacvr9", A64SysReg_TRCACVR9},
|
||||
{"trcacvr10", A64SysReg_TRCACVR10},
|
||||
{"trcacvr11", A64SysReg_TRCACVR11},
|
||||
{"trcacvr12", A64SysReg_TRCACVR12},
|
||||
{"trcacvr13", A64SysReg_TRCACVR13},
|
||||
{"trcacvr14", A64SysReg_TRCACVR14},
|
||||
{"trcacvr15", A64SysReg_TRCACVR15},
|
||||
{"trcacatr0", A64SysReg_TRCACATR0},
|
||||
{"trcacatr1", A64SysReg_TRCACATR1},
|
||||
{"trcacatr2", A64SysReg_TRCACATR2},
|
||||
{"trcacatr3", A64SysReg_TRCACATR3},
|
||||
{"trcacatr4", A64SysReg_TRCACATR4},
|
||||
{"trcacatr5", A64SysReg_TRCACATR5},
|
||||
{"trcacatr6", A64SysReg_TRCACATR6},
|
||||
{"trcacatr7", A64SysReg_TRCACATR7},
|
||||
{"trcacatr8", A64SysReg_TRCACATR8},
|
||||
{"trcacatr9", A64SysReg_TRCACATR9},
|
||||
{"trcacatr10", A64SysReg_TRCACATR10},
|
||||
{"trcacatr11", A64SysReg_TRCACATR11},
|
||||
{"trcacatr12", A64SysReg_TRCACATR12},
|
||||
{"trcacatr13", A64SysReg_TRCACATR13},
|
||||
{"trcacatr14", A64SysReg_TRCACATR14},
|
||||
{"trcacatr15", A64SysReg_TRCACATR15},
|
||||
{"trcdvcvr0", A64SysReg_TRCDVCVR0},
|
||||
{"trcdvcvr1", A64SysReg_TRCDVCVR1},
|
||||
{"trcdvcvr2", A64SysReg_TRCDVCVR2},
|
||||
{"trcdvcvr3", A64SysReg_TRCDVCVR3},
|
||||
{"trcdvcvr4", A64SysReg_TRCDVCVR4},
|
||||
{"trcdvcvr5", A64SysReg_TRCDVCVR5},
|
||||
{"trcdvcvr6", A64SysReg_TRCDVCVR6},
|
||||
{"trcdvcvr7", A64SysReg_TRCDVCVR7},
|
||||
{"trcdvcmr0", A64SysReg_TRCDVCMR0},
|
||||
{"trcdvcmr1", A64SysReg_TRCDVCMR1},
|
||||
{"trcdvcmr2", A64SysReg_TRCDVCMR2},
|
||||
{"trcdvcmr3", A64SysReg_TRCDVCMR3},
|
||||
{"trcdvcmr4", A64SysReg_TRCDVCMR4},
|
||||
{"trcdvcmr5", A64SysReg_TRCDVCMR5},
|
||||
{"trcdvcmr6", A64SysReg_TRCDVCMR6},
|
||||
{"trcdvcmr7", A64SysReg_TRCDVCMR7},
|
||||
{"trccidcvr0", A64SysReg_TRCCIDCVR0},
|
||||
{"trccidcvr1", A64SysReg_TRCCIDCVR1},
|
||||
{"trccidcvr2", A64SysReg_TRCCIDCVR2},
|
||||
{"trccidcvr3", A64SysReg_TRCCIDCVR3},
|
||||
{"trccidcvr4", A64SysReg_TRCCIDCVR4},
|
||||
{"trccidcvr5", A64SysReg_TRCCIDCVR5},
|
||||
{"trccidcvr6", A64SysReg_TRCCIDCVR6},
|
||||
{"trccidcvr7", A64SysReg_TRCCIDCVR7},
|
||||
{"trcvmidcvr0", A64SysReg_TRCVMIDCVR0},
|
||||
{"trcvmidcvr1", A64SysReg_TRCVMIDCVR1},
|
||||
{"trcvmidcvr2", A64SysReg_TRCVMIDCVR2},
|
||||
{"trcvmidcvr3", A64SysReg_TRCVMIDCVR3},
|
||||
{"trcvmidcvr4", A64SysReg_TRCVMIDCVR4},
|
||||
{"trcvmidcvr5", A64SysReg_TRCVMIDCVR5},
|
||||
{"trcvmidcvr6", A64SysReg_TRCVMIDCVR6},
|
||||
{"trcvmidcvr7", A64SysReg_TRCVMIDCVR7},
|
||||
{"trccidcctlr0", A64SysReg_TRCCIDCCTLR0},
|
||||
{"trccidcctlr1", A64SysReg_TRCCIDCCTLR1},
|
||||
{"trcvmidcctlr0", A64SysReg_TRCVMIDCCTLR0},
|
||||
{"trcvmidcctlr1", A64SysReg_TRCVMIDCCTLR1},
|
||||
{"trcitctrl", A64SysReg_TRCITCTRL},
|
||||
{"trcclaimset", A64SysReg_TRCCLAIMSET},
|
||||
{"trcclaimclr", A64SysReg_TRCCLAIMCLR},
|
||||
|
||||
// GICv3 registers
|
||||
{"icc_bpr1_el1", A64SysReg_ICC_BPR1_EL1},
|
||||
{"icc_bpr0_el1", A64SysReg_ICC_BPR0_EL1},
|
||||
{"icc_pmr_el1", A64SysReg_ICC_PMR_EL1},
|
||||
{"icc_ctlr_el1", A64SysReg_ICC_CTLR_EL1},
|
||||
{"icc_ctlr_el3", A64SysReg_ICC_CTLR_EL3},
|
||||
{"icc_sre_el1", A64SysReg_ICC_SRE_EL1},
|
||||
{"icc_sre_el2", A64SysReg_ICC_SRE_EL2},
|
||||
{"icc_sre_el3", A64SysReg_ICC_SRE_EL3},
|
||||
{"icc_igrpen0_el1", A64SysReg_ICC_IGRPEN0_EL1},
|
||||
{"icc_igrpen1_el1", A64SysReg_ICC_IGRPEN1_EL1},
|
||||
{"icc_igrpen1_el3", A64SysReg_ICC_IGRPEN1_EL3},
|
||||
{"icc_seien_el1", A64SysReg_ICC_SEIEN_EL1},
|
||||
{"icc_ap0r0_el1", A64SysReg_ICC_AP0R0_EL1},
|
||||
{"icc_ap0r1_el1", A64SysReg_ICC_AP0R1_EL1},
|
||||
{"icc_ap0r2_el1", A64SysReg_ICC_AP0R2_EL1},
|
||||
{"icc_ap0r3_el1", A64SysReg_ICC_AP0R3_EL1},
|
||||
{"icc_ap1r0_el1", A64SysReg_ICC_AP1R0_EL1},
|
||||
{"icc_ap1r1_el1", A64SysReg_ICC_AP1R1_EL1},
|
||||
{"icc_ap1r2_el1", A64SysReg_ICC_AP1R2_EL1},
|
||||
{"icc_ap1r3_el1", A64SysReg_ICC_AP1R3_EL1},
|
||||
{"ich_ap0r0_el2", A64SysReg_ICH_AP0R0_EL2},
|
||||
{"ich_ap0r1_el2", A64SysReg_ICH_AP0R1_EL2},
|
||||
{"ich_ap0r2_el2", A64SysReg_ICH_AP0R2_EL2},
|
||||
{"ich_ap0r3_el2", A64SysReg_ICH_AP0R3_EL2},
|
||||
{"ich_ap1r0_el2", A64SysReg_ICH_AP1R0_EL2},
|
||||
{"ich_ap1r1_el2", A64SysReg_ICH_AP1R1_EL2},
|
||||
{"ich_ap1r2_el2", A64SysReg_ICH_AP1R2_EL2},
|
||||
{"ich_ap1r3_el2", A64SysReg_ICH_AP1R3_EL2},
|
||||
{"ich_hcr_el2", A64SysReg_ICH_HCR_EL2},
|
||||
{"ich_misr_el2", A64SysReg_ICH_MISR_EL2},
|
||||
{"ich_vmcr_el2", A64SysReg_ICH_VMCR_EL2},
|
||||
{"ich_vseir_el2", A64SysReg_ICH_VSEIR_EL2},
|
||||
{"ich_lr0_el2", A64SysReg_ICH_LR0_EL2},
|
||||
{"ich_lr1_el2", A64SysReg_ICH_LR1_EL2},
|
||||
{"ich_lr2_el2", A64SysReg_ICH_LR2_EL2},
|
||||
{"ich_lr3_el2", A64SysReg_ICH_LR3_EL2},
|
||||
{"ich_lr4_el2", A64SysReg_ICH_LR4_EL2},
|
||||
{"ich_lr5_el2", A64SysReg_ICH_LR5_EL2},
|
||||
{"ich_lr6_el2", A64SysReg_ICH_LR6_EL2},
|
||||
{"ich_lr7_el2", A64SysReg_ICH_LR7_EL2},
|
||||
{"ich_lr8_el2", A64SysReg_ICH_LR8_EL2},
|
||||
{"ich_lr9_el2", A64SysReg_ICH_LR9_EL2},
|
||||
{"ich_lr10_el2", A64SysReg_ICH_LR10_EL2},
|
||||
{"ich_lr11_el2", A64SysReg_ICH_LR11_EL2},
|
||||
{"ich_lr12_el2", A64SysReg_ICH_LR12_EL2},
|
||||
{"ich_lr13_el2", A64SysReg_ICH_LR13_EL2},
|
||||
{"ich_lr14_el2", A64SysReg_ICH_LR14_EL2},
|
||||
{"ich_lr15_el2", A64SysReg_ICH_LR15_EL2},
|
||||
|
||||
// Statistical profiling registers
|
||||
{"pmblimitr_el1", A64SysReg_PMBLIMITR_EL1},
|
||||
{"pmbptr_el1", A64SysReg_PMBPTR_EL1},
|
||||
{"pmbsr_el1", A64SysReg_PMBSR_EL1},
|
||||
{"pmscr_el1", A64SysReg_PMSCR_EL1},
|
||||
{"pmscr_el12", A64SysReg_PMSCR_EL12},
|
||||
{"pmscr_el2", A64SysReg_PMSCR_EL2},
|
||||
{"pmsicr_el1", A64SysReg_PMSICR_EL1},
|
||||
{"pmsirr_el1", A64SysReg_PMSIRR_EL1},
|
||||
{"pmsfcr_el1", A64SysReg_PMSFCR_EL1},
|
||||
{"pmsevfr_el1", A64SysReg_PMSEVFR_EL1},
|
||||
{"pmslatfr_el1", A64SysReg_PMSLATFR_EL1}
|
||||
};
|
||||
|
||||
static const A64NamedImmMapper_Mapping CycloneSysRegPairs[] = {
|
||||
{"cpm_ioacc_ctl_el3", A64SysReg_CPM_IOACC_CTL_EL3}
|
||||
};
|
||||
|
||||
// result must be a big enough buffer: 128 bytes is more than enough
|
||||
void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result)
|
||||
{
|
||||
@ -685,299 +158,60 @@ void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *res
|
||||
cs_mem_free(Op2S);
|
||||
}
|
||||
|
||||
static const A64NamedImmMapper_Mapping TLBIPairs[] = {
|
||||
{"ipas2e1is", A64TLBI_IPAS2E1IS},
|
||||
{"ipas2le1is", A64TLBI_IPAS2LE1IS},
|
||||
{"vmalle1is", A64TLBI_VMALLE1IS},
|
||||
{"alle2is", A64TLBI_ALLE2IS},
|
||||
{"alle3is", A64TLBI_ALLE3IS},
|
||||
{"vae1is", A64TLBI_VAE1IS},
|
||||
{"vae2is", A64TLBI_VAE2IS},
|
||||
{"vae3is", A64TLBI_VAE3IS},
|
||||
{"aside1is", A64TLBI_ASIDE1IS},
|
||||
{"vaae1is", A64TLBI_VAAE1IS},
|
||||
{"alle1is", A64TLBI_ALLE1IS},
|
||||
{"vale1is", A64TLBI_VALE1IS},
|
||||
{"vale2is", A64TLBI_VALE2IS},
|
||||
{"vale3is", A64TLBI_VALE3IS},
|
||||
{"vmalls12e1is", A64TLBI_VMALLS12E1IS},
|
||||
{"vaale1is", A64TLBI_VAALE1IS},
|
||||
{"ipas2e1", A64TLBI_IPAS2E1},
|
||||
{"ipas2le1", A64TLBI_IPAS2LE1},
|
||||
{"vmalle1", A64TLBI_VMALLE1},
|
||||
{"alle2", A64TLBI_ALLE2},
|
||||
{"alle3", A64TLBI_ALLE3},
|
||||
{"vae1", A64TLBI_VAE1},
|
||||
{"vae2", A64TLBI_VAE2},
|
||||
{"vae3", A64TLBI_VAE3},
|
||||
{"aside1", A64TLBI_ASIDE1},
|
||||
{"vaae1", A64TLBI_VAAE1},
|
||||
{"alle1", A64TLBI_ALLE1},
|
||||
{"vale1", A64TLBI_VALE1},
|
||||
{"vale2", A64TLBI_VALE2},
|
||||
{"vale3", A64TLBI_VALE3},
|
||||
{"vmalls12e1", A64TLBI_VMALLS12E1},
|
||||
{"vaale1", A64TLBI_VAALE1}
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64TLBI_TLBIMapper = {
|
||||
TLBIPairs,
|
||||
ARR_SIZE(TLBIPairs),
|
||||
0,
|
||||
};
|
||||
|
||||
static const A64NamedImmMapper_Mapping ATPairs[] = {
|
||||
{"s1e1r", A64AT_S1E1R},
|
||||
{"s1e2r", A64AT_S1E2R},
|
||||
{"s1e3r", A64AT_S1E3R},
|
||||
{"s1e1w", A64AT_S1E1W},
|
||||
{"s1e2w", A64AT_S1E2W},
|
||||
{"s1e3w", A64AT_S1E3W},
|
||||
{"s1e0r", A64AT_S1E0R},
|
||||
{"s1e0w", A64AT_S1E0W},
|
||||
{"s12e1r", A64AT_S12E1R},
|
||||
{"s12e1w", A64AT_S12E1W},
|
||||
{"s12e0r", A64AT_S12E0R},
|
||||
{"s12e0w", A64AT_S12E0W}
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64AT_ATMapper = {
|
||||
ATPairs,
|
||||
ARR_SIZE(ATPairs),
|
||||
0,
|
||||
};
|
||||
|
||||
static const A64NamedImmMapper_Mapping DBarrierPairs[] = {
|
||||
{"oshld", A64DB_OSHLD},
|
||||
{"oshst", A64DB_OSHST},
|
||||
{"osh", A64DB_OSH},
|
||||
{"nshld", A64DB_NSHLD},
|
||||
{"nshst", A64DB_NSHST},
|
||||
{"nsh", A64DB_NSH},
|
||||
{"ishld", A64DB_ISHLD},
|
||||
{"ishst", A64DB_ISHST},
|
||||
{"ish", A64DB_ISH},
|
||||
{"ld", A64DB_LD},
|
||||
{"st", A64DB_ST},
|
||||
{"sy", A64DB_SY}
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64DB_DBarrierMapper = {
|
||||
DBarrierPairs,
|
||||
ARR_SIZE(DBarrierPairs),
|
||||
16,
|
||||
};
|
||||
|
||||
static const A64NamedImmMapper_Mapping DCPairs[] = {
|
||||
{"zva", A64DC_ZVA},
|
||||
{"ivac", A64DC_IVAC},
|
||||
{"isw", A64DC_ISW},
|
||||
{"cvac", A64DC_CVAC},
|
||||
{"csw", A64DC_CSW},
|
||||
{"cvau", A64DC_CVAU},
|
||||
{"civac", A64DC_CIVAC},
|
||||
{"cisw", A64DC_CISW}
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64DC_DCMapper = {
|
||||
DCPairs,
|
||||
ARR_SIZE(DCPairs),
|
||||
0,
|
||||
};
|
||||
|
||||
static const A64NamedImmMapper_Mapping ICPairs[] = {
|
||||
{"ialluis", A64IC_IALLUIS},
|
||||
{"iallu", A64IC_IALLU},
|
||||
{"ivau", A64IC_IVAU}
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64IC_ICMapper = {
|
||||
ICPairs,
|
||||
ARR_SIZE(ICPairs),
|
||||
0,
|
||||
};
|
||||
|
||||
static const A64NamedImmMapper_Mapping ISBPairs[] = {
|
||||
{"sy", A64DB_SY},
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64ISB_ISBMapper = {
|
||||
ISBPairs,
|
||||
ARR_SIZE(ISBPairs),
|
||||
16,
|
||||
};
|
||||
|
||||
static const A64NamedImmMapper_Mapping PRFMPairs[] = {
|
||||
{"pldl1keep", A64PRFM_PLDL1KEEP},
|
||||
{"pldl1strm", A64PRFM_PLDL1STRM},
|
||||
{"pldl2keep", A64PRFM_PLDL2KEEP},
|
||||
{"pldl2strm", A64PRFM_PLDL2STRM},
|
||||
{"pldl3keep", A64PRFM_PLDL3KEEP},
|
||||
{"pldl3strm", A64PRFM_PLDL3STRM},
|
||||
{"plil1keep", A64PRFM_PLIL1KEEP},
|
||||
{"plil1strm", A64PRFM_PLIL1STRM},
|
||||
{"plil2keep", A64PRFM_PLIL2KEEP},
|
||||
{"plil2strm", A64PRFM_PLIL2STRM},
|
||||
{"plil3keep", A64PRFM_PLIL3KEEP},
|
||||
{"plil3strm", A64PRFM_PLIL3STRM},
|
||||
{"pstl1keep", A64PRFM_PSTL1KEEP},
|
||||
{"pstl1strm", A64PRFM_PSTL1STRM},
|
||||
{"pstl2keep", A64PRFM_PSTL2KEEP},
|
||||
{"pstl2strm", A64PRFM_PSTL2STRM},
|
||||
{"pstl3keep", A64PRFM_PSTL3KEEP},
|
||||
{"pstl3strm", A64PRFM_PSTL3STRM}
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64PRFM_PRFMMapper = {
|
||||
PRFMPairs,
|
||||
ARR_SIZE(PRFMPairs),
|
||||
32,
|
||||
};
|
||||
|
||||
static const A64NamedImmMapper_Mapping PStatePairs[] = {
|
||||
{"spsel", A64PState_SPSel},
|
||||
{"daifset", A64PState_DAIFSet},
|
||||
{"daifclr", A64PState_DAIFClr},
|
||||
{"pan", A64PState_PAN},
|
||||
{"uao", A64PState_UAO}
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64PState_PStateMapper = {
|
||||
PStatePairs,
|
||||
ARR_SIZE(PStatePairs),
|
||||
0,
|
||||
};
|
||||
|
||||
static const A64NamedImmMapper_Mapping MRSPairs[] = {
|
||||
{"mdccsr_el0", A64SysReg_MDCCSR_EL0},
|
||||
{"dbgdtrrx_el0", A64SysReg_DBGDTRRX_EL0},
|
||||
{"mdrar_el1", A64SysReg_MDRAR_EL1},
|
||||
{"oslsr_el1", A64SysReg_OSLSR_EL1},
|
||||
{"dbgauthstatus_el1", A64SysReg_DBGAUTHSTATUS_EL1},
|
||||
{"pmceid0_el0", A64SysReg_PMCEID0_EL0},
|
||||
{"pmceid1_el0", A64SysReg_PMCEID1_EL0},
|
||||
{"midr_el1", A64SysReg_MIDR_EL1},
|
||||
{"ccsidr_el1", A64SysReg_CCSIDR_EL1},
|
||||
{"clidr_el1", A64SysReg_CLIDR_EL1},
|
||||
{"ctr_el0", A64SysReg_CTR_EL0},
|
||||
{"mpidr_el1", A64SysReg_MPIDR_EL1},
|
||||
{"revidr_el1", A64SysReg_REVIDR_EL1},
|
||||
{"aidr_el1", A64SysReg_AIDR_EL1},
|
||||
{"dczid_el0", A64SysReg_DCZID_EL0},
|
||||
{"id_pfr0_el1", A64SysReg_ID_PFR0_EL1},
|
||||
{"id_pfr1_el1", A64SysReg_ID_PFR1_EL1},
|
||||
{"id_dfr0_el1", A64SysReg_ID_DFR0_EL1},
|
||||
{"id_afr0_el1", A64SysReg_ID_AFR0_EL1},
|
||||
{"id_mmfr0_el1", A64SysReg_ID_MMFR0_EL1},
|
||||
{"id_mmfr1_el1", A64SysReg_ID_MMFR1_EL1},
|
||||
{"id_mmfr2_el1", A64SysReg_ID_MMFR2_EL1},
|
||||
{"id_mmfr3_el1", A64SysReg_ID_MMFR3_EL1},
|
||||
{"id_mmfr4_el1", A64SysReg_ID_MMFR4_EL1},
|
||||
{"id_isar0_el1", A64SysReg_ID_ISAR0_EL1},
|
||||
{"id_isar1_el1", A64SysReg_ID_ISAR1_EL1},
|
||||
{"id_isar2_el1", A64SysReg_ID_ISAR2_EL1},
|
||||
{"id_isar3_el1", A64SysReg_ID_ISAR3_EL1},
|
||||
{"id_isar4_el1", A64SysReg_ID_ISAR4_EL1},
|
||||
{"id_isar5_el1", A64SysReg_ID_ISAR5_EL1},
|
||||
{"id_aa64pfr0_el1", A64SysReg_ID_A64PFR0_EL1},
|
||||
{"id_aa64pfr1_el1", A64SysReg_ID_A64PFR1_EL1},
|
||||
{"id_aa64dfr0_el1", A64SysReg_ID_A64DFR0_EL1},
|
||||
{"id_aa64dfr1_el1", A64SysReg_ID_A64DFR1_EL1},
|
||||
{"id_aa64afr0_el1", A64SysReg_ID_A64AFR0_EL1},
|
||||
{"id_aa64afr1_el1", A64SysReg_ID_A64AFR1_EL1},
|
||||
{"id_aa64isar0_el1", A64SysReg_ID_A64ISAR0_EL1},
|
||||
{"id_aa64isar1_el1", A64SysReg_ID_A64ISAR1_EL1},
|
||||
{"id_aa64mmfr0_el1", A64SysReg_ID_A64MMFR0_EL1},
|
||||
{"id_aa64mmfr1_el1", A64SysReg_ID_A64MMFR1_EL1},
|
||||
{"id_aa64mmfr2_el1", A64SysReg_ID_A64MMFR2_EL1},
|
||||
{"lorid_el1", A64SysReg_LORID_EL1},
|
||||
{"mvfr0_el1", A64SysReg_MVFR0_EL1},
|
||||
{"mvfr1_el1", A64SysReg_MVFR1_EL1},
|
||||
{"mvfr2_el1", A64SysReg_MVFR2_EL1},
|
||||
{"rvbar_el1", A64SysReg_RVBAR_EL1},
|
||||
{"rvbar_el2", A64SysReg_RVBAR_EL2},
|
||||
{"rvbar_el3", A64SysReg_RVBAR_EL3},
|
||||
{"isr_el1", A64SysReg_ISR_EL1},
|
||||
{"cntpct_el0", A64SysReg_CNTPCT_EL0},
|
||||
{"cntvct_el0", A64SysReg_CNTVCT_EL0},
|
||||
|
||||
// Trace registers
|
||||
{"trcstatr", A64SysReg_TRCSTATR},
|
||||
{"trcidr8", A64SysReg_TRCIDR8},
|
||||
{"trcidr9", A64SysReg_TRCIDR9},
|
||||
{"trcidr10", A64SysReg_TRCIDR10},
|
||||
{"trcidr11", A64SysReg_TRCIDR11},
|
||||
{"trcidr12", A64SysReg_TRCIDR12},
|
||||
{"trcidr13", A64SysReg_TRCIDR13},
|
||||
{"trcidr0", A64SysReg_TRCIDR0},
|
||||
{"trcidr1", A64SysReg_TRCIDR1},
|
||||
{"trcidr2", A64SysReg_TRCIDR2},
|
||||
{"trcidr3", A64SysReg_TRCIDR3},
|
||||
{"trcidr4", A64SysReg_TRCIDR4},
|
||||
{"trcidr5", A64SysReg_TRCIDR5},
|
||||
{"trcidr6", A64SysReg_TRCIDR6},
|
||||
{"trcidr7", A64SysReg_TRCIDR7},
|
||||
{"trcoslsr", A64SysReg_TRCOSLSR},
|
||||
{"trcpdsr", A64SysReg_TRCPDSR},
|
||||
{"trcdevaff0", A64SysReg_TRCDEVAFF0},
|
||||
{"trcdevaff1", A64SysReg_TRCDEVAFF1},
|
||||
{"trclsr", A64SysReg_TRCLSR},
|
||||
{"trcauthstatus", A64SysReg_TRCAUTHSTATUS},
|
||||
{"trcdevarch", A64SysReg_TRCDEVARCH},
|
||||
{"trcdevid", A64SysReg_TRCDEVID},
|
||||
{"trcdevtype", A64SysReg_TRCDEVTYPE},
|
||||
{"trcpidr4", A64SysReg_TRCPIDR4},
|
||||
{"trcpidr5", A64SysReg_TRCPIDR5},
|
||||
{"trcpidr6", A64SysReg_TRCPIDR6},
|
||||
{"trcpidr7", A64SysReg_TRCPIDR7},
|
||||
{"trcpidr0", A64SysReg_TRCPIDR0},
|
||||
{"trcpidr1", A64SysReg_TRCPIDR1},
|
||||
{"trcpidr2", A64SysReg_TRCPIDR2},
|
||||
{"trcpidr3", A64SysReg_TRCPIDR3},
|
||||
{"trccidr0", A64SysReg_TRCCIDR0},
|
||||
{"trccidr1", A64SysReg_TRCCIDR1},
|
||||
{"trccidr2", A64SysReg_TRCCIDR2},
|
||||
{"trccidr3", A64SysReg_TRCCIDR3},
|
||||
|
||||
// GICv3 registers
|
||||
{"icc_iar1_el1", A64SysReg_ICC_IAR1_EL1},
|
||||
{"icc_iar0_el1", A64SysReg_ICC_IAR0_EL1},
|
||||
{"icc_hppir1_el1", A64SysReg_ICC_HPPIR1_EL1},
|
||||
{"icc_hppir0_el1", A64SysReg_ICC_HPPIR0_EL1},
|
||||
{"icc_rpr_el1", A64SysReg_ICC_RPR_EL1},
|
||||
{"ich_vtr_el2", A64SysReg_ICH_VTR_EL2},
|
||||
{"ich_eisr_el2", A64SysReg_ICH_EISR_EL2},
|
||||
{"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2},
|
||||
|
||||
// Statistical profiling registers
|
||||
{"pmsidr_el1", A64SysReg_PMSIDR_EL1},
|
||||
{"pmbidr_el1", A64SysReg_PMBIDR_EL1}
|
||||
};
|
||||
|
||||
const A64SysRegMapper AArch64_MRSMapper = {
|
||||
NULL,
|
||||
MRSPairs,
|
||||
ARR_SIZE(MRSPairs),
|
||||
};
|
||||
|
||||
static const A64NamedImmMapper_Mapping MSRPairs[] = {
|
||||
{"dbgdtrtx_el0", A64SysReg_DBGDTRTX_EL0},
|
||||
{"oslar_el1", A64SysReg_OSLAR_EL1},
|
||||
{"pmswinc_el0", A64SysReg_PMSWINC_EL0},
|
||||
|
||||
// Trace registers
|
||||
{"trcoslar", A64SysReg_TRCOSLAR},
|
||||
{"trclar", A64SysReg_TRCLAR},
|
||||
|
||||
// GICv3 registers
|
||||
{"icc_eoir1_el1", A64SysReg_ICC_EOIR1_EL1},
|
||||
{"icc_eoir0_el1", A64SysReg_ICC_EOIR0_EL1},
|
||||
{"icc_dir_el1", A64SysReg_ICC_DIR_EL1},
|
||||
{"icc_sgi1r_el1", A64SysReg_ICC_SGI1R_EL1},
|
||||
{"icc_asgi1r_el1", A64SysReg_ICC_ASGI1R_EL1},
|
||||
{"icc_sgi0r_el1", A64SysReg_ICC_SGI0R_EL1}
|
||||
};
|
||||
|
||||
const A64SysRegMapper AArch64_MSRMapper = {
|
||||
NULL,
|
||||
MSRPairs,
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -14,7 +14,7 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
#ifdef CAPSTONE_HAS_ARM64
|
||||
|
||||
@ -26,25 +26,20 @@
|
||||
|
||||
#include "AArch64Disassembler.h"
|
||||
|
||||
#include "../../MCDisassembler.h"
|
||||
#include "../../MCFixedLenDisassembler.h"
|
||||
#include "../../MCInst.h"
|
||||
#include "../../MCInstrDesc.h"
|
||||
#include "../../MCFixedLenDisassembler.h"
|
||||
#include "../../MCRegisterInfo.h"
|
||||
#include "../../MCDisassembler.h"
|
||||
|
||||
#include "AArch64BaseInfo.h"
|
||||
#include "AArch64AddressingModes.h"
|
||||
|
||||
#include "AArch64BaseInfo.h"
|
||||
|
||||
// Forward declare these because the autogenerated code will reference them.
|
||||
// Definitions are further down.
|
||||
static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
@ -88,6 +83,30 @@ static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeZPRRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeZPR2RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeZPR3RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeZPR4RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodePPRRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodePPR_3bRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
@ -101,11 +120,8 @@ static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
|
||||
uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
@ -177,6 +193,23 @@ static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeImm8OptLsl(MCInst *Inst, unsigned Imm, uint64_t Addr,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeSVEIncDecImm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder);
|
||||
|
||||
static bool Check(DecodeStatus *Out, DecodeStatus In)
|
||||
{
|
||||
@ -409,6 +442,18 @@ static const unsigned GPR64DecoderTable[] = {
|
||||
AArch64_LR, AArch64_XZR
|
||||
};
|
||||
|
||||
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo > 30)
|
||||
return Fail;
|
||||
|
||||
unsigned Register = GPR64DecoderTable[RegNo];
|
||||
MCOperand_CreateReg0(Inst, Register);
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
const void *Decoder)
|
||||
@ -427,17 +472,12 @@ static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
if (RegNo > 31)
|
||||
return Fail;
|
||||
|
||||
Register = GPR64DecoderTable[RegNo];
|
||||
unsigned Register = GPR64DecoderTable[RegNo];
|
||||
if (Register == AArch64_XZR)
|
||||
Register = AArch64_SP;
|
||||
|
||||
MCOperand_CreateReg0(Inst, Register);
|
||||
|
||||
return Success;
|
||||
}
|
||||
|
||||
@ -452,36 +492,170 @@ static const unsigned GPR32DecoderTable[] = {
|
||||
};
|
||||
|
||||
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
const void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
if (RegNo > 31)
|
||||
return Fail;
|
||||
|
||||
Register = GPR32DecoderTable[RegNo];
|
||||
unsigned Register = GPR32DecoderTable[RegNo];
|
||||
MCOperand_CreateReg0(Inst, Register);
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
const void *Decoder)
|
||||
uint64_t Addr,
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
if (RegNo > 31)
|
||||
return Fail;
|
||||
|
||||
Register = GPR32DecoderTable[RegNo];
|
||||
unsigned Register = GPR32DecoderTable[RegNo];
|
||||
if (Register == AArch64_WZR)
|
||||
Register = AArch64_WSP;
|
||||
|
||||
MCOperand_CreateReg0(Inst, Register);
|
||||
return Success;
|
||||
}
|
||||
|
||||
static const unsigned ZPRDecoderTable[] = {
|
||||
AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4,
|
||||
AArch64_Z5, AArch64_Z6, AArch64_Z7, AArch64_Z8, AArch64_Z9,
|
||||
AArch64_Z10, AArch64_Z11, AArch64_Z12, AArch64_Z13, AArch64_Z14,
|
||||
AArch64_Z15, AArch64_Z16, AArch64_Z17, AArch64_Z18, AArch64_Z19,
|
||||
AArch64_Z20, AArch64_Z21, AArch64_Z22, AArch64_Z23, AArch64_Z24,
|
||||
AArch64_Z25, AArch64_Z26, AArch64_Z27, AArch64_Z28, AArch64_Z29,
|
||||
AArch64_Z30, AArch64_Z31
|
||||
};
|
||||
|
||||
static DecodeStatus DecodeZPRRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo > 31)
|
||||
return Fail;
|
||||
|
||||
unsigned Register = ZPRDecoderTable[RegNo];
|
||||
MCOperand_CreateReg0(Inst, Register);
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo > 15)
|
||||
return Fail;
|
||||
return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo > 7)
|
||||
return Fail;
|
||||
return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
|
||||
}
|
||||
|
||||
static const unsigned ZZDecoderTable[] = {
|
||||
AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4,
|
||||
AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8,
|
||||
AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12,
|
||||
AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16,
|
||||
AArch64_Z16_Z17, AArch64_Z17_Z18, AArch64_Z18_Z19, AArch64_Z19_Z20,
|
||||
AArch64_Z20_Z21, AArch64_Z21_Z22, AArch64_Z22_Z23, AArch64_Z23_Z24,
|
||||
AArch64_Z24_Z25, AArch64_Z25_Z26, AArch64_Z26_Z27, AArch64_Z27_Z28,
|
||||
AArch64_Z28_Z29, AArch64_Z29_Z30, AArch64_Z30_Z31, AArch64_Z31_Z0
|
||||
};
|
||||
|
||||
static DecodeStatus DecodeZPR2RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo > 31)
|
||||
return Fail;
|
||||
unsigned Register = ZZDecoderTable[RegNo];
|
||||
MCOperand_CreateReg0(Inst, Register);
|
||||
return Success;
|
||||
}
|
||||
|
||||
static const unsigned ZZZDecoderTable[] = {
|
||||
AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4,
|
||||
AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7,
|
||||
AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10,
|
||||
AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13,
|
||||
AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16,
|
||||
AArch64_Z15_Z16_Z17, AArch64_Z16_Z17_Z18, AArch64_Z17_Z18_Z19,
|
||||
AArch64_Z18_Z19_Z20, AArch64_Z19_Z20_Z21, AArch64_Z20_Z21_Z22,
|
||||
AArch64_Z21_Z22_Z23, AArch64_Z22_Z23_Z24, AArch64_Z23_Z24_Z25,
|
||||
AArch64_Z24_Z25_Z26, AArch64_Z25_Z26_Z27, AArch64_Z26_Z27_Z28,
|
||||
AArch64_Z27_Z28_Z29, AArch64_Z28_Z29_Z30, AArch64_Z29_Z30_Z31,
|
||||
AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1
|
||||
};
|
||||
|
||||
static DecodeStatus DecodeZPR3RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo > 31)
|
||||
return Fail;
|
||||
unsigned Register = ZZZDecoderTable[RegNo];
|
||||
MCOperand_CreateReg0(Inst, Register);
|
||||
return Success;
|
||||
}
|
||||
|
||||
static const unsigned ZZZZDecoderTable[] = {
|
||||
AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5,
|
||||
AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8,
|
||||
AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11,
|
||||
AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14,
|
||||
AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17,
|
||||
AArch64_Z15_Z16_Z17_Z18, AArch64_Z16_Z17_Z18_Z19, AArch64_Z17_Z18_Z19_Z20,
|
||||
AArch64_Z18_Z19_Z20_Z21, AArch64_Z19_Z20_Z21_Z22, AArch64_Z20_Z21_Z22_Z23,
|
||||
AArch64_Z21_Z22_Z23_Z24, AArch64_Z22_Z23_Z24_Z25, AArch64_Z23_Z24_Z25_Z26,
|
||||
AArch64_Z24_Z25_Z26_Z27, AArch64_Z25_Z26_Z27_Z28, AArch64_Z26_Z27_Z28_Z29,
|
||||
AArch64_Z27_Z28_Z29_Z30, AArch64_Z28_Z29_Z30_Z31, AArch64_Z29_Z30_Z31_Z0,
|
||||
AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2
|
||||
};
|
||||
|
||||
static DecodeStatus DecodeZPR4RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo > 31)
|
||||
return Fail;
|
||||
unsigned Register = ZZZZDecoderTable[RegNo];
|
||||
MCOperand_CreateReg0(Inst, Register);
|
||||
return Success;
|
||||
}
|
||||
|
||||
static const unsigned PPRDecoderTable[] = {
|
||||
AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, AArch64_P4, AArch64_P5,
|
||||
AArch64_P6, AArch64_P7, AArch64_P8, AArch64_P9, AArch64_P10, AArch64_P11,
|
||||
AArch64_P12, AArch64_P13, AArch64_P14, AArch64_P15
|
||||
};
|
||||
|
||||
static DecodeStatus DecodePPRRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
if (RegNo > 15)
|
||||
return Fail;
|
||||
|
||||
unsigned Register = PPRDecoderTable[RegNo];
|
||||
MCOperand_CreateReg0(Inst, Register);
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodePPR_3bRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo > 7)
|
||||
return Fail;
|
||||
|
||||
// Just reuse the PPR decode table
|
||||
return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
|
||||
}
|
||||
|
||||
static const unsigned VectorDecoderTable[] = {
|
||||
AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4,
|
||||
AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9,
|
||||
@ -668,7 +842,7 @@ static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
|
||||
const void *Decoder)
|
||||
{
|
||||
// scale{5} is asserted as 1 in tblgen.
|
||||
Imm |= 0x20;
|
||||
Imm |= 0x20;
|
||||
MCOperand_CreateImm0(Inst, 64 - Imm);
|
||||
return Success;
|
||||
}
|
||||
@ -1387,60 +1561,60 @@ static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Rd, Rn, Rm;
|
||||
unsigned extend = fieldFromInstruction(insn, 10, 6);
|
||||
unsigned shift = extend & 0x7;
|
||||
unsigned Rd, Rn, Rm;
|
||||
unsigned extend = fieldFromInstruction(insn, 10, 6);
|
||||
unsigned shift = extend & 0x7;
|
||||
|
||||
if (shift > 4)
|
||||
return Fail;
|
||||
if (shift > 4)
|
||||
return Fail;
|
||||
|
||||
Rd = fieldFromInstruction(insn, 0, 5);
|
||||
Rn = fieldFromInstruction(insn, 5, 5);
|
||||
Rm = fieldFromInstruction(insn, 16, 5);
|
||||
Rd = fieldFromInstruction(insn, 0, 5);
|
||||
Rn = fieldFromInstruction(insn, 5, 5);
|
||||
Rm = fieldFromInstruction(insn, 16, 5);
|
||||
|
||||
switch (MCInst_getOpcode(Inst)) {
|
||||
default:
|
||||
return Fail;
|
||||
case AArch64_ADDWrx:
|
||||
case AArch64_SUBWrx:
|
||||
DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
|
||||
DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
case AArch64_ADDSWrx:
|
||||
case AArch64_SUBSWrx:
|
||||
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
|
||||
DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
case AArch64_ADDXrx:
|
||||
case AArch64_SUBXrx:
|
||||
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
|
||||
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
case AArch64_ADDSXrx:
|
||||
case AArch64_SUBSXrx:
|
||||
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
|
||||
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
case AArch64_ADDXrx64:
|
||||
case AArch64_SUBXrx64:
|
||||
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
|
||||
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
case AArch64_SUBSXrx64:
|
||||
case AArch64_ADDSXrx64:
|
||||
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
|
||||
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
}
|
||||
switch (MCInst_getOpcode(Inst)) {
|
||||
default:
|
||||
return Fail;
|
||||
case AArch64_ADDWrx:
|
||||
case AArch64_SUBWrx:
|
||||
DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
|
||||
DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
case AArch64_ADDSWrx:
|
||||
case AArch64_SUBSWrx:
|
||||
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
|
||||
DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
case AArch64_ADDXrx:
|
||||
case AArch64_SUBXrx:
|
||||
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
|
||||
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
case AArch64_ADDSXrx:
|
||||
case AArch64_SUBSXrx:
|
||||
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
|
||||
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
case AArch64_ADDXrx64:
|
||||
case AArch64_SUBXrx64:
|
||||
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
|
||||
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
case AArch64_SUBSXrx64:
|
||||
case AArch64_ADDSXrx64:
|
||||
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
|
||||
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
}
|
||||
|
||||
MCOperand_CreateImm0(Inst, extend);
|
||||
return Success;
|
||||
MCOperand_CreateImm0(Inst, extend);
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
|
||||
@ -1645,6 +1819,90 @@ static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
|
||||
MCOperand_CreateImm0(Inst, dst);
|
||||
|
||||
return Success;
|
||||
|
||||
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst *Inst,
|
||||
unsigned RegClassID,
|
||||
unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
const void *Decoder)
|
||||
{
|
||||
// Register number must be even (see CASP instruction)
|
||||
if (RegNo & 0x1)
|
||||
return Fail;
|
||||
|
||||
unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
|
||||
MCOperand_CreateReg0(Inst, Register);
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
const void *Decoder)
|
||||
{
|
||||
return DecodeGPRSeqPairsClassRegisterClass(
|
||||
Inst, AArch64_WSeqPairsClassRegClassID, RegNo, Addr, Decoder);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
const void *Decoder)
|
||||
{
|
||||
return DecodeGPRSeqPairsClassRegisterClass(
|
||||
Inst, AArch64_XSeqPairsClassRegClassID, RegNo, Addr, Decoder);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Zdn = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned imm = fieldFromInstruction(insn, 5, 13);
|
||||
if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64))
|
||||
return Fail;
|
||||
|
||||
// The same (tied) operand is added twice to the instruction.
|
||||
DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
|
||||
if (MCInst_getOpcode(Inst) != AArch64_DUPM_ZI)
|
||||
DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
|
||||
MCOperand_CreateImm0(Inst, imm);
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (Imm & ~((1LL << Bits) - 1))
|
||||
return Fail;
|
||||
|
||||
// Imm is a signed immediate, so sign extend it.
|
||||
if (Imm & (1 << (Bits - 1)))
|
||||
Imm |= ~((1LL << Bits) - 1);
|
||||
|
||||
MCOperand_CreateImm0(Inst, Imm);
|
||||
return Success;
|
||||
}
|
||||
|
||||
// Decode 8-bit signed/unsigned immediate for a given element width.
|
||||
static DecodeStatus DecodeImm8OptLsl(MCInst *Inst, unsigned Imm, uint64_t Addr,
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Val = (uint8_t)Imm;
|
||||
unsigned Shift = (Imm & 0x100) ? 8 : 0;
|
||||
if (ElementWidth == 8 && Shift)
|
||||
return Fail;
|
||||
MCInst_addOperand2(MCOperand_CreateImm0(Val));
|
||||
MCInst_addOperand2(MCOperand_CreateImm0(Shift));
|
||||
return Success;
|
||||
}
|
||||
|
||||
// Decode uimm4 ranged from 1-16.
|
||||
static DecodeStatus DecodeSVEIncDecImm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
MCInst_addOperand2(MCOperand_CreateImm0(Imm + 1));
|
||||
return Success;
|
||||
}
|
||||
|
||||
void AArch64_init(MCRegisterInfo *MRI)
|
||||
@ -1661,10 +1919,10 @@ void AArch64_init(MCRegisterInfo *MRI)
|
||||
*/
|
||||
|
||||
MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 420,
|
||||
0, 0,
|
||||
0, 0,
|
||||
AArch64MCRegisterClasses, 43,
|
||||
0, 0, AArch64RegDiffLists,
|
||||
0,
|
||||
0,
|
||||
AArch64SubRegIdxLists, 53,
|
||||
0);
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
#ifndef CS_AARCH64_DISASSEMBLER_H
|
||||
#define CS_AARCH64_DISASSEMBLER_H
|
||||
|
||||
@ -39,7 +39,7 @@
|
||||
|
||||
|
||||
static const char *getRegisterName(unsigned RegNo, int AltIdx);
|
||||
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O);
|
||||
static bool printSysAlias(MCInst *MI, SStream *O);
|
||||
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info);
|
||||
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
|
||||
@ -83,6 +83,12 @@ static void set_mem_access(MCInst *MI, bool status)
|
||||
}
|
||||
}
|
||||
|
||||
void AArch64_printRegName(SStream *O, unsigned RegNo)
|
||||
{
|
||||
// This is for .cfi directives.
|
||||
SStream_concat0(O, getRegisterName(RegNo, AArch64_NoRegAltName));
|
||||
}
|
||||
|
||||
void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
|
||||
{
|
||||
// Check for special encodings and print the canonical alias instead.
|
||||
@ -727,9 +733,9 @@ static bool printSysAlias(MCInst *MI, SStream *O)
|
||||
return Asm != NULL;
|
||||
}
|
||||
|
||||
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNo);
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNum);
|
||||
|
||||
if (MCOperand_isReg(Op)) {
|
||||
unsigned Reg = MCOperand_getReg(Op);
|
||||
@ -789,9 +795,25 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
}
|
||||
}
|
||||
|
||||
static void printHexImm(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
static void printImm(MCInst *MI, unsigned OpNum, SStream *O) {
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNum);
|
||||
SStream_concat0(O, "#", MCOperand_getImm(Op));
|
||||
if (MI->csh->detail) {
|
||||
#ifndef CAPSTONE_DIET
|
||||
uint8_t access;
|
||||
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
|
||||
MI->ac_idx++;
|
||||
#endif
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
|
||||
MI->flat_insn->detail->arm64.op_count++;
|
||||
}
|
||||
}
|
||||
|
||||
static void printImmHex(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNo);
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNum);
|
||||
SStream_concat(O, "#%#llx", MCOperand_getImm(Op));
|
||||
if (MI->csh->detail) {
|
||||
#ifndef CAPSTONE_DIET
|
||||
@ -806,10 +828,10 @@ static void printHexImm(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
}
|
||||
}
|
||||
|
||||
static void printPostIncOperand(MCInst *MI, unsigned OpNo,
|
||||
static void printPostIncOperand(MCInst *MI, unsigned OpNum,
|
||||
unsigned Imm, SStream *O)
|
||||
{
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNo);
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNum);
|
||||
|
||||
if (MCOperand_isReg(Op)) {
|
||||
unsigned Reg = MCOperand_getReg(Op);
|
||||
@ -844,14 +866,14 @@ static void printPostIncOperand(MCInst *MI, unsigned OpNo,
|
||||
//llvm_unreachable("unknown operand kind in printPostIncOperand64");
|
||||
}
|
||||
|
||||
static void printPostIncOperand2(MCInst *MI, unsigned OpNo, SStream *O, int Amount)
|
||||
static void printPostIncOperand2(MCInst *MI, unsigned OpNum, SStream *O, int Amount)
|
||||
{
|
||||
printPostIncOperand(MI, OpNo, Amount, O);
|
||||
printPostIncOperand(MI, OpNum, Amount, O);
|
||||
}
|
||||
|
||||
static void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
static void printVRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNo);
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNum);
|
||||
//assert(Op.isReg() && "Non-register vreg operand!");
|
||||
unsigned Reg = MCOperand_getReg(Op);
|
||||
SStream_concat0(O, getRegisterName(Reg, AArch64_vreg));
|
||||
@ -868,9 +890,9 @@ static void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
}
|
||||
}
|
||||
|
||||
static void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
static void printSysCROperand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNo);
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNum);
|
||||
//assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
|
||||
SStream_concat(O, "c%u", MCOperand_getImm(Op));
|
||||
if (MI->csh->detail) {
|
||||
@ -1114,12 +1136,10 @@ static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
printArithExtend(MI, OpNum + 1, O);
|
||||
}
|
||||
|
||||
static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, unsigned Width)
|
||||
static void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width,
|
||||
char SrcRegKind, SStream *O)
|
||||
{
|
||||
unsigned SignExtend = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
unsigned DoShift = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
|
||||
|
||||
// sxtw, sxtx, uxtw or lsl (== uxtx)
|
||||
// sxtw, sxtx, uxtw or lsl (== uxtx)
|
||||
bool IsLSL = !SignExtend && SrcRegKind == 'x';
|
||||
if (IsLSL) {
|
||||
SStream_concat0(O, "lsl");
|
||||
@ -1171,6 +1191,30 @@ static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKi
|
||||
}
|
||||
}
|
||||
|
||||
static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, unsigned Width)
|
||||
{
|
||||
unsigned SignExtend = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
unsigned DoShift = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
|
||||
printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O)
|
||||
}
|
||||
|
||||
static void printRegWithShiftExtend(MCInst *MI, unsigned OpNum, SStream *O,
|
||||
bool SignExtend, int ExtWidth,
|
||||
char SrcRegKind, char Suffix)
|
||||
{
|
||||
printOperand(MI, OpNum, O);
|
||||
if (Suffix == 's' || Suffix == 'd')
|
||||
SStream_concat0(O, ".", Suffix);
|
||||
// else
|
||||
// assert(Suffix == 0 && "Unsupported suffix size");
|
||||
|
||||
bool DoShift = ExtWidth != 8;
|
||||
if (SignExtend || DoShift || SrcRegKind == 'w') {
|
||||
SStream_concat0(O, ", ");
|
||||
printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O);
|
||||
}
|
||||
}
|
||||
|
||||
static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
A64CC_CondCode CC = (A64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
@ -1190,6 +1234,11 @@ static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
}
|
||||
}
|
||||
|
||||
static void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
SStream_concat0(O, "[", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName), "]");
|
||||
}
|
||||
|
||||
static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale)
|
||||
{
|
||||
int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
@ -1238,11 +1287,26 @@ static void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStrea
|
||||
}
|
||||
}
|
||||
|
||||
static void printUImm12Offset2(MCInst *MI, unsigned OpNum, SStream *O, int Scale)
|
||||
static void printUImm12Offset2(MCInst *MI, unsigned OpNum, SStream *O, unsigned int Scale)
|
||||
{
|
||||
printUImm12Offset(MI, OpNum, Scale, O);
|
||||
}
|
||||
|
||||
static void printAMIndexedWB(MCInst *MI, unsigned OpNum, SStream *O, unsigned int Scale)
|
||||
{
|
||||
MCOperand *MO = MCInst_getOperand(MI, OpNum + 1);
|
||||
SStream_concat0(O, "[", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName));
|
||||
if (MCOperand_isImm(MO)) {
|
||||
int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
printInt64Bang(O, val);
|
||||
// } else {
|
||||
// // assert(MO1.isExpr() && "Unexpected operand type!");
|
||||
// SStream_concat0(O, ", ");
|
||||
// MO1.getExpr()->print(O, &MAI);
|
||||
}
|
||||
SStream_concat0(O, "]");
|
||||
}
|
||||
|
||||
static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
@ -1273,6 +1337,17 @@ static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
}
|
||||
}
|
||||
|
||||
static void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNum);
|
||||
unsigned int psbhintop = MCOperand_getImm(Op);
|
||||
// auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
|
||||
// if (PSB)
|
||||
// O << PSB->Name;
|
||||
// else
|
||||
printInt32Bang(O, psbhintop);
|
||||
}
|
||||
|
||||
static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
MCOperand *MO = MCInst_getOperand(MI, OpNum);
|
||||
@ -1344,6 +1419,18 @@ static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride)
|
||||
return Reg;
|
||||
}
|
||||
|
||||
static void printGPRSeqPairsClassOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned int size)
|
||||
{
|
||||
// static_assert(size == 64 || size == 32,
|
||||
// "Template parameter must be either 32 or 64");
|
||||
unsigned Reg = MI->getOperand(OpNum).getReg();
|
||||
unsigned Sube = (size == 32) ? AArch64_sube32 : AArch64_sube64;
|
||||
unsigned Subo = (size == 32) ? AArch64_subo32 : AArch64_subo64;
|
||||
unsigned Even = MCRegisterInfo_getSubReg(MRI, Reg, Sube);
|
||||
unsigned Odd = MCRegisterInfo_getSubReg(MRI, Reg, Subo);
|
||||
SStream_concat0(O, getRegisterName(Even, AArch64_NoRegAltName), ", ", getRegisterName(Odd, AArch64_NoRegAltName);
|
||||
}
|
||||
|
||||
static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas, arm64_vess vess)
|
||||
{
|
||||
#define GETREGCLASS_CONTAIN0(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg)
|
||||
@ -1400,6 +1487,11 @@ static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *Layout
|
||||
SStream_concat0(O, "}");
|
||||
}
|
||||
|
||||
static void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
printVectorList(MI, OpNum, O, "");
|
||||
}
|
||||
|
||||
static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind, MCRegisterInfo *MRI)
|
||||
{
|
||||
char Suffix[32];
|
||||
@ -1544,9 +1636,9 @@ static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
}
|
||||
}
|
||||
|
||||
static void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
||||
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
unsigned Opcode = MCInst_getOpcode(MI);
|
||||
bool Valid;
|
||||
const char *Name;
|
||||
@ -1585,9 +1677,9 @@ static void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
}
|
||||
}
|
||||
|
||||
static void printMRSSystemRegister(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
||||
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
char Name[128];
|
||||
|
||||
A64SysRegMapper_toString(&AArch64_MRSMapper, Val, Name);
|
||||
@ -1606,9 +1698,9 @@ static void printMRSSystemRegister(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
}
|
||||
}
|
||||
|
||||
static void printMSRSystemRegister(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
||||
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
char Name[128];
|
||||
|
||||
A64SysRegMapper_toString(&AArch64_MSRMapper, Val, Name);
|
||||
@ -1627,9 +1719,9 @@ static void printMSRSystemRegister(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
}
|
||||
}
|
||||
|
||||
static void printSystemPStateField(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
||||
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
bool Valid;
|
||||
const char *Name;
|
||||
|
||||
@ -1663,9 +1755,9 @@ static void printSystemPStateField(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
}
|
||||
}
|
||||
|
||||
static void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
static void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
||||
uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal);
|
||||
SStream_concat(O, "#%#016llx", Val);
|
||||
if (MI->csh->detail) {
|
||||
@ -1681,6 +1773,127 @@ static void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
}
|
||||
}
|
||||
|
||||
static void printComplexRotationOp(MCInst *MI, unsigned OpNum, SStream *O, int64_t Angle, int64_t Remainder)
|
||||
{
|
||||
unsigned int Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
printInt64Bang((Val * Angle) + Remainder);
|
||||
}
|
||||
|
||||
static void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
// TODO: Fix this
|
||||
// if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
|
||||
// O << Pat->Name;
|
||||
// else
|
||||
SStream_concat0(O, "#", Val);
|
||||
}
|
||||
|
||||
static void printSVERegOp(MCInst *MI, unsigned OpNum, SStream *O, char suffix)
|
||||
{
|
||||
switch (suffix) {
|
||||
case 0:
|
||||
case 'b':
|
||||
case 'h':
|
||||
case 's':
|
||||
case 'd':
|
||||
case 'q':
|
||||
break;
|
||||
default:
|
||||
// llvm_unreachable("Invalid kind specifier.");
|
||||
}
|
||||
|
||||
unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
|
||||
if (suffix != 0)
|
||||
SStream_concat0(O, ".", suffix);
|
||||
}
|
||||
|
||||
// TODO: should I make a few more versions of this func to handle the other templates?
|
||||
static void printImmSVE(uint64_t Val, SStream *O)
|
||||
{
|
||||
// do not print number in negative form
|
||||
if (Val >= 0 && Val <= HEX_THRESHOLD)
|
||||
SStream_concat(O, "#%u", (int)Val);
|
||||
else
|
||||
SStream_concat(O, "#0x%"PRIx64, Val);
|
||||
// Do the opposite to that used for instruction operands.
|
||||
// TODO: Add CommentStream support
|
||||
// if (CommentStream) {
|
||||
// // do not print number in negative form
|
||||
// if (Val >= 0 && Val <= HEX_THRESHOLD)
|
||||
// SStream_concat(CommentStream, "=#%u\n", (int)Val);
|
||||
// else
|
||||
// SStream_concat(CommentStream, "=#0x%llx\n", Val);
|
||||
// }
|
||||
}
|
||||
|
||||
static void printImm8OptLsl(MCInst *MI, unsigned OpNum, SStream *O, bool is_signed)
|
||||
{
|
||||
unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
|
||||
// assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
|
||||
// "Unexepected shift type!");
|
||||
|
||||
// #0 lsl #8 is never pretty printed
|
||||
if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) {
|
||||
SStream_concat0(O, "#", UnscaledVal);
|
||||
printShifter(MI, OpNum + 1, O);
|
||||
return;
|
||||
}
|
||||
|
||||
if (is_signed)
|
||||
int8_t Val = (int8_t)UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift));
|
||||
else
|
||||
uint8_t Val = (uint8_t)UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift));
|
||||
|
||||
printImmSVE(Val, O);
|
||||
}
|
||||
|
||||
static void printSVELogicalImm(MCInst *MI, unsigned OpNum, SStream *O, bool Signed)
|
||||
{
|
||||
// typedef typename std::make_signed<T>::type SignedT;
|
||||
// typedef typename std::make_unsigned<T>::type UnsignedT;
|
||||
uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64);
|
||||
|
||||
// Prefer the default format for 16bit values, hex otherwise.
|
||||
if (Signed)
|
||||
printImmSVE((int16_t)PrintVal, O);
|
||||
else
|
||||
printUInt64Bang(O, PrintVal)
|
||||
}
|
||||
|
||||
static void printZPRasFPR(MCInst *MI, unsigned OpNum, SStream *O, int Width)
|
||||
{
|
||||
unsigned int Base;
|
||||
switch (Width) {
|
||||
case 8: Base = AArch64_B0; break;
|
||||
case 16: Base = AArch64_H0; break;
|
||||
case 32: Base = AArch64_S0; break;
|
||||
case 64: Base = AArch64_D0; break;
|
||||
case 128: Base = AArch64_Q0; break;
|
||||
default:
|
||||
// llvm_unreachable("Unsupported width");
|
||||
}
|
||||
unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum))
|
||||
SStream_concat0(O, getRegisterName(Reg - AArch64_Z0 + Base, AArch64_NoRegAltName));
|
||||
}
|
||||
|
||||
static void printExactFPImm(MCInst *MI, unsigned OpNum, SStream *O, unsigned ImmIs0, unsigned ImmIs1)
|
||||
{
|
||||
// TODO: fix this !!!!
|
||||
// auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
|
||||
// auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
|
||||
// unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
// O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
|
||||
}
|
||||
|
||||
static void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum))
|
||||
SStream_concat0(O, getRegisterName(getWRegFromXReg(Reg), AArch64_NoRegAltName));
|
||||
}
|
||||
|
||||
#define PRINT_ALIAS_INSTR
|
||||
#include "AArch64GenAsmWriter.inc"
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
#ifndef CS_LLVM_AARCH64INSTPRINTER_H
|
||||
#define CS_LLVM_AARCH64INSTPRINTER_H
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
#ifdef CAPSTONE_HAS_ARM64
|
||||
|
||||
@ -331,425 +331,11 @@ void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static const name_map insn_name_maps[] = {
|
||||
{ ARM64_INS_INVALID, NULL },
|
||||
|
||||
{ ARM64_INS_ABS, "abs" },
|
||||
{ ARM64_INS_ADC, "adc" },
|
||||
{ ARM64_INS_ADDHN, "addhn" },
|
||||
{ ARM64_INS_ADDHN2, "addhn2" },
|
||||
{ ARM64_INS_ADDP, "addp" },
|
||||
{ ARM64_INS_ADD, "add" },
|
||||
{ ARM64_INS_ADDV, "addv" },
|
||||
{ ARM64_INS_ADR, "adr" },
|
||||
{ ARM64_INS_ADRP, "adrp" },
|
||||
{ ARM64_INS_AESD, "aesd" },
|
||||
{ ARM64_INS_AESE, "aese" },
|
||||
{ ARM64_INS_AESIMC, "aesimc" },
|
||||
{ ARM64_INS_AESMC, "aesmc" },
|
||||
{ ARM64_INS_AND, "and" },
|
||||
{ ARM64_INS_ASR, "asr" },
|
||||
{ ARM64_INS_B, "b" },
|
||||
{ ARM64_INS_BFM, "bfm" },
|
||||
{ ARM64_INS_BIC, "bic" },
|
||||
{ ARM64_INS_BIF, "bif" },
|
||||
{ ARM64_INS_BIT, "bit" },
|
||||
{ ARM64_INS_BL, "bl" },
|
||||
{ ARM64_INS_BLR, "blr" },
|
||||
{ ARM64_INS_BR, "br" },
|
||||
{ ARM64_INS_BRK, "brk" },
|
||||
{ ARM64_INS_BSL, "bsl" },
|
||||
{ ARM64_INS_CBNZ, "cbnz" },
|
||||
{ ARM64_INS_CBZ, "cbz" },
|
||||
{ ARM64_INS_CCMN, "ccmn" },
|
||||
{ ARM64_INS_CCMP, "ccmp" },
|
||||
{ ARM64_INS_CLREX, "clrex" },
|
||||
{ ARM64_INS_CLS, "cls" },
|
||||
{ ARM64_INS_CLZ, "clz" },
|
||||
{ ARM64_INS_CMEQ, "cmeq" },
|
||||
{ ARM64_INS_CMGE, "cmge" },
|
||||
{ ARM64_INS_CMGT, "cmgt" },
|
||||
{ ARM64_INS_CMHI, "cmhi" },
|
||||
{ ARM64_INS_CMHS, "cmhs" },
|
||||
{ ARM64_INS_CMLE, "cmle" },
|
||||
{ ARM64_INS_CMLT, "cmlt" },
|
||||
{ ARM64_INS_CMTST, "cmtst" },
|
||||
{ ARM64_INS_CNT, "cnt" },
|
||||
{ ARM64_INS_MOV, "mov" },
|
||||
{ ARM64_INS_CRC32B, "crc32b" },
|
||||
{ ARM64_INS_CRC32CB, "crc32cb" },
|
||||
{ ARM64_INS_CRC32CH, "crc32ch" },
|
||||
{ ARM64_INS_CRC32CW, "crc32cw" },
|
||||
{ ARM64_INS_CRC32CX, "crc32cx" },
|
||||
{ ARM64_INS_CRC32H, "crc32h" },
|
||||
{ ARM64_INS_CRC32W, "crc32w" },
|
||||
{ ARM64_INS_CRC32X, "crc32x" },
|
||||
{ ARM64_INS_CSEL, "csel" },
|
||||
{ ARM64_INS_CSINC, "csinc" },
|
||||
{ ARM64_INS_CSINV, "csinv" },
|
||||
{ ARM64_INS_CSNEG, "csneg" },
|
||||
{ ARM64_INS_DCPS1, "dcps1" },
|
||||
{ ARM64_INS_DCPS2, "dcps2" },
|
||||
{ ARM64_INS_DCPS3, "dcps3" },
|
||||
{ ARM64_INS_DMB, "dmb" },
|
||||
{ ARM64_INS_DRPS, "drps" },
|
||||
{ ARM64_INS_DSB, "dsb" },
|
||||
{ ARM64_INS_DUP, "dup" },
|
||||
{ ARM64_INS_EON, "eon" },
|
||||
{ ARM64_INS_EOR, "eor" },
|
||||
{ ARM64_INS_ERET, "eret" },
|
||||
{ ARM64_INS_EXTR, "extr" },
|
||||
{ ARM64_INS_EXT, "ext" },
|
||||
{ ARM64_INS_FABD, "fabd" },
|
||||
{ ARM64_INS_FABS, "fabs" },
|
||||
{ ARM64_INS_FACGE, "facge" },
|
||||
{ ARM64_INS_FACGT, "facgt" },
|
||||
{ ARM64_INS_FADD, "fadd" },
|
||||
{ ARM64_INS_FADDP, "faddp" },
|
||||
{ ARM64_INS_FCCMP, "fccmp" },
|
||||
{ ARM64_INS_FCCMPE, "fccmpe" },
|
||||
{ ARM64_INS_FCMEQ, "fcmeq" },
|
||||
{ ARM64_INS_FCMGE, "fcmge" },
|
||||
{ ARM64_INS_FCMGT, "fcmgt" },
|
||||
{ ARM64_INS_FCMLE, "fcmle" },
|
||||
{ ARM64_INS_FCMLT, "fcmlt" },
|
||||
{ ARM64_INS_FCMP, "fcmp" },
|
||||
{ ARM64_INS_FCMPE, "fcmpe" },
|
||||
{ ARM64_INS_FCSEL, "fcsel" },
|
||||
{ ARM64_INS_FCVTAS, "fcvtas" },
|
||||
{ ARM64_INS_FCVTAU, "fcvtau" },
|
||||
{ ARM64_INS_FCVT, "fcvt" },
|
||||
{ ARM64_INS_FCVTL, "fcvtl" },
|
||||
{ ARM64_INS_FCVTL2, "fcvtl2" },
|
||||
{ ARM64_INS_FCVTMS, "fcvtms" },
|
||||
{ ARM64_INS_FCVTMU, "fcvtmu" },
|
||||
{ ARM64_INS_FCVTNS, "fcvtns" },
|
||||
{ ARM64_INS_FCVTNU, "fcvtnu" },
|
||||
{ ARM64_INS_FCVTN, "fcvtn" },
|
||||
{ ARM64_INS_FCVTN2, "fcvtn2" },
|
||||
{ ARM64_INS_FCVTPS, "fcvtps" },
|
||||
{ ARM64_INS_FCVTPU, "fcvtpu" },
|
||||
{ ARM64_INS_FCVTXN, "fcvtxn" },
|
||||
{ ARM64_INS_FCVTXN2, "fcvtxn2" },
|
||||
{ ARM64_INS_FCVTZS, "fcvtzs" },
|
||||
{ ARM64_INS_FCVTZU, "fcvtzu" },
|
||||
{ ARM64_INS_FDIV, "fdiv" },
|
||||
{ ARM64_INS_FMADD, "fmadd" },
|
||||
{ ARM64_INS_FMAX, "fmax" },
|
||||
{ ARM64_INS_FMAXNM, "fmaxnm" },
|
||||
{ ARM64_INS_FMAXNMP, "fmaxnmp" },
|
||||
{ ARM64_INS_FMAXNMV, "fmaxnmv" },
|
||||
{ ARM64_INS_FMAXP, "fmaxp" },
|
||||
{ ARM64_INS_FMAXV, "fmaxv" },
|
||||
{ ARM64_INS_FMIN, "fmin" },
|
||||
{ ARM64_INS_FMINNM, "fminnm" },
|
||||
{ ARM64_INS_FMINNMP, "fminnmp" },
|
||||
{ ARM64_INS_FMINNMV, "fminnmv" },
|
||||
{ ARM64_INS_FMINP, "fminp" },
|
||||
{ ARM64_INS_FMINV, "fminv" },
|
||||
{ ARM64_INS_FMLA, "fmla" },
|
||||
{ ARM64_INS_FMLS, "fmls" },
|
||||
{ ARM64_INS_FMOV, "fmov" },
|
||||
{ ARM64_INS_FMSUB, "fmsub" },
|
||||
{ ARM64_INS_FMUL, "fmul" },
|
||||
{ ARM64_INS_FMULX, "fmulx" },
|
||||
{ ARM64_INS_FNEG, "fneg" },
|
||||
{ ARM64_INS_FNMADD, "fnmadd" },
|
||||
{ ARM64_INS_FNMSUB, "fnmsub" },
|
||||
{ ARM64_INS_FNMUL, "fnmul" },
|
||||
{ ARM64_INS_FRECPE, "frecpe" },
|
||||
{ ARM64_INS_FRECPS, "frecps" },
|
||||
{ ARM64_INS_FRECPX, "frecpx" },
|
||||
{ ARM64_INS_FRINTA, "frinta" },
|
||||
{ ARM64_INS_FRINTI, "frinti" },
|
||||
{ ARM64_INS_FRINTM, "frintm" },
|
||||
{ ARM64_INS_FRINTN, "frintn" },
|
||||
{ ARM64_INS_FRINTP, "frintp" },
|
||||
{ ARM64_INS_FRINTX, "frintx" },
|
||||
{ ARM64_INS_FRINTZ, "frintz" },
|
||||
{ ARM64_INS_FRSQRTE, "frsqrte" },
|
||||
{ ARM64_INS_FRSQRTS, "frsqrts" },
|
||||
{ ARM64_INS_FSQRT, "fsqrt" },
|
||||
{ ARM64_INS_FSUB, "fsub" },
|
||||
{ ARM64_INS_HINT, "hint" },
|
||||
{ ARM64_INS_HLT, "hlt" },
|
||||
{ ARM64_INS_HVC, "hvc" },
|
||||
{ ARM64_INS_INS, "ins" },
|
||||
{ ARM64_INS_ISB, "isb" },
|
||||
{ ARM64_INS_LD1, "ld1" },
|
||||
{ ARM64_INS_LD1R, "ld1r" },
|
||||
{ ARM64_INS_LD2R, "ld2r" },
|
||||
{ ARM64_INS_LD2, "ld2" },
|
||||
{ ARM64_INS_LD3R, "ld3r" },
|
||||
{ ARM64_INS_LD3, "ld3" },
|
||||
{ ARM64_INS_LD4, "ld4" },
|
||||
{ ARM64_INS_LD4R, "ld4r" },
|
||||
{ ARM64_INS_LDARB, "ldarb" },
|
||||
{ ARM64_INS_LDARH, "ldarh" },
|
||||
{ ARM64_INS_LDAR, "ldar" },
|
||||
{ ARM64_INS_LDAXP, "ldaxp" },
|
||||
{ ARM64_INS_LDAXRB, "ldaxrb" },
|
||||
{ ARM64_INS_LDAXRH, "ldaxrh" },
|
||||
{ ARM64_INS_LDAXR, "ldaxr" },
|
||||
{ ARM64_INS_LDNP, "ldnp" },
|
||||
{ ARM64_INS_LDP, "ldp" },
|
||||
{ ARM64_INS_LDPSW, "ldpsw" },
|
||||
{ ARM64_INS_LDRB, "ldrb" },
|
||||
{ ARM64_INS_LDR, "ldr" },
|
||||
{ ARM64_INS_LDRH, "ldrh" },
|
||||
{ ARM64_INS_LDRSB, "ldrsb" },
|
||||
{ ARM64_INS_LDRSH, "ldrsh" },
|
||||
{ ARM64_INS_LDRSW, "ldrsw" },
|
||||
{ ARM64_INS_LDTRB, "ldtrb" },
|
||||
{ ARM64_INS_LDTRH, "ldtrh" },
|
||||
{ ARM64_INS_LDTRSB, "ldtrsb" },
|
||||
{ ARM64_INS_LDTRSH, "ldtrsh" },
|
||||
{ ARM64_INS_LDTRSW, "ldtrsw" },
|
||||
{ ARM64_INS_LDTR, "ldtr" },
|
||||
{ ARM64_INS_LDURB, "ldurb" },
|
||||
{ ARM64_INS_LDUR, "ldur" },
|
||||
{ ARM64_INS_LDURH, "ldurh" },
|
||||
{ ARM64_INS_LDURSB, "ldursb" },
|
||||
{ ARM64_INS_LDURSH, "ldursh" },
|
||||
{ ARM64_INS_LDURSW, "ldursw" },
|
||||
{ ARM64_INS_LDXP, "ldxp" },
|
||||
{ ARM64_INS_LDXRB, "ldxrb" },
|
||||
{ ARM64_INS_LDXRH, "ldxrh" },
|
||||
{ ARM64_INS_LDXR, "ldxr" },
|
||||
{ ARM64_INS_LSL, "lsl" },
|
||||
{ ARM64_INS_LSR, "lsr" },
|
||||
{ ARM64_INS_MADD, "madd" },
|
||||
{ ARM64_INS_MLA, "mla" },
|
||||
{ ARM64_INS_MLS, "mls" },
|
||||
{ ARM64_INS_MOVI, "movi" },
|
||||
{ ARM64_INS_MOVK, "movk" },
|
||||
{ ARM64_INS_MOVN, "movn" },
|
||||
{ ARM64_INS_MOVZ, "movz" },
|
||||
{ ARM64_INS_MRS, "mrs" },
|
||||
{ ARM64_INS_MSR, "msr" },
|
||||
{ ARM64_INS_MSUB, "msub" },
|
||||
{ ARM64_INS_MUL, "mul" },
|
||||
{ ARM64_INS_MVNI, "mvni" },
|
||||
{ ARM64_INS_NEG, "neg" },
|
||||
{ ARM64_INS_NOT, "not" },
|
||||
{ ARM64_INS_ORN, "orn" },
|
||||
{ ARM64_INS_ORR, "orr" },
|
||||
{ ARM64_INS_PMULL2, "pmull2" },
|
||||
{ ARM64_INS_PMULL, "pmull" },
|
||||
{ ARM64_INS_PMUL, "pmul" },
|
||||
{ ARM64_INS_PRFM, "prfm" },
|
||||
{ ARM64_INS_PRFUM, "prfum" },
|
||||
{ ARM64_INS_RADDHN, "raddhn" },
|
||||
{ ARM64_INS_RADDHN2, "raddhn2" },
|
||||
{ ARM64_INS_RBIT, "rbit" },
|
||||
{ ARM64_INS_RET, "ret" },
|
||||
{ ARM64_INS_REV16, "rev16" },
|
||||
{ ARM64_INS_REV32, "rev32" },
|
||||
{ ARM64_INS_REV64, "rev64" },
|
||||
{ ARM64_INS_REV, "rev" },
|
||||
{ ARM64_INS_ROR, "ror" },
|
||||
{ ARM64_INS_RSHRN2, "rshrn2" },
|
||||
{ ARM64_INS_RSHRN, "rshrn" },
|
||||
{ ARM64_INS_RSUBHN, "rsubhn" },
|
||||
{ ARM64_INS_RSUBHN2, "rsubhn2" },
|
||||
{ ARM64_INS_SABAL2, "sabal2" },
|
||||
{ ARM64_INS_SABAL, "sabal" },
|
||||
{ ARM64_INS_SABA, "saba" },
|
||||
{ ARM64_INS_SABDL2, "sabdl2" },
|
||||
{ ARM64_INS_SABDL, "sabdl" },
|
||||
{ ARM64_INS_SABD, "sabd" },
|
||||
{ ARM64_INS_SADALP, "sadalp" },
|
||||
{ ARM64_INS_SADDLP, "saddlp" },
|
||||
{ ARM64_INS_SADDLV, "saddlv" },
|
||||
{ ARM64_INS_SADDL2, "saddl2" },
|
||||
{ ARM64_INS_SADDL, "saddl" },
|
||||
{ ARM64_INS_SADDW2, "saddw2" },
|
||||
{ ARM64_INS_SADDW, "saddw" },
|
||||
{ ARM64_INS_SBC, "sbc" },
|
||||
{ ARM64_INS_SBFM, "sbfm" },
|
||||
{ ARM64_INS_SCVTF, "scvtf" },
|
||||
{ ARM64_INS_SDIV, "sdiv" },
|
||||
{ ARM64_INS_SHA1C, "sha1c" },
|
||||
{ ARM64_INS_SHA1H, "sha1h" },
|
||||
{ ARM64_INS_SHA1M, "sha1m" },
|
||||
{ ARM64_INS_SHA1P, "sha1p" },
|
||||
{ ARM64_INS_SHA1SU0, "sha1su0" },
|
||||
{ ARM64_INS_SHA1SU1, "sha1su1" },
|
||||
{ ARM64_INS_SHA256H2, "sha256h2" },
|
||||
{ ARM64_INS_SHA256H, "sha256h" },
|
||||
{ ARM64_INS_SHA256SU0, "sha256su0" },
|
||||
{ ARM64_INS_SHA256SU1, "sha256su1" },
|
||||
{ ARM64_INS_SHADD, "shadd" },
|
||||
{ ARM64_INS_SHLL2, "shll2" },
|
||||
{ ARM64_INS_SHLL, "shll" },
|
||||
{ ARM64_INS_SHL, "shl" },
|
||||
{ ARM64_INS_SHRN2, "shrn2" },
|
||||
{ ARM64_INS_SHRN, "shrn" },
|
||||
{ ARM64_INS_SHSUB, "shsub" },
|
||||
{ ARM64_INS_SLI, "sli" },
|
||||
{ ARM64_INS_SMADDL, "smaddl" },
|
||||
{ ARM64_INS_SMAXP, "smaxp" },
|
||||
{ ARM64_INS_SMAXV, "smaxv" },
|
||||
{ ARM64_INS_SMAX, "smax" },
|
||||
{ ARM64_INS_SMC, "smc" },
|
||||
{ ARM64_INS_SMINP, "sminp" },
|
||||
{ ARM64_INS_SMINV, "sminv" },
|
||||
{ ARM64_INS_SMIN, "smin" },
|
||||
{ ARM64_INS_SMLAL2, "smlal2" },
|
||||
{ ARM64_INS_SMLAL, "smlal" },
|
||||
{ ARM64_INS_SMLSL2, "smlsl2" },
|
||||
{ ARM64_INS_SMLSL, "smlsl" },
|
||||
{ ARM64_INS_SMOV, "smov" },
|
||||
{ ARM64_INS_SMSUBL, "smsubl" },
|
||||
{ ARM64_INS_SMULH, "smulh" },
|
||||
{ ARM64_INS_SMULL2, "smull2" },
|
||||
{ ARM64_INS_SMULL, "smull" },
|
||||
{ ARM64_INS_SQABS, "sqabs" },
|
||||
{ ARM64_INS_SQADD, "sqadd" },
|
||||
{ ARM64_INS_SQDMLAL, "sqdmlal" },
|
||||
{ ARM64_INS_SQDMLAL2, "sqdmlal2" },
|
||||
{ ARM64_INS_SQDMLSL, "sqdmlsl" },
|
||||
{ ARM64_INS_SQDMLSL2, "sqdmlsl2" },
|
||||
{ ARM64_INS_SQDMULH, "sqdmulh" },
|
||||
{ ARM64_INS_SQDMULL, "sqdmull" },
|
||||
{ ARM64_INS_SQDMULL2, "sqdmull2" },
|
||||
{ ARM64_INS_SQNEG, "sqneg" },
|
||||
{ ARM64_INS_SQRDMULH, "sqrdmulh" },
|
||||
{ ARM64_INS_SQRSHL, "sqrshl" },
|
||||
{ ARM64_INS_SQRSHRN, "sqrshrn" },
|
||||
{ ARM64_INS_SQRSHRN2, "sqrshrn2" },
|
||||
{ ARM64_INS_SQRSHRUN, "sqrshrun" },
|
||||
{ ARM64_INS_SQRSHRUN2, "sqrshrun2" },
|
||||
{ ARM64_INS_SQSHLU, "sqshlu" },
|
||||
{ ARM64_INS_SQSHL, "sqshl" },
|
||||
{ ARM64_INS_SQSHRN, "sqshrn" },
|
||||
{ ARM64_INS_SQSHRN2, "sqshrn2" },
|
||||
{ ARM64_INS_SQSHRUN, "sqshrun" },
|
||||
{ ARM64_INS_SQSHRUN2, "sqshrun2" },
|
||||
{ ARM64_INS_SQSUB, "sqsub" },
|
||||
{ ARM64_INS_SQXTN2, "sqxtn2" },
|
||||
{ ARM64_INS_SQXTN, "sqxtn" },
|
||||
{ ARM64_INS_SQXTUN2, "sqxtun2" },
|
||||
{ ARM64_INS_SQXTUN, "sqxtun" },
|
||||
{ ARM64_INS_SRHADD, "srhadd" },
|
||||
{ ARM64_INS_SRI, "sri" },
|
||||
{ ARM64_INS_SRSHL, "srshl" },
|
||||
{ ARM64_INS_SRSHR, "srshr" },
|
||||
{ ARM64_INS_SRSRA, "srsra" },
|
||||
{ ARM64_INS_SSHLL2, "sshll2" },
|
||||
{ ARM64_INS_SSHLL, "sshll" },
|
||||
{ ARM64_INS_SSHL, "sshl" },
|
||||
{ ARM64_INS_SSHR, "sshr" },
|
||||
{ ARM64_INS_SSRA, "ssra" },
|
||||
{ ARM64_INS_SSUBL2, "ssubl2" },
|
||||
{ ARM64_INS_SSUBL, "ssubl" },
|
||||
{ ARM64_INS_SSUBW2, "ssubw2" },
|
||||
{ ARM64_INS_SSUBW, "ssubw" },
|
||||
{ ARM64_INS_ST1, "st1" },
|
||||
{ ARM64_INS_ST2, "st2" },
|
||||
{ ARM64_INS_ST3, "st3" },
|
||||
{ ARM64_INS_ST4, "st4" },
|
||||
{ ARM64_INS_STLRB, "stlrb" },
|
||||
{ ARM64_INS_STLRH, "stlrh" },
|
||||
{ ARM64_INS_STLR, "stlr" },
|
||||
{ ARM64_INS_STLXP, "stlxp" },
|
||||
{ ARM64_INS_STLXRB, "stlxrb" },
|
||||
{ ARM64_INS_STLXRH, "stlxrh" },
|
||||
{ ARM64_INS_STLXR, "stlxr" },
|
||||
{ ARM64_INS_STNP, "stnp" },
|
||||
{ ARM64_INS_STP, "stp" },
|
||||
{ ARM64_INS_STRB, "strb" },
|
||||
{ ARM64_INS_STR, "str" },
|
||||
{ ARM64_INS_STRH, "strh" },
|
||||
{ ARM64_INS_STTRB, "sttrb" },
|
||||
{ ARM64_INS_STTRH, "sttrh" },
|
||||
{ ARM64_INS_STTR, "sttr" },
|
||||
{ ARM64_INS_STURB, "sturb" },
|
||||
{ ARM64_INS_STUR, "stur" },
|
||||
{ ARM64_INS_STURH, "sturh" },
|
||||
{ ARM64_INS_STXP, "stxp" },
|
||||
{ ARM64_INS_STXRB, "stxrb" },
|
||||
{ ARM64_INS_STXRH, "stxrh" },
|
||||
{ ARM64_INS_STXR, "stxr" },
|
||||
{ ARM64_INS_SUBHN, "subhn" },
|
||||
{ ARM64_INS_SUBHN2, "subhn2" },
|
||||
{ ARM64_INS_SUB, "sub" },
|
||||
{ ARM64_INS_SUQADD, "suqadd" },
|
||||
{ ARM64_INS_SVC, "svc" },
|
||||
{ ARM64_INS_SYSL, "sysl" },
|
||||
{ ARM64_INS_SYS, "sys" },
|
||||
{ ARM64_INS_TBL, "tbl" },
|
||||
{ ARM64_INS_TBNZ, "tbnz" },
|
||||
{ ARM64_INS_TBX, "tbx" },
|
||||
{ ARM64_INS_TBZ, "tbz" },
|
||||
{ ARM64_INS_TRN1, "trn1" },
|
||||
{ ARM64_INS_TRN2, "trn2" },
|
||||
{ ARM64_INS_UABAL2, "uabal2" },
|
||||
{ ARM64_INS_UABAL, "uabal" },
|
||||
{ ARM64_INS_UABA, "uaba" },
|
||||
{ ARM64_INS_UABDL2, "uabdl2" },
|
||||
{ ARM64_INS_UABDL, "uabdl" },
|
||||
{ ARM64_INS_UABD, "uabd" },
|
||||
{ ARM64_INS_UADALP, "uadalp" },
|
||||
{ ARM64_INS_UADDLP, "uaddlp" },
|
||||
{ ARM64_INS_UADDLV, "uaddlv" },
|
||||
{ ARM64_INS_UADDL2, "uaddl2" },
|
||||
{ ARM64_INS_UADDL, "uaddl" },
|
||||
{ ARM64_INS_UADDW2, "uaddw2" },
|
||||
{ ARM64_INS_UADDW, "uaddw" },
|
||||
{ ARM64_INS_UBFM, "ubfm" },
|
||||
{ ARM64_INS_UCVTF, "ucvtf" },
|
||||
{ ARM64_INS_UDIV, "udiv" },
|
||||
{ ARM64_INS_UHADD, "uhadd" },
|
||||
{ ARM64_INS_UHSUB, "uhsub" },
|
||||
{ ARM64_INS_UMADDL, "umaddl" },
|
||||
{ ARM64_INS_UMAXP, "umaxp" },
|
||||
{ ARM64_INS_UMAXV, "umaxv" },
|
||||
{ ARM64_INS_UMAX, "umax" },
|
||||
{ ARM64_INS_UMINP, "uminp" },
|
||||
{ ARM64_INS_UMINV, "uminv" },
|
||||
{ ARM64_INS_UMIN, "umin" },
|
||||
{ ARM64_INS_UMLAL2, "umlal2" },
|
||||
{ ARM64_INS_UMLAL, "umlal" },
|
||||
{ ARM64_INS_UMLSL2, "umlsl2" },
|
||||
{ ARM64_INS_UMLSL, "umlsl" },
|
||||
{ ARM64_INS_UMOV, "umov" },
|
||||
{ ARM64_INS_UMSUBL, "umsubl" },
|
||||
{ ARM64_INS_UMULH, "umulh" },
|
||||
{ ARM64_INS_UMULL2, "umull2" },
|
||||
{ ARM64_INS_UMULL, "umull" },
|
||||
{ ARM64_INS_UQADD, "uqadd" },
|
||||
{ ARM64_INS_UQRSHL, "uqrshl" },
|
||||
{ ARM64_INS_UQRSHRN, "uqrshrn" },
|
||||
{ ARM64_INS_UQRSHRN2, "uqrshrn2" },
|
||||
{ ARM64_INS_UQSHL, "uqshl" },
|
||||
{ ARM64_INS_UQSHRN, "uqshrn" },
|
||||
{ ARM64_INS_UQSHRN2, "uqshrn2" },
|
||||
{ ARM64_INS_UQSUB, "uqsub" },
|
||||
{ ARM64_INS_UQXTN2, "uqxtn2" },
|
||||
{ ARM64_INS_UQXTN, "uqxtn" },
|
||||
{ ARM64_INS_URECPE, "urecpe" },
|
||||
{ ARM64_INS_URHADD, "urhadd" },
|
||||
{ ARM64_INS_URSHL, "urshl" },
|
||||
{ ARM64_INS_URSHR, "urshr" },
|
||||
{ ARM64_INS_URSQRTE, "ursqrte" },
|
||||
{ ARM64_INS_URSRA, "ursra" },
|
||||
{ ARM64_INS_USHLL2, "ushll2" },
|
||||
{ ARM64_INS_USHLL, "ushll" },
|
||||
{ ARM64_INS_USHL, "ushl" },
|
||||
{ ARM64_INS_USHR, "ushr" },
|
||||
{ ARM64_INS_USQADD, "usqadd" },
|
||||
{ ARM64_INS_USRA, "usra" },
|
||||
{ ARM64_INS_USUBL2, "usubl2" },
|
||||
{ ARM64_INS_USUBL, "usubl" },
|
||||
{ ARM64_INS_USUBW2, "usubw2" },
|
||||
{ ARM64_INS_USUBW, "usubw" },
|
||||
{ ARM64_INS_UZP1, "uzp1" },
|
||||
{ ARM64_INS_UZP2, "uzp2" },
|
||||
{ ARM64_INS_XTN2, "xtn2" },
|
||||
{ ARM64_INS_XTN, "xtn" },
|
||||
{ ARM64_INS_ZIP1, "zip1" },
|
||||
{ ARM64_INS_ZIP2, "zip2" },
|
||||
#include "AArch64GenInsnNameMaps.inc"
|
||||
};
|
||||
|
||||
// map *S & alias instructions back to original id
|
||||
@ -802,6 +388,7 @@ static const name_map alias_insn_name_maps[] = {
|
||||
{ ARM64_INS_AT, "at" },
|
||||
{ ARM64_INS_TLBI, "tlbi" },
|
||||
};
|
||||
#endif
|
||||
|
||||
const char *AArch64_insn_name(csh handle, unsigned int id)
|
||||
{
|
||||
@ -812,7 +399,7 @@ const char *AArch64_insn_name(csh handle, unsigned int id)
|
||||
return NULL;
|
||||
|
||||
if (id < ARR_SIZE(insn_name_maps))
|
||||
return insn_name_maps[id].name;
|
||||
return insn_name_maps[id];
|
||||
|
||||
// then find alias insn
|
||||
for (i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) {
|
||||
@ -843,6 +430,24 @@ static const name_map group_name_maps[] = {
|
||||
{ ARM64_GRP_FPARMV8, "fparmv8" },
|
||||
{ ARM64_GRP_NEON, "neon" },
|
||||
{ ARM64_GRP_CRC, "crc" },
|
||||
|
||||
// new
|
||||
{ ARM64_GRP_HASAES, "hasaes" },
|
||||
{ ARM64_GRP_HASCRC, "hascrc" },
|
||||
{ ARM64_GRP_HASDOTPROD, "hasdotprod" },
|
||||
{ ARM64_GRP_HASFPARMV8, "hasfparmv8" },
|
||||
{ ARM64_GRP_HASFULLFP16, "hasfullfp16" },
|
||||
{ ARM64_GRP_HASLSE, "haslse" },
|
||||
{ ARM64_GRP_HASNEON, "hasneon" },
|
||||
{ ARM64_GRP_HASRCPC, "hasrcpc" },
|
||||
{ ARM64_GRP_HASRDM, "hasrdm" },
|
||||
{ ARM64_GRP_HASSHA2, "hassha2" },
|
||||
{ ARM64_GRP_HASSHA3, "hassha3" },
|
||||
{ ARM64_GRP_HASSM4, "hassm4" },
|
||||
{ ARM64_GRP_HASSVE, "hassve" },
|
||||
{ ARM64_GRP_HASV8_1A, "hasv8_1a" },
|
||||
{ ARM64_GRP_HASV8_3A, "hasv8_3a" },
|
||||
{ ARM64_GRP_HASV8_4A, "hasv8_4a" },
|
||||
};
|
||||
#endif
|
||||
|
||||
@ -1076,4 +681,4 @@ void AArch64_reg_access(const cs_insn *insn,
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
@ -1,5 +1,5 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
#ifndef CS_ARM64_MAP_H
|
||||
#define CS_ARM64_MAP_H
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user