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bindings: support QPX mode & QPX alias instructions

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This commit is contained in:
Nguyen Anh Quynh 2015-03-12 17:03:33 +08:00
parent b8ffb86b02
commit cac770a0cb
10 changed files with 56 additions and 3 deletions
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1
bindings/java/capstone/Capstone.java
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@ -304,6 +304,7 @@ public class Capstone {
public static final int CS_MODE_V9 = 1 << 4; // SparcV9 mode (Sparc arch)
public static final int CS_MODE_MIPS32 = CS_MODE_32; // Mips32 ISA
public static final int CS_MODE_MIPS64 = CS_MODE_64; // Mips64 ISA
public static final int CS_MODE_QPX = 1 << 4; // Quad Processing eXtensions mode (PPC)
// Capstone error
public static final int CS_ERR_OK = 0;

14
bindings/java/capstone/Ppc_const.java
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@ -1345,7 +1345,19 @@ public class Ppc_const {
public static final int PPC_INS_BDNZFLRL = 1095;
public static final int PPC_INS_BDZTLRL = 1096;
public static final int PPC_INS_BDZFLRL = 1097;
public static final int PPC_INS_ENDING = 1098;
public static final int PPC_INS_QVFAND = 1098;
public static final int PPC_INS_QVFCLR = 1099;
public static final int PPC_INS_QVFANDC = 1100;
public static final int PPC_INS_QVFCTFB = 1101;
public static final int PPC_INS_QVFXOR = 1102;
public static final int PPC_INS_QVFOR = 1103;
public static final int PPC_INS_QVFNOR = 1104;
public static final int PPC_INS_QVFEQU = 1105;
public static final int PPC_INS_QVFNOT = 1106;
public static final int PPC_INS_QVFORC = 1107;
public static final int PPC_INS_QVFNAND = 1108;
public static final int PPC_INS_QVFSET = 1109;
public static final int PPC_INS_ENDING = 1110;
// Group of PPC instructions

2
bindings/ocaml/capstone.ml
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@ -39,6 +39,8 @@ type mode =
| CS_MODE_BIG_ENDIAN (* big-endian mode *)
| CS_MODE_MIPS32 (* Mips32 mode (for Mips) *)
| CS_MODE_MIPS64 (* Mips64 mode (for Mips) *)
| CS_MODE_QPX (* Quad Processing eXtensions mode (PowerPC) *)
(* Runtime option for the disassembled engine *)

6
bindings/ocaml/ocaml.c
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@ -711,6 +711,9 @@ CAMLprim value ocaml_cs_disasm(value _arch, value _mode, value _code, value _add
case 14:
mode |= CS_MODE_MIPS64;
break;
case 15:
mode |= CS_MODE_QPX;
break;
default:
caml_invalid_argument("Invalid mode");
return Val_emptylist;
@ -839,6 +842,9 @@ CAMLprim value ocaml_open(value _arch, value _mode)
case 14:
mode |= CS_MODE_MIPS64;
break;
case 15:
mode |= CS_MODE_QPX;
break;
default:
caml_invalid_argument("Invalid mode");
return Val_emptylist;

14
bindings/ocaml/ppc_const.ml
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@ -1342,7 +1342,19 @@ let _PPC_INS_BDNZTLRL = 1094;;
let _PPC_INS_BDNZFLRL = 1095;;
let _PPC_INS_BDZTLRL = 1096;;
let _PPC_INS_BDZFLRL = 1097;;
let _PPC_INS_ENDING = 1098;;
let _PPC_INS_QVFAND = 1098;;
let _PPC_INS_QVFCLR = 1099;;
let _PPC_INS_QVFANDC = 1100;;
let _PPC_INS_QVFCTFB = 1101;;
let _PPC_INS_QVFXOR = 1102;;
let _PPC_INS_QVFOR = 1103;;
let _PPC_INS_QVFNOR = 1104;;
let _PPC_INS_QVFEQU = 1105;;
let _PPC_INS_QVFNOT = 1106;;
let _PPC_INS_QVFORC = 1107;;
let _PPC_INS_QVFNAND = 1108;;
let _PPC_INS_QVFSET = 1109;;
let _PPC_INS_ENDING = 1110;;
(* Group of PPC instructions *)

2
bindings/python/capstone/__init__.py
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@ -44,6 +44,7 @@ __all__ = [
'CS_MODE_V9',
'CS_MODE_MIPS32',
'CS_MODE_MIPS64',
'CS_MODE_QPX',
'CS_OPT_SYNTAX',
'CS_OPT_SYNTAX_DEFAULT',
@ -126,6 +127,7 @@ CS_MODE_V9 = (1 << 4) # Sparc V9 mode (for Sparc)
CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode
CS_MODE_MIPS32 = CS_MODE_32 # Mips32 ISA
CS_MODE_MIPS64 = CS_MODE_64 # Mips64 ISA
CS_MODE_QPX = (1 << 4) # Quad Processing eXtensions mode (PPC)
# Capstone option type
CS_OPT_SYNTAX = 1 # Intel X86 asm syntax (CS_ARCH_X86 arch)

14
bindings/python/capstone/ppc_const.py
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@ -1342,7 +1342,19 @@ PPC_INS_BDNZTLRL = 1094
PPC_INS_BDNZFLRL = 1095
PPC_INS_BDZTLRL = 1096
PPC_INS_BDZFLRL = 1097
PPC_INS_ENDING = 1098
PPC_INS_QVFAND = 1098
PPC_INS_QVFCLR = 1099
PPC_INS_QVFANDC = 1100
PPC_INS_QVFCTFB = 1101
PPC_INS_QVFXOR = 1102
PPC_INS_QVFOR = 1103
PPC_INS_QVFNOR = 1104
PPC_INS_QVFEQU = 1105
PPC_INS_QVFNOT = 1106
PPC_INS_QVFORC = 1107
PPC_INS_QVFNAND = 1108
PPC_INS_QVFSET = 1109
PPC_INS_ENDING = 1110
# Group of PPC instructions

2
bindings/python/test.py
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@ -26,6 +26,7 @@ MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
ARM64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
@ -49,6 +50,7 @@ all_tests = (
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", 0),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", 0),
(CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", 0),

2
bindings/python/test_detail.py
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@ -20,6 +20,7 @@ MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
@ -42,6 +43,7 @@ all_tests = (
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", 0),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", 0),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", 0),
(CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", 0),

2
bindings/python/test_ppc.py
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@ -7,9 +7,11 @@ from capstone.ppc import *
from xprint import to_x, to_hex, to_x_32
PPC_CODE = b"\x43\x20\x0c\x07\x41\x56\xff\x17\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
all_tests = (
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64"),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX"),
)