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https://github.com/capstone-engine/capstone.git
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mips: update core
This commit is contained in:
Nguyen Anh Quynh
parent
e0352d69d8
commit
cfe18ad7ca
@ -12,7 +12,7 @@
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#include "MCRegisterInfo.h"
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@ -14,7 +14,7 @@
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#ifndef CS_LLVM_MC_MCREGISTERINFO_H
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#define CS_LLVM_MC_MCREGISTERINFO_H
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@ -39,6 +39,18 @@ typedef struct MCRegisterClass {
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bool Allocatable;
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} MCRegisterClass;
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typedef struct MCRegisterClass2 {
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iterator RegsBegin;
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uint8_t *RegSet;
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uint32_t NameIdx;
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uint16_t RegsSize;
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uint16_t RegSetSize;
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uint16_t ID;
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uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
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int8_t CopyCost;
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bool Allocatable;
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} MCRegisterClass2;
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/// MCRegisterDesc - This record contains information about a particular
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/// register. The SubRegs field is a zero terminated array of registers that
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/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
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@ -12,7 +12,7 @@
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#ifdef CAPSTONE_HAS_MIPS
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@ -46,6 +46,15 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
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static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst,
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst,
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst,
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
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@ -118,6 +127,16 @@ static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
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static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
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unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
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// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
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// shifted left by 1 bit.
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static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst,
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unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
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// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
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// shifted left by 1 bit.
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static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst,
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unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
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// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
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// shifted left by 1 bit.
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static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
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@ -131,12 +150,33 @@ static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
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static DecodeStatus DecodeMem(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeCachePref(MCInst *Inst,
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static DecodeStatus DecodeCacheOp(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeCacheOpR6(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeCacheOpMM(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeSyncI(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeMSA128Mem(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeMemMMImm4(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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@ -146,15 +186,30 @@ static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
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static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn,
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uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeCOP2Mem(MCInst *Inst, unsigned Insn,
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static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn,
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uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeCOP3Mem(MCInst *Inst, unsigned Insn,
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static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn,
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uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn,
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uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst,
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unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst,
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unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeLiSimm7(MCInst *Inst,
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unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeSimm4(MCInst *Inst,
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unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeSimm16(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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@ -175,6 +230,18 @@ static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
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static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeSimm9SP(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeANDI16Imm(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeUImm5lsl2(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst,
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
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/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
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/// handle.
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static DecodeStatus DecodeINSVE_DF_4(MCInst *MI,
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@ -198,6 +265,14 @@ static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI,
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static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI,
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uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeRegListOperand(MCInst *Inst,
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uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeRegListOperand16(MCInst *Inst,
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uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
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static DecodeStatus DecodeMovePRegPair(MCInst *Inst,
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uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
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#define GET_SUBTARGETINFO_ENUM
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#include "MipsGenSubtargetInfo.inc"
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@ -265,19 +340,22 @@ static uint64_t getFeatureBits(int mode)
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void Mips_init(MCRegisterInfo *MRI)
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{
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// InitMCRegisterInfo(MipsRegDesc, 394, RA, PC,
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// MipsMCRegisterClasses, 48,
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// MipsMCRegisterClasses, 62,
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// MipsRegUnitRoots,
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// 273,
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// MipsRegDiffLists,
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// MipsLaneMaskLists,
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// MipsRegStrings,
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// MipsRegClassStrings,
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// MipsSubRegIdxLists,
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// 12,
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// MipsSubRegIdxRanges,
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// MipsRegEncodingTable);
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MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394,
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0, 0,
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MipsMCRegisterClasses, 48,
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MipsMCRegisterClasses, 62,
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0, 0,
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MipsRegDiffLists,
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0,
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@ -285,36 +363,44 @@ void Mips_init(MCRegisterInfo *MRI)
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0);
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}
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/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
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/// according to the given endianess.
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static void readInstruction16(unsigned char *code, uint32_t *insn,
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bool IsBigEndian)
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{
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// We want to read exactly 2 Bytes of data.
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if (IsBigEndian)
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*insn = (code[0] << 8) | code[1];
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else
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*insn = (code[1] << 8) | code[0];
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}
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/// readInstruction - read four bytes from the MemoryObject
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/// and return 32 bit word sorted according to the given endianess
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static DecodeStatus readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips)
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static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips)
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{
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// High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
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// always precede the low 16 bits in the instruction stream (that is, they
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// are placed at lower addresses in the instruction stream).
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//
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// microMIPS byte ordering:
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// Big-endian: 0 | 1 | 2 | 3
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// Little-endian: 1 | 0 | 3 | 2
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// We want to read exactly 4 Bytes of data.
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if (isBigEndian) {
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if (IsBigEndian) {
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// Encoded as a big-endian 32-bit word in the stream.
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*insn = (code[3] << 0) |
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(code[2] << 8) |
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(code[1] << 16) |
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(code[0] << 24);
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*insn =
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(code[3] << 0) | (code[2] << 8) | (code[1] << 16) | (code[0] << 24);
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} else {
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// Encoded as a small-endian 32-bit word in the stream.
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// Little-endian byte ordering:
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// mips32r2: 4 | 3 | 2 | 1
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// microMIPS: 2 | 1 | 4 | 3
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if (isMicroMips) {
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*insn = (code[2] << 0) |
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(code[3] << 8) |
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(code[0] << 16) |
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if (IsMicroMips) {
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*insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) |
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(code[1] << 24);
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} else {
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*insn = (code[0] << 0) |
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(code[1] << 8) |
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(code[2] << 16) |
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*insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) |
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(code[3] << 24);
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}
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}
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return MCDisassembler_Success;
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}
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static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
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@ -325,20 +411,31 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
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uint32_t Insn;
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DecodeStatus Result;
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if (code_len < 4)
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// not enough data
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return MCDisassembler_Fail;
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if (instr->flat_insn->detail) {
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memset(instr->flat_insn->detail, 0, sizeof(cs_detail));
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}
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Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian,
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mode & CS_MODE_MICRO);
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if (Result == MCDisassembler_Fail)
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return MCDisassembler_Fail;
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if (mode & CS_MODE_MICRO) {
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if (code_len < 2)
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// not enough data
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return MCDisassembler_Fail;
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readInstruction16((unsigned char*)code, &Insn, IsBigEndian);
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode);
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if (Result != MCDisassembler_Fail) {
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*Size = 2;
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return Result;
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}
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if (code_len < 4)
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// not enough data
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return MCDisassembler_Fail;
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readInstruction32((unsigned char*)code, &Insn, IsBigEndian, true);
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//DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode);
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if (Result != MCDisassembler_Fail) {
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@ -348,9 +445,13 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
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return MCDisassembler_Fail;
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}
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#if 0
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// TODO: properly handle this in the future with MIPS1/2 modes
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if (((mode & CS_MODE_32) == 0) && ((mode & CS_MODE_MIPS3) == 0)) { // COP3
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if (code_len < 4)
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// not enough data
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return MCDisassembler_Fail;
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readInstruction32((unsigned char*)code, &Insn, IsBigEndian, false);
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if (hasCOP3()) {
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// DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
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Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode);
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if (Result != MCDisassembler_Fail) {
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@ -358,9 +459,8 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
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return Result;
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}
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}
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#endif
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if (((mode & CS_MODE_MIPS32R6) != 0) && ((mode & CS_MODE_MIPSGP64) != 0)) {
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if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPSGP64)) {
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// DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
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Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
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Address, MRI, mode);
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@ -370,7 +470,7 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
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}
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}
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if ((mode & CS_MODE_MIPS32R6) != 0) {
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if (mode & CS_MODE_MIPS32R6) {
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// DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
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Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
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Address, MRI, mode);
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@ -380,6 +480,17 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
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}
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}
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if (mode & CS_MODE_MIPSGP64) {
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// DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
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Result = decodeInstruction(DecoderTableMips6432, instr, Insn,
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Address, MRI, mode)
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if (Result != MCDisassembler_Fail) {
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*Size = 4;
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return Result;
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}
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}
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// DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode);
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if (Result != MCDisassembler_Fail) {
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@ -403,55 +514,8 @@ bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *i
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return status == MCDisassembler_Success;
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}
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static DecodeStatus Mips64Disassembler_getInstruction(int mode, MCInst *instr,
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const uint8_t *code, size_t code_len,
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uint16_t *Size,
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uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI)
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{
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uint32_t Insn;
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DecodeStatus Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian, false);
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if (Result == MCDisassembler_Fail)
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return MCDisassembler_Fail;
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if (instr->flat_insn->detail) {
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memset(instr->flat_insn->detail, 0, sizeof(cs_detail));
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}
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address, MRI, mode);
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if (Result != MCDisassembler_Fail) {
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*Size = 4;
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return Result;
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}
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// If we fail to decode in Mips64 decoder space we can try in Mips32
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Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode);
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if (Result != MCDisassembler_Fail) {
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*Size = 4;
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return Result;
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}
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return MCDisassembler_Fail;
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}
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bool Mips64_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
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uint16_t *size, uint64_t address, void *info)
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{
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cs_struct *handle = (cs_struct *)(uintptr_t)ud;
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DecodeStatus status = Mips64Disassembler_getInstruction(handle->mode, instr,
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code, code_len,
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size,
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address, handle->big_endian, (MCRegisterInfo *)info);
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|
||||
return status == MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
|
||||
{
|
||||
//MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
|
||||
//return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
|
||||
MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
|
||||
return rc->RegsBegin[RegNo];
|
||||
}
|
||||
@ -766,6 +830,45 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 7)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo);
|
||||
MCOperand_CreateReg0(Inst, Reg);
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 7)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo);
|
||||
MCOperand_CreateReg0(Inst, Reg);
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
if (RegNo > 7)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo);
|
||||
MCOperand_CreateReg0(Inst, Reg);
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
@ -782,7 +885,8 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
|
||||
static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
if (Inst->csh->mode & CS_MODE_64)
|
||||
// if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
|
||||
if (Inst->csh->mode & CS_MODE_MIPSGP64) // FIXME
|
||||
return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
|
||||
|
||||
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
|
||||
@ -878,11 +982,12 @@ static DecodeStatus DecodeMem(MCInst *Inst,
|
||||
int Offset = SignExtend32(Insn & 0xffff, 16);
|
||||
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
|
||||
unsigned Base = fieldFromInstruction(Insn, 21, 5);
|
||||
int opcode = MCInst_getOpcode(Inst);
|
||||
|
||||
Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
|
||||
Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
|
||||
|
||||
if (MCInst_getOpcode(Inst) == Mips_SC){
|
||||
if (opcode == Mips_SC || opcode == Mips_SCD) {
|
||||
MCOperand_CreateReg0(Inst, Reg);
|
||||
}
|
||||
|
||||
@ -893,7 +998,7 @@ static DecodeStatus DecodeMem(MCInst *Inst,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeCachePref(MCInst *Inst,
|
||||
static DecodeStatus DecodeCacheOp(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0xffff, 16);
|
||||
@ -909,6 +1014,52 @@ static DecodeStatus DecodeCachePref(MCInst *Inst,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeCacheOpMM(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0xfff, 12);
|
||||
unsigned Base = fieldFromInstruction(Insn, 16, 5);
|
||||
unsigned Hint = fieldFromInstruction(Insn, 21, 5);
|
||||
|
||||
Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
|
||||
|
||||
MCOperand_CreateReg0(Inst, Base);
|
||||
MCOperand_CreateImm0(Inst, Offset);
|
||||
MCOperand_CreateImm0(Inst, Hint);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeCacheOpR6(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = fieldFromInstruction(Insn, 7, 9);
|
||||
unsigned Hint = fieldFromInstruction(Insn, 16, 5);
|
||||
unsigned Base = fieldFromInstruction(Insn, 21, 5);
|
||||
|
||||
Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
|
||||
|
||||
MCOperand_CreateReg0(Inst, Base);
|
||||
MCOperand_CreateImm0(Inst, Offset);
|
||||
MCOperand_CreateImm0(Inst, Hint);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSyncI(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0xffff, 16);
|
||||
unsigned Base = fieldFromInstruction(Insn, 21, 5);
|
||||
|
||||
Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
|
||||
|
||||
MCOperand_CreateReg0(Inst, Base);
|
||||
MCOperand_CreateImm0(Inst, Offset);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
@ -956,6 +1107,101 @@ static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeMemMMImm4(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Offset = Insn & 0xf;
|
||||
unsigned Reg = fieldFromInstruction(Insn, 7, 3);
|
||||
unsigned Base = fieldFromInstruction(Insn, 4, 3);
|
||||
|
||||
switch (MCInst_getOpcode(Inst)) {
|
||||
case Mips_LBU16_MM:
|
||||
case Mips_LHU16_MM:
|
||||
case Mips_LW16_MM:
|
||||
if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
|
||||
== MCDisassembler_Fail)
|
||||
return MCDisassembler_Fail;
|
||||
break;
|
||||
case Mips_SB16_MM:
|
||||
case Mips_SH16_MM:
|
||||
case Mips_SW16_MM:
|
||||
if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
|
||||
== MCDisassembler_Fail)
|
||||
return MCDisassembler_Fail;
|
||||
break;
|
||||
}
|
||||
|
||||
if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
|
||||
== MCDisassembler_Fail)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
switch (MCInst_getOpcode(Inst)) {
|
||||
case Mips_LBU16_MM:
|
||||
if (Offset == 0xf)
|
||||
MCOperand_CreateImm0(Inst, -1);
|
||||
else
|
||||
MCOperand_CreateImm0(Inst, Offset);
|
||||
break;
|
||||
case Mips_SB16_MM:
|
||||
MCOperand_CreateImm0(Inst, Offset);
|
||||
break;
|
||||
case Mips_LHU16_MM:
|
||||
case Mips_SH16_MM:
|
||||
MCOperand_CreateImm0(Inst, Offset << 1);
|
||||
break;
|
||||
case Mips_LW16_MM:
|
||||
case Mips_SW16_MM:
|
||||
MCOperand_CreateImm0(Inst, Offset << 2);
|
||||
break;
|
||||
}
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Offset = Insn & 0x1F;
|
||||
unsigned Reg = fieldFromInstruction(Insn, 5, 5);
|
||||
|
||||
Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
|
||||
|
||||
MCOperand_CreateReg0(Inst, Reg);
|
||||
MCOperand_CreateReg0(Inst, Mips_SP);
|
||||
MCOperand_CreateImm0(Inst, Offset << 2);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Offset = Insn & 0x7F;
|
||||
unsigned Reg = fieldFromInstruction(Insn, 7, 3);
|
||||
|
||||
Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
|
||||
|
||||
MCOperand_CreateReg0(Inst, Reg);
|
||||
MCOperand_CreateReg0(Inst, Mips_GP);
|
||||
MCOperand_CreateImm0(Inst, Offset << 2);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0xf, 4);
|
||||
|
||||
if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCOperand_CreateReg0(Inst, Mips_SP);
|
||||
MCOperand_CreateImm0(Inst, Offset << 2);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
@ -966,12 +1212,26 @@ static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
|
||||
Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
|
||||
Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
|
||||
|
||||
if (MCInst_getOpcode(Inst) == Mips_SC_MM)
|
||||
MCOperand_CreateReg0(Inst, Reg);
|
||||
switch (Inst.getOpcode()) {
|
||||
case Mips_SWM32_MM:
|
||||
case Mips_LWM32_MM:
|
||||
if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
|
||||
== MCDisassembler_Fail)
|
||||
return MCDisassembler_Fail;
|
||||
MCOperand_CreateReg0(Inst, Base);
|
||||
MCOperand_CreateImm0(Inst, Offset);
|
||||
break;
|
||||
case Mips_SC_MM:
|
||||
MCOperand_CreateReg0(Inst, Reg);
|
||||
// fallthrough
|
||||
default:
|
||||
MCOperand_CreateReg0(Inst, Reg);
|
||||
if (Inst.getOpcode() == Mips_LWP_MM || Inst.getOpcode() == Mips_SWP_MM)
|
||||
MCOperand_CreateReg0(Inst, Reg + 1);
|
||||
|
||||
MCOperand_CreateReg0(Inst, Reg);
|
||||
MCOperand_CreateReg0(Inst, Base);
|
||||
MCOperand_CreateImm0(Inst, Offset);
|
||||
MCOperand_CreateReg0(Inst, Base);
|
||||
MCOperand_CreateImm0(Inst, Offset);
|
||||
}
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
@ -1010,7 +1270,7 @@ static DecodeStatus DecodeFMem(MCInst *Inst,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeCOP2Mem(MCInst *Inst,
|
||||
static DecodeStatus DecodeFMem2(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0xffff, 16);
|
||||
@ -1027,7 +1287,7 @@ static DecodeStatus DecodeCOP2Mem(MCInst *Inst,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeCOP3Mem(MCInst *Inst,
|
||||
static DecodeStatus DecodeFMem3(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0xffff, 16);
|
||||
@ -1044,6 +1304,23 @@ static DecodeStatus DecodeCOP3Mem(MCInst *Inst,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeFMemCop2R6(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0x07ff, 11);
|
||||
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
|
||||
unsigned Base = fieldFromInstruction(Insn, 11, 5);
|
||||
|
||||
Reg = getReg(Decoder, Mips_COP2RegClassID, Reg);
|
||||
Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
|
||||
|
||||
MCOperand_CreateReg0(Inst, Reg);
|
||||
MCOperand_CreateReg0(Inst, Base);
|
||||
MCOperand_CreateImm0(Inst, Offset);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
@ -1254,6 +1531,22 @@ static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst,
|
||||
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
int32_t BranchOffset = SignExtend32(Offset, 7) << 1;
|
||||
MCOperand_CreateImm0(Inst, BranchOffset);
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst,
|
||||
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
int32_t BranchOffset = SignExtend32(Offset, 10) << 1;
|
||||
MCOperand_CreateImm0(Inst, BranchOffset);
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
|
||||
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
@ -1272,10 +1565,51 @@ static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst,
|
||||
unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
if (Value == 0)
|
||||
MCOperand_CreateImm0(Inst, 1);
|
||||
else if (Value == 0x7)
|
||||
MCOperand_CreateImm0(Inst, -1);
|
||||
else
|
||||
MCOperand_CreateImm0(Inst, Value << 2);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst,
|
||||
unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, Value << 2);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeLiSimm7(MCInst *Inst,
|
||||
unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
if (Value == 0x7F)
|
||||
MCOperand_CreateImm0(Inst, -1)
|
||||
else
|
||||
MCOperand_CreateImm0(Inst, Value);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSimm4(MCInst *Inst,
|
||||
unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, SignExtend32(Value, 4));
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSimm16(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16));
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
@ -1284,6 +1618,7 @@ static DecodeStatus DecodeLSAImm(MCInst *Inst,
|
||||
{
|
||||
// We add one to the immediate field as it was encoded as 'imm - 1'.
|
||||
MCOperand_CreateImm0(Inst, Insn + 1);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
@ -1294,14 +1629,17 @@ static DecodeStatus DecodeInsSize(MCInst *Inst,
|
||||
int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2));
|
||||
int Size = (int) Insn - Pos + 1;
|
||||
MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeExtSize(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Size = (int) Insn + 1;
|
||||
int Size = (int)Insn + 1;
|
||||
|
||||
MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
@ -1309,6 +1647,7 @@ static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
@ -1316,6 +1655,136 @@ static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
int32_t DecodedValue;
|
||||
|
||||
switch (Insn) {
|
||||
case 0: DecodedValue = 256; break;
|
||||
case 1: DecodedValue = 257; break;
|
||||
case 510: DecodedValue = -258; break;
|
||||
case 511: DecodedValue = -257; break;
|
||||
default: DecodedValue = SignExtend32(Insn, 9); break;
|
||||
}
|
||||
MCOperand_CreateImm0(Inst, DecodedValue * 4);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
// Insn must be >= 0, since it is unsigned that condition is always true.
|
||||
// assert(Insn < 16);
|
||||
int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
|
||||
255, 32768, 65535};
|
||||
|
||||
MCOperand_CreateImm0(Inst, DecodedValues[Insn]);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, Insn << 2);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5,
|
||||
Mips_S6, Mips_FP};
|
||||
unsigned RegNum;
|
||||
unsigned int i;
|
||||
|
||||
unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
|
||||
// Empty register lists are not allowed.
|
||||
if (RegLst == 0)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
RegNum = RegLst & 0xf;
|
||||
for (i = 0; i < RegNum; i++)
|
||||
MCOperand_CreateReg0(Inst, Regs[i]);
|
||||
|
||||
if (RegLst & 0x10)
|
||||
MCOperand_CreateReg0(Inst, Mips_RA);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3};
|
||||
unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
|
||||
unsigned RegNum = RegLst & 0x3;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i <= RegNum; i++)
|
||||
MCOperand_CreateReg0(Inst, Regs[i]);
|
||||
|
||||
MCOperand_CreateReg0(Inst, Mips_RA);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
|
||||
|
||||
switch (RegPair) {
|
||||
default:
|
||||
return MCDisassembler_Fail;
|
||||
case 0:
|
||||
MCOperand_CreateReg0(Inst, Mips_A1);
|
||||
MCOperand_CreateReg0(Inst, Mips_A2);
|
||||
break;
|
||||
case 1:
|
||||
MCOperand_CreateReg0(Inst, Mips_A1);
|
||||
MCOperand_CreateReg0(Inst, Mips_A3);
|
||||
break;
|
||||
case 2:
|
||||
MCOperand_CreateReg0(Inst, Mips_A2);
|
||||
MCOperand_CreateReg0(Inst, Mips_A3);
|
||||
break;
|
||||
case 3:
|
||||
MCOperand_CreateReg0(Inst, Mips_A0);
|
||||
MCOperand_CreateReg0(Inst, Mips_S5);
|
||||
break;
|
||||
case 4:
|
||||
MCOperand_CreateReg0(Inst, Mips_A0);
|
||||
MCOperand_CreateReg0(Inst, Mips_S6);
|
||||
break;
|
||||
case 5:
|
||||
MCOperand_CreateReg0(Inst, Mips_A0);
|
||||
MCOperand_CreateReg0(Inst, Mips_A1);
|
||||
break;
|
||||
case 6:
|
||||
MCOperand_CreateReg0(Inst, Mips_A0);
|
||||
MCOperand_CreateReg0(Inst, Mips_A2);
|
||||
break;
|
||||
case 7:
|
||||
MCOperand_CreateReg0(Inst, Mips_A0);
|
||||
MCOperand_CreateReg0(Inst, Mips_A3);
|
||||
break;
|
||||
}
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) << 2);
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -7,7 +7,7 @@
|
||||
\*===----------------------------------------------------------------------===*/
|
||||
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
|
||||
|
||||
#ifdef GET_SUBTARGETINFO_ENUM
|
||||
@ -16,35 +16,35 @@
|
||||
#define Mips_FeatureCnMips (1ULL << 0)
|
||||
#define Mips_FeatureDSP (1ULL << 1)
|
||||
#define Mips_FeatureDSPR2 (1ULL << 2)
|
||||
#define Mips_FeatureEABI (1ULL << 3)
|
||||
#define Mips_FeatureFP64Bit (1ULL << 4)
|
||||
#define Mips_FeatureFPXX (1ULL << 5)
|
||||
#define Mips_FeatureGP64Bit (1ULL << 6)
|
||||
#define Mips_FeatureMSA (1ULL << 7)
|
||||
#define Mips_FeatureMicroMips (1ULL << 8)
|
||||
#define Mips_FeatureMips1 (1ULL << 9)
|
||||
#define Mips_FeatureMips2 (1ULL << 10)
|
||||
#define Mips_FeatureMips3 (1ULL << 11)
|
||||
#define Mips_FeatureMips3_32 (1ULL << 12)
|
||||
#define Mips_FeatureMips3_32r2 (1ULL << 13)
|
||||
#define Mips_FeatureMips4 (1ULL << 14)
|
||||
#define Mips_FeatureMips4_32 (1ULL << 15)
|
||||
#define Mips_FeatureMips4_32r2 (1ULL << 16)
|
||||
#define Mips_FeatureMips5 (1ULL << 17)
|
||||
#define Mips_FeatureMips5_32r2 (1ULL << 18)
|
||||
#define Mips_FeatureMips16 (1ULL << 19)
|
||||
#define Mips_FeatureMips32 (1ULL << 20)
|
||||
#define Mips_FeatureMips32r2 (1ULL << 21)
|
||||
#define Mips_FeatureMips32r6 (1ULL << 22)
|
||||
#define Mips_FeatureMips64 (1ULL << 23)
|
||||
#define Mips_FeatureMips64r2 (1ULL << 24)
|
||||
#define Mips_FeatureMips64r6 (1ULL << 25)
|
||||
#define Mips_FeatureN32 (1ULL << 26)
|
||||
#define Mips_FeatureN64 (1ULL << 27)
|
||||
#define Mips_FeatureNaN2008 (1ULL << 28)
|
||||
#define Mips_FeatureNoABICalls (1ULL << 29)
|
||||
#define Mips_FeatureNoOddSPReg (1ULL << 30)
|
||||
#define Mips_FeatureO32 (1ULL << 31)
|
||||
#define Mips_FeatureFP64Bit (1ULL << 3)
|
||||
#define Mips_FeatureFPXX (1ULL << 4)
|
||||
#define Mips_FeatureGP64Bit (1ULL << 5)
|
||||
#define Mips_FeatureMSA (1ULL << 6)
|
||||
#define Mips_FeatureMicroMips (1ULL << 7)
|
||||
#define Mips_FeatureMips1 (1ULL << 8)
|
||||
#define Mips_FeatureMips2 (1ULL << 9)
|
||||
#define Mips_FeatureMips3 (1ULL << 10)
|
||||
#define Mips_FeatureMips3_32 (1ULL << 11)
|
||||
#define Mips_FeatureMips3_32r2 (1ULL << 12)
|
||||
#define Mips_FeatureMips4 (1ULL << 13)
|
||||
#define Mips_FeatureMips4_32 (1ULL << 14)
|
||||
#define Mips_FeatureMips4_32r2 (1ULL << 15)
|
||||
#define Mips_FeatureMips5 (1ULL << 16)
|
||||
#define Mips_FeatureMips5_32r2 (1ULL << 17)
|
||||
#define Mips_FeatureMips16 (1ULL << 18)
|
||||
#define Mips_FeatureMips32 (1ULL << 19)
|
||||
#define Mips_FeatureMips32r2 (1ULL << 20)
|
||||
#define Mips_FeatureMips32r3 (1ULL << 21)
|
||||
#define Mips_FeatureMips32r5 (1ULL << 22)
|
||||
#define Mips_FeatureMips32r6 (1ULL << 23)
|
||||
#define Mips_FeatureMips64 (1ULL << 24)
|
||||
#define Mips_FeatureMips64r2 (1ULL << 25)
|
||||
#define Mips_FeatureMips64r3 (1ULL << 26)
|
||||
#define Mips_FeatureMips64r5 (1ULL << 27)
|
||||
#define Mips_FeatureMips64r6 (1ULL << 28)
|
||||
#define Mips_FeatureNaN2008 (1ULL << 29)
|
||||
#define Mips_FeatureNoABICalls (1ULL << 30)
|
||||
#define Mips_FeatureNoOddSPReg (1ULL << 31)
|
||||
#define Mips_FeatureSingleFloat (1ULL << 32)
|
||||
#define Mips_FeatureVFPU (1ULL << 33)
|
||||
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
|
||||
#ifdef CAPSTONE_HAS_MIPS
|
||||
|
||||
@ -290,6 +290,20 @@ static void printMemOperand(MCInst *MI, int opNum, SStream *O)
|
||||
// Load/Store memory operands -- imm($reg)
|
||||
// If PIC target the target is loaded as the
|
||||
// pattern lw $25,%call16($28)
|
||||
|
||||
// opNum can be invalid if instruction had reglist as operand.
|
||||
// MemOperand is always last operand of instruction (base + offset).
|
||||
switch (MCInst_getOpcode(MI)) {
|
||||
default:
|
||||
break;
|
||||
case Mips_SWM32_MM:
|
||||
case Mips_LWM32_MM:
|
||||
case Mips_SWM16_MM:
|
||||
case Mips_LWM16_MM:
|
||||
opNum = MCInst_getNumOperands(MI) - 2;
|
||||
break;
|
||||
}
|
||||
|
||||
set_mem_access(MI, true);
|
||||
printOperand(MI, opNum + 1, O);
|
||||
SStream_concat0(O, "(");
|
||||
@ -315,6 +329,11 @@ static void printFCCOperand(MCInst *MI, int opNum, SStream *O)
|
||||
SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
|
||||
}
|
||||
|
||||
static void printRegisterPair(MCInst *MI, int opNum, SStream *O)
|
||||
{
|
||||
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum)));
|
||||
}
|
||||
|
||||
static char *printAlias1(char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
|
||||
{
|
||||
SStream_concat(OS, "%s\t", Str);
|
||||
@ -341,6 +360,7 @@ static char *printAlias(MCInst *MI, SStream *OS)
|
||||
{
|
||||
switch (MCInst_getOpcode(MI)) {
|
||||
case Mips_BEQ:
|
||||
case Mips_BEQ_MM:
|
||||
// beq $zero, $zero, $L2 => b $L2
|
||||
// beq $r0, $zero, $L2 => beqz $r0, $L2
|
||||
if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
|
||||
@ -348,11 +368,6 @@ static char *printAlias(MCInst *MI, SStream *OS)
|
||||
if (isReg(MI, 1, Mips_ZERO))
|
||||
return printAlias2("beqz", MI, 0, 2, OS);
|
||||
return NULL;
|
||||
case Mips_BEQL:
|
||||
// beql $r0, $zero, $L2 => beqzl $r0, $L2
|
||||
if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
|
||||
return printAlias2("beqzl", MI, 0, 2, OS);
|
||||
return NULL;
|
||||
case Mips_BEQ64:
|
||||
// beq $r0, $zero, $L2 => beqz $r0, $L2
|
||||
if (isReg(MI, 1, Mips_ZERO_64))
|
||||
@ -363,11 +378,6 @@ static char *printAlias(MCInst *MI, SStream *OS)
|
||||
if (isReg(MI, 1, Mips_ZERO))
|
||||
return printAlias2("bnez", MI, 0, 2, OS);
|
||||
return NULL;
|
||||
case Mips_BNEL:
|
||||
// bnel $r0, $zero, $L2 => bnezl $r0, $L2
|
||||
if (isReg(MI, 1, Mips_ZERO))
|
||||
return printAlias2("bnezl", MI, 0, 2, OS);
|
||||
return NULL;
|
||||
case Mips_BNE64:
|
||||
// bne $r0, $zero, $L2 => bnez $r0, $L2
|
||||
if (isReg(MI, 1, Mips_ZERO_64))
|
||||
@ -418,6 +428,19 @@ static char *printAlias(MCInst *MI, SStream *OS)
|
||||
}
|
||||
}
|
||||
|
||||
static void printRegisterList(MCInst *MI, int opNum, SStream *O)
|
||||
{
|
||||
int i;
|
||||
|
||||
// - 2 because register List is always first operand of instruction and it is
|
||||
// always followed by memory operand (base + offset).
|
||||
for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) {
|
||||
if (i != opNum)
|
||||
SStream_concat0(O, ", ");
|
||||
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, i)));
|
||||
}
|
||||
}
|
||||
|
||||
#define PRINT_ALIAS_INSTR
|
||||
#include "MipsGenAsmWriter.inc"
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
|
||||
#ifdef CAPSTONE_HAS_MIPS
|
||||
|
||||
|
||||
@ -29,11 +29,7 @@ static cs_err init(cs_struct *ud)
|
||||
ud->insn_id = Mips_get_insn_id;
|
||||
ud->insn_name = Mips_insn_name;
|
||||
ud->group_name = Mips_group_name;
|
||||
|
||||
if (ud->mode & CS_MODE_32 || ud->mode & CS_MODE_MIPS32R6)
|
||||
ud->disasm = Mips_getInstruction;
|
||||
else
|
||||
ud->disasm = Mips64_getInstruction;
|
||||
ud->disasm = Mips_getInstruction;
|
||||
|
||||
return CS_ERR_OK;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user