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refactor: Refactor TriCore register names.

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- Rename TriCore register names for better readability
- Update TriCore instruction information
This commit is contained in:
billow 2023-04-02 01:10:08 +08:00
parent ad0e18fece
commit d515e62ddc
2 changed files with 304 additions and 275 deletions
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571
arch/TriCore/TriCoreInstrInfo.td
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8
arch/TriCore/TriCoreRegisterInfo.td
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@ -118,24 +118,24 @@ def FCX : TriCorePSReg<3, "fcx">, DwarfRegNum<[43]>;
//@Register Classes
//===----------------------------------------------------------------------===//
def DataRegs : RegisterClass<"TriCore", [i32], 32, (add
def RD : RegisterClass<"TriCore", [i32], 32, (add
D0, D1, D2, D3, D4,
D5, D6, D7, D8, D9,
D10, D11, D12, D13, D14,
D15)>;
def AddrRegs : RegisterClass<"TriCore", [i32], 32, (add
def RA : RegisterClass<"TriCore", [i32], 32, (add
A0, A1, A2, A3, A4,
A5, A6, A7, A8, A9,
A10, A11, A12, A13, A14,
A15)>;
def ExtRegs : RegisterClass<"TriCore", [i64], 64, (add
def RE : RegisterClass<"TriCore", [i64], 64, (add
E0, E2, E4,
E6, E8, E10,
E12, E14)>;
def AddrExtRegs : RegisterClass<"TriCore", [i64], 64, (add
def RP : RegisterClass<"TriCore", [i64], 64, (add
P0, P2, P4,
P6, P8, P10,
P12, P14)>;