Fix all compiler errors

This commit is contained in:
Sidney Pontes Filho 2016-08-04 17:50:25 +02:00 committed by billow
parent 4ec3dd12a8
commit dd4011297b
3 changed files with 17 additions and 19 deletions

1
.gitignore vendored
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@ -62,6 +62,7 @@ tests/test_skipdata
tests/test_sparc
tests/test_systemz
tests/test_xcore
tests/test_tricore
tests/*.static
tests/test_customized_mnem
tests/test_m68k

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@ -101,7 +101,7 @@ static insn_map insns[] = {
{
TriCore_ABS, TRICORE_INS_ABS,
#ifndef CAPSTONE_DIET
{ 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{
@ -113,13 +113,13 @@ static insn_map insns[] = {
{
TriCore_ADDCrc, TRICORE_INS_ADD,
#ifndef CAPSTONE_DIET
{ TriCore_PSW, 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ TRICORE_REG_PSW, 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_ADDCrr, TRICORE_INS_ADD,
#ifndef CAPSTONE_DIET
{ TriCore_PSW, 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ TRICORE_REG_PSW, 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{
@ -131,25 +131,25 @@ static insn_map insns[] = {
{
TriCore_ADDXrc, TRICORE_INS_ADD,
#ifndef CAPSTONE_DIET
{ TriCore_PSW, 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ TRICORE_REG_PSW, 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_ADDXrr, TRICORE_INS_ADD,
#ifndef CAPSTONE_DIET
{ TriCore_PSW, 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ TRICORE_REG_PSW, 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_ADDi64, TRICORE_INS_ADD,
#ifndef CAPSTONE_DIET
{ 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_ADDi64C, TRICORE_INS_ADD,
#ifndef CAPSTONE_DIET
{ 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{
@ -275,7 +275,7 @@ static insn_map insns[] = {
{
TriCore_CALLb, TRICORE_INS_CALL,
#ifndef CAPSTONE_DIET
{ TriCore_A10, 0 }, { TriCore_A11, 0 }, { 0 }, 0, 0
{ TRICORE_REG_A10, 0 }, { TRICORE_REG_A11, 0 }, { 0 }, 0, 0
#endif
},
{
@ -449,19 +449,19 @@ static insn_map insns[] = {
{
TriCore_MULrc, TRICORE_INS_MUL,
#ifndef CAPSTONE_DIET
{ 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_MULrr2, TRICORE_INS_MUL,
#ifndef CAPSTONE_DIET
{ 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_MULsrr, TRICORE_INS_MUL,
#ifndef CAPSTONE_DIET
{ 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{
@ -690,25 +690,25 @@ static insn_map insns[] = {
{
TriCore_SUBAsc, TRICORE_INS_SUBA,
#ifndef CAPSTONE_DIET
{ TriCore_A10, 0 }, { TriCore_A10, 0 }, { 0 }, 0, 0
{ TRICORE_REG_A10, 0 }, { TRICORE_REG_A10, 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_SUBCrr, TRICORE_INS_SUBC,
#ifndef CAPSTONE_DIET
{ TriCore_PSW, 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ TRICORE_REG_PSW, 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_SUBXrr, TRICORE_INS_SUBX,
#ifndef CAPSTONE_DIET
{ TriCore_PSW, 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ TRICORE_REG_PSW, 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_SUBi64, TRICORE_INS_SUB,
#ifndef CAPSTONE_DIET
{ 0 }, { TriCore_PSW, 0 }, { 0 }, 0, 0
{ 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
#endif
},
{

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@ -64,9 +64,6 @@ static void print_insn_detail(cs_insn *ins)
i, cs_reg_name(handle, op->mem.index));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
if (op->mem.direct != 1)
printf("\t\t\toperands[%u].mem.direct: -1\n", i);
break;
}
@ -77,7 +74,7 @@ static void print_insn_detail(cs_insn *ins)
static void test()
{
#define TRICORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10\x09\xfd\xec\xa7"
#define TRICORE_CODE "\x16\x01"
struct platform platforms[] = {
{