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move some alias registers around to after REG_MAX. this seems to fix some issues of clang, which struggles with enum that assign value from other enum

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This commit is contained in:
Nguyen Anh Quynh 2013-12-04 12:10:47 +08:00
parent b39ef0bfa6
commit ea5b79d058
8 changed files with 331 additions and 289 deletions
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6
bindings/java/capstone/Arm_const.java
View File

@ -119,9 +119,6 @@ public class Arm_const {
public static final int ARM_REG_R10 = 76;
public static final int ARM_REG_R11 = 77;
public static final int ARM_REG_R12 = 78;
public static final int ARM_REG_R13 = ARM_REG_SP;
public static final int ARM_REG_R14 = ARM_REG_LR;
public static final int ARM_REG_R15 = ARM_REG_PC;
public static final int ARM_REG_S0 = 79;
public static final int ARM_REG_S1 = 80;
public static final int ARM_REG_S2 = 81;
@ -155,6 +152,9 @@ public class Arm_const {
public static final int ARM_REG_S30 = 109;
public static final int ARM_REG_S31 = 110;
public static final int ARM_REG_MAX = 111;
public static final int ARM_REG_R13 = ARM_REG_SP;
public static final int ARM_REG_R14 = ARM_REG_LR;
public static final int ARM_REG_R15 = ARM_REG_PC;
public static final int ARM_INS_INVALID = 0;
public static final int ARM_INS_ADC = 1;

238
bindings/java/capstone/Mips_const.java
View File

@ -10,166 +10,166 @@ public class Mips_const {
public static final int MIPS_REG_INVALID = 0;
public static final int MIPS_REG_0 = 1;
public static final int MIPS_REG_1 = 2;
public static final int MIPS_REG_2 = 3;
public static final int MIPS_REG_3 = 4;
public static final int MIPS_REG_4 = 5;
public static final int MIPS_REG_5 = 6;
public static final int MIPS_REG_6 = 7;
public static final int MIPS_REG_7 = 8;
public static final int MIPS_REG_8 = 9;
public static final int MIPS_REG_9 = 10;
public static final int MIPS_REG_10 = 11;
public static final int MIPS_REG_11 = 12;
public static final int MIPS_REG_12 = 13;
public static final int MIPS_REG_13 = 14;
public static final int MIPS_REG_14 = 15;
public static final int MIPS_REG_15 = 16;
public static final int MIPS_REG_16 = 17;
public static final int MIPS_REG_17 = 18;
public static final int MIPS_REG_18 = 19;
public static final int MIPS_REG_19 = 20;
public static final int MIPS_REG_20 = 21;
public static final int MIPS_REG_21 = 22;
public static final int MIPS_REG_22 = 23;
public static final int MIPS_REG_23 = 24;
public static final int MIPS_REG_24 = 25;
public static final int MIPS_REG_25 = 26;
public static final int MIPS_REG_26 = 27;
public static final int MIPS_REG_27 = 28;
public static final int MIPS_REG_28 = 29;
public static final int MIPS_REG_29 = 30;
public static final int MIPS_REG_30 = 31;
public static final int MIPS_REG_31 = 32;
public static final int MIPS_REG_DSPCCOND = 33;
public static final int MIPS_REG_DSPCARRY = 34;
public static final int MIPS_REG_DSPEFI = 35;
public static final int MIPS_REG_DSPOUTFLAG = 36;
public static final int MIPS_REG_DSPOUTFLAG16_19 = 37;
public static final int MIPS_REG_DSPOUTFLAG20 = 38;
public static final int MIPS_REG_DSPOUTFLAG21 = 39;
public static final int MIPS_REG_DSPOUTFLAG22 = 40;
public static final int MIPS_REG_DSPOUTFLAG23 = 41;
public static final int MIPS_REG_DSPPOS = 42;
public static final int MIPS_REG_DSPSCOUNT = 43;
public static final int MIPS_REG_AC0 = 44;
public static final int MIPS_REG_AC1 = 45;
public static final int MIPS_REG_AC2 = 46;
public static final int MIPS_REG_AC3 = 47;
public static final int MIPS_REG_F0 = 48;
public static final int MIPS_REG_F1 = 49;
public static final int MIPS_REG_F2 = 50;
public static final int MIPS_REG_F3 = 51;
public static final int MIPS_REG_F4 = 52;
public static final int MIPS_REG_F5 = 53;
public static final int MIPS_REG_F6 = 54;
public static final int MIPS_REG_F7 = 55;
public static final int MIPS_REG_F8 = 56;
public static final int MIPS_REG_F9 = 57;
public static final int MIPS_REG_F10 = 58;
public static final int MIPS_REG_F11 = 59;
public static final int MIPS_REG_F12 = 60;
public static final int MIPS_REG_F13 = 61;
public static final int MIPS_REG_F14 = 62;
public static final int MIPS_REG_F15 = 63;
public static final int MIPS_REG_F16 = 64;
public static final int MIPS_REG_F17 = 65;
public static final int MIPS_REG_F18 = 66;
public static final int MIPS_REG_F19 = 67;
public static final int MIPS_REG_F20 = 68;
public static final int MIPS_REG_F21 = 69;
public static final int MIPS_REG_F22 = 70;
public static final int MIPS_REG_F23 = 71;
public static final int MIPS_REG_F24 = 72;
public static final int MIPS_REG_F25 = 73;
public static final int MIPS_REG_F26 = 74;
public static final int MIPS_REG_F27 = 75;
public static final int MIPS_REG_F28 = 76;
public static final int MIPS_REG_F29 = 77;
public static final int MIPS_REG_F30 = 78;
public static final int MIPS_REG_F31 = 79;
public static final int MIPS_REG_FCC0 = 80;
public static final int MIPS_REG_FCC1 = 81;
public static final int MIPS_REG_FCC2 = 82;
public static final int MIPS_REG_FCC3 = 83;
public static final int MIPS_REG_FCC4 = 84;
public static final int MIPS_REG_FCC5 = 85;
public static final int MIPS_REG_FCC6 = 86;
public static final int MIPS_REG_FCC7 = 87;
public static final int MIPS_REG_W0 = 88;
public static final int MIPS_REG_W1 = 89;
public static final int MIPS_REG_W2 = 90;
public static final int MIPS_REG_W3 = 91;
public static final int MIPS_REG_W4 = 92;
public static final int MIPS_REG_W5 = 93;
public static final int MIPS_REG_W6 = 94;
public static final int MIPS_REG_W7 = 95;
public static final int MIPS_REG_W8 = 96;
public static final int MIPS_REG_W9 = 97;
public static final int MIPS_REG_W10 = 98;
public static final int MIPS_REG_W11 = 99;
public static final int MIPS_REG_W12 = 100;
public static final int MIPS_REG_W13 = 101;
public static final int MIPS_REG_W14 = 102;
public static final int MIPS_REG_W15 = 103;
public static final int MIPS_REG_W16 = 104;
public static final int MIPS_REG_W17 = 105;
public static final int MIPS_REG_W18 = 106;
public static final int MIPS_REG_W19 = 107;
public static final int MIPS_REG_W20 = 108;
public static final int MIPS_REG_W21 = 109;
public static final int MIPS_REG_W22 = 110;
public static final int MIPS_REG_W23 = 111;
public static final int MIPS_REG_W24 = 112;
public static final int MIPS_REG_W25 = 113;
public static final int MIPS_REG_W26 = 114;
public static final int MIPS_REG_W27 = 115;
public static final int MIPS_REG_W28 = 116;
public static final int MIPS_REG_W29 = 117;
public static final int MIPS_REG_W30 = 118;
public static final int MIPS_REG_W31 = 119;
public static final int MIPS_REG_MAX = 120;
public static final int MIPS_REG_ZERO = MIPS_REG_0;
public static final int MIPS_REG_1 = 1;
public static final int MIPS_REG_AT = MIPS_REG_1;
public static final int MIPS_REG_2 = 2;
public static final int MIPS_REG_V0 = MIPS_REG_2;
public static final int MIPS_REG_3 = 3;
public static final int MIPS_REG_V1 = MIPS_REG_3;
public static final int MIPS_REG_4 = 4;
public static final int MIPS_REG_A0 = MIPS_REG_4;
public static final int MIPS_REG_5 = 5;
public static final int MIPS_REG_A1 = MIPS_REG_5;
public static final int MIPS_REG_6 = 6;
public static final int MIPS_REG_A2 = MIPS_REG_6;
public static final int MIPS_REG_7 = 7;
public static final int MIPS_REG_A3 = MIPS_REG_7;
public static final int MIPS_REG_8 = 8;
public static final int MIPS_REG_T0 = MIPS_REG_8;
public static final int MIPS_REG_9 = 9;
public static final int MIPS_REG_T1 = MIPS_REG_9;
public static final int MIPS_REG_10 = 10;
public static final int MIPS_REG_T2 = MIPS_REG_10;
public static final int MIPS_REG_11 = 11;
public static final int MIPS_REG_T3 = MIPS_REG_11;
public static final int MIPS_REG_12 = 12;
public static final int MIPS_REG_T4 = MIPS_REG_12;
public static final int MIPS_REG_13 = 13;
public static final int MIPS_REG_T5 = MIPS_REG_13;
public static final int MIPS_REG_14 = 14;
public static final int MIPS_REG_T6 = MIPS_REG_14;
public static final int MIPS_REG_15 = 15;
public static final int MIPS_REG_T7 = MIPS_REG_15;
public static final int MIPS_REG_16 = 16;
public static final int MIPS_REG_S0 = MIPS_REG_16;
public static final int MIPS_REG_17 = 17;
public static final int MIPS_REG_S1 = MIPS_REG_17;
public static final int MIPS_REG_18 = 18;
public static final int MIPS_REG_S2 = MIPS_REG_18;
public static final int MIPS_REG_19 = 19;
public static final int MIPS_REG_S3 = MIPS_REG_19;
public static final int MIPS_REG_20 = 20;
public static final int MIPS_REG_S4 = MIPS_REG_20;
public static final int MIPS_REG_21 = 21;
public static final int MIPS_REG_S5 = MIPS_REG_21;
public static final int MIPS_REG_22 = 22;
public static final int MIPS_REG_S6 = MIPS_REG_22;
public static final int MIPS_REG_23 = 23;
public static final int MIPS_REG_S7 = MIPS_REG_23;
public static final int MIPS_REG_24 = 24;
public static final int MIPS_REG_T8 = MIPS_REG_24;
public static final int MIPS_REG_25 = 25;
public static final int MIPS_REG_T9 = MIPS_REG_25;
public static final int MIPS_REG_26 = 26;
public static final int MIPS_REG_K0 = MIPS_REG_26;
public static final int MIPS_REG_27 = 27;
public static final int MIPS_REG_K1 = MIPS_REG_27;
public static final int MIPS_REG_28 = 28;
public static final int MIPS_REG_GP = MIPS_REG_28;
public static final int MIPS_REG_29 = 29;
public static final int MIPS_REG_SP = MIPS_REG_29;
public static final int MIPS_REG_30 = 30;
public static final int MIPS_REG_FP = MIPS_REG_30;
public static final int MIPS_REG_S8 = MIPS_REG_30;
public static final int MIPS_REG_31 = 31;
public static final int MIPS_REG_RA = MIPS_REG_31;
public static final int MIPS_REG_DSPCCOND = 32;
public static final int MIPS_REG_DSPCARRY = 33;
public static final int MIPS_REG_DSPEFI = 34;
public static final int MIPS_REG_DSPOUTFLAG = 35;
public static final int MIPS_REG_DSPOUTFLAG16_19 = 36;
public static final int MIPS_REG_DSPOUTFLAG20 = 37;
public static final int MIPS_REG_DSPOUTFLAG21 = 38;
public static final int MIPS_REG_DSPOUTFLAG22 = 39;
public static final int MIPS_REG_DSPOUTFLAG23 = 40;
public static final int MIPS_REG_DSPPOS = 41;
public static final int MIPS_REG_DSPSCOUNT = 42;
public static final int MIPS_REG_AC0 = 43;
public static final int MIPS_REG_HI0 = MIPS_REG_AC0;
public static final int MIPS_REG_AC1 = 44;
public static final int MIPS_REG_HI1 = MIPS_REG_AC1;
public static final int MIPS_REG_AC2 = 45;
public static final int MIPS_REG_HI2 = MIPS_REG_AC2;
public static final int MIPS_REG_AC3 = 46;
public static final int MIPS_REG_HI3 = MIPS_REG_AC3;
public static final int MIPS_REG_LO0 = MIPS_REG_HI0;
public static final int MIPS_REG_LO1 = MIPS_REG_HI1;
public static final int MIPS_REG_LO2 = MIPS_REG_HI2;
public static final int MIPS_REG_LO3 = MIPS_REG_HI3;
public static final int MIPS_REG_F0 = 47;
public static final int MIPS_REG_F1 = 48;
public static final int MIPS_REG_F2 = 49;
public static final int MIPS_REG_F3 = 50;
public static final int MIPS_REG_F4 = 51;
public static final int MIPS_REG_F5 = 52;
public static final int MIPS_REG_F6 = 53;
public static final int MIPS_REG_F7 = 54;
public static final int MIPS_REG_F8 = 55;
public static final int MIPS_REG_F9 = 56;
public static final int MIPS_REG_F10 = 57;
public static final int MIPS_REG_F11 = 58;
public static final int MIPS_REG_F12 = 59;
public static final int MIPS_REG_F13 = 60;
public static final int MIPS_REG_F14 = 61;
public static final int MIPS_REG_F15 = 62;
public static final int MIPS_REG_F16 = 63;
public static final int MIPS_REG_F17 = 64;
public static final int MIPS_REG_F18 = 65;
public static final int MIPS_REG_F19 = 66;
public static final int MIPS_REG_F20 = 67;
public static final int MIPS_REG_F21 = 68;
public static final int MIPS_REG_F22 = 69;
public static final int MIPS_REG_F23 = 70;
public static final int MIPS_REG_F24 = 71;
public static final int MIPS_REG_F25 = 72;
public static final int MIPS_REG_F26 = 73;
public static final int MIPS_REG_F27 = 74;
public static final int MIPS_REG_F28 = 75;
public static final int MIPS_REG_F29 = 76;
public static final int MIPS_REG_F30 = 77;
public static final int MIPS_REG_F31 = 78;
public static final int MIPS_REG_FCC0 = 79;
public static final int MIPS_REG_FCC1 = 80;
public static final int MIPS_REG_FCC2 = 81;
public static final int MIPS_REG_FCC3 = 82;
public static final int MIPS_REG_FCC4 = 83;
public static final int MIPS_REG_FCC5 = 84;
public static final int MIPS_REG_FCC6 = 85;
public static final int MIPS_REG_FCC7 = 86;
public static final int MIPS_REG_W0 = 87;
public static final int MIPS_REG_W1 = 88;
public static final int MIPS_REG_W2 = 89;
public static final int MIPS_REG_W3 = 90;
public static final int MIPS_REG_W4 = 91;
public static final int MIPS_REG_W5 = 92;
public static final int MIPS_REG_W6 = 93;
public static final int MIPS_REG_W7 = 94;
public static final int MIPS_REG_W8 = 95;
public static final int MIPS_REG_W9 = 96;
public static final int MIPS_REG_W10 = 97;
public static final int MIPS_REG_W11 = 98;
public static final int MIPS_REG_W12 = 99;
public static final int MIPS_REG_W13 = 100;
public static final int MIPS_REG_W14 = 101;
public static final int MIPS_REG_W15 = 102;
public static final int MIPS_REG_W16 = 103;
public static final int MIPS_REG_W17 = 104;
public static final int MIPS_REG_W18 = 105;
public static final int MIPS_REG_W19 = 106;
public static final int MIPS_REG_W20 = 107;
public static final int MIPS_REG_W21 = 108;
public static final int MIPS_REG_W22 = 109;
public static final int MIPS_REG_W23 = 110;
public static final int MIPS_REG_W24 = 111;
public static final int MIPS_REG_W25 = 112;
public static final int MIPS_REG_W26 = 113;
public static final int MIPS_REG_W27 = 114;
public static final int MIPS_REG_W28 = 115;
public static final int MIPS_REG_W29 = 116;
public static final int MIPS_REG_W30 = 117;
public static final int MIPS_REG_W31 = 118;
public static final int MIPS_REG_MAX = 119;
public static final int MIPS_INS_INVALID = 0;
public static final int MIPS_INS_ABSQ_S = 1;

6
bindings/python/capstone/arm_const.py
View File

@ -116,9 +116,6 @@ ARM_REG_R9 = 75
ARM_REG_R10 = 76
ARM_REG_R11 = 77
ARM_REG_R12 = 78
ARM_REG_R13 = ARM_REG_SP
ARM_REG_R14 = ARM_REG_LR
ARM_REG_R15 = ARM_REG_PC
ARM_REG_S0 = 79
ARM_REG_S1 = 80
ARM_REG_S2 = 81
@ -152,6 +149,9 @@ ARM_REG_S29 = 108
ARM_REG_S30 = 109
ARM_REG_S31 = 110
ARM_REG_MAX = 111
ARM_REG_R13 = ARM_REG_SP
ARM_REG_R14 = ARM_REG_LR
ARM_REG_R15 = ARM_REG_PC
ARM_INS_INVALID = 0
ARM_INS_ADC = 1

238
bindings/python/capstone/mips_const.py
View File

@ -7,166 +7,166 @@ MIPS_OP_MEM = 3
MIPS_REG_INVALID = 0
MIPS_REG_0 = 1
MIPS_REG_1 = 2
MIPS_REG_2 = 3
MIPS_REG_3 = 4
MIPS_REG_4 = 5
MIPS_REG_5 = 6
MIPS_REG_6 = 7
MIPS_REG_7 = 8
MIPS_REG_8 = 9
MIPS_REG_9 = 10
MIPS_REG_10 = 11
MIPS_REG_11 = 12
MIPS_REG_12 = 13
MIPS_REG_13 = 14
MIPS_REG_14 = 15
MIPS_REG_15 = 16
MIPS_REG_16 = 17
MIPS_REG_17 = 18
MIPS_REG_18 = 19
MIPS_REG_19 = 20
MIPS_REG_20 = 21
MIPS_REG_21 = 22
MIPS_REG_22 = 23
MIPS_REG_23 = 24
MIPS_REG_24 = 25
MIPS_REG_25 = 26
MIPS_REG_26 = 27
MIPS_REG_27 = 28
MIPS_REG_28 = 29
MIPS_REG_29 = 30
MIPS_REG_30 = 31
MIPS_REG_31 = 32
MIPS_REG_DSPCCOND = 33
MIPS_REG_DSPCARRY = 34
MIPS_REG_DSPEFI = 35
MIPS_REG_DSPOUTFLAG = 36
MIPS_REG_DSPOUTFLAG16_19 = 37
MIPS_REG_DSPOUTFLAG20 = 38
MIPS_REG_DSPOUTFLAG21 = 39
MIPS_REG_DSPOUTFLAG22 = 40
MIPS_REG_DSPOUTFLAG23 = 41
MIPS_REG_DSPPOS = 42
MIPS_REG_DSPSCOUNT = 43
MIPS_REG_AC0 = 44
MIPS_REG_AC1 = 45
MIPS_REG_AC2 = 46
MIPS_REG_AC3 = 47
MIPS_REG_F0 = 48
MIPS_REG_F1 = 49
MIPS_REG_F2 = 50
MIPS_REG_F3 = 51
MIPS_REG_F4 = 52
MIPS_REG_F5 = 53
MIPS_REG_F6 = 54
MIPS_REG_F7 = 55
MIPS_REG_F8 = 56
MIPS_REG_F9 = 57
MIPS_REG_F10 = 58
MIPS_REG_F11 = 59
MIPS_REG_F12 = 60
MIPS_REG_F13 = 61
MIPS_REG_F14 = 62
MIPS_REG_F15 = 63
MIPS_REG_F16 = 64
MIPS_REG_F17 = 65
MIPS_REG_F18 = 66
MIPS_REG_F19 = 67
MIPS_REG_F20 = 68
MIPS_REG_F21 = 69
MIPS_REG_F22 = 70
MIPS_REG_F23 = 71
MIPS_REG_F24 = 72
MIPS_REG_F25 = 73
MIPS_REG_F26 = 74
MIPS_REG_F27 = 75
MIPS_REG_F28 = 76
MIPS_REG_F29 = 77
MIPS_REG_F30 = 78
MIPS_REG_F31 = 79
MIPS_REG_FCC0 = 80
MIPS_REG_FCC1 = 81
MIPS_REG_FCC2 = 82
MIPS_REG_FCC3 = 83
MIPS_REG_FCC4 = 84
MIPS_REG_FCC5 = 85
MIPS_REG_FCC6 = 86
MIPS_REG_FCC7 = 87
MIPS_REG_W0 = 88
MIPS_REG_W1 = 89
MIPS_REG_W2 = 90
MIPS_REG_W3 = 91
MIPS_REG_W4 = 92
MIPS_REG_W5 = 93
MIPS_REG_W6 = 94
MIPS_REG_W7 = 95
MIPS_REG_W8 = 96
MIPS_REG_W9 = 97
MIPS_REG_W10 = 98
MIPS_REG_W11 = 99
MIPS_REG_W12 = 100
MIPS_REG_W13 = 101
MIPS_REG_W14 = 102
MIPS_REG_W15 = 103
MIPS_REG_W16 = 104
MIPS_REG_W17 = 105
MIPS_REG_W18 = 106
MIPS_REG_W19 = 107
MIPS_REG_W20 = 108
MIPS_REG_W21 = 109
MIPS_REG_W22 = 110
MIPS_REG_W23 = 111
MIPS_REG_W24 = 112
MIPS_REG_W25 = 113
MIPS_REG_W26 = 114
MIPS_REG_W27 = 115
MIPS_REG_W28 = 116
MIPS_REG_W29 = 117
MIPS_REG_W30 = 118
MIPS_REG_W31 = 119
MIPS_REG_MAX = 120
MIPS_REG_ZERO = MIPS_REG_0
MIPS_REG_1 = 1
MIPS_REG_AT = MIPS_REG_1
MIPS_REG_2 = 2
MIPS_REG_V0 = MIPS_REG_2
MIPS_REG_3 = 3
MIPS_REG_V1 = MIPS_REG_3
MIPS_REG_4 = 4
MIPS_REG_A0 = MIPS_REG_4
MIPS_REG_5 = 5
MIPS_REG_A1 = MIPS_REG_5
MIPS_REG_6 = 6
MIPS_REG_A2 = MIPS_REG_6
MIPS_REG_7 = 7
MIPS_REG_A3 = MIPS_REG_7
MIPS_REG_8 = 8
MIPS_REG_T0 = MIPS_REG_8
MIPS_REG_9 = 9
MIPS_REG_T1 = MIPS_REG_9
MIPS_REG_10 = 10
MIPS_REG_T2 = MIPS_REG_10
MIPS_REG_11 = 11
MIPS_REG_T3 = MIPS_REG_11
MIPS_REG_12 = 12
MIPS_REG_T4 = MIPS_REG_12
MIPS_REG_13 = 13
MIPS_REG_T5 = MIPS_REG_13
MIPS_REG_14 = 14
MIPS_REG_T6 = MIPS_REG_14
MIPS_REG_15 = 15
MIPS_REG_T7 = MIPS_REG_15
MIPS_REG_16 = 16
MIPS_REG_S0 = MIPS_REG_16
MIPS_REG_17 = 17
MIPS_REG_S1 = MIPS_REG_17
MIPS_REG_18 = 18
MIPS_REG_S2 = MIPS_REG_18
MIPS_REG_19 = 19
MIPS_REG_S3 = MIPS_REG_19
MIPS_REG_20 = 20
MIPS_REG_S4 = MIPS_REG_20
MIPS_REG_21 = 21
MIPS_REG_S5 = MIPS_REG_21
MIPS_REG_22 = 22
MIPS_REG_S6 = MIPS_REG_22
MIPS_REG_23 = 23
MIPS_REG_S7 = MIPS_REG_23
MIPS_REG_24 = 24
MIPS_REG_T8 = MIPS_REG_24
MIPS_REG_25 = 25
MIPS_REG_T9 = MIPS_REG_25
MIPS_REG_26 = 26
MIPS_REG_K0 = MIPS_REG_26
MIPS_REG_27 = 27
MIPS_REG_K1 = MIPS_REG_27
MIPS_REG_28 = 28
MIPS_REG_GP = MIPS_REG_28
MIPS_REG_29 = 29
MIPS_REG_SP = MIPS_REG_29
MIPS_REG_30 = 30
MIPS_REG_FP = MIPS_REG_30
MIPS_REG_S8 = MIPS_REG_30
MIPS_REG_31 = 31
MIPS_REG_RA = MIPS_REG_31
MIPS_REG_DSPCCOND = 32
MIPS_REG_DSPCARRY = 33
MIPS_REG_DSPEFI = 34
MIPS_REG_DSPOUTFLAG = 35
MIPS_REG_DSPOUTFLAG16_19 = 36
MIPS_REG_DSPOUTFLAG20 = 37
MIPS_REG_DSPOUTFLAG21 = 38
MIPS_REG_DSPOUTFLAG22 = 39
MIPS_REG_DSPOUTFLAG23 = 40
MIPS_REG_DSPPOS = 41
MIPS_REG_DSPSCOUNT = 42
MIPS_REG_AC0 = 43
MIPS_REG_HI0 = MIPS_REG_AC0
MIPS_REG_AC1 = 44
MIPS_REG_HI1 = MIPS_REG_AC1
MIPS_REG_AC2 = 45
MIPS_REG_HI2 = MIPS_REG_AC2
MIPS_REG_AC3 = 46
MIPS_REG_HI3 = MIPS_REG_AC3
MIPS_REG_LO0 = MIPS_REG_HI0
MIPS_REG_LO1 = MIPS_REG_HI1
MIPS_REG_LO2 = MIPS_REG_HI2
MIPS_REG_LO3 = MIPS_REG_HI3
MIPS_REG_F0 = 47
MIPS_REG_F1 = 48
MIPS_REG_F2 = 49
MIPS_REG_F3 = 50
MIPS_REG_F4 = 51
MIPS_REG_F5 = 52
MIPS_REG_F6 = 53
MIPS_REG_F7 = 54
MIPS_REG_F8 = 55
MIPS_REG_F9 = 56
MIPS_REG_F10 = 57
MIPS_REG_F11 = 58
MIPS_REG_F12 = 59
MIPS_REG_F13 = 60
MIPS_REG_F14 = 61
MIPS_REG_F15 = 62
MIPS_REG_F16 = 63
MIPS_REG_F17 = 64
MIPS_REG_F18 = 65
MIPS_REG_F19 = 66
MIPS_REG_F20 = 67
MIPS_REG_F21 = 68
MIPS_REG_F22 = 69
MIPS_REG_F23 = 70
MIPS_REG_F24 = 71
MIPS_REG_F25 = 72
MIPS_REG_F26 = 73
MIPS_REG_F27 = 74
MIPS_REG_F28 = 75
MIPS_REG_F29 = 76
MIPS_REG_F30 = 77
MIPS_REG_F31 = 78
MIPS_REG_FCC0 = 79
MIPS_REG_FCC1 = 80
MIPS_REG_FCC2 = 81
MIPS_REG_FCC3 = 82
MIPS_REG_FCC4 = 83
MIPS_REG_FCC5 = 84
MIPS_REG_FCC6 = 85
MIPS_REG_FCC7 = 86
MIPS_REG_W0 = 87
MIPS_REG_W1 = 88
MIPS_REG_W2 = 89
MIPS_REG_W3 = 90
MIPS_REG_W4 = 91
MIPS_REG_W5 = 92
MIPS_REG_W6 = 93
MIPS_REG_W7 = 94
MIPS_REG_W8 = 95
MIPS_REG_W9 = 96
MIPS_REG_W10 = 97
MIPS_REG_W11 = 98
MIPS_REG_W12 = 99
MIPS_REG_W13 = 100
MIPS_REG_W14 = 101
MIPS_REG_W15 = 102
MIPS_REG_W16 = 103
MIPS_REG_W17 = 104
MIPS_REG_W18 = 105
MIPS_REG_W19 = 106
MIPS_REG_W20 = 107
MIPS_REG_W21 = 108
MIPS_REG_W22 = 109
MIPS_REG_W23 = 110
MIPS_REG_W24 = 111
MIPS_REG_W25 = 112
MIPS_REG_W26 = 113
MIPS_REG_W27 = 114
MIPS_REG_W28 = 115
MIPS_REG_W29 = 116
MIPS_REG_W30 = 117
MIPS_REG_W31 = 118
MIPS_REG_MAX = 119
MIPS_INS_INVALID = 0
MIPS_INS_ABSQ_S = 1

3
include/arm.h
View File

@ -207,8 +207,9 @@ typedef enum arm_reg {
ARM_REG_S30,
ARM_REG_S31,
ARM_REG_MAX,
ARM_REG_MAX, // <-- mark the end of the list or registers
// alias registers
ARM_REG_R13 = ARM_REG_SP,
ARM_REG_R14 = ARM_REG_LR,
ARM_REG_R15 = ARM_REG_PC,

3
include/arm64.h
View File

@ -332,7 +332,8 @@ typedef enum arm64_reg {
ARM64_REG_X28 = 225,
ARM64_REG_X29 = 226,
ARM64_REG_X30 = 227,
ARM64_REG_MAX = 228,
ARM64_REG_MAX = 228, // <-- mark the end of the list of registers
} arm64_reg;
// ARM64 instruction

123
include/mips.h
View File

@ -48,38 +48,38 @@ typedef struct cs_mips {
typedef enum mips_reg {
MIPS_REG_INVALID = 0,
// General purpose registers
MIPS_REG_0 = 1, MIPS_REG_ZERO = MIPS_REG_0,
MIPS_REG_1, MIPS_REG_AT = MIPS_REG_1,
MIPS_REG_2, MIPS_REG_V0 = MIPS_REG_2,
MIPS_REG_3, MIPS_REG_V1 = MIPS_REG_3,
MIPS_REG_4, MIPS_REG_A0 = MIPS_REG_4,
MIPS_REG_5, MIPS_REG_A1 = MIPS_REG_5,
MIPS_REG_6, MIPS_REG_A2 = MIPS_REG_6,
MIPS_REG_7, MIPS_REG_A3 = MIPS_REG_7,
MIPS_REG_8, MIPS_REG_T0 = MIPS_REG_8,
MIPS_REG_9, MIPS_REG_T1 = MIPS_REG_9,
MIPS_REG_10, MIPS_REG_T2 = MIPS_REG_10,
MIPS_REG_11, MIPS_REG_T3 = MIPS_REG_11,
MIPS_REG_12, MIPS_REG_T4 = MIPS_REG_12,
MIPS_REG_13, MIPS_REG_T5 = MIPS_REG_13,
MIPS_REG_14, MIPS_REG_T6 = MIPS_REG_14,
MIPS_REG_15, MIPS_REG_T7 = MIPS_REG_15,
MIPS_REG_16, MIPS_REG_S0 = MIPS_REG_16,
MIPS_REG_17, MIPS_REG_S1 = MIPS_REG_17,
MIPS_REG_18, MIPS_REG_S2 = MIPS_REG_18,
MIPS_REG_19, MIPS_REG_S3 = MIPS_REG_19,
MIPS_REG_20, MIPS_REG_S4 = MIPS_REG_20,
MIPS_REG_21, MIPS_REG_S5 = MIPS_REG_21,
MIPS_REG_22, MIPS_REG_S6 = MIPS_REG_22,
MIPS_REG_23, MIPS_REG_S7 = MIPS_REG_23,
MIPS_REG_24, MIPS_REG_T8 = MIPS_REG_24,
MIPS_REG_25, MIPS_REG_T9 = MIPS_REG_25,
MIPS_REG_26, MIPS_REG_K0 = MIPS_REG_26,
MIPS_REG_27, MIPS_REG_K1 = MIPS_REG_27,
MIPS_REG_28, MIPS_REG_GP = MIPS_REG_28,
MIPS_REG_29, MIPS_REG_SP = MIPS_REG_29,
MIPS_REG_30, MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30,
MIPS_REG_31, MIPS_REG_RA = MIPS_REG_31,
MIPS_REG_0,
MIPS_REG_1,
MIPS_REG_2,
MIPS_REG_3,
MIPS_REG_4,
MIPS_REG_5,
MIPS_REG_6,
MIPS_REG_7,
MIPS_REG_8,
MIPS_REG_9,
MIPS_REG_10,
MIPS_REG_11,
MIPS_REG_12,
MIPS_REG_13,
MIPS_REG_14,
MIPS_REG_15,
MIPS_REG_16,
MIPS_REG_17,
MIPS_REG_18,
MIPS_REG_19,
MIPS_REG_20,
MIPS_REG_21,
MIPS_REG_22,
MIPS_REG_23,
MIPS_REG_24,
MIPS_REG_25,
MIPS_REG_26,
MIPS_REG_27,
MIPS_REG_28,
MIPS_REG_29,
MIPS_REG_30,
MIPS_REG_31,
// DSP registers
MIPS_REG_DSPCCOND,
@ -95,15 +95,10 @@ typedef enum mips_reg {
MIPS_REG_DSPSCOUNT,
// ACC registers
MIPS_REG_AC0, MIPS_REG_HI0 = MIPS_REG_AC0,
MIPS_REG_AC1, MIPS_REG_HI1 = MIPS_REG_AC1,
MIPS_REG_AC2, MIPS_REG_HI2 = MIPS_REG_AC2,
MIPS_REG_AC3, MIPS_REG_HI3 = MIPS_REG_AC3,
MIPS_REG_LO0 = MIPS_REG_HI0,
MIPS_REG_LO1 = MIPS_REG_HI1,
MIPS_REG_LO2 = MIPS_REG_HI2,
MIPS_REG_LO3 = MIPS_REG_HI3,
MIPS_REG_AC0,
MIPS_REG_AC1,
MIPS_REG_AC2,
MIPS_REG_AC3,
// FPU registers
MIPS_REG_F0,
@ -182,7 +177,51 @@ typedef enum mips_reg {
MIPS_REG_W30,
MIPS_REG_W31,
MIPS_REG_MAX,
MIPS_REG_MAX, // <-- mark the end of the list or registers
// alias registers
MIPS_REG_ZERO = MIPS_REG_0,
MIPS_REG_AT = MIPS_REG_1,
MIPS_REG_V0 = MIPS_REG_2,
MIPS_REG_V1 = MIPS_REG_3,
MIPS_REG_A0 = MIPS_REG_4,
MIPS_REG_A1 = MIPS_REG_5,
MIPS_REG_A2 = MIPS_REG_6,
MIPS_REG_A3 = MIPS_REG_7,
MIPS_REG_T0 = MIPS_REG_8,
MIPS_REG_T1 = MIPS_REG_9,
MIPS_REG_T2 = MIPS_REG_10,
MIPS_REG_T3 = MIPS_REG_11,
MIPS_REG_T4 = MIPS_REG_12,
MIPS_REG_T5 = MIPS_REG_13,
MIPS_REG_T6 = MIPS_REG_14,
MIPS_REG_T7 = MIPS_REG_15,
MIPS_REG_S0 = MIPS_REG_16,
MIPS_REG_S1 = MIPS_REG_17,
MIPS_REG_S2 = MIPS_REG_18,
MIPS_REG_S3 = MIPS_REG_19,
MIPS_REG_S4 = MIPS_REG_20,
MIPS_REG_S5 = MIPS_REG_21,
MIPS_REG_S6 = MIPS_REG_22,
MIPS_REG_S7 = MIPS_REG_23,
MIPS_REG_T8 = MIPS_REG_24,
MIPS_REG_T9 = MIPS_REG_25,
MIPS_REG_K0 = MIPS_REG_26,
MIPS_REG_K1 = MIPS_REG_27,
MIPS_REG_GP = MIPS_REG_28,
MIPS_REG_SP = MIPS_REG_29,
MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30,
MIPS_REG_RA = MIPS_REG_31,
MIPS_REG_HI0 = MIPS_REG_AC0,
MIPS_REG_HI1 = MIPS_REG_AC1,
MIPS_REG_HI2 = MIPS_REG_AC2,
MIPS_REG_HI3 = MIPS_REG_AC3,
MIPS_REG_LO0 = MIPS_REG_HI0,
MIPS_REG_LO1 = MIPS_REG_HI1,
MIPS_REG_LO2 = MIPS_REG_HI2,
MIPS_REG_LO3 = MIPS_REG_HI3,
} mips_reg;
// MIPS instruction

3
include/x86.h
View File

@ -62,7 +62,8 @@ typedef enum x86_reg {
X86_REG_R9D, X86_REG_R10D, X86_REG_R11D, X86_REG_R12D, X86_REG_R13D,
X86_REG_R14D, X86_REG_R15D, X86_REG_R8W, X86_REG_R9W, X86_REG_R10W,
X86_REG_R11W, X86_REG_R12W, X86_REG_R13W, X86_REG_R14W, X86_REG_R15W,
X86_REG_MAX
X86_REG_MAX // <-- mark the end of the list of registers
} x86_reg;
// Operand type for instruction's operands